Improved performance in ZnO/CdS/CuGaSe2 thin‐film solar cells

We report the growth and characterization of improved efficiency wide‐bandgap ZnO/CdS/CuGaSe2 thin‐film solar cells. The CuGaSe2 absorber thickness was intentionally decreased to better match depletion widths indicated by drive‐level capacitance profiling data. A total‐area efficiency of 9·5% was achieved with a fill factor of 70·8% and a Voc of 910 mV. Published in 2003 by John Wiley & Sons, Ltd.


INTRODUCTION
R ecently, improved efficiencies for CdS/CuIn 1 À x Ga x Se 2 solar cells have been reported for x $ 0Á3 (E gap $ 1Á1 eV) composition 1 and for x ¼ 0 (E gap $ 0Á95 eV) composition. 2 These successes have capitalized on insights about growth-related defects in the CuIn 1Àx Ga x Se 2 material system during a threestage elemental evaporation process. 3 Despite these successes, higher-bandgap (E gap 51Á5 eV) absorber materials for solar cells are desirable because of their higher open-circuit voltage, and lower currents for better module performance and current matching in a two-terminal tandem. However, attempts to increase the bandgap (i.e., increase x) in the CuIn 1 À x Ga x Se 2 material system have led to lower-than-expected open-circuit voltages and lower efficiencies. 4 One of the greatest challenges for a thin-film tandem device is raising the efficiency of the wide-bandgap top solar cell from the current $9% 5,6 to the $16% range. The CuIn 1Àx Ga x Se 2 material system is one of the leading candidates for a top-cell absorber because of its ideal bandgap 7 at x ¼ 1 ($1Á7 eV) and the knowledge base and success of the material at x $ 0Á3 as a solar cell absorber.
In this short communication, we report improved performance for a wide-bandgap polycrystalline CdS/ CuGaSe 2 (CGS) solar cell with V oc ¼ 0Á910 V, FF ¼ 70Á8% and a total area efficiency of 9Á5%. The highest efficiency reported for a polycrystalline device is 8Á7% (total area) with V oc ¼ 0Á870 V and FF ¼ 67Á3%, and 9Á7% active area efficiency for a single crystal device with a V oc ¼ 0Á946 V and FF ¼ 66Á5%. The recent improvements, we believe, are due, in part, to a better matching of the thickness of the absorber material to the electronic depletion width as measured by drive-level capacitance profiling.

EXPERIMENTAL DETAILS
CGS absorbers were grown by elemental evaporation of Cu, Ga, and Se following the three-stage process. 3 A pressure-contact thermocouple (T s ), located on the back of the substrate, detected the substrate temperature changes throughout the deposition. Ga was deposited at 4Á0 Å /s during the first stage at $450 C (T s ) and at $ 600 C (T s ) during the third stage. Cu was deposited at 3Á0 Å /s during the second stage at $ 600 C (T s ). Se flux was constant at 30 Å /s during all three stages. T s decreased by about 2 C as the films became Cu-rich at the end of the second stage, and then increased by 2 C during the third stage as Ga was added back to the film. This temperature response is due to an emissivity difference between Cu-rich and Cu-poor CGS films. 8 The temperature detected by the T s thermocouple is known to be about 30-50 C lower than the growth surface temperature of the substrate. Films were grown on sputter-deposited Mo-coated soda-lime glass. Junctions were formed by the deposition of a layer of CdS by chemical-bath deposition at 65 C. 1 A bilayer of sputter-deposited ZnO formed a buffer and lateral conduction film topped by a contacting grid of Ni/Al ( $5% optical obscuration). A MgF 2 anti-reflection coating was deposited over the grid. Details of each layer have been reported previously. 1 Individual cells were isolated by mechanical scribing to $ 0Á43 cm 2 and tested under an AM1Á5 global spectrum for 1000 W/m 2 irradiance.
Drive-level capacitance profiles 9 (DLCP) of the completed cells were measured at À0Á5-0Á2 V bias at 10-100 kHz. A dielectric constant of 11Á5 was used for all devices and measurements were made at room temperature. Figure 1 shows DLCP (defect density as a function of depletion width) data for three CdS/CuIn 1 À x Ga x Se 2 cells grown by the three-stage process. Sample CIGS S2038 is a typical x $ 0Á3 cell, while sample CGS S1820 is an x ¼ 1 sample grown to the same thickness as sample S2038. Both samples are Cu-poor. Figure 1 reveals the striking differences between the samples in two key areas: (1) the CGS sample has a higher defect density and a less uniform defect density profile then the CIGS sample; and (2) the depletion width for the CGS sample is much smaller than the CIGS sample. These data indicate that the drift collection length for photo-generated carriers may be much smaller in CGS than in CIGS samples. Figure 2 showing quantum efficiency data for a CGS and a CIGS solar cell support this conclusion, due to the poor collection efficiency above 550 nm in the CGS cell.

RESULTS
Based on the data of Figure 1 sample CGS S2087 in Figure 1 was intentionally grown about half as thick (thickness $1Á75 mm, see Figure 4) as sample CGS S1820 (thickness $2Á9 mm) to make a better match of the physical thickness of the absorber layer to the electronic depletion width in the absorber layer. The thickness of the absorber material is adjusted by varying the time of the first stage growth in the three-stage process. The data of Figure 1 show two important differences between samples S1820 and S2087. First, the defect density level on the thinner sample is lower than in the thicker sample. Second, the defect profile is much more uniform throughout the film and does not increase near the back of the cell. Unfortunately the DLCP data could not be extended deeper into the sample with additional reverse bias. Further DLCP studies are underway. Figure 3 shows the NREL-confirmed current density-voltage (J-V) characteristics for our best CdS/CGS solar cell, S2087. The cell parameters for this cell and for other cells from the same deposition are given in Table I. The 9Á53% efficiency is an improvement from the previous 8Á7% total-area efficiency for a polycrystalline device. 6 It is also comparable to the best single crystal CGS device to date of 9Á7% active area efficiency. 5 The main improvements for the polycrystalline devices are in the fill factor (FF), 70Á8% (67Á3%), 6 and in the open-circuit voltage (V oc ), 0Á91 V (0Á87 V). 6 The series and shunt resistances (Table I) were improved over our previously best CGS cell (device S1820 of Figure 1 R s $1Á7 cm 2 , R sh $ 903 cm 2 ), which contributed to the improved fill factor and voltage. The J 0 value of 7 Â 10 À7 mA/cm 2 , calculated from the dark J-V data for a one-diode model, is smaller than previous reports 10 and helps explain the slight improvement in V oc . V oc at T ¼ 0 K was extrapolated from J-V(T) data (T>200 K) to be $1Á6 eV. V oc data below 200 K do not follow the extrapolated line back to 1Á6 eV at 0 K, but rather, fall away from the line toward lower V oc values as seen in other CdS/CGS devices. 10 The ideality factor A, calculated from the dark J-V data for a one-diode model, at room temperature is 2Á1 and has only a slight temperature dependence, revealing a characteristic tunneling energy of E oo / $ 30 meV. 10 The small tunneling energy (compare with Kohara et al. 8 ) is consistent with the low J 0 of the device and the low Figure 2. Absolute, external quantum efficiencies for CdS/CGS (cell S2087) and CdS/CIGS devices carrier concentration (with respect to CIGS) in the absorber material ($2 Â 10 15 cm À3 ) as determined from high-frequency (100 kHz) DLCP. 9 Table I also shows the electrical characteristics of an unofficial measurement of a device with V oc $ 0Á97 V. This improved V oc was seen in several thinned devices after a 2-min, 200 C anneal in air, as observed by others. 6,10 However, our best devices (as determined by FF and efficiency) were not improved by a 2-min, 200 C air anneal. These encouraging results show that higher open-circuit voltages are possible in CdS/CGS devices and that the thickness of the absorber layer may be a relevant variable for achieving these higher voltages.
The external quantum efficiency (QE) of our best cell is shown in Figure 2. The roll-off of current below 550 nm is due to absorption in the CdS. The poor red response above 550 nm is typical for CdS/CGS cells, but not so in CdS/CuIn 0Á7 Ga 0Á3 Se 2 cells, where the QE response is higher and flatter over the same region. However, both cells do suffer poor collection near their respective band edges. Contreras et al. 11 have shown that higher absorber deposition temperatures and, along with others, 6 higher CdS CBD temperatures produce an improved QE response in CdS/CGS solar cells above 550 nm. Experiments are ongoing to utilize this information in our thinner absorbers.   Figure 4(a) shows a cross-sectional scanning electron microscopy (SEM) image of absorber layer S2087. Large, columnar grains extend almost completely from the Mo back-contact to the surface. In addition, the image reveals excellent nucleation of the CGS on the Mo substrate. The grains appear relatively free of extended defects, as evidenced from transmission electron microscopy examinations (not shown). The plan view SEM image (Figure 4b) shows dense, large, faceted grains at the surface, typical for high-quality CIGS absorber material. An X-ray diffraction scan showed the film to be phase pure and highly (220) oriented, with an orientation factor of (220/112) ¼ 11Á4.
Auger depth profiles of the absorber material are shown in Figure 5. The inset graph was obtained with a low sputter rate to capture the variation of the Cu/Ga ratio near the surface. The surface is clearly Cu-poor. Figure 5 shows the complete Auger depth profile from the surface to the Mo, revealing a uniform distribution of the Ga throughout the film. Low-energy (10 keV) electron probe micro-analysis (EPMA) gave a ratio of Cu to Ga of $0Á91.

DISCUSSION
The main modification to our standard growth technique that produced the improved CdS/CGS solar cell was to reduce the thickness of the CGS absorber by decreasing the time of the first stage of the three-stage process. This modification was inspired by the DLCP data that indicated a much smaller depletion width in the CGS cells compared with the CIGS cells. Because CGS has relatively poor transport properties 10 (mobilities less than 10 cm 2 V À1 s À1 ), a drift-collection device design should be better than one relying on diffusion for the collection of carriers. The carrier concentration in CIGS (x ¼ 0Á3) is a good match to the carrier concentration of our CdS, such that devices have a large depletion width and hence good collection throughout the spectrum. The carrier concentration in typical CGS, on the other hand, is higher than our CIGS (x ¼ 0Á3) and thus has a smaller depletion width. We are currently working to control the carrier concentration in the window layer and in the CGS to optimize the depletion region.
Decreasing the thickness of the CGS absorber layer had a beneficial consequence for our thermocouple feedback system as well. We have found that growing CGS with a typical three-stage deposition profile designed for optimum CuIn 0Á7 Ga 0Á3 Se 2 absorbers gives a typical characteristic temperature decrease (see experimental details) at the end of the second stage, but that the films are usually Cu-rich and make poor solar cells. Redesigning the three-stage deposition profile for thin CGS absorbers gave us a temperature signal that allowed us to finish off the films Ga-rich and thus make improved solar cells. The slower diffusion rate of Ga compared with In is the main reason for this difference in three-stage recipes. Thus, as indicated by the data, simply decreasing the absorber thickness in CGS cells gave better stoichiometric feedback control during the growth process, good grain growth and crystalline quality CGS and improved electronic properties in a complete CdS/CGS solar cell.