Vlsi Implementation of Area Efficient 2-Parallel Fir Digital Filter

This paper aims to implement an area efficient 2-parallel FIR digital filter. Xilinx 14.2 is used for synthesis and simulation. Parallel filters are designed by using VHDL. Comparison among primary 2–parallel FIR digital filter and area efficient 2-parallel FIR digital filter has been done. Since adders are less weight in term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter. 2-parallel FIR filter is used in digital signal processing (DSP) application.


INTRODUCTION
A finite impulse response (FIR) digital filter has no feedback and is used in DSP application, which starts ranging from wireless mobile communications to video and image processing [2]. However, an area efficient 2-parallel FIR filter uses booth multiplier, carry look-ahead adder, and a carry-look-ahead subtractor for the design of the filter. Booth multiplier only multiplies in two signed binary numbers in two's complement and had high performance, consume low power and it does not have weak regularity. Let's take for an 8-bit binary number, in which the number may be either positive or negative and will be shown in two's complement format, i.e. the value is from -128 to +127 [4]. Traditional hardware multiplication is presented similarly as multiplication is done by hand: a. Partial products are computed, b. shifted appropriately, and c. Summed.
This booth algorithm can be increased if we reduced the number of the partial product (i.e. fewer bits) because output will wait only for few sum to perform [7]. Figure.  Carry look-ahead adder is used in a digital logic circuit. The advantage of using carry lookahead adder is that it speeds up the bits and reduces area, and also it reduces the time required to examine the carry bits [3].Since adders are less weight in term of silicon area, compare to multipliers. Therefore multipliers are replaced with adders for reducing area and speed of the filter [5]. The carry look ahead subtractor is a fast subtractor which is designed to reduce the delay. If utilize the fact that, at each point of the bit position, whether it should carry with a generated at that bit or it can carry with a propagated at that bit.
In this paper, we are implementing the area-efficient 2-paralel FIR digital filter using VHDL. Integrated circuit (IC) which is designed in VLSI has become a drawback regarding area and speed. Our project is about improving the drawback which makes the area less that is storage resource of memory becomes small, and the speed of the operator becomes faster [6].

PARALLEL PROCESSING
Parallel processing and pipelining system are similar with one another. Independent sets of computations are computed and inserted in a pipelined technique, whereas a duplicate hardware computation is calculated and added in parallel processing [1].

Parallel processing FIR filters for High Speed or Low power
Consider a 2-parallel FIR digital filter shown in figure.3 [1]. The 2-parallel FIR filter has exactly two copies of the primary 4-tap FIR filter. The dashed line in fig.3 indicates the critical path.16bit Binary adder and the 16 bit binary multiplier are used for 2-parallel FIR filter designing. We consider the input x(2k) and x(2k+1) as even and odd respectively. Here h0,h1,h2,h3 indicates the filter coefficient of 2-parallel filter. D means delay. Delay of one clock cycle, which means the value, has to be stored for one clock cycle. Similarly, consider the area efficient 2-parallel FIR filter in figure.4 [1]. The area efficient 2parallel filter shown in figure.4 is more efficient in term of area and speed when compared with a basic 2-parallel FIR filter shown in figure.3. In figure.4, we consider the input x (2k) and x (2k+1) as even and odd respectively. D indicates the delay. Delay of one clock cycle, which means the value has to be stored for one clock cycle. The dashed line shows the critical line. h0, h1, h2, h3 are the filter coefficients. The system equation for the given area efficient 2-parallel FIR filter is as follows: y(n) = h 0 (n) + h 1 x(n-1) + h 2 x(n-2) + h 3 x(n-3) Defining the outputs at node A, B and C as yA, yB and yC respectively from fig.5, we have y A = h 0 x(2k) + h 2 x(2k-2) y B = (h 0 +h 1 ) (x(2k) + x(2k + 1)) + (h 2 +h 3 ) (x(2k-2) + x(2k-1)) y c = h 1 x(2k+1) + h 3 x(2k-1) Then y(2k) = y A + [y C after 1 block delay] = h 0 x(2k) + h 1 x(2k-1) + h 2 x(2k-2) + h 3 x(2k-3) y(2k+1) = y B -y A -y C

CONCLUSIONS
In this paper, area-efficient 2-parallel FIR filter is designed and compared with a primary 2parallel filter. Area and speed of area-efficient 2-parallel filter are improved. Carry-look-ahead adder and subtractor are used in an area-efficient 2-parallel filter. For multiplication, booth multiplier is used in an area-efficient 2-parallel filter. All the simulated waveforms are discussed.