Towards Temperature Insensitive Nanoscale CMOS Circuits with Adaptively Regulated Voltage Power Supplies

In this paper, we show that the temperature-induced performance drop seen in nanoscale CMOS circuitscan be tackled by powering the circuits with adaptively regulated voltage power supplies. Essentially, when temperature rises, the supply voltage will be bumped up to offset otherwise performance degradation. To avoid thermal over-drift as chip temperature exceeds its operation range, a voltage limiteris integrated into the proposed power supply to cap the supply voltage. Using this proposed adaptive voltage source to power individual CMOS logic gates and/or subsystems will free the chips from using expensive high-precision temperature sensors for thermal management and performance tuning. Experiments on various benchmark circuits, which are implemented with a 45nm CMOS technology, have confirmed that the circuit delay variation can be reduced to 15%~30% over a wide temperature range (0℃ to 90℃), a sharp contrast to the large delay variations (50%~75%)observed in most IC designs where a constant power supply is employed.


INTRODUCTION
Variations in power supply voltages ( ) and temperatures (T) have strong implications on the delay of a CMOS circuit, and even may cause the chip to fail.In general, as chip temperature rises, two effects are observed: (i) the descending mobility of the transistor carriers, which contributes to the increase of the circuit propagation delay, and (ii) the decreasing of the absolute value of the threshold voltage ( )of a transistor, which leads to a better delay performance.Experiments show that when both thermal effects come into play, the delay of a circuit operating at 90 o Ccould be twice of that at 0 o C.Moreover, such sheer thermal-induced delay performance penalty can vary significantly from one chip area to another [1], due to the imbalanced utilization and diversity of circuitry at different sections.As a result, ensuring the performance resilience against a wide range of temperature variations has become one of the greatest challenges facing nano scale VLSI circuit designs [2], One most effective way to combat this temperature-induced delays is by changing the of the circuits.Along this line, two different approach shave been considered in the literature.The first approach is based on the fact that if is pulled up, it can offset the circuit delay introduced by International Journal of VLSI design & Communicat the rise of temperature.Such approach require (LUT) [4], to alter the according to the readings from the chip.By doing so, delay variations 20% as the chip(0.25 technologies) work in [6] harnessed PVT sensors each region had its own that could designs [4]- [6] is that they require high precision temperature sensors and abundant power control circuits, which are not easy to com Another approach to deal with the circuit at the zero-temperature-coefficient (ZTC) voltage thermal effects on the carrier mobility and MOSFET threshold are approximately and thus, performance variations range, from 25℃ to 125℃in [2].Unfortunately, this ZTC voltage is usually close to the threshold voltage of MOSFETs, which can be problematic to approach is more suitable for low power In what follows, we will examine the temperature in Section 2, through theoretical analysis and use of an adaptive power supply temperature (CTAT) current source shown in to a first order approximation, can be used to subsystems.In addition, a voltage output voltage after the temperature logic circuits experience much smaller (Section 4), but no high-precision temperature sensors drawn in Section 5.

DELAY OF BASIC CMOS VOLTAGE
Principally, all primitive CMOS same delay performance.Without loss of generality, inverter (Figure 1),related to the time spent on charging or discharging its capacitive load can be expressed as: approach requires the use of a power manager, with a look according to the readings from the embedded temperature sensors , delay variations of primary Boolean logic gates could be confined technologies) temperature varies from 0℃ to 90℃ [5].Furthermore, t PVT sensors in multiple voltage and frequency domains of the chip could be adjusted individually.One big downside require high precision temperature sensors and abundant power control to come by.approach to deal with the temperature-induced delay variations is through powering coefficient (ZTC) voltage level [2][7].Essentially, by doing so, carrier mobility and MOSFET threshold are approximately canceled out variations of the logic circuits could be negligible over a wide .Unfortunately, this ZTC voltage is usually close to the threshold can be problematic to high speed circuit designs.low power, but less performance-critical applications.
In what follows, we will examine the temperature-delay relationship of basic CMOS logic gates through theoretical analysis and circuit simulations.Such relationship as detailed in Section 3.In light of a complementary to absolute temperature (CTAT) current source shown in [8][9], the proposed adaptive power supply source, rder approximation, can be used to build temperature-insensitive logic circuits and In addition, a voltage limiter is integrated into the proposed power source after the temperature rises above a certain point.With this adaptive power supply logic circuits experience much smaller circuit delay variations over a wide temperature range precision temperature sensors are required.Finally, the co

MOS LOGIC GATES VS. TEMPERATURE AND
logic gates can be conceptually collapsed to inverters with the ithout loss of generality, the propagation delay model the time spent on charging or discharging its capacitive load Gate delay model of an inverter with a capacitive load.
June 2017 2 manager, with a look-up table embedded temperature sensors [3] in confined within Furthermore, the of the chip, and downside of all these require high precision temperature sensors and abundant power control through powering the by doing so, the canceled out, over a wide temperature .Unfortunately, this ZTC voltage is usually close to the threshold .Rather, this basic CMOS logic gates .Such relationship suggests the a complementary to absolute the proposed adaptive power supply source, insensitive logic circuits and power source to limit the this adaptive power supply, over a wide temperature range Finally, the conclusion is ND collapsed to inverters with the model of a CMOS the time spent on charging or discharging its capacitive load [10], Electronic copy available at: https://ssrn.com/abstract=3389126 where is the amount of charge to drive the capacitive load to logic 1/0 (i.e./ ); is the charging/discharging current through the transistor; is the load capacitance; W and L are the channel width and length of the transistor, respectively; ( ) is the carrier mobility, roughly proportional to [10]; ( ) decreases with the growth of T in a nearly linear fashion [10][11]; and is the unit gate capacitance of the MOSFET.
If the input is considered as a step signal, a simplified approximation of Eq. ( 1) can be given as: Where $ is a coefficient introduced to simplify Eq.( 1).Therefore, once the process and design parameters (e.g.W, L, ) are fixed, we can only regulate as a function of T to offset the thermal effect on the propagation delay.Given that ( ) ∝ , and ( ) varies negligibly in a range of 0℃ to 90℃ [10], we can treat ( ) as a constant, , and obtain the derivative of the delay described in Eq. ( 2) with respect to temperature, given as Eq.( 3), where A is a positive, process-related, temperature-independent coefficient.
Eq. ( 3) suggests that,in principle, proper adjustment of (e.g ∝ T 5 , 7 > 0 )can make) ) ⁄ equal to 0, i.e., the temperature-induced delay can be eliminated.This effect is examined through simulations of a CMOS inverter implemented with a 45nm CMOS technology.Since the supply voltage of the 45nm technology is usually in range of 0.8V to 1.0V, we run simulations with a supply voltage range from 0.3V (slightly higher than ) to 1.2V.The delays versus temperatures at different levels are plotted in Figure 2, and the delay change rates with respect to temperatures at different levels are also reported in Table 1.The results reveal that when is set to be low (around 0.3V in Figure 2), the circuit delay at 0℃ is as high as 800 ps, and it drops as the temperature increases.As is set to be slightly higher, reaching the ZTC voltage [2][7], about 0.32V in our experiments, the circuit delay is approximately insensitive to the temperature changes.Once continues to rise to an even higher level (e.g.1.0V, as is usually employed in high-speed circuits), the delay drops significantly (6.1ps at 0℃), but it rises rapidly as temperature increases (the delay actually is more than doubled at 90℃, compared to that at 0℃).
By studying the delays at different temperatures and levels in Figure 2, one can see that, if is set to be around 0.7V at 0℃, 0.8V at 30℃, 1.0V at 60℃, 1.2V at 90℃, respectively, (i.e., a net change of 0.5V for when the temperature rises from 0℃ to 90℃), the inverter's delay is almost independentof the temperature variations (about 10ps across the temperature range as shown in the red dashed line in Figure 2).Similarly, if we relax the performance requirement of the circuit, we can set properly so that the inverter delay is nearly unchanged from 0℃ to 90℃ at about 15ps (the green dotted line in Figure 2), while merely changes in a range from 0.6V to 0.8V.Agreeing to Eq. ( 3), these observations indicate that by using a temperature-adaptive Electronic copy available at: https://ssrn.com/abstract=3389126 International Journal of VLSI design & Communicat voltage power supply source, which is detailed in the next section, delay variations can be well controlled.
Figure 2 Inverter delay (ps) against temperature under different V Table 1 Change rates of delay (ps) vs. temperature under various V

SELF-ADAPTIVE, TEMPERATURE CIRCUIT
To offset the performance penalty introduced section, needs to be slightly increased temperature in the CTAT [8] is the regulated temperature-adaptive voltage source that actually powers the digital logic circuits)is proposed.Compared to the designs in [4]- [6], no high-precision temperature sensors or redundant power supply managers are required.In addition, the voltage limiter restrains within a certain predefined range; that is, when the temperature exceeds certain level, will stop climbing, preventing the circuit from overheating due to the overrun of .In order to optimize the voltages at each node for a large dynamic swing over the entire temperature range of interest, we first study the equivalent impedance of a PMOS/NMOS, with its drain connecting to its gate (i.e.:; = <; ), as given by Eq.( 4).
Where <; is the current from the drain to the source through the MOS channel and A is a constant coefficient that only relates to the manufacture process.Eq. ( 4) indicates that the equivalent impedance of the PMOS/NMOS increasesroughly proportional to .Based on this observation, resistors, which have a relatively low (linear) temperature sensitivity [10], can be employed to replace some PMOS transistors where :; = <; .That is, impedances Z1, Z4, Z5 and Z6 in Figure 3 could be implemented as either resistors or PMOS/NMOS (Figure 3).By doing so, we can expect to be truly adaptive to the temperature change.It shall be noticed that the resistance values and the size of each transistor need to be carefully chosen to match the impedance of the logic circuits or subsystems powered by , so that the value at a high temperature, say 90℃, could drive the logic circuit with approximately the same delay as that of value at a low temperature, say 0℃.In addition, the output impedance induced by Z7 and MN6 should be small (i.e.relatively large width of MN6), so that this CTAT-like voltage power supply could drive a complicated logic circuit and/or a subsystem.
On the other hand, since the output voltage of this CTAT-like power supply is designed to rise as the temperature climbs, this increasing voltage output may exacerbate the circuit power consumption.To prevent this problem from happening, an impedance (Z8) and a diode (D1)are added to function as a voltage limiter(Figure 3).This voltage limiter has little effect when is low, but once exceeds a certain voltage that turns D1 on, will be capped.This voltage limiter helps protect the circuit from overheating, at a cost of performance degradation only at extremely high temperature (e.g.120℃or higher).
In this paper, we provide an area-efficient (not necessarily delay optimized) CTAT-like voltage supply (Figure 4).In this case, Z1, Z4, Z5 and Z6 in Figure 3 are still implemented using PMOS transistors, yet all the widths of the PMOS and NMOS devices are set fixed, except for the width of MN6 and the resistance of R7(i.e.Z7 in Figure 3) that require manual adjustment during circuit design/layout process to match the impedances of different logic circuits powered by .Meanwhile, two NMOS are cascaded as the voltage limiter by connecting the body of NMOS to and its drain (together with the source and the gate) to the ground.As a result, each NMOS device is forward-biased, from the P-type body to the N-type drain/source, working as a diode to set a limit on the output voltage .
In the circuit shown in Figure 4, only MP3 operates in the saturation mode, while MP7,MP8, MN2 and MN4 are all in the linear mode.Since the impedance of PMOS changes more rapidly Electronic copy available at: https://ssrn.com/abstract=3389126 than that of NMOS [10], voltages at nodes 2, 5, 6 and 7 will decrease with the increase of temperature, and thus, the current through MN6 will actually decrease, leading to an increased output voltage, .In addition, transistor pairs (MN1, MN2), (MN3, MN4) and (MN5, MN6) can help magnify the output voltage changes with respect to the temperature In a simple term, with the proposed CTAT temperature increases, so that the delay can be held to a relatively constant level.This voltage saturates as temperature reaches a preset level determined by the voltage

SIMULATION RESULTS
To verify the performance advancement over a wide temperature range, we that are implemented using a 45nm one of the three different supplies like temperature-adaptive power supply thereafter), and 3) the proposed CTAT limiter (Figure 4, denoted as CTAT_vr of these benchmarks operating in to 180℃.In a simple term, with the proposed CTAT-like power supply, higher can be achieved as temperature increases, so that the delay can be held to a relatively constant level.This voltage saturates as temperature reaches a preset level determined by the voltage limiter.

ESULTS advancement of the proposed technique in terms of delay variation
, we run HSPICE simulations on a number of benchmark circuits a 45nm CMOS technology.Each benchmark circuit is powered by different supplies (Figure 5): 1) a 1.0V constant power, 2) the proposed CTAT adaptive power supply without voltage limiter (Figure 3, denoted as CTAT 3) the proposed CTAT-like temperature-adaptive power supply with voltage , denoted as CTAT_vr).We then measure the propagation delays and variations operating in all scenarios, respectively, with a temperature swing from June 2017 6 , voltages at nodes 2, 5, 6 and 7 will decrease with the increase of temperature, and thus, the current through MN6 will actually decrease, leading to an increased .In addition, transistor pairs (MN1, MN2), (MN3, MN4) and (MN5, MN6) variations.
like voltage power supply (left) and thevoltage limiter (right) can be achieved as temperature increases, so that the delay can be held to a relatively constant level.This voltage the proposed technique in terms of delay variations on a number of benchmark circuits Each benchmark circuit is powered by : 1) a 1.0V constant power, 2) the proposed CTAT-, denoted as CTAT-like adaptive power supply with voltage and variations with a temperature swing from 0℃ Electronic copy available at: https://ssrn.com/abstract=3389126We size the CTAT-like power supply circuits in the way that the delays of a benchmark circuit with the proposed CTAT-like power supply (0℃ to90℃)match the delay of the same circuit when powered with a constant 1.0V at 30℃ (the baseline implementation).
We set in Figure 3 and Figure 4 to be 2V, and the widths of the PMOS/NMOS transistors adopted in this power supply are listed in Table 2.The width of MN6 can beset somewhere between 360nm and 2160nm, while the resistance of R7 is in the range of 500Ω or 2kΩdepending on the type of logic circuit that is applied to (e.g.R7 can be about 600 Ω and MN6 at 2160nm for all the benchmark circuits used in the following simulations, including inverters, FAs, DFFs and ISCAS-85 benchmarks).By doing so, in Figure 3 could fall into the range of about 0.9V to 1.5V, while in Figure 4 are limited up to 1.4V, so that the logic circuit it powers could maintain a relatively uniform delay performance across the temperature range of0℃to 90℃.With a total of 14 PMOS/NMOS transistors and a resistor, this circuit occupies an area of about 0.2mm 2 in a 45nm technology.
We first run simulations and measure the propagation delays on simple logic circuits, such as a single-stage inverter, a three-stage cascaded inverter, one-bit full adder (FA) and a 4-bit ripple carry adder (RCA), powered by the three voltage supplies, respectively.The simulation results are shown in Figure 6 and Figure 7.One can see that, when these simple circuits are powered by a constant 1.0V power supply, delay variations exceed 60% when temperature goes from 0℃ to 90℃ (Figure 6), while if they are powered by the proposed CTAT-like voltage supply, delay variations are down to be about 15%~30%.On average, the proposed CTAT-like power supply can suppress the temperature-induced delay variation by 40%and more.Note that the proposed power supplies with and without a voltage limiter deliver almost indistinguishable performance for temperature up to90℃.However, the circuit performances with the voltage limiter degrade quickly once exceeding120℃, due to the blocking on 's growth, yet still outperform the ones powered by constant 1V.
We also run experiments over more complex circuits and subsystems, including a d-type flip-flop (D-FF) and three ISCAS-85 benchmarks (Figure 7), including C6288, which is a 16-by-16 binary multiplier, C499, a 32-bit Single-Error-Correcting (SEC) circuit, and C432, a 27-channel interrupt controller; all of these benchmark circuits are also powered by the three voltage supply Electronic copy available at: https://ssrn.com/abstract=3389126scenarios, respectively.The results shown in Figure 6 and Figure 7 demonstrate that, of all the four circuits, if they are powered by the proposed CTAT-like voltage power, the thermal-related delay variations range from about 15% to30%, whereas the delays of circuits powered by the uniform power supply of 1.0V vary between 50% and 70%.Meanwhile, the voltage limiter also caps when temperature exceeds 120℃, but barely affects the performance at 0℃ to 90℃.It should be noted that, CTAT_vr may provide a lower circuit delay variation than CTAT-like because the absolute circuit delay at 30℃ powered by CTAT_vr is slightly higher than that supplied by CTAT-like.While using the proposed adaptive power supply circuit can help manage the temperatureinduced delays in CMOS circuits, it comes with a cost.The proposed CTAT-like voltage power has a static leakage current, ranging from 1mA to 2mA, depending on the temperature and digital circuits it powers.In the worst scenario, if = 2V as adopted in the simulations, the static power could be as high as 4mW.Nevertheless, as the temperature rises, the impedances of CTAT-like power supply tends to increase as well, leading to lower static current and consequently, lower static power consumption (static current drops from 1.5mA at 0℃ to 1.0mA at 90℃), which actually helps prevent the operation temperature from continuing to rise.In addition, if power gating techniques are applied, such static power consumption can be minuscule.

CONCLUSIONS
Due to the continuous scaling of integrated circuits to deep nanoscale, temperature variations could have substantial impact on the delay of a logic circuit.By exploring the temperaturevoltage-delay relationship, in this paper, we have demonstrated that delay variations resulting from temperature changes can be significantly reduced using the proposed self-adaptive power supply.Of the benchmark circuits adopted in the experiments, if they were driven by a constant voltage power supply, the delay variations could be as high as 50 to 75% over a 90℃ temperature range; however, for the same circuits but powered by the proposed CTAT-like voltage power supply, the delay variations dropped significantly, to a significantly lower level, between15% and 30%.
[9] current source supply with a voltage limiter(Figure3International Journal of VLSI design & Communication Systems (VLSICS) Vol.8, No.3, June voltage power supply source, which is detailed in the next section, delay variations can be well Inverter delay (ps) against temperature under different V pp levels Change rates of delay (ps) vs. temperature under various V pp EMPERATURE-AWARE VOLTAGE POWER SUPPLY penalty introduced by the rising temperature, as alluded in be slightly increased.In light of the linearity between the output current and current source, a self-adaptive, temperature-aware voltage Figure 3, where refers to the external DC voltage source, and June 2017 4 voltage power supply source, which is detailed in the next section, delay variations can be well UPPLY the previous output current and aware voltage power refers to the external DC voltage source, and Electronic copy available at: https://ssrn.com/abstract=3389126

Figure 3
Figure 3 The proposed CTAT

International
Journal of VLSI design & Communication Systems (VLSICS) No.3, June , voltages at nodes 2, 5, 6 and 7 will decrease with the increase of temperature, and thus, the current through MN6 will actually decrease, leading to an increased .In addition, transistor pairs (MN1, MN2), (MN3, MN4) and (MN5, MN6) can help magnify the output voltage changes with respect to the temperature variations The proposed CTAT-like voltage power supply (left) and thevoltage limiter (right) use CTAT-like voltage power supply with voltage limiter

Figure 5
Figure 5  The circuit architecture that includes a power supply and a logic circuit.

Figure 7
Figure 7 Delays (normalized over the baseline) of a single inverter, an inverter chain of three cascaded inverters, a 1-bit FA, and a 4-bit RCA, D-FF and ISCAS-85 benchmark circuits.