A Comparative Study of Electrical Transport Phenomena in Ultrathin vs. Nanoscale SOI MOSFETs Devices
Ultrathin (UTD) and Nanoscale (NSD) SOI-MOSFET devices, sharing a similar W/L but with a channel thickness of 46nm and 1.6nm respectively, were fabricated using a selective “gate recessed” process on the same silicon wafer. The electrical transport characterization at room temperature has shown a large difference between the two kinds of devices and has been interpreted in terms of a huge unexpected series resistance. Electrical characteristics of the Nanoscale device, taken in the linear region, can be analytically derived from the ultrathin device ones. A comparison of the structure and composition of the layers, using advanced techniques such as Focused Ion Beam (FIB) and High Resolution TEM (HRTEM) coupled with Energy Dispersive X-ray Spectroscopy (EDS), contributes an explanation as to the difference of transport between the devices.
A. Karsenty, A. Sa'ar, N. Ben-Yosef, and J. Shappir, "Enhanced electroluminescence in silicon-on-insulator metal-oxide-semiconductor transistors with thin silicon layer", Appl. Phys. Lett., 82, 4830 (2003).
B. Dance, "European SOI Comes of Age, Semiconductor International", p. 83-90, November 1994.
D. Abraham, A. Chelly, D. Elbaz, S. Schiff, M. Nabozny, and Z. Zalevsky, "Modeling of Current-Voltage Characteristics of the Photoactivated Device Based on SOI Technology", Active and Passive Electronic Components, vol. 2012, Article ID 276145, 7 pages, 2012.
D. Esseni, P. Palestri and L. Selmi, "Nanoscale MOS transistors, semi-classical transport and applications", Cambridge University Press, 2011.
L. Peters, "SOI Takes Over Where Silicon Leaves Off", Semiconductor International, March 1993.
 M. Alles and S. Wilson, "Thin Film Silicon on Insulator: An Enabling Technology", Semiconductor International, April 1997.
 A. J. Auberton-Herve and Tadashi Nishimura, "SOI-based devices: Status Overview", Solid State Technology, July 1994.
 A. J. Auberton-Herve, J. M. Lamure, T. Barge, M. Bruel, B. Aspar, and J. L. Pelloie, "SOI Materials for ULSI Applications", Semiconductor International, p.97-104, October 1995.
 T. E. Thompson, "SOI sandwich promises fast, low-power ICs", Electronic Business Today, p. 43-47, October 1995.
 J. Rhea, "DARPA low power program aims at mobile applications", Military & Aerospace Electronics, July 1996.
 P. H. Singer, "U. S. Chipmakers: Penny-Wise, Million-Dollar Foolish", Semiconductor International, August 1995.
 M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A.-J. Auberton-Herve, J. M. Lamure, T. Barge, F. Metral, and S. Trucchi, "SMART CUT ®: A Promising New SOI Material Technology", Proceedings 1995 IEEE International Conference, p. 178-179, October 1995.
 B. Aspar, C. Pudda, A. M. Papon, A.J. Auberton-Herve, and J. M. Lamure, "Ultra-thin buried oxide layers formed by low dose SIMOX processes", The Electrochemical Society: proceedings, Vol. 94, No. 11, p. 62, abstract 541 Silicon On Insulator Technology and Devices edited by S. Cristoloveanu.
 R. Datta, L. P. Allen, R. P. Dolan, K. S. Jones, and M. Farley, "Independent implant parameter effects on SIMOX SOI dislocation formation", Materials Science & Engineering B, Vol. 46, Elsevier Science publications p. 8-13, 1997.
 V. V. Afanas'ev, G. A. Brown, H. L. Hughes, S. T. Liu, and A. G. Revesz, "Conducting and Charge-Trapping Defects in Buried Oxide Layers of SIMOX Structures", J. Electrochem. Soc., Vol. 143, No. 1, p. 347-352, January 1996.
 A. Karsenty, A. Chelly, "Modeling the Transfer Characteristics for High Series Resistance Nanoscale Silicon-On-Insulator (SOI) MOSFETs", Appl. Phys. Lett., submitted for publication.
 A. Karsenty, "Study of the Electrical and Electro-Optical Phenomena in Thin SOI MOS Transistors", PhD Thesis, Hebrew University Of Jerusalem, May 2003.
 L. Do Thanh and P. Balk, "Elimination and Generation of Si-SiO2 Interface Traps by Low Temperature Hydrogen Annealing", J. Electrochem. Soc., Vol. 135, No. 7, p. 1797-1801, July 1988.
 S. Cristoloveanu and T. Ouisse, "The Physics and Chemistry of SiO2 and the Si-SiO2 Interface 2", edited by C.R. Helms and B.E. Deal Plenum Press New York, p. 309-318, 1993.
 V. V. Afanas'ev, A. G. Revesz, and H. L. Hughes, "Confinement Phenomena in Buried Oxides of SIMOX Structures as Affected by Processing", J. Electrochem. Soc., Vol. 143, No. 2, p. 695-700, February 1996.
 J. Wan, C. Le Royer, A. Zaslavsky, S. Cristoloveanu, "Gate-induced drain leakage in FD-SOI devices: What the TFET teaches us about the MOSFET", Microelectronic Engineering, Volume 88, issue 7, July 2011, Pages 1301-1304.
 J. Wang, N. Kistler, J. Woo, and C. R. Viswanathan, "Mobility-field behavior of fully depleted SOI MOSFET's", IEEE Electron Device Lett. 15, 117 (1994).
 D. Esseni, M. Mastrapasqua, G.K. Celler, C. Fiegna, L. Selmi, and E. Sangiorgi, "Low field electron and hole mobility of SOI transistors fabricated on ultrathin silicon films for deep submicrometer technology application", IEEE Electron Device Lett. 48, 2842 (2001).
 K. Uchida and S. Takagi, "Carrier scattering induced by thickness fluctuation of silicon-on-insulator film in ultrathin-body metal–oxide–semiconductor field-effect transistors", Appl. Phys. Lett. 82, 2916 (2003).
 T. Ernst, S. Cristoloveanu, G. Ghibaudo, T.Ouisse, S. Horiguchi, Y. Ono, Y. Takahashi and K. Murase, "Ultimately thin double-gate SOI MOSFETs", IEEE Trans. Electron Devices ED-50, 3 (2003).
 Y. Omura, S. Horiguchi, M. Tabe and K. Kishi, "Quantum-Mechanical Effects on the Threshold Voltage of Ultathin-SOI nMOSFET's", IEEE Electron Device Lett. 14, 569 (1993).
 J. H. Choi, Y.J. Park and H.S. Min, "Electron mobility behavior in extremely thin SOI technology with MOSFETs", IEEE Electron Device Lett. 16, 527 (1995).
 M. Schmidt, M.C. Lemm. H.D.B. Gottlob, F. Driussi, L.Selmi and H. Kurz, "Mobility extraction in SOI MOSFETs with sub 1 nm body thickness", Solid State Electronics 53, 1246 (2009).
 K. Lee, M. Shur and T. A. Fjeldly, "Semiconductor device modeling for VLSI", Prentice Hall 244 (1993).
 K. K. NG and W. T. Lynch, "Analysis of the gate-voltage-dependent series resistance of MOSFET's", IEEE Trans. Electron Devices ED-33, 7 (1986).</p>
M. Bruel, B. Aspar, B. Charlet, C. Maleville, T. Poumeyrol, A. Soubie, A.-J. Auberton-Herve, J. M. Lamure, T. Barge, F. Metral, and S. Trucchi, "SMART CUT: A Promising New SOI Material Technology", Proceedings 1995 IEEE International Conference, p. 178-179, October 1995.
M. Chan, F. Assaderaghi, S. A. Parke, S. S.Yuen, C. Hu, and P. K. Ko, "Recess channel structure for reducing source/drain series resistance in ultra-thin SOI MOSFETs", Proc. IEEE Int. SOI Conf.,Oct.1993, pp.172–173.
S. Cristaloveanu and S. S. Li, "Methods of Forming SOI Wafers - Electrical Characterization of S.O.I. Material and Devices", Kluwer Academic Publishers, Chapter 2, p. 7-15, 1995.
S. Cristoloveanu, Status, "Trends and Challenges of Silicon-on-Insulator Technology - SOI: A Metamorphosis of Silicon", IEEE Circuits & Devices, p. 26-32, January 1999.