Journal article Open Access

FPGA Hardware Implementation and Evaluation of a Micro-Network Architecture for Multi-Core Systems

Yahia Salah; Med Lassaad Kaddachi; Rached Tourki

This paper presents the design, implementation and evaluation of a micro-network, or Network-on-Chip (NoC), based on a generic pipeline router architecture. The router is designed to efficiently support traffic generated by multimedia applications on embedded multi-core systems. It employs a simplest routing mechanism and implements the round-robin scheduling strategy to resolve output port contentions and minimize latency. A virtual channel flow control is applied to avoid the head-of-line blocking problem and enhance performance in the NoC. The hardware design of the router architecture has been implemented at the register transfer level; its functionality is evaluated in the case of the two dimensional Mesh/Torus topology, and performance results are derived from ModelSim simulator and Xilinx ISE 9.2i synthesis tool. An example of a multi-core image processing system utilizing the NoC structure has been implemented and validated to demonstrate the capability of the proposed micro-network architecture. To reduce complexity of the image compression and decompression architecture, the system use image processing algorithm based on classical discrete cosine transform with an efficient zonal processing approach. The experimental results have confirmed that both the proposed image compression scheme and NoC architecture can achieve a reasonable image quality with lower processing time.

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  • <p>
  • B. Grot, et al., "Kilo-NOC: a heterogeneous network-on-chip architecture for scalability and service guarantees," in Proc. of the 38th ISCA, 2011, pp. 1–12.
  • E. Bolotin, I. Cidon, R. Ginosar, A. Kolodny, "QNoC: QoS architecture and design process for network on chip," Journal of Systems Architecture, vol.50, no. 2-3, pp. 105–128, 2004.
  • J.J.H. Pontes, M.T. Moreira, F.G. Moraes, N.L.V. Calazans, "Hermes-A – An Asynchronous NoC Router with Distributed Routing," in International Workshop on Power and Timing Modeling, Optimization and Simulation, 2010, pp. 150–159.
  • M. Ali, M. Welzl, M. Zwicknagl, "Networks on Chips: Scalable Interconnects for Future Systems on Chips," in Proc. of the 3rd IEEE International Conference on Circuits and Systems for Communications, 2006, pp. 1–6.
  • M.A. Al Faruque, J. Henkel, "QoS-Supported On-chip Communication for Multi-Processors," International Journal of Parallel Programming, vol. 36, no. 1, pp. 114–139, 2008.
  • S. Saponara, L. Fanucci, M. Coppola, "Design and coverage-driven verification of a novel network-interface IP macrocell for network-on-chip interconnects," Microprocessors and Microsystems - Embedded Hardware Design, vol. 35, no. 6, pp. 579–592, 2011.
  • S.A. Asghari, H. Pedram, M. Khademi, P. Yaghini, "Designing and Implementation of a Network on Chip Router Based on Handshaking Communication Mechanism," World Applied Sciences Journal, vol. 6, no. 1, pp. 88–93, 2009.
  • T. Bjerregaard, J. Sparsø, "Implementation of guaranteed services in the MANGO clockless network-on-chip," IEE Proc. Computers and Digital Techniques, vol. 153, no. 4, pp. 217–229, 2006. [10] K. Goossens, et al., "The Æthereal network on chip: Concepts, architectures, and implementations," IEEE Design and Test of Computers, vol. 22, no. 5, pp. 414–421, 2005. [11] M. Millberg, E. Nilsson, R. Thid, A. Jantsch, "Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip," in Proc. of DATE'04, 2004, vol. 2, pp. 890–895. [12] R.N.R. Mohammad, K. Reza, "Performance Comparison of 3D-Mesh and 3D-Torus Network-on-Chip," Journal of Computing, vol. 4, no. 1, pp. 78–82, 2012. [13] M. Valinataj, S. Mohammadi, S. Safari, "Fault-aware and Reconfigurable Routing Algorithms for Networks-on-Chip," IETE Journal of Research, vol. 57, no. 3, pp. 215–223, 2011. [14] M. Tang, X. Lin, "Rqrt: Reduce Querying Routing Table for Mesh-Based Network-on-Chip," Journal of Circuits, Systems, and Computers, vol. 20, no. 8, pp. 1529–1545, 2011. [15] Med. L. Kaddachi, L. Makkaoui, A. Soudani, V. Lecuire, J.-M. Moureaux, "FPGA-based image compression for low-power Wireless Camera Sensor Networks," in Proc. of the 3rd International Conference on Next Generation Networks and Services (NGNS 2011), December 2011, pp. 68–71. [16] L. Makkaoui, V. Lecuire, J.-M. Moureaux, "Fast Zonal DCT-based Image Compression for Wireless Camera Sensor Networks," in Proc. of the IEEE international Conference on Image Processing Theory, Tools and Applications (IPTA 2010), July 2010, pp. 126–129. [17]</p>
  • W.-C. Tsai, Y.-C. Lan, Y.H. Hu, S.-J. Chen, "Networks on Chips: Structure and Design Methodologies," Journal of Electrical and Computer Engineering, pp. 1–15, 2012, DOI:10.1155/2012/509465.
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