Optimized Multiplier Based upon 6-Input Luts and Vedic Mathematics
Shuja A. Abbasi
A new approach has been used for optimized design of multipliers based upon the concepts of Vedic mathematics. The design has been targeted to state-of-the art field-programmable gate arrays (FPGAs). The multiplier generates partial products using Vedic mathematics method by employing basic 4x4 multipliers designed by exploiting 6-input LUTs and multiplexers in the same slices resulting in drastic reduction in area. The multiplier is realized on Xilinx FPGAs using devices Virtex-5 and Virtex-6.Carry Chain Adder was employed to obtain final products. The performance of the proposed multiplier was examined and compared to well-known multipliers such as Booth, Carry Save, Carry ripple, and array multipliers. It is demonstrated that the proposed multiplier is superior in terms of speed as well as power consumption.
G. C. T. Chow, K. Eguro, W. Luk, and P. Leong, "A Karatsuba-Based
Montgomery Multiplier," in Field Programmable Logic and
Applications (FPL), 2010 International Conference on, 2010, pp. 434-
J.Senthil Kumar , G.Sriram, G.Lakshminarayanan , B.Venkataramani, "
Design and Implementation of FPGA based Fast Multipliers with
Optimum Placement & Routing Using Structure Organizer", National
Conference on VLSI design & Testing, PSG College of Technology,
Coimbatore, 21-22 February, 2003
K. S. Gurumurthy and M. S. Prahalad, "Fast and power efficient 16 X16
Array of Array multiplier using Vedic Multiplication," in Microsystems
Packaging Assembly and Circuits Technology Conference (IMPACT),
2010 5th International, 2010, pp. 1-4.
 H. D. Tiwari, G. Gankhuyag, K. Chan Mo, and C. Yong Beom,
"Multiplier design based on ancient Indian Vedic Mathematics," in SoC
Design Conference, 2008. ISOCC '08. International, 2008, pp. II-65-II-
 P. Mehta and D. Gawali, "Conventional versus Vedic Mathematical
Method for Hardware Implementation of a Multiplier," in Advances in
Computing, Control, & Telecommunication Technologies, 2009. ACT
'09. International Conference on, 2009, pp. 640-642.
 V. Kunchigi, L. Kulkarni, and S. Kulkarni, "High speed and area
efficient Vedic multiplier," in Devices, Circuits and Systems (ICDCS),
2012 International Conference on, 2012, pp. 360-364.
 L. Sriraman and T. N. Prabakar, "Design and implementation of two
variable multiplier using KCM and Vedic Mathematics," in Recent
Advances in Information Technology (RAIT), 2012 1st International
Conference on, 2012, pp. 782-787.
 Ahmed et. al, "Architecture-Specific Packing for Virtex-5 FPGAs,"
FPGA-08, February 24-26, 2008, Monterey, California, USA.
 Xilinx, "ds100, Virtex-5 Family Overview," February 6, 2009, Xilinx.
 Xilinx, "ds150, Virtex-6 Family Overview," March 24, 2011, Xilinx.
Michael John Sebastian Smith, "Application-specific integrated
circuits", Addison-Wesley, (1997).
P. R. Aparna and N. Thomas, "Design and implementation of a high
performance multiplier using HDL," in Computing, Communication and
Applications (ICCCA), 2012 International Conference on, 2012, pp. 1-5.
S. Akhter, "VHDL implementation of fast NxN multiplier based on
vedic mathematic," in Circuit Theory and Design, 2007. ECCTD 2007.
18th European Conference on, 2007, pp. 472-475.
S. Bhattacharjee, S. Sil, B. Basak, and A. Chakrabarti, "Evaluation of
power efficient adder and multiplier circuits for FPGA based DSP
applications," in Communication and Industrial Application (ICCIA),
2011 International Conference on, 2011, pp. 1-5.
S. K. Mangal, R. B. Deshmukh, R. M. Badghare, and R. M. Patrikar,
"FPGA Implementation of Low Power Parallel Multiplier," in VLSI
Design, 2007. Held jointly with 6th International Conference on
Embedded Systems., 20th International Conference on, 2007, pp. 115-
T. V. More and R. V. Kshirsagar, "Design of low power column bypass
multiplier using FPGA," in Electronics Computer Technology (ICECT),
2011 3rd International Conference on, 2011, pp. 431-435.