1080514
doi
10.5281/zenodo.1080514
oai:zenodo.org:1080514
user-waset
Akinori Kanasugi
A Processor with Dynamically Reconfigurable Circuit for Floating-Point Arithmetic
Yukinari Minagi
info:eu-repo/semantics/openAccess
Creative Commons Attribution 4.0 International
https://creativecommons.org/licenses/by/4.0/legalcode
dynamic reconfiguration
floating-point arithmetic
double precision
FPGA
This paper describes about dynamic reconfiguration to
miniaturize arithmetic circuits in general-purpose processor. Dynamic
reconfiguration is a technique to realize required functions by
changing hardware construction during operation. The proposed
arithmetic circuit performs floating-point arithmetic which is
frequently used in science and technology. The data format is
floating-point based on IEEE754. The proposed circuit is designed
using VHDL, and verified the correct operation by simulations and
experiments.
Zenodo
2010-08-28
info:eu-repo/semantics/article
1080513
user-waset
13110
1579540688.800142
576931
md5:02805567850cd7612a392453ce82ed1e
https://zenodo.org/records/1080514/files/13110.pdf
public
10.5281/zenodo.1080513
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doi