hw/ip/aes/rtl/aes_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package aes_reg_pkg;
8:
9: // Param list
10: parameter int NumRegsKey = 8;
11: parameter int NumRegsData = 4;
12:
13: ////////////////////////////
14: // Typedefs for registers //
15: ////////////////////////////
16: typedef struct packed {
17: logic [31:0] q;
18: logic qe;
19: } aes_reg2hw_key_mreg_t;
20:
21: typedef struct packed {
22: logic [31:0] q;
23: logic qe;
24: } aes_reg2hw_data_in_mreg_t;
25:
26: typedef struct packed {
27: logic [31:0] q;
28: logic re;
29: } aes_reg2hw_data_out_mreg_t;
30:
31: typedef struct packed {
32: struct packed {
33: logic q;
34: logic qe;
35: } mode;
36: struct packed {
37: logic [2:0] q;
38: logic qe;
39: } key_len;
40: struct packed {
41: logic q;
42: logic qe;
43: } manual_start_trigger;
44: struct packed {
45: logic q;
46: logic qe;
47: } force_data_overwrite;
48: } aes_reg2hw_ctrl_reg_t;
49:
50: typedef struct packed {
51: struct packed {
52: logic q;
53: } start;
54: struct packed {
55: logic q;
56: } key_clear;
57: struct packed {
58: logic q;
59: } data_in_clear;
60: struct packed {
61: logic q;
62: } data_out_clear;
63: } aes_reg2hw_trigger_reg_t;
64:
65:
66: typedef struct packed {
67: logic [31:0] d;
68: } aes_hw2reg_key_mreg_t;
69:
70: typedef struct packed {
71: logic [31:0] d;
72: logic de;
73: } aes_hw2reg_data_in_mreg_t;
74:
75: typedef struct packed {
76: logic [31:0] d;
77: } aes_hw2reg_data_out_mreg_t;
78:
79: typedef struct packed {
80: struct packed {
81: logic [2:0] d;
82: } key_len;
83: } aes_hw2reg_ctrl_reg_t;
84:
85: typedef struct packed {
86: struct packed {
87: logic d;
88: logic de;
89: } start;
90: struct packed {
91: logic d;
92: logic de;
93: } key_clear;
94: struct packed {
95: logic d;
96: logic de;
97: } data_in_clear;
98: struct packed {
99: logic d;
100: logic de;
101: } data_out_clear;
102: } aes_hw2reg_trigger_reg_t;
103:
104: typedef struct packed {
105: struct packed {
106: logic d;
107: logic de;
108: } idle;
109: struct packed {
110: logic d;
111: logic de;
112: } stall;
113: struct packed {
114: logic d;
115: logic de;
116: } output_valid;
117: struct packed {
118: logic d;
119: logic de;
120: } input_ready;
121: } aes_hw2reg_status_reg_t;
122:
123:
124: ///////////////////////////////////////
125: // Register to internal design logic //
126: ///////////////////////////////////////
127: typedef struct packed {
128: aes_reg2hw_key_mreg_t [7:0] key; // [541:278]
129: aes_reg2hw_data_in_mreg_t [3:0] data_in; // [277:146]
130: aes_reg2hw_data_out_mreg_t [3:0] data_out; // [145:14]
131: aes_reg2hw_ctrl_reg_t ctrl; // [13:4]
132: aes_reg2hw_trigger_reg_t trigger; // [3:0]
133: } aes_reg2hw_t;
134:
135: ///////////////////////////////////////
136: // Internal design logic to register //
137: ///////////////////////////////////////
138: typedef struct packed {
139: aes_hw2reg_key_mreg_t [7:0] key; // [534:279]
140: aes_hw2reg_data_in_mreg_t [3:0] data_in; // [278:147]
141: aes_hw2reg_data_out_mreg_t [3:0] data_out; // [146:19]
142: aes_hw2reg_ctrl_reg_t ctrl; // [18:9]
143: aes_hw2reg_trigger_reg_t trigger; // [8:5]
144: aes_hw2reg_status_reg_t status; // [4:5]
145: } aes_hw2reg_t;
146:
147: // Register Address
148: parameter logic [6:0] AES_KEY0_OFFSET = 7'h 0;
149: parameter logic [6:0] AES_KEY1_OFFSET = 7'h 4;
150: parameter logic [6:0] AES_KEY2_OFFSET = 7'h 8;
151: parameter logic [6:0] AES_KEY3_OFFSET = 7'h c;
152: parameter logic [6:0] AES_KEY4_OFFSET = 7'h 10;
153: parameter logic [6:0] AES_KEY5_OFFSET = 7'h 14;
154: parameter logic [6:0] AES_KEY6_OFFSET = 7'h 18;
155: parameter logic [6:0] AES_KEY7_OFFSET = 7'h 1c;
156: parameter logic [6:0] AES_DATA_IN0_OFFSET = 7'h 20;
157: parameter logic [6:0] AES_DATA_IN1_OFFSET = 7'h 24;
158: parameter logic [6:0] AES_DATA_IN2_OFFSET = 7'h 28;
159: parameter logic [6:0] AES_DATA_IN3_OFFSET = 7'h 2c;
160: parameter logic [6:0] AES_DATA_OUT0_OFFSET = 7'h 30;
161: parameter logic [6:0] AES_DATA_OUT1_OFFSET = 7'h 34;
162: parameter logic [6:0] AES_DATA_OUT2_OFFSET = 7'h 38;
163: parameter logic [6:0] AES_DATA_OUT3_OFFSET = 7'h 3c;
164: parameter logic [6:0] AES_CTRL_OFFSET = 7'h 40;
165: parameter logic [6:0] AES_TRIGGER_OFFSET = 7'h 44;
166: parameter logic [6:0] AES_STATUS_OFFSET = 7'h 48;
167:
168:
169: // Register Index
170: typedef enum int {
171: AES_KEY0,
172: AES_KEY1,
173: AES_KEY2,
174: AES_KEY3,
175: AES_KEY4,
176: AES_KEY5,
177: AES_KEY6,
178: AES_KEY7,
179: AES_DATA_IN0,
180: AES_DATA_IN1,
181: AES_DATA_IN2,
182: AES_DATA_IN3,
183: AES_DATA_OUT0,
184: AES_DATA_OUT1,
185: AES_DATA_OUT2,
186: AES_DATA_OUT3,
187: AES_CTRL,
188: AES_TRIGGER,
189: AES_STATUS
190: } aes_id_e;
191:
192: // Register width information to check illegal writes
193: parameter logic [3:0] AES_PERMIT [19] = '{
194: 4'b 1111, // index[ 0] AES_KEY0
195: 4'b 1111, // index[ 1] AES_KEY1
196: 4'b 1111, // index[ 2] AES_KEY2
197: 4'b 1111, // index[ 3] AES_KEY3
198: 4'b 1111, // index[ 4] AES_KEY4
199: 4'b 1111, // index[ 5] AES_KEY5
200: 4'b 1111, // index[ 6] AES_KEY6
201: 4'b 1111, // index[ 7] AES_KEY7
202: 4'b 1111, // index[ 8] AES_DATA_IN0
203: 4'b 1111, // index[ 9] AES_DATA_IN1
204: 4'b 1111, // index[10] AES_DATA_IN2
205: 4'b 1111, // index[11] AES_DATA_IN3
206: 4'b 1111, // index[12] AES_DATA_OUT0
207: 4'b 1111, // index[13] AES_DATA_OUT1
208: 4'b 1111, // index[14] AES_DATA_OUT2
209: 4'b 1111, // index[15] AES_DATA_OUT3
210: 4'b 0001, // index[16] AES_CTRL
211: 4'b 0001, // index[17] AES_TRIGGER
212: 4'b 0001 // index[18] AES_STATUS
213: };
214: endpackage
215:
216: