../src/lowrisc_ip_rv_core_ibex_0.1/rtl/rv_core_ibex.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: /**
   6:  * Ibex RISC-V core
   7:  *
   8:  * 32 bit RISC-V core supporting the RV32I + optionally EMC instruction sets.
   9:  * Instruction and data bus are 32 bit wide TileLink-UL (TL-UL).
  10:  */
  11: module rv_core_ibex #(
  12:   parameter bit          PMPEnable                = 1'b0,
  13:   parameter int unsigned PMPGranularity           = 0,
  14:   parameter int unsigned PMPNumRegions            = 4,
  15:   parameter int unsigned MHPMCounterNum           = 8,
  16:   parameter int unsigned MHPMCounterWidth         = 40,
  17:   parameter bit          RV32E                    = 0,
  18:   parameter bit          RV32M                    = 1,
  19:   parameter bit          BranchTargetALU          = 1,
  20:   parameter bit          WritebackStage           = 1,
  21:   parameter              MultiplierImplementation = "single-cycle",
  22:   parameter bit          ICache                   = 1'b0,
  23:   parameter bit          ICacheECC                = 1'b0,
  24:   parameter bit          DbgTriggerEn             = 1'b1,
  25:   parameter bit          SecureIbex               = 1'b0,
  26:   parameter int unsigned DmHaltAddr               = 32'h1A110800,
  27:   parameter int unsigned DmExceptionAddr          = 32'h1A110808,
  28:   parameter bit          PipeLine                 = 0
  29: ) (
  30:   // Clock and Reset
  31:   input  logic        clk_i,
  32:   input  logic        rst_ni,
  33: 
  34:   input  logic        test_en_i,     // enable all clock gates for testing
  35: 
  36:   input  logic [31:0] hart_id_i,
  37:   input  logic [31:0] boot_addr_i,
  38: 
  39:   // Instruction memory interface
  40:   output tlul_pkg::tl_h2d_t     tl_i_o,
  41:   input  tlul_pkg::tl_d2h_t     tl_i_i,
  42: 
  43:   // Data memory interface
  44:   output tlul_pkg::tl_h2d_t     tl_d_o,
  45:   input  tlul_pkg::tl_d2h_t     tl_d_i,
  46: 
  47:   // Interrupt inputs
  48:   input  logic        irq_software_i,
  49:   input  logic        irq_timer_i,
  50:   input  logic        irq_external_i,
  51:   input  logic [14:0] irq_fast_i,
  52:   input  logic        irq_nm_i,
  53: 
  54:   // Debug Interface
  55:   input  logic        debug_req_i,
  56: 
  57:   // CPU Control Signals
  58:   input  logic        fetch_enable_i,
  59:   output logic        core_sleep_o
  60: );
  61: 
  62:   import top_pkg::*;
  63:   import tlul_pkg::*;
  64: 
  65:   // if pipeline=1, do not allow pass through and always break the path
  66:   // if pipeline is 0, passthrough the fifo completely
  67:   localparam int FifoPass = PipeLine ? 1'b0 : 1'b1;
  68:   localparam int FifoDepth = PipeLine ? 4'h2 : 4'h0;
  69: 
  70:   // Instruction interface (internal)
  71:   logic        instr_req;
  72:   logic        instr_gnt;
  73:   logic        instr_rvalid;
  74:   logic [31:0] instr_addr;
  75:   logic [31:0] instr_rdata;
  76:   logic        instr_err;
  77: 
  78:   // Data interface (internal)
  79:   logic        data_req;
  80:   logic        data_gnt;
  81:   logic        data_rvalid;
  82:   logic        data_we;
  83:   logic [3:0]  data_be;
  84:   logic [31:0] data_addr;
  85:   logic [31:0] data_wdata;
  86:   logic [31:0] data_rdata;
  87:   logic        data_err;
  88: 
  89:   // Pipeline interfaces
  90:   tl_h2d_t tl_i_ibex2fifo;
  91:   tl_d2h_t tl_i_fifo2ibex;
  92:   tl_h2d_t tl_d_ibex2fifo;
  93:   tl_d2h_t tl_d_fifo2ibex;
  94: 
  95: `ifdef RVFI
  96:   logic        rvfi_valid;
  97:   logic [63:0] rvfi_order;
  98:   logic [31:0] rvfi_insn;
  99:   logic        rvfi_trap;
 100:   logic        rvfi_halt;
 101:   logic        rvfi_intr;
 102:   logic [ 1:0] rvfi_mode;
 103:   logic [ 1:0] rvfi_ixl;
 104:   logic [ 4:0] rvfi_rs1_addr;
 105:   logic [ 4:0] rvfi_rs2_addr;
 106:   logic [ 4:0] rvfi_rs3_addr;
 107:   logic [31:0] rvfi_rs1_rdata;
 108:   logic [31:0] rvfi_rs2_rdata;
 109:   logic [31:0] rvfi_rs3_rdata;
 110:   logic [ 4:0] rvfi_rd_addr;
 111:   logic [31:0] rvfi_rd_wdata;
 112:   logic [31:0] rvfi_pc_rdata;
 113:   logic [31:0] rvfi_pc_wdata;
 114:   logic [31:0] rvfi_mem_addr;
 115:   logic [ 3:0] rvfi_mem_rmask;
 116:   logic [ 3:0] rvfi_mem_wmask;
 117:   logic [31:0] rvfi_mem_rdata;
 118:   logic [31:0] rvfi_mem_wdata;
 119: `endif
 120: 
 121:   ibex_core #(
 122:     .PMPEnable                ( PMPEnable                ),
 123:     .PMPGranularity           ( PMPGranularity           ),
 124:     .PMPNumRegions            ( PMPNumRegions            ),
 125:     .MHPMCounterNum           ( MHPMCounterNum           ),
 126:     .MHPMCounterWidth         ( MHPMCounterWidth         ),
 127:     .RV32E                    ( RV32E                    ),
 128:     .RV32M                    ( RV32M                    ),
 129:     .BranchTargetALU          ( BranchTargetALU          ),
 130:     .WritebackStage           ( WritebackStage           ),
 131:     .MultiplierImplementation ( MultiplierImplementation ),
 132:     .ICache                   ( ICache                   ),
 133:     .ICacheECC                ( ICacheECC                ),
 134:     .DbgTriggerEn             ( DbgTriggerEn             ),
 135:     .SecureIbex               ( SecureIbex               ),
 136:     .DmHaltAddr               ( DmHaltAddr               ),
 137:     .DmExceptionAddr          ( DmExceptionAddr          )
 138:   ) u_core (
 139:     .clk_i,
 140:     .rst_ni,
 141: 
 142:     .test_en_i,
 143: 
 144:     .hart_id_i,
 145:     .boot_addr_i,
 146: 
 147:     .instr_req_o    ( instr_req    ),
 148:     .instr_gnt_i    ( instr_gnt    ),
 149:     .instr_rvalid_i ( instr_rvalid ),
 150:     .instr_addr_o   ( instr_addr   ),
 151:     .instr_rdata_i  ( instr_rdata  ),
 152:     .instr_err_i    ( instr_err    ),
 153: 
 154:     .data_req_o     ( data_req     ),
 155:     .data_gnt_i     ( data_gnt     ),
 156:     .data_rvalid_i  ( data_rvalid  ),
 157:     .data_we_o      ( data_we      ),
 158:     .data_be_o      ( data_be      ),
 159:     .data_addr_o    ( data_addr    ),
 160:     .data_wdata_o   ( data_wdata   ),
 161:     .data_rdata_i   ( data_rdata   ),
 162:     .data_err_i     ( data_err     ),
 163: 
 164:     .irq_software_i,
 165:     .irq_timer_i,
 166:     .irq_external_i,
 167:     .irq_fast_i,
 168:     .irq_nm_i,
 169: 
 170:     .debug_req_i,
 171: 
 172: `ifdef RVFI
 173:     .rvfi_valid,
 174:     .rvfi_order,
 175:     .rvfi_insn,
 176:     .rvfi_trap,
 177:     .rvfi_halt,
 178:     .rvfi_intr,
 179:     .rvfi_mode,
 180:     .rvfi_ixl,
 181:     .rvfi_rs1_addr,
 182:     .rvfi_rs2_addr,
 183:     .rvfi_rs3_addr,
 184:     .rvfi_rs1_rdata,
 185:     .rvfi_rs2_rdata,
 186:     .rvfi_rs3_rdata,
 187:     .rvfi_rd_addr,
 188:     .rvfi_rd_wdata,
 189:     .rvfi_pc_rdata,
 190:     .rvfi_pc_wdata,
 191:     .rvfi_mem_addr,
 192:     .rvfi_mem_rmask,
 193:     .rvfi_mem_wmask,
 194:     .rvfi_mem_rdata,
 195:     .rvfi_mem_wdata,
 196: `endif
 197: 
 198:     .fetch_enable_i,
 199:     .core_sleep_o
 200:   );
 201: 
 202:   //
 203:   // Convert ibex data/instruction bus to TL-UL
 204:   //
 205: 
 206:   tlul_adapter_host #(
 207:     .MAX_REQS(2)
 208:   ) tl_adapter_host_i_ibex (
 209:     .clk_i,
 210:     .rst_ni,
 211:     .req_i   (instr_req),
 212:     .gnt_o   (instr_gnt),
 213:     .addr_i  (instr_addr),
 214:     .we_i    (1'b0),
 215:     .wdata_i (32'b0),
 216:     .be_i    (4'hF),
 217:     .valid_o (instr_rvalid),
 218:     .rdata_o (instr_rdata),
 219:     .err_o   (instr_err),
 220:     .tl_o    (tl_i_ibex2fifo),
 221:     .tl_i    (tl_i_fifo2ibex)
 222:   );
 223: 
 224:   tlul_fifo_sync #(
 225:     .ReqPass(FifoPass),
 226:     .RspPass(FifoPass),
 227:     .ReqDepth(FifoDepth),
 228:     .RspDepth(FifoDepth)
 229:   ) fifo_i (
 230:     .clk_i,
 231:     .rst_ni,
 232:     .tl_h_i      (tl_i_ibex2fifo),
 233:     .tl_h_o      (tl_i_fifo2ibex),
 234:     .tl_d_o      (tl_i_o),
 235:     .tl_d_i      (tl_i_i),
 236:     .spare_req_i (1'b0),
 237:     .spare_req_o (),
 238:     .spare_rsp_i (1'b0),
 239:     .spare_rsp_o ());
 240: 
 241:   tlul_adapter_host #(
 242:     .MAX_REQS(2)
 243:   ) tl_adapter_host_d_ibex (
 244:     .clk_i,
 245:     .rst_ni,
 246:     .req_i   (data_req),
 247:     .gnt_o   (data_gnt),
 248:     .addr_i  (data_addr),
 249:     .we_i    (data_we),
 250:     .wdata_i (data_wdata),
 251:     .be_i    (data_be),
 252:     .valid_o (data_rvalid),
 253:     .rdata_o (data_rdata),
 254:     .err_o   (data_err),
 255:     .tl_o    (tl_d_ibex2fifo),
 256:     .tl_i    (tl_d_fifo2ibex)
 257:   );
 258: 
 259:   tlul_fifo_sync #(
 260:     .ReqPass(FifoPass),
 261:     .RspPass(FifoPass),
 262:     .ReqDepth(FifoDepth),
 263:     .RspDepth(FifoDepth)
 264:   ) fifo_d (
 265:     .clk_i,
 266:     .rst_ni,
 267:     .tl_h_i      (tl_d_ibex2fifo),
 268:     .tl_h_o      (tl_d_fifo2ibex),
 269:     .tl_d_o      (tl_d_o),
 270:     .tl_d_i      (tl_d_i),
 271:     .spare_req_i (1'b0),
 272:     .spare_req_o (),
 273:     .spare_rsp_i (1'b0),
 274:     .spare_rsp_o ());
 275: 
 276: 
 277: `ifdef RVFI
 278:   ibex_tracer ibex_tracer_i (
 279:     .clk_i,
 280:     .rst_ni,
 281: 
 282:     .hart_id_i,
 283: 
 284:     .rvfi_valid,
 285:     .rvfi_order,
 286:     .rvfi_insn,
 287:     .rvfi_trap,
 288:     .rvfi_halt,
 289:     .rvfi_intr,
 290:     .rvfi_mode,
 291:     .rvfi_ixl,
 292:     .rvfi_rs1_addr,
 293:     .rvfi_rs2_addr,
 294:     .rvfi_rs3_addr,
 295:     .rvfi_rs1_rdata,
 296:     .rvfi_rs2_rdata,
 297:     .rvfi_rs3_rdata,
 298:     .rvfi_rd_addr,
 299:     .rvfi_rd_wdata,
 300:     .rvfi_pc_rdata,
 301:     .rvfi_pc_wdata,
 302:     .rvfi_mem_addr,
 303:     .rvfi_mem_rmask,
 304:     .rvfi_mem_wmask,
 305:     .rvfi_mem_rdata,
 306:     .rvfi_mem_wdata
 307:   );
 308: `endif
 309: 
 310: 
 311: endmodule
 312: