../src/lowrisc_top_earlgrey_pinmux_reg_0.1/rtl/autogen/pinmux_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: `include "prim_assert.sv"
   8: 
   9: module pinmux_reg_top (
  10:   input clk_i,
  11:   input rst_ni,
  12: 
  13:   // Below Regster interface can be changed
  14:   input  tlul_pkg::tl_h2d_t tl_i,
  15:   output tlul_pkg::tl_d2h_t tl_o,
  16:   // To HW
  17:   output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
  18:   input  pinmux_reg_pkg::pinmux_hw2reg_t hw2reg, // Read
  19: 
  20:   // Config
  21:   input devmode_i // If 1, explicit error return for unmapped register access
  22: );
  23: 
  24:   import pinmux_reg_pkg::* ;
  25: 
  26:   localparam int AW = 7;
  27:   localparam int DW = 32;
  28:   localparam int DBW = DW/8;                    // Byte Width
  29: 
  30:   // register signals
  31:   logic           reg_we;
  32:   logic           reg_re;
  33:   logic [AW-1:0]  reg_addr;
  34:   logic [DW-1:0]  reg_wdata;
  35:   logic [DBW-1:0] reg_be;
  36:   logic [DW-1:0]  reg_rdata;
  37:   logic           reg_error;
  38: 
  39:   logic          addrmiss, wr_err;
  40: 
  41:   logic [DW-1:0] reg_rdata_next;
  42: 
  43:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  44:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  45: 
  46:   assign tl_reg_h2d = tl_i;
  47:   assign tl_o       = tl_reg_d2h;
  48: 
  49:   tlul_adapter_reg #(
  50:     .RegAw(AW),
  51:     .RegDw(DW)
  52:   ) u_reg_if (
  53:     .clk_i,
  54:     .rst_ni,
  55: 
  56:     .tl_i (tl_reg_h2d),
  57:     .tl_o (tl_reg_d2h),
  58: 
  59:     .we_o    (reg_we),
  60:     .re_o    (reg_re),
  61:     .addr_o  (reg_addr),
  62:     .wdata_o (reg_wdata),
  63:     .be_o    (reg_be),
  64:     .rdata_i (reg_rdata),
  65:     .error_i (reg_error)
  66:   );
  67: 
  68:   assign reg_rdata = reg_rdata_next ;
  69:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  70: 
  71:   // Define SW related signals
  72:   // Format: __{wd|we|qs}
  73:   //        or _{wd|we|qs} if field == 1 or 0
  74:   logic regen_qs;
  75:   logic regen_wd;
  76:   logic regen_we;
  77:   logic [5:0] periph_insel0_in0_qs;
  78:   logic [5:0] periph_insel0_in0_wd;
  79:   logic periph_insel0_in0_we;
  80:   logic [5:0] periph_insel0_in1_qs;
  81:   logic [5:0] periph_insel0_in1_wd;
  82:   logic periph_insel0_in1_we;
  83:   logic [5:0] periph_insel0_in2_qs;
  84:   logic [5:0] periph_insel0_in2_wd;
  85:   logic periph_insel0_in2_we;
  86:   logic [5:0] periph_insel0_in3_qs;
  87:   logic [5:0] periph_insel0_in3_wd;
  88:   logic periph_insel0_in3_we;
  89:   logic [5:0] periph_insel0_in4_qs;
  90:   logic [5:0] periph_insel0_in4_wd;
  91:   logic periph_insel0_in4_we;
  92:   logic [5:0] periph_insel1_in5_qs;
  93:   logic [5:0] periph_insel1_in5_wd;
  94:   logic periph_insel1_in5_we;
  95:   logic [5:0] periph_insel1_in6_qs;
  96:   logic [5:0] periph_insel1_in6_wd;
  97:   logic periph_insel1_in6_we;
  98:   logic [5:0] periph_insel1_in7_qs;
  99:   logic [5:0] periph_insel1_in7_wd;
 100:   logic periph_insel1_in7_we;
 101:   logic [5:0] periph_insel1_in8_qs;
 102:   logic [5:0] periph_insel1_in8_wd;
 103:   logic periph_insel1_in8_we;
 104:   logic [5:0] periph_insel1_in9_qs;
 105:   logic [5:0] periph_insel1_in9_wd;
 106:   logic periph_insel1_in9_we;
 107:   logic [5:0] periph_insel2_in10_qs;
 108:   logic [5:0] periph_insel2_in10_wd;
 109:   logic periph_insel2_in10_we;
 110:   logic [5:0] periph_insel2_in11_qs;
 111:   logic [5:0] periph_insel2_in11_wd;
 112:   logic periph_insel2_in11_we;
 113:   logic [5:0] periph_insel2_in12_qs;
 114:   logic [5:0] periph_insel2_in12_wd;
 115:   logic periph_insel2_in12_we;
 116:   logic [5:0] periph_insel2_in13_qs;
 117:   logic [5:0] periph_insel2_in13_wd;
 118:   logic periph_insel2_in13_we;
 119:   logic [5:0] periph_insel2_in14_qs;
 120:   logic [5:0] periph_insel2_in14_wd;
 121:   logic periph_insel2_in14_we;
 122:   logic [5:0] periph_insel3_in15_qs;
 123:   logic [5:0] periph_insel3_in15_wd;
 124:   logic periph_insel3_in15_we;
 125:   logic [5:0] periph_insel3_in16_qs;
 126:   logic [5:0] periph_insel3_in16_wd;
 127:   logic periph_insel3_in16_we;
 128:   logic [5:0] periph_insel3_in17_qs;
 129:   logic [5:0] periph_insel3_in17_wd;
 130:   logic periph_insel3_in17_we;
 131:   logic [5:0] periph_insel3_in18_qs;
 132:   logic [5:0] periph_insel3_in18_wd;
 133:   logic periph_insel3_in18_we;
 134:   logic [5:0] periph_insel3_in19_qs;
 135:   logic [5:0] periph_insel3_in19_wd;
 136:   logic periph_insel3_in19_we;
 137:   logic [5:0] periph_insel4_in20_qs;
 138:   logic [5:0] periph_insel4_in20_wd;
 139:   logic periph_insel4_in20_we;
 140:   logic [5:0] periph_insel4_in21_qs;
 141:   logic [5:0] periph_insel4_in21_wd;
 142:   logic periph_insel4_in21_we;
 143:   logic [5:0] periph_insel4_in22_qs;
 144:   logic [5:0] periph_insel4_in22_wd;
 145:   logic periph_insel4_in22_we;
 146:   logic [5:0] periph_insel4_in23_qs;
 147:   logic [5:0] periph_insel4_in23_wd;
 148:   logic periph_insel4_in23_we;
 149:   logic [5:0] periph_insel4_in24_qs;
 150:   logic [5:0] periph_insel4_in24_wd;
 151:   logic periph_insel4_in24_we;
 152:   logic [5:0] periph_insel5_in25_qs;
 153:   logic [5:0] periph_insel5_in25_wd;
 154:   logic periph_insel5_in25_we;
 155:   logic [5:0] periph_insel5_in26_qs;
 156:   logic [5:0] periph_insel5_in26_wd;
 157:   logic periph_insel5_in26_we;
 158:   logic [5:0] periph_insel5_in27_qs;
 159:   logic [5:0] periph_insel5_in27_wd;
 160:   logic periph_insel5_in27_we;
 161:   logic [5:0] periph_insel5_in28_qs;
 162:   logic [5:0] periph_insel5_in28_wd;
 163:   logic periph_insel5_in28_we;
 164:   logic [5:0] periph_insel5_in29_qs;
 165:   logic [5:0] periph_insel5_in29_wd;
 166:   logic periph_insel5_in29_we;
 167:   logic [5:0] periph_insel6_in30_qs;
 168:   logic [5:0] periph_insel6_in30_wd;
 169:   logic periph_insel6_in30_we;
 170:   logic [5:0] periph_insel6_in31_qs;
 171:   logic [5:0] periph_insel6_in31_wd;
 172:   logic periph_insel6_in31_we;
 173:   logic [5:0] mio_outsel0_out0_qs;
 174:   logic [5:0] mio_outsel0_out0_wd;
 175:   logic mio_outsel0_out0_we;
 176:   logic [5:0] mio_outsel0_out1_qs;
 177:   logic [5:0] mio_outsel0_out1_wd;
 178:   logic mio_outsel0_out1_we;
 179:   logic [5:0] mio_outsel0_out2_qs;
 180:   logic [5:0] mio_outsel0_out2_wd;
 181:   logic mio_outsel0_out2_we;
 182:   logic [5:0] mio_outsel0_out3_qs;
 183:   logic [5:0] mio_outsel0_out3_wd;
 184:   logic mio_outsel0_out3_we;
 185:   logic [5:0] mio_outsel0_out4_qs;
 186:   logic [5:0] mio_outsel0_out4_wd;
 187:   logic mio_outsel0_out4_we;
 188:   logic [5:0] mio_outsel1_out5_qs;
 189:   logic [5:0] mio_outsel1_out5_wd;
 190:   logic mio_outsel1_out5_we;
 191:   logic [5:0] mio_outsel1_out6_qs;
 192:   logic [5:0] mio_outsel1_out6_wd;
 193:   logic mio_outsel1_out6_we;
 194:   logic [5:0] mio_outsel1_out7_qs;
 195:   logic [5:0] mio_outsel1_out7_wd;
 196:   logic mio_outsel1_out7_we;
 197:   logic [5:0] mio_outsel1_out8_qs;
 198:   logic [5:0] mio_outsel1_out8_wd;
 199:   logic mio_outsel1_out8_we;
 200:   logic [5:0] mio_outsel1_out9_qs;
 201:   logic [5:0] mio_outsel1_out9_wd;
 202:   logic mio_outsel1_out9_we;
 203:   logic [5:0] mio_outsel2_out10_qs;
 204:   logic [5:0] mio_outsel2_out10_wd;
 205:   logic mio_outsel2_out10_we;
 206:   logic [5:0] mio_outsel2_out11_qs;
 207:   logic [5:0] mio_outsel2_out11_wd;
 208:   logic mio_outsel2_out11_we;
 209:   logic [5:0] mio_outsel2_out12_qs;
 210:   logic [5:0] mio_outsel2_out12_wd;
 211:   logic mio_outsel2_out12_we;
 212:   logic [5:0] mio_outsel2_out13_qs;
 213:   logic [5:0] mio_outsel2_out13_wd;
 214:   logic mio_outsel2_out13_we;
 215:   logic [5:0] mio_outsel2_out14_qs;
 216:   logic [5:0] mio_outsel2_out14_wd;
 217:   logic mio_outsel2_out14_we;
 218:   logic [5:0] mio_outsel3_out15_qs;
 219:   logic [5:0] mio_outsel3_out15_wd;
 220:   logic mio_outsel3_out15_we;
 221:   logic [5:0] mio_outsel3_out16_qs;
 222:   logic [5:0] mio_outsel3_out16_wd;
 223:   logic mio_outsel3_out16_we;
 224:   logic [5:0] mio_outsel3_out17_qs;
 225:   logic [5:0] mio_outsel3_out17_wd;
 226:   logic mio_outsel3_out17_we;
 227:   logic [5:0] mio_outsel3_out18_qs;
 228:   logic [5:0] mio_outsel3_out18_wd;
 229:   logic mio_outsel3_out18_we;
 230:   logic [5:0] mio_outsel3_out19_qs;
 231:   logic [5:0] mio_outsel3_out19_wd;
 232:   logic mio_outsel3_out19_we;
 233:   logic [5:0] mio_outsel4_out20_qs;
 234:   logic [5:0] mio_outsel4_out20_wd;
 235:   logic mio_outsel4_out20_we;
 236:   logic [5:0] mio_outsel4_out21_qs;
 237:   logic [5:0] mio_outsel4_out21_wd;
 238:   logic mio_outsel4_out21_we;
 239:   logic [5:0] mio_outsel4_out22_qs;
 240:   logic [5:0] mio_outsel4_out22_wd;
 241:   logic mio_outsel4_out22_we;
 242:   logic [5:0] mio_outsel4_out23_qs;
 243:   logic [5:0] mio_outsel4_out23_wd;
 244:   logic mio_outsel4_out23_we;
 245:   logic [5:0] mio_outsel4_out24_qs;
 246:   logic [5:0] mio_outsel4_out24_wd;
 247:   logic mio_outsel4_out24_we;
 248:   logic [5:0] mio_outsel5_out25_qs;
 249:   logic [5:0] mio_outsel5_out25_wd;
 250:   logic mio_outsel5_out25_we;
 251:   logic [5:0] mio_outsel5_out26_qs;
 252:   logic [5:0] mio_outsel5_out26_wd;
 253:   logic mio_outsel5_out26_we;
 254:   logic [5:0] mio_outsel5_out27_qs;
 255:   logic [5:0] mio_outsel5_out27_wd;
 256:   logic mio_outsel5_out27_we;
 257:   logic [5:0] mio_outsel5_out28_qs;
 258:   logic [5:0] mio_outsel5_out28_wd;
 259:   logic mio_outsel5_out28_we;
 260:   logic [5:0] mio_outsel5_out29_qs;
 261:   logic [5:0] mio_outsel5_out29_wd;
 262:   logic mio_outsel5_out29_we;
 263:   logic [5:0] mio_outsel6_out30_qs;
 264:   logic [5:0] mio_outsel6_out30_wd;
 265:   logic mio_outsel6_out30_we;
 266:   logic [5:0] mio_outsel6_out31_qs;
 267:   logic [5:0] mio_outsel6_out31_wd;
 268:   logic mio_outsel6_out31_we;
 269:   logic [1:0] mio_out_sleep_val0_out0_qs;
 270:   logic [1:0] mio_out_sleep_val0_out0_wd;
 271:   logic mio_out_sleep_val0_out0_we;
 272:   logic [1:0] mio_out_sleep_val0_out1_qs;
 273:   logic [1:0] mio_out_sleep_val0_out1_wd;
 274:   logic mio_out_sleep_val0_out1_we;
 275:   logic [1:0] mio_out_sleep_val0_out2_qs;
 276:   logic [1:0] mio_out_sleep_val0_out2_wd;
 277:   logic mio_out_sleep_val0_out2_we;
 278:   logic [1:0] mio_out_sleep_val0_out3_qs;
 279:   logic [1:0] mio_out_sleep_val0_out3_wd;
 280:   logic mio_out_sleep_val0_out3_we;
 281:   logic [1:0] mio_out_sleep_val0_out4_qs;
 282:   logic [1:0] mio_out_sleep_val0_out4_wd;
 283:   logic mio_out_sleep_val0_out4_we;
 284:   logic [1:0] mio_out_sleep_val0_out5_qs;
 285:   logic [1:0] mio_out_sleep_val0_out5_wd;
 286:   logic mio_out_sleep_val0_out5_we;
 287:   logic [1:0] mio_out_sleep_val0_out6_qs;
 288:   logic [1:0] mio_out_sleep_val0_out6_wd;
 289:   logic mio_out_sleep_val0_out6_we;
 290:   logic [1:0] mio_out_sleep_val0_out7_qs;
 291:   logic [1:0] mio_out_sleep_val0_out7_wd;
 292:   logic mio_out_sleep_val0_out7_we;
 293:   logic [1:0] mio_out_sleep_val0_out8_qs;
 294:   logic [1:0] mio_out_sleep_val0_out8_wd;
 295:   logic mio_out_sleep_val0_out8_we;
 296:   logic [1:0] mio_out_sleep_val0_out9_qs;
 297:   logic [1:0] mio_out_sleep_val0_out9_wd;
 298:   logic mio_out_sleep_val0_out9_we;
 299:   logic [1:0] mio_out_sleep_val0_out10_qs;
 300:   logic [1:0] mio_out_sleep_val0_out10_wd;
 301:   logic mio_out_sleep_val0_out10_we;
 302:   logic [1:0] mio_out_sleep_val0_out11_qs;
 303:   logic [1:0] mio_out_sleep_val0_out11_wd;
 304:   logic mio_out_sleep_val0_out11_we;
 305:   logic [1:0] mio_out_sleep_val0_out12_qs;
 306:   logic [1:0] mio_out_sleep_val0_out12_wd;
 307:   logic mio_out_sleep_val0_out12_we;
 308:   logic [1:0] mio_out_sleep_val0_out13_qs;
 309:   logic [1:0] mio_out_sleep_val0_out13_wd;
 310:   logic mio_out_sleep_val0_out13_we;
 311:   logic [1:0] mio_out_sleep_val0_out14_qs;
 312:   logic [1:0] mio_out_sleep_val0_out14_wd;
 313:   logic mio_out_sleep_val0_out14_we;
 314:   logic [1:0] mio_out_sleep_val0_out15_qs;
 315:   logic [1:0] mio_out_sleep_val0_out15_wd;
 316:   logic mio_out_sleep_val0_out15_we;
 317:   logic [1:0] mio_out_sleep_val1_out16_qs;
 318:   logic [1:0] mio_out_sleep_val1_out16_wd;
 319:   logic mio_out_sleep_val1_out16_we;
 320:   logic [1:0] mio_out_sleep_val1_out17_qs;
 321:   logic [1:0] mio_out_sleep_val1_out17_wd;
 322:   logic mio_out_sleep_val1_out17_we;
 323:   logic [1:0] mio_out_sleep_val1_out18_qs;
 324:   logic [1:0] mio_out_sleep_val1_out18_wd;
 325:   logic mio_out_sleep_val1_out18_we;
 326:   logic [1:0] mio_out_sleep_val1_out19_qs;
 327:   logic [1:0] mio_out_sleep_val1_out19_wd;
 328:   logic mio_out_sleep_val1_out19_we;
 329:   logic [1:0] mio_out_sleep_val1_out20_qs;
 330:   logic [1:0] mio_out_sleep_val1_out20_wd;
 331:   logic mio_out_sleep_val1_out20_we;
 332:   logic [1:0] mio_out_sleep_val1_out21_qs;
 333:   logic [1:0] mio_out_sleep_val1_out21_wd;
 334:   logic mio_out_sleep_val1_out21_we;
 335:   logic [1:0] mio_out_sleep_val1_out22_qs;
 336:   logic [1:0] mio_out_sleep_val1_out22_wd;
 337:   logic mio_out_sleep_val1_out22_we;
 338:   logic [1:0] mio_out_sleep_val1_out23_qs;
 339:   logic [1:0] mio_out_sleep_val1_out23_wd;
 340:   logic mio_out_sleep_val1_out23_we;
 341:   logic [1:0] mio_out_sleep_val1_out24_qs;
 342:   logic [1:0] mio_out_sleep_val1_out24_wd;
 343:   logic mio_out_sleep_val1_out24_we;
 344:   logic [1:0] mio_out_sleep_val1_out25_qs;
 345:   logic [1:0] mio_out_sleep_val1_out25_wd;
 346:   logic mio_out_sleep_val1_out25_we;
 347:   logic [1:0] mio_out_sleep_val1_out26_qs;
 348:   logic [1:0] mio_out_sleep_val1_out26_wd;
 349:   logic mio_out_sleep_val1_out26_we;
 350:   logic [1:0] mio_out_sleep_val1_out27_qs;
 351:   logic [1:0] mio_out_sleep_val1_out27_wd;
 352:   logic mio_out_sleep_val1_out27_we;
 353:   logic [1:0] mio_out_sleep_val1_out28_qs;
 354:   logic [1:0] mio_out_sleep_val1_out28_wd;
 355:   logic mio_out_sleep_val1_out28_we;
 356:   logic [1:0] mio_out_sleep_val1_out29_qs;
 357:   logic [1:0] mio_out_sleep_val1_out29_wd;
 358:   logic mio_out_sleep_val1_out29_we;
 359:   logic [1:0] mio_out_sleep_val1_out30_qs;
 360:   logic [1:0] mio_out_sleep_val1_out30_wd;
 361:   logic mio_out_sleep_val1_out30_we;
 362:   logic [1:0] mio_out_sleep_val1_out31_qs;
 363:   logic [1:0] mio_out_sleep_val1_out31_wd;
 364:   logic mio_out_sleep_val1_out31_we;
 365:   logic [1:0] dio_out_sleep_val_out0_qs;
 366:   logic [1:0] dio_out_sleep_val_out0_wd;
 367:   logic dio_out_sleep_val_out0_we;
 368:   logic dio_out_sleep_val_out0_re;
 369:   logic [1:0] dio_out_sleep_val_out1_qs;
 370:   logic [1:0] dio_out_sleep_val_out1_wd;
 371:   logic dio_out_sleep_val_out1_we;
 372:   logic dio_out_sleep_val_out1_re;
 373:   logic [1:0] dio_out_sleep_val_out2_qs;
 374:   logic [1:0] dio_out_sleep_val_out2_wd;
 375:   logic dio_out_sleep_val_out2_we;
 376:   logic dio_out_sleep_val_out2_re;
 377:   logic [1:0] dio_out_sleep_val_out3_qs;
 378:   logic [1:0] dio_out_sleep_val_out3_wd;
 379:   logic dio_out_sleep_val_out3_we;
 380:   logic dio_out_sleep_val_out3_re;
 381:   logic [1:0] dio_out_sleep_val_out4_qs;
 382:   logic [1:0] dio_out_sleep_val_out4_wd;
 383:   logic dio_out_sleep_val_out4_we;
 384:   logic dio_out_sleep_val_out4_re;
 385:   logic [1:0] dio_out_sleep_val_out5_qs;
 386:   logic [1:0] dio_out_sleep_val_out5_wd;
 387:   logic dio_out_sleep_val_out5_we;
 388:   logic dio_out_sleep_val_out5_re;
 389:   logic [1:0] dio_out_sleep_val_out6_qs;
 390:   logic [1:0] dio_out_sleep_val_out6_wd;
 391:   logic dio_out_sleep_val_out6_we;
 392:   logic dio_out_sleep_val_out6_re;
 393:   logic [1:0] dio_out_sleep_val_out7_qs;
 394:   logic [1:0] dio_out_sleep_val_out7_wd;
 395:   logic dio_out_sleep_val_out7_we;
 396:   logic dio_out_sleep_val_out7_re;
 397:   logic [1:0] dio_out_sleep_val_out8_qs;
 398:   logic [1:0] dio_out_sleep_val_out8_wd;
 399:   logic dio_out_sleep_val_out8_we;
 400:   logic dio_out_sleep_val_out8_re;
 401:   logic [1:0] dio_out_sleep_val_out9_qs;
 402:   logic [1:0] dio_out_sleep_val_out9_wd;
 403:   logic dio_out_sleep_val_out9_we;
 404:   logic dio_out_sleep_val_out9_re;
 405:   logic [1:0] dio_out_sleep_val_out10_qs;
 406:   logic [1:0] dio_out_sleep_val_out10_wd;
 407:   logic dio_out_sleep_val_out10_we;
 408:   logic dio_out_sleep_val_out10_re;
 409:   logic [1:0] dio_out_sleep_val_out11_qs;
 410:   logic [1:0] dio_out_sleep_val_out11_wd;
 411:   logic dio_out_sleep_val_out11_we;
 412:   logic dio_out_sleep_val_out11_re;
 413:   logic [1:0] dio_out_sleep_val_out12_qs;
 414:   logic [1:0] dio_out_sleep_val_out12_wd;
 415:   logic dio_out_sleep_val_out12_we;
 416:   logic dio_out_sleep_val_out12_re;
 417:   logic [1:0] dio_out_sleep_val_out13_qs;
 418:   logic [1:0] dio_out_sleep_val_out13_wd;
 419:   logic dio_out_sleep_val_out13_we;
 420:   logic dio_out_sleep_val_out13_re;
 421:   logic [1:0] dio_out_sleep_val_out14_qs;
 422:   logic [1:0] dio_out_sleep_val_out14_wd;
 423:   logic dio_out_sleep_val_out14_we;
 424:   logic dio_out_sleep_val_out14_re;
 425:   logic wkup_detector_en_en0_qs;
 426:   logic wkup_detector_en_en0_wd;
 427:   logic wkup_detector_en_en0_we;
 428:   logic wkup_detector_en_en1_qs;
 429:   logic wkup_detector_en_en1_wd;
 430:   logic wkup_detector_en_en1_we;
 431:   logic wkup_detector_en_en2_qs;
 432:   logic wkup_detector_en_en2_wd;
 433:   logic wkup_detector_en_en2_we;
 434:   logic wkup_detector_en_en3_qs;
 435:   logic wkup_detector_en_en3_wd;
 436:   logic wkup_detector_en_en3_we;
 437:   logic wkup_detector_en_en4_qs;
 438:   logic wkup_detector_en_en4_wd;
 439:   logic wkup_detector_en_en4_we;
 440:   logic wkup_detector_en_en5_qs;
 441:   logic wkup_detector_en_en5_wd;
 442:   logic wkup_detector_en_en5_we;
 443:   logic wkup_detector_en_en6_qs;
 444:   logic wkup_detector_en_en6_wd;
 445:   logic wkup_detector_en_en6_we;
 446:   logic wkup_detector_en_en7_qs;
 447:   logic wkup_detector_en_en7_wd;
 448:   logic wkup_detector_en_en7_we;
 449:   logic [2:0] wkup_detector0_mode0_qs;
 450:   logic [2:0] wkup_detector0_mode0_wd;
 451:   logic wkup_detector0_mode0_we;
 452:   logic wkup_detector0_filter0_qs;
 453:   logic wkup_detector0_filter0_wd;
 454:   logic wkup_detector0_filter0_we;
 455:   logic wkup_detector0_miodio0_qs;
 456:   logic wkup_detector0_miodio0_wd;
 457:   logic wkup_detector0_miodio0_we;
 458:   logic [2:0] wkup_detector1_mode1_qs;
 459:   logic [2:0] wkup_detector1_mode1_wd;
 460:   logic wkup_detector1_mode1_we;
 461:   logic wkup_detector1_filter1_qs;
 462:   logic wkup_detector1_filter1_wd;
 463:   logic wkup_detector1_filter1_we;
 464:   logic wkup_detector1_miodio1_qs;
 465:   logic wkup_detector1_miodio1_wd;
 466:   logic wkup_detector1_miodio1_we;
 467:   logic [2:0] wkup_detector2_mode2_qs;
 468:   logic [2:0] wkup_detector2_mode2_wd;
 469:   logic wkup_detector2_mode2_we;
 470:   logic wkup_detector2_filter2_qs;
 471:   logic wkup_detector2_filter2_wd;
 472:   logic wkup_detector2_filter2_we;
 473:   logic wkup_detector2_miodio2_qs;
 474:   logic wkup_detector2_miodio2_wd;
 475:   logic wkup_detector2_miodio2_we;
 476:   logic [2:0] wkup_detector3_mode3_qs;
 477:   logic [2:0] wkup_detector3_mode3_wd;
 478:   logic wkup_detector3_mode3_we;
 479:   logic wkup_detector3_filter3_qs;
 480:   logic wkup_detector3_filter3_wd;
 481:   logic wkup_detector3_filter3_we;
 482:   logic wkup_detector3_miodio3_qs;
 483:   logic wkup_detector3_miodio3_wd;
 484:   logic wkup_detector3_miodio3_we;
 485:   logic [2:0] wkup_detector4_mode4_qs;
 486:   logic [2:0] wkup_detector4_mode4_wd;
 487:   logic wkup_detector4_mode4_we;
 488:   logic wkup_detector4_filter4_qs;
 489:   logic wkup_detector4_filter4_wd;
 490:   logic wkup_detector4_filter4_we;
 491:   logic wkup_detector4_miodio4_qs;
 492:   logic wkup_detector4_miodio4_wd;
 493:   logic wkup_detector4_miodio4_we;
 494:   logic [2:0] wkup_detector5_mode5_qs;
 495:   logic [2:0] wkup_detector5_mode5_wd;
 496:   logic wkup_detector5_mode5_we;
 497:   logic wkup_detector5_filter5_qs;
 498:   logic wkup_detector5_filter5_wd;
 499:   logic wkup_detector5_filter5_we;
 500:   logic wkup_detector5_miodio5_qs;
 501:   logic wkup_detector5_miodio5_wd;
 502:   logic wkup_detector5_miodio5_we;
 503:   logic [2:0] wkup_detector6_mode6_qs;
 504:   logic [2:0] wkup_detector6_mode6_wd;
 505:   logic wkup_detector6_mode6_we;
 506:   logic wkup_detector6_filter6_qs;
 507:   logic wkup_detector6_filter6_wd;
 508:   logic wkup_detector6_filter6_we;
 509:   logic wkup_detector6_miodio6_qs;
 510:   logic wkup_detector6_miodio6_wd;
 511:   logic wkup_detector6_miodio6_we;
 512:   logic [2:0] wkup_detector7_mode7_qs;
 513:   logic [2:0] wkup_detector7_mode7_wd;
 514:   logic wkup_detector7_mode7_we;
 515:   logic wkup_detector7_filter7_qs;
 516:   logic wkup_detector7_filter7_wd;
 517:   logic wkup_detector7_filter7_we;
 518:   logic wkup_detector7_miodio7_qs;
 519:   logic wkup_detector7_miodio7_wd;
 520:   logic wkup_detector7_miodio7_we;
 521:   logic [7:0] wkup_detector_cnt_th0_th0_qs;
 522:   logic [7:0] wkup_detector_cnt_th0_th0_wd;
 523:   logic wkup_detector_cnt_th0_th0_we;
 524:   logic [7:0] wkup_detector_cnt_th0_th1_qs;
 525:   logic [7:0] wkup_detector_cnt_th0_th1_wd;
 526:   logic wkup_detector_cnt_th0_th1_we;
 527:   logic [7:0] wkup_detector_cnt_th0_th2_qs;
 528:   logic [7:0] wkup_detector_cnt_th0_th2_wd;
 529:   logic wkup_detector_cnt_th0_th2_we;
 530:   logic [7:0] wkup_detector_cnt_th0_th3_qs;
 531:   logic [7:0] wkup_detector_cnt_th0_th3_wd;
 532:   logic wkup_detector_cnt_th0_th3_we;
 533:   logic [7:0] wkup_detector_cnt_th1_th4_qs;
 534:   logic [7:0] wkup_detector_cnt_th1_th4_wd;
 535:   logic wkup_detector_cnt_th1_th4_we;
 536:   logic [7:0] wkup_detector_cnt_th1_th5_qs;
 537:   logic [7:0] wkup_detector_cnt_th1_th5_wd;
 538:   logic wkup_detector_cnt_th1_th5_we;
 539:   logic [7:0] wkup_detector_cnt_th1_th6_qs;
 540:   logic [7:0] wkup_detector_cnt_th1_th6_wd;
 541:   logic wkup_detector_cnt_th1_th6_we;
 542:   logic [7:0] wkup_detector_cnt_th1_th7_qs;
 543:   logic [7:0] wkup_detector_cnt_th1_th7_wd;
 544:   logic wkup_detector_cnt_th1_th7_we;
 545:   logic [4:0] wkup_detector_padsel0_sel0_qs;
 546:   logic [4:0] wkup_detector_padsel0_sel0_wd;
 547:   logic wkup_detector_padsel0_sel0_we;
 548:   logic [4:0] wkup_detector_padsel0_sel1_qs;
 549:   logic [4:0] wkup_detector_padsel0_sel1_wd;
 550:   logic wkup_detector_padsel0_sel1_we;
 551:   logic [4:0] wkup_detector_padsel0_sel2_qs;
 552:   logic [4:0] wkup_detector_padsel0_sel2_wd;
 553:   logic wkup_detector_padsel0_sel2_we;
 554:   logic [4:0] wkup_detector_padsel0_sel3_qs;
 555:   logic [4:0] wkup_detector_padsel0_sel3_wd;
 556:   logic wkup_detector_padsel0_sel3_we;
 557:   logic [4:0] wkup_detector_padsel0_sel4_qs;
 558:   logic [4:0] wkup_detector_padsel0_sel4_wd;
 559:   logic wkup_detector_padsel0_sel4_we;
 560:   logic [4:0] wkup_detector_padsel0_sel5_qs;
 561:   logic [4:0] wkup_detector_padsel0_sel5_wd;
 562:   logic wkup_detector_padsel0_sel5_we;
 563:   logic [4:0] wkup_detector_padsel1_sel6_qs;
 564:   logic [4:0] wkup_detector_padsel1_sel6_wd;
 565:   logic wkup_detector_padsel1_sel6_we;
 566:   logic [4:0] wkup_detector_padsel1_sel7_qs;
 567:   logic [4:0] wkup_detector_padsel1_sel7_wd;
 568:   logic wkup_detector_padsel1_sel7_we;
 569:   logic wkup_cause_cause0_qs;
 570:   logic wkup_cause_cause0_wd;
 571:   logic wkup_cause_cause0_we;
 572:   logic wkup_cause_cause0_re;
 573:   logic wkup_cause_cause1_qs;
 574:   logic wkup_cause_cause1_wd;
 575:   logic wkup_cause_cause1_we;
 576:   logic wkup_cause_cause1_re;
 577:   logic wkup_cause_cause2_qs;
 578:   logic wkup_cause_cause2_wd;
 579:   logic wkup_cause_cause2_we;
 580:   logic wkup_cause_cause2_re;
 581:   logic wkup_cause_cause3_qs;
 582:   logic wkup_cause_cause3_wd;
 583:   logic wkup_cause_cause3_we;
 584:   logic wkup_cause_cause3_re;
 585:   logic wkup_cause_cause4_qs;
 586:   logic wkup_cause_cause4_wd;
 587:   logic wkup_cause_cause4_we;
 588:   logic wkup_cause_cause4_re;
 589:   logic wkup_cause_cause5_qs;
 590:   logic wkup_cause_cause5_wd;
 591:   logic wkup_cause_cause5_we;
 592:   logic wkup_cause_cause5_re;
 593:   logic wkup_cause_cause6_qs;
 594:   logic wkup_cause_cause6_wd;
 595:   logic wkup_cause_cause6_we;
 596:   logic wkup_cause_cause6_re;
 597:   logic wkup_cause_cause7_qs;
 598:   logic wkup_cause_cause7_wd;
 599:   logic wkup_cause_cause7_we;
 600:   logic wkup_cause_cause7_re;
 601: 
 602:   // Register instances
 603:   // R[regen]: V(False)
 604: 
 605:   prim_subreg #(
 606:     .DW      (1),
 607:     .SWACCESS("W0C"),
 608:     .RESVAL  (1'h1)
 609:   ) u_regen (
 610:     .clk_i   (clk_i    ),
 611:     .rst_ni  (rst_ni  ),
 612: 
 613:     // from register interface
 614:     .we     (regen_we),
 615:     .wd     (regen_wd),
 616: 
 617:     // from internal hardware
 618:     .de     (1'b0),
 619:     .d      ('0  ),
 620: 
 621:     // to internal hardware
 622:     .qe     (),
 623:     .q      (),
 624: 
 625:     // to register interface (read)
 626:     .qs     (regen_qs)
 627:   );
 628: 
 629: 
 630: 
 631:   // Subregister 0 of Multireg periph_insel
 632:   // R[periph_insel0]: V(False)
 633: 
 634:   // F[in0]: 5:0
 635:   prim_subreg #(
 636:     .DW      (6),
 637:     .SWACCESS("RW"),
 638:     .RESVAL  (6'h0)
 639:   ) u_periph_insel0_in0 (
 640:     .clk_i   (clk_i    ),
 641:     .rst_ni  (rst_ni  ),
 642: 
 643:     // from register interface (qualified with register enable)
 644:     .we     (periph_insel0_in0_we & regen_qs),
 645:     .wd     (periph_insel0_in0_wd),
 646: 
 647:     // from internal hardware
 648:     .de     (1'b0),
 649:     .d      ('0  ),
 650: 
 651:     // to internal hardware
 652:     .qe     (),
 653:     .q      (reg2hw.periph_insel[0].q ),
 654: 
 655:     // to register interface (read)
 656:     .qs     (periph_insel0_in0_qs)
 657:   );
 658: 
 659: 
 660:   // F[in1]: 11:6
 661:   prim_subreg #(
 662:     .DW      (6),
 663:     .SWACCESS("RW"),
 664:     .RESVAL  (6'h0)
 665:   ) u_periph_insel0_in1 (
 666:     .clk_i   (clk_i    ),
 667:     .rst_ni  (rst_ni  ),
 668: 
 669:     // from register interface (qualified with register enable)
 670:     .we     (periph_insel0_in1_we & regen_qs),
 671:     .wd     (periph_insel0_in1_wd),
 672: 
 673:     // from internal hardware
 674:     .de     (1'b0),
 675:     .d      ('0  ),
 676: 
 677:     // to internal hardware
 678:     .qe     (),
 679:     .q      (reg2hw.periph_insel[1].q ),
 680: 
 681:     // to register interface (read)
 682:     .qs     (periph_insel0_in1_qs)
 683:   );
 684: 
 685: 
 686:   // F[in2]: 17:12
 687:   prim_subreg #(
 688:     .DW      (6),
 689:     .SWACCESS("RW"),
 690:     .RESVAL  (6'h0)
 691:   ) u_periph_insel0_in2 (
 692:     .clk_i   (clk_i    ),
 693:     .rst_ni  (rst_ni  ),
 694: 
 695:     // from register interface (qualified with register enable)
 696:     .we     (periph_insel0_in2_we & regen_qs),
 697:     .wd     (periph_insel0_in2_wd),
 698: 
 699:     // from internal hardware
 700:     .de     (1'b0),
 701:     .d      ('0  ),
 702: 
 703:     // to internal hardware
 704:     .qe     (),
 705:     .q      (reg2hw.periph_insel[2].q ),
 706: 
 707:     // to register interface (read)
 708:     .qs     (periph_insel0_in2_qs)
 709:   );
 710: 
 711: 
 712:   // F[in3]: 23:18
 713:   prim_subreg #(
 714:     .DW      (6),
 715:     .SWACCESS("RW"),
 716:     .RESVAL  (6'h0)
 717:   ) u_periph_insel0_in3 (
 718:     .clk_i   (clk_i    ),
 719:     .rst_ni  (rst_ni  ),
 720: 
 721:     // from register interface (qualified with register enable)
 722:     .we     (periph_insel0_in3_we & regen_qs),
 723:     .wd     (periph_insel0_in3_wd),
 724: 
 725:     // from internal hardware
 726:     .de     (1'b0),
 727:     .d      ('0  ),
 728: 
 729:     // to internal hardware
 730:     .qe     (),
 731:     .q      (reg2hw.periph_insel[3].q ),
 732: 
 733:     // to register interface (read)
 734:     .qs     (periph_insel0_in3_qs)
 735:   );
 736: 
 737: 
 738:   // F[in4]: 29:24
 739:   prim_subreg #(
 740:     .DW      (6),
 741:     .SWACCESS("RW"),
 742:     .RESVAL  (6'h0)
 743:   ) u_periph_insel0_in4 (
 744:     .clk_i   (clk_i    ),
 745:     .rst_ni  (rst_ni  ),
 746: 
 747:     // from register interface (qualified with register enable)
 748:     .we     (periph_insel0_in4_we & regen_qs),
 749:     .wd     (periph_insel0_in4_wd),
 750: 
 751:     // from internal hardware
 752:     .de     (1'b0),
 753:     .d      ('0  ),
 754: 
 755:     // to internal hardware
 756:     .qe     (),
 757:     .q      (reg2hw.periph_insel[4].q ),
 758: 
 759:     // to register interface (read)
 760:     .qs     (periph_insel0_in4_qs)
 761:   );
 762: 
 763: 
 764:   // Subregister 5 of Multireg periph_insel
 765:   // R[periph_insel1]: V(False)
 766: 
 767:   // F[in5]: 5:0
 768:   prim_subreg #(
 769:     .DW      (6),
 770:     .SWACCESS("RW"),
 771:     .RESVAL  (6'h0)
 772:   ) u_periph_insel1_in5 (
 773:     .clk_i   (clk_i    ),
 774:     .rst_ni  (rst_ni  ),
 775: 
 776:     // from register interface (qualified with register enable)
 777:     .we     (periph_insel1_in5_we & regen_qs),
 778:     .wd     (periph_insel1_in5_wd),
 779: 
 780:     // from internal hardware
 781:     .de     (1'b0),
 782:     .d      ('0  ),
 783: 
 784:     // to internal hardware
 785:     .qe     (),
 786:     .q      (reg2hw.periph_insel[5].q ),
 787: 
 788:     // to register interface (read)
 789:     .qs     (periph_insel1_in5_qs)
 790:   );
 791: 
 792: 
 793:   // F[in6]: 11:6
 794:   prim_subreg #(
 795:     .DW      (6),
 796:     .SWACCESS("RW"),
 797:     .RESVAL  (6'h0)
 798:   ) u_periph_insel1_in6 (
 799:     .clk_i   (clk_i    ),
 800:     .rst_ni  (rst_ni  ),
 801: 
 802:     // from register interface (qualified with register enable)
 803:     .we     (periph_insel1_in6_we & regen_qs),
 804:     .wd     (periph_insel1_in6_wd),
 805: 
 806:     // from internal hardware
 807:     .de     (1'b0),
 808:     .d      ('0  ),
 809: 
 810:     // to internal hardware
 811:     .qe     (),
 812:     .q      (reg2hw.periph_insel[6].q ),
 813: 
 814:     // to register interface (read)
 815:     .qs     (periph_insel1_in6_qs)
 816:   );
 817: 
 818: 
 819:   // F[in7]: 17:12
 820:   prim_subreg #(
 821:     .DW      (6),
 822:     .SWACCESS("RW"),
 823:     .RESVAL  (6'h0)
 824:   ) u_periph_insel1_in7 (
 825:     .clk_i   (clk_i    ),
 826:     .rst_ni  (rst_ni  ),
 827: 
 828:     // from register interface (qualified with register enable)
 829:     .we     (periph_insel1_in7_we & regen_qs),
 830:     .wd     (periph_insel1_in7_wd),
 831: 
 832:     // from internal hardware
 833:     .de     (1'b0),
 834:     .d      ('0  ),
 835: 
 836:     // to internal hardware
 837:     .qe     (),
 838:     .q      (reg2hw.periph_insel[7].q ),
 839: 
 840:     // to register interface (read)
 841:     .qs     (periph_insel1_in7_qs)
 842:   );
 843: 
 844: 
 845:   // F[in8]: 23:18
 846:   prim_subreg #(
 847:     .DW      (6),
 848:     .SWACCESS("RW"),
 849:     .RESVAL  (6'h0)
 850:   ) u_periph_insel1_in8 (
 851:     .clk_i   (clk_i    ),
 852:     .rst_ni  (rst_ni  ),
 853: 
 854:     // from register interface (qualified with register enable)
 855:     .we     (periph_insel1_in8_we & regen_qs),
 856:     .wd     (periph_insel1_in8_wd),
 857: 
 858:     // from internal hardware
 859:     .de     (1'b0),
 860:     .d      ('0  ),
 861: 
 862:     // to internal hardware
 863:     .qe     (),
 864:     .q      (reg2hw.periph_insel[8].q ),
 865: 
 866:     // to register interface (read)
 867:     .qs     (periph_insel1_in8_qs)
 868:   );
 869: 
 870: 
 871:   // F[in9]: 29:24
 872:   prim_subreg #(
 873:     .DW      (6),
 874:     .SWACCESS("RW"),
 875:     .RESVAL  (6'h0)
 876:   ) u_periph_insel1_in9 (
 877:     .clk_i   (clk_i    ),
 878:     .rst_ni  (rst_ni  ),
 879: 
 880:     // from register interface (qualified with register enable)
 881:     .we     (periph_insel1_in9_we & regen_qs),
 882:     .wd     (periph_insel1_in9_wd),
 883: 
 884:     // from internal hardware
 885:     .de     (1'b0),
 886:     .d      ('0  ),
 887: 
 888:     // to internal hardware
 889:     .qe     (),
 890:     .q      (reg2hw.periph_insel[9].q ),
 891: 
 892:     // to register interface (read)
 893:     .qs     (periph_insel1_in9_qs)
 894:   );
 895: 
 896: 
 897:   // Subregister 10 of Multireg periph_insel
 898:   // R[periph_insel2]: V(False)
 899: 
 900:   // F[in10]: 5:0
 901:   prim_subreg #(
 902:     .DW      (6),
 903:     .SWACCESS("RW"),
 904:     .RESVAL  (6'h0)
 905:   ) u_periph_insel2_in10 (
 906:     .clk_i   (clk_i    ),
 907:     .rst_ni  (rst_ni  ),
 908: 
 909:     // from register interface (qualified with register enable)
 910:     .we     (periph_insel2_in10_we & regen_qs),
 911:     .wd     (periph_insel2_in10_wd),
 912: 
 913:     // from internal hardware
 914:     .de     (1'b0),
 915:     .d      ('0  ),
 916: 
 917:     // to internal hardware
 918:     .qe     (),
 919:     .q      (reg2hw.periph_insel[10].q ),
 920: 
 921:     // to register interface (read)
 922:     .qs     (periph_insel2_in10_qs)
 923:   );
 924: 
 925: 
 926:   // F[in11]: 11:6
 927:   prim_subreg #(
 928:     .DW      (6),
 929:     .SWACCESS("RW"),
 930:     .RESVAL  (6'h0)
 931:   ) u_periph_insel2_in11 (
 932:     .clk_i   (clk_i    ),
 933:     .rst_ni  (rst_ni  ),
 934: 
 935:     // from register interface (qualified with register enable)
 936:     .we     (periph_insel2_in11_we & regen_qs),
 937:     .wd     (periph_insel2_in11_wd),
 938: 
 939:     // from internal hardware
 940:     .de     (1'b0),
 941:     .d      ('0  ),
 942: 
 943:     // to internal hardware
 944:     .qe     (),
 945:     .q      (reg2hw.periph_insel[11].q ),
 946: 
 947:     // to register interface (read)
 948:     .qs     (periph_insel2_in11_qs)
 949:   );
 950: 
 951: 
 952:   // F[in12]: 17:12
 953:   prim_subreg #(
 954:     .DW      (6),
 955:     .SWACCESS("RW"),
 956:     .RESVAL  (6'h0)
 957:   ) u_periph_insel2_in12 (
 958:     .clk_i   (clk_i    ),
 959:     .rst_ni  (rst_ni  ),
 960: 
 961:     // from register interface (qualified with register enable)
 962:     .we     (periph_insel2_in12_we & regen_qs),
 963:     .wd     (periph_insel2_in12_wd),
 964: 
 965:     // from internal hardware
 966:     .de     (1'b0),
 967:     .d      ('0  ),
 968: 
 969:     // to internal hardware
 970:     .qe     (),
 971:     .q      (reg2hw.periph_insel[12].q ),
 972: 
 973:     // to register interface (read)
 974:     .qs     (periph_insel2_in12_qs)
 975:   );
 976: 
 977: 
 978:   // F[in13]: 23:18
 979:   prim_subreg #(
 980:     .DW      (6),
 981:     .SWACCESS("RW"),
 982:     .RESVAL  (6'h0)
 983:   ) u_periph_insel2_in13 (
 984:     .clk_i   (clk_i    ),
 985:     .rst_ni  (rst_ni  ),
 986: 
 987:     // from register interface (qualified with register enable)
 988:     .we     (periph_insel2_in13_we & regen_qs),
 989:     .wd     (periph_insel2_in13_wd),
 990: 
 991:     // from internal hardware
 992:     .de     (1'b0),
 993:     .d      ('0  ),
 994: 
 995:     // to internal hardware
 996:     .qe     (),
 997:     .q      (reg2hw.periph_insel[13].q ),
 998: 
 999:     // to register interface (read)
1000:     .qs     (periph_insel2_in13_qs)
1001:   );
1002: 
1003: 
1004:   // F[in14]: 29:24
1005:   prim_subreg #(
1006:     .DW      (6),
1007:     .SWACCESS("RW"),
1008:     .RESVAL  (6'h0)
1009:   ) u_periph_insel2_in14 (
1010:     .clk_i   (clk_i    ),
1011:     .rst_ni  (rst_ni  ),
1012: 
1013:     // from register interface (qualified with register enable)
1014:     .we     (periph_insel2_in14_we & regen_qs),
1015:     .wd     (periph_insel2_in14_wd),
1016: 
1017:     // from internal hardware
1018:     .de     (1'b0),
1019:     .d      ('0  ),
1020: 
1021:     // to internal hardware
1022:     .qe     (),
1023:     .q      (reg2hw.periph_insel[14].q ),
1024: 
1025:     // to register interface (read)
1026:     .qs     (periph_insel2_in14_qs)
1027:   );
1028: 
1029: 
1030:   // Subregister 15 of Multireg periph_insel
1031:   // R[periph_insel3]: V(False)
1032: 
1033:   // F[in15]: 5:0
1034:   prim_subreg #(
1035:     .DW      (6),
1036:     .SWACCESS("RW"),
1037:     .RESVAL  (6'h0)
1038:   ) u_periph_insel3_in15 (
1039:     .clk_i   (clk_i    ),
1040:     .rst_ni  (rst_ni  ),
1041: 
1042:     // from register interface (qualified with register enable)
1043:     .we     (periph_insel3_in15_we & regen_qs),
1044:     .wd     (periph_insel3_in15_wd),
1045: 
1046:     // from internal hardware
1047:     .de     (1'b0),
1048:     .d      ('0  ),
1049: 
1050:     // to internal hardware
1051:     .qe     (),
1052:     .q      (reg2hw.periph_insel[15].q ),
1053: 
1054:     // to register interface (read)
1055:     .qs     (periph_insel3_in15_qs)
1056:   );
1057: 
1058: 
1059:   // F[in16]: 11:6
1060:   prim_subreg #(
1061:     .DW      (6),
1062:     .SWACCESS("RW"),
1063:     .RESVAL  (6'h0)
1064:   ) u_periph_insel3_in16 (
1065:     .clk_i   (clk_i    ),
1066:     .rst_ni  (rst_ni  ),
1067: 
1068:     // from register interface (qualified with register enable)
1069:     .we     (periph_insel3_in16_we & regen_qs),
1070:     .wd     (periph_insel3_in16_wd),
1071: 
1072:     // from internal hardware
1073:     .de     (1'b0),
1074:     .d      ('0  ),
1075: 
1076:     // to internal hardware
1077:     .qe     (),
1078:     .q      (reg2hw.periph_insel[16].q ),
1079: 
1080:     // to register interface (read)
1081:     .qs     (periph_insel3_in16_qs)
1082:   );
1083: 
1084: 
1085:   // F[in17]: 17:12
1086:   prim_subreg #(
1087:     .DW      (6),
1088:     .SWACCESS("RW"),
1089:     .RESVAL  (6'h0)
1090:   ) u_periph_insel3_in17 (
1091:     .clk_i   (clk_i    ),
1092:     .rst_ni  (rst_ni  ),
1093: 
1094:     // from register interface (qualified with register enable)
1095:     .we     (periph_insel3_in17_we & regen_qs),
1096:     .wd     (periph_insel3_in17_wd),
1097: 
1098:     // from internal hardware
1099:     .de     (1'b0),
1100:     .d      ('0  ),
1101: 
1102:     // to internal hardware
1103:     .qe     (),
1104:     .q      (reg2hw.periph_insel[17].q ),
1105: 
1106:     // to register interface (read)
1107:     .qs     (periph_insel3_in17_qs)
1108:   );
1109: 
1110: 
1111:   // F[in18]: 23:18
1112:   prim_subreg #(
1113:     .DW      (6),
1114:     .SWACCESS("RW"),
1115:     .RESVAL  (6'h0)
1116:   ) u_periph_insel3_in18 (
1117:     .clk_i   (clk_i    ),
1118:     .rst_ni  (rst_ni  ),
1119: 
1120:     // from register interface (qualified with register enable)
1121:     .we     (periph_insel3_in18_we & regen_qs),
1122:     .wd     (periph_insel3_in18_wd),
1123: 
1124:     // from internal hardware
1125:     .de     (1'b0),
1126:     .d      ('0  ),
1127: 
1128:     // to internal hardware
1129:     .qe     (),
1130:     .q      (reg2hw.periph_insel[18].q ),
1131: 
1132:     // to register interface (read)
1133:     .qs     (periph_insel3_in18_qs)
1134:   );
1135: 
1136: 
1137:   // F[in19]: 29:24
1138:   prim_subreg #(
1139:     .DW      (6),
1140:     .SWACCESS("RW"),
1141:     .RESVAL  (6'h0)
1142:   ) u_periph_insel3_in19 (
1143:     .clk_i   (clk_i    ),
1144:     .rst_ni  (rst_ni  ),
1145: 
1146:     // from register interface (qualified with register enable)
1147:     .we     (periph_insel3_in19_we & regen_qs),
1148:     .wd     (periph_insel3_in19_wd),
1149: 
1150:     // from internal hardware
1151:     .de     (1'b0),
1152:     .d      ('0  ),
1153: 
1154:     // to internal hardware
1155:     .qe     (),
1156:     .q      (reg2hw.periph_insel[19].q ),
1157: 
1158:     // to register interface (read)
1159:     .qs     (periph_insel3_in19_qs)
1160:   );
1161: 
1162: 
1163:   // Subregister 20 of Multireg periph_insel
1164:   // R[periph_insel4]: V(False)
1165: 
1166:   // F[in20]: 5:0
1167:   prim_subreg #(
1168:     .DW      (6),
1169:     .SWACCESS("RW"),
1170:     .RESVAL  (6'h0)
1171:   ) u_periph_insel4_in20 (
1172:     .clk_i   (clk_i    ),
1173:     .rst_ni  (rst_ni  ),
1174: 
1175:     // from register interface (qualified with register enable)
1176:     .we     (periph_insel4_in20_we & regen_qs),
1177:     .wd     (periph_insel4_in20_wd),
1178: 
1179:     // from internal hardware
1180:     .de     (1'b0),
1181:     .d      ('0  ),
1182: 
1183:     // to internal hardware
1184:     .qe     (),
1185:     .q      (reg2hw.periph_insel[20].q ),
1186: 
1187:     // to register interface (read)
1188:     .qs     (periph_insel4_in20_qs)
1189:   );
1190: 
1191: 
1192:   // F[in21]: 11:6
1193:   prim_subreg #(
1194:     .DW      (6),
1195:     .SWACCESS("RW"),
1196:     .RESVAL  (6'h0)
1197:   ) u_periph_insel4_in21 (
1198:     .clk_i   (clk_i    ),
1199:     .rst_ni  (rst_ni  ),
1200: 
1201:     // from register interface (qualified with register enable)
1202:     .we     (periph_insel4_in21_we & regen_qs),
1203:     .wd     (periph_insel4_in21_wd),
1204: 
1205:     // from internal hardware
1206:     .de     (1'b0),
1207:     .d      ('0  ),
1208: 
1209:     // to internal hardware
1210:     .qe     (),
1211:     .q      (reg2hw.periph_insel[21].q ),
1212: 
1213:     // to register interface (read)
1214:     .qs     (periph_insel4_in21_qs)
1215:   );
1216: 
1217: 
1218:   // F[in22]: 17:12
1219:   prim_subreg #(
1220:     .DW      (6),
1221:     .SWACCESS("RW"),
1222:     .RESVAL  (6'h0)
1223:   ) u_periph_insel4_in22 (
1224:     .clk_i   (clk_i    ),
1225:     .rst_ni  (rst_ni  ),
1226: 
1227:     // from register interface (qualified with register enable)
1228:     .we     (periph_insel4_in22_we & regen_qs),
1229:     .wd     (periph_insel4_in22_wd),
1230: 
1231:     // from internal hardware
1232:     .de     (1'b0),
1233:     .d      ('0  ),
1234: 
1235:     // to internal hardware
1236:     .qe     (),
1237:     .q      (reg2hw.periph_insel[22].q ),
1238: 
1239:     // to register interface (read)
1240:     .qs     (periph_insel4_in22_qs)
1241:   );
1242: 
1243: 
1244:   // F[in23]: 23:18
1245:   prim_subreg #(
1246:     .DW      (6),
1247:     .SWACCESS("RW"),
1248:     .RESVAL  (6'h0)
1249:   ) u_periph_insel4_in23 (
1250:     .clk_i   (clk_i    ),
1251:     .rst_ni  (rst_ni  ),
1252: 
1253:     // from register interface (qualified with register enable)
1254:     .we     (periph_insel4_in23_we & regen_qs),
1255:     .wd     (periph_insel4_in23_wd),
1256: 
1257:     // from internal hardware
1258:     .de     (1'b0),
1259:     .d      ('0  ),
1260: 
1261:     // to internal hardware
1262:     .qe     (),
1263:     .q      (reg2hw.periph_insel[23].q ),
1264: 
1265:     // to register interface (read)
1266:     .qs     (periph_insel4_in23_qs)
1267:   );
1268: 
1269: 
1270:   // F[in24]: 29:24
1271:   prim_subreg #(
1272:     .DW      (6),
1273:     .SWACCESS("RW"),
1274:     .RESVAL  (6'h0)
1275:   ) u_periph_insel4_in24 (
1276:     .clk_i   (clk_i    ),
1277:     .rst_ni  (rst_ni  ),
1278: 
1279:     // from register interface (qualified with register enable)
1280:     .we     (periph_insel4_in24_we & regen_qs),
1281:     .wd     (periph_insel4_in24_wd),
1282: 
1283:     // from internal hardware
1284:     .de     (1'b0),
1285:     .d      ('0  ),
1286: 
1287:     // to internal hardware
1288:     .qe     (),
1289:     .q      (reg2hw.periph_insel[24].q ),
1290: 
1291:     // to register interface (read)
1292:     .qs     (periph_insel4_in24_qs)
1293:   );
1294: 
1295: 
1296:   // Subregister 25 of Multireg periph_insel
1297:   // R[periph_insel5]: V(False)
1298: 
1299:   // F[in25]: 5:0
1300:   prim_subreg #(
1301:     .DW      (6),
1302:     .SWACCESS("RW"),
1303:     .RESVAL  (6'h0)
1304:   ) u_periph_insel5_in25 (
1305:     .clk_i   (clk_i    ),
1306:     .rst_ni  (rst_ni  ),
1307: 
1308:     // from register interface (qualified with register enable)
1309:     .we     (periph_insel5_in25_we & regen_qs),
1310:     .wd     (periph_insel5_in25_wd),
1311: 
1312:     // from internal hardware
1313:     .de     (1'b0),
1314:     .d      ('0  ),
1315: 
1316:     // to internal hardware
1317:     .qe     (),
1318:     .q      (reg2hw.periph_insel[25].q ),
1319: 
1320:     // to register interface (read)
1321:     .qs     (periph_insel5_in25_qs)
1322:   );
1323: 
1324: 
1325:   // F[in26]: 11:6
1326:   prim_subreg #(
1327:     .DW      (6),
1328:     .SWACCESS("RW"),
1329:     .RESVAL  (6'h0)
1330:   ) u_periph_insel5_in26 (
1331:     .clk_i   (clk_i    ),
1332:     .rst_ni  (rst_ni  ),
1333: 
1334:     // from register interface (qualified with register enable)
1335:     .we     (periph_insel5_in26_we & regen_qs),
1336:     .wd     (periph_insel5_in26_wd),
1337: 
1338:     // from internal hardware
1339:     .de     (1'b0),
1340:     .d      ('0  ),
1341: 
1342:     // to internal hardware
1343:     .qe     (),
1344:     .q      (reg2hw.periph_insel[26].q ),
1345: 
1346:     // to register interface (read)
1347:     .qs     (periph_insel5_in26_qs)
1348:   );
1349: 
1350: 
1351:   // F[in27]: 17:12
1352:   prim_subreg #(
1353:     .DW      (6),
1354:     .SWACCESS("RW"),
1355:     .RESVAL  (6'h0)
1356:   ) u_periph_insel5_in27 (
1357:     .clk_i   (clk_i    ),
1358:     .rst_ni  (rst_ni  ),
1359: 
1360:     // from register interface (qualified with register enable)
1361:     .we     (periph_insel5_in27_we & regen_qs),
1362:     .wd     (periph_insel5_in27_wd),
1363: 
1364:     // from internal hardware
1365:     .de     (1'b0),
1366:     .d      ('0  ),
1367: 
1368:     // to internal hardware
1369:     .qe     (),
1370:     .q      (reg2hw.periph_insel[27].q ),
1371: 
1372:     // to register interface (read)
1373:     .qs     (periph_insel5_in27_qs)
1374:   );
1375: 
1376: 
1377:   // F[in28]: 23:18
1378:   prim_subreg #(
1379:     .DW      (6),
1380:     .SWACCESS("RW"),
1381:     .RESVAL  (6'h0)
1382:   ) u_periph_insel5_in28 (
1383:     .clk_i   (clk_i    ),
1384:     .rst_ni  (rst_ni  ),
1385: 
1386:     // from register interface (qualified with register enable)
1387:     .we     (periph_insel5_in28_we & regen_qs),
1388:     .wd     (periph_insel5_in28_wd),
1389: 
1390:     // from internal hardware
1391:     .de     (1'b0),
1392:     .d      ('0  ),
1393: 
1394:     // to internal hardware
1395:     .qe     (),
1396:     .q      (reg2hw.periph_insel[28].q ),
1397: 
1398:     // to register interface (read)
1399:     .qs     (periph_insel5_in28_qs)
1400:   );
1401: 
1402: 
1403:   // F[in29]: 29:24
1404:   prim_subreg #(
1405:     .DW      (6),
1406:     .SWACCESS("RW"),
1407:     .RESVAL  (6'h0)
1408:   ) u_periph_insel5_in29 (
1409:     .clk_i   (clk_i    ),
1410:     .rst_ni  (rst_ni  ),
1411: 
1412:     // from register interface (qualified with register enable)
1413:     .we     (periph_insel5_in29_we & regen_qs),
1414:     .wd     (periph_insel5_in29_wd),
1415: 
1416:     // from internal hardware
1417:     .de     (1'b0),
1418:     .d      ('0  ),
1419: 
1420:     // to internal hardware
1421:     .qe     (),
1422:     .q      (reg2hw.periph_insel[29].q ),
1423: 
1424:     // to register interface (read)
1425:     .qs     (periph_insel5_in29_qs)
1426:   );
1427: 
1428: 
1429:   // Subregister 30 of Multireg periph_insel
1430:   // R[periph_insel6]: V(False)
1431: 
1432:   // F[in30]: 5:0
1433:   prim_subreg #(
1434:     .DW      (6),
1435:     .SWACCESS("RW"),
1436:     .RESVAL  (6'h0)
1437:   ) u_periph_insel6_in30 (
1438:     .clk_i   (clk_i    ),
1439:     .rst_ni  (rst_ni  ),
1440: 
1441:     // from register interface (qualified with register enable)
1442:     .we     (periph_insel6_in30_we & regen_qs),
1443:     .wd     (periph_insel6_in30_wd),
1444: 
1445:     // from internal hardware
1446:     .de     (1'b0),
1447:     .d      ('0  ),
1448: 
1449:     // to internal hardware
1450:     .qe     (),
1451:     .q      (reg2hw.periph_insel[30].q ),
1452: 
1453:     // to register interface (read)
1454:     .qs     (periph_insel6_in30_qs)
1455:   );
1456: 
1457: 
1458:   // F[in31]: 11:6
1459:   prim_subreg #(
1460:     .DW      (6),
1461:     .SWACCESS("RW"),
1462:     .RESVAL  (6'h0)
1463:   ) u_periph_insel6_in31 (
1464:     .clk_i   (clk_i    ),
1465:     .rst_ni  (rst_ni  ),
1466: 
1467:     // from register interface (qualified with register enable)
1468:     .we     (periph_insel6_in31_we & regen_qs),
1469:     .wd     (periph_insel6_in31_wd),
1470: 
1471:     // from internal hardware
1472:     .de     (1'b0),
1473:     .d      ('0  ),
1474: 
1475:     // to internal hardware
1476:     .qe     (),
1477:     .q      (reg2hw.periph_insel[31].q ),
1478: 
1479:     // to register interface (read)
1480:     .qs     (periph_insel6_in31_qs)
1481:   );
1482: 
1483: 
1484: 
1485: 
1486:   // Subregister 0 of Multireg mio_outsel
1487:   // R[mio_outsel0]: V(False)
1488: 
1489:   // F[out0]: 5:0
1490:   prim_subreg #(
1491:     .DW      (6),
1492:     .SWACCESS("RW"),
1493:     .RESVAL  (6'h2)
1494:   ) u_mio_outsel0_out0 (
1495:     .clk_i   (clk_i    ),
1496:     .rst_ni  (rst_ni  ),
1497: 
1498:     // from register interface (qualified with register enable)
1499:     .we     (mio_outsel0_out0_we & regen_qs),
1500:     .wd     (mio_outsel0_out0_wd),
1501: 
1502:     // from internal hardware
1503:     .de     (1'b0),
1504:     .d      ('0  ),
1505: 
1506:     // to internal hardware
1507:     .qe     (),
1508:     .q      (reg2hw.mio_outsel[0].q ),
1509: 
1510:     // to register interface (read)
1511:     .qs     (mio_outsel0_out0_qs)
1512:   );
1513: 
1514: 
1515:   // F[out1]: 11:6
1516:   prim_subreg #(
1517:     .DW      (6),
1518:     .SWACCESS("RW"),
1519:     .RESVAL  (6'h2)
1520:   ) u_mio_outsel0_out1 (
1521:     .clk_i   (clk_i    ),
1522:     .rst_ni  (rst_ni  ),
1523: 
1524:     // from register interface (qualified with register enable)
1525:     .we     (mio_outsel0_out1_we & regen_qs),
1526:     .wd     (mio_outsel0_out1_wd),
1527: 
1528:     // from internal hardware
1529:     .de     (1'b0),
1530:     .d      ('0  ),
1531: 
1532:     // to internal hardware
1533:     .qe     (),
1534:     .q      (reg2hw.mio_outsel[1].q ),
1535: 
1536:     // to register interface (read)
1537:     .qs     (mio_outsel0_out1_qs)
1538:   );
1539: 
1540: 
1541:   // F[out2]: 17:12
1542:   prim_subreg #(
1543:     .DW      (6),
1544:     .SWACCESS("RW"),
1545:     .RESVAL  (6'h2)
1546:   ) u_mio_outsel0_out2 (
1547:     .clk_i   (clk_i    ),
1548:     .rst_ni  (rst_ni  ),
1549: 
1550:     // from register interface (qualified with register enable)
1551:     .we     (mio_outsel0_out2_we & regen_qs),
1552:     .wd     (mio_outsel0_out2_wd),
1553: 
1554:     // from internal hardware
1555:     .de     (1'b0),
1556:     .d      ('0  ),
1557: 
1558:     // to internal hardware
1559:     .qe     (),
1560:     .q      (reg2hw.mio_outsel[2].q ),
1561: 
1562:     // to register interface (read)
1563:     .qs     (mio_outsel0_out2_qs)
1564:   );
1565: 
1566: 
1567:   // F[out3]: 23:18
1568:   prim_subreg #(
1569:     .DW      (6),
1570:     .SWACCESS("RW"),
1571:     .RESVAL  (6'h2)
1572:   ) u_mio_outsel0_out3 (
1573:     .clk_i   (clk_i    ),
1574:     .rst_ni  (rst_ni  ),
1575: 
1576:     // from register interface (qualified with register enable)
1577:     .we     (mio_outsel0_out3_we & regen_qs),
1578:     .wd     (mio_outsel0_out3_wd),
1579: 
1580:     // from internal hardware
1581:     .de     (1'b0),
1582:     .d      ('0  ),
1583: 
1584:     // to internal hardware
1585:     .qe     (),
1586:     .q      (reg2hw.mio_outsel[3].q ),
1587: 
1588:     // to register interface (read)
1589:     .qs     (mio_outsel0_out3_qs)
1590:   );
1591: 
1592: 
1593:   // F[out4]: 29:24
1594:   prim_subreg #(
1595:     .DW      (6),
1596:     .SWACCESS("RW"),
1597:     .RESVAL  (6'h2)
1598:   ) u_mio_outsel0_out4 (
1599:     .clk_i   (clk_i    ),
1600:     .rst_ni  (rst_ni  ),
1601: 
1602:     // from register interface (qualified with register enable)
1603:     .we     (mio_outsel0_out4_we & regen_qs),
1604:     .wd     (mio_outsel0_out4_wd),
1605: 
1606:     // from internal hardware
1607:     .de     (1'b0),
1608:     .d      ('0  ),
1609: 
1610:     // to internal hardware
1611:     .qe     (),
1612:     .q      (reg2hw.mio_outsel[4].q ),
1613: 
1614:     // to register interface (read)
1615:     .qs     (mio_outsel0_out4_qs)
1616:   );
1617: 
1618: 
1619:   // Subregister 5 of Multireg mio_outsel
1620:   // R[mio_outsel1]: V(False)
1621: 
1622:   // F[out5]: 5:0
1623:   prim_subreg #(
1624:     .DW      (6),
1625:     .SWACCESS("RW"),
1626:     .RESVAL  (6'h2)
1627:   ) u_mio_outsel1_out5 (
1628:     .clk_i   (clk_i    ),
1629:     .rst_ni  (rst_ni  ),
1630: 
1631:     // from register interface (qualified with register enable)
1632:     .we     (mio_outsel1_out5_we & regen_qs),
1633:     .wd     (mio_outsel1_out5_wd),
1634: 
1635:     // from internal hardware
1636:     .de     (1'b0),
1637:     .d      ('0  ),
1638: 
1639:     // to internal hardware
1640:     .qe     (),
1641:     .q      (reg2hw.mio_outsel[5].q ),
1642: 
1643:     // to register interface (read)
1644:     .qs     (mio_outsel1_out5_qs)
1645:   );
1646: 
1647: 
1648:   // F[out6]: 11:6
1649:   prim_subreg #(
1650:     .DW      (6),
1651:     .SWACCESS("RW"),
1652:     .RESVAL  (6'h2)
1653:   ) u_mio_outsel1_out6 (
1654:     .clk_i   (clk_i    ),
1655:     .rst_ni  (rst_ni  ),
1656: 
1657:     // from register interface (qualified with register enable)
1658:     .we     (mio_outsel1_out6_we & regen_qs),
1659:     .wd     (mio_outsel1_out6_wd),
1660: 
1661:     // from internal hardware
1662:     .de     (1'b0),
1663:     .d      ('0  ),
1664: 
1665:     // to internal hardware
1666:     .qe     (),
1667:     .q      (reg2hw.mio_outsel[6].q ),
1668: 
1669:     // to register interface (read)
1670:     .qs     (mio_outsel1_out6_qs)
1671:   );
1672: 
1673: 
1674:   // F[out7]: 17:12
1675:   prim_subreg #(
1676:     .DW      (6),
1677:     .SWACCESS("RW"),
1678:     .RESVAL  (6'h2)
1679:   ) u_mio_outsel1_out7 (
1680:     .clk_i   (clk_i    ),
1681:     .rst_ni  (rst_ni  ),
1682: 
1683:     // from register interface (qualified with register enable)
1684:     .we     (mio_outsel1_out7_we & regen_qs),
1685:     .wd     (mio_outsel1_out7_wd),
1686: 
1687:     // from internal hardware
1688:     .de     (1'b0),
1689:     .d      ('0  ),
1690: 
1691:     // to internal hardware
1692:     .qe     (),
1693:     .q      (reg2hw.mio_outsel[7].q ),
1694: 
1695:     // to register interface (read)
1696:     .qs     (mio_outsel1_out7_qs)
1697:   );
1698: 
1699: 
1700:   // F[out8]: 23:18
1701:   prim_subreg #(
1702:     .DW      (6),
1703:     .SWACCESS("RW"),
1704:     .RESVAL  (6'h2)
1705:   ) u_mio_outsel1_out8 (
1706:     .clk_i   (clk_i    ),
1707:     .rst_ni  (rst_ni  ),
1708: 
1709:     // from register interface (qualified with register enable)
1710:     .we     (mio_outsel1_out8_we & regen_qs),
1711:     .wd     (mio_outsel1_out8_wd),
1712: 
1713:     // from internal hardware
1714:     .de     (1'b0),
1715:     .d      ('0  ),
1716: 
1717:     // to internal hardware
1718:     .qe     (),
1719:     .q      (reg2hw.mio_outsel[8].q ),
1720: 
1721:     // to register interface (read)
1722:     .qs     (mio_outsel1_out8_qs)
1723:   );
1724: 
1725: 
1726:   // F[out9]: 29:24
1727:   prim_subreg #(
1728:     .DW      (6),
1729:     .SWACCESS("RW"),
1730:     .RESVAL  (6'h2)
1731:   ) u_mio_outsel1_out9 (
1732:     .clk_i   (clk_i    ),
1733:     .rst_ni  (rst_ni  ),
1734: 
1735:     // from register interface (qualified with register enable)
1736:     .we     (mio_outsel1_out9_we & regen_qs),
1737:     .wd     (mio_outsel1_out9_wd),
1738: 
1739:     // from internal hardware
1740:     .de     (1'b0),
1741:     .d      ('0  ),
1742: 
1743:     // to internal hardware
1744:     .qe     (),
1745:     .q      (reg2hw.mio_outsel[9].q ),
1746: 
1747:     // to register interface (read)
1748:     .qs     (mio_outsel1_out9_qs)
1749:   );
1750: 
1751: 
1752:   // Subregister 10 of Multireg mio_outsel
1753:   // R[mio_outsel2]: V(False)
1754: 
1755:   // F[out10]: 5:0
1756:   prim_subreg #(
1757:     .DW      (6),
1758:     .SWACCESS("RW"),
1759:     .RESVAL  (6'h2)
1760:   ) u_mio_outsel2_out10 (
1761:     .clk_i   (clk_i    ),
1762:     .rst_ni  (rst_ni  ),
1763: 
1764:     // from register interface (qualified with register enable)
1765:     .we     (mio_outsel2_out10_we & regen_qs),
1766:     .wd     (mio_outsel2_out10_wd),
1767: 
1768:     // from internal hardware
1769:     .de     (1'b0),
1770:     .d      ('0  ),
1771: 
1772:     // to internal hardware
1773:     .qe     (),
1774:     .q      (reg2hw.mio_outsel[10].q ),
1775: 
1776:     // to register interface (read)
1777:     .qs     (mio_outsel2_out10_qs)
1778:   );
1779: 
1780: 
1781:   // F[out11]: 11:6
1782:   prim_subreg #(
1783:     .DW      (6),
1784:     .SWACCESS("RW"),
1785:     .RESVAL  (6'h2)
1786:   ) u_mio_outsel2_out11 (
1787:     .clk_i   (clk_i    ),
1788:     .rst_ni  (rst_ni  ),
1789: 
1790:     // from register interface (qualified with register enable)
1791:     .we     (mio_outsel2_out11_we & regen_qs),
1792:     .wd     (mio_outsel2_out11_wd),
1793: 
1794:     // from internal hardware
1795:     .de     (1'b0),
1796:     .d      ('0  ),
1797: 
1798:     // to internal hardware
1799:     .qe     (),
1800:     .q      (reg2hw.mio_outsel[11].q ),
1801: 
1802:     // to register interface (read)
1803:     .qs     (mio_outsel2_out11_qs)
1804:   );
1805: 
1806: 
1807:   // F[out12]: 17:12
1808:   prim_subreg #(
1809:     .DW      (6),
1810:     .SWACCESS("RW"),
1811:     .RESVAL  (6'h2)
1812:   ) u_mio_outsel2_out12 (
1813:     .clk_i   (clk_i    ),
1814:     .rst_ni  (rst_ni  ),
1815: 
1816:     // from register interface (qualified with register enable)
1817:     .we     (mio_outsel2_out12_we & regen_qs),
1818:     .wd     (mio_outsel2_out12_wd),
1819: 
1820:     // from internal hardware
1821:     .de     (1'b0),
1822:     .d      ('0  ),
1823: 
1824:     // to internal hardware
1825:     .qe     (),
1826:     .q      (reg2hw.mio_outsel[12].q ),
1827: 
1828:     // to register interface (read)
1829:     .qs     (mio_outsel2_out12_qs)
1830:   );
1831: 
1832: 
1833:   // F[out13]: 23:18
1834:   prim_subreg #(
1835:     .DW      (6),
1836:     .SWACCESS("RW"),
1837:     .RESVAL  (6'h2)
1838:   ) u_mio_outsel2_out13 (
1839:     .clk_i   (clk_i    ),
1840:     .rst_ni  (rst_ni  ),
1841: 
1842:     // from register interface (qualified with register enable)
1843:     .we     (mio_outsel2_out13_we & regen_qs),
1844:     .wd     (mio_outsel2_out13_wd),
1845: 
1846:     // from internal hardware
1847:     .de     (1'b0),
1848:     .d      ('0  ),
1849: 
1850:     // to internal hardware
1851:     .qe     (),
1852:     .q      (reg2hw.mio_outsel[13].q ),
1853: 
1854:     // to register interface (read)
1855:     .qs     (mio_outsel2_out13_qs)
1856:   );
1857: 
1858: 
1859:   // F[out14]: 29:24
1860:   prim_subreg #(
1861:     .DW      (6),
1862:     .SWACCESS("RW"),
1863:     .RESVAL  (6'h2)
1864:   ) u_mio_outsel2_out14 (
1865:     .clk_i   (clk_i    ),
1866:     .rst_ni  (rst_ni  ),
1867: 
1868:     // from register interface (qualified with register enable)
1869:     .we     (mio_outsel2_out14_we & regen_qs),
1870:     .wd     (mio_outsel2_out14_wd),
1871: 
1872:     // from internal hardware
1873:     .de     (1'b0),
1874:     .d      ('0  ),
1875: 
1876:     // to internal hardware
1877:     .qe     (),
1878:     .q      (reg2hw.mio_outsel[14].q ),
1879: 
1880:     // to register interface (read)
1881:     .qs     (mio_outsel2_out14_qs)
1882:   );
1883: 
1884: 
1885:   // Subregister 15 of Multireg mio_outsel
1886:   // R[mio_outsel3]: V(False)
1887: 
1888:   // F[out15]: 5:0
1889:   prim_subreg #(
1890:     .DW      (6),
1891:     .SWACCESS("RW"),
1892:     .RESVAL  (6'h2)
1893:   ) u_mio_outsel3_out15 (
1894:     .clk_i   (clk_i    ),
1895:     .rst_ni  (rst_ni  ),
1896: 
1897:     // from register interface (qualified with register enable)
1898:     .we     (mio_outsel3_out15_we & regen_qs),
1899:     .wd     (mio_outsel3_out15_wd),
1900: 
1901:     // from internal hardware
1902:     .de     (1'b0),
1903:     .d      ('0  ),
1904: 
1905:     // to internal hardware
1906:     .qe     (),
1907:     .q      (reg2hw.mio_outsel[15].q ),
1908: 
1909:     // to register interface (read)
1910:     .qs     (mio_outsel3_out15_qs)
1911:   );
1912: 
1913: 
1914:   // F[out16]: 11:6
1915:   prim_subreg #(
1916:     .DW      (6),
1917:     .SWACCESS("RW"),
1918:     .RESVAL  (6'h2)
1919:   ) u_mio_outsel3_out16 (
1920:     .clk_i   (clk_i    ),
1921:     .rst_ni  (rst_ni  ),
1922: 
1923:     // from register interface (qualified with register enable)
1924:     .we     (mio_outsel3_out16_we & regen_qs),
1925:     .wd     (mio_outsel3_out16_wd),
1926: 
1927:     // from internal hardware
1928:     .de     (1'b0),
1929:     .d      ('0  ),
1930: 
1931:     // to internal hardware
1932:     .qe     (),
1933:     .q      (reg2hw.mio_outsel[16].q ),
1934: 
1935:     // to register interface (read)
1936:     .qs     (mio_outsel3_out16_qs)
1937:   );
1938: 
1939: 
1940:   // F[out17]: 17:12
1941:   prim_subreg #(
1942:     .DW      (6),
1943:     .SWACCESS("RW"),
1944:     .RESVAL  (6'h2)
1945:   ) u_mio_outsel3_out17 (
1946:     .clk_i   (clk_i    ),
1947:     .rst_ni  (rst_ni  ),
1948: 
1949:     // from register interface (qualified with register enable)
1950:     .we     (mio_outsel3_out17_we & regen_qs),
1951:     .wd     (mio_outsel3_out17_wd),
1952: 
1953:     // from internal hardware
1954:     .de     (1'b0),
1955:     .d      ('0  ),
1956: 
1957:     // to internal hardware
1958:     .qe     (),
1959:     .q      (reg2hw.mio_outsel[17].q ),
1960: 
1961:     // to register interface (read)
1962:     .qs     (mio_outsel3_out17_qs)
1963:   );
1964: 
1965: 
1966:   // F[out18]: 23:18
1967:   prim_subreg #(
1968:     .DW      (6),
1969:     .SWACCESS("RW"),
1970:     .RESVAL  (6'h2)
1971:   ) u_mio_outsel3_out18 (
1972:     .clk_i   (clk_i    ),
1973:     .rst_ni  (rst_ni  ),
1974: 
1975:     // from register interface (qualified with register enable)
1976:     .we     (mio_outsel3_out18_we & regen_qs),
1977:     .wd     (mio_outsel3_out18_wd),
1978: 
1979:     // from internal hardware
1980:     .de     (1'b0),
1981:     .d      ('0  ),
1982: 
1983:     // to internal hardware
1984:     .qe     (),
1985:     .q      (reg2hw.mio_outsel[18].q ),
1986: 
1987:     // to register interface (read)
1988:     .qs     (mio_outsel3_out18_qs)
1989:   );
1990: 
1991: 
1992:   // F[out19]: 29:24
1993:   prim_subreg #(
1994:     .DW      (6),
1995:     .SWACCESS("RW"),
1996:     .RESVAL  (6'h2)
1997:   ) u_mio_outsel3_out19 (
1998:     .clk_i   (clk_i    ),
1999:     .rst_ni  (rst_ni  ),
2000: 
2001:     // from register interface (qualified with register enable)
2002:     .we     (mio_outsel3_out19_we & regen_qs),
2003:     .wd     (mio_outsel3_out19_wd),
2004: 
2005:     // from internal hardware
2006:     .de     (1'b0),
2007:     .d      ('0  ),
2008: 
2009:     // to internal hardware
2010:     .qe     (),
2011:     .q      (reg2hw.mio_outsel[19].q ),
2012: 
2013:     // to register interface (read)
2014:     .qs     (mio_outsel3_out19_qs)
2015:   );
2016: 
2017: 
2018:   // Subregister 20 of Multireg mio_outsel
2019:   // R[mio_outsel4]: V(False)
2020: 
2021:   // F[out20]: 5:0
2022:   prim_subreg #(
2023:     .DW      (6),
2024:     .SWACCESS("RW"),
2025:     .RESVAL  (6'h2)
2026:   ) u_mio_outsel4_out20 (
2027:     .clk_i   (clk_i    ),
2028:     .rst_ni  (rst_ni  ),
2029: 
2030:     // from register interface (qualified with register enable)
2031:     .we     (mio_outsel4_out20_we & regen_qs),
2032:     .wd     (mio_outsel4_out20_wd),
2033: 
2034:     // from internal hardware
2035:     .de     (1'b0),
2036:     .d      ('0  ),
2037: 
2038:     // to internal hardware
2039:     .qe     (),
2040:     .q      (reg2hw.mio_outsel[20].q ),
2041: 
2042:     // to register interface (read)
2043:     .qs     (mio_outsel4_out20_qs)
2044:   );
2045: 
2046: 
2047:   // F[out21]: 11:6
2048:   prim_subreg #(
2049:     .DW      (6),
2050:     .SWACCESS("RW"),
2051:     .RESVAL  (6'h2)
2052:   ) u_mio_outsel4_out21 (
2053:     .clk_i   (clk_i    ),
2054:     .rst_ni  (rst_ni  ),
2055: 
2056:     // from register interface (qualified with register enable)
2057:     .we     (mio_outsel4_out21_we & regen_qs),
2058:     .wd     (mio_outsel4_out21_wd),
2059: 
2060:     // from internal hardware
2061:     .de     (1'b0),
2062:     .d      ('0  ),
2063: 
2064:     // to internal hardware
2065:     .qe     (),
2066:     .q      (reg2hw.mio_outsel[21].q ),
2067: 
2068:     // to register interface (read)
2069:     .qs     (mio_outsel4_out21_qs)
2070:   );
2071: 
2072: 
2073:   // F[out22]: 17:12
2074:   prim_subreg #(
2075:     .DW      (6),
2076:     .SWACCESS("RW"),
2077:     .RESVAL  (6'h2)
2078:   ) u_mio_outsel4_out22 (
2079:     .clk_i   (clk_i    ),
2080:     .rst_ni  (rst_ni  ),
2081: 
2082:     // from register interface (qualified with register enable)
2083:     .we     (mio_outsel4_out22_we & regen_qs),
2084:     .wd     (mio_outsel4_out22_wd),
2085: 
2086:     // from internal hardware
2087:     .de     (1'b0),
2088:     .d      ('0  ),
2089: 
2090:     // to internal hardware
2091:     .qe     (),
2092:     .q      (reg2hw.mio_outsel[22].q ),
2093: 
2094:     // to register interface (read)
2095:     .qs     (mio_outsel4_out22_qs)
2096:   );
2097: 
2098: 
2099:   // F[out23]: 23:18
2100:   prim_subreg #(
2101:     .DW      (6),
2102:     .SWACCESS("RW"),
2103:     .RESVAL  (6'h2)
2104:   ) u_mio_outsel4_out23 (
2105:     .clk_i   (clk_i    ),
2106:     .rst_ni  (rst_ni  ),
2107: 
2108:     // from register interface (qualified with register enable)
2109:     .we     (mio_outsel4_out23_we & regen_qs),
2110:     .wd     (mio_outsel4_out23_wd),
2111: 
2112:     // from internal hardware
2113:     .de     (1'b0),
2114:     .d      ('0  ),
2115: 
2116:     // to internal hardware
2117:     .qe     (),
2118:     .q      (reg2hw.mio_outsel[23].q ),
2119: 
2120:     // to register interface (read)
2121:     .qs     (mio_outsel4_out23_qs)
2122:   );
2123: 
2124: 
2125:   // F[out24]: 29:24
2126:   prim_subreg #(
2127:     .DW      (6),
2128:     .SWACCESS("RW"),
2129:     .RESVAL  (6'h2)
2130:   ) u_mio_outsel4_out24 (
2131:     .clk_i   (clk_i    ),
2132:     .rst_ni  (rst_ni  ),
2133: 
2134:     // from register interface (qualified with register enable)
2135:     .we     (mio_outsel4_out24_we & regen_qs),
2136:     .wd     (mio_outsel4_out24_wd),
2137: 
2138:     // from internal hardware
2139:     .de     (1'b0),
2140:     .d      ('0  ),
2141: 
2142:     // to internal hardware
2143:     .qe     (),
2144:     .q      (reg2hw.mio_outsel[24].q ),
2145: 
2146:     // to register interface (read)
2147:     .qs     (mio_outsel4_out24_qs)
2148:   );
2149: 
2150: 
2151:   // Subregister 25 of Multireg mio_outsel
2152:   // R[mio_outsel5]: V(False)
2153: 
2154:   // F[out25]: 5:0
2155:   prim_subreg #(
2156:     .DW      (6),
2157:     .SWACCESS("RW"),
2158:     .RESVAL  (6'h2)
2159:   ) u_mio_outsel5_out25 (
2160:     .clk_i   (clk_i    ),
2161:     .rst_ni  (rst_ni  ),
2162: 
2163:     // from register interface (qualified with register enable)
2164:     .we     (mio_outsel5_out25_we & regen_qs),
2165:     .wd     (mio_outsel5_out25_wd),
2166: 
2167:     // from internal hardware
2168:     .de     (1'b0),
2169:     .d      ('0  ),
2170: 
2171:     // to internal hardware
2172:     .qe     (),
2173:     .q      (reg2hw.mio_outsel[25].q ),
2174: 
2175:     // to register interface (read)
2176:     .qs     (mio_outsel5_out25_qs)
2177:   );
2178: 
2179: 
2180:   // F[out26]: 11:6
2181:   prim_subreg #(
2182:     .DW      (6),
2183:     .SWACCESS("RW"),
2184:     .RESVAL  (6'h2)
2185:   ) u_mio_outsel5_out26 (
2186:     .clk_i   (clk_i    ),
2187:     .rst_ni  (rst_ni  ),
2188: 
2189:     // from register interface (qualified with register enable)
2190:     .we     (mio_outsel5_out26_we & regen_qs),
2191:     .wd     (mio_outsel5_out26_wd),
2192: 
2193:     // from internal hardware
2194:     .de     (1'b0),
2195:     .d      ('0  ),
2196: 
2197:     // to internal hardware
2198:     .qe     (),
2199:     .q      (reg2hw.mio_outsel[26].q ),
2200: 
2201:     // to register interface (read)
2202:     .qs     (mio_outsel5_out26_qs)
2203:   );
2204: 
2205: 
2206:   // F[out27]: 17:12
2207:   prim_subreg #(
2208:     .DW      (6),
2209:     .SWACCESS("RW"),
2210:     .RESVAL  (6'h2)
2211:   ) u_mio_outsel5_out27 (
2212:     .clk_i   (clk_i    ),
2213:     .rst_ni  (rst_ni  ),
2214: 
2215:     // from register interface (qualified with register enable)
2216:     .we     (mio_outsel5_out27_we & regen_qs),
2217:     .wd     (mio_outsel5_out27_wd),
2218: 
2219:     // from internal hardware
2220:     .de     (1'b0),
2221:     .d      ('0  ),
2222: 
2223:     // to internal hardware
2224:     .qe     (),
2225:     .q      (reg2hw.mio_outsel[27].q ),
2226: 
2227:     // to register interface (read)
2228:     .qs     (mio_outsel5_out27_qs)
2229:   );
2230: 
2231: 
2232:   // F[out28]: 23:18
2233:   prim_subreg #(
2234:     .DW      (6),
2235:     .SWACCESS("RW"),
2236:     .RESVAL  (6'h2)
2237:   ) u_mio_outsel5_out28 (
2238:     .clk_i   (clk_i    ),
2239:     .rst_ni  (rst_ni  ),
2240: 
2241:     // from register interface (qualified with register enable)
2242:     .we     (mio_outsel5_out28_we & regen_qs),
2243:     .wd     (mio_outsel5_out28_wd),
2244: 
2245:     // from internal hardware
2246:     .de     (1'b0),
2247:     .d      ('0  ),
2248: 
2249:     // to internal hardware
2250:     .qe     (),
2251:     .q      (reg2hw.mio_outsel[28].q ),
2252: 
2253:     // to register interface (read)
2254:     .qs     (mio_outsel5_out28_qs)
2255:   );
2256: 
2257: 
2258:   // F[out29]: 29:24
2259:   prim_subreg #(
2260:     .DW      (6),
2261:     .SWACCESS("RW"),
2262:     .RESVAL  (6'h2)
2263:   ) u_mio_outsel5_out29 (
2264:     .clk_i   (clk_i    ),
2265:     .rst_ni  (rst_ni  ),
2266: 
2267:     // from register interface (qualified with register enable)
2268:     .we     (mio_outsel5_out29_we & regen_qs),
2269:     .wd     (mio_outsel5_out29_wd),
2270: 
2271:     // from internal hardware
2272:     .de     (1'b0),
2273:     .d      ('0  ),
2274: 
2275:     // to internal hardware
2276:     .qe     (),
2277:     .q      (reg2hw.mio_outsel[29].q ),
2278: 
2279:     // to register interface (read)
2280:     .qs     (mio_outsel5_out29_qs)
2281:   );
2282: 
2283: 
2284:   // Subregister 30 of Multireg mio_outsel
2285:   // R[mio_outsel6]: V(False)
2286: 
2287:   // F[out30]: 5:0
2288:   prim_subreg #(
2289:     .DW      (6),
2290:     .SWACCESS("RW"),
2291:     .RESVAL  (6'h2)
2292:   ) u_mio_outsel6_out30 (
2293:     .clk_i   (clk_i    ),
2294:     .rst_ni  (rst_ni  ),
2295: 
2296:     // from register interface (qualified with register enable)
2297:     .we     (mio_outsel6_out30_we & regen_qs),
2298:     .wd     (mio_outsel6_out30_wd),
2299: 
2300:     // from internal hardware
2301:     .de     (1'b0),
2302:     .d      ('0  ),
2303: 
2304:     // to internal hardware
2305:     .qe     (),
2306:     .q      (reg2hw.mio_outsel[30].q ),
2307: 
2308:     // to register interface (read)
2309:     .qs     (mio_outsel6_out30_qs)
2310:   );
2311: 
2312: 
2313:   // F[out31]: 11:6
2314:   prim_subreg #(
2315:     .DW      (6),
2316:     .SWACCESS("RW"),
2317:     .RESVAL  (6'h2)
2318:   ) u_mio_outsel6_out31 (
2319:     .clk_i   (clk_i    ),
2320:     .rst_ni  (rst_ni  ),
2321: 
2322:     // from register interface (qualified with register enable)
2323:     .we     (mio_outsel6_out31_we & regen_qs),
2324:     .wd     (mio_outsel6_out31_wd),
2325: 
2326:     // from internal hardware
2327:     .de     (1'b0),
2328:     .d      ('0  ),
2329: 
2330:     // to internal hardware
2331:     .qe     (),
2332:     .q      (reg2hw.mio_outsel[31].q ),
2333: 
2334:     // to register interface (read)
2335:     .qs     (mio_outsel6_out31_qs)
2336:   );
2337: 
2338: 
2339: 
2340: 
2341:   // Subregister 0 of Multireg mio_out_sleep_val
2342:   // R[mio_out_sleep_val0]: V(False)
2343: 
2344:   // F[out0]: 1:0
2345:   prim_subreg #(
2346:     .DW      (2),
2347:     .SWACCESS("RW"),
2348:     .RESVAL  (2'h2)
2349:   ) u_mio_out_sleep_val0_out0 (
2350:     .clk_i   (clk_i    ),
2351:     .rst_ni  (rst_ni  ),
2352: 
2353:     // from register interface (qualified with register enable)
2354:     .we     (mio_out_sleep_val0_out0_we & regen_qs),
2355:     .wd     (mio_out_sleep_val0_out0_wd),
2356: 
2357:     // from internal hardware
2358:     .de     (1'b0),
2359:     .d      ('0  ),
2360: 
2361:     // to internal hardware
2362:     .qe     (),
2363:     .q      (reg2hw.mio_out_sleep_val[0].q ),
2364: 
2365:     // to register interface (read)
2366:     .qs     (mio_out_sleep_val0_out0_qs)
2367:   );
2368: 
2369: 
2370:   // F[out1]: 3:2
2371:   prim_subreg #(
2372:     .DW      (2),
2373:     .SWACCESS("RW"),
2374:     .RESVAL  (2'h2)
2375:   ) u_mio_out_sleep_val0_out1 (
2376:     .clk_i   (clk_i    ),
2377:     .rst_ni  (rst_ni  ),
2378: 
2379:     // from register interface (qualified with register enable)
2380:     .we     (mio_out_sleep_val0_out1_we & regen_qs),
2381:     .wd     (mio_out_sleep_val0_out1_wd),
2382: 
2383:     // from internal hardware
2384:     .de     (1'b0),
2385:     .d      ('0  ),
2386: 
2387:     // to internal hardware
2388:     .qe     (),
2389:     .q      (reg2hw.mio_out_sleep_val[1].q ),
2390: 
2391:     // to register interface (read)
2392:     .qs     (mio_out_sleep_val0_out1_qs)
2393:   );
2394: 
2395: 
2396:   // F[out2]: 5:4
2397:   prim_subreg #(
2398:     .DW      (2),
2399:     .SWACCESS("RW"),
2400:     .RESVAL  (2'h2)
2401:   ) u_mio_out_sleep_val0_out2 (
2402:     .clk_i   (clk_i    ),
2403:     .rst_ni  (rst_ni  ),
2404: 
2405:     // from register interface (qualified with register enable)
2406:     .we     (mio_out_sleep_val0_out2_we & regen_qs),
2407:     .wd     (mio_out_sleep_val0_out2_wd),
2408: 
2409:     // from internal hardware
2410:     .de     (1'b0),
2411:     .d      ('0  ),
2412: 
2413:     // to internal hardware
2414:     .qe     (),
2415:     .q      (reg2hw.mio_out_sleep_val[2].q ),
2416: 
2417:     // to register interface (read)
2418:     .qs     (mio_out_sleep_val0_out2_qs)
2419:   );
2420: 
2421: 
2422:   // F[out3]: 7:6
2423:   prim_subreg #(
2424:     .DW      (2),
2425:     .SWACCESS("RW"),
2426:     .RESVAL  (2'h2)
2427:   ) u_mio_out_sleep_val0_out3 (
2428:     .clk_i   (clk_i    ),
2429:     .rst_ni  (rst_ni  ),
2430: 
2431:     // from register interface (qualified with register enable)
2432:     .we     (mio_out_sleep_val0_out3_we & regen_qs),
2433:     .wd     (mio_out_sleep_val0_out3_wd),
2434: 
2435:     // from internal hardware
2436:     .de     (1'b0),
2437:     .d      ('0  ),
2438: 
2439:     // to internal hardware
2440:     .qe     (),
2441:     .q      (reg2hw.mio_out_sleep_val[3].q ),
2442: 
2443:     // to register interface (read)
2444:     .qs     (mio_out_sleep_val0_out3_qs)
2445:   );
2446: 
2447: 
2448:   // F[out4]: 9:8
2449:   prim_subreg #(
2450:     .DW      (2),
2451:     .SWACCESS("RW"),
2452:     .RESVAL  (2'h2)
2453:   ) u_mio_out_sleep_val0_out4 (
2454:     .clk_i   (clk_i    ),
2455:     .rst_ni  (rst_ni  ),
2456: 
2457:     // from register interface (qualified with register enable)
2458:     .we     (mio_out_sleep_val0_out4_we & regen_qs),
2459:     .wd     (mio_out_sleep_val0_out4_wd),
2460: 
2461:     // from internal hardware
2462:     .de     (1'b0),
2463:     .d      ('0  ),
2464: 
2465:     // to internal hardware
2466:     .qe     (),
2467:     .q      (reg2hw.mio_out_sleep_val[4].q ),
2468: 
2469:     // to register interface (read)
2470:     .qs     (mio_out_sleep_val0_out4_qs)
2471:   );
2472: 
2473: 
2474:   // F[out5]: 11:10
2475:   prim_subreg #(
2476:     .DW      (2),
2477:     .SWACCESS("RW"),
2478:     .RESVAL  (2'h2)
2479:   ) u_mio_out_sleep_val0_out5 (
2480:     .clk_i   (clk_i    ),
2481:     .rst_ni  (rst_ni  ),
2482: 
2483:     // from register interface (qualified with register enable)
2484:     .we     (mio_out_sleep_val0_out5_we & regen_qs),
2485:     .wd     (mio_out_sleep_val0_out5_wd),
2486: 
2487:     // from internal hardware
2488:     .de     (1'b0),
2489:     .d      ('0  ),
2490: 
2491:     // to internal hardware
2492:     .qe     (),
2493:     .q      (reg2hw.mio_out_sleep_val[5].q ),
2494: 
2495:     // to register interface (read)
2496:     .qs     (mio_out_sleep_val0_out5_qs)
2497:   );
2498: 
2499: 
2500:   // F[out6]: 13:12
2501:   prim_subreg #(
2502:     .DW      (2),
2503:     .SWACCESS("RW"),
2504:     .RESVAL  (2'h2)
2505:   ) u_mio_out_sleep_val0_out6 (
2506:     .clk_i   (clk_i    ),
2507:     .rst_ni  (rst_ni  ),
2508: 
2509:     // from register interface (qualified with register enable)
2510:     .we     (mio_out_sleep_val0_out6_we & regen_qs),
2511:     .wd     (mio_out_sleep_val0_out6_wd),
2512: 
2513:     // from internal hardware
2514:     .de     (1'b0),
2515:     .d      ('0  ),
2516: 
2517:     // to internal hardware
2518:     .qe     (),
2519:     .q      (reg2hw.mio_out_sleep_val[6].q ),
2520: 
2521:     // to register interface (read)
2522:     .qs     (mio_out_sleep_val0_out6_qs)
2523:   );
2524: 
2525: 
2526:   // F[out7]: 15:14
2527:   prim_subreg #(
2528:     .DW      (2),
2529:     .SWACCESS("RW"),
2530:     .RESVAL  (2'h2)
2531:   ) u_mio_out_sleep_val0_out7 (
2532:     .clk_i   (clk_i    ),
2533:     .rst_ni  (rst_ni  ),
2534: 
2535:     // from register interface (qualified with register enable)
2536:     .we     (mio_out_sleep_val0_out7_we & regen_qs),
2537:     .wd     (mio_out_sleep_val0_out7_wd),
2538: 
2539:     // from internal hardware
2540:     .de     (1'b0),
2541:     .d      ('0  ),
2542: 
2543:     // to internal hardware
2544:     .qe     (),
2545:     .q      (reg2hw.mio_out_sleep_val[7].q ),
2546: 
2547:     // to register interface (read)
2548:     .qs     (mio_out_sleep_val0_out7_qs)
2549:   );
2550: 
2551: 
2552:   // F[out8]: 17:16
2553:   prim_subreg #(
2554:     .DW      (2),
2555:     .SWACCESS("RW"),
2556:     .RESVAL  (2'h2)
2557:   ) u_mio_out_sleep_val0_out8 (
2558:     .clk_i   (clk_i    ),
2559:     .rst_ni  (rst_ni  ),
2560: 
2561:     // from register interface (qualified with register enable)
2562:     .we     (mio_out_sleep_val0_out8_we & regen_qs),
2563:     .wd     (mio_out_sleep_val0_out8_wd),
2564: 
2565:     // from internal hardware
2566:     .de     (1'b0),
2567:     .d      ('0  ),
2568: 
2569:     // to internal hardware
2570:     .qe     (),
2571:     .q      (reg2hw.mio_out_sleep_val[8].q ),
2572: 
2573:     // to register interface (read)
2574:     .qs     (mio_out_sleep_val0_out8_qs)
2575:   );
2576: 
2577: 
2578:   // F[out9]: 19:18
2579:   prim_subreg #(
2580:     .DW      (2),
2581:     .SWACCESS("RW"),
2582:     .RESVAL  (2'h2)
2583:   ) u_mio_out_sleep_val0_out9 (
2584:     .clk_i   (clk_i    ),
2585:     .rst_ni  (rst_ni  ),
2586: 
2587:     // from register interface (qualified with register enable)
2588:     .we     (mio_out_sleep_val0_out9_we & regen_qs),
2589:     .wd     (mio_out_sleep_val0_out9_wd),
2590: 
2591:     // from internal hardware
2592:     .de     (1'b0),
2593:     .d      ('0  ),
2594: 
2595:     // to internal hardware
2596:     .qe     (),
2597:     .q      (reg2hw.mio_out_sleep_val[9].q ),
2598: 
2599:     // to register interface (read)
2600:     .qs     (mio_out_sleep_val0_out9_qs)
2601:   );
2602: 
2603: 
2604:   // F[out10]: 21:20
2605:   prim_subreg #(
2606:     .DW      (2),
2607:     .SWACCESS("RW"),
2608:     .RESVAL  (2'h2)
2609:   ) u_mio_out_sleep_val0_out10 (
2610:     .clk_i   (clk_i    ),
2611:     .rst_ni  (rst_ni  ),
2612: 
2613:     // from register interface (qualified with register enable)
2614:     .we     (mio_out_sleep_val0_out10_we & regen_qs),
2615:     .wd     (mio_out_sleep_val0_out10_wd),
2616: 
2617:     // from internal hardware
2618:     .de     (1'b0),
2619:     .d      ('0  ),
2620: 
2621:     // to internal hardware
2622:     .qe     (),
2623:     .q      (reg2hw.mio_out_sleep_val[10].q ),
2624: 
2625:     // to register interface (read)
2626:     .qs     (mio_out_sleep_val0_out10_qs)
2627:   );
2628: 
2629: 
2630:   // F[out11]: 23:22
2631:   prim_subreg #(
2632:     .DW      (2),
2633:     .SWACCESS("RW"),
2634:     .RESVAL  (2'h2)
2635:   ) u_mio_out_sleep_val0_out11 (
2636:     .clk_i   (clk_i    ),
2637:     .rst_ni  (rst_ni  ),
2638: 
2639:     // from register interface (qualified with register enable)
2640:     .we     (mio_out_sleep_val0_out11_we & regen_qs),
2641:     .wd     (mio_out_sleep_val0_out11_wd),
2642: 
2643:     // from internal hardware
2644:     .de     (1'b0),
2645:     .d      ('0  ),
2646: 
2647:     // to internal hardware
2648:     .qe     (),
2649:     .q      (reg2hw.mio_out_sleep_val[11].q ),
2650: 
2651:     // to register interface (read)
2652:     .qs     (mio_out_sleep_val0_out11_qs)
2653:   );
2654: 
2655: 
2656:   // F[out12]: 25:24
2657:   prim_subreg #(
2658:     .DW      (2),
2659:     .SWACCESS("RW"),
2660:     .RESVAL  (2'h2)
2661:   ) u_mio_out_sleep_val0_out12 (
2662:     .clk_i   (clk_i    ),
2663:     .rst_ni  (rst_ni  ),
2664: 
2665:     // from register interface (qualified with register enable)
2666:     .we     (mio_out_sleep_val0_out12_we & regen_qs),
2667:     .wd     (mio_out_sleep_val0_out12_wd),
2668: 
2669:     // from internal hardware
2670:     .de     (1'b0),
2671:     .d      ('0  ),
2672: 
2673:     // to internal hardware
2674:     .qe     (),
2675:     .q      (reg2hw.mio_out_sleep_val[12].q ),
2676: 
2677:     // to register interface (read)
2678:     .qs     (mio_out_sleep_val0_out12_qs)
2679:   );
2680: 
2681: 
2682:   // F[out13]: 27:26
2683:   prim_subreg #(
2684:     .DW      (2),
2685:     .SWACCESS("RW"),
2686:     .RESVAL  (2'h2)
2687:   ) u_mio_out_sleep_val0_out13 (
2688:     .clk_i   (clk_i    ),
2689:     .rst_ni  (rst_ni  ),
2690: 
2691:     // from register interface (qualified with register enable)
2692:     .we     (mio_out_sleep_val0_out13_we & regen_qs),
2693:     .wd     (mio_out_sleep_val0_out13_wd),
2694: 
2695:     // from internal hardware
2696:     .de     (1'b0),
2697:     .d      ('0  ),
2698: 
2699:     // to internal hardware
2700:     .qe     (),
2701:     .q      (reg2hw.mio_out_sleep_val[13].q ),
2702: 
2703:     // to register interface (read)
2704:     .qs     (mio_out_sleep_val0_out13_qs)
2705:   );
2706: 
2707: 
2708:   // F[out14]: 29:28
2709:   prim_subreg #(
2710:     .DW      (2),
2711:     .SWACCESS("RW"),
2712:     .RESVAL  (2'h2)
2713:   ) u_mio_out_sleep_val0_out14 (
2714:     .clk_i   (clk_i    ),
2715:     .rst_ni  (rst_ni  ),
2716: 
2717:     // from register interface (qualified with register enable)
2718:     .we     (mio_out_sleep_val0_out14_we & regen_qs),
2719:     .wd     (mio_out_sleep_val0_out14_wd),
2720: 
2721:     // from internal hardware
2722:     .de     (1'b0),
2723:     .d      ('0  ),
2724: 
2725:     // to internal hardware
2726:     .qe     (),
2727:     .q      (reg2hw.mio_out_sleep_val[14].q ),
2728: 
2729:     // to register interface (read)
2730:     .qs     (mio_out_sleep_val0_out14_qs)
2731:   );
2732: 
2733: 
2734:   // F[out15]: 31:30
2735:   prim_subreg #(
2736:     .DW      (2),
2737:     .SWACCESS("RW"),
2738:     .RESVAL  (2'h2)
2739:   ) u_mio_out_sleep_val0_out15 (
2740:     .clk_i   (clk_i    ),
2741:     .rst_ni  (rst_ni  ),
2742: 
2743:     // from register interface (qualified with register enable)
2744:     .we     (mio_out_sleep_val0_out15_we & regen_qs),
2745:     .wd     (mio_out_sleep_val0_out15_wd),
2746: 
2747:     // from internal hardware
2748:     .de     (1'b0),
2749:     .d      ('0  ),
2750: 
2751:     // to internal hardware
2752:     .qe     (),
2753:     .q      (reg2hw.mio_out_sleep_val[15].q ),
2754: 
2755:     // to register interface (read)
2756:     .qs     (mio_out_sleep_val0_out15_qs)
2757:   );
2758: 
2759: 
2760:   // Subregister 16 of Multireg mio_out_sleep_val
2761:   // R[mio_out_sleep_val1]: V(False)
2762: 
2763:   // F[out16]: 1:0
2764:   prim_subreg #(
2765:     .DW      (2),
2766:     .SWACCESS("RW"),
2767:     .RESVAL  (2'h2)
2768:   ) u_mio_out_sleep_val1_out16 (
2769:     .clk_i   (clk_i    ),
2770:     .rst_ni  (rst_ni  ),
2771: 
2772:     // from register interface (qualified with register enable)
2773:     .we     (mio_out_sleep_val1_out16_we & regen_qs),
2774:     .wd     (mio_out_sleep_val1_out16_wd),
2775: 
2776:     // from internal hardware
2777:     .de     (1'b0),
2778:     .d      ('0  ),
2779: 
2780:     // to internal hardware
2781:     .qe     (),
2782:     .q      (reg2hw.mio_out_sleep_val[16].q ),
2783: 
2784:     // to register interface (read)
2785:     .qs     (mio_out_sleep_val1_out16_qs)
2786:   );
2787: 
2788: 
2789:   // F[out17]: 3:2
2790:   prim_subreg #(
2791:     .DW      (2),
2792:     .SWACCESS("RW"),
2793:     .RESVAL  (2'h2)
2794:   ) u_mio_out_sleep_val1_out17 (
2795:     .clk_i   (clk_i    ),
2796:     .rst_ni  (rst_ni  ),
2797: 
2798:     // from register interface (qualified with register enable)
2799:     .we     (mio_out_sleep_val1_out17_we & regen_qs),
2800:     .wd     (mio_out_sleep_val1_out17_wd),
2801: 
2802:     // from internal hardware
2803:     .de     (1'b0),
2804:     .d      ('0  ),
2805: 
2806:     // to internal hardware
2807:     .qe     (),
2808:     .q      (reg2hw.mio_out_sleep_val[17].q ),
2809: 
2810:     // to register interface (read)
2811:     .qs     (mio_out_sleep_val1_out17_qs)
2812:   );
2813: 
2814: 
2815:   // F[out18]: 5:4
2816:   prim_subreg #(
2817:     .DW      (2),
2818:     .SWACCESS("RW"),
2819:     .RESVAL  (2'h2)
2820:   ) u_mio_out_sleep_val1_out18 (
2821:     .clk_i   (clk_i    ),
2822:     .rst_ni  (rst_ni  ),
2823: 
2824:     // from register interface (qualified with register enable)
2825:     .we     (mio_out_sleep_val1_out18_we & regen_qs),
2826:     .wd     (mio_out_sleep_val1_out18_wd),
2827: 
2828:     // from internal hardware
2829:     .de     (1'b0),
2830:     .d      ('0  ),
2831: 
2832:     // to internal hardware
2833:     .qe     (),
2834:     .q      (reg2hw.mio_out_sleep_val[18].q ),
2835: 
2836:     // to register interface (read)
2837:     .qs     (mio_out_sleep_val1_out18_qs)
2838:   );
2839: 
2840: 
2841:   // F[out19]: 7:6
2842:   prim_subreg #(
2843:     .DW      (2),
2844:     .SWACCESS("RW"),
2845:     .RESVAL  (2'h2)
2846:   ) u_mio_out_sleep_val1_out19 (
2847:     .clk_i   (clk_i    ),
2848:     .rst_ni  (rst_ni  ),
2849: 
2850:     // from register interface (qualified with register enable)
2851:     .we     (mio_out_sleep_val1_out19_we & regen_qs),
2852:     .wd     (mio_out_sleep_val1_out19_wd),
2853: 
2854:     // from internal hardware
2855:     .de     (1'b0),
2856:     .d      ('0  ),
2857: 
2858:     // to internal hardware
2859:     .qe     (),
2860:     .q      (reg2hw.mio_out_sleep_val[19].q ),
2861: 
2862:     // to register interface (read)
2863:     .qs     (mio_out_sleep_val1_out19_qs)
2864:   );
2865: 
2866: 
2867:   // F[out20]: 9:8
2868:   prim_subreg #(
2869:     .DW      (2),
2870:     .SWACCESS("RW"),
2871:     .RESVAL  (2'h2)
2872:   ) u_mio_out_sleep_val1_out20 (
2873:     .clk_i   (clk_i    ),
2874:     .rst_ni  (rst_ni  ),
2875: 
2876:     // from register interface (qualified with register enable)
2877:     .we     (mio_out_sleep_val1_out20_we & regen_qs),
2878:     .wd     (mio_out_sleep_val1_out20_wd),
2879: 
2880:     // from internal hardware
2881:     .de     (1'b0),
2882:     .d      ('0  ),
2883: 
2884:     // to internal hardware
2885:     .qe     (),
2886:     .q      (reg2hw.mio_out_sleep_val[20].q ),
2887: 
2888:     // to register interface (read)
2889:     .qs     (mio_out_sleep_val1_out20_qs)
2890:   );
2891: 
2892: 
2893:   // F[out21]: 11:10
2894:   prim_subreg #(
2895:     .DW      (2),
2896:     .SWACCESS("RW"),
2897:     .RESVAL  (2'h2)
2898:   ) u_mio_out_sleep_val1_out21 (
2899:     .clk_i   (clk_i    ),
2900:     .rst_ni  (rst_ni  ),
2901: 
2902:     // from register interface (qualified with register enable)
2903:     .we     (mio_out_sleep_val1_out21_we & regen_qs),
2904:     .wd     (mio_out_sleep_val1_out21_wd),
2905: 
2906:     // from internal hardware
2907:     .de     (1'b0),
2908:     .d      ('0  ),
2909: 
2910:     // to internal hardware
2911:     .qe     (),
2912:     .q      (reg2hw.mio_out_sleep_val[21].q ),
2913: 
2914:     // to register interface (read)
2915:     .qs     (mio_out_sleep_val1_out21_qs)
2916:   );
2917: 
2918: 
2919:   // F[out22]: 13:12
2920:   prim_subreg #(
2921:     .DW      (2),
2922:     .SWACCESS("RW"),
2923:     .RESVAL  (2'h2)
2924:   ) u_mio_out_sleep_val1_out22 (
2925:     .clk_i   (clk_i    ),
2926:     .rst_ni  (rst_ni  ),
2927: 
2928:     // from register interface (qualified with register enable)
2929:     .we     (mio_out_sleep_val1_out22_we & regen_qs),
2930:     .wd     (mio_out_sleep_val1_out22_wd),
2931: 
2932:     // from internal hardware
2933:     .de     (1'b0),
2934:     .d      ('0  ),
2935: 
2936:     // to internal hardware
2937:     .qe     (),
2938:     .q      (reg2hw.mio_out_sleep_val[22].q ),
2939: 
2940:     // to register interface (read)
2941:     .qs     (mio_out_sleep_val1_out22_qs)
2942:   );
2943: 
2944: 
2945:   // F[out23]: 15:14
2946:   prim_subreg #(
2947:     .DW      (2),
2948:     .SWACCESS("RW"),
2949:     .RESVAL  (2'h2)
2950:   ) u_mio_out_sleep_val1_out23 (
2951:     .clk_i   (clk_i    ),
2952:     .rst_ni  (rst_ni  ),
2953: 
2954:     // from register interface (qualified with register enable)
2955:     .we     (mio_out_sleep_val1_out23_we & regen_qs),
2956:     .wd     (mio_out_sleep_val1_out23_wd),
2957: 
2958:     // from internal hardware
2959:     .de     (1'b0),
2960:     .d      ('0  ),
2961: 
2962:     // to internal hardware
2963:     .qe     (),
2964:     .q      (reg2hw.mio_out_sleep_val[23].q ),
2965: 
2966:     // to register interface (read)
2967:     .qs     (mio_out_sleep_val1_out23_qs)
2968:   );
2969: 
2970: 
2971:   // F[out24]: 17:16
2972:   prim_subreg #(
2973:     .DW      (2),
2974:     .SWACCESS("RW"),
2975:     .RESVAL  (2'h2)
2976:   ) u_mio_out_sleep_val1_out24 (
2977:     .clk_i   (clk_i    ),
2978:     .rst_ni  (rst_ni  ),
2979: 
2980:     // from register interface (qualified with register enable)
2981:     .we     (mio_out_sleep_val1_out24_we & regen_qs),
2982:     .wd     (mio_out_sleep_val1_out24_wd),
2983: 
2984:     // from internal hardware
2985:     .de     (1'b0),
2986:     .d      ('0  ),
2987: 
2988:     // to internal hardware
2989:     .qe     (),
2990:     .q      (reg2hw.mio_out_sleep_val[24].q ),
2991: 
2992:     // to register interface (read)
2993:     .qs     (mio_out_sleep_val1_out24_qs)
2994:   );
2995: 
2996: 
2997:   // F[out25]: 19:18
2998:   prim_subreg #(
2999:     .DW      (2),
3000:     .SWACCESS("RW"),
3001:     .RESVAL  (2'h2)
3002:   ) u_mio_out_sleep_val1_out25 (
3003:     .clk_i   (clk_i    ),
3004:     .rst_ni  (rst_ni  ),
3005: 
3006:     // from register interface (qualified with register enable)
3007:     .we     (mio_out_sleep_val1_out25_we & regen_qs),
3008:     .wd     (mio_out_sleep_val1_out25_wd),
3009: 
3010:     // from internal hardware
3011:     .de     (1'b0),
3012:     .d      ('0  ),
3013: 
3014:     // to internal hardware
3015:     .qe     (),
3016:     .q      (reg2hw.mio_out_sleep_val[25].q ),
3017: 
3018:     // to register interface (read)
3019:     .qs     (mio_out_sleep_val1_out25_qs)
3020:   );
3021: 
3022: 
3023:   // F[out26]: 21:20
3024:   prim_subreg #(
3025:     .DW      (2),
3026:     .SWACCESS("RW"),
3027:     .RESVAL  (2'h2)
3028:   ) u_mio_out_sleep_val1_out26 (
3029:     .clk_i   (clk_i    ),
3030:     .rst_ni  (rst_ni  ),
3031: 
3032:     // from register interface (qualified with register enable)
3033:     .we     (mio_out_sleep_val1_out26_we & regen_qs),
3034:     .wd     (mio_out_sleep_val1_out26_wd),
3035: 
3036:     // from internal hardware
3037:     .de     (1'b0),
3038:     .d      ('0  ),
3039: 
3040:     // to internal hardware
3041:     .qe     (),
3042:     .q      (reg2hw.mio_out_sleep_val[26].q ),
3043: 
3044:     // to register interface (read)
3045:     .qs     (mio_out_sleep_val1_out26_qs)
3046:   );
3047: 
3048: 
3049:   // F[out27]: 23:22
3050:   prim_subreg #(
3051:     .DW      (2),
3052:     .SWACCESS("RW"),
3053:     .RESVAL  (2'h2)
3054:   ) u_mio_out_sleep_val1_out27 (
3055:     .clk_i   (clk_i    ),
3056:     .rst_ni  (rst_ni  ),
3057: 
3058:     // from register interface (qualified with register enable)
3059:     .we     (mio_out_sleep_val1_out27_we & regen_qs),
3060:     .wd     (mio_out_sleep_val1_out27_wd),
3061: 
3062:     // from internal hardware
3063:     .de     (1'b0),
3064:     .d      ('0  ),
3065: 
3066:     // to internal hardware
3067:     .qe     (),
3068:     .q      (reg2hw.mio_out_sleep_val[27].q ),
3069: 
3070:     // to register interface (read)
3071:     .qs     (mio_out_sleep_val1_out27_qs)
3072:   );
3073: 
3074: 
3075:   // F[out28]: 25:24
3076:   prim_subreg #(
3077:     .DW      (2),
3078:     .SWACCESS("RW"),
3079:     .RESVAL  (2'h2)
3080:   ) u_mio_out_sleep_val1_out28 (
3081:     .clk_i   (clk_i    ),
3082:     .rst_ni  (rst_ni  ),
3083: 
3084:     // from register interface (qualified with register enable)
3085:     .we     (mio_out_sleep_val1_out28_we & regen_qs),
3086:     .wd     (mio_out_sleep_val1_out28_wd),
3087: 
3088:     // from internal hardware
3089:     .de     (1'b0),
3090:     .d      ('0  ),
3091: 
3092:     // to internal hardware
3093:     .qe     (),
3094:     .q      (reg2hw.mio_out_sleep_val[28].q ),
3095: 
3096:     // to register interface (read)
3097:     .qs     (mio_out_sleep_val1_out28_qs)
3098:   );
3099: 
3100: 
3101:   // F[out29]: 27:26
3102:   prim_subreg #(
3103:     .DW      (2),
3104:     .SWACCESS("RW"),
3105:     .RESVAL  (2'h2)
3106:   ) u_mio_out_sleep_val1_out29 (
3107:     .clk_i   (clk_i    ),
3108:     .rst_ni  (rst_ni  ),
3109: 
3110:     // from register interface (qualified with register enable)
3111:     .we     (mio_out_sleep_val1_out29_we & regen_qs),
3112:     .wd     (mio_out_sleep_val1_out29_wd),
3113: 
3114:     // from internal hardware
3115:     .de     (1'b0),
3116:     .d      ('0  ),
3117: 
3118:     // to internal hardware
3119:     .qe     (),
3120:     .q      (reg2hw.mio_out_sleep_val[29].q ),
3121: 
3122:     // to register interface (read)
3123:     .qs     (mio_out_sleep_val1_out29_qs)
3124:   );
3125: 
3126: 
3127:   // F[out30]: 29:28
3128:   prim_subreg #(
3129:     .DW      (2),
3130:     .SWACCESS("RW"),
3131:     .RESVAL  (2'h2)
3132:   ) u_mio_out_sleep_val1_out30 (
3133:     .clk_i   (clk_i    ),
3134:     .rst_ni  (rst_ni  ),
3135: 
3136:     // from register interface (qualified with register enable)
3137:     .we     (mio_out_sleep_val1_out30_we & regen_qs),
3138:     .wd     (mio_out_sleep_val1_out30_wd),
3139: 
3140:     // from internal hardware
3141:     .de     (1'b0),
3142:     .d      ('0  ),
3143: 
3144:     // to internal hardware
3145:     .qe     (),
3146:     .q      (reg2hw.mio_out_sleep_val[30].q ),
3147: 
3148:     // to register interface (read)
3149:     .qs     (mio_out_sleep_val1_out30_qs)
3150:   );
3151: 
3152: 
3153:   // F[out31]: 31:30
3154:   prim_subreg #(
3155:     .DW      (2),
3156:     .SWACCESS("RW"),
3157:     .RESVAL  (2'h2)
3158:   ) u_mio_out_sleep_val1_out31 (
3159:     .clk_i   (clk_i    ),
3160:     .rst_ni  (rst_ni  ),
3161: 
3162:     // from register interface (qualified with register enable)
3163:     .we     (mio_out_sleep_val1_out31_we & regen_qs),
3164:     .wd     (mio_out_sleep_val1_out31_wd),
3165: 
3166:     // from internal hardware
3167:     .de     (1'b0),
3168:     .d      ('0  ),
3169: 
3170:     // to internal hardware
3171:     .qe     (),
3172:     .q      (reg2hw.mio_out_sleep_val[31].q ),
3173: 
3174:     // to register interface (read)
3175:     .qs     (mio_out_sleep_val1_out31_qs)
3176:   );
3177: 
3178: 
3179: 
3180: 
3181:   // Subregister 0 of Multireg dio_out_sleep_val
3182:   // R[dio_out_sleep_val]: V(True)
3183: 
3184:   // F[out0]: 1:0
3185:   prim_subreg_ext #(
3186:     .DW    (2)
3187:   ) u_dio_out_sleep_val_out0 (
3188:     .re     (dio_out_sleep_val_out0_re),
3189:     // qualified with register enable
3190:     .we     (dio_out_sleep_val_out0_we & regen_qs),
3191:     .wd     (dio_out_sleep_val_out0_wd),
3192:     .d      (hw2reg.dio_out_sleep_val[0].d),
3193:     .qre    (),
3194:     .qe     (reg2hw.dio_out_sleep_val[0].qe),
3195:     .q      (reg2hw.dio_out_sleep_val[0].q ),
3196:     .qs     (dio_out_sleep_val_out0_qs)
3197:   );
3198: 
3199: 
3200:   // F[out1]: 3:2
3201:   prim_subreg_ext #(
3202:     .DW    (2)
3203:   ) u_dio_out_sleep_val_out1 (
3204:     .re     (dio_out_sleep_val_out1_re),
3205:     // qualified with register enable
3206:     .we     (dio_out_sleep_val_out1_we & regen_qs),
3207:     .wd     (dio_out_sleep_val_out1_wd),
3208:     .d      (hw2reg.dio_out_sleep_val[1].d),
3209:     .qre    (),
3210:     .qe     (reg2hw.dio_out_sleep_val[1].qe),
3211:     .q      (reg2hw.dio_out_sleep_val[1].q ),
3212:     .qs     (dio_out_sleep_val_out1_qs)
3213:   );
3214: 
3215: 
3216:   // F[out2]: 5:4
3217:   prim_subreg_ext #(
3218:     .DW    (2)
3219:   ) u_dio_out_sleep_val_out2 (
3220:     .re     (dio_out_sleep_val_out2_re),
3221:     // qualified with register enable
3222:     .we     (dio_out_sleep_val_out2_we & regen_qs),
3223:     .wd     (dio_out_sleep_val_out2_wd),
3224:     .d      (hw2reg.dio_out_sleep_val[2].d),
3225:     .qre    (),
3226:     .qe     (reg2hw.dio_out_sleep_val[2].qe),
3227:     .q      (reg2hw.dio_out_sleep_val[2].q ),
3228:     .qs     (dio_out_sleep_val_out2_qs)
3229:   );
3230: 
3231: 
3232:   // F[out3]: 7:6
3233:   prim_subreg_ext #(
3234:     .DW    (2)
3235:   ) u_dio_out_sleep_val_out3 (
3236:     .re     (dio_out_sleep_val_out3_re),
3237:     // qualified with register enable
3238:     .we     (dio_out_sleep_val_out3_we & regen_qs),
3239:     .wd     (dio_out_sleep_val_out3_wd),
3240:     .d      (hw2reg.dio_out_sleep_val[3].d),
3241:     .qre    (),
3242:     .qe     (reg2hw.dio_out_sleep_val[3].qe),
3243:     .q      (reg2hw.dio_out_sleep_val[3].q ),
3244:     .qs     (dio_out_sleep_val_out3_qs)
3245:   );
3246: 
3247: 
3248:   // F[out4]: 9:8
3249:   prim_subreg_ext #(
3250:     .DW    (2)
3251:   ) u_dio_out_sleep_val_out4 (
3252:     .re     (dio_out_sleep_val_out4_re),
3253:     // qualified with register enable
3254:     .we     (dio_out_sleep_val_out4_we & regen_qs),
3255:     .wd     (dio_out_sleep_val_out4_wd),
3256:     .d      (hw2reg.dio_out_sleep_val[4].d),
3257:     .qre    (),
3258:     .qe     (reg2hw.dio_out_sleep_val[4].qe),
3259:     .q      (reg2hw.dio_out_sleep_val[4].q ),
3260:     .qs     (dio_out_sleep_val_out4_qs)
3261:   );
3262: 
3263: 
3264:   // F[out5]: 11:10
3265:   prim_subreg_ext #(
3266:     .DW    (2)
3267:   ) u_dio_out_sleep_val_out5 (
3268:     .re     (dio_out_sleep_val_out5_re),
3269:     // qualified with register enable
3270:     .we     (dio_out_sleep_val_out5_we & regen_qs),
3271:     .wd     (dio_out_sleep_val_out5_wd),
3272:     .d      (hw2reg.dio_out_sleep_val[5].d),
3273:     .qre    (),
3274:     .qe     (reg2hw.dio_out_sleep_val[5].qe),
3275:     .q      (reg2hw.dio_out_sleep_val[5].q ),
3276:     .qs     (dio_out_sleep_val_out5_qs)
3277:   );
3278: 
3279: 
3280:   // F[out6]: 13:12
3281:   prim_subreg_ext #(
3282:     .DW    (2)
3283:   ) u_dio_out_sleep_val_out6 (
3284:     .re     (dio_out_sleep_val_out6_re),
3285:     // qualified with register enable
3286:     .we     (dio_out_sleep_val_out6_we & regen_qs),
3287:     .wd     (dio_out_sleep_val_out6_wd),
3288:     .d      (hw2reg.dio_out_sleep_val[6].d),
3289:     .qre    (),
3290:     .qe     (reg2hw.dio_out_sleep_val[6].qe),
3291:     .q      (reg2hw.dio_out_sleep_val[6].q ),
3292:     .qs     (dio_out_sleep_val_out6_qs)
3293:   );
3294: 
3295: 
3296:   // F[out7]: 15:14
3297:   prim_subreg_ext #(
3298:     .DW    (2)
3299:   ) u_dio_out_sleep_val_out7 (
3300:     .re     (dio_out_sleep_val_out7_re),
3301:     // qualified with register enable
3302:     .we     (dio_out_sleep_val_out7_we & regen_qs),
3303:     .wd     (dio_out_sleep_val_out7_wd),
3304:     .d      (hw2reg.dio_out_sleep_val[7].d),
3305:     .qre    (),
3306:     .qe     (reg2hw.dio_out_sleep_val[7].qe),
3307:     .q      (reg2hw.dio_out_sleep_val[7].q ),
3308:     .qs     (dio_out_sleep_val_out7_qs)
3309:   );
3310: 
3311: 
3312:   // F[out8]: 17:16
3313:   prim_subreg_ext #(
3314:     .DW    (2)
3315:   ) u_dio_out_sleep_val_out8 (
3316:     .re     (dio_out_sleep_val_out8_re),
3317:     // qualified with register enable
3318:     .we     (dio_out_sleep_val_out8_we & regen_qs),
3319:     .wd     (dio_out_sleep_val_out8_wd),
3320:     .d      (hw2reg.dio_out_sleep_val[8].d),
3321:     .qre    (),
3322:     .qe     (reg2hw.dio_out_sleep_val[8].qe),
3323:     .q      (reg2hw.dio_out_sleep_val[8].q ),
3324:     .qs     (dio_out_sleep_val_out8_qs)
3325:   );
3326: 
3327: 
3328:   // F[out9]: 19:18
3329:   prim_subreg_ext #(
3330:     .DW    (2)
3331:   ) u_dio_out_sleep_val_out9 (
3332:     .re     (dio_out_sleep_val_out9_re),
3333:     // qualified with register enable
3334:     .we     (dio_out_sleep_val_out9_we & regen_qs),
3335:     .wd     (dio_out_sleep_val_out9_wd),
3336:     .d      (hw2reg.dio_out_sleep_val[9].d),
3337:     .qre    (),
3338:     .qe     (reg2hw.dio_out_sleep_val[9].qe),
3339:     .q      (reg2hw.dio_out_sleep_val[9].q ),
3340:     .qs     (dio_out_sleep_val_out9_qs)
3341:   );
3342: 
3343: 
3344:   // F[out10]: 21:20
3345:   prim_subreg_ext #(
3346:     .DW    (2)
3347:   ) u_dio_out_sleep_val_out10 (
3348:     .re     (dio_out_sleep_val_out10_re),
3349:     // qualified with register enable
3350:     .we     (dio_out_sleep_val_out10_we & regen_qs),
3351:     .wd     (dio_out_sleep_val_out10_wd),
3352:     .d      (hw2reg.dio_out_sleep_val[10].d),
3353:     .qre    (),
3354:     .qe     (reg2hw.dio_out_sleep_val[10].qe),
3355:     .q      (reg2hw.dio_out_sleep_val[10].q ),
3356:     .qs     (dio_out_sleep_val_out10_qs)
3357:   );
3358: 
3359: 
3360:   // F[out11]: 23:22
3361:   prim_subreg_ext #(
3362:     .DW    (2)
3363:   ) u_dio_out_sleep_val_out11 (
3364:     .re     (dio_out_sleep_val_out11_re),
3365:     // qualified with register enable
3366:     .we     (dio_out_sleep_val_out11_we & regen_qs),
3367:     .wd     (dio_out_sleep_val_out11_wd),
3368:     .d      (hw2reg.dio_out_sleep_val[11].d),
3369:     .qre    (),
3370:     .qe     (reg2hw.dio_out_sleep_val[11].qe),
3371:     .q      (reg2hw.dio_out_sleep_val[11].q ),
3372:     .qs     (dio_out_sleep_val_out11_qs)
3373:   );
3374: 
3375: 
3376:   // F[out12]: 25:24
3377:   prim_subreg_ext #(
3378:     .DW    (2)
3379:   ) u_dio_out_sleep_val_out12 (
3380:     .re     (dio_out_sleep_val_out12_re),
3381:     // qualified with register enable
3382:     .we     (dio_out_sleep_val_out12_we & regen_qs),
3383:     .wd     (dio_out_sleep_val_out12_wd),
3384:     .d      (hw2reg.dio_out_sleep_val[12].d),
3385:     .qre    (),
3386:     .qe     (reg2hw.dio_out_sleep_val[12].qe),
3387:     .q      (reg2hw.dio_out_sleep_val[12].q ),
3388:     .qs     (dio_out_sleep_val_out12_qs)
3389:   );
3390: 
3391: 
3392:   // F[out13]: 27:26
3393:   prim_subreg_ext #(
3394:     .DW    (2)
3395:   ) u_dio_out_sleep_val_out13 (
3396:     .re     (dio_out_sleep_val_out13_re),
3397:     // qualified with register enable
3398:     .we     (dio_out_sleep_val_out13_we & regen_qs),
3399:     .wd     (dio_out_sleep_val_out13_wd),
3400:     .d      (hw2reg.dio_out_sleep_val[13].d),
3401:     .qre    (),
3402:     .qe     (reg2hw.dio_out_sleep_val[13].qe),
3403:     .q      (reg2hw.dio_out_sleep_val[13].q ),
3404:     .qs     (dio_out_sleep_val_out13_qs)
3405:   );
3406: 
3407: 
3408:   // F[out14]: 29:28
3409:   prim_subreg_ext #(
3410:     .DW    (2)
3411:   ) u_dio_out_sleep_val_out14 (
3412:     .re     (dio_out_sleep_val_out14_re),
3413:     // qualified with register enable
3414:     .we     (dio_out_sleep_val_out14_we & regen_qs),
3415:     .wd     (dio_out_sleep_val_out14_wd),
3416:     .d      (hw2reg.dio_out_sleep_val[14].d),
3417:     .qre    (),
3418:     .qe     (reg2hw.dio_out_sleep_val[14].qe),
3419:     .q      (reg2hw.dio_out_sleep_val[14].q ),
3420:     .qs     (dio_out_sleep_val_out14_qs)
3421:   );
3422: 
3423: 
3424: 
3425: 
3426:   // Subregister 0 of Multireg wkup_detector_en
3427:   // R[wkup_detector_en]: V(False)
3428: 
3429:   // F[en0]: 0:0
3430:   prim_subreg #(
3431:     .DW      (1),
3432:     .SWACCESS("RW"),
3433:     .RESVAL  (1'h0)
3434:   ) u_wkup_detector_en_en0 (
3435:     .clk_i   (clk_i    ),
3436:     .rst_ni  (rst_ni  ),
3437: 
3438:     // from register interface (qualified with register enable)
3439:     .we     (wkup_detector_en_en0_we & regen_qs),
3440:     .wd     (wkup_detector_en_en0_wd),
3441: 
3442:     // from internal hardware
3443:     .de     (1'b0),
3444:     .d      ('0  ),
3445: 
3446:     // to internal hardware
3447:     .qe     (),
3448:     .q      (reg2hw.wkup_detector_en[0].q ),
3449: 
3450:     // to register interface (read)
3451:     .qs     (wkup_detector_en_en0_qs)
3452:   );
3453: 
3454: 
3455:   // F[en1]: 1:1
3456:   prim_subreg #(
3457:     .DW      (1),
3458:     .SWACCESS("RW"),
3459:     .RESVAL  (1'h0)
3460:   ) u_wkup_detector_en_en1 (
3461:     .clk_i   (clk_i    ),
3462:     .rst_ni  (rst_ni  ),
3463: 
3464:     // from register interface (qualified with register enable)
3465:     .we     (wkup_detector_en_en1_we & regen_qs),
3466:     .wd     (wkup_detector_en_en1_wd),
3467: 
3468:     // from internal hardware
3469:     .de     (1'b0),
3470:     .d      ('0  ),
3471: 
3472:     // to internal hardware
3473:     .qe     (),
3474:     .q      (reg2hw.wkup_detector_en[1].q ),
3475: 
3476:     // to register interface (read)
3477:     .qs     (wkup_detector_en_en1_qs)
3478:   );
3479: 
3480: 
3481:   // F[en2]: 2:2
3482:   prim_subreg #(
3483:     .DW      (1),
3484:     .SWACCESS("RW"),
3485:     .RESVAL  (1'h0)
3486:   ) u_wkup_detector_en_en2 (
3487:     .clk_i   (clk_i    ),
3488:     .rst_ni  (rst_ni  ),
3489: 
3490:     // from register interface (qualified with register enable)
3491:     .we     (wkup_detector_en_en2_we & regen_qs),
3492:     .wd     (wkup_detector_en_en2_wd),
3493: 
3494:     // from internal hardware
3495:     .de     (1'b0),
3496:     .d      ('0  ),
3497: 
3498:     // to internal hardware
3499:     .qe     (),
3500:     .q      (reg2hw.wkup_detector_en[2].q ),
3501: 
3502:     // to register interface (read)
3503:     .qs     (wkup_detector_en_en2_qs)
3504:   );
3505: 
3506: 
3507:   // F[en3]: 3:3
3508:   prim_subreg #(
3509:     .DW      (1),
3510:     .SWACCESS("RW"),
3511:     .RESVAL  (1'h0)
3512:   ) u_wkup_detector_en_en3 (
3513:     .clk_i   (clk_i    ),
3514:     .rst_ni  (rst_ni  ),
3515: 
3516:     // from register interface (qualified with register enable)
3517:     .we     (wkup_detector_en_en3_we & regen_qs),
3518:     .wd     (wkup_detector_en_en3_wd),
3519: 
3520:     // from internal hardware
3521:     .de     (1'b0),
3522:     .d      ('0  ),
3523: 
3524:     // to internal hardware
3525:     .qe     (),
3526:     .q      (reg2hw.wkup_detector_en[3].q ),
3527: 
3528:     // to register interface (read)
3529:     .qs     (wkup_detector_en_en3_qs)
3530:   );
3531: 
3532: 
3533:   // F[en4]: 4:4
3534:   prim_subreg #(
3535:     .DW      (1),
3536:     .SWACCESS("RW"),
3537:     .RESVAL  (1'h0)
3538:   ) u_wkup_detector_en_en4 (
3539:     .clk_i   (clk_i    ),
3540:     .rst_ni  (rst_ni  ),
3541: 
3542:     // from register interface (qualified with register enable)
3543:     .we     (wkup_detector_en_en4_we & regen_qs),
3544:     .wd     (wkup_detector_en_en4_wd),
3545: 
3546:     // from internal hardware
3547:     .de     (1'b0),
3548:     .d      ('0  ),
3549: 
3550:     // to internal hardware
3551:     .qe     (),
3552:     .q      (reg2hw.wkup_detector_en[4].q ),
3553: 
3554:     // to register interface (read)
3555:     .qs     (wkup_detector_en_en4_qs)
3556:   );
3557: 
3558: 
3559:   // F[en5]: 5:5
3560:   prim_subreg #(
3561:     .DW      (1),
3562:     .SWACCESS("RW"),
3563:     .RESVAL  (1'h0)
3564:   ) u_wkup_detector_en_en5 (
3565:     .clk_i   (clk_i    ),
3566:     .rst_ni  (rst_ni  ),
3567: 
3568:     // from register interface (qualified with register enable)
3569:     .we     (wkup_detector_en_en5_we & regen_qs),
3570:     .wd     (wkup_detector_en_en5_wd),
3571: 
3572:     // from internal hardware
3573:     .de     (1'b0),
3574:     .d      ('0  ),
3575: 
3576:     // to internal hardware
3577:     .qe     (),
3578:     .q      (reg2hw.wkup_detector_en[5].q ),
3579: 
3580:     // to register interface (read)
3581:     .qs     (wkup_detector_en_en5_qs)
3582:   );
3583: 
3584: 
3585:   // F[en6]: 6:6
3586:   prim_subreg #(
3587:     .DW      (1),
3588:     .SWACCESS("RW"),
3589:     .RESVAL  (1'h0)
3590:   ) u_wkup_detector_en_en6 (
3591:     .clk_i   (clk_i    ),
3592:     .rst_ni  (rst_ni  ),
3593: 
3594:     // from register interface (qualified with register enable)
3595:     .we     (wkup_detector_en_en6_we & regen_qs),
3596:     .wd     (wkup_detector_en_en6_wd),
3597: 
3598:     // from internal hardware
3599:     .de     (1'b0),
3600:     .d      ('0  ),
3601: 
3602:     // to internal hardware
3603:     .qe     (),
3604:     .q      (reg2hw.wkup_detector_en[6].q ),
3605: 
3606:     // to register interface (read)
3607:     .qs     (wkup_detector_en_en6_qs)
3608:   );
3609: 
3610: 
3611:   // F[en7]: 7:7
3612:   prim_subreg #(
3613:     .DW      (1),
3614:     .SWACCESS("RW"),
3615:     .RESVAL  (1'h0)
3616:   ) u_wkup_detector_en_en7 (
3617:     .clk_i   (clk_i    ),
3618:     .rst_ni  (rst_ni  ),
3619: 
3620:     // from register interface (qualified with register enable)
3621:     .we     (wkup_detector_en_en7_we & regen_qs),
3622:     .wd     (wkup_detector_en_en7_wd),
3623: 
3624:     // from internal hardware
3625:     .de     (1'b0),
3626:     .d      ('0  ),
3627: 
3628:     // to internal hardware
3629:     .qe     (),
3630:     .q      (reg2hw.wkup_detector_en[7].q ),
3631: 
3632:     // to register interface (read)
3633:     .qs     (wkup_detector_en_en7_qs)
3634:   );
3635: 
3636: 
3637: 
3638: 
3639:   // Subregister 0 of Multireg wkup_detector
3640:   // R[wkup_detector0]: V(False)
3641: 
3642:   // F[mode0]: 2:0
3643:   prim_subreg #(
3644:     .DW      (3),
3645:     .SWACCESS("RW"),
3646:     .RESVAL  (3'h0)
3647:   ) u_wkup_detector0_mode0 (
3648:     .clk_i   (clk_i    ),
3649:     .rst_ni  (rst_ni  ),
3650: 
3651:     // from register interface (qualified with register enable)
3652:     .we     (wkup_detector0_mode0_we & regen_qs),
3653:     .wd     (wkup_detector0_mode0_wd),
3654: 
3655:     // from internal hardware
3656:     .de     (1'b0),
3657:     .d      ('0  ),
3658: 
3659:     // to internal hardware
3660:     .qe     (),
3661:     .q      (reg2hw.wkup_detector[0].mode.q ),
3662: 
3663:     // to register interface (read)
3664:     .qs     (wkup_detector0_mode0_qs)
3665:   );
3666: 
3667: 
3668:   // F[filter0]: 3:3
3669:   prim_subreg #(
3670:     .DW      (1),
3671:     .SWACCESS("RW"),
3672:     .RESVAL  (1'h0)
3673:   ) u_wkup_detector0_filter0 (
3674:     .clk_i   (clk_i    ),
3675:     .rst_ni  (rst_ni  ),
3676: 
3677:     // from register interface (qualified with register enable)
3678:     .we     (wkup_detector0_filter0_we & regen_qs),
3679:     .wd     (wkup_detector0_filter0_wd),
3680: 
3681:     // from internal hardware
3682:     .de     (1'b0),
3683:     .d      ('0  ),
3684: 
3685:     // to internal hardware
3686:     .qe     (),
3687:     .q      (reg2hw.wkup_detector[0].filter.q ),
3688: 
3689:     // to register interface (read)
3690:     .qs     (wkup_detector0_filter0_qs)
3691:   );
3692: 
3693: 
3694:   // F[miodio0]: 4:4
3695:   prim_subreg #(
3696:     .DW      (1),
3697:     .SWACCESS("RW"),
3698:     .RESVAL  (1'h0)
3699:   ) u_wkup_detector0_miodio0 (
3700:     .clk_i   (clk_i    ),
3701:     .rst_ni  (rst_ni  ),
3702: 
3703:     // from register interface (qualified with register enable)
3704:     .we     (wkup_detector0_miodio0_we & regen_qs),
3705:     .wd     (wkup_detector0_miodio0_wd),
3706: 
3707:     // from internal hardware
3708:     .de     (1'b0),
3709:     .d      ('0  ),
3710: 
3711:     // to internal hardware
3712:     .qe     (),
3713:     .q      (reg2hw.wkup_detector[0].miodio.q ),
3714: 
3715:     // to register interface (read)
3716:     .qs     (wkup_detector0_miodio0_qs)
3717:   );
3718: 
3719: 
3720:   // Subregister 1 of Multireg wkup_detector
3721:   // R[wkup_detector1]: V(False)
3722: 
3723:   // F[mode1]: 2:0
3724:   prim_subreg #(
3725:     .DW      (3),
3726:     .SWACCESS("RW"),
3727:     .RESVAL  (3'h0)
3728:   ) u_wkup_detector1_mode1 (
3729:     .clk_i   (clk_i    ),
3730:     .rst_ni  (rst_ni  ),
3731: 
3732:     // from register interface (qualified with register enable)
3733:     .we     (wkup_detector1_mode1_we & regen_qs),
3734:     .wd     (wkup_detector1_mode1_wd),
3735: 
3736:     // from internal hardware
3737:     .de     (1'b0),
3738:     .d      ('0  ),
3739: 
3740:     // to internal hardware
3741:     .qe     (),
3742:     .q      (reg2hw.wkup_detector[1].mode.q ),
3743: 
3744:     // to register interface (read)
3745:     .qs     (wkup_detector1_mode1_qs)
3746:   );
3747: 
3748: 
3749:   // F[filter1]: 3:3
3750:   prim_subreg #(
3751:     .DW      (1),
3752:     .SWACCESS("RW"),
3753:     .RESVAL  (1'h0)
3754:   ) u_wkup_detector1_filter1 (
3755:     .clk_i   (clk_i    ),
3756:     .rst_ni  (rst_ni  ),
3757: 
3758:     // from register interface (qualified with register enable)
3759:     .we     (wkup_detector1_filter1_we & regen_qs),
3760:     .wd     (wkup_detector1_filter1_wd),
3761: 
3762:     // from internal hardware
3763:     .de     (1'b0),
3764:     .d      ('0  ),
3765: 
3766:     // to internal hardware
3767:     .qe     (),
3768:     .q      (reg2hw.wkup_detector[1].filter.q ),
3769: 
3770:     // to register interface (read)
3771:     .qs     (wkup_detector1_filter1_qs)
3772:   );
3773: 
3774: 
3775:   // F[miodio1]: 4:4
3776:   prim_subreg #(
3777:     .DW      (1),
3778:     .SWACCESS("RW"),
3779:     .RESVAL  (1'h0)
3780:   ) u_wkup_detector1_miodio1 (
3781:     .clk_i   (clk_i    ),
3782:     .rst_ni  (rst_ni  ),
3783: 
3784:     // from register interface (qualified with register enable)
3785:     .we     (wkup_detector1_miodio1_we & regen_qs),
3786:     .wd     (wkup_detector1_miodio1_wd),
3787: 
3788:     // from internal hardware
3789:     .de     (1'b0),
3790:     .d      ('0  ),
3791: 
3792:     // to internal hardware
3793:     .qe     (),
3794:     .q      (reg2hw.wkup_detector[1].miodio.q ),
3795: 
3796:     // to register interface (read)
3797:     .qs     (wkup_detector1_miodio1_qs)
3798:   );
3799: 
3800: 
3801:   // Subregister 2 of Multireg wkup_detector
3802:   // R[wkup_detector2]: V(False)
3803: 
3804:   // F[mode2]: 2:0
3805:   prim_subreg #(
3806:     .DW      (3),
3807:     .SWACCESS("RW"),
3808:     .RESVAL  (3'h0)
3809:   ) u_wkup_detector2_mode2 (
3810:     .clk_i   (clk_i    ),
3811:     .rst_ni  (rst_ni  ),
3812: 
3813:     // from register interface (qualified with register enable)
3814:     .we     (wkup_detector2_mode2_we & regen_qs),
3815:     .wd     (wkup_detector2_mode2_wd),
3816: 
3817:     // from internal hardware
3818:     .de     (1'b0),
3819:     .d      ('0  ),
3820: 
3821:     // to internal hardware
3822:     .qe     (),
3823:     .q      (reg2hw.wkup_detector[2].mode.q ),
3824: 
3825:     // to register interface (read)
3826:     .qs     (wkup_detector2_mode2_qs)
3827:   );
3828: 
3829: 
3830:   // F[filter2]: 3:3
3831:   prim_subreg #(
3832:     .DW      (1),
3833:     .SWACCESS("RW"),
3834:     .RESVAL  (1'h0)
3835:   ) u_wkup_detector2_filter2 (
3836:     .clk_i   (clk_i    ),
3837:     .rst_ni  (rst_ni  ),
3838: 
3839:     // from register interface (qualified with register enable)
3840:     .we     (wkup_detector2_filter2_we & regen_qs),
3841:     .wd     (wkup_detector2_filter2_wd),
3842: 
3843:     // from internal hardware
3844:     .de     (1'b0),
3845:     .d      ('0  ),
3846: 
3847:     // to internal hardware
3848:     .qe     (),
3849:     .q      (reg2hw.wkup_detector[2].filter.q ),
3850: 
3851:     // to register interface (read)
3852:     .qs     (wkup_detector2_filter2_qs)
3853:   );
3854: 
3855: 
3856:   // F[miodio2]: 4:4
3857:   prim_subreg #(
3858:     .DW      (1),
3859:     .SWACCESS("RW"),
3860:     .RESVAL  (1'h0)
3861:   ) u_wkup_detector2_miodio2 (
3862:     .clk_i   (clk_i    ),
3863:     .rst_ni  (rst_ni  ),
3864: 
3865:     // from register interface (qualified with register enable)
3866:     .we     (wkup_detector2_miodio2_we & regen_qs),
3867:     .wd     (wkup_detector2_miodio2_wd),
3868: 
3869:     // from internal hardware
3870:     .de     (1'b0),
3871:     .d      ('0  ),
3872: 
3873:     // to internal hardware
3874:     .qe     (),
3875:     .q      (reg2hw.wkup_detector[2].miodio.q ),
3876: 
3877:     // to register interface (read)
3878:     .qs     (wkup_detector2_miodio2_qs)
3879:   );
3880: 
3881: 
3882:   // Subregister 3 of Multireg wkup_detector
3883:   // R[wkup_detector3]: V(False)
3884: 
3885:   // F[mode3]: 2:0
3886:   prim_subreg #(
3887:     .DW      (3),
3888:     .SWACCESS("RW"),
3889:     .RESVAL  (3'h0)
3890:   ) u_wkup_detector3_mode3 (
3891:     .clk_i   (clk_i    ),
3892:     .rst_ni  (rst_ni  ),
3893: 
3894:     // from register interface (qualified with register enable)
3895:     .we     (wkup_detector3_mode3_we & regen_qs),
3896:     .wd     (wkup_detector3_mode3_wd),
3897: 
3898:     // from internal hardware
3899:     .de     (1'b0),
3900:     .d      ('0  ),
3901: 
3902:     // to internal hardware
3903:     .qe     (),
3904:     .q      (reg2hw.wkup_detector[3].mode.q ),
3905: 
3906:     // to register interface (read)
3907:     .qs     (wkup_detector3_mode3_qs)
3908:   );
3909: 
3910: 
3911:   // F[filter3]: 3:3
3912:   prim_subreg #(
3913:     .DW      (1),
3914:     .SWACCESS("RW"),
3915:     .RESVAL  (1'h0)
3916:   ) u_wkup_detector3_filter3 (
3917:     .clk_i   (clk_i    ),
3918:     .rst_ni  (rst_ni  ),
3919: 
3920:     // from register interface (qualified with register enable)
3921:     .we     (wkup_detector3_filter3_we & regen_qs),
3922:     .wd     (wkup_detector3_filter3_wd),
3923: 
3924:     // from internal hardware
3925:     .de     (1'b0),
3926:     .d      ('0  ),
3927: 
3928:     // to internal hardware
3929:     .qe     (),
3930:     .q      (reg2hw.wkup_detector[3].filter.q ),
3931: 
3932:     // to register interface (read)
3933:     .qs     (wkup_detector3_filter3_qs)
3934:   );
3935: 
3936: 
3937:   // F[miodio3]: 4:4
3938:   prim_subreg #(
3939:     .DW      (1),
3940:     .SWACCESS("RW"),
3941:     .RESVAL  (1'h0)
3942:   ) u_wkup_detector3_miodio3 (
3943:     .clk_i   (clk_i    ),
3944:     .rst_ni  (rst_ni  ),
3945: 
3946:     // from register interface (qualified with register enable)
3947:     .we     (wkup_detector3_miodio3_we & regen_qs),
3948:     .wd     (wkup_detector3_miodio3_wd),
3949: 
3950:     // from internal hardware
3951:     .de     (1'b0),
3952:     .d      ('0  ),
3953: 
3954:     // to internal hardware
3955:     .qe     (),
3956:     .q      (reg2hw.wkup_detector[3].miodio.q ),
3957: 
3958:     // to register interface (read)
3959:     .qs     (wkup_detector3_miodio3_qs)
3960:   );
3961: 
3962: 
3963:   // Subregister 4 of Multireg wkup_detector
3964:   // R[wkup_detector4]: V(False)
3965: 
3966:   // F[mode4]: 2:0
3967:   prim_subreg #(
3968:     .DW      (3),
3969:     .SWACCESS("RW"),
3970:     .RESVAL  (3'h0)
3971:   ) u_wkup_detector4_mode4 (
3972:     .clk_i   (clk_i    ),
3973:     .rst_ni  (rst_ni  ),
3974: 
3975:     // from register interface (qualified with register enable)
3976:     .we     (wkup_detector4_mode4_we & regen_qs),
3977:     .wd     (wkup_detector4_mode4_wd),
3978: 
3979:     // from internal hardware
3980:     .de     (1'b0),
3981:     .d      ('0  ),
3982: 
3983:     // to internal hardware
3984:     .qe     (),
3985:     .q      (reg2hw.wkup_detector[4].mode.q ),
3986: 
3987:     // to register interface (read)
3988:     .qs     (wkup_detector4_mode4_qs)
3989:   );
3990: 
3991: 
3992:   // F[filter4]: 3:3
3993:   prim_subreg #(
3994:     .DW      (1),
3995:     .SWACCESS("RW"),
3996:     .RESVAL  (1'h0)
3997:   ) u_wkup_detector4_filter4 (
3998:     .clk_i   (clk_i    ),
3999:     .rst_ni  (rst_ni  ),
4000: 
4001:     // from register interface (qualified with register enable)
4002:     .we     (wkup_detector4_filter4_we & regen_qs),
4003:     .wd     (wkup_detector4_filter4_wd),
4004: 
4005:     // from internal hardware
4006:     .de     (1'b0),
4007:     .d      ('0  ),
4008: 
4009:     // to internal hardware
4010:     .qe     (),
4011:     .q      (reg2hw.wkup_detector[4].filter.q ),
4012: 
4013:     // to register interface (read)
4014:     .qs     (wkup_detector4_filter4_qs)
4015:   );
4016: 
4017: 
4018:   // F[miodio4]: 4:4
4019:   prim_subreg #(
4020:     .DW      (1),
4021:     .SWACCESS("RW"),
4022:     .RESVAL  (1'h0)
4023:   ) u_wkup_detector4_miodio4 (
4024:     .clk_i   (clk_i    ),
4025:     .rst_ni  (rst_ni  ),
4026: 
4027:     // from register interface (qualified with register enable)
4028:     .we     (wkup_detector4_miodio4_we & regen_qs),
4029:     .wd     (wkup_detector4_miodio4_wd),
4030: 
4031:     // from internal hardware
4032:     .de     (1'b0),
4033:     .d      ('0  ),
4034: 
4035:     // to internal hardware
4036:     .qe     (),
4037:     .q      (reg2hw.wkup_detector[4].miodio.q ),
4038: 
4039:     // to register interface (read)
4040:     .qs     (wkup_detector4_miodio4_qs)
4041:   );
4042: 
4043: 
4044:   // Subregister 5 of Multireg wkup_detector
4045:   // R[wkup_detector5]: V(False)
4046: 
4047:   // F[mode5]: 2:0
4048:   prim_subreg #(
4049:     .DW      (3),
4050:     .SWACCESS("RW"),
4051:     .RESVAL  (3'h0)
4052:   ) u_wkup_detector5_mode5 (
4053:     .clk_i   (clk_i    ),
4054:     .rst_ni  (rst_ni  ),
4055: 
4056:     // from register interface (qualified with register enable)
4057:     .we     (wkup_detector5_mode5_we & regen_qs),
4058:     .wd     (wkup_detector5_mode5_wd),
4059: 
4060:     // from internal hardware
4061:     .de     (1'b0),
4062:     .d      ('0  ),
4063: 
4064:     // to internal hardware
4065:     .qe     (),
4066:     .q      (reg2hw.wkup_detector[5].mode.q ),
4067: 
4068:     // to register interface (read)
4069:     .qs     (wkup_detector5_mode5_qs)
4070:   );
4071: 
4072: 
4073:   // F[filter5]: 3:3
4074:   prim_subreg #(
4075:     .DW      (1),
4076:     .SWACCESS("RW"),
4077:     .RESVAL  (1'h0)
4078:   ) u_wkup_detector5_filter5 (
4079:     .clk_i   (clk_i    ),
4080:     .rst_ni  (rst_ni  ),
4081: 
4082:     // from register interface (qualified with register enable)
4083:     .we     (wkup_detector5_filter5_we & regen_qs),
4084:     .wd     (wkup_detector5_filter5_wd),
4085: 
4086:     // from internal hardware
4087:     .de     (1'b0),
4088:     .d      ('0  ),
4089: 
4090:     // to internal hardware
4091:     .qe     (),
4092:     .q      (reg2hw.wkup_detector[5].filter.q ),
4093: 
4094:     // to register interface (read)
4095:     .qs     (wkup_detector5_filter5_qs)
4096:   );
4097: 
4098: 
4099:   // F[miodio5]: 4:4
4100:   prim_subreg #(
4101:     .DW      (1),
4102:     .SWACCESS("RW"),
4103:     .RESVAL  (1'h0)
4104:   ) u_wkup_detector5_miodio5 (
4105:     .clk_i   (clk_i    ),
4106:     .rst_ni  (rst_ni  ),
4107: 
4108:     // from register interface (qualified with register enable)
4109:     .we     (wkup_detector5_miodio5_we & regen_qs),
4110:     .wd     (wkup_detector5_miodio5_wd),
4111: 
4112:     // from internal hardware
4113:     .de     (1'b0),
4114:     .d      ('0  ),
4115: 
4116:     // to internal hardware
4117:     .qe     (),
4118:     .q      (reg2hw.wkup_detector[5].miodio.q ),
4119: 
4120:     // to register interface (read)
4121:     .qs     (wkup_detector5_miodio5_qs)
4122:   );
4123: 
4124: 
4125:   // Subregister 6 of Multireg wkup_detector
4126:   // R[wkup_detector6]: V(False)
4127: 
4128:   // F[mode6]: 2:0
4129:   prim_subreg #(
4130:     .DW      (3),
4131:     .SWACCESS("RW"),
4132:     .RESVAL  (3'h0)
4133:   ) u_wkup_detector6_mode6 (
4134:     .clk_i   (clk_i    ),
4135:     .rst_ni  (rst_ni  ),
4136: 
4137:     // from register interface (qualified with register enable)
4138:     .we     (wkup_detector6_mode6_we & regen_qs),
4139:     .wd     (wkup_detector6_mode6_wd),
4140: 
4141:     // from internal hardware
4142:     .de     (1'b0),
4143:     .d      ('0  ),
4144: 
4145:     // to internal hardware
4146:     .qe     (),
4147:     .q      (reg2hw.wkup_detector[6].mode.q ),
4148: 
4149:     // to register interface (read)
4150:     .qs     (wkup_detector6_mode6_qs)
4151:   );
4152: 
4153: 
4154:   // F[filter6]: 3:3
4155:   prim_subreg #(
4156:     .DW      (1),
4157:     .SWACCESS("RW"),
4158:     .RESVAL  (1'h0)
4159:   ) u_wkup_detector6_filter6 (
4160:     .clk_i   (clk_i    ),
4161:     .rst_ni  (rst_ni  ),
4162: 
4163:     // from register interface (qualified with register enable)
4164:     .we     (wkup_detector6_filter6_we & regen_qs),
4165:     .wd     (wkup_detector6_filter6_wd),
4166: 
4167:     // from internal hardware
4168:     .de     (1'b0),
4169:     .d      ('0  ),
4170: 
4171:     // to internal hardware
4172:     .qe     (),
4173:     .q      (reg2hw.wkup_detector[6].filter.q ),
4174: 
4175:     // to register interface (read)
4176:     .qs     (wkup_detector6_filter6_qs)
4177:   );
4178: 
4179: 
4180:   // F[miodio6]: 4:4
4181:   prim_subreg #(
4182:     .DW      (1),
4183:     .SWACCESS("RW"),
4184:     .RESVAL  (1'h0)
4185:   ) u_wkup_detector6_miodio6 (
4186:     .clk_i   (clk_i    ),
4187:     .rst_ni  (rst_ni  ),
4188: 
4189:     // from register interface (qualified with register enable)
4190:     .we     (wkup_detector6_miodio6_we & regen_qs),
4191:     .wd     (wkup_detector6_miodio6_wd),
4192: 
4193:     // from internal hardware
4194:     .de     (1'b0),
4195:     .d      ('0  ),
4196: 
4197:     // to internal hardware
4198:     .qe     (),
4199:     .q      (reg2hw.wkup_detector[6].miodio.q ),
4200: 
4201:     // to register interface (read)
4202:     .qs     (wkup_detector6_miodio6_qs)
4203:   );
4204: 
4205: 
4206:   // Subregister 7 of Multireg wkup_detector
4207:   // R[wkup_detector7]: V(False)
4208: 
4209:   // F[mode7]: 2:0
4210:   prim_subreg #(
4211:     .DW      (3),
4212:     .SWACCESS("RW"),
4213:     .RESVAL  (3'h0)
4214:   ) u_wkup_detector7_mode7 (
4215:     .clk_i   (clk_i    ),
4216:     .rst_ni  (rst_ni  ),
4217: 
4218:     // from register interface (qualified with register enable)
4219:     .we     (wkup_detector7_mode7_we & regen_qs),
4220:     .wd     (wkup_detector7_mode7_wd),
4221: 
4222:     // from internal hardware
4223:     .de     (1'b0),
4224:     .d      ('0  ),
4225: 
4226:     // to internal hardware
4227:     .qe     (),
4228:     .q      (reg2hw.wkup_detector[7].mode.q ),
4229: 
4230:     // to register interface (read)
4231:     .qs     (wkup_detector7_mode7_qs)
4232:   );
4233: 
4234: 
4235:   // F[filter7]: 3:3
4236:   prim_subreg #(
4237:     .DW      (1),
4238:     .SWACCESS("RW"),
4239:     .RESVAL  (1'h0)
4240:   ) u_wkup_detector7_filter7 (
4241:     .clk_i   (clk_i    ),
4242:     .rst_ni  (rst_ni  ),
4243: 
4244:     // from register interface (qualified with register enable)
4245:     .we     (wkup_detector7_filter7_we & regen_qs),
4246:     .wd     (wkup_detector7_filter7_wd),
4247: 
4248:     // from internal hardware
4249:     .de     (1'b0),
4250:     .d      ('0  ),
4251: 
4252:     // to internal hardware
4253:     .qe     (),
4254:     .q      (reg2hw.wkup_detector[7].filter.q ),
4255: 
4256:     // to register interface (read)
4257:     .qs     (wkup_detector7_filter7_qs)
4258:   );
4259: 
4260: 
4261:   // F[miodio7]: 4:4
4262:   prim_subreg #(
4263:     .DW      (1),
4264:     .SWACCESS("RW"),
4265:     .RESVAL  (1'h0)
4266:   ) u_wkup_detector7_miodio7 (
4267:     .clk_i   (clk_i    ),
4268:     .rst_ni  (rst_ni  ),
4269: 
4270:     // from register interface (qualified with register enable)
4271:     .we     (wkup_detector7_miodio7_we & regen_qs),
4272:     .wd     (wkup_detector7_miodio7_wd),
4273: 
4274:     // from internal hardware
4275:     .de     (1'b0),
4276:     .d      ('0  ),
4277: 
4278:     // to internal hardware
4279:     .qe     (),
4280:     .q      (reg2hw.wkup_detector[7].miodio.q ),
4281: 
4282:     // to register interface (read)
4283:     .qs     (wkup_detector7_miodio7_qs)
4284:   );
4285: 
4286: 
4287: 
4288: 
4289:   // Subregister 0 of Multireg wkup_detector_cnt_th
4290:   // R[wkup_detector_cnt_th0]: V(False)
4291: 
4292:   // F[th0]: 7:0
4293:   prim_subreg #(
4294:     .DW      (8),
4295:     .SWACCESS("RW"),
4296:     .RESVAL  (8'h0)
4297:   ) u_wkup_detector_cnt_th0_th0 (
4298:     .clk_i   (clk_i    ),
4299:     .rst_ni  (rst_ni  ),
4300: 
4301:     // from register interface (qualified with register enable)
4302:     .we     (wkup_detector_cnt_th0_th0_we & regen_qs),
4303:     .wd     (wkup_detector_cnt_th0_th0_wd),
4304: 
4305:     // from internal hardware
4306:     .de     (1'b0),
4307:     .d      ('0  ),
4308: 
4309:     // to internal hardware
4310:     .qe     (),
4311:     .q      (reg2hw.wkup_detector_cnt_th[0].q ),
4312: 
4313:     // to register interface (read)
4314:     .qs     (wkup_detector_cnt_th0_th0_qs)
4315:   );
4316: 
4317: 
4318:   // F[th1]: 15:8
4319:   prim_subreg #(
4320:     .DW      (8),
4321:     .SWACCESS("RW"),
4322:     .RESVAL  (8'h0)
4323:   ) u_wkup_detector_cnt_th0_th1 (
4324:     .clk_i   (clk_i    ),
4325:     .rst_ni  (rst_ni  ),
4326: 
4327:     // from register interface (qualified with register enable)
4328:     .we     (wkup_detector_cnt_th0_th1_we & regen_qs),
4329:     .wd     (wkup_detector_cnt_th0_th1_wd),
4330: 
4331:     // from internal hardware
4332:     .de     (1'b0),
4333:     .d      ('0  ),
4334: 
4335:     // to internal hardware
4336:     .qe     (),
4337:     .q      (reg2hw.wkup_detector_cnt_th[1].q ),
4338: 
4339:     // to register interface (read)
4340:     .qs     (wkup_detector_cnt_th0_th1_qs)
4341:   );
4342: 
4343: 
4344:   // F[th2]: 23:16
4345:   prim_subreg #(
4346:     .DW      (8),
4347:     .SWACCESS("RW"),
4348:     .RESVAL  (8'h0)
4349:   ) u_wkup_detector_cnt_th0_th2 (
4350:     .clk_i   (clk_i    ),
4351:     .rst_ni  (rst_ni  ),
4352: 
4353:     // from register interface (qualified with register enable)
4354:     .we     (wkup_detector_cnt_th0_th2_we & regen_qs),
4355:     .wd     (wkup_detector_cnt_th0_th2_wd),
4356: 
4357:     // from internal hardware
4358:     .de     (1'b0),
4359:     .d      ('0  ),
4360: 
4361:     // to internal hardware
4362:     .qe     (),
4363:     .q      (reg2hw.wkup_detector_cnt_th[2].q ),
4364: 
4365:     // to register interface (read)
4366:     .qs     (wkup_detector_cnt_th0_th2_qs)
4367:   );
4368: 
4369: 
4370:   // F[th3]: 31:24
4371:   prim_subreg #(
4372:     .DW      (8),
4373:     .SWACCESS("RW"),
4374:     .RESVAL  (8'h0)
4375:   ) u_wkup_detector_cnt_th0_th3 (
4376:     .clk_i   (clk_i    ),
4377:     .rst_ni  (rst_ni  ),
4378: 
4379:     // from register interface (qualified with register enable)
4380:     .we     (wkup_detector_cnt_th0_th3_we & regen_qs),
4381:     .wd     (wkup_detector_cnt_th0_th3_wd),
4382: 
4383:     // from internal hardware
4384:     .de     (1'b0),
4385:     .d      ('0  ),
4386: 
4387:     // to internal hardware
4388:     .qe     (),
4389:     .q      (reg2hw.wkup_detector_cnt_th[3].q ),
4390: 
4391:     // to register interface (read)
4392:     .qs     (wkup_detector_cnt_th0_th3_qs)
4393:   );
4394: 
4395: 
4396:   // Subregister 4 of Multireg wkup_detector_cnt_th
4397:   // R[wkup_detector_cnt_th1]: V(False)
4398: 
4399:   // F[th4]: 7:0
4400:   prim_subreg #(
4401:     .DW      (8),
4402:     .SWACCESS("RW"),
4403:     .RESVAL  (8'h0)
4404:   ) u_wkup_detector_cnt_th1_th4 (
4405:     .clk_i   (clk_i    ),
4406:     .rst_ni  (rst_ni  ),
4407: 
4408:     // from register interface (qualified with register enable)
4409:     .we     (wkup_detector_cnt_th1_th4_we & regen_qs),
4410:     .wd     (wkup_detector_cnt_th1_th4_wd),
4411: 
4412:     // from internal hardware
4413:     .de     (1'b0),
4414:     .d      ('0  ),
4415: 
4416:     // to internal hardware
4417:     .qe     (),
4418:     .q      (reg2hw.wkup_detector_cnt_th[4].q ),
4419: 
4420:     // to register interface (read)
4421:     .qs     (wkup_detector_cnt_th1_th4_qs)
4422:   );
4423: 
4424: 
4425:   // F[th5]: 15:8
4426:   prim_subreg #(
4427:     .DW      (8),
4428:     .SWACCESS("RW"),
4429:     .RESVAL  (8'h0)
4430:   ) u_wkup_detector_cnt_th1_th5 (
4431:     .clk_i   (clk_i    ),
4432:     .rst_ni  (rst_ni  ),
4433: 
4434:     // from register interface (qualified with register enable)
4435:     .we     (wkup_detector_cnt_th1_th5_we & regen_qs),
4436:     .wd     (wkup_detector_cnt_th1_th5_wd),
4437: 
4438:     // from internal hardware
4439:     .de     (1'b0),
4440:     .d      ('0  ),
4441: 
4442:     // to internal hardware
4443:     .qe     (),
4444:     .q      (reg2hw.wkup_detector_cnt_th[5].q ),
4445: 
4446:     // to register interface (read)
4447:     .qs     (wkup_detector_cnt_th1_th5_qs)
4448:   );
4449: 
4450: 
4451:   // F[th6]: 23:16
4452:   prim_subreg #(
4453:     .DW      (8),
4454:     .SWACCESS("RW"),
4455:     .RESVAL  (8'h0)
4456:   ) u_wkup_detector_cnt_th1_th6 (
4457:     .clk_i   (clk_i    ),
4458:     .rst_ni  (rst_ni  ),
4459: 
4460:     // from register interface (qualified with register enable)
4461:     .we     (wkup_detector_cnt_th1_th6_we & regen_qs),
4462:     .wd     (wkup_detector_cnt_th1_th6_wd),
4463: 
4464:     // from internal hardware
4465:     .de     (1'b0),
4466:     .d      ('0  ),
4467: 
4468:     // to internal hardware
4469:     .qe     (),
4470:     .q      (reg2hw.wkup_detector_cnt_th[6].q ),
4471: 
4472:     // to register interface (read)
4473:     .qs     (wkup_detector_cnt_th1_th6_qs)
4474:   );
4475: 
4476: 
4477:   // F[th7]: 31:24
4478:   prim_subreg #(
4479:     .DW      (8),
4480:     .SWACCESS("RW"),
4481:     .RESVAL  (8'h0)
4482:   ) u_wkup_detector_cnt_th1_th7 (
4483:     .clk_i   (clk_i    ),
4484:     .rst_ni  (rst_ni  ),
4485: 
4486:     // from register interface (qualified with register enable)
4487:     .we     (wkup_detector_cnt_th1_th7_we & regen_qs),
4488:     .wd     (wkup_detector_cnt_th1_th7_wd),
4489: 
4490:     // from internal hardware
4491:     .de     (1'b0),
4492:     .d      ('0  ),
4493: 
4494:     // to internal hardware
4495:     .qe     (),
4496:     .q      (reg2hw.wkup_detector_cnt_th[7].q ),
4497: 
4498:     // to register interface (read)
4499:     .qs     (wkup_detector_cnt_th1_th7_qs)
4500:   );
4501: 
4502: 
4503: 
4504: 
4505:   // Subregister 0 of Multireg wkup_detector_padsel
4506:   // R[wkup_detector_padsel0]: V(False)
4507: 
4508:   // F[sel0]: 4:0
4509:   prim_subreg #(
4510:     .DW      (5),
4511:     .SWACCESS("RW"),
4512:     .RESVAL  (5'h0)
4513:   ) u_wkup_detector_padsel0_sel0 (
4514:     .clk_i   (clk_i    ),
4515:     .rst_ni  (rst_ni  ),
4516: 
4517:     // from register interface (qualified with register enable)
4518:     .we     (wkup_detector_padsel0_sel0_we & regen_qs),
4519:     .wd     (wkup_detector_padsel0_sel0_wd),
4520: 
4521:     // from internal hardware
4522:     .de     (1'b0),
4523:     .d      ('0  ),
4524: 
4525:     // to internal hardware
4526:     .qe     (),
4527:     .q      (reg2hw.wkup_detector_padsel[0].q ),
4528: 
4529:     // to register interface (read)
4530:     .qs     (wkup_detector_padsel0_sel0_qs)
4531:   );
4532: 
4533: 
4534:   // F[sel1]: 9:5
4535:   prim_subreg #(
4536:     .DW      (5),
4537:     .SWACCESS("RW"),
4538:     .RESVAL  (5'h0)
4539:   ) u_wkup_detector_padsel0_sel1 (
4540:     .clk_i   (clk_i    ),
4541:     .rst_ni  (rst_ni  ),
4542: 
4543:     // from register interface (qualified with register enable)
4544:     .we     (wkup_detector_padsel0_sel1_we & regen_qs),
4545:     .wd     (wkup_detector_padsel0_sel1_wd),
4546: 
4547:     // from internal hardware
4548:     .de     (1'b0),
4549:     .d      ('0  ),
4550: 
4551:     // to internal hardware
4552:     .qe     (),
4553:     .q      (reg2hw.wkup_detector_padsel[1].q ),
4554: 
4555:     // to register interface (read)
4556:     .qs     (wkup_detector_padsel0_sel1_qs)
4557:   );
4558: 
4559: 
4560:   // F[sel2]: 14:10
4561:   prim_subreg #(
4562:     .DW      (5),
4563:     .SWACCESS("RW"),
4564:     .RESVAL  (5'h0)
4565:   ) u_wkup_detector_padsel0_sel2 (
4566:     .clk_i   (clk_i    ),
4567:     .rst_ni  (rst_ni  ),
4568: 
4569:     // from register interface (qualified with register enable)
4570:     .we     (wkup_detector_padsel0_sel2_we & regen_qs),
4571:     .wd     (wkup_detector_padsel0_sel2_wd),
4572: 
4573:     // from internal hardware
4574:     .de     (1'b0),
4575:     .d      ('0  ),
4576: 
4577:     // to internal hardware
4578:     .qe     (),
4579:     .q      (reg2hw.wkup_detector_padsel[2].q ),
4580: 
4581:     // to register interface (read)
4582:     .qs     (wkup_detector_padsel0_sel2_qs)
4583:   );
4584: 
4585: 
4586:   // F[sel3]: 19:15
4587:   prim_subreg #(
4588:     .DW      (5),
4589:     .SWACCESS("RW"),
4590:     .RESVAL  (5'h0)
4591:   ) u_wkup_detector_padsel0_sel3 (
4592:     .clk_i   (clk_i    ),
4593:     .rst_ni  (rst_ni  ),
4594: 
4595:     // from register interface (qualified with register enable)
4596:     .we     (wkup_detector_padsel0_sel3_we & regen_qs),
4597:     .wd     (wkup_detector_padsel0_sel3_wd),
4598: 
4599:     // from internal hardware
4600:     .de     (1'b0),
4601:     .d      ('0  ),
4602: 
4603:     // to internal hardware
4604:     .qe     (),
4605:     .q      (reg2hw.wkup_detector_padsel[3].q ),
4606: 
4607:     // to register interface (read)
4608:     .qs     (wkup_detector_padsel0_sel3_qs)
4609:   );
4610: 
4611: 
4612:   // F[sel4]: 24:20
4613:   prim_subreg #(
4614:     .DW      (5),
4615:     .SWACCESS("RW"),
4616:     .RESVAL  (5'h0)
4617:   ) u_wkup_detector_padsel0_sel4 (
4618:     .clk_i   (clk_i    ),
4619:     .rst_ni  (rst_ni  ),
4620: 
4621:     // from register interface (qualified with register enable)
4622:     .we     (wkup_detector_padsel0_sel4_we & regen_qs),
4623:     .wd     (wkup_detector_padsel0_sel4_wd),
4624: 
4625:     // from internal hardware
4626:     .de     (1'b0),
4627:     .d      ('0  ),
4628: 
4629:     // to internal hardware
4630:     .qe     (),
4631:     .q      (reg2hw.wkup_detector_padsel[4].q ),
4632: 
4633:     // to register interface (read)
4634:     .qs     (wkup_detector_padsel0_sel4_qs)
4635:   );
4636: 
4637: 
4638:   // F[sel5]: 29:25
4639:   prim_subreg #(
4640:     .DW      (5),
4641:     .SWACCESS("RW"),
4642:     .RESVAL  (5'h0)
4643:   ) u_wkup_detector_padsel0_sel5 (
4644:     .clk_i   (clk_i    ),
4645:     .rst_ni  (rst_ni  ),
4646: 
4647:     // from register interface (qualified with register enable)
4648:     .we     (wkup_detector_padsel0_sel5_we & regen_qs),
4649:     .wd     (wkup_detector_padsel0_sel5_wd),
4650: 
4651:     // from internal hardware
4652:     .de     (1'b0),
4653:     .d      ('0  ),
4654: 
4655:     // to internal hardware
4656:     .qe     (),
4657:     .q      (reg2hw.wkup_detector_padsel[5].q ),
4658: 
4659:     // to register interface (read)
4660:     .qs     (wkup_detector_padsel0_sel5_qs)
4661:   );
4662: 
4663: 
4664:   // Subregister 6 of Multireg wkup_detector_padsel
4665:   // R[wkup_detector_padsel1]: V(False)
4666: 
4667:   // F[sel6]: 4:0
4668:   prim_subreg #(
4669:     .DW      (5),
4670:     .SWACCESS("RW"),
4671:     .RESVAL  (5'h0)
4672:   ) u_wkup_detector_padsel1_sel6 (
4673:     .clk_i   (clk_i    ),
4674:     .rst_ni  (rst_ni  ),
4675: 
4676:     // from register interface (qualified with register enable)
4677:     .we     (wkup_detector_padsel1_sel6_we & regen_qs),
4678:     .wd     (wkup_detector_padsel1_sel6_wd),
4679: 
4680:     // from internal hardware
4681:     .de     (1'b0),
4682:     .d      ('0  ),
4683: 
4684:     // to internal hardware
4685:     .qe     (),
4686:     .q      (reg2hw.wkup_detector_padsel[6].q ),
4687: 
4688:     // to register interface (read)
4689:     .qs     (wkup_detector_padsel1_sel6_qs)
4690:   );
4691: 
4692: 
4693:   // F[sel7]: 9:5
4694:   prim_subreg #(
4695:     .DW      (5),
4696:     .SWACCESS("RW"),
4697:     .RESVAL  (5'h0)
4698:   ) u_wkup_detector_padsel1_sel7 (
4699:     .clk_i   (clk_i    ),
4700:     .rst_ni  (rst_ni  ),
4701: 
4702:     // from register interface (qualified with register enable)
4703:     .we     (wkup_detector_padsel1_sel7_we & regen_qs),
4704:     .wd     (wkup_detector_padsel1_sel7_wd),
4705: 
4706:     // from internal hardware
4707:     .de     (1'b0),
4708:     .d      ('0  ),
4709: 
4710:     // to internal hardware
4711:     .qe     (),
4712:     .q      (reg2hw.wkup_detector_padsel[7].q ),
4713: 
4714:     // to register interface (read)
4715:     .qs     (wkup_detector_padsel1_sel7_qs)
4716:   );
4717: 
4718: 
4719: 
4720: 
4721:   // Subregister 0 of Multireg wkup_cause
4722:   // R[wkup_cause]: V(True)
4723: 
4724:   // F[cause0]: 0:0
4725:   prim_subreg_ext #(
4726:     .DW    (1)
4727:   ) u_wkup_cause_cause0 (
4728:     .re     (wkup_cause_cause0_re),
4729:     // qualified with register enable
4730:     .we     (wkup_cause_cause0_we & regen_qs),
4731:     .wd     (wkup_cause_cause0_wd),
4732:     .d      (hw2reg.wkup_cause[0].d),
4733:     .qre    (),
4734:     .qe     (reg2hw.wkup_cause[0].qe),
4735:     .q      (reg2hw.wkup_cause[0].q ),
4736:     .qs     (wkup_cause_cause0_qs)
4737:   );
4738: 
4739: 
4740:   // F[cause1]: 1:1
4741:   prim_subreg_ext #(
4742:     .DW    (1)
4743:   ) u_wkup_cause_cause1 (
4744:     .re     (wkup_cause_cause1_re),
4745:     // qualified with register enable
4746:     .we     (wkup_cause_cause1_we & regen_qs),
4747:     .wd     (wkup_cause_cause1_wd),
4748:     .d      (hw2reg.wkup_cause[1].d),
4749:     .qre    (),
4750:     .qe     (reg2hw.wkup_cause[1].qe),
4751:     .q      (reg2hw.wkup_cause[1].q ),
4752:     .qs     (wkup_cause_cause1_qs)
4753:   );
4754: 
4755: 
4756:   // F[cause2]: 2:2
4757:   prim_subreg_ext #(
4758:     .DW    (1)
4759:   ) u_wkup_cause_cause2 (
4760:     .re     (wkup_cause_cause2_re),
4761:     // qualified with register enable
4762:     .we     (wkup_cause_cause2_we & regen_qs),
4763:     .wd     (wkup_cause_cause2_wd),
4764:     .d      (hw2reg.wkup_cause[2].d),
4765:     .qre    (),
4766:     .qe     (reg2hw.wkup_cause[2].qe),
4767:     .q      (reg2hw.wkup_cause[2].q ),
4768:     .qs     (wkup_cause_cause2_qs)
4769:   );
4770: 
4771: 
4772:   // F[cause3]: 3:3
4773:   prim_subreg_ext #(
4774:     .DW    (1)
4775:   ) u_wkup_cause_cause3 (
4776:     .re     (wkup_cause_cause3_re),
4777:     // qualified with register enable
4778:     .we     (wkup_cause_cause3_we & regen_qs),
4779:     .wd     (wkup_cause_cause3_wd),
4780:     .d      (hw2reg.wkup_cause[3].d),
4781:     .qre    (),
4782:     .qe     (reg2hw.wkup_cause[3].qe),
4783:     .q      (reg2hw.wkup_cause[3].q ),
4784:     .qs     (wkup_cause_cause3_qs)
4785:   );
4786: 
4787: 
4788:   // F[cause4]: 4:4
4789:   prim_subreg_ext #(
4790:     .DW    (1)
4791:   ) u_wkup_cause_cause4 (
4792:     .re     (wkup_cause_cause4_re),
4793:     // qualified with register enable
4794:     .we     (wkup_cause_cause4_we & regen_qs),
4795:     .wd     (wkup_cause_cause4_wd),
4796:     .d      (hw2reg.wkup_cause[4].d),
4797:     .qre    (),
4798:     .qe     (reg2hw.wkup_cause[4].qe),
4799:     .q      (reg2hw.wkup_cause[4].q ),
4800:     .qs     (wkup_cause_cause4_qs)
4801:   );
4802: 
4803: 
4804:   // F[cause5]: 5:5
4805:   prim_subreg_ext #(
4806:     .DW    (1)
4807:   ) u_wkup_cause_cause5 (
4808:     .re     (wkup_cause_cause5_re),
4809:     // qualified with register enable
4810:     .we     (wkup_cause_cause5_we & regen_qs),
4811:     .wd     (wkup_cause_cause5_wd),
4812:     .d      (hw2reg.wkup_cause[5].d),
4813:     .qre    (),
4814:     .qe     (reg2hw.wkup_cause[5].qe),
4815:     .q      (reg2hw.wkup_cause[5].q ),
4816:     .qs     (wkup_cause_cause5_qs)
4817:   );
4818: 
4819: 
4820:   // F[cause6]: 6:6
4821:   prim_subreg_ext #(
4822:     .DW    (1)
4823:   ) u_wkup_cause_cause6 (
4824:     .re     (wkup_cause_cause6_re),
4825:     // qualified with register enable
4826:     .we     (wkup_cause_cause6_we & regen_qs),
4827:     .wd     (wkup_cause_cause6_wd),
4828:     .d      (hw2reg.wkup_cause[6].d),
4829:     .qre    (),
4830:     .qe     (reg2hw.wkup_cause[6].qe),
4831:     .q      (reg2hw.wkup_cause[6].q ),
4832:     .qs     (wkup_cause_cause6_qs)
4833:   );
4834: 
4835: 
4836:   // F[cause7]: 7:7
4837:   prim_subreg_ext #(
4838:     .DW    (1)
4839:   ) u_wkup_cause_cause7 (
4840:     .re     (wkup_cause_cause7_re),
4841:     // qualified with register enable
4842:     .we     (wkup_cause_cause7_we & regen_qs),
4843:     .wd     (wkup_cause_cause7_wd),
4844:     .d      (hw2reg.wkup_cause[7].d),
4845:     .qre    (),
4846:     .qe     (reg2hw.wkup_cause[7].qe),
4847:     .q      (reg2hw.wkup_cause[7].q ),
4848:     .qs     (wkup_cause_cause7_qs)
4849:   );
4850: 
4851: 
4852: 
4853: 
4854: 
4855:   logic [31:0] addr_hit;
4856:   always_comb begin
4857:     addr_hit = '0;
4858:     addr_hit[ 0] = (reg_addr == PINMUX_REGEN_OFFSET);
4859:     addr_hit[ 1] = (reg_addr == PINMUX_PERIPH_INSEL0_OFFSET);
4860:     addr_hit[ 2] = (reg_addr == PINMUX_PERIPH_INSEL1_OFFSET);
4861:     addr_hit[ 3] = (reg_addr == PINMUX_PERIPH_INSEL2_OFFSET);
4862:     addr_hit[ 4] = (reg_addr == PINMUX_PERIPH_INSEL3_OFFSET);
4863:     addr_hit[ 5] = (reg_addr == PINMUX_PERIPH_INSEL4_OFFSET);
4864:     addr_hit[ 6] = (reg_addr == PINMUX_PERIPH_INSEL5_OFFSET);
4865:     addr_hit[ 7] = (reg_addr == PINMUX_PERIPH_INSEL6_OFFSET);
4866:     addr_hit[ 8] = (reg_addr == PINMUX_MIO_OUTSEL0_OFFSET);
4867:     addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL1_OFFSET);
4868:     addr_hit[10] = (reg_addr == PINMUX_MIO_OUTSEL2_OFFSET);
4869:     addr_hit[11] = (reg_addr == PINMUX_MIO_OUTSEL3_OFFSET);
4870:     addr_hit[12] = (reg_addr == PINMUX_MIO_OUTSEL4_OFFSET);
4871:     addr_hit[13] = (reg_addr == PINMUX_MIO_OUTSEL5_OFFSET);
4872:     addr_hit[14] = (reg_addr == PINMUX_MIO_OUTSEL6_OFFSET);
4873:     addr_hit[15] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL0_OFFSET);
4874:     addr_hit[16] = (reg_addr == PINMUX_MIO_OUT_SLEEP_VAL1_OFFSET);
4875:     addr_hit[17] = (reg_addr == PINMUX_DIO_OUT_SLEEP_VAL_OFFSET);
4876:     addr_hit[18] = (reg_addr == PINMUX_WKUP_DETECTOR_EN_OFFSET);
4877:     addr_hit[19] = (reg_addr == PINMUX_WKUP_DETECTOR0_OFFSET);
4878:     addr_hit[20] = (reg_addr == PINMUX_WKUP_DETECTOR1_OFFSET);
4879:     addr_hit[21] = (reg_addr == PINMUX_WKUP_DETECTOR2_OFFSET);
4880:     addr_hit[22] = (reg_addr == PINMUX_WKUP_DETECTOR3_OFFSET);
4881:     addr_hit[23] = (reg_addr == PINMUX_WKUP_DETECTOR4_OFFSET);
4882:     addr_hit[24] = (reg_addr == PINMUX_WKUP_DETECTOR5_OFFSET);
4883:     addr_hit[25] = (reg_addr == PINMUX_WKUP_DETECTOR6_OFFSET);
4884:     addr_hit[26] = (reg_addr == PINMUX_WKUP_DETECTOR7_OFFSET);
4885:     addr_hit[27] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH0_OFFSET);
4886:     addr_hit[28] = (reg_addr == PINMUX_WKUP_DETECTOR_CNT_TH1_OFFSET);
4887:     addr_hit[29] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL0_OFFSET);
4888:     addr_hit[30] = (reg_addr == PINMUX_WKUP_DETECTOR_PADSEL1_OFFSET);
4889:     addr_hit[31] = (reg_addr == PINMUX_WKUP_CAUSE_OFFSET);
4890:   end
4891: 
4892:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
4893: 
4894:   // Check sub-word write is permitted
4895:   always_comb begin
4896:     wr_err = 1'b0;
4897:     if (addr_hit[ 0] && reg_we && (PINMUX_PERMIT[ 0] != (PINMUX_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
4898:     if (addr_hit[ 1] && reg_we && (PINMUX_PERMIT[ 1] != (PINMUX_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
4899:     if (addr_hit[ 2] && reg_we && (PINMUX_PERMIT[ 2] != (PINMUX_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
4900:     if (addr_hit[ 3] && reg_we && (PINMUX_PERMIT[ 3] != (PINMUX_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
4901:     if (addr_hit[ 4] && reg_we && (PINMUX_PERMIT[ 4] != (PINMUX_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
4902:     if (addr_hit[ 5] && reg_we && (PINMUX_PERMIT[ 5] != (PINMUX_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
4903:     if (addr_hit[ 6] && reg_we && (PINMUX_PERMIT[ 6] != (PINMUX_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
4904:     if (addr_hit[ 7] && reg_we && (PINMUX_PERMIT[ 7] != (PINMUX_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
4905:     if (addr_hit[ 8] && reg_we && (PINMUX_PERMIT[ 8] != (PINMUX_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
4906:     if (addr_hit[ 9] && reg_we && (PINMUX_PERMIT[ 9] != (PINMUX_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
4907:     if (addr_hit[10] && reg_we && (PINMUX_PERMIT[10] != (PINMUX_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
4908:     if (addr_hit[11] && reg_we && (PINMUX_PERMIT[11] != (PINMUX_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
4909:     if (addr_hit[12] && reg_we && (PINMUX_PERMIT[12] != (PINMUX_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
4910:     if (addr_hit[13] && reg_we && (PINMUX_PERMIT[13] != (PINMUX_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
4911:     if (addr_hit[14] && reg_we && (PINMUX_PERMIT[14] != (PINMUX_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
4912:     if (addr_hit[15] && reg_we && (PINMUX_PERMIT[15] != (PINMUX_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
4913:     if (addr_hit[16] && reg_we && (PINMUX_PERMIT[16] != (PINMUX_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
4914:     if (addr_hit[17] && reg_we && (PINMUX_PERMIT[17] != (PINMUX_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
4915:     if (addr_hit[18] && reg_we && (PINMUX_PERMIT[18] != (PINMUX_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
4916:     if (addr_hit[19] && reg_we && (PINMUX_PERMIT[19] != (PINMUX_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
4917:     if (addr_hit[20] && reg_we && (PINMUX_PERMIT[20] != (PINMUX_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
4918:     if (addr_hit[21] && reg_we && (PINMUX_PERMIT[21] != (PINMUX_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
4919:     if (addr_hit[22] && reg_we && (PINMUX_PERMIT[22] != (PINMUX_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
4920:     if (addr_hit[23] && reg_we && (PINMUX_PERMIT[23] != (PINMUX_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
4921:     if (addr_hit[24] && reg_we && (PINMUX_PERMIT[24] != (PINMUX_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
4922:     if (addr_hit[25] && reg_we && (PINMUX_PERMIT[25] != (PINMUX_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
4923:     if (addr_hit[26] && reg_we && (PINMUX_PERMIT[26] != (PINMUX_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
4924:     if (addr_hit[27] && reg_we && (PINMUX_PERMIT[27] != (PINMUX_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
4925:     if (addr_hit[28] && reg_we && (PINMUX_PERMIT[28] != (PINMUX_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
4926:     if (addr_hit[29] && reg_we && (PINMUX_PERMIT[29] != (PINMUX_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
4927:     if (addr_hit[30] && reg_we && (PINMUX_PERMIT[30] != (PINMUX_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
4928:     if (addr_hit[31] && reg_we && (PINMUX_PERMIT[31] != (PINMUX_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
4929:   end
4930: 
4931:   assign regen_we = addr_hit[0] & reg_we & ~wr_err;
4932:   assign regen_wd = reg_wdata[0];
4933: 
4934:   assign periph_insel0_in0_we = addr_hit[1] & reg_we & ~wr_err;
4935:   assign periph_insel0_in0_wd = reg_wdata[5:0];
4936: 
4937:   assign periph_insel0_in1_we = addr_hit[1] & reg_we & ~wr_err;
4938:   assign periph_insel0_in1_wd = reg_wdata[11:6];
4939: 
4940:   assign periph_insel0_in2_we = addr_hit[1] & reg_we & ~wr_err;
4941:   assign periph_insel0_in2_wd = reg_wdata[17:12];
4942: 
4943:   assign periph_insel0_in3_we = addr_hit[1] & reg_we & ~wr_err;
4944:   assign periph_insel0_in3_wd = reg_wdata[23:18];
4945: 
4946:   assign periph_insel0_in4_we = addr_hit[1] & reg_we & ~wr_err;
4947:   assign periph_insel0_in4_wd = reg_wdata[29:24];
4948: 
4949:   assign periph_insel1_in5_we = addr_hit[2] & reg_we & ~wr_err;
4950:   assign periph_insel1_in5_wd = reg_wdata[5:0];
4951: 
4952:   assign periph_insel1_in6_we = addr_hit[2] & reg_we & ~wr_err;
4953:   assign periph_insel1_in6_wd = reg_wdata[11:6];
4954: 
4955:   assign periph_insel1_in7_we = addr_hit[2] & reg_we & ~wr_err;
4956:   assign periph_insel1_in7_wd = reg_wdata[17:12];
4957: 
4958:   assign periph_insel1_in8_we = addr_hit[2] & reg_we & ~wr_err;
4959:   assign periph_insel1_in8_wd = reg_wdata[23:18];
4960: 
4961:   assign periph_insel1_in9_we = addr_hit[2] & reg_we & ~wr_err;
4962:   assign periph_insel1_in9_wd = reg_wdata[29:24];
4963: 
4964:   assign periph_insel2_in10_we = addr_hit[3] & reg_we & ~wr_err;
4965:   assign periph_insel2_in10_wd = reg_wdata[5:0];
4966: 
4967:   assign periph_insel2_in11_we = addr_hit[3] & reg_we & ~wr_err;
4968:   assign periph_insel2_in11_wd = reg_wdata[11:6];
4969: 
4970:   assign periph_insel2_in12_we = addr_hit[3] & reg_we & ~wr_err;
4971:   assign periph_insel2_in12_wd = reg_wdata[17:12];
4972: 
4973:   assign periph_insel2_in13_we = addr_hit[3] & reg_we & ~wr_err;
4974:   assign periph_insel2_in13_wd = reg_wdata[23:18];
4975: 
4976:   assign periph_insel2_in14_we = addr_hit[3] & reg_we & ~wr_err;
4977:   assign periph_insel2_in14_wd = reg_wdata[29:24];
4978: 
4979:   assign periph_insel3_in15_we = addr_hit[4] & reg_we & ~wr_err;
4980:   assign periph_insel3_in15_wd = reg_wdata[5:0];
4981: 
4982:   assign periph_insel3_in16_we = addr_hit[4] & reg_we & ~wr_err;
4983:   assign periph_insel3_in16_wd = reg_wdata[11:6];
4984: 
4985:   assign periph_insel3_in17_we = addr_hit[4] & reg_we & ~wr_err;
4986:   assign periph_insel3_in17_wd = reg_wdata[17:12];
4987: 
4988:   assign periph_insel3_in18_we = addr_hit[4] & reg_we & ~wr_err;
4989:   assign periph_insel3_in18_wd = reg_wdata[23:18];
4990: 
4991:   assign periph_insel3_in19_we = addr_hit[4] & reg_we & ~wr_err;
4992:   assign periph_insel3_in19_wd = reg_wdata[29:24];
4993: 
4994:   assign periph_insel4_in20_we = addr_hit[5] & reg_we & ~wr_err;
4995:   assign periph_insel4_in20_wd = reg_wdata[5:0];
4996: 
4997:   assign periph_insel4_in21_we = addr_hit[5] & reg_we & ~wr_err;
4998:   assign periph_insel4_in21_wd = reg_wdata[11:6];
4999: 
5000:   assign periph_insel4_in22_we = addr_hit[5] & reg_we & ~wr_err;
5001:   assign periph_insel4_in22_wd = reg_wdata[17:12];
5002: 
5003:   assign periph_insel4_in23_we = addr_hit[5] & reg_we & ~wr_err;
5004:   assign periph_insel4_in23_wd = reg_wdata[23:18];
5005: 
5006:   assign periph_insel4_in24_we = addr_hit[5] & reg_we & ~wr_err;
5007:   assign periph_insel4_in24_wd = reg_wdata[29:24];
5008: 
5009:   assign periph_insel5_in25_we = addr_hit[6] & reg_we & ~wr_err;
5010:   assign periph_insel5_in25_wd = reg_wdata[5:0];
5011: 
5012:   assign periph_insel5_in26_we = addr_hit[6] & reg_we & ~wr_err;
5013:   assign periph_insel5_in26_wd = reg_wdata[11:6];
5014: 
5015:   assign periph_insel5_in27_we = addr_hit[6] & reg_we & ~wr_err;
5016:   assign periph_insel5_in27_wd = reg_wdata[17:12];
5017: 
5018:   assign periph_insel5_in28_we = addr_hit[6] & reg_we & ~wr_err;
5019:   assign periph_insel5_in28_wd = reg_wdata[23:18];
5020: 
5021:   assign periph_insel5_in29_we = addr_hit[6] & reg_we & ~wr_err;
5022:   assign periph_insel5_in29_wd = reg_wdata[29:24];
5023: 
5024:   assign periph_insel6_in30_we = addr_hit[7] & reg_we & ~wr_err;
5025:   assign periph_insel6_in30_wd = reg_wdata[5:0];
5026: 
5027:   assign periph_insel6_in31_we = addr_hit[7] & reg_we & ~wr_err;
5028:   assign periph_insel6_in31_wd = reg_wdata[11:6];
5029: 
5030:   assign mio_outsel0_out0_we = addr_hit[8] & reg_we & ~wr_err;
5031:   assign mio_outsel0_out0_wd = reg_wdata[5:0];
5032: 
5033:   assign mio_outsel0_out1_we = addr_hit[8] & reg_we & ~wr_err;
5034:   assign mio_outsel0_out1_wd = reg_wdata[11:6];
5035: 
5036:   assign mio_outsel0_out2_we = addr_hit[8] & reg_we & ~wr_err;
5037:   assign mio_outsel0_out2_wd = reg_wdata[17:12];
5038: 
5039:   assign mio_outsel0_out3_we = addr_hit[8] & reg_we & ~wr_err;
5040:   assign mio_outsel0_out3_wd = reg_wdata[23:18];
5041: 
5042:   assign mio_outsel0_out4_we = addr_hit[8] & reg_we & ~wr_err;
5043:   assign mio_outsel0_out4_wd = reg_wdata[29:24];
5044: 
5045:   assign mio_outsel1_out5_we = addr_hit[9] & reg_we & ~wr_err;
5046:   assign mio_outsel1_out5_wd = reg_wdata[5:0];
5047: 
5048:   assign mio_outsel1_out6_we = addr_hit[9] & reg_we & ~wr_err;
5049:   assign mio_outsel1_out6_wd = reg_wdata[11:6];
5050: 
5051:   assign mio_outsel1_out7_we = addr_hit[9] & reg_we & ~wr_err;
5052:   assign mio_outsel1_out7_wd = reg_wdata[17:12];
5053: 
5054:   assign mio_outsel1_out8_we = addr_hit[9] & reg_we & ~wr_err;
5055:   assign mio_outsel1_out8_wd = reg_wdata[23:18];
5056: 
5057:   assign mio_outsel1_out9_we = addr_hit[9] & reg_we & ~wr_err;
5058:   assign mio_outsel1_out9_wd = reg_wdata[29:24];
5059: 
5060:   assign mio_outsel2_out10_we = addr_hit[10] & reg_we & ~wr_err;
5061:   assign mio_outsel2_out10_wd = reg_wdata[5:0];
5062: 
5063:   assign mio_outsel2_out11_we = addr_hit[10] & reg_we & ~wr_err;
5064:   assign mio_outsel2_out11_wd = reg_wdata[11:6];
5065: 
5066:   assign mio_outsel2_out12_we = addr_hit[10] & reg_we & ~wr_err;
5067:   assign mio_outsel2_out12_wd = reg_wdata[17:12];
5068: 
5069:   assign mio_outsel2_out13_we = addr_hit[10] & reg_we & ~wr_err;
5070:   assign mio_outsel2_out13_wd = reg_wdata[23:18];
5071: 
5072:   assign mio_outsel2_out14_we = addr_hit[10] & reg_we & ~wr_err;
5073:   assign mio_outsel2_out14_wd = reg_wdata[29:24];
5074: 
5075:   assign mio_outsel3_out15_we = addr_hit[11] & reg_we & ~wr_err;
5076:   assign mio_outsel3_out15_wd = reg_wdata[5:0];
5077: 
5078:   assign mio_outsel3_out16_we = addr_hit[11] & reg_we & ~wr_err;
5079:   assign mio_outsel3_out16_wd = reg_wdata[11:6];
5080: 
5081:   assign mio_outsel3_out17_we = addr_hit[11] & reg_we & ~wr_err;
5082:   assign mio_outsel3_out17_wd = reg_wdata[17:12];
5083: 
5084:   assign mio_outsel3_out18_we = addr_hit[11] & reg_we & ~wr_err;
5085:   assign mio_outsel3_out18_wd = reg_wdata[23:18];
5086: 
5087:   assign mio_outsel3_out19_we = addr_hit[11] & reg_we & ~wr_err;
5088:   assign mio_outsel3_out19_wd = reg_wdata[29:24];
5089: 
5090:   assign mio_outsel4_out20_we = addr_hit[12] & reg_we & ~wr_err;
5091:   assign mio_outsel4_out20_wd = reg_wdata[5:0];
5092: 
5093:   assign mio_outsel4_out21_we = addr_hit[12] & reg_we & ~wr_err;
5094:   assign mio_outsel4_out21_wd = reg_wdata[11:6];
5095: 
5096:   assign mio_outsel4_out22_we = addr_hit[12] & reg_we & ~wr_err;
5097:   assign mio_outsel4_out22_wd = reg_wdata[17:12];
5098: 
5099:   assign mio_outsel4_out23_we = addr_hit[12] & reg_we & ~wr_err;
5100:   assign mio_outsel4_out23_wd = reg_wdata[23:18];
5101: 
5102:   assign mio_outsel4_out24_we = addr_hit[12] & reg_we & ~wr_err;
5103:   assign mio_outsel4_out24_wd = reg_wdata[29:24];
5104: 
5105:   assign mio_outsel5_out25_we = addr_hit[13] & reg_we & ~wr_err;
5106:   assign mio_outsel5_out25_wd = reg_wdata[5:0];
5107: 
5108:   assign mio_outsel5_out26_we = addr_hit[13] & reg_we & ~wr_err;
5109:   assign mio_outsel5_out26_wd = reg_wdata[11:6];
5110: 
5111:   assign mio_outsel5_out27_we = addr_hit[13] & reg_we & ~wr_err;
5112:   assign mio_outsel5_out27_wd = reg_wdata[17:12];
5113: 
5114:   assign mio_outsel5_out28_we = addr_hit[13] & reg_we & ~wr_err;
5115:   assign mio_outsel5_out28_wd = reg_wdata[23:18];
5116: 
5117:   assign mio_outsel5_out29_we = addr_hit[13] & reg_we & ~wr_err;
5118:   assign mio_outsel5_out29_wd = reg_wdata[29:24];
5119: 
5120:   assign mio_outsel6_out30_we = addr_hit[14] & reg_we & ~wr_err;
5121:   assign mio_outsel6_out30_wd = reg_wdata[5:0];
5122: 
5123:   assign mio_outsel6_out31_we = addr_hit[14] & reg_we & ~wr_err;
5124:   assign mio_outsel6_out31_wd = reg_wdata[11:6];
5125: 
5126:   assign mio_out_sleep_val0_out0_we = addr_hit[15] & reg_we & ~wr_err;
5127:   assign mio_out_sleep_val0_out0_wd = reg_wdata[1:0];
5128: 
5129:   assign mio_out_sleep_val0_out1_we = addr_hit[15] & reg_we & ~wr_err;
5130:   assign mio_out_sleep_val0_out1_wd = reg_wdata[3:2];
5131: 
5132:   assign mio_out_sleep_val0_out2_we = addr_hit[15] & reg_we & ~wr_err;
5133:   assign mio_out_sleep_val0_out2_wd = reg_wdata[5:4];
5134: 
5135:   assign mio_out_sleep_val0_out3_we = addr_hit[15] & reg_we & ~wr_err;
5136:   assign mio_out_sleep_val0_out3_wd = reg_wdata[7:6];
5137: 
5138:   assign mio_out_sleep_val0_out4_we = addr_hit[15] & reg_we & ~wr_err;
5139:   assign mio_out_sleep_val0_out4_wd = reg_wdata[9:8];
5140: 
5141:   assign mio_out_sleep_val0_out5_we = addr_hit[15] & reg_we & ~wr_err;
5142:   assign mio_out_sleep_val0_out5_wd = reg_wdata[11:10];
5143: 
5144:   assign mio_out_sleep_val0_out6_we = addr_hit[15] & reg_we & ~wr_err;
5145:   assign mio_out_sleep_val0_out6_wd = reg_wdata[13:12];
5146: 
5147:   assign mio_out_sleep_val0_out7_we = addr_hit[15] & reg_we & ~wr_err;
5148:   assign mio_out_sleep_val0_out7_wd = reg_wdata[15:14];
5149: 
5150:   assign mio_out_sleep_val0_out8_we = addr_hit[15] & reg_we & ~wr_err;
5151:   assign mio_out_sleep_val0_out8_wd = reg_wdata[17:16];
5152: 
5153:   assign mio_out_sleep_val0_out9_we = addr_hit[15] & reg_we & ~wr_err;
5154:   assign mio_out_sleep_val0_out9_wd = reg_wdata[19:18];
5155: 
5156:   assign mio_out_sleep_val0_out10_we = addr_hit[15] & reg_we & ~wr_err;
5157:   assign mio_out_sleep_val0_out10_wd = reg_wdata[21:20];
5158: 
5159:   assign mio_out_sleep_val0_out11_we = addr_hit[15] & reg_we & ~wr_err;
5160:   assign mio_out_sleep_val0_out11_wd = reg_wdata[23:22];
5161: 
5162:   assign mio_out_sleep_val0_out12_we = addr_hit[15] & reg_we & ~wr_err;
5163:   assign mio_out_sleep_val0_out12_wd = reg_wdata[25:24];
5164: 
5165:   assign mio_out_sleep_val0_out13_we = addr_hit[15] & reg_we & ~wr_err;
5166:   assign mio_out_sleep_val0_out13_wd = reg_wdata[27:26];
5167: 
5168:   assign mio_out_sleep_val0_out14_we = addr_hit[15] & reg_we & ~wr_err;
5169:   assign mio_out_sleep_val0_out14_wd = reg_wdata[29:28];
5170: 
5171:   assign mio_out_sleep_val0_out15_we = addr_hit[15] & reg_we & ~wr_err;
5172:   assign mio_out_sleep_val0_out15_wd = reg_wdata[31:30];
5173: 
5174:   assign mio_out_sleep_val1_out16_we = addr_hit[16] & reg_we & ~wr_err;
5175:   assign mio_out_sleep_val1_out16_wd = reg_wdata[1:0];
5176: 
5177:   assign mio_out_sleep_val1_out17_we = addr_hit[16] & reg_we & ~wr_err;
5178:   assign mio_out_sleep_val1_out17_wd = reg_wdata[3:2];
5179: 
5180:   assign mio_out_sleep_val1_out18_we = addr_hit[16] & reg_we & ~wr_err;
5181:   assign mio_out_sleep_val1_out18_wd = reg_wdata[5:4];
5182: 
5183:   assign mio_out_sleep_val1_out19_we = addr_hit[16] & reg_we & ~wr_err;
5184:   assign mio_out_sleep_val1_out19_wd = reg_wdata[7:6];
5185: 
5186:   assign mio_out_sleep_val1_out20_we = addr_hit[16] & reg_we & ~wr_err;
5187:   assign mio_out_sleep_val1_out20_wd = reg_wdata[9:8];
5188: 
5189:   assign mio_out_sleep_val1_out21_we = addr_hit[16] & reg_we & ~wr_err;
5190:   assign mio_out_sleep_val1_out21_wd = reg_wdata[11:10];
5191: 
5192:   assign mio_out_sleep_val1_out22_we = addr_hit[16] & reg_we & ~wr_err;
5193:   assign mio_out_sleep_val1_out22_wd = reg_wdata[13:12];
5194: 
5195:   assign mio_out_sleep_val1_out23_we = addr_hit[16] & reg_we & ~wr_err;
5196:   assign mio_out_sleep_val1_out23_wd = reg_wdata[15:14];
5197: 
5198:   assign mio_out_sleep_val1_out24_we = addr_hit[16] & reg_we & ~wr_err;
5199:   assign mio_out_sleep_val1_out24_wd = reg_wdata[17:16];
5200: 
5201:   assign mio_out_sleep_val1_out25_we = addr_hit[16] & reg_we & ~wr_err;
5202:   assign mio_out_sleep_val1_out25_wd = reg_wdata[19:18];
5203: 
5204:   assign mio_out_sleep_val1_out26_we = addr_hit[16] & reg_we & ~wr_err;
5205:   assign mio_out_sleep_val1_out26_wd = reg_wdata[21:20];
5206: 
5207:   assign mio_out_sleep_val1_out27_we = addr_hit[16] & reg_we & ~wr_err;
5208:   assign mio_out_sleep_val1_out27_wd = reg_wdata[23:22];
5209: 
5210:   assign mio_out_sleep_val1_out28_we = addr_hit[16] & reg_we & ~wr_err;
5211:   assign mio_out_sleep_val1_out28_wd = reg_wdata[25:24];
5212: 
5213:   assign mio_out_sleep_val1_out29_we = addr_hit[16] & reg_we & ~wr_err;
5214:   assign mio_out_sleep_val1_out29_wd = reg_wdata[27:26];
5215: 
5216:   assign mio_out_sleep_val1_out30_we = addr_hit[16] & reg_we & ~wr_err;
5217:   assign mio_out_sleep_val1_out30_wd = reg_wdata[29:28];
5218: 
5219:   assign mio_out_sleep_val1_out31_we = addr_hit[16] & reg_we & ~wr_err;
5220:   assign mio_out_sleep_val1_out31_wd = reg_wdata[31:30];
5221: 
5222:   assign dio_out_sleep_val_out0_we = addr_hit[17] & reg_we & ~wr_err;
5223:   assign dio_out_sleep_val_out0_wd = reg_wdata[1:0];
5224:   assign dio_out_sleep_val_out0_re = addr_hit[17] && reg_re;
5225: 
5226:   assign dio_out_sleep_val_out1_we = addr_hit[17] & reg_we & ~wr_err;
5227:   assign dio_out_sleep_val_out1_wd = reg_wdata[3:2];
5228:   assign dio_out_sleep_val_out1_re = addr_hit[17] && reg_re;
5229: 
5230:   assign dio_out_sleep_val_out2_we = addr_hit[17] & reg_we & ~wr_err;
5231:   assign dio_out_sleep_val_out2_wd = reg_wdata[5:4];
5232:   assign dio_out_sleep_val_out2_re = addr_hit[17] && reg_re;
5233: 
5234:   assign dio_out_sleep_val_out3_we = addr_hit[17] & reg_we & ~wr_err;
5235:   assign dio_out_sleep_val_out3_wd = reg_wdata[7:6];
5236:   assign dio_out_sleep_val_out3_re = addr_hit[17] && reg_re;
5237: 
5238:   assign dio_out_sleep_val_out4_we = addr_hit[17] & reg_we & ~wr_err;
5239:   assign dio_out_sleep_val_out4_wd = reg_wdata[9:8];
5240:   assign dio_out_sleep_val_out4_re = addr_hit[17] && reg_re;
5241: 
5242:   assign dio_out_sleep_val_out5_we = addr_hit[17] & reg_we & ~wr_err;
5243:   assign dio_out_sleep_val_out5_wd = reg_wdata[11:10];
5244:   assign dio_out_sleep_val_out5_re = addr_hit[17] && reg_re;
5245: 
5246:   assign dio_out_sleep_val_out6_we = addr_hit[17] & reg_we & ~wr_err;
5247:   assign dio_out_sleep_val_out6_wd = reg_wdata[13:12];
5248:   assign dio_out_sleep_val_out6_re = addr_hit[17] && reg_re;
5249: 
5250:   assign dio_out_sleep_val_out7_we = addr_hit[17] & reg_we & ~wr_err;
5251:   assign dio_out_sleep_val_out7_wd = reg_wdata[15:14];
5252:   assign dio_out_sleep_val_out7_re = addr_hit[17] && reg_re;
5253: 
5254:   assign dio_out_sleep_val_out8_we = addr_hit[17] & reg_we & ~wr_err;
5255:   assign dio_out_sleep_val_out8_wd = reg_wdata[17:16];
5256:   assign dio_out_sleep_val_out8_re = addr_hit[17] && reg_re;
5257: 
5258:   assign dio_out_sleep_val_out9_we = addr_hit[17] & reg_we & ~wr_err;
5259:   assign dio_out_sleep_val_out9_wd = reg_wdata[19:18];
5260:   assign dio_out_sleep_val_out9_re = addr_hit[17] && reg_re;
5261: 
5262:   assign dio_out_sleep_val_out10_we = addr_hit[17] & reg_we & ~wr_err;
5263:   assign dio_out_sleep_val_out10_wd = reg_wdata[21:20];
5264:   assign dio_out_sleep_val_out10_re = addr_hit[17] && reg_re;
5265: 
5266:   assign dio_out_sleep_val_out11_we = addr_hit[17] & reg_we & ~wr_err;
5267:   assign dio_out_sleep_val_out11_wd = reg_wdata[23:22];
5268:   assign dio_out_sleep_val_out11_re = addr_hit[17] && reg_re;
5269: 
5270:   assign dio_out_sleep_val_out12_we = addr_hit[17] & reg_we & ~wr_err;
5271:   assign dio_out_sleep_val_out12_wd = reg_wdata[25:24];
5272:   assign dio_out_sleep_val_out12_re = addr_hit[17] && reg_re;
5273: 
5274:   assign dio_out_sleep_val_out13_we = addr_hit[17] & reg_we & ~wr_err;
5275:   assign dio_out_sleep_val_out13_wd = reg_wdata[27:26];
5276:   assign dio_out_sleep_val_out13_re = addr_hit[17] && reg_re;
5277: 
5278:   assign dio_out_sleep_val_out14_we = addr_hit[17] & reg_we & ~wr_err;
5279:   assign dio_out_sleep_val_out14_wd = reg_wdata[29:28];
5280:   assign dio_out_sleep_val_out14_re = addr_hit[17] && reg_re;
5281: 
5282:   assign wkup_detector_en_en0_we = addr_hit[18] & reg_we & ~wr_err;
5283:   assign wkup_detector_en_en0_wd = reg_wdata[0];
5284: 
5285:   assign wkup_detector_en_en1_we = addr_hit[18] & reg_we & ~wr_err;
5286:   assign wkup_detector_en_en1_wd = reg_wdata[1];
5287: 
5288:   assign wkup_detector_en_en2_we = addr_hit[18] & reg_we & ~wr_err;
5289:   assign wkup_detector_en_en2_wd = reg_wdata[2];
5290: 
5291:   assign wkup_detector_en_en3_we = addr_hit[18] & reg_we & ~wr_err;
5292:   assign wkup_detector_en_en3_wd = reg_wdata[3];
5293: 
5294:   assign wkup_detector_en_en4_we = addr_hit[18] & reg_we & ~wr_err;
5295:   assign wkup_detector_en_en4_wd = reg_wdata[4];
5296: 
5297:   assign wkup_detector_en_en5_we = addr_hit[18] & reg_we & ~wr_err;
5298:   assign wkup_detector_en_en5_wd = reg_wdata[5];
5299: 
5300:   assign wkup_detector_en_en6_we = addr_hit[18] & reg_we & ~wr_err;
5301:   assign wkup_detector_en_en6_wd = reg_wdata[6];
5302: 
5303:   assign wkup_detector_en_en7_we = addr_hit[18] & reg_we & ~wr_err;
5304:   assign wkup_detector_en_en7_wd = reg_wdata[7];
5305: 
5306:   assign wkup_detector0_mode0_we = addr_hit[19] & reg_we & ~wr_err;
5307:   assign wkup_detector0_mode0_wd = reg_wdata[2:0];
5308: 
5309:   assign wkup_detector0_filter0_we = addr_hit[19] & reg_we & ~wr_err;
5310:   assign wkup_detector0_filter0_wd = reg_wdata[3];
5311: 
5312:   assign wkup_detector0_miodio0_we = addr_hit[19] & reg_we & ~wr_err;
5313:   assign wkup_detector0_miodio0_wd = reg_wdata[4];
5314: 
5315:   assign wkup_detector1_mode1_we = addr_hit[20] & reg_we & ~wr_err;
5316:   assign wkup_detector1_mode1_wd = reg_wdata[2:0];
5317: 
5318:   assign wkup_detector1_filter1_we = addr_hit[20] & reg_we & ~wr_err;
5319:   assign wkup_detector1_filter1_wd = reg_wdata[3];
5320: 
5321:   assign wkup_detector1_miodio1_we = addr_hit[20] & reg_we & ~wr_err;
5322:   assign wkup_detector1_miodio1_wd = reg_wdata[4];
5323: 
5324:   assign wkup_detector2_mode2_we = addr_hit[21] & reg_we & ~wr_err;
5325:   assign wkup_detector2_mode2_wd = reg_wdata[2:0];
5326: 
5327:   assign wkup_detector2_filter2_we = addr_hit[21] & reg_we & ~wr_err;
5328:   assign wkup_detector2_filter2_wd = reg_wdata[3];
5329: 
5330:   assign wkup_detector2_miodio2_we = addr_hit[21] & reg_we & ~wr_err;
5331:   assign wkup_detector2_miodio2_wd = reg_wdata[4];
5332: 
5333:   assign wkup_detector3_mode3_we = addr_hit[22] & reg_we & ~wr_err;
5334:   assign wkup_detector3_mode3_wd = reg_wdata[2:0];
5335: 
5336:   assign wkup_detector3_filter3_we = addr_hit[22] & reg_we & ~wr_err;
5337:   assign wkup_detector3_filter3_wd = reg_wdata[3];
5338: 
5339:   assign wkup_detector3_miodio3_we = addr_hit[22] & reg_we & ~wr_err;
5340:   assign wkup_detector3_miodio3_wd = reg_wdata[4];
5341: 
5342:   assign wkup_detector4_mode4_we = addr_hit[23] & reg_we & ~wr_err;
5343:   assign wkup_detector4_mode4_wd = reg_wdata[2:0];
5344: 
5345:   assign wkup_detector4_filter4_we = addr_hit[23] & reg_we & ~wr_err;
5346:   assign wkup_detector4_filter4_wd = reg_wdata[3];
5347: 
5348:   assign wkup_detector4_miodio4_we = addr_hit[23] & reg_we & ~wr_err;
5349:   assign wkup_detector4_miodio4_wd = reg_wdata[4];
5350: 
5351:   assign wkup_detector5_mode5_we = addr_hit[24] & reg_we & ~wr_err;
5352:   assign wkup_detector5_mode5_wd = reg_wdata[2:0];
5353: 
5354:   assign wkup_detector5_filter5_we = addr_hit[24] & reg_we & ~wr_err;
5355:   assign wkup_detector5_filter5_wd = reg_wdata[3];
5356: 
5357:   assign wkup_detector5_miodio5_we = addr_hit[24] & reg_we & ~wr_err;
5358:   assign wkup_detector5_miodio5_wd = reg_wdata[4];
5359: 
5360:   assign wkup_detector6_mode6_we = addr_hit[25] & reg_we & ~wr_err;
5361:   assign wkup_detector6_mode6_wd = reg_wdata[2:0];
5362: 
5363:   assign wkup_detector6_filter6_we = addr_hit[25] & reg_we & ~wr_err;
5364:   assign wkup_detector6_filter6_wd = reg_wdata[3];
5365: 
5366:   assign wkup_detector6_miodio6_we = addr_hit[25] & reg_we & ~wr_err;
5367:   assign wkup_detector6_miodio6_wd = reg_wdata[4];
5368: 
5369:   assign wkup_detector7_mode7_we = addr_hit[26] & reg_we & ~wr_err;
5370:   assign wkup_detector7_mode7_wd = reg_wdata[2:0];
5371: 
5372:   assign wkup_detector7_filter7_we = addr_hit[26] & reg_we & ~wr_err;
5373:   assign wkup_detector7_filter7_wd = reg_wdata[3];
5374: 
5375:   assign wkup_detector7_miodio7_we = addr_hit[26] & reg_we & ~wr_err;
5376:   assign wkup_detector7_miodio7_wd = reg_wdata[4];
5377: 
5378:   assign wkup_detector_cnt_th0_th0_we = addr_hit[27] & reg_we & ~wr_err;
5379:   assign wkup_detector_cnt_th0_th0_wd = reg_wdata[7:0];
5380: 
5381:   assign wkup_detector_cnt_th0_th1_we = addr_hit[27] & reg_we & ~wr_err;
5382:   assign wkup_detector_cnt_th0_th1_wd = reg_wdata[15:8];
5383: 
5384:   assign wkup_detector_cnt_th0_th2_we = addr_hit[27] & reg_we & ~wr_err;
5385:   assign wkup_detector_cnt_th0_th2_wd = reg_wdata[23:16];
5386: 
5387:   assign wkup_detector_cnt_th0_th3_we = addr_hit[27] & reg_we & ~wr_err;
5388:   assign wkup_detector_cnt_th0_th3_wd = reg_wdata[31:24];
5389: 
5390:   assign wkup_detector_cnt_th1_th4_we = addr_hit[28] & reg_we & ~wr_err;
5391:   assign wkup_detector_cnt_th1_th4_wd = reg_wdata[7:0];
5392: 
5393:   assign wkup_detector_cnt_th1_th5_we = addr_hit[28] & reg_we & ~wr_err;
5394:   assign wkup_detector_cnt_th1_th5_wd = reg_wdata[15:8];
5395: 
5396:   assign wkup_detector_cnt_th1_th6_we = addr_hit[28] & reg_we & ~wr_err;
5397:   assign wkup_detector_cnt_th1_th6_wd = reg_wdata[23:16];
5398: 
5399:   assign wkup_detector_cnt_th1_th7_we = addr_hit[28] & reg_we & ~wr_err;
5400:   assign wkup_detector_cnt_th1_th7_wd = reg_wdata[31:24];
5401: 
5402:   assign wkup_detector_padsel0_sel0_we = addr_hit[29] & reg_we & ~wr_err;
5403:   assign wkup_detector_padsel0_sel0_wd = reg_wdata[4:0];
5404: 
5405:   assign wkup_detector_padsel0_sel1_we = addr_hit[29] & reg_we & ~wr_err;
5406:   assign wkup_detector_padsel0_sel1_wd = reg_wdata[9:5];
5407: 
5408:   assign wkup_detector_padsel0_sel2_we = addr_hit[29] & reg_we & ~wr_err;
5409:   assign wkup_detector_padsel0_sel2_wd = reg_wdata[14:10];
5410: 
5411:   assign wkup_detector_padsel0_sel3_we = addr_hit[29] & reg_we & ~wr_err;
5412:   assign wkup_detector_padsel0_sel3_wd = reg_wdata[19:15];
5413: 
5414:   assign wkup_detector_padsel0_sel4_we = addr_hit[29] & reg_we & ~wr_err;
5415:   assign wkup_detector_padsel0_sel4_wd = reg_wdata[24:20];
5416: 
5417:   assign wkup_detector_padsel0_sel5_we = addr_hit[29] & reg_we & ~wr_err;
5418:   assign wkup_detector_padsel0_sel5_wd = reg_wdata[29:25];
5419: 
5420:   assign wkup_detector_padsel1_sel6_we = addr_hit[30] & reg_we & ~wr_err;
5421:   assign wkup_detector_padsel1_sel6_wd = reg_wdata[4:0];
5422: 
5423:   assign wkup_detector_padsel1_sel7_we = addr_hit[30] & reg_we & ~wr_err;
5424:   assign wkup_detector_padsel1_sel7_wd = reg_wdata[9:5];
5425: 
5426:   assign wkup_cause_cause0_we = addr_hit[31] & reg_we & ~wr_err;
5427:   assign wkup_cause_cause0_wd = reg_wdata[0];
5428:   assign wkup_cause_cause0_re = addr_hit[31] && reg_re;
5429: 
5430:   assign wkup_cause_cause1_we = addr_hit[31] & reg_we & ~wr_err;
5431:   assign wkup_cause_cause1_wd = reg_wdata[1];
5432:   assign wkup_cause_cause1_re = addr_hit[31] && reg_re;
5433: 
5434:   assign wkup_cause_cause2_we = addr_hit[31] & reg_we & ~wr_err;
5435:   assign wkup_cause_cause2_wd = reg_wdata[2];
5436:   assign wkup_cause_cause2_re = addr_hit[31] && reg_re;
5437: 
5438:   assign wkup_cause_cause3_we = addr_hit[31] & reg_we & ~wr_err;
5439:   assign wkup_cause_cause3_wd = reg_wdata[3];
5440:   assign wkup_cause_cause3_re = addr_hit[31] && reg_re;
5441: 
5442:   assign wkup_cause_cause4_we = addr_hit[31] & reg_we & ~wr_err;
5443:   assign wkup_cause_cause4_wd = reg_wdata[4];
5444:   assign wkup_cause_cause4_re = addr_hit[31] && reg_re;
5445: 
5446:   assign wkup_cause_cause5_we = addr_hit[31] & reg_we & ~wr_err;
5447:   assign wkup_cause_cause5_wd = reg_wdata[5];
5448:   assign wkup_cause_cause5_re = addr_hit[31] && reg_re;
5449: 
5450:   assign wkup_cause_cause6_we = addr_hit[31] & reg_we & ~wr_err;
5451:   assign wkup_cause_cause6_wd = reg_wdata[6];
5452:   assign wkup_cause_cause6_re = addr_hit[31] && reg_re;
5453: 
5454:   assign wkup_cause_cause7_we = addr_hit[31] & reg_we & ~wr_err;
5455:   assign wkup_cause_cause7_wd = reg_wdata[7];
5456:   assign wkup_cause_cause7_re = addr_hit[31] && reg_re;
5457: 
5458:   // Read data return
5459:   always_comb begin
5460:     reg_rdata_next = '0;
5461:     unique case (1'b1)
5462:       addr_hit[0]: begin
5463:         reg_rdata_next[0] = regen_qs;
5464:       end
5465: 
5466:       addr_hit[1]: begin
5467:         reg_rdata_next[5:0] = periph_insel0_in0_qs;
5468:         reg_rdata_next[11:6] = periph_insel0_in1_qs;
5469:         reg_rdata_next[17:12] = periph_insel0_in2_qs;
5470:         reg_rdata_next[23:18] = periph_insel0_in3_qs;
5471:         reg_rdata_next[29:24] = periph_insel0_in4_qs;
5472:       end
5473: 
5474:       addr_hit[2]: begin
5475:         reg_rdata_next[5:0] = periph_insel1_in5_qs;
5476:         reg_rdata_next[11:6] = periph_insel1_in6_qs;
5477:         reg_rdata_next[17:12] = periph_insel1_in7_qs;
5478:         reg_rdata_next[23:18] = periph_insel1_in8_qs;
5479:         reg_rdata_next[29:24] = periph_insel1_in9_qs;
5480:       end
5481: 
5482:       addr_hit[3]: begin
5483:         reg_rdata_next[5:0] = periph_insel2_in10_qs;
5484:         reg_rdata_next[11:6] = periph_insel2_in11_qs;
5485:         reg_rdata_next[17:12] = periph_insel2_in12_qs;
5486:         reg_rdata_next[23:18] = periph_insel2_in13_qs;
5487:         reg_rdata_next[29:24] = periph_insel2_in14_qs;
5488:       end
5489: 
5490:       addr_hit[4]: begin
5491:         reg_rdata_next[5:0] = periph_insel3_in15_qs;
5492:         reg_rdata_next[11:6] = periph_insel3_in16_qs;
5493:         reg_rdata_next[17:12] = periph_insel3_in17_qs;
5494:         reg_rdata_next[23:18] = periph_insel3_in18_qs;
5495:         reg_rdata_next[29:24] = periph_insel3_in19_qs;
5496:       end
5497: 
5498:       addr_hit[5]: begin
5499:         reg_rdata_next[5:0] = periph_insel4_in20_qs;
5500:         reg_rdata_next[11:6] = periph_insel4_in21_qs;
5501:         reg_rdata_next[17:12] = periph_insel4_in22_qs;
5502:         reg_rdata_next[23:18] = periph_insel4_in23_qs;
5503:         reg_rdata_next[29:24] = periph_insel4_in24_qs;
5504:       end
5505: 
5506:       addr_hit[6]: begin
5507:         reg_rdata_next[5:0] = periph_insel5_in25_qs;
5508:         reg_rdata_next[11:6] = periph_insel5_in26_qs;
5509:         reg_rdata_next[17:12] = periph_insel5_in27_qs;
5510:         reg_rdata_next[23:18] = periph_insel5_in28_qs;
5511:         reg_rdata_next[29:24] = periph_insel5_in29_qs;
5512:       end
5513: 
5514:       addr_hit[7]: begin
5515:         reg_rdata_next[5:0] = periph_insel6_in30_qs;
5516:         reg_rdata_next[11:6] = periph_insel6_in31_qs;
5517:       end
5518: 
5519:       addr_hit[8]: begin
5520:         reg_rdata_next[5:0] = mio_outsel0_out0_qs;
5521:         reg_rdata_next[11:6] = mio_outsel0_out1_qs;
5522:         reg_rdata_next[17:12] = mio_outsel0_out2_qs;
5523:         reg_rdata_next[23:18] = mio_outsel0_out3_qs;
5524:         reg_rdata_next[29:24] = mio_outsel0_out4_qs;
5525:       end
5526: 
5527:       addr_hit[9]: begin
5528:         reg_rdata_next[5:0] = mio_outsel1_out5_qs;
5529:         reg_rdata_next[11:6] = mio_outsel1_out6_qs;
5530:         reg_rdata_next[17:12] = mio_outsel1_out7_qs;
5531:         reg_rdata_next[23:18] = mio_outsel1_out8_qs;
5532:         reg_rdata_next[29:24] = mio_outsel1_out9_qs;
5533:       end
5534: 
5535:       addr_hit[10]: begin
5536:         reg_rdata_next[5:0] = mio_outsel2_out10_qs;
5537:         reg_rdata_next[11:6] = mio_outsel2_out11_qs;
5538:         reg_rdata_next[17:12] = mio_outsel2_out12_qs;
5539:         reg_rdata_next[23:18] = mio_outsel2_out13_qs;
5540:         reg_rdata_next[29:24] = mio_outsel2_out14_qs;
5541:       end
5542: 
5543:       addr_hit[11]: begin
5544:         reg_rdata_next[5:0] = mio_outsel3_out15_qs;
5545:         reg_rdata_next[11:6] = mio_outsel3_out16_qs;
5546:         reg_rdata_next[17:12] = mio_outsel3_out17_qs;
5547:         reg_rdata_next[23:18] = mio_outsel3_out18_qs;
5548:         reg_rdata_next[29:24] = mio_outsel3_out19_qs;
5549:       end
5550: 
5551:       addr_hit[12]: begin
5552:         reg_rdata_next[5:0] = mio_outsel4_out20_qs;
5553:         reg_rdata_next[11:6] = mio_outsel4_out21_qs;
5554:         reg_rdata_next[17:12] = mio_outsel4_out22_qs;
5555:         reg_rdata_next[23:18] = mio_outsel4_out23_qs;
5556:         reg_rdata_next[29:24] = mio_outsel4_out24_qs;
5557:       end
5558: 
5559:       addr_hit[13]: begin
5560:         reg_rdata_next[5:0] = mio_outsel5_out25_qs;
5561:         reg_rdata_next[11:6] = mio_outsel5_out26_qs;
5562:         reg_rdata_next[17:12] = mio_outsel5_out27_qs;
5563:         reg_rdata_next[23:18] = mio_outsel5_out28_qs;
5564:         reg_rdata_next[29:24] = mio_outsel5_out29_qs;
5565:       end
5566: 
5567:       addr_hit[14]: begin
5568:         reg_rdata_next[5:0] = mio_outsel6_out30_qs;
5569:         reg_rdata_next[11:6] = mio_outsel6_out31_qs;
5570:       end
5571: 
5572:       addr_hit[15]: begin
5573:         reg_rdata_next[1:0] = mio_out_sleep_val0_out0_qs;
5574:         reg_rdata_next[3:2] = mio_out_sleep_val0_out1_qs;
5575:         reg_rdata_next[5:4] = mio_out_sleep_val0_out2_qs;
5576:         reg_rdata_next[7:6] = mio_out_sleep_val0_out3_qs;
5577:         reg_rdata_next[9:8] = mio_out_sleep_val0_out4_qs;
5578:         reg_rdata_next[11:10] = mio_out_sleep_val0_out5_qs;
5579:         reg_rdata_next[13:12] = mio_out_sleep_val0_out6_qs;
5580:         reg_rdata_next[15:14] = mio_out_sleep_val0_out7_qs;
5581:         reg_rdata_next[17:16] = mio_out_sleep_val0_out8_qs;
5582:         reg_rdata_next[19:18] = mio_out_sleep_val0_out9_qs;
5583:         reg_rdata_next[21:20] = mio_out_sleep_val0_out10_qs;
5584:         reg_rdata_next[23:22] = mio_out_sleep_val0_out11_qs;
5585:         reg_rdata_next[25:24] = mio_out_sleep_val0_out12_qs;
5586:         reg_rdata_next[27:26] = mio_out_sleep_val0_out13_qs;
5587:         reg_rdata_next[29:28] = mio_out_sleep_val0_out14_qs;
5588:         reg_rdata_next[31:30] = mio_out_sleep_val0_out15_qs;
5589:       end
5590: 
5591:       addr_hit[16]: begin
5592:         reg_rdata_next[1:0] = mio_out_sleep_val1_out16_qs;
5593:         reg_rdata_next[3:2] = mio_out_sleep_val1_out17_qs;
5594:         reg_rdata_next[5:4] = mio_out_sleep_val1_out18_qs;
5595:         reg_rdata_next[7:6] = mio_out_sleep_val1_out19_qs;
5596:         reg_rdata_next[9:8] = mio_out_sleep_val1_out20_qs;
5597:         reg_rdata_next[11:10] = mio_out_sleep_val1_out21_qs;
5598:         reg_rdata_next[13:12] = mio_out_sleep_val1_out22_qs;
5599:         reg_rdata_next[15:14] = mio_out_sleep_val1_out23_qs;
5600:         reg_rdata_next[17:16] = mio_out_sleep_val1_out24_qs;
5601:         reg_rdata_next[19:18] = mio_out_sleep_val1_out25_qs;
5602:         reg_rdata_next[21:20] = mio_out_sleep_val1_out26_qs;
5603:         reg_rdata_next[23:22] = mio_out_sleep_val1_out27_qs;
5604:         reg_rdata_next[25:24] = mio_out_sleep_val1_out28_qs;
5605:         reg_rdata_next[27:26] = mio_out_sleep_val1_out29_qs;
5606:         reg_rdata_next[29:28] = mio_out_sleep_val1_out30_qs;
5607:         reg_rdata_next[31:30] = mio_out_sleep_val1_out31_qs;
5608:       end
5609: 
5610:       addr_hit[17]: begin
5611:         reg_rdata_next[1:0] = dio_out_sleep_val_out0_qs;
5612:         reg_rdata_next[3:2] = dio_out_sleep_val_out1_qs;
5613:         reg_rdata_next[5:4] = dio_out_sleep_val_out2_qs;
5614:         reg_rdata_next[7:6] = dio_out_sleep_val_out3_qs;
5615:         reg_rdata_next[9:8] = dio_out_sleep_val_out4_qs;
5616:         reg_rdata_next[11:10] = dio_out_sleep_val_out5_qs;
5617:         reg_rdata_next[13:12] = dio_out_sleep_val_out6_qs;
5618:         reg_rdata_next[15:14] = dio_out_sleep_val_out7_qs;
5619:         reg_rdata_next[17:16] = dio_out_sleep_val_out8_qs;
5620:         reg_rdata_next[19:18] = dio_out_sleep_val_out9_qs;
5621:         reg_rdata_next[21:20] = dio_out_sleep_val_out10_qs;
5622:         reg_rdata_next[23:22] = dio_out_sleep_val_out11_qs;
5623:         reg_rdata_next[25:24] = dio_out_sleep_val_out12_qs;
5624:         reg_rdata_next[27:26] = dio_out_sleep_val_out13_qs;
5625:         reg_rdata_next[29:28] = dio_out_sleep_val_out14_qs;
5626:       end
5627: 
5628:       addr_hit[18]: begin
5629:         reg_rdata_next[0] = wkup_detector_en_en0_qs;
5630:         reg_rdata_next[1] = wkup_detector_en_en1_qs;
5631:         reg_rdata_next[2] = wkup_detector_en_en2_qs;
5632:         reg_rdata_next[3] = wkup_detector_en_en3_qs;
5633:         reg_rdata_next[4] = wkup_detector_en_en4_qs;
5634:         reg_rdata_next[5] = wkup_detector_en_en5_qs;
5635:         reg_rdata_next[6] = wkup_detector_en_en6_qs;
5636:         reg_rdata_next[7] = wkup_detector_en_en7_qs;
5637:       end
5638: 
5639:       addr_hit[19]: begin
5640:         reg_rdata_next[2:0] = wkup_detector0_mode0_qs;
5641:         reg_rdata_next[3] = wkup_detector0_filter0_qs;
5642:         reg_rdata_next[4] = wkup_detector0_miodio0_qs;
5643:       end
5644: 
5645:       addr_hit[20]: begin
5646:         reg_rdata_next[2:0] = wkup_detector1_mode1_qs;
5647:         reg_rdata_next[3] = wkup_detector1_filter1_qs;
5648:         reg_rdata_next[4] = wkup_detector1_miodio1_qs;
5649:       end
5650: 
5651:       addr_hit[21]: begin
5652:         reg_rdata_next[2:0] = wkup_detector2_mode2_qs;
5653:         reg_rdata_next[3] = wkup_detector2_filter2_qs;
5654:         reg_rdata_next[4] = wkup_detector2_miodio2_qs;
5655:       end
5656: 
5657:       addr_hit[22]: begin
5658:         reg_rdata_next[2:0] = wkup_detector3_mode3_qs;
5659:         reg_rdata_next[3] = wkup_detector3_filter3_qs;
5660:         reg_rdata_next[4] = wkup_detector3_miodio3_qs;
5661:       end
5662: 
5663:       addr_hit[23]: begin
5664:         reg_rdata_next[2:0] = wkup_detector4_mode4_qs;
5665:         reg_rdata_next[3] = wkup_detector4_filter4_qs;
5666:         reg_rdata_next[4] = wkup_detector4_miodio4_qs;
5667:       end
5668: 
5669:       addr_hit[24]: begin
5670:         reg_rdata_next[2:0] = wkup_detector5_mode5_qs;
5671:         reg_rdata_next[3] = wkup_detector5_filter5_qs;
5672:         reg_rdata_next[4] = wkup_detector5_miodio5_qs;
5673:       end
5674: 
5675:       addr_hit[25]: begin
5676:         reg_rdata_next[2:0] = wkup_detector6_mode6_qs;
5677:         reg_rdata_next[3] = wkup_detector6_filter6_qs;
5678:         reg_rdata_next[4] = wkup_detector6_miodio6_qs;
5679:       end
5680: 
5681:       addr_hit[26]: begin
5682:         reg_rdata_next[2:0] = wkup_detector7_mode7_qs;
5683:         reg_rdata_next[3] = wkup_detector7_filter7_qs;
5684:         reg_rdata_next[4] = wkup_detector7_miodio7_qs;
5685:       end
5686: 
5687:       addr_hit[27]: begin
5688:         reg_rdata_next[7:0] = wkup_detector_cnt_th0_th0_qs;
5689:         reg_rdata_next[15:8] = wkup_detector_cnt_th0_th1_qs;
5690:         reg_rdata_next[23:16] = wkup_detector_cnt_th0_th2_qs;
5691:         reg_rdata_next[31:24] = wkup_detector_cnt_th0_th3_qs;
5692:       end
5693: 
5694:       addr_hit[28]: begin
5695:         reg_rdata_next[7:0] = wkup_detector_cnt_th1_th4_qs;
5696:         reg_rdata_next[15:8] = wkup_detector_cnt_th1_th5_qs;
5697:         reg_rdata_next[23:16] = wkup_detector_cnt_th1_th6_qs;
5698:         reg_rdata_next[31:24] = wkup_detector_cnt_th1_th7_qs;
5699:       end
5700: 
5701:       addr_hit[29]: begin
5702:         reg_rdata_next[4:0] = wkup_detector_padsel0_sel0_qs;
5703:         reg_rdata_next[9:5] = wkup_detector_padsel0_sel1_qs;
5704:         reg_rdata_next[14:10] = wkup_detector_padsel0_sel2_qs;
5705:         reg_rdata_next[19:15] = wkup_detector_padsel0_sel3_qs;
5706:         reg_rdata_next[24:20] = wkup_detector_padsel0_sel4_qs;
5707:         reg_rdata_next[29:25] = wkup_detector_padsel0_sel5_qs;
5708:       end
5709: 
5710:       addr_hit[30]: begin
5711:         reg_rdata_next[4:0] = wkup_detector_padsel1_sel6_qs;
5712:         reg_rdata_next[9:5] = wkup_detector_padsel1_sel7_qs;
5713:       end
5714: 
5715:       addr_hit[31]: begin
5716:         reg_rdata_next[0] = wkup_cause_cause0_qs;
5717:         reg_rdata_next[1] = wkup_cause_cause1_qs;
5718:         reg_rdata_next[2] = wkup_cause_cause2_qs;
5719:         reg_rdata_next[3] = wkup_cause_cause3_qs;
5720:         reg_rdata_next[4] = wkup_cause_cause4_qs;
5721:         reg_rdata_next[5] = wkup_cause_cause5_qs;
5722:         reg_rdata_next[6] = wkup_cause_cause6_qs;
5723:         reg_rdata_next[7] = wkup_cause_cause7_qs;
5724:       end
5725: 
5726:       default: begin
5727:         reg_rdata_next = '1;
5728:       end
5729:     endcase
5730:   end
5731: 
5732:   // Assertions for Register Interface
5733:   `ASSERT_PULSE(wePulse, reg_we)
5734:   `ASSERT_PULSE(rePulse, reg_re)
5735: 
5736:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
5737: 
5738:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
5739: 
5740:   // this is formulated as an assumption such that the FPV testbenches do disprove this
5741:   // property by mistake
5742:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
5743: 
5744: endmodule
5745: