hw/ip/rv_timer/rtl/timer_core.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5:
6:
7: module timer_core #(
8: parameter int N = 1
9: ) (
10: input clk_i,
11: input rst_ni,
12:
13: input active,
14: input [11:0] prescaler,
15: input [ 7:0] step,
16:
17: output logic tick,
18: output logic [63:0] mtime_d,
19: input [63:0] mtime,
20: input [63:0] mtimecmp [N],
21:
22: output logic [N-1:0] intr
23: );
24:
25: logic [11:0] tick_count;
26:
27: always_ff @(posedge clk_i or negedge rst_ni) begin : generate_tick
28: if (!rst_ni) begin
29: tick_count <= 12'h0;
30: end else if (!active) begin
31: tick_count <= 12'h0;
32: end else if (tick_count == prescaler) begin
33: tick_count <= 12'h0;
34: end else begin
35: tick_count <= tick_count + 1'b1;
36: end
37: end
38:
39: assign tick = active & (tick_count >= prescaler);
40:
41: assign mtime_d = mtime + 64'(step);
42:
43: // interrupt is generated if mtime is greater than or equal to mtimecmp
44: // TODO: Check if it must consider overflow case
45: for (genvar t = 0 ; t < N ; t++) begin : gen_intr
46: assign intr[t] = active & (mtime >= mtimecmp[t]);
47: end
48:
49: endmodule : timer_core
50: