../src/lowrisc_ip_padctrl_component_0.1/rtl/padring.sv Cov: 56.9%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // This it the padctrl portion that has to be instantiated on the chip level.
   6: // The module instantiates the technology dependent pads, and connects them
   7: // to the MIOs/DIOs and pad attributes coming from the padctrl block.
   8: //
   9: 
  10: `include "prim_assert.sv"
  11: 
  12: module padring import padctrl_reg_pkg::*; #(
  13:   // This allows to selectively connect Pad instances.
  14:   // unconnected inputs are tied to 0, unconnected outputs are high-z.
  15:   parameter logic [NMioPads-1:0] ConnectMioIn = '1,
  16:   parameter logic [NMioPads-1:0] ConnectMioOut = '1,
  17:   parameter logic [NDioPads-1:0] ConnectDioIn = '1,
  18:   parameter logic [NDioPads-1:0] ConnectDioOut = '1
  19: ) (
  20:   // pad input
  21:   input wire                  clk_pad_i,
  22:   input wire                  clk_usb_48mhz_pad_i,
  23:   input wire                  rst_pad_ni,
  24:   // to clocking/reset infrastructure
  25:   output logic                clk_o,
  26:   output logic                clk_usb_48mhz_o,
  27:   output logic                rst_no,
  28:   // pads
  29:   inout wire   [NMioPads-1:0] mio_pad_io,
  30:   inout wire   [NDioPads-1:0] dio_pad_io,
  31:   // muxed IO signals coming from pinmux
  32:   output logic [NMioPads-1:0] mio_in_o,
  33:   input        [NMioPads-1:0] mio_out_i,
  34:   input        [NMioPads-1:0] mio_oe_i,
  35:   // dedicated IO signals coming from peripherals
  36:   output logic [NDioPads-1:0] dio_in_o,
  37:   input        [NDioPads-1:0] dio_out_i,
  38:   input        [NDioPads-1:0] dio_oe_i,
  39:   // pad attributes from top level instance
  40:   input        [NMioPads-1:0][AttrDw-1:0] mio_attr_i,
  41:   input        [NDioPads-1:0][AttrDw-1:0] dio_attr_i
  42: );
  43: 
  44:   /////////////////////////
  45:   // Clock / Reset Infra //
  46:   /////////////////////////
  47: 
  48:   // use this intermediate assignment to make both lint and fpv happy.
  49:   // the clock/reset wires should be input-only, otherwise fpv
  50:   // has trouble defining/tracing the clock signal. on the other hand, a direct
  51:   // connection of input wire to an inout pad causes lint problems
  52:   // (even though oe is hardwired to 0).
  53:   wire clk, clk_usb_48mhz, rst_n;
  54:   assign clk           = clk_pad_i;
  55:   assign clk_usb_48mhz = clk_usb_48mhz_pad_i;
  56:   assign rst_n         = rst_pad_ni;
  57: 
  58:   prim_pad_wrapper #(
  59:     .AttrDw(AttrDw)
  60:   ) i_clk_pad (
  61:     .inout_io ( clk   ),
  62:     .in_o     ( clk_o ),
  63:     .out_i    ( 1'b0  ),
  64:     .oe_i     ( 1'b0  ),
  65:     .attr_i   (   '0  )
  66:   );
  67: 
  68:   prim_pad_wrapper #(
  69:     .AttrDw(AttrDw)
  70:   ) i_clk_usb_48mhz_pad (
  71:     .inout_io ( clk_usb_48mhz   ),
  72:     .in_o     ( clk_usb_48mhz_o ),
  73:     .out_i    ( 1'b0  ),
  74:     .oe_i     ( 1'b0  ),
  75:     .attr_i   (   '0  )
  76:   );
  77: 
  78:   prim_pad_wrapper #(
  79:     .AttrDw(AttrDw)
  80:   ) i_rst_pad (
  81:     .inout_io ( rst_n  ),
  82:     .in_o     ( rst_no ),
  83:     .out_i    ( 1'b0  ),
  84:     .oe_i     ( 1'b0  ),
  85:     .attr_i   (   '0  )
  86:   );
  87: 
  88:   //////////////
  89:   // MIO Pads //
  90:   //////////////
  91: 
  92:   for (genvar k = 0; k < NMioPads; k++) begin : gen_mio_pads
  93:     if (ConnectMioIn[k] && ConnectMioOut[k]) begin : gen_mio_inout
  94:       prim_pad_wrapper #(
  95:         .AttrDw(AttrDw)
  96:       ) i_mio_pad (
  97:         .inout_io ( mio_pad_io[k] ),
  98:         .in_o     ( mio_in_o[k]   ),
  99:         .out_i    ( mio_out_i[k]  ),
 100:         .oe_i     ( mio_oe_i[k]   ),
 101:         .attr_i   ( mio_attr_i[k] )
 102:       );
 103:     end else if (ConnectMioOut[k]) begin : gen_mio_output
 104:       prim_pad_wrapper #(
 105:         .AttrDw(AttrDw)
 106:       ) i_mio_pad (
 107:         .inout_io ( mio_pad_io[k] ),
 108:         .in_o     (               ),
 109:         .out_i    ( mio_out_i[k]  ),
 110:         .oe_i     ( mio_oe_i[k]   ),
 111:         .attr_i   ( mio_attr_i[k] )
 112:       );
 113: 
 114:       assign mio_in_o[k]  = 1'b0;
 115:     end else if (ConnectMioIn[k]) begin : gen_mio_input
 116:       prim_pad_wrapper #(
 117:         .AttrDw(AttrDw)
 118:       ) i_mio_pad (
 119:         .inout_io ( mio_pad_io[k] ),
 120:         .in_o     ( mio_in_o[k]   ),
 121:         .out_i    ( 1'b0          ),
 122:         .oe_i     ( 1'b0          ),
 123:         .attr_i   ( mio_attr_i[k] )
 124:       );
 125: 
 126:       logic unused_out, unused_oe;
 127:       assign unused_out   = mio_out_i[k];
 128:       assign unused_oe    = mio_oe_i[k];
 129:     end else begin : gen_mio_tie_off
 130:       logic unused_out, unused_oe;
 131:       logic [AttrDw-1:0] unused_attr;
 132:       assign mio_pad_io[k] = 1'bz;
 133:       assign unused_out   = mio_out_i[k];
 134:       assign unused_oe    = mio_oe_i[k];
 135:       assign unused_attr  = mio_attr_i[k];
 136:       assign mio_in_o[k]  = 1'b0;
 137:     end
 138:   end
 139: 
 140:   //////////////
 141:   // DIO Pads //
 142:   //////////////
 143: 
 144:   for (genvar k = 0; k < NDioPads; k++) begin : gen_dio_pads
 145:     if (ConnectDioIn[k] && ConnectDioOut[k]) begin : gen_dio_inout
 146:       prim_pad_wrapper #(
 147:         .AttrDw(AttrDw)
 148:       ) i_dio_pad (
 149:         .inout_io ( dio_pad_io[k] ),
 150:         .in_o     ( dio_in_o[k]   ),
 151:         .out_i    ( dio_out_i[k]  ),
 152:         .oe_i     ( dio_oe_i[k]   ),
 153:         .attr_i   ( dio_attr_i[k] )
 154:       );
 155:     end else if (ConnectDioOut[k]) begin : gen_dio_output
 156:       prim_pad_wrapper #(
 157:         .AttrDw(AttrDw)
 158:       ) i_dio_pad (
 159:         .inout_io ( dio_pad_io[k] ),
 160:         .in_o     (               ),
 161:         .out_i    ( dio_out_i[k]  ),
 162:         .oe_i     ( dio_oe_i[k]   ),
 163:         .attr_i   ( dio_attr_i[k] )
 164:       );
 165: 
 166:       assign dio_in_o[k]  = 1'b0;
 167:     end else if (ConnectDioIn[k]) begin : gen_dio_input
 168:       prim_pad_wrapper #(
 169:         .AttrDw(AttrDw)
 170:       ) i_dio_pad (
 171:         .inout_io ( dio_pad_io[k] ),
 172:         .in_o     ( dio_in_o[k]   ),
 173:         .out_i    ( 1'b0          ),
 174:         .oe_i     ( 1'b0          ),
 175:         .attr_i   ( dio_attr_i[k] )
 176:       );
 177: 
 178:       logic unused_out, unused_oe;
 179:       assign unused_out   = dio_out_i[k];
 180:       assign unused_oe    = dio_oe_i[k];
 181:     end else begin : gen_dio_tie_off
 182:       logic unused_out, unused_oe;
 183:       logic [AttrDw-1:0] unused_attr;
 184:       assign dio_pad_io[k] = 1'bz;
 185:       assign unused_out   = dio_out_i[k];
 186:       assign unused_oe    = dio_oe_i[k];
 187:       assign unused_attr  = dio_attr_i[k];
 188:       assign dio_in_o[k]  = 1'b0;
 189:     end
 190:   end
 191: 
 192: endmodule : padring
 193: