../src/lowrisc_ip_flash_ctrl_pkg_0.1/rtl/flash_phy_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Flash phy module package
6: //
7:
8: package flash_phy_pkg;
9: parameter int NumBanks = flash_ctrl_pkg::NumBanks;
10: parameter int PagesPerBank = flash_ctrl_pkg::PagesPerBank;
11: parameter int WordsPerPage = flash_ctrl_pkg::WordsPerPage;
12: parameter int BytesPerWord = flash_ctrl_pkg::BytesPerWord;
13: parameter int BankW = flash_ctrl_pkg::BankW;
14: parameter int PageW = flash_ctrl_pkg::PageW;
15: parameter int WordW = flash_ctrl_pkg::WordW;
16: parameter int BusWidth = flash_ctrl_pkg::BusWidth;
17: parameter int DataWidth = flash_ctrl_pkg::DataWidth;
18: parameter int NumBuf = 4; // number of flash read buffers
19: parameter int RspOrderDepth = 2; // this should be DataWidth / BusWidth
20: // will switch to this after bus widening
21:
22: // This address width is from the perspective of the sw / flash controller
23: // which may assume a different width relative to the flash primitive
24: parameter int BankAddrW = flash_ctrl_pkg::BankAddrW;
25:
26: // This address width is from the perspective of the flash primitive,
27: // which is an integer multiple of the bus width. As a result, the number
28: // of relevant address bits changes.
29:
30: // address bits remain must be 0
31: parameter int AddrBitsRemain = DataWidth % BusWidth;
32:
33: // must be powers of 2 multiple
34: parameter int WidthMultiple = DataWidth / BusWidth;
35:
36: // number of flash words per page vs bus words per page
37: parameter int FlashWordsPerPage = WordsPerPage / WidthMultiple;
38: parameter int FlashWordsW = $clog2(FlashWordsPerPage);
39:
40: // base index
41: // This is the lsb position of the prim flash address when looking at the bus address
42: parameter int LsbAddrBit = $clog2(WidthMultiple);
43: parameter int WordSelW = WidthMultiple == 1 ? 1 : LsbAddrBit;
44:
45: // prim flash addr width
46: parameter int PrimFlashAddrW = BankAddrW - LsbAddrBit;
47:
48: // Read buffer metadata
49: typedef enum logic [1:0] {
50: Invalid = 2'h0,
51: Wip = 2'h1,
52: Valid = 2'h2,
53: Undef = 2'h3
54: } rd_buf_attr_e;
55:
56: typedef struct packed {
57: logic [DataWidth-1:0] data;
58: logic [PrimFlashAddrW-1:0] addr; // all address bits preserved to pick return portion
59: rd_buf_attr_e attr;
60: } rd_buf_t;
61:
62: typedef struct packed {
63: logic [NumBuf-1:0] buf_sel;
64: logic [WordSelW-1:0] word_sel;
65: } rsp_fifo_entry_t;
66:
67: parameter int RspOrderFifoWidth = $bits(rsp_fifo_entry_t);
68:
69: // Flash Operations Supported
70: typedef enum logic [2:0] {
71: PhyRead = 3'h0,
72: PhyProg = 3'h1,
73: PhyPgErase = 3'h2,
74: PhyBkErase = 3'h3,
75: PhyOps = 3'h4
76: } flash_phy_op_e;
77:
78: // Flash Operations Selected
79: typedef enum logic [1:0] {
80: None = 2'h0,
81: Host = 2'h1,
82: Ctrl = 2'h2
83: } flash_phy_op_sel_e;
84:
85:
86:
87:
88: endpackage // flash_phy_pkg
89: