hw/ip/prim/rtl/prim_filter.sv Cov: 100%

   1: // Copyright 2018 lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Indentifier: Apache-2.0
   4: //
   5: // Primitive input filter, with enable.  Configurable number of cycles.
   6: //
   7: // when in reset, stored vector is zero
   8: // when enable is false, output is input
   9: // when enable is true, output is stored value,
  10: //   new input must be opposite value from stored value for
  11: //   #Cycles before switching to new value.
  12: 
  13: module prim_filter #(parameter Cycles = 4) (
  14:   input  clk_i,
  15:   input  rst_ni,
  16:   input  enable_i,
  17:   input  filter_i,
  18:   output filter_o
  19: );
  20: 
  21:   logic [Cycles-1:0] stored_vector_q, stored_vector_d;
  22:   logic stored_value_q, update_stored_value;
  23: 
  24:   always_ff @(posedge clk_i or negedge rst_ni) begin
  25:     if (!rst_ni) begin
  26:       stored_value_q <= 1'b0;
  27:     end else if (update_stored_value) begin
  28:       stored_value_q <= filter_i;
  29:     end
  30:   end
  31: 
  32:   assign stored_vector_d = {stored_vector_q[Cycles-2:0],filter_i};
  33: 
  34:   always_ff @(posedge clk_i or negedge rst_ni) begin
  35:     if (!rst_ni) begin
  36:       stored_vector_q <= {Cycles{1'b0}};
  37:     end else begin
  38:       stored_vector_q <= stored_vector_d;
  39:     end
  40:   end
  41: 
  42:   assign update_stored_value =
  43:              (stored_vector_d == {Cycles{1'b0}}) |
  44:              (stored_vector_d == {Cycles{1'b1}});
  45: 
  46:   assign filter_o = enable_i ? stored_value_q : filter_i;
  47: 
  48: endmodule
  49: 
  50: