hw/ip/uart/rtl/uart.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Description: UART top level wrapper file
   6: 
   7: module uart (
   8:   input           clk_i,
   9:   input           rst_ni,
  10: 
  11:   // Bus Interface
  12:   input  tlul_pkg::tl_h2d_t tl_i,
  13:   output tlul_pkg::tl_d2h_t tl_o,
  14: 
  15:   // Generic IO
  16:   input           cio_rx_i,
  17:   output logic    cio_tx_o,
  18:   output logic    cio_tx_en_o,
  19: 
  20:   // Interrupts
  21:   output logic    intr_tx_watermark_o ,
  22:   output logic    intr_rx_watermark_o ,
  23:   output logic    intr_tx_empty_o  ,
  24:   output logic    intr_rx_overflow_o  ,
  25:   output logic    intr_rx_frame_err_o ,
  26:   output logic    intr_rx_break_err_o ,
  27:   output logic    intr_rx_timeout_o   ,
  28:   output logic    intr_rx_parity_err_o
  29: );
  30: 
  31:   import uart_reg_pkg::*;
  32: 
  33:   uart_reg2hw_t reg2hw;
  34:   uart_hw2reg_t hw2reg;
  35: 
  36:   uart_reg_top u_reg (
  37:     .clk_i,
  38:     .rst_ni,
  39:     .tl_i,
  40:     .tl_o,
  41:     .reg2hw,
  42:     .hw2reg,
  43: 
  44:     .devmode_i  (1'b1)
  45:   );
  46: 
  47:   uart_core uart_core (
  48:     .clk_i,
  49:     .rst_ni,
  50:     .reg2hw,
  51:     .hw2reg,
  52: 
  53:     .rx    (cio_rx_i   ),
  54:     .tx    (cio_tx_o   ),
  55: 
  56:     .intr_tx_watermark_o,
  57:     .intr_rx_watermark_o,
  58:     .intr_tx_empty_o,
  59:     .intr_rx_overflow_o,
  60:     .intr_rx_frame_err_o,
  61:     .intr_rx_break_err_o,
  62:     .intr_rx_timeout_o,
  63:     .intr_rx_parity_err_o
  64:   );
  65: 
  66:   // always enable the driving out of TX
  67:   assign cio_tx_en_o = 1'b1;
  68: 
  69:   // Assert Known for outputs
  70:   `ASSERT_KNOWN(txenKnown, cio_tx_en_o, clk_i, !rst_ni)
  71:   `ASSERT_KNOWN(txKnown, cio_tx_o, clk_i, !rst_ni || !cio_tx_en_o)
  72: 
  73:   // Assert Known for interrupts
  74:   `ASSERT_KNOWN(txWatermarkKnown, intr_tx_watermark_o, clk_i, !rst_ni)
  75:   `ASSERT_KNOWN(rxWatermarkKnown, intr_rx_watermark_o, clk_i, !rst_ni)
  76:   `ASSERT_KNOWN(txEmptyKnown, intr_tx_empty_o, clk_i, !rst_ni)
  77:   `ASSERT_KNOWN(rxOverflowKnown, intr_rx_overflow_o, clk_i, !rst_ni)
  78:   `ASSERT_KNOWN(rxFrameErrKnown, intr_rx_frame_err_o, clk_i, !rst_ni)
  79:   `ASSERT_KNOWN(rxBreakErrKnown, intr_rx_break_err_o, clk_i, !rst_ni)
  80:   `ASSERT_KNOWN(rxTimeoutKnown, intr_rx_timeout_o, clk_i, !rst_ni)
  81:   `ASSERT_KNOWN(rxParityErrKnown, intr_rx_parity_err_o, clk_i, !rst_ni)
  82: 
  83: endmodule
  84: