hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: module alert_handler_reg_top (
   8:   input clk_i,
   9:   input rst_ni,
  10: 
  11:   // Below Regster interface can be changed
  12:   input  tlul_pkg::tl_h2d_t tl_i,
  13:   output tlul_pkg::tl_d2h_t tl_o,
  14:   // To HW
  15:   output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
  16:   input  alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read
  17: 
  18:   // Config
  19:   input devmode_i // If 1, explicit error return for unmapped register access
  20: );
  21: 
  22:   import alert_handler_reg_pkg::* ;
  23: 
  24:   localparam AW = 8;
  25:   localparam DW = 32;
  26:   localparam DBW = DW/8;                    // Byte Width
  27: 
  28:   // register signals
  29:   logic           reg_we;
  30:   logic           reg_re;
  31:   logic [AW-1:0]  reg_addr;
  32:   logic [DW-1:0]  reg_wdata;
  33:   logic [DBW-1:0] reg_be;
  34:   logic [DW-1:0]  reg_rdata;
  35:   logic           reg_error;
  36: 
  37:   logic          addrmiss, wr_err;
  38: 
  39:   logic [DW-1:0] reg_rdata_next;
  40: 
  41:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  42:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  43: 
  44:   assign tl_reg_h2d = tl_i;
  45:   assign tl_o       = tl_reg_d2h;
  46: 
  47:   tlul_adapter_reg #(
  48:     .RegAw(AW),
  49:     .RegDw(DW)
  50:   ) u_reg_if (
  51:     .clk_i,
  52:     .rst_ni,
  53: 
  54:     .tl_i (tl_reg_h2d),
  55:     .tl_o (tl_reg_d2h),
  56: 
  57:     .we_o    (reg_we),
  58:     .re_o    (reg_re),
  59:     .addr_o  (reg_addr),
  60:     .wdata_o (reg_wdata),
  61:     .be_o    (reg_be),
  62:     .rdata_i (reg_rdata),
  63:     .error_i (reg_error)
  64:   );
  65: 
  66:   assign reg_rdata = reg_rdata_next ;
  67:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  68: 
  69:   // Define SW related signals
  70:   // Format: __{wd|we|qs}
  71:   //        or _{wd|we|qs} if field == 1 or 0
  72:   logic intr_state_classa_qs;
  73:   logic intr_state_classa_wd;
  74:   logic intr_state_classa_we;
  75:   logic intr_state_classb_qs;
  76:   logic intr_state_classb_wd;
  77:   logic intr_state_classb_we;
  78:   logic intr_state_classc_qs;
  79:   logic intr_state_classc_wd;
  80:   logic intr_state_classc_we;
  81:   logic intr_state_classd_qs;
  82:   logic intr_state_classd_wd;
  83:   logic intr_state_classd_we;
  84:   logic intr_enable_classa_qs;
  85:   logic intr_enable_classa_wd;
  86:   logic intr_enable_classa_we;
  87:   logic intr_enable_classb_qs;
  88:   logic intr_enable_classb_wd;
  89:   logic intr_enable_classb_we;
  90:   logic intr_enable_classc_qs;
  91:   logic intr_enable_classc_wd;
  92:   logic intr_enable_classc_we;
  93:   logic intr_enable_classd_qs;
  94:   logic intr_enable_classd_wd;
  95:   logic intr_enable_classd_we;
  96:   logic intr_test_classa_wd;
  97:   logic intr_test_classa_we;
  98:   logic intr_test_classb_wd;
  99:   logic intr_test_classb_we;
 100:   logic intr_test_classc_wd;
 101:   logic intr_test_classc_we;
 102:   logic intr_test_classd_wd;
 103:   logic intr_test_classd_we;
 104:   logic regen_qs;
 105:   logic regen_wd;
 106:   logic regen_we;
 107:   logic [23:0] ping_timeout_cyc_qs;
 108:   logic [23:0] ping_timeout_cyc_wd;
 109:   logic ping_timeout_cyc_we;
 110:   logic alert_en_qs;
 111:   logic alert_en_wd;
 112:   logic alert_en_we;
 113:   logic [1:0] alert_class_qs;
 114:   logic [1:0] alert_class_wd;
 115:   logic alert_class_we;
 116:   logic alert_cause_qs;
 117:   logic alert_cause_wd;
 118:   logic alert_cause_we;
 119:   logic loc_alert_en_en_la0_qs;
 120:   logic loc_alert_en_en_la0_wd;
 121:   logic loc_alert_en_en_la0_we;
 122:   logic loc_alert_en_en_la1_qs;
 123:   logic loc_alert_en_en_la1_wd;
 124:   logic loc_alert_en_en_la1_we;
 125:   logic loc_alert_en_en_la2_qs;
 126:   logic loc_alert_en_en_la2_wd;
 127:   logic loc_alert_en_en_la2_we;
 128:   logic loc_alert_en_en_la3_qs;
 129:   logic loc_alert_en_en_la3_wd;
 130:   logic loc_alert_en_en_la3_we;
 131:   logic [1:0] loc_alert_class_class_la0_qs;
 132:   logic [1:0] loc_alert_class_class_la0_wd;
 133:   logic loc_alert_class_class_la0_we;
 134:   logic [1:0] loc_alert_class_class_la1_qs;
 135:   logic [1:0] loc_alert_class_class_la1_wd;
 136:   logic loc_alert_class_class_la1_we;
 137:   logic [1:0] loc_alert_class_class_la2_qs;
 138:   logic [1:0] loc_alert_class_class_la2_wd;
 139:   logic loc_alert_class_class_la2_we;
 140:   logic [1:0] loc_alert_class_class_la3_qs;
 141:   logic [1:0] loc_alert_class_class_la3_wd;
 142:   logic loc_alert_class_class_la3_we;
 143:   logic loc_alert_cause_la0_qs;
 144:   logic loc_alert_cause_la0_wd;
 145:   logic loc_alert_cause_la0_we;
 146:   logic loc_alert_cause_la1_qs;
 147:   logic loc_alert_cause_la1_wd;
 148:   logic loc_alert_cause_la1_we;
 149:   logic loc_alert_cause_la2_qs;
 150:   logic loc_alert_cause_la2_wd;
 151:   logic loc_alert_cause_la2_we;
 152:   logic loc_alert_cause_la3_qs;
 153:   logic loc_alert_cause_la3_wd;
 154:   logic loc_alert_cause_la3_we;
 155:   logic classa_ctrl_en_qs;
 156:   logic classa_ctrl_en_wd;
 157:   logic classa_ctrl_en_we;
 158:   logic classa_ctrl_lock_qs;
 159:   logic classa_ctrl_lock_wd;
 160:   logic classa_ctrl_lock_we;
 161:   logic classa_ctrl_en_e0_qs;
 162:   logic classa_ctrl_en_e0_wd;
 163:   logic classa_ctrl_en_e0_we;
 164:   logic classa_ctrl_en_e1_qs;
 165:   logic classa_ctrl_en_e1_wd;
 166:   logic classa_ctrl_en_e1_we;
 167:   logic classa_ctrl_en_e2_qs;
 168:   logic classa_ctrl_en_e2_wd;
 169:   logic classa_ctrl_en_e2_we;
 170:   logic classa_ctrl_en_e3_qs;
 171:   logic classa_ctrl_en_e3_wd;
 172:   logic classa_ctrl_en_e3_we;
 173:   logic [1:0] classa_ctrl_map_e0_qs;
 174:   logic [1:0] classa_ctrl_map_e0_wd;
 175:   logic classa_ctrl_map_e0_we;
 176:   logic [1:0] classa_ctrl_map_e1_qs;
 177:   logic [1:0] classa_ctrl_map_e1_wd;
 178:   logic classa_ctrl_map_e1_we;
 179:   logic [1:0] classa_ctrl_map_e2_qs;
 180:   logic [1:0] classa_ctrl_map_e2_wd;
 181:   logic classa_ctrl_map_e2_we;
 182:   logic [1:0] classa_ctrl_map_e3_qs;
 183:   logic [1:0] classa_ctrl_map_e3_wd;
 184:   logic classa_ctrl_map_e3_we;
 185:   logic classa_clren_qs;
 186:   logic classa_clren_wd;
 187:   logic classa_clren_we;
 188:   logic classa_clr_wd;
 189:   logic classa_clr_we;
 190:   logic [15:0] classa_accum_cnt_qs;
 191:   logic classa_accum_cnt_re;
 192:   logic [15:0] classa_accum_thresh_qs;
 193:   logic [15:0] classa_accum_thresh_wd;
 194:   logic classa_accum_thresh_we;
 195:   logic [31:0] classa_timeout_cyc_qs;
 196:   logic [31:0] classa_timeout_cyc_wd;
 197:   logic classa_timeout_cyc_we;
 198:   logic [31:0] classa_phase0_cyc_qs;
 199:   logic [31:0] classa_phase0_cyc_wd;
 200:   logic classa_phase0_cyc_we;
 201:   logic [31:0] classa_phase1_cyc_qs;
 202:   logic [31:0] classa_phase1_cyc_wd;
 203:   logic classa_phase1_cyc_we;
 204:   logic [31:0] classa_phase2_cyc_qs;
 205:   logic [31:0] classa_phase2_cyc_wd;
 206:   logic classa_phase2_cyc_we;
 207:   logic [31:0] classa_phase3_cyc_qs;
 208:   logic [31:0] classa_phase3_cyc_wd;
 209:   logic classa_phase3_cyc_we;
 210:   logic [31:0] classa_esc_cnt_qs;
 211:   logic classa_esc_cnt_re;
 212:   logic [2:0] classa_state_qs;
 213:   logic classa_state_re;
 214:   logic classb_ctrl_en_qs;
 215:   logic classb_ctrl_en_wd;
 216:   logic classb_ctrl_en_we;
 217:   logic classb_ctrl_lock_qs;
 218:   logic classb_ctrl_lock_wd;
 219:   logic classb_ctrl_lock_we;
 220:   logic classb_ctrl_en_e0_qs;
 221:   logic classb_ctrl_en_e0_wd;
 222:   logic classb_ctrl_en_e0_we;
 223:   logic classb_ctrl_en_e1_qs;
 224:   logic classb_ctrl_en_e1_wd;
 225:   logic classb_ctrl_en_e1_we;
 226:   logic classb_ctrl_en_e2_qs;
 227:   logic classb_ctrl_en_e2_wd;
 228:   logic classb_ctrl_en_e2_we;
 229:   logic classb_ctrl_en_e3_qs;
 230:   logic classb_ctrl_en_e3_wd;
 231:   logic classb_ctrl_en_e3_we;
 232:   logic [1:0] classb_ctrl_map_e0_qs;
 233:   logic [1:0] classb_ctrl_map_e0_wd;
 234:   logic classb_ctrl_map_e0_we;
 235:   logic [1:0] classb_ctrl_map_e1_qs;
 236:   logic [1:0] classb_ctrl_map_e1_wd;
 237:   logic classb_ctrl_map_e1_we;
 238:   logic [1:0] classb_ctrl_map_e2_qs;
 239:   logic [1:0] classb_ctrl_map_e2_wd;
 240:   logic classb_ctrl_map_e2_we;
 241:   logic [1:0] classb_ctrl_map_e3_qs;
 242:   logic [1:0] classb_ctrl_map_e3_wd;
 243:   logic classb_ctrl_map_e3_we;
 244:   logic classb_clren_qs;
 245:   logic classb_clren_wd;
 246:   logic classb_clren_we;
 247:   logic classb_clr_wd;
 248:   logic classb_clr_we;
 249:   logic [15:0] classb_accum_cnt_qs;
 250:   logic classb_accum_cnt_re;
 251:   logic [15:0] classb_accum_thresh_qs;
 252:   logic [15:0] classb_accum_thresh_wd;
 253:   logic classb_accum_thresh_we;
 254:   logic [31:0] classb_timeout_cyc_qs;
 255:   logic [31:0] classb_timeout_cyc_wd;
 256:   logic classb_timeout_cyc_we;
 257:   logic [31:0] classb_phase0_cyc_qs;
 258:   logic [31:0] classb_phase0_cyc_wd;
 259:   logic classb_phase0_cyc_we;
 260:   logic [31:0] classb_phase1_cyc_qs;
 261:   logic [31:0] classb_phase1_cyc_wd;
 262:   logic classb_phase1_cyc_we;
 263:   logic [31:0] classb_phase2_cyc_qs;
 264:   logic [31:0] classb_phase2_cyc_wd;
 265:   logic classb_phase2_cyc_we;
 266:   logic [31:0] classb_phase3_cyc_qs;
 267:   logic [31:0] classb_phase3_cyc_wd;
 268:   logic classb_phase3_cyc_we;
 269:   logic [31:0] classb_esc_cnt_qs;
 270:   logic classb_esc_cnt_re;
 271:   logic [2:0] classb_state_qs;
 272:   logic classb_state_re;
 273:   logic classc_ctrl_en_qs;
 274:   logic classc_ctrl_en_wd;
 275:   logic classc_ctrl_en_we;
 276:   logic classc_ctrl_lock_qs;
 277:   logic classc_ctrl_lock_wd;
 278:   logic classc_ctrl_lock_we;
 279:   logic classc_ctrl_en_e0_qs;
 280:   logic classc_ctrl_en_e0_wd;
 281:   logic classc_ctrl_en_e0_we;
 282:   logic classc_ctrl_en_e1_qs;
 283:   logic classc_ctrl_en_e1_wd;
 284:   logic classc_ctrl_en_e1_we;
 285:   logic classc_ctrl_en_e2_qs;
 286:   logic classc_ctrl_en_e2_wd;
 287:   logic classc_ctrl_en_e2_we;
 288:   logic classc_ctrl_en_e3_qs;
 289:   logic classc_ctrl_en_e3_wd;
 290:   logic classc_ctrl_en_e3_we;
 291:   logic [1:0] classc_ctrl_map_e0_qs;
 292:   logic [1:0] classc_ctrl_map_e0_wd;
 293:   logic classc_ctrl_map_e0_we;
 294:   logic [1:0] classc_ctrl_map_e1_qs;
 295:   logic [1:0] classc_ctrl_map_e1_wd;
 296:   logic classc_ctrl_map_e1_we;
 297:   logic [1:0] classc_ctrl_map_e2_qs;
 298:   logic [1:0] classc_ctrl_map_e2_wd;
 299:   logic classc_ctrl_map_e2_we;
 300:   logic [1:0] classc_ctrl_map_e3_qs;
 301:   logic [1:0] classc_ctrl_map_e3_wd;
 302:   logic classc_ctrl_map_e3_we;
 303:   logic classc_clren_qs;
 304:   logic classc_clren_wd;
 305:   logic classc_clren_we;
 306:   logic classc_clr_wd;
 307:   logic classc_clr_we;
 308:   logic [15:0] classc_accum_cnt_qs;
 309:   logic classc_accum_cnt_re;
 310:   logic [15:0] classc_accum_thresh_qs;
 311:   logic [15:0] classc_accum_thresh_wd;
 312:   logic classc_accum_thresh_we;
 313:   logic [31:0] classc_timeout_cyc_qs;
 314:   logic [31:0] classc_timeout_cyc_wd;
 315:   logic classc_timeout_cyc_we;
 316:   logic [31:0] classc_phase0_cyc_qs;
 317:   logic [31:0] classc_phase0_cyc_wd;
 318:   logic classc_phase0_cyc_we;
 319:   logic [31:0] classc_phase1_cyc_qs;
 320:   logic [31:0] classc_phase1_cyc_wd;
 321:   logic classc_phase1_cyc_we;
 322:   logic [31:0] classc_phase2_cyc_qs;
 323:   logic [31:0] classc_phase2_cyc_wd;
 324:   logic classc_phase2_cyc_we;
 325:   logic [31:0] classc_phase3_cyc_qs;
 326:   logic [31:0] classc_phase3_cyc_wd;
 327:   logic classc_phase3_cyc_we;
 328:   logic [31:0] classc_esc_cnt_qs;
 329:   logic classc_esc_cnt_re;
 330:   logic [2:0] classc_state_qs;
 331:   logic classc_state_re;
 332:   logic classd_ctrl_en_qs;
 333:   logic classd_ctrl_en_wd;
 334:   logic classd_ctrl_en_we;
 335:   logic classd_ctrl_lock_qs;
 336:   logic classd_ctrl_lock_wd;
 337:   logic classd_ctrl_lock_we;
 338:   logic classd_ctrl_en_e0_qs;
 339:   logic classd_ctrl_en_e0_wd;
 340:   logic classd_ctrl_en_e0_we;
 341:   logic classd_ctrl_en_e1_qs;
 342:   logic classd_ctrl_en_e1_wd;
 343:   logic classd_ctrl_en_e1_we;
 344:   logic classd_ctrl_en_e2_qs;
 345:   logic classd_ctrl_en_e2_wd;
 346:   logic classd_ctrl_en_e2_we;
 347:   logic classd_ctrl_en_e3_qs;
 348:   logic classd_ctrl_en_e3_wd;
 349:   logic classd_ctrl_en_e3_we;
 350:   logic [1:0] classd_ctrl_map_e0_qs;
 351:   logic [1:0] classd_ctrl_map_e0_wd;
 352:   logic classd_ctrl_map_e0_we;
 353:   logic [1:0] classd_ctrl_map_e1_qs;
 354:   logic [1:0] classd_ctrl_map_e1_wd;
 355:   logic classd_ctrl_map_e1_we;
 356:   logic [1:0] classd_ctrl_map_e2_qs;
 357:   logic [1:0] classd_ctrl_map_e2_wd;
 358:   logic classd_ctrl_map_e2_we;
 359:   logic [1:0] classd_ctrl_map_e3_qs;
 360:   logic [1:0] classd_ctrl_map_e3_wd;
 361:   logic classd_ctrl_map_e3_we;
 362:   logic classd_clren_qs;
 363:   logic classd_clren_wd;
 364:   logic classd_clren_we;
 365:   logic classd_clr_wd;
 366:   logic classd_clr_we;
 367:   logic [15:0] classd_accum_cnt_qs;
 368:   logic classd_accum_cnt_re;
 369:   logic [15:0] classd_accum_thresh_qs;
 370:   logic [15:0] classd_accum_thresh_wd;
 371:   logic classd_accum_thresh_we;
 372:   logic [31:0] classd_timeout_cyc_qs;
 373:   logic [31:0] classd_timeout_cyc_wd;
 374:   logic classd_timeout_cyc_we;
 375:   logic [31:0] classd_phase0_cyc_qs;
 376:   logic [31:0] classd_phase0_cyc_wd;
 377:   logic classd_phase0_cyc_we;
 378:   logic [31:0] classd_phase1_cyc_qs;
 379:   logic [31:0] classd_phase1_cyc_wd;
 380:   logic classd_phase1_cyc_we;
 381:   logic [31:0] classd_phase2_cyc_qs;
 382:   logic [31:0] classd_phase2_cyc_wd;
 383:   logic classd_phase2_cyc_we;
 384:   logic [31:0] classd_phase3_cyc_qs;
 385:   logic [31:0] classd_phase3_cyc_wd;
 386:   logic classd_phase3_cyc_we;
 387:   logic [31:0] classd_esc_cnt_qs;
 388:   logic classd_esc_cnt_re;
 389:   logic [2:0] classd_state_qs;
 390:   logic classd_state_re;
 391: 
 392:   // Register instances
 393:   // R[intr_state]: V(False)
 394: 
 395:   //   F[classa]: 0:0
 396:   prim_subreg #(
 397:     .DW      (1),
 398:     .SWACCESS("W1C"),
 399:     .RESVAL  (1'h0)
 400:   ) u_intr_state_classa (
 401:     .clk_i   (clk_i    ),
 402:     .rst_ni  (rst_ni  ),
 403: 
 404:     // from register interface
 405:     .we     (intr_state_classa_we),
 406:     .wd     (intr_state_classa_wd),
 407: 
 408:     // from internal hardware
 409:     .de     (hw2reg.intr_state.classa.de),
 410:     .d      (hw2reg.intr_state.classa.d ),
 411: 
 412:     // to internal hardware
 413:     .qe     (),
 414:     .q      (reg2hw.intr_state.classa.q ),
 415: 
 416:     // to register interface (read)
 417:     .qs     (intr_state_classa_qs)
 418:   );
 419: 
 420: 
 421:   //   F[classb]: 1:1
 422:   prim_subreg #(
 423:     .DW      (1),
 424:     .SWACCESS("W1C"),
 425:     .RESVAL  (1'h0)
 426:   ) u_intr_state_classb (
 427:     .clk_i   (clk_i    ),
 428:     .rst_ni  (rst_ni  ),
 429: 
 430:     // from register interface
 431:     .we     (intr_state_classb_we),
 432:     .wd     (intr_state_classb_wd),
 433: 
 434:     // from internal hardware
 435:     .de     (hw2reg.intr_state.classb.de),
 436:     .d      (hw2reg.intr_state.classb.d ),
 437: 
 438:     // to internal hardware
 439:     .qe     (),
 440:     .q      (reg2hw.intr_state.classb.q ),
 441: 
 442:     // to register interface (read)
 443:     .qs     (intr_state_classb_qs)
 444:   );
 445: 
 446: 
 447:   //   F[classc]: 2:2
 448:   prim_subreg #(
 449:     .DW      (1),
 450:     .SWACCESS("W1C"),
 451:     .RESVAL  (1'h0)
 452:   ) u_intr_state_classc (
 453:     .clk_i   (clk_i    ),
 454:     .rst_ni  (rst_ni  ),
 455: 
 456:     // from register interface
 457:     .we     (intr_state_classc_we),
 458:     .wd     (intr_state_classc_wd),
 459: 
 460:     // from internal hardware
 461:     .de     (hw2reg.intr_state.classc.de),
 462:     .d      (hw2reg.intr_state.classc.d ),
 463: 
 464:     // to internal hardware
 465:     .qe     (),
 466:     .q      (reg2hw.intr_state.classc.q ),
 467: 
 468:     // to register interface (read)
 469:     .qs     (intr_state_classc_qs)
 470:   );
 471: 
 472: 
 473:   //   F[classd]: 3:3
 474:   prim_subreg #(
 475:     .DW      (1),
 476:     .SWACCESS("W1C"),
 477:     .RESVAL  (1'h0)
 478:   ) u_intr_state_classd (
 479:     .clk_i   (clk_i    ),
 480:     .rst_ni  (rst_ni  ),
 481: 
 482:     // from register interface
 483:     .we     (intr_state_classd_we),
 484:     .wd     (intr_state_classd_wd),
 485: 
 486:     // from internal hardware
 487:     .de     (hw2reg.intr_state.classd.de),
 488:     .d      (hw2reg.intr_state.classd.d ),
 489: 
 490:     // to internal hardware
 491:     .qe     (),
 492:     .q      (reg2hw.intr_state.classd.q ),
 493: 
 494:     // to register interface (read)
 495:     .qs     (intr_state_classd_qs)
 496:   );
 497: 
 498: 
 499:   // R[intr_enable]: V(False)
 500: 
 501:   //   F[classa]: 0:0
 502:   prim_subreg #(
 503:     .DW      (1),
 504:     .SWACCESS("RW"),
 505:     .RESVAL  (1'h0)
 506:   ) u_intr_enable_classa (
 507:     .clk_i   (clk_i    ),
 508:     .rst_ni  (rst_ni  ),
 509: 
 510:     // from register interface
 511:     .we     (intr_enable_classa_we),
 512:     .wd     (intr_enable_classa_wd),
 513: 
 514:     // from internal hardware
 515:     .de     (1'b0),
 516:     .d      ('0  ),
 517: 
 518:     // to internal hardware
 519:     .qe     (),
 520:     .q      (reg2hw.intr_enable.classa.q ),
 521: 
 522:     // to register interface (read)
 523:     .qs     (intr_enable_classa_qs)
 524:   );
 525: 
 526: 
 527:   //   F[classb]: 1:1
 528:   prim_subreg #(
 529:     .DW      (1),
 530:     .SWACCESS("RW"),
 531:     .RESVAL  (1'h0)
 532:   ) u_intr_enable_classb (
 533:     .clk_i   (clk_i    ),
 534:     .rst_ni  (rst_ni  ),
 535: 
 536:     // from register interface
 537:     .we     (intr_enable_classb_we),
 538:     .wd     (intr_enable_classb_wd),
 539: 
 540:     // from internal hardware
 541:     .de     (1'b0),
 542:     .d      ('0  ),
 543: 
 544:     // to internal hardware
 545:     .qe     (),
 546:     .q      (reg2hw.intr_enable.classb.q ),
 547: 
 548:     // to register interface (read)
 549:     .qs     (intr_enable_classb_qs)
 550:   );
 551: 
 552: 
 553:   //   F[classc]: 2:2
 554:   prim_subreg #(
 555:     .DW      (1),
 556:     .SWACCESS("RW"),
 557:     .RESVAL  (1'h0)
 558:   ) u_intr_enable_classc (
 559:     .clk_i   (clk_i    ),
 560:     .rst_ni  (rst_ni  ),
 561: 
 562:     // from register interface
 563:     .we     (intr_enable_classc_we),
 564:     .wd     (intr_enable_classc_wd),
 565: 
 566:     // from internal hardware
 567:     .de     (1'b0),
 568:     .d      ('0  ),
 569: 
 570:     // to internal hardware
 571:     .qe     (),
 572:     .q      (reg2hw.intr_enable.classc.q ),
 573: 
 574:     // to register interface (read)
 575:     .qs     (intr_enable_classc_qs)
 576:   );
 577: 
 578: 
 579:   //   F[classd]: 3:3
 580:   prim_subreg #(
 581:     .DW      (1),
 582:     .SWACCESS("RW"),
 583:     .RESVAL  (1'h0)
 584:   ) u_intr_enable_classd (
 585:     .clk_i   (clk_i    ),
 586:     .rst_ni  (rst_ni  ),
 587: 
 588:     // from register interface
 589:     .we     (intr_enable_classd_we),
 590:     .wd     (intr_enable_classd_wd),
 591: 
 592:     // from internal hardware
 593:     .de     (1'b0),
 594:     .d      ('0  ),
 595: 
 596:     // to internal hardware
 597:     .qe     (),
 598:     .q      (reg2hw.intr_enable.classd.q ),
 599: 
 600:     // to register interface (read)
 601:     .qs     (intr_enable_classd_qs)
 602:   );
 603: 
 604: 
 605:   // R[intr_test]: V(True)
 606: 
 607:   //   F[classa]: 0:0
 608:   prim_subreg_ext #(
 609:     .DW    (1)
 610:   ) u_intr_test_classa (
 611:     .re     (1'b0),
 612:     .we     (intr_test_classa_we),
 613:     .wd     (intr_test_classa_wd),
 614:     .d      ('0),
 615:     .qre    (),
 616:     .qe     (reg2hw.intr_test.classa.qe),
 617:     .q      (reg2hw.intr_test.classa.q ),
 618:     .qs     ()
 619:   );
 620: 
 621: 
 622:   //   F[classb]: 1:1
 623:   prim_subreg_ext #(
 624:     .DW    (1)
 625:   ) u_intr_test_classb (
 626:     .re     (1'b0),
 627:     .we     (intr_test_classb_we),
 628:     .wd     (intr_test_classb_wd),
 629:     .d      ('0),
 630:     .qre    (),
 631:     .qe     (reg2hw.intr_test.classb.qe),
 632:     .q      (reg2hw.intr_test.classb.q ),
 633:     .qs     ()
 634:   );
 635: 
 636: 
 637:   //   F[classc]: 2:2
 638:   prim_subreg_ext #(
 639:     .DW    (1)
 640:   ) u_intr_test_classc (
 641:     .re     (1'b0),
 642:     .we     (intr_test_classc_we),
 643:     .wd     (intr_test_classc_wd),
 644:     .d      ('0),
 645:     .qre    (),
 646:     .qe     (reg2hw.intr_test.classc.qe),
 647:     .q      (reg2hw.intr_test.classc.q ),
 648:     .qs     ()
 649:   );
 650: 
 651: 
 652:   //   F[classd]: 3:3
 653:   prim_subreg_ext #(
 654:     .DW    (1)
 655:   ) u_intr_test_classd (
 656:     .re     (1'b0),
 657:     .we     (intr_test_classd_we),
 658:     .wd     (intr_test_classd_wd),
 659:     .d      ('0),
 660:     .qre    (),
 661:     .qe     (reg2hw.intr_test.classd.qe),
 662:     .q      (reg2hw.intr_test.classd.q ),
 663:     .qs     ()
 664:   );
 665: 
 666: 
 667:   // R[regen]: V(False)
 668: 
 669:   prim_subreg #(
 670:     .DW      (1),
 671:     .SWACCESS("W1C"),
 672:     .RESVAL  (1'h1)
 673:   ) u_regen (
 674:     .clk_i   (clk_i    ),
 675:     .rst_ni  (rst_ni  ),
 676: 
 677:     // from register interface
 678:     .we     (regen_we),
 679:     .wd     (regen_wd),
 680: 
 681:     // from internal hardware
 682:     .de     (1'b0),
 683:     .d      ('0  ),
 684: 
 685:     // to internal hardware
 686:     .qe     (),
 687:     .q      (reg2hw.regen.q ),
 688: 
 689:     // to register interface (read)
 690:     .qs     (regen_qs)
 691:   );
 692: 
 693: 
 694:   // R[ping_timeout_cyc]: V(False)
 695: 
 696:   prim_subreg #(
 697:     .DW      (24),
 698:     .SWACCESS("RW"),
 699:     .RESVAL  (24'h20)
 700:   ) u_ping_timeout_cyc (
 701:     .clk_i   (clk_i    ),
 702:     .rst_ni  (rst_ni  ),
 703: 
 704:     // from register interface (qualified with register enable)
 705:     .we     (ping_timeout_cyc_we & regen_qs),
 706:     .wd     (ping_timeout_cyc_wd),
 707: 
 708:     // from internal hardware
 709:     .de     (1'b0),
 710:     .d      ('0  ),
 711: 
 712:     // to internal hardware
 713:     .qe     (),
 714:     .q      (reg2hw.ping_timeout_cyc.q ),
 715: 
 716:     // to register interface (read)
 717:     .qs     (ping_timeout_cyc_qs)
 718:   );
 719: 
 720: 
 721: 
 722:   // Subregister 0 of Multireg alert_en
 723:   // R[alert_en]: V(False)
 724: 
 725:   prim_subreg #(
 726:     .DW      (1),
 727:     .SWACCESS("RW"),
 728:     .RESVAL  (1'h0)
 729:   ) u_alert_en (
 730:     .clk_i   (clk_i    ),
 731:     .rst_ni  (rst_ni  ),
 732: 
 733:     // from register interface (qualified with register enable)
 734:     .we     (alert_en_we & regen_qs),
 735:     .wd     (alert_en_wd),
 736: 
 737:     // from internal hardware
 738:     .de     (1'b0),
 739:     .d      ('0  ),
 740: 
 741:     // to internal hardware
 742:     .qe     (),
 743:     .q      (reg2hw.alert_en[0].q ),
 744: 
 745:     // to register interface (read)
 746:     .qs     (alert_en_qs)
 747:   );
 748: 
 749: 
 750: 
 751:   // Subregister 0 of Multireg alert_class
 752:   // R[alert_class]: V(False)
 753: 
 754:   prim_subreg #(
 755:     .DW      (2),
 756:     .SWACCESS("RW"),
 757:     .RESVAL  (2'h0)
 758:   ) u_alert_class (
 759:     .clk_i   (clk_i    ),
 760:     .rst_ni  (rst_ni  ),
 761: 
 762:     // from register interface (qualified with register enable)
 763:     .we     (alert_class_we & regen_qs),
 764:     .wd     (alert_class_wd),
 765: 
 766:     // from internal hardware
 767:     .de     (1'b0),
 768:     .d      ('0  ),
 769: 
 770:     // to internal hardware
 771:     .qe     (),
 772:     .q      (reg2hw.alert_class[0].q ),
 773: 
 774:     // to register interface (read)
 775:     .qs     (alert_class_qs)
 776:   );
 777: 
 778: 
 779: 
 780:   // Subregister 0 of Multireg alert_cause
 781:   // R[alert_cause]: V(False)
 782: 
 783:   prim_subreg #(
 784:     .DW      (1),
 785:     .SWACCESS("W1C"),
 786:     .RESVAL  (1'h0)
 787:   ) u_alert_cause (
 788:     .clk_i   (clk_i    ),
 789:     .rst_ni  (rst_ni  ),
 790: 
 791:     // from register interface
 792:     .we     (alert_cause_we),
 793:     .wd     (alert_cause_wd),
 794: 
 795:     // from internal hardware
 796:     .de     (hw2reg.alert_cause[0].de),
 797:     .d      (hw2reg.alert_cause[0].d ),
 798: 
 799:     // to internal hardware
 800:     .qe     (),
 801:     .q      (reg2hw.alert_cause[0].q ),
 802: 
 803:     // to register interface (read)
 804:     .qs     (alert_cause_qs)
 805:   );
 806: 
 807: 
 808: 
 809:   // Subregister 0 of Multireg loc_alert_en
 810:   // R[loc_alert_en]: V(False)
 811: 
 812:   // F[en_la0]: 0:0
 813:   prim_subreg #(
 814:     .DW      (1),
 815:     .SWACCESS("RW"),
 816:     .RESVAL  (1'h0)
 817:   ) u_loc_alert_en_en_la0 (
 818:     .clk_i   (clk_i    ),
 819:     .rst_ni  (rst_ni  ),
 820: 
 821:     // from register interface (qualified with register enable)
 822:     .we     (loc_alert_en_en_la0_we & regen_qs),
 823:     .wd     (loc_alert_en_en_la0_wd),
 824: 
 825:     // from internal hardware
 826:     .de     (1'b0),
 827:     .d      ('0  ),
 828: 
 829:     // to internal hardware
 830:     .qe     (),
 831:     .q      (reg2hw.loc_alert_en[0].q ),
 832: 
 833:     // to register interface (read)
 834:     .qs     (loc_alert_en_en_la0_qs)
 835:   );
 836: 
 837: 
 838:   // F[en_la1]: 1:1
 839:   prim_subreg #(
 840:     .DW      (1),
 841:     .SWACCESS("RW"),
 842:     .RESVAL  (1'h0)
 843:   ) u_loc_alert_en_en_la1 (
 844:     .clk_i   (clk_i    ),
 845:     .rst_ni  (rst_ni  ),
 846: 
 847:     // from register interface (qualified with register enable)
 848:     .we     (loc_alert_en_en_la1_we & regen_qs),
 849:     .wd     (loc_alert_en_en_la1_wd),
 850: 
 851:     // from internal hardware
 852:     .de     (1'b0),
 853:     .d      ('0  ),
 854: 
 855:     // to internal hardware
 856:     .qe     (),
 857:     .q      (reg2hw.loc_alert_en[1].q ),
 858: 
 859:     // to register interface (read)
 860:     .qs     (loc_alert_en_en_la1_qs)
 861:   );
 862: 
 863: 
 864:   // F[en_la2]: 2:2
 865:   prim_subreg #(
 866:     .DW      (1),
 867:     .SWACCESS("RW"),
 868:     .RESVAL  (1'h0)
 869:   ) u_loc_alert_en_en_la2 (
 870:     .clk_i   (clk_i    ),
 871:     .rst_ni  (rst_ni  ),
 872: 
 873:     // from register interface (qualified with register enable)
 874:     .we     (loc_alert_en_en_la2_we & regen_qs),
 875:     .wd     (loc_alert_en_en_la2_wd),
 876: 
 877:     // from internal hardware
 878:     .de     (1'b0),
 879:     .d      ('0  ),
 880: 
 881:     // to internal hardware
 882:     .qe     (),
 883:     .q      (reg2hw.loc_alert_en[2].q ),
 884: 
 885:     // to register interface (read)
 886:     .qs     (loc_alert_en_en_la2_qs)
 887:   );
 888: 
 889: 
 890:   // F[en_la3]: 3:3
 891:   prim_subreg #(
 892:     .DW      (1),
 893:     .SWACCESS("RW"),
 894:     .RESVAL  (1'h0)
 895:   ) u_loc_alert_en_en_la3 (
 896:     .clk_i   (clk_i    ),
 897:     .rst_ni  (rst_ni  ),
 898: 
 899:     // from register interface (qualified with register enable)
 900:     .we     (loc_alert_en_en_la3_we & regen_qs),
 901:     .wd     (loc_alert_en_en_la3_wd),
 902: 
 903:     // from internal hardware
 904:     .de     (1'b0),
 905:     .d      ('0  ),
 906: 
 907:     // to internal hardware
 908:     .qe     (),
 909:     .q      (reg2hw.loc_alert_en[3].q ),
 910: 
 911:     // to register interface (read)
 912:     .qs     (loc_alert_en_en_la3_qs)
 913:   );
 914: 
 915: 
 916: 
 917: 
 918:   // Subregister 0 of Multireg loc_alert_class
 919:   // R[loc_alert_class]: V(False)
 920: 
 921:   // F[class_la0]: 1:0
 922:   prim_subreg #(
 923:     .DW      (2),
 924:     .SWACCESS("RW"),
 925:     .RESVAL  (2'h0)
 926:   ) u_loc_alert_class_class_la0 (
 927:     .clk_i   (clk_i    ),
 928:     .rst_ni  (rst_ni  ),
 929: 
 930:     // from register interface (qualified with register enable)
 931:     .we     (loc_alert_class_class_la0_we & regen_qs),
 932:     .wd     (loc_alert_class_class_la0_wd),
 933: 
 934:     // from internal hardware
 935:     .de     (1'b0),
 936:     .d      ('0  ),
 937: 
 938:     // to internal hardware
 939:     .qe     (),
 940:     .q      (reg2hw.loc_alert_class[0].q ),
 941: 
 942:     // to register interface (read)
 943:     .qs     (loc_alert_class_class_la0_qs)
 944:   );
 945: 
 946: 
 947:   // F[class_la1]: 3:2
 948:   prim_subreg #(
 949:     .DW      (2),
 950:     .SWACCESS("RW"),
 951:     .RESVAL  (2'h0)
 952:   ) u_loc_alert_class_class_la1 (
 953:     .clk_i   (clk_i    ),
 954:     .rst_ni  (rst_ni  ),
 955: 
 956:     // from register interface (qualified with register enable)
 957:     .we     (loc_alert_class_class_la1_we & regen_qs),
 958:     .wd     (loc_alert_class_class_la1_wd),
 959: 
 960:     // from internal hardware
 961:     .de     (1'b0),
 962:     .d      ('0  ),
 963: 
 964:     // to internal hardware
 965:     .qe     (),
 966:     .q      (reg2hw.loc_alert_class[1].q ),
 967: 
 968:     // to register interface (read)
 969:     .qs     (loc_alert_class_class_la1_qs)
 970:   );
 971: 
 972: 
 973:   // F[class_la2]: 5:4
 974:   prim_subreg #(
 975:     .DW      (2),
 976:     .SWACCESS("RW"),
 977:     .RESVAL  (2'h0)
 978:   ) u_loc_alert_class_class_la2 (
 979:     .clk_i   (clk_i    ),
 980:     .rst_ni  (rst_ni  ),
 981: 
 982:     // from register interface (qualified with register enable)
 983:     .we     (loc_alert_class_class_la2_we & regen_qs),
 984:     .wd     (loc_alert_class_class_la2_wd),
 985: 
 986:     // from internal hardware
 987:     .de     (1'b0),
 988:     .d      ('0  ),
 989: 
 990:     // to internal hardware
 991:     .qe     (),
 992:     .q      (reg2hw.loc_alert_class[2].q ),
 993: 
 994:     // to register interface (read)
 995:     .qs     (loc_alert_class_class_la2_qs)
 996:   );
 997: 
 998: 
 999:   // F[class_la3]: 7:6
1000:   prim_subreg #(
1001:     .DW      (2),
1002:     .SWACCESS("RW"),
1003:     .RESVAL  (2'h0)
1004:   ) u_loc_alert_class_class_la3 (
1005:     .clk_i   (clk_i    ),
1006:     .rst_ni  (rst_ni  ),
1007: 
1008:     // from register interface (qualified with register enable)
1009:     .we     (loc_alert_class_class_la3_we & regen_qs),
1010:     .wd     (loc_alert_class_class_la3_wd),
1011: 
1012:     // from internal hardware
1013:     .de     (1'b0),
1014:     .d      ('0  ),
1015: 
1016:     // to internal hardware
1017:     .qe     (),
1018:     .q      (reg2hw.loc_alert_class[3].q ),
1019: 
1020:     // to register interface (read)
1021:     .qs     (loc_alert_class_class_la3_qs)
1022:   );
1023: 
1024: 
1025: 
1026: 
1027:   // Subregister 0 of Multireg loc_alert_cause
1028:   // R[loc_alert_cause]: V(False)
1029: 
1030:   // F[la0]: 0:0
1031:   prim_subreg #(
1032:     .DW      (1),
1033:     .SWACCESS("W1C"),
1034:     .RESVAL  (1'h0)
1035:   ) u_loc_alert_cause_la0 (
1036:     .clk_i   (clk_i    ),
1037:     .rst_ni  (rst_ni  ),
1038: 
1039:     // from register interface
1040:     .we     (loc_alert_cause_la0_we),
1041:     .wd     (loc_alert_cause_la0_wd),
1042: 
1043:     // from internal hardware
1044:     .de     (hw2reg.loc_alert_cause[0].de),
1045:     .d      (hw2reg.loc_alert_cause[0].d ),
1046: 
1047:     // to internal hardware
1048:     .qe     (),
1049:     .q      (reg2hw.loc_alert_cause[0].q ),
1050: 
1051:     // to register interface (read)
1052:     .qs     (loc_alert_cause_la0_qs)
1053:   );
1054: 
1055: 
1056:   // F[la1]: 1:1
1057:   prim_subreg #(
1058:     .DW      (1),
1059:     .SWACCESS("W1C"),
1060:     .RESVAL  (1'h0)
1061:   ) u_loc_alert_cause_la1 (
1062:     .clk_i   (clk_i    ),
1063:     .rst_ni  (rst_ni  ),
1064: 
1065:     // from register interface
1066:     .we     (loc_alert_cause_la1_we),
1067:     .wd     (loc_alert_cause_la1_wd),
1068: 
1069:     // from internal hardware
1070:     .de     (hw2reg.loc_alert_cause[1].de),
1071:     .d      (hw2reg.loc_alert_cause[1].d ),
1072: 
1073:     // to internal hardware
1074:     .qe     (),
1075:     .q      (reg2hw.loc_alert_cause[1].q ),
1076: 
1077:     // to register interface (read)
1078:     .qs     (loc_alert_cause_la1_qs)
1079:   );
1080: 
1081: 
1082:   // F[la2]: 2:2
1083:   prim_subreg #(
1084:     .DW      (1),
1085:     .SWACCESS("W1C"),
1086:     .RESVAL  (1'h0)
1087:   ) u_loc_alert_cause_la2 (
1088:     .clk_i   (clk_i    ),
1089:     .rst_ni  (rst_ni  ),
1090: 
1091:     // from register interface
1092:     .we     (loc_alert_cause_la2_we),
1093:     .wd     (loc_alert_cause_la2_wd),
1094: 
1095:     // from internal hardware
1096:     .de     (hw2reg.loc_alert_cause[2].de),
1097:     .d      (hw2reg.loc_alert_cause[2].d ),
1098: 
1099:     // to internal hardware
1100:     .qe     (),
1101:     .q      (reg2hw.loc_alert_cause[2].q ),
1102: 
1103:     // to register interface (read)
1104:     .qs     (loc_alert_cause_la2_qs)
1105:   );
1106: 
1107: 
1108:   // F[la3]: 3:3
1109:   prim_subreg #(
1110:     .DW      (1),
1111:     .SWACCESS("W1C"),
1112:     .RESVAL  (1'h0)
1113:   ) u_loc_alert_cause_la3 (
1114:     .clk_i   (clk_i    ),
1115:     .rst_ni  (rst_ni  ),
1116: 
1117:     // from register interface
1118:     .we     (loc_alert_cause_la3_we),
1119:     .wd     (loc_alert_cause_la3_wd),
1120: 
1121:     // from internal hardware
1122:     .de     (hw2reg.loc_alert_cause[3].de),
1123:     .d      (hw2reg.loc_alert_cause[3].d ),
1124: 
1125:     // to internal hardware
1126:     .qe     (),
1127:     .q      (reg2hw.loc_alert_cause[3].q ),
1128: 
1129:     // to register interface (read)
1130:     .qs     (loc_alert_cause_la3_qs)
1131:   );
1132: 
1133: 
1134: 
1135:   // R[classa_ctrl]: V(False)
1136: 
1137:   //   F[en]: 0:0
1138:   prim_subreg #(
1139:     .DW      (1),
1140:     .SWACCESS("RW"),
1141:     .RESVAL  (1'h0)
1142:   ) u_classa_ctrl_en (
1143:     .clk_i   (clk_i    ),
1144:     .rst_ni  (rst_ni  ),
1145: 
1146:     // from register interface (qualified with register enable)
1147:     .we     (classa_ctrl_en_we & regen_qs),
1148:     .wd     (classa_ctrl_en_wd),
1149: 
1150:     // from internal hardware
1151:     .de     (1'b0),
1152:     .d      ('0  ),
1153: 
1154:     // to internal hardware
1155:     .qe     (),
1156:     .q      (reg2hw.classa_ctrl.en.q ),
1157: 
1158:     // to register interface (read)
1159:     .qs     (classa_ctrl_en_qs)
1160:   );
1161: 
1162: 
1163:   //   F[lock]: 1:1
1164:   prim_subreg #(
1165:     .DW      (1),
1166:     .SWACCESS("RW"),
1167:     .RESVAL  (1'h0)
1168:   ) u_classa_ctrl_lock (
1169:     .clk_i   (clk_i    ),
1170:     .rst_ni  (rst_ni  ),
1171: 
1172:     // from register interface (qualified with register enable)
1173:     .we     (classa_ctrl_lock_we & regen_qs),
1174:     .wd     (classa_ctrl_lock_wd),
1175: 
1176:     // from internal hardware
1177:     .de     (1'b0),
1178:     .d      ('0  ),
1179: 
1180:     // to internal hardware
1181:     .qe     (),
1182:     .q      (reg2hw.classa_ctrl.lock.q ),
1183: 
1184:     // to register interface (read)
1185:     .qs     (classa_ctrl_lock_qs)
1186:   );
1187: 
1188: 
1189:   //   F[en_e0]: 2:2
1190:   prim_subreg #(
1191:     .DW      (1),
1192:     .SWACCESS("RW"),
1193:     .RESVAL  (1'h1)
1194:   ) u_classa_ctrl_en_e0 (
1195:     .clk_i   (clk_i    ),
1196:     .rst_ni  (rst_ni  ),
1197: 
1198:     // from register interface (qualified with register enable)
1199:     .we     (classa_ctrl_en_e0_we & regen_qs),
1200:     .wd     (classa_ctrl_en_e0_wd),
1201: 
1202:     // from internal hardware
1203:     .de     (1'b0),
1204:     .d      ('0  ),
1205: 
1206:     // to internal hardware
1207:     .qe     (),
1208:     .q      (reg2hw.classa_ctrl.en_e0.q ),
1209: 
1210:     // to register interface (read)
1211:     .qs     (classa_ctrl_en_e0_qs)
1212:   );
1213: 
1214: 
1215:   //   F[en_e1]: 3:3
1216:   prim_subreg #(
1217:     .DW      (1),
1218:     .SWACCESS("RW"),
1219:     .RESVAL  (1'h1)
1220:   ) u_classa_ctrl_en_e1 (
1221:     .clk_i   (clk_i    ),
1222:     .rst_ni  (rst_ni  ),
1223: 
1224:     // from register interface (qualified with register enable)
1225:     .we     (classa_ctrl_en_e1_we & regen_qs),
1226:     .wd     (classa_ctrl_en_e1_wd),
1227: 
1228:     // from internal hardware
1229:     .de     (1'b0),
1230:     .d      ('0  ),
1231: 
1232:     // to internal hardware
1233:     .qe     (),
1234:     .q      (reg2hw.classa_ctrl.en_e1.q ),
1235: 
1236:     // to register interface (read)
1237:     .qs     (classa_ctrl_en_e1_qs)
1238:   );
1239: 
1240: 
1241:   //   F[en_e2]: 4:4
1242:   prim_subreg #(
1243:     .DW      (1),
1244:     .SWACCESS("RW"),
1245:     .RESVAL  (1'h1)
1246:   ) u_classa_ctrl_en_e2 (
1247:     .clk_i   (clk_i    ),
1248:     .rst_ni  (rst_ni  ),
1249: 
1250:     // from register interface (qualified with register enable)
1251:     .we     (classa_ctrl_en_e2_we & regen_qs),
1252:     .wd     (classa_ctrl_en_e2_wd),
1253: 
1254:     // from internal hardware
1255:     .de     (1'b0),
1256:     .d      ('0  ),
1257: 
1258:     // to internal hardware
1259:     .qe     (),
1260:     .q      (reg2hw.classa_ctrl.en_e2.q ),
1261: 
1262:     // to register interface (read)
1263:     .qs     (classa_ctrl_en_e2_qs)
1264:   );
1265: 
1266: 
1267:   //   F[en_e3]: 5:5
1268:   prim_subreg #(
1269:     .DW      (1),
1270:     .SWACCESS("RW"),
1271:     .RESVAL  (1'h1)
1272:   ) u_classa_ctrl_en_e3 (
1273:     .clk_i   (clk_i    ),
1274:     .rst_ni  (rst_ni  ),
1275: 
1276:     // from register interface (qualified with register enable)
1277:     .we     (classa_ctrl_en_e3_we & regen_qs),
1278:     .wd     (classa_ctrl_en_e3_wd),
1279: 
1280:     // from internal hardware
1281:     .de     (1'b0),
1282:     .d      ('0  ),
1283: 
1284:     // to internal hardware
1285:     .qe     (),
1286:     .q      (reg2hw.classa_ctrl.en_e3.q ),
1287: 
1288:     // to register interface (read)
1289:     .qs     (classa_ctrl_en_e3_qs)
1290:   );
1291: 
1292: 
1293:   //   F[map_e0]: 7:6
1294:   prim_subreg #(
1295:     .DW      (2),
1296:     .SWACCESS("RW"),
1297:     .RESVAL  (2'h0)
1298:   ) u_classa_ctrl_map_e0 (
1299:     .clk_i   (clk_i    ),
1300:     .rst_ni  (rst_ni  ),
1301: 
1302:     // from register interface (qualified with register enable)
1303:     .we     (classa_ctrl_map_e0_we & regen_qs),
1304:     .wd     (classa_ctrl_map_e0_wd),
1305: 
1306:     // from internal hardware
1307:     .de     (1'b0),
1308:     .d      ('0  ),
1309: 
1310:     // to internal hardware
1311:     .qe     (),
1312:     .q      (reg2hw.classa_ctrl.map_e0.q ),
1313: 
1314:     // to register interface (read)
1315:     .qs     (classa_ctrl_map_e0_qs)
1316:   );
1317: 
1318: 
1319:   //   F[map_e1]: 9:8
1320:   prim_subreg #(
1321:     .DW      (2),
1322:     .SWACCESS("RW"),
1323:     .RESVAL  (2'h1)
1324:   ) u_classa_ctrl_map_e1 (
1325:     .clk_i   (clk_i    ),
1326:     .rst_ni  (rst_ni  ),
1327: 
1328:     // from register interface (qualified with register enable)
1329:     .we     (classa_ctrl_map_e1_we & regen_qs),
1330:     .wd     (classa_ctrl_map_e1_wd),
1331: 
1332:     // from internal hardware
1333:     .de     (1'b0),
1334:     .d      ('0  ),
1335: 
1336:     // to internal hardware
1337:     .qe     (),
1338:     .q      (reg2hw.classa_ctrl.map_e1.q ),
1339: 
1340:     // to register interface (read)
1341:     .qs     (classa_ctrl_map_e1_qs)
1342:   );
1343: 
1344: 
1345:   //   F[map_e2]: 11:10
1346:   prim_subreg #(
1347:     .DW      (2),
1348:     .SWACCESS("RW"),
1349:     .RESVAL  (2'h2)
1350:   ) u_classa_ctrl_map_e2 (
1351:     .clk_i   (clk_i    ),
1352:     .rst_ni  (rst_ni  ),
1353: 
1354:     // from register interface (qualified with register enable)
1355:     .we     (classa_ctrl_map_e2_we & regen_qs),
1356:     .wd     (classa_ctrl_map_e2_wd),
1357: 
1358:     // from internal hardware
1359:     .de     (1'b0),
1360:     .d      ('0  ),
1361: 
1362:     // to internal hardware
1363:     .qe     (),
1364:     .q      (reg2hw.classa_ctrl.map_e2.q ),
1365: 
1366:     // to register interface (read)
1367:     .qs     (classa_ctrl_map_e2_qs)
1368:   );
1369: 
1370: 
1371:   //   F[map_e3]: 13:12
1372:   prim_subreg #(
1373:     .DW      (2),
1374:     .SWACCESS("RW"),
1375:     .RESVAL  (2'h3)
1376:   ) u_classa_ctrl_map_e3 (
1377:     .clk_i   (clk_i    ),
1378:     .rst_ni  (rst_ni  ),
1379: 
1380:     // from register interface (qualified with register enable)
1381:     .we     (classa_ctrl_map_e3_we & regen_qs),
1382:     .wd     (classa_ctrl_map_e3_wd),
1383: 
1384:     // from internal hardware
1385:     .de     (1'b0),
1386:     .d      ('0  ),
1387: 
1388:     // to internal hardware
1389:     .qe     (),
1390:     .q      (reg2hw.classa_ctrl.map_e3.q ),
1391: 
1392:     // to register interface (read)
1393:     .qs     (classa_ctrl_map_e3_qs)
1394:   );
1395: 
1396: 
1397:   // R[classa_clren]: V(False)
1398: 
1399:   prim_subreg #(
1400:     .DW      (1),
1401:     .SWACCESS("W1C"),
1402:     .RESVAL  (1'h1)
1403:   ) u_classa_clren (
1404:     .clk_i   (clk_i    ),
1405:     .rst_ni  (rst_ni  ),
1406: 
1407:     // from register interface
1408:     .we     (classa_clren_we),
1409:     .wd     (classa_clren_wd),
1410: 
1411:     // from internal hardware
1412:     .de     (hw2reg.classa_clren.de),
1413:     .d      (hw2reg.classa_clren.d ),
1414: 
1415:     // to internal hardware
1416:     .qe     (),
1417:     .q      (),
1418: 
1419:     // to register interface (read)
1420:     .qs     (classa_clren_qs)
1421:   );
1422: 
1423: 
1424:   // R[classa_clr]: V(False)
1425: 
1426:   prim_subreg #(
1427:     .DW      (1),
1428:     .SWACCESS("WO"),
1429:     .RESVAL  (1'h0)
1430:   ) u_classa_clr (
1431:     .clk_i   (clk_i    ),
1432:     .rst_ni  (rst_ni  ),
1433: 
1434:     // from register interface (qualified with register enable)
1435:     .we     (classa_clr_we & classa_clren_qs),
1436:     .wd     (classa_clr_wd),
1437: 
1438:     // from internal hardware
1439:     .de     (1'b0),
1440:     .d      ('0  ),
1441: 
1442:     // to internal hardware
1443:     .qe     (reg2hw.classa_clr.qe),
1444:     .q      (reg2hw.classa_clr.q ),
1445: 
1446:     .qs     ()
1447:   );
1448: 
1449: 
1450:   // R[classa_accum_cnt]: V(True)
1451: 
1452:   prim_subreg_ext #(
1453:     .DW    (16)
1454:   ) u_classa_accum_cnt (
1455:     .re     (classa_accum_cnt_re),
1456:     .we     (1'b0),
1457:     .wd     ('0),
1458:     .d      (hw2reg.classa_accum_cnt.d),
1459:     .qre    (),
1460:     .qe     (),
1461:     .q      (),
1462:     .qs     (classa_accum_cnt_qs)
1463:   );
1464: 
1465: 
1466:   // R[classa_accum_thresh]: V(False)
1467: 
1468:   prim_subreg #(
1469:     .DW      (16),
1470:     .SWACCESS("RW"),
1471:     .RESVAL  (16'h0)
1472:   ) u_classa_accum_thresh (
1473:     .clk_i   (clk_i    ),
1474:     .rst_ni  (rst_ni  ),
1475: 
1476:     // from register interface (qualified with register enable)
1477:     .we     (classa_accum_thresh_we & regen_qs),
1478:     .wd     (classa_accum_thresh_wd),
1479: 
1480:     // from internal hardware
1481:     .de     (1'b0),
1482:     .d      ('0  ),
1483: 
1484:     // to internal hardware
1485:     .qe     (),
1486:     .q      (reg2hw.classa_accum_thresh.q ),
1487: 
1488:     // to register interface (read)
1489:     .qs     (classa_accum_thresh_qs)
1490:   );
1491: 
1492: 
1493:   // R[classa_timeout_cyc]: V(False)
1494: 
1495:   prim_subreg #(
1496:     .DW      (32),
1497:     .SWACCESS("RW"),
1498:     .RESVAL  (32'h0)
1499:   ) u_classa_timeout_cyc (
1500:     .clk_i   (clk_i    ),
1501:     .rst_ni  (rst_ni  ),
1502: 
1503:     // from register interface (qualified with register enable)
1504:     .we     (classa_timeout_cyc_we & regen_qs),
1505:     .wd     (classa_timeout_cyc_wd),
1506: 
1507:     // from internal hardware
1508:     .de     (1'b0),
1509:     .d      ('0  ),
1510: 
1511:     // to internal hardware
1512:     .qe     (),
1513:     .q      (reg2hw.classa_timeout_cyc.q ),
1514: 
1515:     // to register interface (read)
1516:     .qs     (classa_timeout_cyc_qs)
1517:   );
1518: 
1519: 
1520:   // R[classa_phase0_cyc]: V(False)
1521: 
1522:   prim_subreg #(
1523:     .DW      (32),
1524:     .SWACCESS("RW"),
1525:     .RESVAL  (32'h0)
1526:   ) u_classa_phase0_cyc (
1527:     .clk_i   (clk_i    ),
1528:     .rst_ni  (rst_ni  ),
1529: 
1530:     // from register interface (qualified with register enable)
1531:     .we     (classa_phase0_cyc_we & regen_qs),
1532:     .wd     (classa_phase0_cyc_wd),
1533: 
1534:     // from internal hardware
1535:     .de     (1'b0),
1536:     .d      ('0  ),
1537: 
1538:     // to internal hardware
1539:     .qe     (),
1540:     .q      (reg2hw.classa_phase0_cyc.q ),
1541: 
1542:     // to register interface (read)
1543:     .qs     (classa_phase0_cyc_qs)
1544:   );
1545: 
1546: 
1547:   // R[classa_phase1_cyc]: V(False)
1548: 
1549:   prim_subreg #(
1550:     .DW      (32),
1551:     .SWACCESS("RW"),
1552:     .RESVAL  (32'h0)
1553:   ) u_classa_phase1_cyc (
1554:     .clk_i   (clk_i    ),
1555:     .rst_ni  (rst_ni  ),
1556: 
1557:     // from register interface (qualified with register enable)
1558:     .we     (classa_phase1_cyc_we & regen_qs),
1559:     .wd     (classa_phase1_cyc_wd),
1560: 
1561:     // from internal hardware
1562:     .de     (1'b0),
1563:     .d      ('0  ),
1564: 
1565:     // to internal hardware
1566:     .qe     (),
1567:     .q      (reg2hw.classa_phase1_cyc.q ),
1568: 
1569:     // to register interface (read)
1570:     .qs     (classa_phase1_cyc_qs)
1571:   );
1572: 
1573: 
1574:   // R[classa_phase2_cyc]: V(False)
1575: 
1576:   prim_subreg #(
1577:     .DW      (32),
1578:     .SWACCESS("RW"),
1579:     .RESVAL  (32'h0)
1580:   ) u_classa_phase2_cyc (
1581:     .clk_i   (clk_i    ),
1582:     .rst_ni  (rst_ni  ),
1583: 
1584:     // from register interface (qualified with register enable)
1585:     .we     (classa_phase2_cyc_we & regen_qs),
1586:     .wd     (classa_phase2_cyc_wd),
1587: 
1588:     // from internal hardware
1589:     .de     (1'b0),
1590:     .d      ('0  ),
1591: 
1592:     // to internal hardware
1593:     .qe     (),
1594:     .q      (reg2hw.classa_phase2_cyc.q ),
1595: 
1596:     // to register interface (read)
1597:     .qs     (classa_phase2_cyc_qs)
1598:   );
1599: 
1600: 
1601:   // R[classa_phase3_cyc]: V(False)
1602: 
1603:   prim_subreg #(
1604:     .DW      (32),
1605:     .SWACCESS("RW"),
1606:     .RESVAL  (32'h0)
1607:   ) u_classa_phase3_cyc (
1608:     .clk_i   (clk_i    ),
1609:     .rst_ni  (rst_ni  ),
1610: 
1611:     // from register interface (qualified with register enable)
1612:     .we     (classa_phase3_cyc_we & regen_qs),
1613:     .wd     (classa_phase3_cyc_wd),
1614: 
1615:     // from internal hardware
1616:     .de     (1'b0),
1617:     .d      ('0  ),
1618: 
1619:     // to internal hardware
1620:     .qe     (),
1621:     .q      (reg2hw.classa_phase3_cyc.q ),
1622: 
1623:     // to register interface (read)
1624:     .qs     (classa_phase3_cyc_qs)
1625:   );
1626: 
1627: 
1628:   // R[classa_esc_cnt]: V(True)
1629: 
1630:   prim_subreg_ext #(
1631:     .DW    (32)
1632:   ) u_classa_esc_cnt (
1633:     .re     (classa_esc_cnt_re),
1634:     .we     (1'b0),
1635:     .wd     ('0),
1636:     .d      (hw2reg.classa_esc_cnt.d),
1637:     .qre    (),
1638:     .qe     (),
1639:     .q      (),
1640:     .qs     (classa_esc_cnt_qs)
1641:   );
1642: 
1643: 
1644:   // R[classa_state]: V(True)
1645: 
1646:   prim_subreg_ext #(
1647:     .DW    (3)
1648:   ) u_classa_state (
1649:     .re     (classa_state_re),
1650:     .we     (1'b0),
1651:     .wd     ('0),
1652:     .d      (hw2reg.classa_state.d),
1653:     .qre    (),
1654:     .qe     (),
1655:     .q      (),
1656:     .qs     (classa_state_qs)
1657:   );
1658: 
1659: 
1660:   // R[classb_ctrl]: V(False)
1661: 
1662:   //   F[en]: 0:0
1663:   prim_subreg #(
1664:     .DW      (1),
1665:     .SWACCESS("RW"),
1666:     .RESVAL  (1'h0)
1667:   ) u_classb_ctrl_en (
1668:     .clk_i   (clk_i    ),
1669:     .rst_ni  (rst_ni  ),
1670: 
1671:     // from register interface (qualified with register enable)
1672:     .we     (classb_ctrl_en_we & regen_qs),
1673:     .wd     (classb_ctrl_en_wd),
1674: 
1675:     // from internal hardware
1676:     .de     (1'b0),
1677:     .d      ('0  ),
1678: 
1679:     // to internal hardware
1680:     .qe     (),
1681:     .q      (reg2hw.classb_ctrl.en.q ),
1682: 
1683:     // to register interface (read)
1684:     .qs     (classb_ctrl_en_qs)
1685:   );
1686: 
1687: 
1688:   //   F[lock]: 1:1
1689:   prim_subreg #(
1690:     .DW      (1),
1691:     .SWACCESS("RW"),
1692:     .RESVAL  (1'h0)
1693:   ) u_classb_ctrl_lock (
1694:     .clk_i   (clk_i    ),
1695:     .rst_ni  (rst_ni  ),
1696: 
1697:     // from register interface (qualified with register enable)
1698:     .we     (classb_ctrl_lock_we & regen_qs),
1699:     .wd     (classb_ctrl_lock_wd),
1700: 
1701:     // from internal hardware
1702:     .de     (1'b0),
1703:     .d      ('0  ),
1704: 
1705:     // to internal hardware
1706:     .qe     (),
1707:     .q      (reg2hw.classb_ctrl.lock.q ),
1708: 
1709:     // to register interface (read)
1710:     .qs     (classb_ctrl_lock_qs)
1711:   );
1712: 
1713: 
1714:   //   F[en_e0]: 2:2
1715:   prim_subreg #(
1716:     .DW      (1),
1717:     .SWACCESS("RW"),
1718:     .RESVAL  (1'h1)
1719:   ) u_classb_ctrl_en_e0 (
1720:     .clk_i   (clk_i    ),
1721:     .rst_ni  (rst_ni  ),
1722: 
1723:     // from register interface (qualified with register enable)
1724:     .we     (classb_ctrl_en_e0_we & regen_qs),
1725:     .wd     (classb_ctrl_en_e0_wd),
1726: 
1727:     // from internal hardware
1728:     .de     (1'b0),
1729:     .d      ('0  ),
1730: 
1731:     // to internal hardware
1732:     .qe     (),
1733:     .q      (reg2hw.classb_ctrl.en_e0.q ),
1734: 
1735:     // to register interface (read)
1736:     .qs     (classb_ctrl_en_e0_qs)
1737:   );
1738: 
1739: 
1740:   //   F[en_e1]: 3:3
1741:   prim_subreg #(
1742:     .DW      (1),
1743:     .SWACCESS("RW"),
1744:     .RESVAL  (1'h1)
1745:   ) u_classb_ctrl_en_e1 (
1746:     .clk_i   (clk_i    ),
1747:     .rst_ni  (rst_ni  ),
1748: 
1749:     // from register interface (qualified with register enable)
1750:     .we     (classb_ctrl_en_e1_we & regen_qs),
1751:     .wd     (classb_ctrl_en_e1_wd),
1752: 
1753:     // from internal hardware
1754:     .de     (1'b0),
1755:     .d      ('0  ),
1756: 
1757:     // to internal hardware
1758:     .qe     (),
1759:     .q      (reg2hw.classb_ctrl.en_e1.q ),
1760: 
1761:     // to register interface (read)
1762:     .qs     (classb_ctrl_en_e1_qs)
1763:   );
1764: 
1765: 
1766:   //   F[en_e2]: 4:4
1767:   prim_subreg #(
1768:     .DW      (1),
1769:     .SWACCESS("RW"),
1770:     .RESVAL  (1'h1)
1771:   ) u_classb_ctrl_en_e2 (
1772:     .clk_i   (clk_i    ),
1773:     .rst_ni  (rst_ni  ),
1774: 
1775:     // from register interface (qualified with register enable)
1776:     .we     (classb_ctrl_en_e2_we & regen_qs),
1777:     .wd     (classb_ctrl_en_e2_wd),
1778: 
1779:     // from internal hardware
1780:     .de     (1'b0),
1781:     .d      ('0  ),
1782: 
1783:     // to internal hardware
1784:     .qe     (),
1785:     .q      (reg2hw.classb_ctrl.en_e2.q ),
1786: 
1787:     // to register interface (read)
1788:     .qs     (classb_ctrl_en_e2_qs)
1789:   );
1790: 
1791: 
1792:   //   F[en_e3]: 5:5
1793:   prim_subreg #(
1794:     .DW      (1),
1795:     .SWACCESS("RW"),
1796:     .RESVAL  (1'h1)
1797:   ) u_classb_ctrl_en_e3 (
1798:     .clk_i   (clk_i    ),
1799:     .rst_ni  (rst_ni  ),
1800: 
1801:     // from register interface (qualified with register enable)
1802:     .we     (classb_ctrl_en_e3_we & regen_qs),
1803:     .wd     (classb_ctrl_en_e3_wd),
1804: 
1805:     // from internal hardware
1806:     .de     (1'b0),
1807:     .d      ('0  ),
1808: 
1809:     // to internal hardware
1810:     .qe     (),
1811:     .q      (reg2hw.classb_ctrl.en_e3.q ),
1812: 
1813:     // to register interface (read)
1814:     .qs     (classb_ctrl_en_e3_qs)
1815:   );
1816: 
1817: 
1818:   //   F[map_e0]: 7:6
1819:   prim_subreg #(
1820:     .DW      (2),
1821:     .SWACCESS("RW"),
1822:     .RESVAL  (2'h0)
1823:   ) u_classb_ctrl_map_e0 (
1824:     .clk_i   (clk_i    ),
1825:     .rst_ni  (rst_ni  ),
1826: 
1827:     // from register interface (qualified with register enable)
1828:     .we     (classb_ctrl_map_e0_we & regen_qs),
1829:     .wd     (classb_ctrl_map_e0_wd),
1830: 
1831:     // from internal hardware
1832:     .de     (1'b0),
1833:     .d      ('0  ),
1834: 
1835:     // to internal hardware
1836:     .qe     (),
1837:     .q      (reg2hw.classb_ctrl.map_e0.q ),
1838: 
1839:     // to register interface (read)
1840:     .qs     (classb_ctrl_map_e0_qs)
1841:   );
1842: 
1843: 
1844:   //   F[map_e1]: 9:8
1845:   prim_subreg #(
1846:     .DW      (2),
1847:     .SWACCESS("RW"),
1848:     .RESVAL  (2'h1)
1849:   ) u_classb_ctrl_map_e1 (
1850:     .clk_i   (clk_i    ),
1851:     .rst_ni  (rst_ni  ),
1852: 
1853:     // from register interface (qualified with register enable)
1854:     .we     (classb_ctrl_map_e1_we & regen_qs),
1855:     .wd     (classb_ctrl_map_e1_wd),
1856: 
1857:     // from internal hardware
1858:     .de     (1'b0),
1859:     .d      ('0  ),
1860: 
1861:     // to internal hardware
1862:     .qe     (),
1863:     .q      (reg2hw.classb_ctrl.map_e1.q ),
1864: 
1865:     // to register interface (read)
1866:     .qs     (classb_ctrl_map_e1_qs)
1867:   );
1868: 
1869: 
1870:   //   F[map_e2]: 11:10
1871:   prim_subreg #(
1872:     .DW      (2),
1873:     .SWACCESS("RW"),
1874:     .RESVAL  (2'h2)
1875:   ) u_classb_ctrl_map_e2 (
1876:     .clk_i   (clk_i    ),
1877:     .rst_ni  (rst_ni  ),
1878: 
1879:     // from register interface (qualified with register enable)
1880:     .we     (classb_ctrl_map_e2_we & regen_qs),
1881:     .wd     (classb_ctrl_map_e2_wd),
1882: 
1883:     // from internal hardware
1884:     .de     (1'b0),
1885:     .d      ('0  ),
1886: 
1887:     // to internal hardware
1888:     .qe     (),
1889:     .q      (reg2hw.classb_ctrl.map_e2.q ),
1890: 
1891:     // to register interface (read)
1892:     .qs     (classb_ctrl_map_e2_qs)
1893:   );
1894: 
1895: 
1896:   //   F[map_e3]: 13:12
1897:   prim_subreg #(
1898:     .DW      (2),
1899:     .SWACCESS("RW"),
1900:     .RESVAL  (2'h3)
1901:   ) u_classb_ctrl_map_e3 (
1902:     .clk_i   (clk_i    ),
1903:     .rst_ni  (rst_ni  ),
1904: 
1905:     // from register interface (qualified with register enable)
1906:     .we     (classb_ctrl_map_e3_we & regen_qs),
1907:     .wd     (classb_ctrl_map_e3_wd),
1908: 
1909:     // from internal hardware
1910:     .de     (1'b0),
1911:     .d      ('0  ),
1912: 
1913:     // to internal hardware
1914:     .qe     (),
1915:     .q      (reg2hw.classb_ctrl.map_e3.q ),
1916: 
1917:     // to register interface (read)
1918:     .qs     (classb_ctrl_map_e3_qs)
1919:   );
1920: 
1921: 
1922:   // R[classb_clren]: V(False)
1923: 
1924:   prim_subreg #(
1925:     .DW      (1),
1926:     .SWACCESS("W1C"),
1927:     .RESVAL  (1'h1)
1928:   ) u_classb_clren (
1929:     .clk_i   (clk_i    ),
1930:     .rst_ni  (rst_ni  ),
1931: 
1932:     // from register interface
1933:     .we     (classb_clren_we),
1934:     .wd     (classb_clren_wd),
1935: 
1936:     // from internal hardware
1937:     .de     (hw2reg.classb_clren.de),
1938:     .d      (hw2reg.classb_clren.d ),
1939: 
1940:     // to internal hardware
1941:     .qe     (),
1942:     .q      (),
1943: 
1944:     // to register interface (read)
1945:     .qs     (classb_clren_qs)
1946:   );
1947: 
1948: 
1949:   // R[classb_clr]: V(False)
1950: 
1951:   prim_subreg #(
1952:     .DW      (1),
1953:     .SWACCESS("WO"),
1954:     .RESVAL  (1'h0)
1955:   ) u_classb_clr (
1956:     .clk_i   (clk_i    ),
1957:     .rst_ni  (rst_ni  ),
1958: 
1959:     // from register interface (qualified with register enable)
1960:     .we     (classb_clr_we & classb_clren_qs),
1961:     .wd     (classb_clr_wd),
1962: 
1963:     // from internal hardware
1964:     .de     (1'b0),
1965:     .d      ('0  ),
1966: 
1967:     // to internal hardware
1968:     .qe     (reg2hw.classb_clr.qe),
1969:     .q      (reg2hw.classb_clr.q ),
1970: 
1971:     .qs     ()
1972:   );
1973: 
1974: 
1975:   // R[classb_accum_cnt]: V(True)
1976: 
1977:   prim_subreg_ext #(
1978:     .DW    (16)
1979:   ) u_classb_accum_cnt (
1980:     .re     (classb_accum_cnt_re),
1981:     .we     (1'b0),
1982:     .wd     ('0),
1983:     .d      (hw2reg.classb_accum_cnt.d),
1984:     .qre    (),
1985:     .qe     (),
1986:     .q      (),
1987:     .qs     (classb_accum_cnt_qs)
1988:   );
1989: 
1990: 
1991:   // R[classb_accum_thresh]: V(False)
1992: 
1993:   prim_subreg #(
1994:     .DW      (16),
1995:     .SWACCESS("RW"),
1996:     .RESVAL  (16'h0)
1997:   ) u_classb_accum_thresh (
1998:     .clk_i   (clk_i    ),
1999:     .rst_ni  (rst_ni  ),
2000: 
2001:     // from register interface (qualified with register enable)
2002:     .we     (classb_accum_thresh_we & regen_qs),
2003:     .wd     (classb_accum_thresh_wd),
2004: 
2005:     // from internal hardware
2006:     .de     (1'b0),
2007:     .d      ('0  ),
2008: 
2009:     // to internal hardware
2010:     .qe     (),
2011:     .q      (reg2hw.classb_accum_thresh.q ),
2012: 
2013:     // to register interface (read)
2014:     .qs     (classb_accum_thresh_qs)
2015:   );
2016: 
2017: 
2018:   // R[classb_timeout_cyc]: V(False)
2019: 
2020:   prim_subreg #(
2021:     .DW      (32),
2022:     .SWACCESS("RW"),
2023:     .RESVAL  (32'h0)
2024:   ) u_classb_timeout_cyc (
2025:     .clk_i   (clk_i    ),
2026:     .rst_ni  (rst_ni  ),
2027: 
2028:     // from register interface (qualified with register enable)
2029:     .we     (classb_timeout_cyc_we & regen_qs),
2030:     .wd     (classb_timeout_cyc_wd),
2031: 
2032:     // from internal hardware
2033:     .de     (1'b0),
2034:     .d      ('0  ),
2035: 
2036:     // to internal hardware
2037:     .qe     (),
2038:     .q      (reg2hw.classb_timeout_cyc.q ),
2039: 
2040:     // to register interface (read)
2041:     .qs     (classb_timeout_cyc_qs)
2042:   );
2043: 
2044: 
2045:   // R[classb_phase0_cyc]: V(False)
2046: 
2047:   prim_subreg #(
2048:     .DW      (32),
2049:     .SWACCESS("RW"),
2050:     .RESVAL  (32'h0)
2051:   ) u_classb_phase0_cyc (
2052:     .clk_i   (clk_i    ),
2053:     .rst_ni  (rst_ni  ),
2054: 
2055:     // from register interface (qualified with register enable)
2056:     .we     (classb_phase0_cyc_we & regen_qs),
2057:     .wd     (classb_phase0_cyc_wd),
2058: 
2059:     // from internal hardware
2060:     .de     (1'b0),
2061:     .d      ('0  ),
2062: 
2063:     // to internal hardware
2064:     .qe     (),
2065:     .q      (reg2hw.classb_phase0_cyc.q ),
2066: 
2067:     // to register interface (read)
2068:     .qs     (classb_phase0_cyc_qs)
2069:   );
2070: 
2071: 
2072:   // R[classb_phase1_cyc]: V(False)
2073: 
2074:   prim_subreg #(
2075:     .DW      (32),
2076:     .SWACCESS("RW"),
2077:     .RESVAL  (32'h0)
2078:   ) u_classb_phase1_cyc (
2079:     .clk_i   (clk_i    ),
2080:     .rst_ni  (rst_ni  ),
2081: 
2082:     // from register interface (qualified with register enable)
2083:     .we     (classb_phase1_cyc_we & regen_qs),
2084:     .wd     (classb_phase1_cyc_wd),
2085: 
2086:     // from internal hardware
2087:     .de     (1'b0),
2088:     .d      ('0  ),
2089: 
2090:     // to internal hardware
2091:     .qe     (),
2092:     .q      (reg2hw.classb_phase1_cyc.q ),
2093: 
2094:     // to register interface (read)
2095:     .qs     (classb_phase1_cyc_qs)
2096:   );
2097: 
2098: 
2099:   // R[classb_phase2_cyc]: V(False)
2100: 
2101:   prim_subreg #(
2102:     .DW      (32),
2103:     .SWACCESS("RW"),
2104:     .RESVAL  (32'h0)
2105:   ) u_classb_phase2_cyc (
2106:     .clk_i   (clk_i    ),
2107:     .rst_ni  (rst_ni  ),
2108: 
2109:     // from register interface (qualified with register enable)
2110:     .we     (classb_phase2_cyc_we & regen_qs),
2111:     .wd     (classb_phase2_cyc_wd),
2112: 
2113:     // from internal hardware
2114:     .de     (1'b0),
2115:     .d      ('0  ),
2116: 
2117:     // to internal hardware
2118:     .qe     (),
2119:     .q      (reg2hw.classb_phase2_cyc.q ),
2120: 
2121:     // to register interface (read)
2122:     .qs     (classb_phase2_cyc_qs)
2123:   );
2124: 
2125: 
2126:   // R[classb_phase3_cyc]: V(False)
2127: 
2128:   prim_subreg #(
2129:     .DW      (32),
2130:     .SWACCESS("RW"),
2131:     .RESVAL  (32'h0)
2132:   ) u_classb_phase3_cyc (
2133:     .clk_i   (clk_i    ),
2134:     .rst_ni  (rst_ni  ),
2135: 
2136:     // from register interface (qualified with register enable)
2137:     .we     (classb_phase3_cyc_we & regen_qs),
2138:     .wd     (classb_phase3_cyc_wd),
2139: 
2140:     // from internal hardware
2141:     .de     (1'b0),
2142:     .d      ('0  ),
2143: 
2144:     // to internal hardware
2145:     .qe     (),
2146:     .q      (reg2hw.classb_phase3_cyc.q ),
2147: 
2148:     // to register interface (read)
2149:     .qs     (classb_phase3_cyc_qs)
2150:   );
2151: 
2152: 
2153:   // R[classb_esc_cnt]: V(True)
2154: 
2155:   prim_subreg_ext #(
2156:     .DW    (32)
2157:   ) u_classb_esc_cnt (
2158:     .re     (classb_esc_cnt_re),
2159:     .we     (1'b0),
2160:     .wd     ('0),
2161:     .d      (hw2reg.classb_esc_cnt.d),
2162:     .qre    (),
2163:     .qe     (),
2164:     .q      (),
2165:     .qs     (classb_esc_cnt_qs)
2166:   );
2167: 
2168: 
2169:   // R[classb_state]: V(True)
2170: 
2171:   prim_subreg_ext #(
2172:     .DW    (3)
2173:   ) u_classb_state (
2174:     .re     (classb_state_re),
2175:     .we     (1'b0),
2176:     .wd     ('0),
2177:     .d      (hw2reg.classb_state.d),
2178:     .qre    (),
2179:     .qe     (),
2180:     .q      (),
2181:     .qs     (classb_state_qs)
2182:   );
2183: 
2184: 
2185:   // R[classc_ctrl]: V(False)
2186: 
2187:   //   F[en]: 0:0
2188:   prim_subreg #(
2189:     .DW      (1),
2190:     .SWACCESS("RW"),
2191:     .RESVAL  (1'h0)
2192:   ) u_classc_ctrl_en (
2193:     .clk_i   (clk_i    ),
2194:     .rst_ni  (rst_ni  ),
2195: 
2196:     // from register interface (qualified with register enable)
2197:     .we     (classc_ctrl_en_we & regen_qs),
2198:     .wd     (classc_ctrl_en_wd),
2199: 
2200:     // from internal hardware
2201:     .de     (1'b0),
2202:     .d      ('0  ),
2203: 
2204:     // to internal hardware
2205:     .qe     (),
2206:     .q      (reg2hw.classc_ctrl.en.q ),
2207: 
2208:     // to register interface (read)
2209:     .qs     (classc_ctrl_en_qs)
2210:   );
2211: 
2212: 
2213:   //   F[lock]: 1:1
2214:   prim_subreg #(
2215:     .DW      (1),
2216:     .SWACCESS("RW"),
2217:     .RESVAL  (1'h0)
2218:   ) u_classc_ctrl_lock (
2219:     .clk_i   (clk_i    ),
2220:     .rst_ni  (rst_ni  ),
2221: 
2222:     // from register interface (qualified with register enable)
2223:     .we     (classc_ctrl_lock_we & regen_qs),
2224:     .wd     (classc_ctrl_lock_wd),
2225: 
2226:     // from internal hardware
2227:     .de     (1'b0),
2228:     .d      ('0  ),
2229: 
2230:     // to internal hardware
2231:     .qe     (),
2232:     .q      (reg2hw.classc_ctrl.lock.q ),
2233: 
2234:     // to register interface (read)
2235:     .qs     (classc_ctrl_lock_qs)
2236:   );
2237: 
2238: 
2239:   //   F[en_e0]: 2:2
2240:   prim_subreg #(
2241:     .DW      (1),
2242:     .SWACCESS("RW"),
2243:     .RESVAL  (1'h1)
2244:   ) u_classc_ctrl_en_e0 (
2245:     .clk_i   (clk_i    ),
2246:     .rst_ni  (rst_ni  ),
2247: 
2248:     // from register interface (qualified with register enable)
2249:     .we     (classc_ctrl_en_e0_we & regen_qs),
2250:     .wd     (classc_ctrl_en_e0_wd),
2251: 
2252:     // from internal hardware
2253:     .de     (1'b0),
2254:     .d      ('0  ),
2255: 
2256:     // to internal hardware
2257:     .qe     (),
2258:     .q      (reg2hw.classc_ctrl.en_e0.q ),
2259: 
2260:     // to register interface (read)
2261:     .qs     (classc_ctrl_en_e0_qs)
2262:   );
2263: 
2264: 
2265:   //   F[en_e1]: 3:3
2266:   prim_subreg #(
2267:     .DW      (1),
2268:     .SWACCESS("RW"),
2269:     .RESVAL  (1'h1)
2270:   ) u_classc_ctrl_en_e1 (
2271:     .clk_i   (clk_i    ),
2272:     .rst_ni  (rst_ni  ),
2273: 
2274:     // from register interface (qualified with register enable)
2275:     .we     (classc_ctrl_en_e1_we & regen_qs),
2276:     .wd     (classc_ctrl_en_e1_wd),
2277: 
2278:     // from internal hardware
2279:     .de     (1'b0),
2280:     .d      ('0  ),
2281: 
2282:     // to internal hardware
2283:     .qe     (),
2284:     .q      (reg2hw.classc_ctrl.en_e1.q ),
2285: 
2286:     // to register interface (read)
2287:     .qs     (classc_ctrl_en_e1_qs)
2288:   );
2289: 
2290: 
2291:   //   F[en_e2]: 4:4
2292:   prim_subreg #(
2293:     .DW      (1),
2294:     .SWACCESS("RW"),
2295:     .RESVAL  (1'h1)
2296:   ) u_classc_ctrl_en_e2 (
2297:     .clk_i   (clk_i    ),
2298:     .rst_ni  (rst_ni  ),
2299: 
2300:     // from register interface (qualified with register enable)
2301:     .we     (classc_ctrl_en_e2_we & regen_qs),
2302:     .wd     (classc_ctrl_en_e2_wd),
2303: 
2304:     // from internal hardware
2305:     .de     (1'b0),
2306:     .d      ('0  ),
2307: 
2308:     // to internal hardware
2309:     .qe     (),
2310:     .q      (reg2hw.classc_ctrl.en_e2.q ),
2311: 
2312:     // to register interface (read)
2313:     .qs     (classc_ctrl_en_e2_qs)
2314:   );
2315: 
2316: 
2317:   //   F[en_e3]: 5:5
2318:   prim_subreg #(
2319:     .DW      (1),
2320:     .SWACCESS("RW"),
2321:     .RESVAL  (1'h1)
2322:   ) u_classc_ctrl_en_e3 (
2323:     .clk_i   (clk_i    ),
2324:     .rst_ni  (rst_ni  ),
2325: 
2326:     // from register interface (qualified with register enable)
2327:     .we     (classc_ctrl_en_e3_we & regen_qs),
2328:     .wd     (classc_ctrl_en_e3_wd),
2329: 
2330:     // from internal hardware
2331:     .de     (1'b0),
2332:     .d      ('0  ),
2333: 
2334:     // to internal hardware
2335:     .qe     (),
2336:     .q      (reg2hw.classc_ctrl.en_e3.q ),
2337: 
2338:     // to register interface (read)
2339:     .qs     (classc_ctrl_en_e3_qs)
2340:   );
2341: 
2342: 
2343:   //   F[map_e0]: 7:6
2344:   prim_subreg #(
2345:     .DW      (2),
2346:     .SWACCESS("RW"),
2347:     .RESVAL  (2'h0)
2348:   ) u_classc_ctrl_map_e0 (
2349:     .clk_i   (clk_i    ),
2350:     .rst_ni  (rst_ni  ),
2351: 
2352:     // from register interface (qualified with register enable)
2353:     .we     (classc_ctrl_map_e0_we & regen_qs),
2354:     .wd     (classc_ctrl_map_e0_wd),
2355: 
2356:     // from internal hardware
2357:     .de     (1'b0),
2358:     .d      ('0  ),
2359: 
2360:     // to internal hardware
2361:     .qe     (),
2362:     .q      (reg2hw.classc_ctrl.map_e0.q ),
2363: 
2364:     // to register interface (read)
2365:     .qs     (classc_ctrl_map_e0_qs)
2366:   );
2367: 
2368: 
2369:   //   F[map_e1]: 9:8
2370:   prim_subreg #(
2371:     .DW      (2),
2372:     .SWACCESS("RW"),
2373:     .RESVAL  (2'h1)
2374:   ) u_classc_ctrl_map_e1 (
2375:     .clk_i   (clk_i    ),
2376:     .rst_ni  (rst_ni  ),
2377: 
2378:     // from register interface (qualified with register enable)
2379:     .we     (classc_ctrl_map_e1_we & regen_qs),
2380:     .wd     (classc_ctrl_map_e1_wd),
2381: 
2382:     // from internal hardware
2383:     .de     (1'b0),
2384:     .d      ('0  ),
2385: 
2386:     // to internal hardware
2387:     .qe     (),
2388:     .q      (reg2hw.classc_ctrl.map_e1.q ),
2389: 
2390:     // to register interface (read)
2391:     .qs     (classc_ctrl_map_e1_qs)
2392:   );
2393: 
2394: 
2395:   //   F[map_e2]: 11:10
2396:   prim_subreg #(
2397:     .DW      (2),
2398:     .SWACCESS("RW"),
2399:     .RESVAL  (2'h2)
2400:   ) u_classc_ctrl_map_e2 (
2401:     .clk_i   (clk_i    ),
2402:     .rst_ni  (rst_ni  ),
2403: 
2404:     // from register interface (qualified with register enable)
2405:     .we     (classc_ctrl_map_e2_we & regen_qs),
2406:     .wd     (classc_ctrl_map_e2_wd),
2407: 
2408:     // from internal hardware
2409:     .de     (1'b0),
2410:     .d      ('0  ),
2411: 
2412:     // to internal hardware
2413:     .qe     (),
2414:     .q      (reg2hw.classc_ctrl.map_e2.q ),
2415: 
2416:     // to register interface (read)
2417:     .qs     (classc_ctrl_map_e2_qs)
2418:   );
2419: 
2420: 
2421:   //   F[map_e3]: 13:12
2422:   prim_subreg #(
2423:     .DW      (2),
2424:     .SWACCESS("RW"),
2425:     .RESVAL  (2'h3)
2426:   ) u_classc_ctrl_map_e3 (
2427:     .clk_i   (clk_i    ),
2428:     .rst_ni  (rst_ni  ),
2429: 
2430:     // from register interface (qualified with register enable)
2431:     .we     (classc_ctrl_map_e3_we & regen_qs),
2432:     .wd     (classc_ctrl_map_e3_wd),
2433: 
2434:     // from internal hardware
2435:     .de     (1'b0),
2436:     .d      ('0  ),
2437: 
2438:     // to internal hardware
2439:     .qe     (),
2440:     .q      (reg2hw.classc_ctrl.map_e3.q ),
2441: 
2442:     // to register interface (read)
2443:     .qs     (classc_ctrl_map_e3_qs)
2444:   );
2445: 
2446: 
2447:   // R[classc_clren]: V(False)
2448: 
2449:   prim_subreg #(
2450:     .DW      (1),
2451:     .SWACCESS("W1C"),
2452:     .RESVAL  (1'h1)
2453:   ) u_classc_clren (
2454:     .clk_i   (clk_i    ),
2455:     .rst_ni  (rst_ni  ),
2456: 
2457:     // from register interface
2458:     .we     (classc_clren_we),
2459:     .wd     (classc_clren_wd),
2460: 
2461:     // from internal hardware
2462:     .de     (hw2reg.classc_clren.de),
2463:     .d      (hw2reg.classc_clren.d ),
2464: 
2465:     // to internal hardware
2466:     .qe     (),
2467:     .q      (),
2468: 
2469:     // to register interface (read)
2470:     .qs     (classc_clren_qs)
2471:   );
2472: 
2473: 
2474:   // R[classc_clr]: V(False)
2475: 
2476:   prim_subreg #(
2477:     .DW      (1),
2478:     .SWACCESS("WO"),
2479:     .RESVAL  (1'h0)
2480:   ) u_classc_clr (
2481:     .clk_i   (clk_i    ),
2482:     .rst_ni  (rst_ni  ),
2483: 
2484:     // from register interface (qualified with register enable)
2485:     .we     (classc_clr_we & classc_clren_qs),
2486:     .wd     (classc_clr_wd),
2487: 
2488:     // from internal hardware
2489:     .de     (1'b0),
2490:     .d      ('0  ),
2491: 
2492:     // to internal hardware
2493:     .qe     (reg2hw.classc_clr.qe),
2494:     .q      (reg2hw.classc_clr.q ),
2495: 
2496:     .qs     ()
2497:   );
2498: 
2499: 
2500:   // R[classc_accum_cnt]: V(True)
2501: 
2502:   prim_subreg_ext #(
2503:     .DW    (16)
2504:   ) u_classc_accum_cnt (
2505:     .re     (classc_accum_cnt_re),
2506:     .we     (1'b0),
2507:     .wd     ('0),
2508:     .d      (hw2reg.classc_accum_cnt.d),
2509:     .qre    (),
2510:     .qe     (),
2511:     .q      (),
2512:     .qs     (classc_accum_cnt_qs)
2513:   );
2514: 
2515: 
2516:   // R[classc_accum_thresh]: V(False)
2517: 
2518:   prim_subreg #(
2519:     .DW      (16),
2520:     .SWACCESS("RW"),
2521:     .RESVAL  (16'h0)
2522:   ) u_classc_accum_thresh (
2523:     .clk_i   (clk_i    ),
2524:     .rst_ni  (rst_ni  ),
2525: 
2526:     // from register interface (qualified with register enable)
2527:     .we     (classc_accum_thresh_we & regen_qs),
2528:     .wd     (classc_accum_thresh_wd),
2529: 
2530:     // from internal hardware
2531:     .de     (1'b0),
2532:     .d      ('0  ),
2533: 
2534:     // to internal hardware
2535:     .qe     (),
2536:     .q      (reg2hw.classc_accum_thresh.q ),
2537: 
2538:     // to register interface (read)
2539:     .qs     (classc_accum_thresh_qs)
2540:   );
2541: 
2542: 
2543:   // R[classc_timeout_cyc]: V(False)
2544: 
2545:   prim_subreg #(
2546:     .DW      (32),
2547:     .SWACCESS("RW"),
2548:     .RESVAL  (32'h0)
2549:   ) u_classc_timeout_cyc (
2550:     .clk_i   (clk_i    ),
2551:     .rst_ni  (rst_ni  ),
2552: 
2553:     // from register interface (qualified with register enable)
2554:     .we     (classc_timeout_cyc_we & regen_qs),
2555:     .wd     (classc_timeout_cyc_wd),
2556: 
2557:     // from internal hardware
2558:     .de     (1'b0),
2559:     .d      ('0  ),
2560: 
2561:     // to internal hardware
2562:     .qe     (),
2563:     .q      (reg2hw.classc_timeout_cyc.q ),
2564: 
2565:     // to register interface (read)
2566:     .qs     (classc_timeout_cyc_qs)
2567:   );
2568: 
2569: 
2570:   // R[classc_phase0_cyc]: V(False)
2571: 
2572:   prim_subreg #(
2573:     .DW      (32),
2574:     .SWACCESS("RW"),
2575:     .RESVAL  (32'h0)
2576:   ) u_classc_phase0_cyc (
2577:     .clk_i   (clk_i    ),
2578:     .rst_ni  (rst_ni  ),
2579: 
2580:     // from register interface (qualified with register enable)
2581:     .we     (classc_phase0_cyc_we & regen_qs),
2582:     .wd     (classc_phase0_cyc_wd),
2583: 
2584:     // from internal hardware
2585:     .de     (1'b0),
2586:     .d      ('0  ),
2587: 
2588:     // to internal hardware
2589:     .qe     (),
2590:     .q      (reg2hw.classc_phase0_cyc.q ),
2591: 
2592:     // to register interface (read)
2593:     .qs     (classc_phase0_cyc_qs)
2594:   );
2595: 
2596: 
2597:   // R[classc_phase1_cyc]: V(False)
2598: 
2599:   prim_subreg #(
2600:     .DW      (32),
2601:     .SWACCESS("RW"),
2602:     .RESVAL  (32'h0)
2603:   ) u_classc_phase1_cyc (
2604:     .clk_i   (clk_i    ),
2605:     .rst_ni  (rst_ni  ),
2606: 
2607:     // from register interface (qualified with register enable)
2608:     .we     (classc_phase1_cyc_we & regen_qs),
2609:     .wd     (classc_phase1_cyc_wd),
2610: 
2611:     // from internal hardware
2612:     .de     (1'b0),
2613:     .d      ('0  ),
2614: 
2615:     // to internal hardware
2616:     .qe     (),
2617:     .q      (reg2hw.classc_phase1_cyc.q ),
2618: 
2619:     // to register interface (read)
2620:     .qs     (classc_phase1_cyc_qs)
2621:   );
2622: 
2623: 
2624:   // R[classc_phase2_cyc]: V(False)
2625: 
2626:   prim_subreg #(
2627:     .DW      (32),
2628:     .SWACCESS("RW"),
2629:     .RESVAL  (32'h0)
2630:   ) u_classc_phase2_cyc (
2631:     .clk_i   (clk_i    ),
2632:     .rst_ni  (rst_ni  ),
2633: 
2634:     // from register interface (qualified with register enable)
2635:     .we     (classc_phase2_cyc_we & regen_qs),
2636:     .wd     (classc_phase2_cyc_wd),
2637: 
2638:     // from internal hardware
2639:     .de     (1'b0),
2640:     .d      ('0  ),
2641: 
2642:     // to internal hardware
2643:     .qe     (),
2644:     .q      (reg2hw.classc_phase2_cyc.q ),
2645: 
2646:     // to register interface (read)
2647:     .qs     (classc_phase2_cyc_qs)
2648:   );
2649: 
2650: 
2651:   // R[classc_phase3_cyc]: V(False)
2652: 
2653:   prim_subreg #(
2654:     .DW      (32),
2655:     .SWACCESS("RW"),
2656:     .RESVAL  (32'h0)
2657:   ) u_classc_phase3_cyc (
2658:     .clk_i   (clk_i    ),
2659:     .rst_ni  (rst_ni  ),
2660: 
2661:     // from register interface (qualified with register enable)
2662:     .we     (classc_phase3_cyc_we & regen_qs),
2663:     .wd     (classc_phase3_cyc_wd),
2664: 
2665:     // from internal hardware
2666:     .de     (1'b0),
2667:     .d      ('0  ),
2668: 
2669:     // to internal hardware
2670:     .qe     (),
2671:     .q      (reg2hw.classc_phase3_cyc.q ),
2672: 
2673:     // to register interface (read)
2674:     .qs     (classc_phase3_cyc_qs)
2675:   );
2676: 
2677: 
2678:   // R[classc_esc_cnt]: V(True)
2679: 
2680:   prim_subreg_ext #(
2681:     .DW    (32)
2682:   ) u_classc_esc_cnt (
2683:     .re     (classc_esc_cnt_re),
2684:     .we     (1'b0),
2685:     .wd     ('0),
2686:     .d      (hw2reg.classc_esc_cnt.d),
2687:     .qre    (),
2688:     .qe     (),
2689:     .q      (),
2690:     .qs     (classc_esc_cnt_qs)
2691:   );
2692: 
2693: 
2694:   // R[classc_state]: V(True)
2695: 
2696:   prim_subreg_ext #(
2697:     .DW    (3)
2698:   ) u_classc_state (
2699:     .re     (classc_state_re),
2700:     .we     (1'b0),
2701:     .wd     ('0),
2702:     .d      (hw2reg.classc_state.d),
2703:     .qre    (),
2704:     .qe     (),
2705:     .q      (),
2706:     .qs     (classc_state_qs)
2707:   );
2708: 
2709: 
2710:   // R[classd_ctrl]: V(False)
2711: 
2712:   //   F[en]: 0:0
2713:   prim_subreg #(
2714:     .DW      (1),
2715:     .SWACCESS("RW"),
2716:     .RESVAL  (1'h0)
2717:   ) u_classd_ctrl_en (
2718:     .clk_i   (clk_i    ),
2719:     .rst_ni  (rst_ni  ),
2720: 
2721:     // from register interface (qualified with register enable)
2722:     .we     (classd_ctrl_en_we & regen_qs),
2723:     .wd     (classd_ctrl_en_wd),
2724: 
2725:     // from internal hardware
2726:     .de     (1'b0),
2727:     .d      ('0  ),
2728: 
2729:     // to internal hardware
2730:     .qe     (),
2731:     .q      (reg2hw.classd_ctrl.en.q ),
2732: 
2733:     // to register interface (read)
2734:     .qs     (classd_ctrl_en_qs)
2735:   );
2736: 
2737: 
2738:   //   F[lock]: 1:1
2739:   prim_subreg #(
2740:     .DW      (1),
2741:     .SWACCESS("RW"),
2742:     .RESVAL  (1'h0)
2743:   ) u_classd_ctrl_lock (
2744:     .clk_i   (clk_i    ),
2745:     .rst_ni  (rst_ni  ),
2746: 
2747:     // from register interface (qualified with register enable)
2748:     .we     (classd_ctrl_lock_we & regen_qs),
2749:     .wd     (classd_ctrl_lock_wd),
2750: 
2751:     // from internal hardware
2752:     .de     (1'b0),
2753:     .d      ('0  ),
2754: 
2755:     // to internal hardware
2756:     .qe     (),
2757:     .q      (reg2hw.classd_ctrl.lock.q ),
2758: 
2759:     // to register interface (read)
2760:     .qs     (classd_ctrl_lock_qs)
2761:   );
2762: 
2763: 
2764:   //   F[en_e0]: 2:2
2765:   prim_subreg #(
2766:     .DW      (1),
2767:     .SWACCESS("RW"),
2768:     .RESVAL  (1'h1)
2769:   ) u_classd_ctrl_en_e0 (
2770:     .clk_i   (clk_i    ),
2771:     .rst_ni  (rst_ni  ),
2772: 
2773:     // from register interface (qualified with register enable)
2774:     .we     (classd_ctrl_en_e0_we & regen_qs),
2775:     .wd     (classd_ctrl_en_e0_wd),
2776: 
2777:     // from internal hardware
2778:     .de     (1'b0),
2779:     .d      ('0  ),
2780: 
2781:     // to internal hardware
2782:     .qe     (),
2783:     .q      (reg2hw.classd_ctrl.en_e0.q ),
2784: 
2785:     // to register interface (read)
2786:     .qs     (classd_ctrl_en_e0_qs)
2787:   );
2788: 
2789: 
2790:   //   F[en_e1]: 3:3
2791:   prim_subreg #(
2792:     .DW      (1),
2793:     .SWACCESS("RW"),
2794:     .RESVAL  (1'h1)
2795:   ) u_classd_ctrl_en_e1 (
2796:     .clk_i   (clk_i    ),
2797:     .rst_ni  (rst_ni  ),
2798: 
2799:     // from register interface (qualified with register enable)
2800:     .we     (classd_ctrl_en_e1_we & regen_qs),
2801:     .wd     (classd_ctrl_en_e1_wd),
2802: 
2803:     // from internal hardware
2804:     .de     (1'b0),
2805:     .d      ('0  ),
2806: 
2807:     // to internal hardware
2808:     .qe     (),
2809:     .q      (reg2hw.classd_ctrl.en_e1.q ),
2810: 
2811:     // to register interface (read)
2812:     .qs     (classd_ctrl_en_e1_qs)
2813:   );
2814: 
2815: 
2816:   //   F[en_e2]: 4:4
2817:   prim_subreg #(
2818:     .DW      (1),
2819:     .SWACCESS("RW"),
2820:     .RESVAL  (1'h1)
2821:   ) u_classd_ctrl_en_e2 (
2822:     .clk_i   (clk_i    ),
2823:     .rst_ni  (rst_ni  ),
2824: 
2825:     // from register interface (qualified with register enable)
2826:     .we     (classd_ctrl_en_e2_we & regen_qs),
2827:     .wd     (classd_ctrl_en_e2_wd),
2828: 
2829:     // from internal hardware
2830:     .de     (1'b0),
2831:     .d      ('0  ),
2832: 
2833:     // to internal hardware
2834:     .qe     (),
2835:     .q      (reg2hw.classd_ctrl.en_e2.q ),
2836: 
2837:     // to register interface (read)
2838:     .qs     (classd_ctrl_en_e2_qs)
2839:   );
2840: 
2841: 
2842:   //   F[en_e3]: 5:5
2843:   prim_subreg #(
2844:     .DW      (1),
2845:     .SWACCESS("RW"),
2846:     .RESVAL  (1'h1)
2847:   ) u_classd_ctrl_en_e3 (
2848:     .clk_i   (clk_i    ),
2849:     .rst_ni  (rst_ni  ),
2850: 
2851:     // from register interface (qualified with register enable)
2852:     .we     (classd_ctrl_en_e3_we & regen_qs),
2853:     .wd     (classd_ctrl_en_e3_wd),
2854: 
2855:     // from internal hardware
2856:     .de     (1'b0),
2857:     .d      ('0  ),
2858: 
2859:     // to internal hardware
2860:     .qe     (),
2861:     .q      (reg2hw.classd_ctrl.en_e3.q ),
2862: 
2863:     // to register interface (read)
2864:     .qs     (classd_ctrl_en_e3_qs)
2865:   );
2866: 
2867: 
2868:   //   F[map_e0]: 7:6
2869:   prim_subreg #(
2870:     .DW      (2),
2871:     .SWACCESS("RW"),
2872:     .RESVAL  (2'h0)
2873:   ) u_classd_ctrl_map_e0 (
2874:     .clk_i   (clk_i    ),
2875:     .rst_ni  (rst_ni  ),
2876: 
2877:     // from register interface (qualified with register enable)
2878:     .we     (classd_ctrl_map_e0_we & regen_qs),
2879:     .wd     (classd_ctrl_map_e0_wd),
2880: 
2881:     // from internal hardware
2882:     .de     (1'b0),
2883:     .d      ('0  ),
2884: 
2885:     // to internal hardware
2886:     .qe     (),
2887:     .q      (reg2hw.classd_ctrl.map_e0.q ),
2888: 
2889:     // to register interface (read)
2890:     .qs     (classd_ctrl_map_e0_qs)
2891:   );
2892: 
2893: 
2894:   //   F[map_e1]: 9:8
2895:   prim_subreg #(
2896:     .DW      (2),
2897:     .SWACCESS("RW"),
2898:     .RESVAL  (2'h1)
2899:   ) u_classd_ctrl_map_e1 (
2900:     .clk_i   (clk_i    ),
2901:     .rst_ni  (rst_ni  ),
2902: 
2903:     // from register interface (qualified with register enable)
2904:     .we     (classd_ctrl_map_e1_we & regen_qs),
2905:     .wd     (classd_ctrl_map_e1_wd),
2906: 
2907:     // from internal hardware
2908:     .de     (1'b0),
2909:     .d      ('0  ),
2910: 
2911:     // to internal hardware
2912:     .qe     (),
2913:     .q      (reg2hw.classd_ctrl.map_e1.q ),
2914: 
2915:     // to register interface (read)
2916:     .qs     (classd_ctrl_map_e1_qs)
2917:   );
2918: 
2919: 
2920:   //   F[map_e2]: 11:10
2921:   prim_subreg #(
2922:     .DW      (2),
2923:     .SWACCESS("RW"),
2924:     .RESVAL  (2'h2)
2925:   ) u_classd_ctrl_map_e2 (
2926:     .clk_i   (clk_i    ),
2927:     .rst_ni  (rst_ni  ),
2928: 
2929:     // from register interface (qualified with register enable)
2930:     .we     (classd_ctrl_map_e2_we & regen_qs),
2931:     .wd     (classd_ctrl_map_e2_wd),
2932: 
2933:     // from internal hardware
2934:     .de     (1'b0),
2935:     .d      ('0  ),
2936: 
2937:     // to internal hardware
2938:     .qe     (),
2939:     .q      (reg2hw.classd_ctrl.map_e2.q ),
2940: 
2941:     // to register interface (read)
2942:     .qs     (classd_ctrl_map_e2_qs)
2943:   );
2944: 
2945: 
2946:   //   F[map_e3]: 13:12
2947:   prim_subreg #(
2948:     .DW      (2),
2949:     .SWACCESS("RW"),
2950:     .RESVAL  (2'h3)
2951:   ) u_classd_ctrl_map_e3 (
2952:     .clk_i   (clk_i    ),
2953:     .rst_ni  (rst_ni  ),
2954: 
2955:     // from register interface (qualified with register enable)
2956:     .we     (classd_ctrl_map_e3_we & regen_qs),
2957:     .wd     (classd_ctrl_map_e3_wd),
2958: 
2959:     // from internal hardware
2960:     .de     (1'b0),
2961:     .d      ('0  ),
2962: 
2963:     // to internal hardware
2964:     .qe     (),
2965:     .q      (reg2hw.classd_ctrl.map_e3.q ),
2966: 
2967:     // to register interface (read)
2968:     .qs     (classd_ctrl_map_e3_qs)
2969:   );
2970: 
2971: 
2972:   // R[classd_clren]: V(False)
2973: 
2974:   prim_subreg #(
2975:     .DW      (1),
2976:     .SWACCESS("W1C"),
2977:     .RESVAL  (1'h1)
2978:   ) u_classd_clren (
2979:     .clk_i   (clk_i    ),
2980:     .rst_ni  (rst_ni  ),
2981: 
2982:     // from register interface
2983:     .we     (classd_clren_we),
2984:     .wd     (classd_clren_wd),
2985: 
2986:     // from internal hardware
2987:     .de     (hw2reg.classd_clren.de),
2988:     .d      (hw2reg.classd_clren.d ),
2989: 
2990:     // to internal hardware
2991:     .qe     (),
2992:     .q      (),
2993: 
2994:     // to register interface (read)
2995:     .qs     (classd_clren_qs)
2996:   );
2997: 
2998: 
2999:   // R[classd_clr]: V(False)
3000: 
3001:   prim_subreg #(
3002:     .DW      (1),
3003:     .SWACCESS("WO"),
3004:     .RESVAL  (1'h0)
3005:   ) u_classd_clr (
3006:     .clk_i   (clk_i    ),
3007:     .rst_ni  (rst_ni  ),
3008: 
3009:     // from register interface (qualified with register enable)
3010:     .we     (classd_clr_we & classd_clren_qs),
3011:     .wd     (classd_clr_wd),
3012: 
3013:     // from internal hardware
3014:     .de     (1'b0),
3015:     .d      ('0  ),
3016: 
3017:     // to internal hardware
3018:     .qe     (reg2hw.classd_clr.qe),
3019:     .q      (reg2hw.classd_clr.q ),
3020: 
3021:     .qs     ()
3022:   );
3023: 
3024: 
3025:   // R[classd_accum_cnt]: V(True)
3026: 
3027:   prim_subreg_ext #(
3028:     .DW    (16)
3029:   ) u_classd_accum_cnt (
3030:     .re     (classd_accum_cnt_re),
3031:     .we     (1'b0),
3032:     .wd     ('0),
3033:     .d      (hw2reg.classd_accum_cnt.d),
3034:     .qre    (),
3035:     .qe     (),
3036:     .q      (),
3037:     .qs     (classd_accum_cnt_qs)
3038:   );
3039: 
3040: 
3041:   // R[classd_accum_thresh]: V(False)
3042: 
3043:   prim_subreg #(
3044:     .DW      (16),
3045:     .SWACCESS("RW"),
3046:     .RESVAL  (16'h0)
3047:   ) u_classd_accum_thresh (
3048:     .clk_i   (clk_i    ),
3049:     .rst_ni  (rst_ni  ),
3050: 
3051:     // from register interface (qualified with register enable)
3052:     .we     (classd_accum_thresh_we & regen_qs),
3053:     .wd     (classd_accum_thresh_wd),
3054: 
3055:     // from internal hardware
3056:     .de     (1'b0),
3057:     .d      ('0  ),
3058: 
3059:     // to internal hardware
3060:     .qe     (),
3061:     .q      (reg2hw.classd_accum_thresh.q ),
3062: 
3063:     // to register interface (read)
3064:     .qs     (classd_accum_thresh_qs)
3065:   );
3066: 
3067: 
3068:   // R[classd_timeout_cyc]: V(False)
3069: 
3070:   prim_subreg #(
3071:     .DW      (32),
3072:     .SWACCESS("RW"),
3073:     .RESVAL  (32'h0)
3074:   ) u_classd_timeout_cyc (
3075:     .clk_i   (clk_i    ),
3076:     .rst_ni  (rst_ni  ),
3077: 
3078:     // from register interface (qualified with register enable)
3079:     .we     (classd_timeout_cyc_we & regen_qs),
3080:     .wd     (classd_timeout_cyc_wd),
3081: 
3082:     // from internal hardware
3083:     .de     (1'b0),
3084:     .d      ('0  ),
3085: 
3086:     // to internal hardware
3087:     .qe     (),
3088:     .q      (reg2hw.classd_timeout_cyc.q ),
3089: 
3090:     // to register interface (read)
3091:     .qs     (classd_timeout_cyc_qs)
3092:   );
3093: 
3094: 
3095:   // R[classd_phase0_cyc]: V(False)
3096: 
3097:   prim_subreg #(
3098:     .DW      (32),
3099:     .SWACCESS("RW"),
3100:     .RESVAL  (32'h0)
3101:   ) u_classd_phase0_cyc (
3102:     .clk_i   (clk_i    ),
3103:     .rst_ni  (rst_ni  ),
3104: 
3105:     // from register interface (qualified with register enable)
3106:     .we     (classd_phase0_cyc_we & regen_qs),
3107:     .wd     (classd_phase0_cyc_wd),
3108: 
3109:     // from internal hardware
3110:     .de     (1'b0),
3111:     .d      ('0  ),
3112: 
3113:     // to internal hardware
3114:     .qe     (),
3115:     .q      (reg2hw.classd_phase0_cyc.q ),
3116: 
3117:     // to register interface (read)
3118:     .qs     (classd_phase0_cyc_qs)
3119:   );
3120: 
3121: 
3122:   // R[classd_phase1_cyc]: V(False)
3123: 
3124:   prim_subreg #(
3125:     .DW      (32),
3126:     .SWACCESS("RW"),
3127:     .RESVAL  (32'h0)
3128:   ) u_classd_phase1_cyc (
3129:     .clk_i   (clk_i    ),
3130:     .rst_ni  (rst_ni  ),
3131: 
3132:     // from register interface (qualified with register enable)
3133:     .we     (classd_phase1_cyc_we & regen_qs),
3134:     .wd     (classd_phase1_cyc_wd),
3135: 
3136:     // from internal hardware
3137:     .de     (1'b0),
3138:     .d      ('0  ),
3139: 
3140:     // to internal hardware
3141:     .qe     (),
3142:     .q      (reg2hw.classd_phase1_cyc.q ),
3143: 
3144:     // to register interface (read)
3145:     .qs     (classd_phase1_cyc_qs)
3146:   );
3147: 
3148: 
3149:   // R[classd_phase2_cyc]: V(False)
3150: 
3151:   prim_subreg #(
3152:     .DW      (32),
3153:     .SWACCESS("RW"),
3154:     .RESVAL  (32'h0)
3155:   ) u_classd_phase2_cyc (
3156:     .clk_i   (clk_i    ),
3157:     .rst_ni  (rst_ni  ),
3158: 
3159:     // from register interface (qualified with register enable)
3160:     .we     (classd_phase2_cyc_we & regen_qs),
3161:     .wd     (classd_phase2_cyc_wd),
3162: 
3163:     // from internal hardware
3164:     .de     (1'b0),
3165:     .d      ('0  ),
3166: 
3167:     // to internal hardware
3168:     .qe     (),
3169:     .q      (reg2hw.classd_phase2_cyc.q ),
3170: 
3171:     // to register interface (read)
3172:     .qs     (classd_phase2_cyc_qs)
3173:   );
3174: 
3175: 
3176:   // R[classd_phase3_cyc]: V(False)
3177: 
3178:   prim_subreg #(
3179:     .DW      (32),
3180:     .SWACCESS("RW"),
3181:     .RESVAL  (32'h0)
3182:   ) u_classd_phase3_cyc (
3183:     .clk_i   (clk_i    ),
3184:     .rst_ni  (rst_ni  ),
3185: 
3186:     // from register interface (qualified with register enable)
3187:     .we     (classd_phase3_cyc_we & regen_qs),
3188:     .wd     (classd_phase3_cyc_wd),
3189: 
3190:     // from internal hardware
3191:     .de     (1'b0),
3192:     .d      ('0  ),
3193: 
3194:     // to internal hardware
3195:     .qe     (),
3196:     .q      (reg2hw.classd_phase3_cyc.q ),
3197: 
3198:     // to register interface (read)
3199:     .qs     (classd_phase3_cyc_qs)
3200:   );
3201: 
3202: 
3203:   // R[classd_esc_cnt]: V(True)
3204: 
3205:   prim_subreg_ext #(
3206:     .DW    (32)
3207:   ) u_classd_esc_cnt (
3208:     .re     (classd_esc_cnt_re),
3209:     .we     (1'b0),
3210:     .wd     ('0),
3211:     .d      (hw2reg.classd_esc_cnt.d),
3212:     .qre    (),
3213:     .qe     (),
3214:     .q      (),
3215:     .qs     (classd_esc_cnt_qs)
3216:   );
3217: 
3218: 
3219:   // R[classd_state]: V(True)
3220: 
3221:   prim_subreg_ext #(
3222:     .DW    (3)
3223:   ) u_classd_state (
3224:     .re     (classd_state_re),
3225:     .we     (1'b0),
3226:     .wd     ('0),
3227:     .d      (hw2reg.classd_state.d),
3228:     .qre    (),
3229:     .qe     (),
3230:     .q      (),
3231:     .qs     (classd_state_qs)
3232:   );
3233: 
3234: 
3235: 
3236: 
3237:   logic [58:0] addr_hit;
3238:   always_comb begin
3239:     addr_hit = '0;
3240:     addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
3241:     addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET);
3242:     addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET);
3243:     addr_hit[ 3] = (reg_addr == ALERT_HANDLER_REGEN_OFFSET);
3244:     addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET);
3245:     addr_hit[ 5] = (reg_addr == ALERT_HANDLER_ALERT_EN_OFFSET);
3246:     addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_OFFSET);
3247:     addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_OFFSET);
3248:     addr_hit[ 8] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_OFFSET);
3249:     addr_hit[ 9] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET);
3250:     addr_hit[10] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET);
3251:     addr_hit[11] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
3252:     addr_hit[12] = (reg_addr == ALERT_HANDLER_CLASSA_CLREN_OFFSET);
3253:     addr_hit[13] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
3254:     addr_hit[14] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
3255:     addr_hit[15] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
3256:     addr_hit[16] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
3257:     addr_hit[17] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
3258:     addr_hit[18] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
3259:     addr_hit[19] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
3260:     addr_hit[20] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
3261:     addr_hit[21] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
3262:     addr_hit[22] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
3263:     addr_hit[23] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
3264:     addr_hit[24] = (reg_addr == ALERT_HANDLER_CLASSB_CLREN_OFFSET);
3265:     addr_hit[25] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
3266:     addr_hit[26] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
3267:     addr_hit[27] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
3268:     addr_hit[28] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
3269:     addr_hit[29] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
3270:     addr_hit[30] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
3271:     addr_hit[31] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
3272:     addr_hit[32] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
3273:     addr_hit[33] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
3274:     addr_hit[34] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
3275:     addr_hit[35] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
3276:     addr_hit[36] = (reg_addr == ALERT_HANDLER_CLASSC_CLREN_OFFSET);
3277:     addr_hit[37] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
3278:     addr_hit[38] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
3279:     addr_hit[39] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
3280:     addr_hit[40] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
3281:     addr_hit[41] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
3282:     addr_hit[42] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
3283:     addr_hit[43] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
3284:     addr_hit[44] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
3285:     addr_hit[45] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
3286:     addr_hit[46] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
3287:     addr_hit[47] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
3288:     addr_hit[48] = (reg_addr == ALERT_HANDLER_CLASSD_CLREN_OFFSET);
3289:     addr_hit[49] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
3290:     addr_hit[50] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
3291:     addr_hit[51] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
3292:     addr_hit[52] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
3293:     addr_hit[53] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
3294:     addr_hit[54] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
3295:     addr_hit[55] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
3296:     addr_hit[56] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
3297:     addr_hit[57] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
3298:     addr_hit[58] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
3299:   end
3300: 
3301:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
3302: 
3303:   // Check sub-word write is permitted
3304:   always_comb begin
3305:     wr_err = 1'b0;
3306:     if (addr_hit[ 0] && reg_we && (ALERT_HANDLER_PERMIT[ 0] != (ALERT_HANDLER_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
3307:     if (addr_hit[ 1] && reg_we && (ALERT_HANDLER_PERMIT[ 1] != (ALERT_HANDLER_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
3308:     if (addr_hit[ 2] && reg_we && (ALERT_HANDLER_PERMIT[ 2] != (ALERT_HANDLER_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
3309:     if (addr_hit[ 3] && reg_we && (ALERT_HANDLER_PERMIT[ 3] != (ALERT_HANDLER_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
3310:     if (addr_hit[ 4] && reg_we && (ALERT_HANDLER_PERMIT[ 4] != (ALERT_HANDLER_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
3311:     if (addr_hit[ 5] && reg_we && (ALERT_HANDLER_PERMIT[ 5] != (ALERT_HANDLER_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
3312:     if (addr_hit[ 6] && reg_we && (ALERT_HANDLER_PERMIT[ 6] != (ALERT_HANDLER_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
3313:     if (addr_hit[ 7] && reg_we && (ALERT_HANDLER_PERMIT[ 7] != (ALERT_HANDLER_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
3314:     if (addr_hit[ 8] && reg_we && (ALERT_HANDLER_PERMIT[ 8] != (ALERT_HANDLER_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
3315:     if (addr_hit[ 9] && reg_we && (ALERT_HANDLER_PERMIT[ 9] != (ALERT_HANDLER_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
3316:     if (addr_hit[10] && reg_we && (ALERT_HANDLER_PERMIT[10] != (ALERT_HANDLER_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
3317:     if (addr_hit[11] && reg_we && (ALERT_HANDLER_PERMIT[11] != (ALERT_HANDLER_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
3318:     if (addr_hit[12] && reg_we && (ALERT_HANDLER_PERMIT[12] != (ALERT_HANDLER_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
3319:     if (addr_hit[13] && reg_we && (ALERT_HANDLER_PERMIT[13] != (ALERT_HANDLER_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
3320:     if (addr_hit[14] && reg_we && (ALERT_HANDLER_PERMIT[14] != (ALERT_HANDLER_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
3321:     if (addr_hit[15] && reg_we && (ALERT_HANDLER_PERMIT[15] != (ALERT_HANDLER_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
3322:     if (addr_hit[16] && reg_we && (ALERT_HANDLER_PERMIT[16] != (ALERT_HANDLER_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
3323:     if (addr_hit[17] && reg_we && (ALERT_HANDLER_PERMIT[17] != (ALERT_HANDLER_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
3324:     if (addr_hit[18] && reg_we && (ALERT_HANDLER_PERMIT[18] != (ALERT_HANDLER_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
3325:     if (addr_hit[19] && reg_we && (ALERT_HANDLER_PERMIT[19] != (ALERT_HANDLER_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
3326:     if (addr_hit[20] && reg_we && (ALERT_HANDLER_PERMIT[20] != (ALERT_HANDLER_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
3327:     if (addr_hit[21] && reg_we && (ALERT_HANDLER_PERMIT[21] != (ALERT_HANDLER_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
3328:     if (addr_hit[22] && reg_we && (ALERT_HANDLER_PERMIT[22] != (ALERT_HANDLER_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
3329:     if (addr_hit[23] && reg_we && (ALERT_HANDLER_PERMIT[23] != (ALERT_HANDLER_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
3330:     if (addr_hit[24] && reg_we && (ALERT_HANDLER_PERMIT[24] != (ALERT_HANDLER_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
3331:     if (addr_hit[25] && reg_we && (ALERT_HANDLER_PERMIT[25] != (ALERT_HANDLER_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
3332:     if (addr_hit[26] && reg_we && (ALERT_HANDLER_PERMIT[26] != (ALERT_HANDLER_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
3333:     if (addr_hit[27] && reg_we && (ALERT_HANDLER_PERMIT[27] != (ALERT_HANDLER_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
3334:     if (addr_hit[28] && reg_we && (ALERT_HANDLER_PERMIT[28] != (ALERT_HANDLER_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
3335:     if (addr_hit[29] && reg_we && (ALERT_HANDLER_PERMIT[29] != (ALERT_HANDLER_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
3336:     if (addr_hit[30] && reg_we && (ALERT_HANDLER_PERMIT[30] != (ALERT_HANDLER_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
3337:     if (addr_hit[31] && reg_we && (ALERT_HANDLER_PERMIT[31] != (ALERT_HANDLER_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
3338:     if (addr_hit[32] && reg_we && (ALERT_HANDLER_PERMIT[32] != (ALERT_HANDLER_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
3339:     if (addr_hit[33] && reg_we && (ALERT_HANDLER_PERMIT[33] != (ALERT_HANDLER_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
3340:     if (addr_hit[34] && reg_we && (ALERT_HANDLER_PERMIT[34] != (ALERT_HANDLER_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
3341:     if (addr_hit[35] && reg_we && (ALERT_HANDLER_PERMIT[35] != (ALERT_HANDLER_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
3342:     if (addr_hit[36] && reg_we && (ALERT_HANDLER_PERMIT[36] != (ALERT_HANDLER_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
3343:     if (addr_hit[37] && reg_we && (ALERT_HANDLER_PERMIT[37] != (ALERT_HANDLER_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
3344:     if (addr_hit[38] && reg_we && (ALERT_HANDLER_PERMIT[38] != (ALERT_HANDLER_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
3345:     if (addr_hit[39] && reg_we && (ALERT_HANDLER_PERMIT[39] != (ALERT_HANDLER_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
3346:     if (addr_hit[40] && reg_we && (ALERT_HANDLER_PERMIT[40] != (ALERT_HANDLER_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
3347:     if (addr_hit[41] && reg_we && (ALERT_HANDLER_PERMIT[41] != (ALERT_HANDLER_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
3348:     if (addr_hit[42] && reg_we && (ALERT_HANDLER_PERMIT[42] != (ALERT_HANDLER_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
3349:     if (addr_hit[43] && reg_we && (ALERT_HANDLER_PERMIT[43] != (ALERT_HANDLER_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
3350:     if (addr_hit[44] && reg_we && (ALERT_HANDLER_PERMIT[44] != (ALERT_HANDLER_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
3351:     if (addr_hit[45] && reg_we && (ALERT_HANDLER_PERMIT[45] != (ALERT_HANDLER_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
3352:     if (addr_hit[46] && reg_we && (ALERT_HANDLER_PERMIT[46] != (ALERT_HANDLER_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
3353:     if (addr_hit[47] && reg_we && (ALERT_HANDLER_PERMIT[47] != (ALERT_HANDLER_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
3354:     if (addr_hit[48] && reg_we && (ALERT_HANDLER_PERMIT[48] != (ALERT_HANDLER_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
3355:     if (addr_hit[49] && reg_we && (ALERT_HANDLER_PERMIT[49] != (ALERT_HANDLER_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
3356:     if (addr_hit[50] && reg_we && (ALERT_HANDLER_PERMIT[50] != (ALERT_HANDLER_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
3357:     if (addr_hit[51] && reg_we && (ALERT_HANDLER_PERMIT[51] != (ALERT_HANDLER_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
3358:     if (addr_hit[52] && reg_we && (ALERT_HANDLER_PERMIT[52] != (ALERT_HANDLER_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
3359:     if (addr_hit[53] && reg_we && (ALERT_HANDLER_PERMIT[53] != (ALERT_HANDLER_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
3360:     if (addr_hit[54] && reg_we && (ALERT_HANDLER_PERMIT[54] != (ALERT_HANDLER_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
3361:     if (addr_hit[55] && reg_we && (ALERT_HANDLER_PERMIT[55] != (ALERT_HANDLER_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
3362:     if (addr_hit[56] && reg_we && (ALERT_HANDLER_PERMIT[56] != (ALERT_HANDLER_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
3363:     if (addr_hit[57] && reg_we && (ALERT_HANDLER_PERMIT[57] != (ALERT_HANDLER_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
3364:     if (addr_hit[58] && reg_we && (ALERT_HANDLER_PERMIT[58] != (ALERT_HANDLER_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
3365:   end
3366: 
3367:   assign intr_state_classa_we = addr_hit[0] & reg_we & ~wr_err;
3368:   assign intr_state_classa_wd = reg_wdata[0];
3369: 
3370:   assign intr_state_classb_we = addr_hit[0] & reg_we & ~wr_err;
3371:   assign intr_state_classb_wd = reg_wdata[1];
3372: 
3373:   assign intr_state_classc_we = addr_hit[0] & reg_we & ~wr_err;
3374:   assign intr_state_classc_wd = reg_wdata[2];
3375: 
3376:   assign intr_state_classd_we = addr_hit[0] & reg_we & ~wr_err;
3377:   assign intr_state_classd_wd = reg_wdata[3];
3378: 
3379:   assign intr_enable_classa_we = addr_hit[1] & reg_we & ~wr_err;
3380:   assign intr_enable_classa_wd = reg_wdata[0];
3381: 
3382:   assign intr_enable_classb_we = addr_hit[1] & reg_we & ~wr_err;
3383:   assign intr_enable_classb_wd = reg_wdata[1];
3384: 
3385:   assign intr_enable_classc_we = addr_hit[1] & reg_we & ~wr_err;
3386:   assign intr_enable_classc_wd = reg_wdata[2];
3387: 
3388:   assign intr_enable_classd_we = addr_hit[1] & reg_we & ~wr_err;
3389:   assign intr_enable_classd_wd = reg_wdata[3];
3390: 
3391:   assign intr_test_classa_we = addr_hit[2] & reg_we & ~wr_err;
3392:   assign intr_test_classa_wd = reg_wdata[0];
3393: 
3394:   assign intr_test_classb_we = addr_hit[2] & reg_we & ~wr_err;
3395:   assign intr_test_classb_wd = reg_wdata[1];
3396: 
3397:   assign intr_test_classc_we = addr_hit[2] & reg_we & ~wr_err;
3398:   assign intr_test_classc_wd = reg_wdata[2];
3399: 
3400:   assign intr_test_classd_we = addr_hit[2] & reg_we & ~wr_err;
3401:   assign intr_test_classd_wd = reg_wdata[3];
3402: 
3403:   assign regen_we = addr_hit[3] & reg_we & ~wr_err;
3404:   assign regen_wd = reg_wdata[0];
3405: 
3406:   assign ping_timeout_cyc_we = addr_hit[4] & reg_we & ~wr_err;
3407:   assign ping_timeout_cyc_wd = reg_wdata[23:0];
3408: 
3409:   assign alert_en_we = addr_hit[5] & reg_we & ~wr_err;
3410:   assign alert_en_wd = reg_wdata[0];
3411: 
3412:   assign alert_class_we = addr_hit[6] & reg_we & ~wr_err;
3413:   assign alert_class_wd = reg_wdata[1:0];
3414: 
3415:   assign alert_cause_we = addr_hit[7] & reg_we & ~wr_err;
3416:   assign alert_cause_wd = reg_wdata[0];
3417: 
3418:   assign loc_alert_en_en_la0_we = addr_hit[8] & reg_we & ~wr_err;
3419:   assign loc_alert_en_en_la0_wd = reg_wdata[0];
3420: 
3421:   assign loc_alert_en_en_la1_we = addr_hit[8] & reg_we & ~wr_err;
3422:   assign loc_alert_en_en_la1_wd = reg_wdata[1];
3423: 
3424:   assign loc_alert_en_en_la2_we = addr_hit[8] & reg_we & ~wr_err;
3425:   assign loc_alert_en_en_la2_wd = reg_wdata[2];
3426: 
3427:   assign loc_alert_en_en_la3_we = addr_hit[8] & reg_we & ~wr_err;
3428:   assign loc_alert_en_en_la3_wd = reg_wdata[3];
3429: 
3430:   assign loc_alert_class_class_la0_we = addr_hit[9] & reg_we & ~wr_err;
3431:   assign loc_alert_class_class_la0_wd = reg_wdata[1:0];
3432: 
3433:   assign loc_alert_class_class_la1_we = addr_hit[9] & reg_we & ~wr_err;
3434:   assign loc_alert_class_class_la1_wd = reg_wdata[3:2];
3435: 
3436:   assign loc_alert_class_class_la2_we = addr_hit[9] & reg_we & ~wr_err;
3437:   assign loc_alert_class_class_la2_wd = reg_wdata[5:4];
3438: 
3439:   assign loc_alert_class_class_la3_we = addr_hit[9] & reg_we & ~wr_err;
3440:   assign loc_alert_class_class_la3_wd = reg_wdata[7:6];
3441: 
3442:   assign loc_alert_cause_la0_we = addr_hit[10] & reg_we & ~wr_err;
3443:   assign loc_alert_cause_la0_wd = reg_wdata[0];
3444: 
3445:   assign loc_alert_cause_la1_we = addr_hit[10] & reg_we & ~wr_err;
3446:   assign loc_alert_cause_la1_wd = reg_wdata[1];
3447: 
3448:   assign loc_alert_cause_la2_we = addr_hit[10] & reg_we & ~wr_err;
3449:   assign loc_alert_cause_la2_wd = reg_wdata[2];
3450: 
3451:   assign loc_alert_cause_la3_we = addr_hit[10] & reg_we & ~wr_err;
3452:   assign loc_alert_cause_la3_wd = reg_wdata[3];
3453: 
3454:   assign classa_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
3455:   assign classa_ctrl_en_wd = reg_wdata[0];
3456: 
3457:   assign classa_ctrl_lock_we = addr_hit[11] & reg_we & ~wr_err;
3458:   assign classa_ctrl_lock_wd = reg_wdata[1];
3459: 
3460:   assign classa_ctrl_en_e0_we = addr_hit[11] & reg_we & ~wr_err;
3461:   assign classa_ctrl_en_e0_wd = reg_wdata[2];
3462: 
3463:   assign classa_ctrl_en_e1_we = addr_hit[11] & reg_we & ~wr_err;
3464:   assign classa_ctrl_en_e1_wd = reg_wdata[3];
3465: 
3466:   assign classa_ctrl_en_e2_we = addr_hit[11] & reg_we & ~wr_err;
3467:   assign classa_ctrl_en_e2_wd = reg_wdata[4];
3468: 
3469:   assign classa_ctrl_en_e3_we = addr_hit[11] & reg_we & ~wr_err;
3470:   assign classa_ctrl_en_e3_wd = reg_wdata[5];
3471: 
3472:   assign classa_ctrl_map_e0_we = addr_hit[11] & reg_we & ~wr_err;
3473:   assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
3474: 
3475:   assign classa_ctrl_map_e1_we = addr_hit[11] & reg_we & ~wr_err;
3476:   assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
3477: 
3478:   assign classa_ctrl_map_e2_we = addr_hit[11] & reg_we & ~wr_err;
3479:   assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
3480: 
3481:   assign classa_ctrl_map_e3_we = addr_hit[11] & reg_we & ~wr_err;
3482:   assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
3483: 
3484:   assign classa_clren_we = addr_hit[12] & reg_we & ~wr_err;
3485:   assign classa_clren_wd = reg_wdata[0];
3486: 
3487:   assign classa_clr_we = addr_hit[13] & reg_we & ~wr_err;
3488:   assign classa_clr_wd = reg_wdata[0];
3489: 
3490:   assign classa_accum_cnt_re = addr_hit[14] && reg_re;
3491: 
3492:   assign classa_accum_thresh_we = addr_hit[15] & reg_we & ~wr_err;
3493:   assign classa_accum_thresh_wd = reg_wdata[15:0];
3494: 
3495:   assign classa_timeout_cyc_we = addr_hit[16] & reg_we & ~wr_err;
3496:   assign classa_timeout_cyc_wd = reg_wdata[31:0];
3497: 
3498:   assign classa_phase0_cyc_we = addr_hit[17] & reg_we & ~wr_err;
3499:   assign classa_phase0_cyc_wd = reg_wdata[31:0];
3500: 
3501:   assign classa_phase1_cyc_we = addr_hit[18] & reg_we & ~wr_err;
3502:   assign classa_phase1_cyc_wd = reg_wdata[31:0];
3503: 
3504:   assign classa_phase2_cyc_we = addr_hit[19] & reg_we & ~wr_err;
3505:   assign classa_phase2_cyc_wd = reg_wdata[31:0];
3506: 
3507:   assign classa_phase3_cyc_we = addr_hit[20] & reg_we & ~wr_err;
3508:   assign classa_phase3_cyc_wd = reg_wdata[31:0];
3509: 
3510:   assign classa_esc_cnt_re = addr_hit[21] && reg_re;
3511: 
3512:   assign classa_state_re = addr_hit[22] && reg_re;
3513: 
3514:   assign classb_ctrl_en_we = addr_hit[23] & reg_we & ~wr_err;
3515:   assign classb_ctrl_en_wd = reg_wdata[0];
3516: 
3517:   assign classb_ctrl_lock_we = addr_hit[23] & reg_we & ~wr_err;
3518:   assign classb_ctrl_lock_wd = reg_wdata[1];
3519: 
3520:   assign classb_ctrl_en_e0_we = addr_hit[23] & reg_we & ~wr_err;
3521:   assign classb_ctrl_en_e0_wd = reg_wdata[2];
3522: 
3523:   assign classb_ctrl_en_e1_we = addr_hit[23] & reg_we & ~wr_err;
3524:   assign classb_ctrl_en_e1_wd = reg_wdata[3];
3525: 
3526:   assign classb_ctrl_en_e2_we = addr_hit[23] & reg_we & ~wr_err;
3527:   assign classb_ctrl_en_e2_wd = reg_wdata[4];
3528: 
3529:   assign classb_ctrl_en_e3_we = addr_hit[23] & reg_we & ~wr_err;
3530:   assign classb_ctrl_en_e3_wd = reg_wdata[5];
3531: 
3532:   assign classb_ctrl_map_e0_we = addr_hit[23] & reg_we & ~wr_err;
3533:   assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
3534: 
3535:   assign classb_ctrl_map_e1_we = addr_hit[23] & reg_we & ~wr_err;
3536:   assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
3537: 
3538:   assign classb_ctrl_map_e2_we = addr_hit[23] & reg_we & ~wr_err;
3539:   assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
3540: 
3541:   assign classb_ctrl_map_e3_we = addr_hit[23] & reg_we & ~wr_err;
3542:   assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
3543: 
3544:   assign classb_clren_we = addr_hit[24] & reg_we & ~wr_err;
3545:   assign classb_clren_wd = reg_wdata[0];
3546: 
3547:   assign classb_clr_we = addr_hit[25] & reg_we & ~wr_err;
3548:   assign classb_clr_wd = reg_wdata[0];
3549: 
3550:   assign classb_accum_cnt_re = addr_hit[26] && reg_re;
3551: 
3552:   assign classb_accum_thresh_we = addr_hit[27] & reg_we & ~wr_err;
3553:   assign classb_accum_thresh_wd = reg_wdata[15:0];
3554: 
3555:   assign classb_timeout_cyc_we = addr_hit[28] & reg_we & ~wr_err;
3556:   assign classb_timeout_cyc_wd = reg_wdata[31:0];
3557: 
3558:   assign classb_phase0_cyc_we = addr_hit[29] & reg_we & ~wr_err;
3559:   assign classb_phase0_cyc_wd = reg_wdata[31:0];
3560: 
3561:   assign classb_phase1_cyc_we = addr_hit[30] & reg_we & ~wr_err;
3562:   assign classb_phase1_cyc_wd = reg_wdata[31:0];
3563: 
3564:   assign classb_phase2_cyc_we = addr_hit[31] & reg_we & ~wr_err;
3565:   assign classb_phase2_cyc_wd = reg_wdata[31:0];
3566: 
3567:   assign classb_phase3_cyc_we = addr_hit[32] & reg_we & ~wr_err;
3568:   assign classb_phase3_cyc_wd = reg_wdata[31:0];
3569: 
3570:   assign classb_esc_cnt_re = addr_hit[33] && reg_re;
3571: 
3572:   assign classb_state_re = addr_hit[34] && reg_re;
3573: 
3574:   assign classc_ctrl_en_we = addr_hit[35] & reg_we & ~wr_err;
3575:   assign classc_ctrl_en_wd = reg_wdata[0];
3576: 
3577:   assign classc_ctrl_lock_we = addr_hit[35] & reg_we & ~wr_err;
3578:   assign classc_ctrl_lock_wd = reg_wdata[1];
3579: 
3580:   assign classc_ctrl_en_e0_we = addr_hit[35] & reg_we & ~wr_err;
3581:   assign classc_ctrl_en_e0_wd = reg_wdata[2];
3582: 
3583:   assign classc_ctrl_en_e1_we = addr_hit[35] & reg_we & ~wr_err;
3584:   assign classc_ctrl_en_e1_wd = reg_wdata[3];
3585: 
3586:   assign classc_ctrl_en_e2_we = addr_hit[35] & reg_we & ~wr_err;
3587:   assign classc_ctrl_en_e2_wd = reg_wdata[4];
3588: 
3589:   assign classc_ctrl_en_e3_we = addr_hit[35] & reg_we & ~wr_err;
3590:   assign classc_ctrl_en_e3_wd = reg_wdata[5];
3591: 
3592:   assign classc_ctrl_map_e0_we = addr_hit[35] & reg_we & ~wr_err;
3593:   assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
3594: 
3595:   assign classc_ctrl_map_e1_we = addr_hit[35] & reg_we & ~wr_err;
3596:   assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
3597: 
3598:   assign classc_ctrl_map_e2_we = addr_hit[35] & reg_we & ~wr_err;
3599:   assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
3600: 
3601:   assign classc_ctrl_map_e3_we = addr_hit[35] & reg_we & ~wr_err;
3602:   assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
3603: 
3604:   assign classc_clren_we = addr_hit[36] & reg_we & ~wr_err;
3605:   assign classc_clren_wd = reg_wdata[0];
3606: 
3607:   assign classc_clr_we = addr_hit[37] & reg_we & ~wr_err;
3608:   assign classc_clr_wd = reg_wdata[0];
3609: 
3610:   assign classc_accum_cnt_re = addr_hit[38] && reg_re;
3611: 
3612:   assign classc_accum_thresh_we = addr_hit[39] & reg_we & ~wr_err;
3613:   assign classc_accum_thresh_wd = reg_wdata[15:0];
3614: 
3615:   assign classc_timeout_cyc_we = addr_hit[40] & reg_we & ~wr_err;
3616:   assign classc_timeout_cyc_wd = reg_wdata[31:0];
3617: 
3618:   assign classc_phase0_cyc_we = addr_hit[41] & reg_we & ~wr_err;
3619:   assign classc_phase0_cyc_wd = reg_wdata[31:0];
3620: 
3621:   assign classc_phase1_cyc_we = addr_hit[42] & reg_we & ~wr_err;
3622:   assign classc_phase1_cyc_wd = reg_wdata[31:0];
3623: 
3624:   assign classc_phase2_cyc_we = addr_hit[43] & reg_we & ~wr_err;
3625:   assign classc_phase2_cyc_wd = reg_wdata[31:0];
3626: 
3627:   assign classc_phase3_cyc_we = addr_hit[44] & reg_we & ~wr_err;
3628:   assign classc_phase3_cyc_wd = reg_wdata[31:0];
3629: 
3630:   assign classc_esc_cnt_re = addr_hit[45] && reg_re;
3631: 
3632:   assign classc_state_re = addr_hit[46] && reg_re;
3633: 
3634:   assign classd_ctrl_en_we = addr_hit[47] & reg_we & ~wr_err;
3635:   assign classd_ctrl_en_wd = reg_wdata[0];
3636: 
3637:   assign classd_ctrl_lock_we = addr_hit[47] & reg_we & ~wr_err;
3638:   assign classd_ctrl_lock_wd = reg_wdata[1];
3639: 
3640:   assign classd_ctrl_en_e0_we = addr_hit[47] & reg_we & ~wr_err;
3641:   assign classd_ctrl_en_e0_wd = reg_wdata[2];
3642: 
3643:   assign classd_ctrl_en_e1_we = addr_hit[47] & reg_we & ~wr_err;
3644:   assign classd_ctrl_en_e1_wd = reg_wdata[3];
3645: 
3646:   assign classd_ctrl_en_e2_we = addr_hit[47] & reg_we & ~wr_err;
3647:   assign classd_ctrl_en_e2_wd = reg_wdata[4];
3648: 
3649:   assign classd_ctrl_en_e3_we = addr_hit[47] & reg_we & ~wr_err;
3650:   assign classd_ctrl_en_e3_wd = reg_wdata[5];
3651: 
3652:   assign classd_ctrl_map_e0_we = addr_hit[47] & reg_we & ~wr_err;
3653:   assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
3654: 
3655:   assign classd_ctrl_map_e1_we = addr_hit[47] & reg_we & ~wr_err;
3656:   assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
3657: 
3658:   assign classd_ctrl_map_e2_we = addr_hit[47] & reg_we & ~wr_err;
3659:   assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
3660: 
3661:   assign classd_ctrl_map_e3_we = addr_hit[47] & reg_we & ~wr_err;
3662:   assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
3663: 
3664:   assign classd_clren_we = addr_hit[48] & reg_we & ~wr_err;
3665:   assign classd_clren_wd = reg_wdata[0];
3666: 
3667:   assign classd_clr_we = addr_hit[49] & reg_we & ~wr_err;
3668:   assign classd_clr_wd = reg_wdata[0];
3669: 
3670:   assign classd_accum_cnt_re = addr_hit[50] && reg_re;
3671: 
3672:   assign classd_accum_thresh_we = addr_hit[51] & reg_we & ~wr_err;
3673:   assign classd_accum_thresh_wd = reg_wdata[15:0];
3674: 
3675:   assign classd_timeout_cyc_we = addr_hit[52] & reg_we & ~wr_err;
3676:   assign classd_timeout_cyc_wd = reg_wdata[31:0];
3677: 
3678:   assign classd_phase0_cyc_we = addr_hit[53] & reg_we & ~wr_err;
3679:   assign classd_phase0_cyc_wd = reg_wdata[31:0];
3680: 
3681:   assign classd_phase1_cyc_we = addr_hit[54] & reg_we & ~wr_err;
3682:   assign classd_phase1_cyc_wd = reg_wdata[31:0];
3683: 
3684:   assign classd_phase2_cyc_we = addr_hit[55] & reg_we & ~wr_err;
3685:   assign classd_phase2_cyc_wd = reg_wdata[31:0];
3686: 
3687:   assign classd_phase3_cyc_we = addr_hit[56] & reg_we & ~wr_err;
3688:   assign classd_phase3_cyc_wd = reg_wdata[31:0];
3689: 
3690:   assign classd_esc_cnt_re = addr_hit[57] && reg_re;
3691: 
3692:   assign classd_state_re = addr_hit[58] && reg_re;
3693: 
3694:   // Read data return
3695:   always_comb begin
3696:     reg_rdata_next = '0;
3697:     unique case (1'b1)
3698:       addr_hit[0]: begin
3699:         reg_rdata_next[0] = intr_state_classa_qs;
3700:         reg_rdata_next[1] = intr_state_classb_qs;
3701:         reg_rdata_next[2] = intr_state_classc_qs;
3702:         reg_rdata_next[3] = intr_state_classd_qs;
3703:       end
3704: 
3705:       addr_hit[1]: begin
3706:         reg_rdata_next[0] = intr_enable_classa_qs;
3707:         reg_rdata_next[1] = intr_enable_classb_qs;
3708:         reg_rdata_next[2] = intr_enable_classc_qs;
3709:         reg_rdata_next[3] = intr_enable_classd_qs;
3710:       end
3711: 
3712:       addr_hit[2]: begin
3713:         reg_rdata_next[0] = '0;
3714:         reg_rdata_next[1] = '0;
3715:         reg_rdata_next[2] = '0;
3716:         reg_rdata_next[3] = '0;
3717:       end
3718: 
3719:       addr_hit[3]: begin
3720:         reg_rdata_next[0] = regen_qs;
3721:       end
3722: 
3723:       addr_hit[4]: begin
3724:         reg_rdata_next[23:0] = ping_timeout_cyc_qs;
3725:       end
3726: 
3727:       addr_hit[5]: begin
3728:         reg_rdata_next[0] = alert_en_qs;
3729:       end
3730: 
3731:       addr_hit[6]: begin
3732:         reg_rdata_next[1:0] = alert_class_qs;
3733:       end
3734: 
3735:       addr_hit[7]: begin
3736:         reg_rdata_next[0] = alert_cause_qs;
3737:       end
3738: 
3739:       addr_hit[8]: begin
3740:         reg_rdata_next[0] = loc_alert_en_en_la0_qs;
3741:         reg_rdata_next[1] = loc_alert_en_en_la1_qs;
3742:         reg_rdata_next[2] = loc_alert_en_en_la2_qs;
3743:         reg_rdata_next[3] = loc_alert_en_en_la3_qs;
3744:       end
3745: 
3746:       addr_hit[9]: begin
3747:         reg_rdata_next[1:0] = loc_alert_class_class_la0_qs;
3748:         reg_rdata_next[3:2] = loc_alert_class_class_la1_qs;
3749:         reg_rdata_next[5:4] = loc_alert_class_class_la2_qs;
3750:         reg_rdata_next[7:6] = loc_alert_class_class_la3_qs;
3751:       end
3752: 
3753:       addr_hit[10]: begin
3754:         reg_rdata_next[0] = loc_alert_cause_la0_qs;
3755:         reg_rdata_next[1] = loc_alert_cause_la1_qs;
3756:         reg_rdata_next[2] = loc_alert_cause_la2_qs;
3757:         reg_rdata_next[3] = loc_alert_cause_la3_qs;
3758:       end
3759: 
3760:       addr_hit[11]: begin
3761:         reg_rdata_next[0] = classa_ctrl_en_qs;
3762:         reg_rdata_next[1] = classa_ctrl_lock_qs;
3763:         reg_rdata_next[2] = classa_ctrl_en_e0_qs;
3764:         reg_rdata_next[3] = classa_ctrl_en_e1_qs;
3765:         reg_rdata_next[4] = classa_ctrl_en_e2_qs;
3766:         reg_rdata_next[5] = classa_ctrl_en_e3_qs;
3767:         reg_rdata_next[7:6] = classa_ctrl_map_e0_qs;
3768:         reg_rdata_next[9:8] = classa_ctrl_map_e1_qs;
3769:         reg_rdata_next[11:10] = classa_ctrl_map_e2_qs;
3770:         reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
3771:       end
3772: 
3773:       addr_hit[12]: begin
3774:         reg_rdata_next[0] = classa_clren_qs;
3775:       end
3776: 
3777:       addr_hit[13]: begin
3778:         reg_rdata_next[0] = '0;
3779:       end
3780: 
3781:       addr_hit[14]: begin
3782:         reg_rdata_next[15:0] = classa_accum_cnt_qs;
3783:       end
3784: 
3785:       addr_hit[15]: begin
3786:         reg_rdata_next[15:0] = classa_accum_thresh_qs;
3787:       end
3788: 
3789:       addr_hit[16]: begin
3790:         reg_rdata_next[31:0] = classa_timeout_cyc_qs;
3791:       end
3792: 
3793:       addr_hit[17]: begin
3794:         reg_rdata_next[31:0] = classa_phase0_cyc_qs;
3795:       end
3796: 
3797:       addr_hit[18]: begin
3798:         reg_rdata_next[31:0] = classa_phase1_cyc_qs;
3799:       end
3800: 
3801:       addr_hit[19]: begin
3802:         reg_rdata_next[31:0] = classa_phase2_cyc_qs;
3803:       end
3804: 
3805:       addr_hit[20]: begin
3806:         reg_rdata_next[31:0] = classa_phase3_cyc_qs;
3807:       end
3808: 
3809:       addr_hit[21]: begin
3810:         reg_rdata_next[31:0] = classa_esc_cnt_qs;
3811:       end
3812: 
3813:       addr_hit[22]: begin
3814:         reg_rdata_next[2:0] = classa_state_qs;
3815:       end
3816: 
3817:       addr_hit[23]: begin
3818:         reg_rdata_next[0] = classb_ctrl_en_qs;
3819:         reg_rdata_next[1] = classb_ctrl_lock_qs;
3820:         reg_rdata_next[2] = classb_ctrl_en_e0_qs;
3821:         reg_rdata_next[3] = classb_ctrl_en_e1_qs;
3822:         reg_rdata_next[4] = classb_ctrl_en_e2_qs;
3823:         reg_rdata_next[5] = classb_ctrl_en_e3_qs;
3824:         reg_rdata_next[7:6] = classb_ctrl_map_e0_qs;
3825:         reg_rdata_next[9:8] = classb_ctrl_map_e1_qs;
3826:         reg_rdata_next[11:10] = classb_ctrl_map_e2_qs;
3827:         reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
3828:       end
3829: 
3830:       addr_hit[24]: begin
3831:         reg_rdata_next[0] = classb_clren_qs;
3832:       end
3833: 
3834:       addr_hit[25]: begin
3835:         reg_rdata_next[0] = '0;
3836:       end
3837: 
3838:       addr_hit[26]: begin
3839:         reg_rdata_next[15:0] = classb_accum_cnt_qs;
3840:       end
3841: 
3842:       addr_hit[27]: begin
3843:         reg_rdata_next[15:0] = classb_accum_thresh_qs;
3844:       end
3845: 
3846:       addr_hit[28]: begin
3847:         reg_rdata_next[31:0] = classb_timeout_cyc_qs;
3848:       end
3849: 
3850:       addr_hit[29]: begin
3851:         reg_rdata_next[31:0] = classb_phase0_cyc_qs;
3852:       end
3853: 
3854:       addr_hit[30]: begin
3855:         reg_rdata_next[31:0] = classb_phase1_cyc_qs;
3856:       end
3857: 
3858:       addr_hit[31]: begin
3859:         reg_rdata_next[31:0] = classb_phase2_cyc_qs;
3860:       end
3861: 
3862:       addr_hit[32]: begin
3863:         reg_rdata_next[31:0] = classb_phase3_cyc_qs;
3864:       end
3865: 
3866:       addr_hit[33]: begin
3867:         reg_rdata_next[31:0] = classb_esc_cnt_qs;
3868:       end
3869: 
3870:       addr_hit[34]: begin
3871:         reg_rdata_next[2:0] = classb_state_qs;
3872:       end
3873: 
3874:       addr_hit[35]: begin
3875:         reg_rdata_next[0] = classc_ctrl_en_qs;
3876:         reg_rdata_next[1] = classc_ctrl_lock_qs;
3877:         reg_rdata_next[2] = classc_ctrl_en_e0_qs;
3878:         reg_rdata_next[3] = classc_ctrl_en_e1_qs;
3879:         reg_rdata_next[4] = classc_ctrl_en_e2_qs;
3880:         reg_rdata_next[5] = classc_ctrl_en_e3_qs;
3881:         reg_rdata_next[7:6] = classc_ctrl_map_e0_qs;
3882:         reg_rdata_next[9:8] = classc_ctrl_map_e1_qs;
3883:         reg_rdata_next[11:10] = classc_ctrl_map_e2_qs;
3884:         reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
3885:       end
3886: 
3887:       addr_hit[36]: begin
3888:         reg_rdata_next[0] = classc_clren_qs;
3889:       end
3890: 
3891:       addr_hit[37]: begin
3892:         reg_rdata_next[0] = '0;
3893:       end
3894: 
3895:       addr_hit[38]: begin
3896:         reg_rdata_next[15:0] = classc_accum_cnt_qs;
3897:       end
3898: 
3899:       addr_hit[39]: begin
3900:         reg_rdata_next[15:0] = classc_accum_thresh_qs;
3901:       end
3902: 
3903:       addr_hit[40]: begin
3904:         reg_rdata_next[31:0] = classc_timeout_cyc_qs;
3905:       end
3906: 
3907:       addr_hit[41]: begin
3908:         reg_rdata_next[31:0] = classc_phase0_cyc_qs;
3909:       end
3910: 
3911:       addr_hit[42]: begin
3912:         reg_rdata_next[31:0] = classc_phase1_cyc_qs;
3913:       end
3914: 
3915:       addr_hit[43]: begin
3916:         reg_rdata_next[31:0] = classc_phase2_cyc_qs;
3917:       end
3918: 
3919:       addr_hit[44]: begin
3920:         reg_rdata_next[31:0] = classc_phase3_cyc_qs;
3921:       end
3922: 
3923:       addr_hit[45]: begin
3924:         reg_rdata_next[31:0] = classc_esc_cnt_qs;
3925:       end
3926: 
3927:       addr_hit[46]: begin
3928:         reg_rdata_next[2:0] = classc_state_qs;
3929:       end
3930: 
3931:       addr_hit[47]: begin
3932:         reg_rdata_next[0] = classd_ctrl_en_qs;
3933:         reg_rdata_next[1] = classd_ctrl_lock_qs;
3934:         reg_rdata_next[2] = classd_ctrl_en_e0_qs;
3935:         reg_rdata_next[3] = classd_ctrl_en_e1_qs;
3936:         reg_rdata_next[4] = classd_ctrl_en_e2_qs;
3937:         reg_rdata_next[5] = classd_ctrl_en_e3_qs;
3938:         reg_rdata_next[7:6] = classd_ctrl_map_e0_qs;
3939:         reg_rdata_next[9:8] = classd_ctrl_map_e1_qs;
3940:         reg_rdata_next[11:10] = classd_ctrl_map_e2_qs;
3941:         reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
3942:       end
3943: 
3944:       addr_hit[48]: begin
3945:         reg_rdata_next[0] = classd_clren_qs;
3946:       end
3947: 
3948:       addr_hit[49]: begin
3949:         reg_rdata_next[0] = '0;
3950:       end
3951: 
3952:       addr_hit[50]: begin
3953:         reg_rdata_next[15:0] = classd_accum_cnt_qs;
3954:       end
3955: 
3956:       addr_hit[51]: begin
3957:         reg_rdata_next[15:0] = classd_accum_thresh_qs;
3958:       end
3959: 
3960:       addr_hit[52]: begin
3961:         reg_rdata_next[31:0] = classd_timeout_cyc_qs;
3962:       end
3963: 
3964:       addr_hit[53]: begin
3965:         reg_rdata_next[31:0] = classd_phase0_cyc_qs;
3966:       end
3967: 
3968:       addr_hit[54]: begin
3969:         reg_rdata_next[31:0] = classd_phase1_cyc_qs;
3970:       end
3971: 
3972:       addr_hit[55]: begin
3973:         reg_rdata_next[31:0] = classd_phase2_cyc_qs;
3974:       end
3975: 
3976:       addr_hit[56]: begin
3977:         reg_rdata_next[31:0] = classd_phase3_cyc_qs;
3978:       end
3979: 
3980:       addr_hit[57]: begin
3981:         reg_rdata_next[31:0] = classd_esc_cnt_qs;
3982:       end
3983: 
3984:       addr_hit[58]: begin
3985:         reg_rdata_next[2:0] = classd_state_qs;
3986:       end
3987: 
3988:       default: begin
3989:         reg_rdata_next = '1;
3990:       end
3991:     endcase
3992:   end
3993: 
3994:   // Assertions for Register Interface
3995:   `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
3996:   `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
3997: 
3998:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
3999: 
4000:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
4001: 
4002:   // this is formulated as an assumption such that the FPV testbenches do disprove this
4003:   // property by mistake
4004:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
4005: 
4006: endmodule
4007: