hw/ip/pinmux/rtl/pinmux.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Pinmux toplevel.
6: //
7:
8: module pinmux (
9: input clk_i,
10: input rst_ni,
11: // Bus Interface (device)
12: input tlul_pkg::tl_h2d_t tl_i,
13: output tlul_pkg::tl_d2h_t tl_o,
14: // Peripheral side
15: input [pinmux_reg_pkg::NPeriphOut-1:0] periph_to_mio_i,
16: input [pinmux_reg_pkg::NPeriphOut-1:0] periph_to_mio_oe_i,
17: output logic [pinmux_reg_pkg::NPeriphIn-1:0] mio_to_periph_o,
18: // Pad side
19: output logic [pinmux_reg_pkg::NMioPads-1:0] mio_out_o,
20: output logic [pinmux_reg_pkg::NMioPads-1:0] mio_oe_o,
21: input [pinmux_reg_pkg::NMioPads-1:0] mio_in_i
22: );
23:
24: //////////////////////////////////
25: // Regfile Breakout and Mapping //
26: //////////////////////////////////
27:
28: pinmux_reg_pkg::pinmux_reg2hw_t reg2hw;
29:
30: pinmux_reg_top i_reg_top (
31: .clk_i ,
32: .rst_ni ,
33: .tl_i ,
34: .tl_o ,
35: .reg2hw ,
36: .devmode_i(1'b1)
37: );
38:
39: ///////////////
40: // Input Mux //
41: ///////////////
42:
43: for (genvar k = 0; k < pinmux_reg_pkg::NPeriphIn; k++) begin : gen_periph_in
44: logic [pinmux_reg_pkg::NMioPads+2-1:0] data_mux;
45: // stack input and default signals for convenient indexing below
46: // possible defaults: constant 0 or 1
47: assign data_mux = $bits(data_mux)'({mio_in_i, 1'b1, 1'b0});
48: // index using configured insel
49: assign mio_to_periph_o[k] = data_mux[reg2hw.periph_insel[k].q];
50: // disallow undefined entries
51: `ASSUME(InSelRange_A, reg2hw.periph_insel[k].q < pinmux_reg_pkg::NMioPads + 2, clk_i, !rst_ni)
52: end
53:
54: ////////////////
55: // Output Mux //
56: ////////////////
57:
58: for (genvar k = 0; k < pinmux_reg_pkg::NMioPads; k++) begin : gen_mio_out
59: logic [pinmux_reg_pkg::NPeriphOut+3-1:0] data_mux, oe_mux;
60: // stack output data/enable and default signals for convenient indexing below
61: // possible defaults: 0, 1 or 2 (high-Z)
62: assign data_mux = $bits(data_mux)'({periph_to_mio_i, 1'b0, 1'b1, 1'b0});
63: assign oe_mux = $bits(oe_mux)'({periph_to_mio_oe_i, 1'b0, 1'b1, 1'b1});
64: // index using configured outsel
65: assign mio_out_o[k] = data_mux[reg2hw.mio_outsel[k].q];
66: assign mio_oe_o[k] = oe_mux[reg2hw.mio_outsel[k].q];
67: // disallow undefined entries
68: `ASSUME(OutSelRange_A, reg2hw.mio_outsel[k].q < pinmux_reg_pkg::NPeriphOut + 3, clk_i, !rst_ni)
69: end
70:
71: ////////////////
72: // Assertions //
73: ////////////////
74:
75: `ASSERT_KNOWN(TlDValidKnownO_A, tl_o.d_valid, clk_i, !rst_ni)
76: `ASSERT_KNOWN(TlAReadyKnownO_A, tl_o.a_ready, clk_i, !rst_ni)
77: `ASSERT_KNOWN(MioToPeriphKnownO_A, mio_to_periph_o, clk_i, !rst_ni)
78: `ASSERT_KNOWN(MioOutKnownO_A, mio_out_o, clk_i, !rst_ni)
79: `ASSERT_KNOWN(MioOeKnownO_A, mio_oe_o, clk_i, !rst_ni)
80:
81: endmodule : pinmux
82: