hw/ip/rv_timer/rtl/rv_timer_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package rv_timer_reg_pkg;
8:
9: // Param list
10: parameter int N_HARTS = 1;
11: parameter int N_TIMERS = 1;
12:
13: ////////////////////////////
14: // Typedefs for registers //
15: ////////////////////////////
16: typedef struct packed {
17: logic q;
18: } rv_timer_reg2hw_ctrl_mreg_t;
19:
20: typedef struct packed {
21: struct packed {
22: logic [11:0] q;
23: } prescale;
24: struct packed {
25: logic [7:0] q;
26: } step;
27: } rv_timer_reg2hw_cfg0_reg_t;
28:
29: typedef struct packed {
30: logic [31:0] q;
31: } rv_timer_reg2hw_timer_v_lower0_reg_t;
32:
33: typedef struct packed {
34: logic [31:0] q;
35: } rv_timer_reg2hw_timer_v_upper0_reg_t;
36:
37: typedef struct packed {
38: logic [31:0] q;
39: } rv_timer_reg2hw_compare_lower0_0_reg_t;
40:
41: typedef struct packed {
42: logic [31:0] q;
43: } rv_timer_reg2hw_compare_upper0_0_reg_t;
44:
45: typedef struct packed {
46: logic q;
47: } rv_timer_reg2hw_intr_enable0_mreg_t;
48:
49: typedef struct packed {
50: logic q;
51: } rv_timer_reg2hw_intr_state0_mreg_t;
52:
53: typedef struct packed {
54: logic q;
55: logic qe;
56: } rv_timer_reg2hw_intr_test0_mreg_t;
57:
58:
59: typedef struct packed {
60: logic [31:0] d;
61: logic de;
62: } rv_timer_hw2reg_timer_v_lower0_reg_t;
63:
64: typedef struct packed {
65: logic [31:0] d;
66: logic de;
67: } rv_timer_hw2reg_timer_v_upper0_reg_t;
68:
69: typedef struct packed {
70: logic d;
71: logic de;
72: } rv_timer_hw2reg_intr_state0_mreg_t;
73:
74:
75: ///////////////////////////////////////
76: // Register to internal design logic //
77: ///////////////////////////////////////
78: typedef struct packed {
79: rv_timer_reg2hw_ctrl_mreg_t [0:0] ctrl; // [152:152]
80: rv_timer_reg2hw_cfg0_reg_t cfg0; // [151:132]
81: rv_timer_reg2hw_timer_v_lower0_reg_t timer_v_lower0; // [131:100]
82: rv_timer_reg2hw_timer_v_upper0_reg_t timer_v_upper0; // [99:68]
83: rv_timer_reg2hw_compare_lower0_0_reg_t compare_lower0_0; // [67:36]
84: rv_timer_reg2hw_compare_upper0_0_reg_t compare_upper0_0; // [35:4]
85: rv_timer_reg2hw_intr_enable0_mreg_t [0:0] intr_enable0; // [3:3]
86: rv_timer_reg2hw_intr_state0_mreg_t [0:0] intr_state0; // [2:2]
87: rv_timer_reg2hw_intr_test0_mreg_t [0:0] intr_test0; // [1:0]
88: } rv_timer_reg2hw_t;
89:
90: ///////////////////////////////////////
91: // Internal design logic to register //
92: ///////////////////////////////////////
93: typedef struct packed {
94: rv_timer_hw2reg_timer_v_lower0_reg_t timer_v_lower0; // [67:36]
95: rv_timer_hw2reg_timer_v_upper0_reg_t timer_v_upper0; // [35:4]
96: rv_timer_hw2reg_intr_state0_mreg_t [0:0] intr_state0; // [3:2]
97: } rv_timer_hw2reg_t;
98:
99: // Register Address
100: parameter logic [8:0] RV_TIMER_CTRL_OFFSET = 9'h 0;
101: parameter logic [8:0] RV_TIMER_CFG0_OFFSET = 9'h 100;
102: parameter logic [8:0] RV_TIMER_TIMER_V_LOWER0_OFFSET = 9'h 104;
103: parameter logic [8:0] RV_TIMER_TIMER_V_UPPER0_OFFSET = 9'h 108;
104: parameter logic [8:0] RV_TIMER_COMPARE_LOWER0_0_OFFSET = 9'h 10c;
105: parameter logic [8:0] RV_TIMER_COMPARE_UPPER0_0_OFFSET = 9'h 110;
106: parameter logic [8:0] RV_TIMER_INTR_ENABLE0_OFFSET = 9'h 114;
107: parameter logic [8:0] RV_TIMER_INTR_STATE0_OFFSET = 9'h 118;
108: parameter logic [8:0] RV_TIMER_INTR_TEST0_OFFSET = 9'h 11c;
109:
110:
111: // Register Index
112: typedef enum int {
113: RV_TIMER_CTRL,
114: RV_TIMER_CFG0,
115: RV_TIMER_TIMER_V_LOWER0,
116: RV_TIMER_TIMER_V_UPPER0,
117: RV_TIMER_COMPARE_LOWER0_0,
118: RV_TIMER_COMPARE_UPPER0_0,
119: RV_TIMER_INTR_ENABLE0,
120: RV_TIMER_INTR_STATE0,
121: RV_TIMER_INTR_TEST0
122: } rv_timer_id_e;
123:
124: // Register width information to check illegal writes
125: parameter logic [3:0] RV_TIMER_PERMIT [9] = '{
126: 4'b 0001, // index[0] RV_TIMER_CTRL
127: 4'b 0111, // index[1] RV_TIMER_CFG0
128: 4'b 1111, // index[2] RV_TIMER_TIMER_V_LOWER0
129: 4'b 1111, // index[3] RV_TIMER_TIMER_V_UPPER0
130: 4'b 1111, // index[4] RV_TIMER_COMPARE_LOWER0_0
131: 4'b 1111, // index[5] RV_TIMER_COMPARE_UPPER0_0
132: 4'b 0001, // index[6] RV_TIMER_INTR_ENABLE0
133: 4'b 0001, // index[7] RV_TIMER_INTR_STATE0
134: 4'b 0001 // index[8] RV_TIMER_INTR_TEST0
135: };
136: endpackage
137:
138: