../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_reg_pkg.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Package auto-generated by `reggen` containing data structure
   6: 
   7: package flash_ctrl_reg_pkg;
   8: 
   9:   // Param list
  10:   parameter int NBanks = 2;
  11:   parameter int NumRegions = 8;
  12: 
  13:   ////////////////////////////
  14:   // Typedefs for registers //
  15:   ////////////////////////////
  16:   typedef struct packed {
  17:     struct packed {
  18:       logic        q;
  19:     } prog_empty;
  20:     struct packed {
  21:       logic        q;
  22:     } prog_lvl;
  23:     struct packed {
  24:       logic        q;
  25:     } rd_full;
  26:     struct packed {
  27:       logic        q;
  28:     } rd_lvl;
  29:     struct packed {
  30:       logic        q;
  31:     } op_done;
  32:     struct packed {
  33:       logic        q;
  34:     } op_error;
  35:   } flash_ctrl_reg2hw_intr_state_reg_t;
  36: 
  37:   typedef struct packed {
  38:     struct packed {
  39:       logic        q;
  40:     } prog_empty;
  41:     struct packed {
  42:       logic        q;
  43:     } prog_lvl;
  44:     struct packed {
  45:       logic        q;
  46:     } rd_full;
  47:     struct packed {
  48:       logic        q;
  49:     } rd_lvl;
  50:     struct packed {
  51:       logic        q;
  52:     } op_done;
  53:     struct packed {
  54:       logic        q;
  55:     } op_error;
  56:   } flash_ctrl_reg2hw_intr_enable_reg_t;
  57: 
  58:   typedef struct packed {
  59:     struct packed {
  60:       logic        q;
  61:       logic        qe;
  62:     } prog_empty;
  63:     struct packed {
  64:       logic        q;
  65:       logic        qe;
  66:     } prog_lvl;
  67:     struct packed {
  68:       logic        q;
  69:       logic        qe;
  70:     } rd_full;
  71:     struct packed {
  72:       logic        q;
  73:       logic        qe;
  74:     } rd_lvl;
  75:     struct packed {
  76:       logic        q;
  77:       logic        qe;
  78:     } op_done;
  79:     struct packed {
  80:       logic        q;
  81:       logic        qe;
  82:     } op_error;
  83:   } flash_ctrl_reg2hw_intr_test_reg_t;
  84: 
  85:   typedef struct packed {
  86:     struct packed {
  87:       logic        q;
  88:     } start;
  89:     struct packed {
  90:       logic [1:0]  q;
  91:     } op;
  92:     struct packed {
  93:       logic        q;
  94:     } erase_sel;
  95:     struct packed {
  96:       logic        q;
  97:     } fifo_rst;
  98:     struct packed {
  99:       logic [11:0] q;
 100:     } num;
 101:   } flash_ctrl_reg2hw_control_reg_t;
 102: 
 103:   typedef struct packed {
 104:     logic [31:0] q;
 105:   } flash_ctrl_reg2hw_addr_reg_t;
 106: 
 107:   typedef struct packed {
 108:     struct packed {
 109:       logic        q;
 110:     } en;
 111:     struct packed {
 112:       logic        q;
 113:     } rd_en;
 114:     struct packed {
 115:       logic        q;
 116:     } prog_en;
 117:     struct packed {
 118:       logic        q;
 119:     } erase_en;
 120:     struct packed {
 121:       logic [8:0]  q;
 122:     } base;
 123:     struct packed {
 124:       logic [8:0]  q;
 125:     } size;
 126:   } flash_ctrl_reg2hw_mp_region_cfg_mreg_t;
 127: 
 128:   typedef struct packed {
 129:     struct packed {
 130:       logic        q;
 131:     } rd_en;
 132:     struct packed {
 133:       logic        q;
 134:     } prog_en;
 135:     struct packed {
 136:       logic        q;
 137:     } erase_en;
 138:   } flash_ctrl_reg2hw_default_region_reg_t;
 139: 
 140:   typedef struct packed {
 141:     logic        q;
 142:   } flash_ctrl_reg2hw_mp_bank_cfg_mreg_t;
 143: 
 144:   typedef struct packed {
 145:     logic [31:0] q;
 146:   } flash_ctrl_reg2hw_scratch_reg_t;
 147: 
 148:   typedef struct packed {
 149:     struct packed {
 150:       logic [4:0]  q;
 151:     } prog;
 152:     struct packed {
 153:       logic [4:0]  q;
 154:     } rd;
 155:   } flash_ctrl_reg2hw_fifo_lvl_reg_t;
 156: 
 157: 
 158:   typedef struct packed {
 159:     struct packed {
 160:       logic        d;
 161:       logic        de;
 162:     } prog_empty;
 163:     struct packed {
 164:       logic        d;
 165:       logic        de;
 166:     } prog_lvl;
 167:     struct packed {
 168:       logic        d;
 169:       logic        de;
 170:     } rd_full;
 171:     struct packed {
 172:       logic        d;
 173:       logic        de;
 174:     } rd_lvl;
 175:     struct packed {
 176:       logic        d;
 177:       logic        de;
 178:     } op_done;
 179:     struct packed {
 180:       logic        d;
 181:       logic        de;
 182:     } op_error;
 183:   } flash_ctrl_hw2reg_intr_state_reg_t;
 184: 
 185:   typedef struct packed {
 186:     struct packed {
 187:       logic        d;
 188:       logic        de;
 189:     } start;
 190:   } flash_ctrl_hw2reg_control_reg_t;
 191: 
 192:   typedef struct packed {
 193:     struct packed {
 194:       logic        d;
 195:       logic        de;
 196:     } done;
 197:     struct packed {
 198:       logic        d;
 199:       logic        de;
 200:     } err;
 201:   } flash_ctrl_hw2reg_op_status_reg_t;
 202: 
 203:   typedef struct packed {
 204:     struct packed {
 205:       logic        d;
 206:     } rd_full;
 207:     struct packed {
 208:       logic        d;
 209:     } rd_empty;
 210:     struct packed {
 211:       logic        d;
 212:     } prog_full;
 213:     struct packed {
 214:       logic        d;
 215:     } prog_empty;
 216:     struct packed {
 217:       logic        d;
 218:     } init_wip;
 219:     struct packed {
 220:       logic [8:0]  d;
 221:     } error_page;
 222:     struct packed {
 223:       logic        d;
 224:     } error_bank;
 225:   } flash_ctrl_hw2reg_status_reg_t;
 226: 
 227: 
 228:   ///////////////////////////////////////
 229:   // Register to internal design logic //
 230:   ///////////////////////////////////////
 231:   typedef struct packed {
 232:     flash_ctrl_reg2hw_intr_state_reg_t intr_state; // [295:290]
 233:     flash_ctrl_reg2hw_intr_enable_reg_t intr_enable; // [289:284]
 234:     flash_ctrl_reg2hw_intr_test_reg_t intr_test; // [283:272]
 235:     flash_ctrl_reg2hw_control_reg_t control; // [271:255]
 236:     flash_ctrl_reg2hw_addr_reg_t addr; // [254:223]
 237:     flash_ctrl_reg2hw_mp_region_cfg_mreg_t [7:0] mp_region_cfg; // [222:47]
 238:     flash_ctrl_reg2hw_default_region_reg_t default_region; // [46:44]
 239:     flash_ctrl_reg2hw_mp_bank_cfg_mreg_t [1:0] mp_bank_cfg; // [43:42]
 240:     flash_ctrl_reg2hw_scratch_reg_t scratch; // [41:10]
 241:     flash_ctrl_reg2hw_fifo_lvl_reg_t fifo_lvl; // [9:0]
 242:   } flash_ctrl_reg2hw_t;
 243: 
 244:   ///////////////////////////////////////
 245:   // Internal design logic to register //
 246:   ///////////////////////////////////////
 247:   typedef struct packed {
 248:     flash_ctrl_hw2reg_intr_state_reg_t intr_state; // [32:27]
 249:     flash_ctrl_hw2reg_control_reg_t control; // [26:10]
 250:     flash_ctrl_hw2reg_op_status_reg_t op_status; // [9:10]
 251:     flash_ctrl_hw2reg_status_reg_t status; // [9:10]
 252:   } flash_ctrl_hw2reg_t;
 253: 
 254:   // Register Address
 255:   parameter logic [6:0] FLASH_CTRL_INTR_STATE_OFFSET = 7'h 0;
 256:   parameter logic [6:0] FLASH_CTRL_INTR_ENABLE_OFFSET = 7'h 4;
 257:   parameter logic [6:0] FLASH_CTRL_INTR_TEST_OFFSET = 7'h 8;
 258:   parameter logic [6:0] FLASH_CTRL_CONTROL_OFFSET = 7'h c;
 259:   parameter logic [6:0] FLASH_CTRL_ADDR_OFFSET = 7'h 10;
 260:   parameter logic [6:0] FLASH_CTRL_REGION_CFG_REGWEN_OFFSET = 7'h 14;
 261:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG0_OFFSET = 7'h 18;
 262:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG1_OFFSET = 7'h 1c;
 263:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG2_OFFSET = 7'h 20;
 264:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG3_OFFSET = 7'h 24;
 265:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG4_OFFSET = 7'h 28;
 266:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG5_OFFSET = 7'h 2c;
 267:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG6_OFFSET = 7'h 30;
 268:   parameter logic [6:0] FLASH_CTRL_MP_REGION_CFG7_OFFSET = 7'h 34;
 269:   parameter logic [6:0] FLASH_CTRL_DEFAULT_REGION_OFFSET = 7'h 38;
 270:   parameter logic [6:0] FLASH_CTRL_BANK_CFG_REGWEN_OFFSET = 7'h 3c;
 271:   parameter logic [6:0] FLASH_CTRL_MP_BANK_CFG_OFFSET = 7'h 40;
 272:   parameter logic [6:0] FLASH_CTRL_OP_STATUS_OFFSET = 7'h 44;
 273:   parameter logic [6:0] FLASH_CTRL_STATUS_OFFSET = 7'h 48;
 274:   parameter logic [6:0] FLASH_CTRL_SCRATCH_OFFSET = 7'h 4c;
 275:   parameter logic [6:0] FLASH_CTRL_FIFO_LVL_OFFSET = 7'h 50;
 276: 
 277:   // Window parameter
 278:   parameter logic [6:0] FLASH_CTRL_PROG_FIFO_OFFSET = 7'h 54;
 279:   parameter logic [6:0] FLASH_CTRL_PROG_FIFO_SIZE   = 7'h 4;
 280:   parameter logic [6:0] FLASH_CTRL_RD_FIFO_OFFSET = 7'h 58;
 281:   parameter logic [6:0] FLASH_CTRL_RD_FIFO_SIZE   = 7'h 4;
 282: 
 283:   // Register Index
 284:   typedef enum int {
 285:     FLASH_CTRL_INTR_STATE,
 286:     FLASH_CTRL_INTR_ENABLE,
 287:     FLASH_CTRL_INTR_TEST,
 288:     FLASH_CTRL_CONTROL,
 289:     FLASH_CTRL_ADDR,
 290:     FLASH_CTRL_REGION_CFG_REGWEN,
 291:     FLASH_CTRL_MP_REGION_CFG0,
 292:     FLASH_CTRL_MP_REGION_CFG1,
 293:     FLASH_CTRL_MP_REGION_CFG2,
 294:     FLASH_CTRL_MP_REGION_CFG3,
 295:     FLASH_CTRL_MP_REGION_CFG4,
 296:     FLASH_CTRL_MP_REGION_CFG5,
 297:     FLASH_CTRL_MP_REGION_CFG6,
 298:     FLASH_CTRL_MP_REGION_CFG7,
 299:     FLASH_CTRL_DEFAULT_REGION,
 300:     FLASH_CTRL_BANK_CFG_REGWEN,
 301:     FLASH_CTRL_MP_BANK_CFG,
 302:     FLASH_CTRL_OP_STATUS,
 303:     FLASH_CTRL_STATUS,
 304:     FLASH_CTRL_SCRATCH,
 305:     FLASH_CTRL_FIFO_LVL
 306:   } flash_ctrl_id_e;
 307: 
 308:   // Register width information to check illegal writes
 309:   parameter logic [3:0] FLASH_CTRL_PERMIT [21] = '{
 310:     4'b 0001, // index[ 0] FLASH_CTRL_INTR_STATE
 311:     4'b 0001, // index[ 1] FLASH_CTRL_INTR_ENABLE
 312:     4'b 0001, // index[ 2] FLASH_CTRL_INTR_TEST
 313:     4'b 1111, // index[ 3] FLASH_CTRL_CONTROL
 314:     4'b 1111, // index[ 4] FLASH_CTRL_ADDR
 315:     4'b 0001, // index[ 5] FLASH_CTRL_REGION_CFG_REGWEN
 316:     4'b 1111, // index[ 6] FLASH_CTRL_MP_REGION_CFG0
 317:     4'b 1111, // index[ 7] FLASH_CTRL_MP_REGION_CFG1
 318:     4'b 1111, // index[ 8] FLASH_CTRL_MP_REGION_CFG2
 319:     4'b 1111, // index[ 9] FLASH_CTRL_MP_REGION_CFG3
 320:     4'b 1111, // index[10] FLASH_CTRL_MP_REGION_CFG4
 321:     4'b 1111, // index[11] FLASH_CTRL_MP_REGION_CFG5
 322:     4'b 1111, // index[12] FLASH_CTRL_MP_REGION_CFG6
 323:     4'b 1111, // index[13] FLASH_CTRL_MP_REGION_CFG7
 324:     4'b 0001, // index[14] FLASH_CTRL_DEFAULT_REGION
 325:     4'b 0001, // index[15] FLASH_CTRL_BANK_CFG_REGWEN
 326:     4'b 0001, // index[16] FLASH_CTRL_MP_BANK_CFG
 327:     4'b 0001, // index[17] FLASH_CTRL_OP_STATUS
 328:     4'b 0111, // index[18] FLASH_CTRL_STATUS
 329:     4'b 1111, // index[19] FLASH_CTRL_SCRATCH
 330:     4'b 0011  // index[20] FLASH_CTRL_FIFO_LVL
 331:   };
 332: endpackage
 333: 
 334: