../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4:
5: module top_earlgrey #(
6: parameter bit IbexPipeLine = 0,
7: parameter BootRomInitFile = ""
8: ) (
9: // Clock and Reset
10: input clk_i,
11: input rst_ni,
12:
13: // Fixed io clock
14: input clk_io_i,
15:
16: // USB clock
17: input clk_usb_i,
18:
19: // aon clock
20: input clk_aon_i,
21:
22: // JTAG interface
23: input jtag_tck_i,
24: input jtag_tms_i,
25: input jtag_trst_ni,
26: input jtag_tdi_i,
27: output jtag_tdo_o,
28:
29: // Multiplexed I/O
30: input [31:0] mio_in_i,
31: output logic [31:0] mio_out_o,
32: output logic [31:0] mio_oe_o,
33: // Dedicated I/O
34: input [14:0] dio_in_i,
35: output logic [14:0] dio_out_o,
36: output logic [14:0] dio_oe_o,
37:
38: // pad attributes to padring
39: output logic[padctrl_reg_pkg::NMioPads-1:0]
40: [padctrl_reg_pkg::AttrDw-1:0] mio_attr_o,
41: output logic[padctrl_reg_pkg::NDioPads-1:0]
42: [padctrl_reg_pkg::AttrDw-1:0] dio_attr_o,
43:
44:
45: input scanmode_i // 1 for Scan
46: );
47:
48: // JTAG IDCODE for development versions of this code.
49: // Manufacturers of OpenTitan chips must replace this code with one of their
50: // own IDs.
51: // Field structure as defined in the IEEE 1149.1 (JTAG) specification,
52: // section 12.1.1.
53: localparam logic [31:0] JTAG_IDCODE = {
54: 4'h0, // Version
55: 16'h4F54, // Part Number: "OT"
56: 11'h426, // Manufacturer Identity: Google
57: 1'b1 // (fixed)
58: };
59:
60: import tlul_pkg::*;
61: import top_pkg::*;
62: import tl_main_pkg::*;
63:
64: tl_h2d_t tl_corei_h_h2d;
65: tl_d2h_t tl_corei_h_d2h;
66:
67: tl_h2d_t tl_cored_h_h2d;
68: tl_d2h_t tl_cored_h_d2h;
69:
70: tl_h2d_t tl_dm_sba_h_h2d;
71: tl_d2h_t tl_dm_sba_h_d2h;
72:
73: tl_h2d_t tl_debug_mem_d_h2d;
74: tl_d2h_t tl_debug_mem_d_d2h;
75:
76: tl_h2d_t tl_uart_d_h2d;
77: tl_d2h_t tl_uart_d_d2h;
78: tl_h2d_t tl_gpio_d_h2d;
79: tl_d2h_t tl_gpio_d_d2h;
80: tl_h2d_t tl_spi_device_d_h2d;
81: tl_d2h_t tl_spi_device_d_d2h;
82: tl_h2d_t tl_flash_ctrl_d_h2d;
83: tl_d2h_t tl_flash_ctrl_d_d2h;
84: tl_h2d_t tl_rv_timer_d_h2d;
85: tl_d2h_t tl_rv_timer_d_d2h;
86: tl_h2d_t tl_aes_d_h2d;
87: tl_d2h_t tl_aes_d_d2h;
88: tl_h2d_t tl_hmac_d_h2d;
89: tl_d2h_t tl_hmac_d_d2h;
90: tl_h2d_t tl_rv_plic_d_h2d;
91: tl_d2h_t tl_rv_plic_d_d2h;
92: tl_h2d_t tl_pinmux_d_h2d;
93: tl_d2h_t tl_pinmux_d_d2h;
94: tl_h2d_t tl_padctrl_d_h2d;
95: tl_d2h_t tl_padctrl_d_d2h;
96: tl_h2d_t tl_alert_handler_d_h2d;
97: tl_d2h_t tl_alert_handler_d_d2h;
98: tl_h2d_t tl_pwrmgr_d_h2d;
99: tl_d2h_t tl_pwrmgr_d_d2h;
100: tl_h2d_t tl_rstmgr_d_h2d;
101: tl_d2h_t tl_rstmgr_d_d2h;
102: tl_h2d_t tl_clkmgr_d_h2d;
103: tl_d2h_t tl_clkmgr_d_d2h;
104: tl_h2d_t tl_nmi_gen_d_h2d;
105: tl_d2h_t tl_nmi_gen_d_d2h;
106: tl_h2d_t tl_usbdev_d_h2d;
107: tl_d2h_t tl_usbdev_d_d2h;
108:
109: tl_h2d_t tl_rom_d_h2d;
110: tl_d2h_t tl_rom_d_d2h;
111: tl_h2d_t tl_ram_main_d_h2d;
112: tl_d2h_t tl_ram_main_d_d2h;
113: tl_h2d_t tl_eflash_d_h2d;
114: tl_d2h_t tl_eflash_d_d2h;
115:
116: tl_h2d_t tl_main_peri_h2d;
117: tl_d2h_t tl_main_peri_d2h;
118:
119: // Signals
120: logic [31:0] mio_p2d;
121: logic [31:0] mio_d2p;
122: logic [31:0] mio_d2p_en;
123: logic [14:0] dio_p2d;
124: logic [14:0] dio_d2p;
125: logic [14:0] dio_d2p_en;
126: // uart
127: logic cio_uart_rx_p2d;
128: logic cio_uart_tx_d2p;
129: logic cio_uart_tx_en_d2p;
130: // gpio
131: logic [31:0] cio_gpio_gpio_p2d;
132: logic [31:0] cio_gpio_gpio_d2p;
133: logic [31:0] cio_gpio_gpio_en_d2p;
134: // spi_device
135: logic cio_spi_device_sck_p2d;
136: logic cio_spi_device_csb_p2d;
137: logic cio_spi_device_mosi_p2d;
138: logic cio_spi_device_miso_d2p;
139: logic cio_spi_device_miso_en_d2p;
140: // flash_ctrl
141: // rv_timer
142: // aes
143: // hmac
144: // rv_plic
145: // pinmux
146: // padctrl
147: // alert_handler
148: // pwrmgr
149: // rstmgr
150: // clkmgr
151: // nmi_gen
152: // usbdev
153: logic cio_usbdev_sense_p2d;
154: logic cio_usbdev_d_p2d;
155: logic cio_usbdev_dp_p2d;
156: logic cio_usbdev_dn_p2d;
157: logic cio_usbdev_se0_d2p;
158: logic cio_usbdev_se0_en_d2p;
159: logic cio_usbdev_dp_pullup_d2p;
160: logic cio_usbdev_dp_pullup_en_d2p;
161: logic cio_usbdev_dn_pullup_d2p;
162: logic cio_usbdev_dn_pullup_en_d2p;
163: logic cio_usbdev_tx_mode_se_d2p;
164: logic cio_usbdev_tx_mode_se_en_d2p;
165: logic cio_usbdev_suspend_d2p;
166: logic cio_usbdev_suspend_en_d2p;
167: logic cio_usbdev_d_d2p;
168: logic cio_usbdev_d_en_d2p;
169: logic cio_usbdev_dp_d2p;
170: logic cio_usbdev_dp_en_d2p;
171: logic cio_usbdev_dn_d2p;
172: logic cio_usbdev_dn_en_d2p;
173:
174:
175: logic [80:0] intr_vector;
176: // Interrupt source list
177: logic intr_uart_tx_watermark;
178: logic intr_uart_rx_watermark;
179: logic intr_uart_tx_empty;
180: logic intr_uart_rx_overflow;
181: logic intr_uart_rx_frame_err;
182: logic intr_uart_rx_break_err;
183: logic intr_uart_rx_timeout;
184: logic intr_uart_rx_parity_err;
185: logic [31:0] intr_gpio_gpio;
186: logic intr_spi_device_rxf;
187: logic intr_spi_device_rxlvl;
188: logic intr_spi_device_txlvl;
189: logic intr_spi_device_rxerr;
190: logic intr_spi_device_rxoverflow;
191: logic intr_spi_device_txunderflow;
192: logic intr_flash_ctrl_prog_empty;
193: logic intr_flash_ctrl_prog_lvl;
194: logic intr_flash_ctrl_rd_full;
195: logic intr_flash_ctrl_rd_lvl;
196: logic intr_flash_ctrl_op_done;
197: logic intr_flash_ctrl_op_error;
198: logic intr_rv_timer_timer_expired_0_0;
199: logic intr_hmac_hmac_done;
200: logic intr_hmac_fifo_empty;
201: logic intr_hmac_hmac_err;
202: logic intr_alert_handler_classa;
203: logic intr_alert_handler_classb;
204: logic intr_alert_handler_classc;
205: logic intr_alert_handler_classd;
206: logic intr_pwrmgr_wakeup;
207: logic intr_nmi_gen_esc0;
208: logic intr_nmi_gen_esc1;
209: logic intr_nmi_gen_esc2;
210: logic intr_nmi_gen_esc3;
211: logic intr_usbdev_pkt_received;
212: logic intr_usbdev_pkt_sent;
213: logic intr_usbdev_disconnected;
214: logic intr_usbdev_host_lost;
215: logic intr_usbdev_link_reset;
216: logic intr_usbdev_link_suspend;
217: logic intr_usbdev_link_resume;
218: logic intr_usbdev_av_empty;
219: logic intr_usbdev_rx_full;
220: logic intr_usbdev_av_overflow;
221: logic intr_usbdev_link_in_err;
222: logic intr_usbdev_rx_crc_err;
223: logic intr_usbdev_rx_pid_err;
224: logic intr_usbdev_rx_bitstuff_err;
225: logic intr_usbdev_frame;
226: logic intr_usbdev_connected;
227:
228:
229:
230: logic [0:0] irq_plic;
231: logic [0:0] msip;
232: logic [6:0] irq_id[1];
233: logic [6:0] unused_irq_id[1];
234:
235: // this avoids lint errors
236: assign unused_irq_id = irq_id;
237:
238: // Alert list
239: prim_alert_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx;
240: prim_alert_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx;
241: // Escalation outputs
242: prim_esc_pkg::esc_tx_t [alert_pkg::N_ESC_SEV-1:0] esc_tx;
243: prim_esc_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0] esc_rx;
244:
245:
246: // define inter-module signals
247: flash_ctrl_pkg::flash_req_t flash_ctrl_flash_req;
248: flash_ctrl_pkg::flash_rsp_t flash_ctrl_flash_rsp;
249: pwrmgr_pkg::pwr_rst_req_t pwrmgr_pwr_rst_req;
250: pwrmgr_pkg::pwr_rst_rsp_t pwrmgr_pwr_rst_rsp;
251: pwrmgr_pkg::pwr_clk_req_t pwrmgr_pwr_clk_req;
252: pwrmgr_pkg::pwr_clk_rsp_t pwrmgr_pwr_clk_rsp;
253: rstmgr_pkg::rstmgr_out_t rstmgr_resets;
254: rstmgr_pkg::rstmgr_cpu_t rstmgr_cpu;
255: pwrmgr_pkg::pwr_cpu_t pwrmgr_pwr_cpu;
256: clkmgr_pkg::clkmgr_out_t clkmgr_clocks;
257:
258: // Non-debug module reset == reset for everything except for the debug module
259: logic ndmreset_req;
260:
261: // debug request from rv_dm to core
262: logic debug_req;
263:
264: // processor core
265: rv_core_ibex #(
266: .PMPEnable (1),
267: .PMPGranularity (0), // 2^(PMPGranularity+2) == 4 byte granularity
268: .PMPNumRegions (16),
269: .MHPMCounterNum (8),
270: .MHPMCounterWidth (40),
271: .RV32E (0),
272: .RV32M (1),
273: .BranchTargetALU (1),
274: .WritebackStage (1),
275: .MultiplierImplementation ("single-cycle"),
276: .ICache (0),
277: .ICacheECC (0),
278: .DbgTriggerEn (1),
279: .SecureIbex (0),
280: .DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
281: .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
282: .PipeLine (IbexPipeLine)
283: ) u_rv_core_ibex (
284: // clock and reset
285: .clk_i (clkmgr_clocks.clk_proc_main),
286: .rst_ni (rstmgr_resets.rst_sys_n),
287: .test_en_i (1'b0),
288: // static pinning
289: .hart_id_i (32'b0),
290: .boot_addr_i (ADDR_SPACE_ROM),
291: // TL-UL buses
292: .tl_i_o (tl_corei_h_h2d),
293: .tl_i_i (tl_corei_h_d2h),
294: .tl_d_o (tl_cored_h_h2d),
295: .tl_d_i (tl_cored_h_d2h),
296: // interrupts
297: .irq_software_i (msip),
298: .irq_timer_i (intr_rv_timer_timer_expired_0_0),
299: .irq_external_i (irq_plic),
300: .irq_fast_i (15'b0),// PLIC handles all peripheral interrupts
301: .irq_nm_i (1'b0),// TODO - add and connect alert responder
302: // debug interface
303: .debug_req_i (debug_req),
304: // CPU control signals
305: .fetch_enable_i (1'b1),
306: .core_sleep_o (pwrmgr_pwr_cpu.core_sleeping)
307: );
308:
309: // Debug Module (RISC-V Debug Spec 0.13)
310: //
311:
312: rv_dm #(
313: .NrHarts (1),
314: .IdcodeValue (JTAG_IDCODE)
315: ) u_dm_top (
316: .clk_i (clkmgr_clocks.clk_proc_main),
317: .rst_ni (rstmgr_resets.rst_lc_n),
318: .testmode_i (1'b0),
319: .ndmreset_o (ndmreset_req),
320: .dmactive_o (),
321: .debug_req_o (debug_req),
322: .unavailable_i (1'b0),
323:
324: // bus device with debug memory (for execution-based debug)
325: .tl_d_i (tl_debug_mem_d_h2d),
326: .tl_d_o (tl_debug_mem_d_d2h),
327:
328: // bus host (for system bus accesses, SBA)
329: .tl_h_o (tl_dm_sba_h_h2d),
330: .tl_h_i (tl_dm_sba_h_d2h),
331:
332: //JTAG
333: .tck_i (jtag_tck_i),
334: .tms_i (jtag_tms_i),
335: .trst_ni (jtag_trst_ni),
336: .td_i (jtag_tdi_i),
337: .td_o (jtag_tdo_o),
338: .tdo_oe_o ( )
339: );
340:
341: assign rstmgr_cpu.ndmreset_req = ndmreset_req;
342: assign rstmgr_cpu.rst_cpu_n = rstmgr_resets.rst_sys_n;
343:
344: // ROM device
345: logic rom_req;
346: logic [11:0] rom_addr;
347: logic [31:0] rom_rdata;
348: logic rom_rvalid;
349:
350: tlul_adapter_sram #(
351: .SramAw(12),
352: .SramDw(32),
353: .Outstanding(2),
354: .ErrOnWrite(1)
355: ) u_tl_adapter_rom (
356: .clk_i (clkmgr_clocks.clk_main_infra),
357: .rst_ni (rstmgr_resets.rst_sys_n),
358:
359: .tl_i (tl_rom_d_h2d),
360: .tl_o (tl_rom_d_d2h),
361:
362: .req_o (rom_req),
363: .gnt_i (1'b1), // Always grant as only one requester exists
364: .we_o (),
365: .addr_o (rom_addr),
366: .wdata_o (),
367: .wmask_o (),
368: .rdata_i (rom_rdata),
369: .rvalid_i (rom_rvalid),
370: .rerror_i (2'b00)
371: );
372:
373: prim_rom_adv #(
374: .Width(32),
375: .Depth(4096),
376: .MemInitFile(BootRomInitFile)
377: ) u_rom_rom (
378: .clk_i (clkmgr_clocks.clk_main_infra),
379: .rst_ni (rstmgr_resets.rst_sys_n),
380: .req_i (rom_req),
381: .addr_i (rom_addr),
382: .rdata_o (rom_rdata),
383: .rvalid_o (rom_rvalid),
384: .cfg_i ('0) // tied off for now
385: );
386:
387: // sram device
388: logic ram_main_req;
389: logic ram_main_we;
390: logic [13:0] ram_main_addr;
391: logic [31:0] ram_main_wdata;
392: logic [31:0] ram_main_wmask;
393: logic [31:0] ram_main_rdata;
394: logic ram_main_rvalid;
395: logic [1:0] ram_main_rerror;
396:
397: tlul_adapter_sram #(
398: .SramAw(14),
399: .SramDw(32),
400: .Outstanding(2)
401: ) u_tl_adapter_ram_main (
402: .clk_i (clkmgr_clocks.clk_main_infra),
403: .rst_ni (rstmgr_resets.rst_sys_n),
404: .tl_i (tl_ram_main_d_h2d),
405: .tl_o (tl_ram_main_d_d2h),
406:
407: .req_o (ram_main_req),
408: .gnt_i (1'b1), // Always grant as only one requester exists
409: .we_o (ram_main_we),
410: .addr_o (ram_main_addr),
411: .wdata_o (ram_main_wdata),
412: .wmask_o (ram_main_wmask),
413: .rdata_i (ram_main_rdata),
414: .rvalid_i (ram_main_rvalid),
415: .rerror_i (ram_main_rerror)
416: );
417:
418: prim_ram_1p_adv #(
419: .Width(32),
420: .Depth(16384),
421: .DataBitsPerMask(8),
422: .CfgW(8),
423: // TODO: enable parity once supported by the simulation infrastructure
424: .EnableParity(0)
425: ) u_ram1p_ram_main (
426: .clk_i (clkmgr_clocks.clk_main_infra),
427: .rst_ni (rstmgr_resets.rst_sys_n),
428:
429: .req_i (ram_main_req),
430: .write_i (ram_main_we),
431: .addr_i (ram_main_addr),
432: .wdata_i (ram_main_wdata),
433: .wmask_i (ram_main_wmask),
434: .rdata_o (ram_main_rdata),
435: .rvalid_o (ram_main_rvalid),
436: .rerror_o (ram_main_rerror),
437: .cfg_i ('0)
438: );
439:
440: // host to flash communication
441: logic flash_host_req;
442: logic flash_host_req_rdy;
443: logic flash_host_req_done;
444: logic [flash_ctrl_pkg::BusWidth-1:0] flash_host_rdata;
445: logic [flash_ctrl_pkg::AddrW-1:0] flash_host_addr;
446:
447: tlul_adapter_sram #(
448: .SramAw(flash_ctrl_pkg::AddrW),
449: .SramDw(flash_ctrl_pkg::BusWidth),
450: .Outstanding(2),
451: .ByteAccess(0),
452: .ErrOnWrite(1)
453: ) u_tl_adapter_eflash (
454: .clk_i (clkmgr_clocks.clk_main_infra),
455: .rst_ni (rstmgr_resets.rst_lc_n),
456:
457: .tl_i (tl_eflash_d_h2d),
458: .tl_o (tl_eflash_d_d2h),
459:
460: .req_o (flash_host_req),
461: .gnt_i (flash_host_req_rdy),
462: .we_o (),
463: .addr_o (flash_host_addr),
464: .wdata_o (),
465: .wmask_o (),
466: .rdata_i (flash_host_rdata),
467: .rvalid_i (flash_host_req_done),
468: .rerror_i (2'b00)
469: );
470:
471: flash_phy u_flash_eflash (
472: .clk_i (clkmgr_clocks.clk_main_infra),
473: .rst_ni (rstmgr_resets.rst_lc_n),
474: .host_req_i (flash_host_req),
475: .host_addr_i (flash_host_addr),
476: .host_req_rdy_o (flash_host_req_rdy),
477: .host_req_done_o (flash_host_req_done),
478: .host_rdata_o (flash_host_rdata),
479: .flash_ctrl_i (flash_ctrl_flash_req),
480: .flash_ctrl_o (flash_ctrl_flash_rsp)
481: );
482:
483:
484:
485: uart u_uart (
486: .tl_i (tl_uart_d_h2d),
487: .tl_o (tl_uart_d_d2h),
488:
489: // Input
490: .cio_rx_i (cio_uart_rx_p2d),
491:
492: // Output
493: .cio_tx_o (cio_uart_tx_d2p),
494: .cio_tx_en_o (cio_uart_tx_en_d2p),
495:
496: // Interrupt
497: .intr_tx_watermark_o (intr_uart_tx_watermark),
498: .intr_rx_watermark_o (intr_uart_rx_watermark),
499: .intr_tx_empty_o (intr_uart_tx_empty),
500: .intr_rx_overflow_o (intr_uart_rx_overflow),
501: .intr_rx_frame_err_o (intr_uart_rx_frame_err),
502: .intr_rx_break_err_o (intr_uart_rx_break_err),
503: .intr_rx_timeout_o (intr_uart_rx_timeout),
504: .intr_rx_parity_err_o (intr_uart_rx_parity_err),
505:
506: .clk_i (clkmgr_clocks.clk_io_secure),
507: .rst_ni (rstmgr_resets.rst_sys_io_n)
508: );
509:
510: gpio u_gpio (
511: .tl_i (tl_gpio_d_h2d),
512: .tl_o (tl_gpio_d_d2h),
513:
514: // Input
515: .cio_gpio_i (cio_gpio_gpio_p2d),
516:
517: // Output
518: .cio_gpio_o (cio_gpio_gpio_d2p),
519: .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
520:
521: // Interrupt
522: .intr_gpio_o (intr_gpio_gpio),
523:
524: .clk_i (clkmgr_clocks.clk_io_peri),
525: .rst_ni (rstmgr_resets.rst_sys_io_n)
526: );
527:
528: spi_device u_spi_device (
529: .tl_i (tl_spi_device_d_h2d),
530: .tl_o (tl_spi_device_d_d2h),
531:
532: // Input
533: .cio_sck_i (cio_spi_device_sck_p2d),
534: .cio_csb_i (cio_spi_device_csb_p2d),
535: .cio_mosi_i (cio_spi_device_mosi_p2d),
536:
537: // Output
538: .cio_miso_o (cio_spi_device_miso_d2p),
539: .cio_miso_en_o (cio_spi_device_miso_en_d2p),
540:
541: // Interrupt
542: .intr_rxf_o (intr_spi_device_rxf),
543: .intr_rxlvl_o (intr_spi_device_rxlvl),
544: .intr_txlvl_o (intr_spi_device_txlvl),
545: .intr_rxerr_o (intr_spi_device_rxerr),
546: .intr_rxoverflow_o (intr_spi_device_rxoverflow),
547: .intr_txunderflow_o (intr_spi_device_txunderflow),
548: .scanmode_i (scanmode_i),
549:
550: .clk_i (clkmgr_clocks.clk_io_peri),
551: .rst_ni (rstmgr_resets.rst_spi_device_n)
552: );
553:
554: flash_ctrl u_flash_ctrl (
555: .tl_i (tl_flash_ctrl_d_h2d),
556: .tl_o (tl_flash_ctrl_d_d2h),
557:
558: // Interrupt
559: .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
560: .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
561: .intr_rd_full_o (intr_flash_ctrl_rd_full),
562: .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
563: .intr_op_done_o (intr_flash_ctrl_op_done),
564: .intr_op_error_o (intr_flash_ctrl_op_error),
565:
566: // Inter-module signals
567: .flash_o(flash_ctrl_flash_req),
568: .flash_i(flash_ctrl_flash_rsp),
569:
570: .clk_i (clkmgr_clocks.clk_main_infra),
571: .rst_ni (rstmgr_resets.rst_lc_n)
572: );
573:
574: rv_timer u_rv_timer (
575: .tl_i (tl_rv_timer_d_h2d),
576: .tl_o (tl_rv_timer_d_d2h),
577:
578: // Interrupt
579: .intr_timer_expired_0_0_o (intr_rv_timer_timer_expired_0_0),
580:
581: .clk_i (clkmgr_clocks.clk_io_timers),
582: .rst_ni (rstmgr_resets.rst_sys_io_n)
583: );
584:
585: aes u_aes (
586: .tl_i (tl_aes_d_h2d),
587: .tl_o (tl_aes_d_d2h),
588:
589: .clk_i (clkmgr_clocks.clk_main_aes),
590: .rst_ni (rstmgr_resets.rst_sys_n)
591: );
592:
593: hmac u_hmac (
594: .tl_i (tl_hmac_d_h2d),
595: .tl_o (tl_hmac_d_d2h),
596:
597: // Interrupt
598: .intr_hmac_done_o (intr_hmac_hmac_done),
599: .intr_fifo_empty_o (intr_hmac_fifo_empty),
600: .intr_hmac_err_o (intr_hmac_hmac_err),
601:
602: // [0]: msg_push_sha_disabled
603: .alert_tx_o ( alert_tx[0:0] ),
604: .alert_rx_i ( alert_rx[0:0] ),
605:
606: .clk_i (clkmgr_clocks.clk_main_hmac),
607: .rst_ni (rstmgr_resets.rst_sys_n)
608: );
609:
610: rv_plic u_rv_plic (
611: .tl_i (tl_rv_plic_d_h2d),
612: .tl_o (tl_rv_plic_d_d2h),
613:
614: .intr_src_i (intr_vector),
615: .irq_o (irq_plic),
616: .irq_id_o (irq_id),
617: .msip_o (msip),
618:
619: .clk_i (clkmgr_clocks.clk_main_secure),
620: .rst_ni (rstmgr_resets.rst_sys_n)
621: );
622:
623: pinmux u_pinmux (
624: .tl_i (tl_pinmux_d_h2d),
625: .tl_o (tl_pinmux_d_d2h),
626:
627: // Inter-module signals
628: .lc_pinmux_strap_i(pinmux_pkg::LC_PINMUX_STRAP_REQ_DEFAULT),
629: .lc_pinmux_strap_o(),
630: .sleep_en_i(1'b0),
631: .aon_wkup_req_o(),
632:
633: .periph_to_mio_i (mio_d2p ),
634: .periph_to_mio_oe_i (mio_d2p_en ),
635: .mio_to_periph_o (mio_p2d ),
636:
637: .mio_out_o,
638: .mio_oe_o,
639: .mio_in_i,
640:
641: .periph_to_dio_i (dio_d2p ),
642: .periph_to_dio_oe_i (dio_d2p_en ),
643: .dio_to_periph_o (dio_p2d ),
644:
645: .dio_out_o,
646: .dio_oe_o,
647: .dio_in_i,
648:
649: .clk_i (clkmgr_clocks.clk_main_secure),
650: .clk_aon_i (clkmgr_clocks.clk_io_secure),
651: .rst_ni (rstmgr_resets.rst_sys_n),
652: .rst_aon_ni (rstmgr_resets.rst_sys_io_n)
653: );
654:
655: padctrl u_padctrl (
656: .tl_i (tl_padctrl_d_h2d),
657: .tl_o (tl_padctrl_d_d2h),
658:
659: .mio_attr_o,
660: .dio_attr_o,
661:
662: .clk_i (clkmgr_clocks.clk_main_secure),
663: .rst_ni (rstmgr_resets.rst_sys_n)
664: );
665:
666: alert_handler u_alert_handler (
667: .tl_i (tl_alert_handler_d_h2d),
668: .tl_o (tl_alert_handler_d_d2h),
669:
670: // Interrupt
671: .intr_classa_o (intr_alert_handler_classa),
672: .intr_classb_o (intr_alert_handler_classb),
673: .intr_classc_o (intr_alert_handler_classc),
674: .intr_classd_o (intr_alert_handler_classd),
675: // TODO: wire this to hardware debug circuit
676: .crashdump_o ( ),
677: // TODO: wire this to TRNG
678: .entropy_i ( 1'b0 ),
679: // alert signals
680: .alert_rx_o ( alert_rx ),
681: .alert_tx_i ( alert_tx ),
682: // escalation outputs
683: .esc_rx_i ( esc_rx ),
684: .esc_tx_o ( esc_tx ),
685:
686: .clk_i (clkmgr_clocks.clk_main_secure),
687: .rst_ni (rstmgr_resets.rst_sys_n)
688: );
689:
690: pwrmgr u_pwrmgr (
691: .tl_i (tl_pwrmgr_d_h2d),
692: .tl_o (tl_pwrmgr_d_d2h),
693:
694: // Interrupt
695: .intr_wakeup_o (intr_pwrmgr_wakeup),
696:
697: // Inter-module signals
698: .pwr_ast_o(),
699: .pwr_ast_i(pwrmgr_pkg::PWR_AST_RSP_DEFAULT),
700: .pwr_rst_o(pwrmgr_pwr_rst_req),
701: .pwr_rst_i(pwrmgr_pwr_rst_rsp),
702: .pwr_clk_o(pwrmgr_pwr_clk_req),
703: .pwr_clk_i(pwrmgr_pwr_clk_rsp),
704: .pwr_otp_o(),
705: .pwr_otp_i(pwrmgr_pkg::PWR_OTP_RSP_DEFAULT),
706: .pwr_lc_o(),
707: .pwr_lc_i(pwrmgr_pkg::PWR_LC_RSP_DEFAULT),
708: .pwr_flash_i(pwrmgr_pkg::PWR_FLASH_DEFAULT),
709: .pwr_cpu_i(pwrmgr_pwr_cpu),
710: .pwr_peri_i(pwrmgr_pkg::PWR_PERI_DEFAULT),
711:
712: .clk_i (clk_io_i),
713: .clk_slow_i (clk_aon_i),
714: .rst_ni (rstmgr_resets.rst_por_n),
715: .rst_slow_ni (rstmgr_resets.rst_por_aon_n)
716: );
717:
718: rstmgr u_rstmgr (
719: .tl_i (tl_rstmgr_d_h2d),
720: .tl_o (tl_rstmgr_d_d2h),
721:
722: // Inter-module signals
723: .pwr_i(pwrmgr_pwr_rst_req),
724: .pwr_o(pwrmgr_pwr_rst_rsp),
725: .resets_o(rstmgr_resets),
726: .ast_i(rstmgr_pkg::RSTMGR_AST_DEFAULT),
727: .cpu_i(rstmgr_cpu),
728: .peri_i(rstmgr_pkg::RSTMGR_PERI_DEFAULT),
729:
730: .clk_i (clk_io_i),
731: .clk_aon_i (clk_aon_i),
732: .clk_main_i (clk_i),
733: .clk_io_i (clk_io_i),
734: .clk_usb_i (clk_usb_i),
735: .rst_ni (rst_ni)
736: );
737:
738: clkmgr u_clkmgr (
739: .tl_i (tl_clkmgr_d_h2d),
740: .tl_o (tl_clkmgr_d_d2h),
741:
742: // Inter-module signals
743: .clocks_o(clkmgr_clocks),
744: .pwr_i(pwrmgr_pwr_clk_req),
745: .pwr_o(pwrmgr_pwr_clk_rsp),
746: .dft_i(clkmgr_pkg::CLK_DFT_DEFAULT),
747: .status_i(clkmgr_pkg::CLK_HINT_STATUS_DEFAULT),
748:
749: .clk_i (clk_io_i),
750: .clk_main_i (clk_i),
751: .clk_io_i (clk_io_i),
752: .clk_usb_i (clk_usb_i),
753: .clk_aon_i (clk_aon_i),
754: .rst_ni (rstmgr_resets.rst_por_io_n),
755: .rst_main_ni (rstmgr_resets.rst_por_n),
756: .rst_io_ni (rstmgr_resets.rst_por_io_n),
757: .rst_usb_ni (rstmgr_resets.rst_por_usb_n)
758: );
759:
760: nmi_gen u_nmi_gen (
761: .tl_i (tl_nmi_gen_d_h2d),
762: .tl_o (tl_nmi_gen_d_d2h),
763:
764: // Interrupt
765: .intr_esc0_o (intr_nmi_gen_esc0),
766: .intr_esc1_o (intr_nmi_gen_esc1),
767: .intr_esc2_o (intr_nmi_gen_esc2),
768: .intr_esc3_o (intr_nmi_gen_esc3),
769: // escalation signal inputs
770: .esc_rx_o ( esc_rx ),
771: .esc_tx_i ( esc_tx ),
772:
773: .clk_i (clkmgr_clocks.clk_main_secure),
774: .rst_ni (rstmgr_resets.rst_sys_n)
775: );
776:
777: usbdev u_usbdev (
778: .tl_i (tl_usbdev_d_h2d),
779: .tl_o (tl_usbdev_d_d2h),
780:
781: // Input
782: .cio_sense_i (cio_usbdev_sense_p2d),
783: .cio_d_i (cio_usbdev_d_p2d),
784: .cio_dp_i (cio_usbdev_dp_p2d),
785: .cio_dn_i (cio_usbdev_dn_p2d),
786:
787: // Output
788: .cio_se0_o (cio_usbdev_se0_d2p),
789: .cio_se0_en_o (cio_usbdev_se0_en_d2p),
790: .cio_dp_pullup_o (cio_usbdev_dp_pullup_d2p),
791: .cio_dp_pullup_en_o (cio_usbdev_dp_pullup_en_d2p),
792: .cio_dn_pullup_o (cio_usbdev_dn_pullup_d2p),
793: .cio_dn_pullup_en_o (cio_usbdev_dn_pullup_en_d2p),
794: .cio_tx_mode_se_o (cio_usbdev_tx_mode_se_d2p),
795: .cio_tx_mode_se_en_o (cio_usbdev_tx_mode_se_en_d2p),
796: .cio_suspend_o (cio_usbdev_suspend_d2p),
797: .cio_suspend_en_o (cio_usbdev_suspend_en_d2p),
798: .cio_d_o (cio_usbdev_d_d2p),
799: .cio_d_en_o (cio_usbdev_d_en_d2p),
800: .cio_dp_o (cio_usbdev_dp_d2p),
801: .cio_dp_en_o (cio_usbdev_dp_en_d2p),
802: .cio_dn_o (cio_usbdev_dn_d2p),
803: .cio_dn_en_o (cio_usbdev_dn_en_d2p),
804:
805: // Interrupt
806: .intr_pkt_received_o (intr_usbdev_pkt_received),
807: .intr_pkt_sent_o (intr_usbdev_pkt_sent),
808: .intr_disconnected_o (intr_usbdev_disconnected),
809: .intr_host_lost_o (intr_usbdev_host_lost),
810: .intr_link_reset_o (intr_usbdev_link_reset),
811: .intr_link_suspend_o (intr_usbdev_link_suspend),
812: .intr_link_resume_o (intr_usbdev_link_resume),
813: .intr_av_empty_o (intr_usbdev_av_empty),
814: .intr_rx_full_o (intr_usbdev_rx_full),
815: .intr_av_overflow_o (intr_usbdev_av_overflow),
816: .intr_link_in_err_o (intr_usbdev_link_in_err),
817: .intr_rx_crc_err_o (intr_usbdev_rx_crc_err),
818: .intr_rx_pid_err_o (intr_usbdev_rx_pid_err),
819: .intr_rx_bitstuff_err_o (intr_usbdev_rx_bitstuff_err),
820: .intr_frame_o (intr_usbdev_frame),
821: .intr_connected_o (intr_usbdev_connected),
822:
823: // Inter-module signals
824: .usb_ref_val_o(),
825: .usb_ref_pulse_o(),
826:
827: .clk_i (clkmgr_clocks.clk_io_peri),
828: .clk_usb_48mhz_i (clkmgr_clocks.clk_usb_peri),
829: .rst_ni (rstmgr_resets.rst_sys_io_n),
830: .rst_usb_48mhz_ni (rstmgr_resets.rst_usb_n)
831: );
832:
833: // interrupt assignments
834: assign intr_vector = {
835: intr_pwrmgr_wakeup,
836: intr_usbdev_connected,
837: intr_usbdev_frame,
838: intr_usbdev_rx_bitstuff_err,
839: intr_usbdev_rx_pid_err,
840: intr_usbdev_rx_crc_err,
841: intr_usbdev_link_in_err,
842: intr_usbdev_av_overflow,
843: intr_usbdev_rx_full,
844: intr_usbdev_av_empty,
845: intr_usbdev_link_resume,
846: intr_usbdev_link_suspend,
847: intr_usbdev_link_reset,
848: intr_usbdev_host_lost,
849: intr_usbdev_disconnected,
850: intr_usbdev_pkt_sent,
851: intr_usbdev_pkt_received,
852: intr_nmi_gen_esc3,
853: intr_nmi_gen_esc2,
854: intr_nmi_gen_esc1,
855: intr_nmi_gen_esc0,
856: intr_alert_handler_classd,
857: intr_alert_handler_classc,
858: intr_alert_handler_classb,
859: intr_alert_handler_classa,
860: intr_hmac_hmac_err,
861: intr_hmac_fifo_empty,
862: intr_hmac_hmac_done,
863: intr_flash_ctrl_op_error,
864: intr_flash_ctrl_op_done,
865: intr_flash_ctrl_rd_lvl,
866: intr_flash_ctrl_rd_full,
867: intr_flash_ctrl_prog_lvl,
868: intr_flash_ctrl_prog_empty,
869: intr_spi_device_txunderflow,
870: intr_spi_device_rxoverflow,
871: intr_spi_device_rxerr,
872: intr_spi_device_txlvl,
873: intr_spi_device_rxlvl,
874: intr_spi_device_rxf,
875: intr_uart_rx_parity_err,
876: intr_uart_rx_timeout,
877: intr_uart_rx_break_err,
878: intr_uart_rx_frame_err,
879: intr_uart_rx_overflow,
880: intr_uart_tx_empty,
881: intr_uart_rx_watermark,
882: intr_uart_tx_watermark,
883: intr_gpio_gpio,
884: 1'b 0 // For ID 0.
885: };
886:
887: // TL-UL Crossbar
888: xbar_main u_xbar_main (
889: .clk_main_i (clkmgr_clocks.clk_main_infra),
890: .clk_fixed_i (clkmgr_clocks.clk_io_infra),
891: .rst_main_ni (rstmgr_resets.rst_sys_n),
892: .rst_fixed_ni (rstmgr_resets.rst_sys_io_n),
893: .tl_corei_i (tl_corei_h_h2d),
894: .tl_corei_o (tl_corei_h_d2h),
895: .tl_cored_i (tl_cored_h_h2d),
896: .tl_cored_o (tl_cored_h_d2h),
897: .tl_dm_sba_i (tl_dm_sba_h_h2d),
898: .tl_dm_sba_o (tl_dm_sba_h_d2h),
899: .tl_rom_o (tl_rom_d_h2d),
900: .tl_rom_i (tl_rom_d_d2h),
901: .tl_debug_mem_o (tl_debug_mem_d_h2d),
902: .tl_debug_mem_i (tl_debug_mem_d_d2h),
903: .tl_ram_main_o (tl_ram_main_d_h2d),
904: .tl_ram_main_i (tl_ram_main_d_d2h),
905: .tl_eflash_o (tl_eflash_d_h2d),
906: .tl_eflash_i (tl_eflash_d_d2h),
907: .tl_peri_o (tl_main_peri_h2d),
908: .tl_peri_i (tl_main_peri_d2h),
909: .tl_flash_ctrl_o (tl_flash_ctrl_d_h2d),
910: .tl_flash_ctrl_i (tl_flash_ctrl_d_d2h),
911: .tl_hmac_o (tl_hmac_d_h2d),
912: .tl_hmac_i (tl_hmac_d_d2h),
913: .tl_aes_o (tl_aes_d_h2d),
914: .tl_aes_i (tl_aes_d_d2h),
915: .tl_rv_plic_o (tl_rv_plic_d_h2d),
916: .tl_rv_plic_i (tl_rv_plic_d_d2h),
917: .tl_pinmux_o (tl_pinmux_d_h2d),
918: .tl_pinmux_i (tl_pinmux_d_d2h),
919: .tl_padctrl_o (tl_padctrl_d_h2d),
920: .tl_padctrl_i (tl_padctrl_d_d2h),
921: .tl_alert_handler_o (tl_alert_handler_d_h2d),
922: .tl_alert_handler_i (tl_alert_handler_d_d2h),
923: .tl_nmi_gen_o (tl_nmi_gen_d_h2d),
924: .tl_nmi_gen_i (tl_nmi_gen_d_d2h),
925:
926: .scanmode_i
927: );
928: xbar_peri u_xbar_peri (
929: .clk_peri_i (clkmgr_clocks.clk_io_infra),
930: .rst_peri_ni (rstmgr_resets.rst_sys_io_n),
931: .tl_main_i (tl_main_peri_h2d),
932: .tl_main_o (tl_main_peri_d2h),
933: .tl_uart_o (tl_uart_d_h2d),
934: .tl_uart_i (tl_uart_d_d2h),
935: .tl_gpio_o (tl_gpio_d_h2d),
936: .tl_gpio_i (tl_gpio_d_d2h),
937: .tl_spi_device_o (tl_spi_device_d_h2d),
938: .tl_spi_device_i (tl_spi_device_d_d2h),
939: .tl_rv_timer_o (tl_rv_timer_d_h2d),
940: .tl_rv_timer_i (tl_rv_timer_d_d2h),
941: .tl_usbdev_o (tl_usbdev_d_h2d),
942: .tl_usbdev_i (tl_usbdev_d_d2h),
943: .tl_pwrmgr_o (tl_pwrmgr_d_h2d),
944: .tl_pwrmgr_i (tl_pwrmgr_d_d2h),
945: .tl_rstmgr_o (tl_rstmgr_d_h2d),
946: .tl_rstmgr_i (tl_rstmgr_d_d2h),
947: .tl_clkmgr_o (tl_clkmgr_d_h2d),
948: .tl_clkmgr_i (tl_clkmgr_d_d2h),
949:
950: .scanmode_i
951: );
952:
953: // Pinmux connections
954: assign mio_d2p = {
955: cio_gpio_gpio_d2p
956: };
957: assign mio_d2p_en = {
958: cio_gpio_gpio_en_d2p
959: };
960: assign {
961: cio_gpio_gpio_p2d
962: } = mio_p2d;
963:
964: // Dedicated IO connections
965: // Input-only DIOs have no d2p signals
966: assign dio_d2p = {
967: 1'b0, // DIO14: cio_spi_device_sck
968: 1'b0, // DIO13: cio_spi_device_csb
969: 1'b0, // DIO12: cio_spi_device_mosi
970: cio_spi_device_miso_d2p, // DIO11
971: 1'b0, // DIO10: cio_uart_rx
972: cio_uart_tx_d2p, // DIO9
973: 1'b0, // DIO8: cio_usbdev_sense
974: cio_usbdev_se0_d2p, // DIO7
975: cio_usbdev_dp_pullup_d2p, // DIO6
976: cio_usbdev_dn_pullup_d2p, // DIO5
977: cio_usbdev_tx_mode_se_d2p, // DIO4
978: cio_usbdev_suspend_d2p, // DIO3
979: cio_usbdev_d_d2p, // DIO2
980: cio_usbdev_dp_d2p, // DIO1
981: cio_usbdev_dn_d2p // DIO0
982: };
983:
984: assign dio_d2p_en = {
985: 1'b0, // DIO14: cio_spi_device_sck
986: 1'b0, // DIO13: cio_spi_device_csb
987: 1'b0, // DIO12: cio_spi_device_mosi
988: cio_spi_device_miso_en_d2p, // DIO11
989: 1'b0, // DIO10: cio_uart_rx
990: cio_uart_tx_en_d2p, // DIO9
991: 1'b0, // DIO8: cio_usbdev_sense
992: cio_usbdev_se0_en_d2p, // DIO7
993: cio_usbdev_dp_pullup_en_d2p, // DIO6
994: cio_usbdev_dn_pullup_en_d2p, // DIO5
995: cio_usbdev_tx_mode_se_en_d2p, // DIO4
996: cio_usbdev_suspend_en_d2p, // DIO3
997: cio_usbdev_d_en_d2p, // DIO2
998: cio_usbdev_dp_en_d2p, // DIO1
999: cio_usbdev_dn_en_d2p // DIO0
1000: };
1001:
1002: // Output-only DIOs have no p2d signal
1003: assign cio_spi_device_sck_p2d = dio_p2d[14]; // DIO14
1004: assign cio_spi_device_csb_p2d = dio_p2d[13]; // DIO13
1005: assign cio_spi_device_mosi_p2d = dio_p2d[12]; // DIO12
1006: // DIO11: cio_spi_device_miso
1007: assign cio_uart_rx_p2d = dio_p2d[10]; // DIO10
1008: // DIO9: cio_uart_tx
1009: assign cio_usbdev_sense_p2d = dio_p2d[8]; // DIO8
1010: // DIO7: cio_usbdev_se0
1011: // DIO6: cio_usbdev_dp_pullup
1012: // DIO5: cio_usbdev_dn_pullup
1013: // DIO4: cio_usbdev_tx_mode_se
1014: // DIO3: cio_usbdev_suspend
1015: assign cio_usbdev_d_p2d = dio_p2d[2]; // DIO2
1016: assign cio_usbdev_dp_p2d = dio_p2d[1]; // DIO1
1017: assign cio_usbdev_dn_p2d = dio_p2d[0]; // DIO0
1018:
1019: // make sure scanmode_i is never X (including during reset)
1020: `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
1021:
1022: endmodule
1023: