../src/lowrisc_prim_ram_2p_adv_0.1/rtl/prim_ram_2p_adv.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Dual-Port SRAM Wrapper
   6: //
   7: // Supported configurations:
   8: // - ECC for 32b wide memories with no write mask
   9: //   (Width == 32 && DataBitsPerMask == 32).
  10: // - Byte parity if Width is a multiple of 8 bit and write masks have Byte
  11: //   granularity (DataBitsPerMask == 8).
  12: //
  13: // Note that the write mask needs to be per Byte if parity is enabled. If ECC is enabled, the write
  14: // mask cannot be used and has to be tied to {Width{1'b1}}.
  15: 
  16: `include "prim_assert.sv"
  17: `include "prim_util.svh"
  18: 
  19: module prim_ram_2p_adv #(
  20:   parameter  int Depth                = 512,
  21:   parameter  int Width                = 32,
  22:   parameter  int DataBitsPerMask      = 1,  // Number of data bits per bit of write mask
  23:   parameter  int CfgW                 = 8,  // WTC, RTC, etc
  24:   parameter      MemInitFile          = "", // VMEM file to initialize the memory with
  25: 
  26:   // Configurations
  27:   parameter  bit EnableECC            = 0, // Enables per-word ECC
  28:   parameter  bit EnableParity         = 0, // Enables per-Byte Parity
  29:   parameter  bit EnableInputPipeline  = 0, // Adds an input register (read latency +1)
  30:   parameter  bit EnableOutputPipeline = 0, // Adds an output register (read latency +1)
  31: 
  32:   localparam int Aw                   = vbits(Depth)
  33: ) (
  34:   input                    clk_i,
  35:   input                    rst_ni,
  36: 
  37:   input                    a_req_i,
  38:   input                    a_write_i,
  39:   input        [Aw-1:0]    a_addr_i,
  40:   input        [Width-1:0] a_wdata_i,
  41:   input        [Width-1:0] a_wmask_i,  // cannot be used with ECC, tie to 1 in that case
  42:   output logic [Width-1:0] a_rdata_o,
  43:   output logic             a_rvalid_o, // read response (a_rdata_o) is valid
  44:   output logic [1:0]       a_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
  45: 
  46:   input                    b_req_i,
  47:   input                    b_write_i,
  48:   input        [Aw-1:0]    b_addr_i,
  49:   input        [Width-1:0] b_wdata_i,
  50:   input        [Width-1:0] b_wmask_i,  // cannot be used with ECC, tie to 1 in that case
  51:   output logic [Width-1:0] b_rdata_o,
  52:   output logic             b_rvalid_o, // read response (b_rdata_o) is valid
  53:   output logic [1:0]       b_rerror_o, // Bit1: Uncorrectable, Bit0: Correctable
  54: 
  55:   input        [CfgW-1:0]  cfg_i
  56: );
  57: 
  58:   prim_ram_2p_async_adv #(
  59:     .Depth               (Depth),
  60:     .Width               (Width),
  61:     .DataBitsPerMask     (DataBitsPerMask),
  62:     .CfgW                (CfgW),
  63:     .MemInitFile         (MemInitFile),
  64:     .EnableECC           (EnableECC),
  65:     .EnableParity        (EnableParity),
  66:     .EnableInputPipeline (EnableInputPipeline),
  67:     .EnableOutputPipeline(EnableOutputPipeline)
  68:   ) i_prim_ram_2p_async_adv (
  69:     .clk_a_i(clk_i),
  70:     .rst_a_ni(rst_ni),
  71:     .clk_b_i(clk_i),
  72:     .rst_b_ni(rst_ni),
  73:     .a_req_i,
  74:     .a_write_i,
  75:     .a_addr_i,
  76:     .a_wdata_i,
  77:     .a_wmask_i,
  78:     .a_rdata_o,
  79:     .a_rvalid_o,
  80:     .a_rerror_o,
  81:     .b_req_i,
  82:     .b_write_i,
  83:     .b_addr_i,
  84:     .b_wdata_i,
  85:     .b_wmask_i,
  86:     .b_rdata_o,
  87:     .b_rvalid_o,
  88:     .b_rerror_o,
  89:     .cfg_i
  90:   );
  91: 
  92: endmodule : prim_ram_2p_adv
  93: