../src/lowrisc_top_earlgrey_alert_handler_reg_0.1/rtl/autogen/alert_handler_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module alert_handler_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16: // To HW
17: output alert_handler_reg_pkg::alert_handler_reg2hw_t reg2hw, // Write
18: input alert_handler_reg_pkg::alert_handler_hw2reg_t hw2reg, // Read
19:
20: // Config
21: input devmode_i // If 1, explicit error return for unmapped register access
22: );
23:
24: import alert_handler_reg_pkg::* ;
25:
26: localparam int AW = 8;
27: localparam int DW = 32;
28: localparam int DBW = DW/8; // Byte Width
29:
30: // register signals
31: logic reg_we;
32: logic reg_re;
33: logic [AW-1:0] reg_addr;
34: logic [DW-1:0] reg_wdata;
35: logic [DBW-1:0] reg_be;
36: logic [DW-1:0] reg_rdata;
37: logic reg_error;
38:
39: logic addrmiss, wr_err;
40:
41: logic [DW-1:0] reg_rdata_next;
42:
43: tlul_pkg::tl_h2d_t tl_reg_h2d;
44: tlul_pkg::tl_d2h_t tl_reg_d2h;
45:
46: assign tl_reg_h2d = tl_i;
47: assign tl_o = tl_reg_d2h;
48:
49: tlul_adapter_reg #(
50: .RegAw(AW),
51: .RegDw(DW)
52: ) u_reg_if (
53: .clk_i,
54: .rst_ni,
55:
56: .tl_i (tl_reg_h2d),
57: .tl_o (tl_reg_d2h),
58:
59: .we_o (reg_we),
60: .re_o (reg_re),
61: .addr_o (reg_addr),
62: .wdata_o (reg_wdata),
63: .be_o (reg_be),
64: .rdata_i (reg_rdata),
65: .error_i (reg_error)
66: );
67:
68: assign reg_rdata = reg_rdata_next ;
69: assign reg_error = (devmode_i & addrmiss) | wr_err ;
70:
71: // Define SW related signals
72: // Format: __{wd|we|qs}
73: // or _{wd|we|qs} if field == 1 or 0
74: logic intr_state_classa_qs;
75: logic intr_state_classa_wd;
76: logic intr_state_classa_we;
77: logic intr_state_classb_qs;
78: logic intr_state_classb_wd;
79: logic intr_state_classb_we;
80: logic intr_state_classc_qs;
81: logic intr_state_classc_wd;
82: logic intr_state_classc_we;
83: logic intr_state_classd_qs;
84: logic intr_state_classd_wd;
85: logic intr_state_classd_we;
86: logic intr_enable_classa_qs;
87: logic intr_enable_classa_wd;
88: logic intr_enable_classa_we;
89: logic intr_enable_classb_qs;
90: logic intr_enable_classb_wd;
91: logic intr_enable_classb_we;
92: logic intr_enable_classc_qs;
93: logic intr_enable_classc_wd;
94: logic intr_enable_classc_we;
95: logic intr_enable_classd_qs;
96: logic intr_enable_classd_wd;
97: logic intr_enable_classd_we;
98: logic intr_test_classa_wd;
99: logic intr_test_classa_we;
100: logic intr_test_classb_wd;
101: logic intr_test_classb_we;
102: logic intr_test_classc_wd;
103: logic intr_test_classc_we;
104: logic intr_test_classd_wd;
105: logic intr_test_classd_we;
106: logic regen_qs;
107: logic regen_wd;
108: logic regen_we;
109: logic [23:0] ping_timeout_cyc_qs;
110: logic [23:0] ping_timeout_cyc_wd;
111: logic ping_timeout_cyc_we;
112: logic alert_en_qs;
113: logic alert_en_wd;
114: logic alert_en_we;
115: logic [1:0] alert_class_qs;
116: logic [1:0] alert_class_wd;
117: logic alert_class_we;
118: logic alert_cause_qs;
119: logic alert_cause_wd;
120: logic alert_cause_we;
121: logic loc_alert_en_en_la0_qs;
122: logic loc_alert_en_en_la0_wd;
123: logic loc_alert_en_en_la0_we;
124: logic loc_alert_en_en_la1_qs;
125: logic loc_alert_en_en_la1_wd;
126: logic loc_alert_en_en_la1_we;
127: logic loc_alert_en_en_la2_qs;
128: logic loc_alert_en_en_la2_wd;
129: logic loc_alert_en_en_la2_we;
130: logic loc_alert_en_en_la3_qs;
131: logic loc_alert_en_en_la3_wd;
132: logic loc_alert_en_en_la3_we;
133: logic [1:0] loc_alert_class_class_la0_qs;
134: logic [1:0] loc_alert_class_class_la0_wd;
135: logic loc_alert_class_class_la0_we;
136: logic [1:0] loc_alert_class_class_la1_qs;
137: logic [1:0] loc_alert_class_class_la1_wd;
138: logic loc_alert_class_class_la1_we;
139: logic [1:0] loc_alert_class_class_la2_qs;
140: logic [1:0] loc_alert_class_class_la2_wd;
141: logic loc_alert_class_class_la2_we;
142: logic [1:0] loc_alert_class_class_la3_qs;
143: logic [1:0] loc_alert_class_class_la3_wd;
144: logic loc_alert_class_class_la3_we;
145: logic loc_alert_cause_la0_qs;
146: logic loc_alert_cause_la0_wd;
147: logic loc_alert_cause_la0_we;
148: logic loc_alert_cause_la1_qs;
149: logic loc_alert_cause_la1_wd;
150: logic loc_alert_cause_la1_we;
151: logic loc_alert_cause_la2_qs;
152: logic loc_alert_cause_la2_wd;
153: logic loc_alert_cause_la2_we;
154: logic loc_alert_cause_la3_qs;
155: logic loc_alert_cause_la3_wd;
156: logic loc_alert_cause_la3_we;
157: logic classa_ctrl_en_qs;
158: logic classa_ctrl_en_wd;
159: logic classa_ctrl_en_we;
160: logic classa_ctrl_lock_qs;
161: logic classa_ctrl_lock_wd;
162: logic classa_ctrl_lock_we;
163: logic classa_ctrl_en_e0_qs;
164: logic classa_ctrl_en_e0_wd;
165: logic classa_ctrl_en_e0_we;
166: logic classa_ctrl_en_e1_qs;
167: logic classa_ctrl_en_e1_wd;
168: logic classa_ctrl_en_e1_we;
169: logic classa_ctrl_en_e2_qs;
170: logic classa_ctrl_en_e2_wd;
171: logic classa_ctrl_en_e2_we;
172: logic classa_ctrl_en_e3_qs;
173: logic classa_ctrl_en_e3_wd;
174: logic classa_ctrl_en_e3_we;
175: logic [1:0] classa_ctrl_map_e0_qs;
176: logic [1:0] classa_ctrl_map_e0_wd;
177: logic classa_ctrl_map_e0_we;
178: logic [1:0] classa_ctrl_map_e1_qs;
179: logic [1:0] classa_ctrl_map_e1_wd;
180: logic classa_ctrl_map_e1_we;
181: logic [1:0] classa_ctrl_map_e2_qs;
182: logic [1:0] classa_ctrl_map_e2_wd;
183: logic classa_ctrl_map_e2_we;
184: logic [1:0] classa_ctrl_map_e3_qs;
185: logic [1:0] classa_ctrl_map_e3_wd;
186: logic classa_ctrl_map_e3_we;
187: logic classa_clren_qs;
188: logic classa_clren_wd;
189: logic classa_clren_we;
190: logic classa_clr_wd;
191: logic classa_clr_we;
192: logic [15:0] classa_accum_cnt_qs;
193: logic classa_accum_cnt_re;
194: logic [15:0] classa_accum_thresh_qs;
195: logic [15:0] classa_accum_thresh_wd;
196: logic classa_accum_thresh_we;
197: logic [31:0] classa_timeout_cyc_qs;
198: logic [31:0] classa_timeout_cyc_wd;
199: logic classa_timeout_cyc_we;
200: logic [31:0] classa_phase0_cyc_qs;
201: logic [31:0] classa_phase0_cyc_wd;
202: logic classa_phase0_cyc_we;
203: logic [31:0] classa_phase1_cyc_qs;
204: logic [31:0] classa_phase1_cyc_wd;
205: logic classa_phase1_cyc_we;
206: logic [31:0] classa_phase2_cyc_qs;
207: logic [31:0] classa_phase2_cyc_wd;
208: logic classa_phase2_cyc_we;
209: logic [31:0] classa_phase3_cyc_qs;
210: logic [31:0] classa_phase3_cyc_wd;
211: logic classa_phase3_cyc_we;
212: logic [31:0] classa_esc_cnt_qs;
213: logic classa_esc_cnt_re;
214: logic [2:0] classa_state_qs;
215: logic classa_state_re;
216: logic classb_ctrl_en_qs;
217: logic classb_ctrl_en_wd;
218: logic classb_ctrl_en_we;
219: logic classb_ctrl_lock_qs;
220: logic classb_ctrl_lock_wd;
221: logic classb_ctrl_lock_we;
222: logic classb_ctrl_en_e0_qs;
223: logic classb_ctrl_en_e0_wd;
224: logic classb_ctrl_en_e0_we;
225: logic classb_ctrl_en_e1_qs;
226: logic classb_ctrl_en_e1_wd;
227: logic classb_ctrl_en_e1_we;
228: logic classb_ctrl_en_e2_qs;
229: logic classb_ctrl_en_e2_wd;
230: logic classb_ctrl_en_e2_we;
231: logic classb_ctrl_en_e3_qs;
232: logic classb_ctrl_en_e3_wd;
233: logic classb_ctrl_en_e3_we;
234: logic [1:0] classb_ctrl_map_e0_qs;
235: logic [1:0] classb_ctrl_map_e0_wd;
236: logic classb_ctrl_map_e0_we;
237: logic [1:0] classb_ctrl_map_e1_qs;
238: logic [1:0] classb_ctrl_map_e1_wd;
239: logic classb_ctrl_map_e1_we;
240: logic [1:0] classb_ctrl_map_e2_qs;
241: logic [1:0] classb_ctrl_map_e2_wd;
242: logic classb_ctrl_map_e2_we;
243: logic [1:0] classb_ctrl_map_e3_qs;
244: logic [1:0] classb_ctrl_map_e3_wd;
245: logic classb_ctrl_map_e3_we;
246: logic classb_clren_qs;
247: logic classb_clren_wd;
248: logic classb_clren_we;
249: logic classb_clr_wd;
250: logic classb_clr_we;
251: logic [15:0] classb_accum_cnt_qs;
252: logic classb_accum_cnt_re;
253: logic [15:0] classb_accum_thresh_qs;
254: logic [15:0] classb_accum_thresh_wd;
255: logic classb_accum_thresh_we;
256: logic [31:0] classb_timeout_cyc_qs;
257: logic [31:0] classb_timeout_cyc_wd;
258: logic classb_timeout_cyc_we;
259: logic [31:0] classb_phase0_cyc_qs;
260: logic [31:0] classb_phase0_cyc_wd;
261: logic classb_phase0_cyc_we;
262: logic [31:0] classb_phase1_cyc_qs;
263: logic [31:0] classb_phase1_cyc_wd;
264: logic classb_phase1_cyc_we;
265: logic [31:0] classb_phase2_cyc_qs;
266: logic [31:0] classb_phase2_cyc_wd;
267: logic classb_phase2_cyc_we;
268: logic [31:0] classb_phase3_cyc_qs;
269: logic [31:0] classb_phase3_cyc_wd;
270: logic classb_phase3_cyc_we;
271: logic [31:0] classb_esc_cnt_qs;
272: logic classb_esc_cnt_re;
273: logic [2:0] classb_state_qs;
274: logic classb_state_re;
275: logic classc_ctrl_en_qs;
276: logic classc_ctrl_en_wd;
277: logic classc_ctrl_en_we;
278: logic classc_ctrl_lock_qs;
279: logic classc_ctrl_lock_wd;
280: logic classc_ctrl_lock_we;
281: logic classc_ctrl_en_e0_qs;
282: logic classc_ctrl_en_e0_wd;
283: logic classc_ctrl_en_e0_we;
284: logic classc_ctrl_en_e1_qs;
285: logic classc_ctrl_en_e1_wd;
286: logic classc_ctrl_en_e1_we;
287: logic classc_ctrl_en_e2_qs;
288: logic classc_ctrl_en_e2_wd;
289: logic classc_ctrl_en_e2_we;
290: logic classc_ctrl_en_e3_qs;
291: logic classc_ctrl_en_e3_wd;
292: logic classc_ctrl_en_e3_we;
293: logic [1:0] classc_ctrl_map_e0_qs;
294: logic [1:0] classc_ctrl_map_e0_wd;
295: logic classc_ctrl_map_e0_we;
296: logic [1:0] classc_ctrl_map_e1_qs;
297: logic [1:0] classc_ctrl_map_e1_wd;
298: logic classc_ctrl_map_e1_we;
299: logic [1:0] classc_ctrl_map_e2_qs;
300: logic [1:0] classc_ctrl_map_e2_wd;
301: logic classc_ctrl_map_e2_we;
302: logic [1:0] classc_ctrl_map_e3_qs;
303: logic [1:0] classc_ctrl_map_e3_wd;
304: logic classc_ctrl_map_e3_we;
305: logic classc_clren_qs;
306: logic classc_clren_wd;
307: logic classc_clren_we;
308: logic classc_clr_wd;
309: logic classc_clr_we;
310: logic [15:0] classc_accum_cnt_qs;
311: logic classc_accum_cnt_re;
312: logic [15:0] classc_accum_thresh_qs;
313: logic [15:0] classc_accum_thresh_wd;
314: logic classc_accum_thresh_we;
315: logic [31:0] classc_timeout_cyc_qs;
316: logic [31:0] classc_timeout_cyc_wd;
317: logic classc_timeout_cyc_we;
318: logic [31:0] classc_phase0_cyc_qs;
319: logic [31:0] classc_phase0_cyc_wd;
320: logic classc_phase0_cyc_we;
321: logic [31:0] classc_phase1_cyc_qs;
322: logic [31:0] classc_phase1_cyc_wd;
323: logic classc_phase1_cyc_we;
324: logic [31:0] classc_phase2_cyc_qs;
325: logic [31:0] classc_phase2_cyc_wd;
326: logic classc_phase2_cyc_we;
327: logic [31:0] classc_phase3_cyc_qs;
328: logic [31:0] classc_phase3_cyc_wd;
329: logic classc_phase3_cyc_we;
330: logic [31:0] classc_esc_cnt_qs;
331: logic classc_esc_cnt_re;
332: logic [2:0] classc_state_qs;
333: logic classc_state_re;
334: logic classd_ctrl_en_qs;
335: logic classd_ctrl_en_wd;
336: logic classd_ctrl_en_we;
337: logic classd_ctrl_lock_qs;
338: logic classd_ctrl_lock_wd;
339: logic classd_ctrl_lock_we;
340: logic classd_ctrl_en_e0_qs;
341: logic classd_ctrl_en_e0_wd;
342: logic classd_ctrl_en_e0_we;
343: logic classd_ctrl_en_e1_qs;
344: logic classd_ctrl_en_e1_wd;
345: logic classd_ctrl_en_e1_we;
346: logic classd_ctrl_en_e2_qs;
347: logic classd_ctrl_en_e2_wd;
348: logic classd_ctrl_en_e2_we;
349: logic classd_ctrl_en_e3_qs;
350: logic classd_ctrl_en_e3_wd;
351: logic classd_ctrl_en_e3_we;
352: logic [1:0] classd_ctrl_map_e0_qs;
353: logic [1:0] classd_ctrl_map_e0_wd;
354: logic classd_ctrl_map_e0_we;
355: logic [1:0] classd_ctrl_map_e1_qs;
356: logic [1:0] classd_ctrl_map_e1_wd;
357: logic classd_ctrl_map_e1_we;
358: logic [1:0] classd_ctrl_map_e2_qs;
359: logic [1:0] classd_ctrl_map_e2_wd;
360: logic classd_ctrl_map_e2_we;
361: logic [1:0] classd_ctrl_map_e3_qs;
362: logic [1:0] classd_ctrl_map_e3_wd;
363: logic classd_ctrl_map_e3_we;
364: logic classd_clren_qs;
365: logic classd_clren_wd;
366: logic classd_clren_we;
367: logic classd_clr_wd;
368: logic classd_clr_we;
369: logic [15:0] classd_accum_cnt_qs;
370: logic classd_accum_cnt_re;
371: logic [15:0] classd_accum_thresh_qs;
372: logic [15:0] classd_accum_thresh_wd;
373: logic classd_accum_thresh_we;
374: logic [31:0] classd_timeout_cyc_qs;
375: logic [31:0] classd_timeout_cyc_wd;
376: logic classd_timeout_cyc_we;
377: logic [31:0] classd_phase0_cyc_qs;
378: logic [31:0] classd_phase0_cyc_wd;
379: logic classd_phase0_cyc_we;
380: logic [31:0] classd_phase1_cyc_qs;
381: logic [31:0] classd_phase1_cyc_wd;
382: logic classd_phase1_cyc_we;
383: logic [31:0] classd_phase2_cyc_qs;
384: logic [31:0] classd_phase2_cyc_wd;
385: logic classd_phase2_cyc_we;
386: logic [31:0] classd_phase3_cyc_qs;
387: logic [31:0] classd_phase3_cyc_wd;
388: logic classd_phase3_cyc_we;
389: logic [31:0] classd_esc_cnt_qs;
390: logic classd_esc_cnt_re;
391: logic [2:0] classd_state_qs;
392: logic classd_state_re;
393:
394: // Register instances
395: // R[intr_state]: V(False)
396:
397: // F[classa]: 0:0
398: prim_subreg #(
399: .DW (1),
400: .SWACCESS("W1C"),
401: .RESVAL (1'h0)
402: ) u_intr_state_classa (
403: .clk_i (clk_i ),
404: .rst_ni (rst_ni ),
405:
406: // from register interface
407: .we (intr_state_classa_we),
408: .wd (intr_state_classa_wd),
409:
410: // from internal hardware
411: .de (hw2reg.intr_state.classa.de),
412: .d (hw2reg.intr_state.classa.d ),
413:
414: // to internal hardware
415: .qe (),
416: .q (reg2hw.intr_state.classa.q ),
417:
418: // to register interface (read)
419: .qs (intr_state_classa_qs)
420: );
421:
422:
423: // F[classb]: 1:1
424: prim_subreg #(
425: .DW (1),
426: .SWACCESS("W1C"),
427: .RESVAL (1'h0)
428: ) u_intr_state_classb (
429: .clk_i (clk_i ),
430: .rst_ni (rst_ni ),
431:
432: // from register interface
433: .we (intr_state_classb_we),
434: .wd (intr_state_classb_wd),
435:
436: // from internal hardware
437: .de (hw2reg.intr_state.classb.de),
438: .d (hw2reg.intr_state.classb.d ),
439:
440: // to internal hardware
441: .qe (),
442: .q (reg2hw.intr_state.classb.q ),
443:
444: // to register interface (read)
445: .qs (intr_state_classb_qs)
446: );
447:
448:
449: // F[classc]: 2:2
450: prim_subreg #(
451: .DW (1),
452: .SWACCESS("W1C"),
453: .RESVAL (1'h0)
454: ) u_intr_state_classc (
455: .clk_i (clk_i ),
456: .rst_ni (rst_ni ),
457:
458: // from register interface
459: .we (intr_state_classc_we),
460: .wd (intr_state_classc_wd),
461:
462: // from internal hardware
463: .de (hw2reg.intr_state.classc.de),
464: .d (hw2reg.intr_state.classc.d ),
465:
466: // to internal hardware
467: .qe (),
468: .q (reg2hw.intr_state.classc.q ),
469:
470: // to register interface (read)
471: .qs (intr_state_classc_qs)
472: );
473:
474:
475: // F[classd]: 3:3
476: prim_subreg #(
477: .DW (1),
478: .SWACCESS("W1C"),
479: .RESVAL (1'h0)
480: ) u_intr_state_classd (
481: .clk_i (clk_i ),
482: .rst_ni (rst_ni ),
483:
484: // from register interface
485: .we (intr_state_classd_we),
486: .wd (intr_state_classd_wd),
487:
488: // from internal hardware
489: .de (hw2reg.intr_state.classd.de),
490: .d (hw2reg.intr_state.classd.d ),
491:
492: // to internal hardware
493: .qe (),
494: .q (reg2hw.intr_state.classd.q ),
495:
496: // to register interface (read)
497: .qs (intr_state_classd_qs)
498: );
499:
500:
501: // R[intr_enable]: V(False)
502:
503: // F[classa]: 0:0
504: prim_subreg #(
505: .DW (1),
506: .SWACCESS("RW"),
507: .RESVAL (1'h0)
508: ) u_intr_enable_classa (
509: .clk_i (clk_i ),
510: .rst_ni (rst_ni ),
511:
512: // from register interface
513: .we (intr_enable_classa_we),
514: .wd (intr_enable_classa_wd),
515:
516: // from internal hardware
517: .de (1'b0),
518: .d ('0 ),
519:
520: // to internal hardware
521: .qe (),
522: .q (reg2hw.intr_enable.classa.q ),
523:
524: // to register interface (read)
525: .qs (intr_enable_classa_qs)
526: );
527:
528:
529: // F[classb]: 1:1
530: prim_subreg #(
531: .DW (1),
532: .SWACCESS("RW"),
533: .RESVAL (1'h0)
534: ) u_intr_enable_classb (
535: .clk_i (clk_i ),
536: .rst_ni (rst_ni ),
537:
538: // from register interface
539: .we (intr_enable_classb_we),
540: .wd (intr_enable_classb_wd),
541:
542: // from internal hardware
543: .de (1'b0),
544: .d ('0 ),
545:
546: // to internal hardware
547: .qe (),
548: .q (reg2hw.intr_enable.classb.q ),
549:
550: // to register interface (read)
551: .qs (intr_enable_classb_qs)
552: );
553:
554:
555: // F[classc]: 2:2
556: prim_subreg #(
557: .DW (1),
558: .SWACCESS("RW"),
559: .RESVAL (1'h0)
560: ) u_intr_enable_classc (
561: .clk_i (clk_i ),
562: .rst_ni (rst_ni ),
563:
564: // from register interface
565: .we (intr_enable_classc_we),
566: .wd (intr_enable_classc_wd),
567:
568: // from internal hardware
569: .de (1'b0),
570: .d ('0 ),
571:
572: // to internal hardware
573: .qe (),
574: .q (reg2hw.intr_enable.classc.q ),
575:
576: // to register interface (read)
577: .qs (intr_enable_classc_qs)
578: );
579:
580:
581: // F[classd]: 3:3
582: prim_subreg #(
583: .DW (1),
584: .SWACCESS("RW"),
585: .RESVAL (1'h0)
586: ) u_intr_enable_classd (
587: .clk_i (clk_i ),
588: .rst_ni (rst_ni ),
589:
590: // from register interface
591: .we (intr_enable_classd_we),
592: .wd (intr_enable_classd_wd),
593:
594: // from internal hardware
595: .de (1'b0),
596: .d ('0 ),
597:
598: // to internal hardware
599: .qe (),
600: .q (reg2hw.intr_enable.classd.q ),
601:
602: // to register interface (read)
603: .qs (intr_enable_classd_qs)
604: );
605:
606:
607: // R[intr_test]: V(True)
608:
609: // F[classa]: 0:0
610: prim_subreg_ext #(
611: .DW (1)
612: ) u_intr_test_classa (
613: .re (1'b0),
614: .we (intr_test_classa_we),
615: .wd (intr_test_classa_wd),
616: .d ('0),
617: .qre (),
618: .qe (reg2hw.intr_test.classa.qe),
619: .q (reg2hw.intr_test.classa.q ),
620: .qs ()
621: );
622:
623:
624: // F[classb]: 1:1
625: prim_subreg_ext #(
626: .DW (1)
627: ) u_intr_test_classb (
628: .re (1'b0),
629: .we (intr_test_classb_we),
630: .wd (intr_test_classb_wd),
631: .d ('0),
632: .qre (),
633: .qe (reg2hw.intr_test.classb.qe),
634: .q (reg2hw.intr_test.classb.q ),
635: .qs ()
636: );
637:
638:
639: // F[classc]: 2:2
640: prim_subreg_ext #(
641: .DW (1)
642: ) u_intr_test_classc (
643: .re (1'b0),
644: .we (intr_test_classc_we),
645: .wd (intr_test_classc_wd),
646: .d ('0),
647: .qre (),
648: .qe (reg2hw.intr_test.classc.qe),
649: .q (reg2hw.intr_test.classc.q ),
650: .qs ()
651: );
652:
653:
654: // F[classd]: 3:3
655: prim_subreg_ext #(
656: .DW (1)
657: ) u_intr_test_classd (
658: .re (1'b0),
659: .we (intr_test_classd_we),
660: .wd (intr_test_classd_wd),
661: .d ('0),
662: .qre (),
663: .qe (reg2hw.intr_test.classd.qe),
664: .q (reg2hw.intr_test.classd.q ),
665: .qs ()
666: );
667:
668:
669: // R[regen]: V(False)
670:
671: prim_subreg #(
672: .DW (1),
673: .SWACCESS("W1C"),
674: .RESVAL (1'h1)
675: ) u_regen (
676: .clk_i (clk_i ),
677: .rst_ni (rst_ni ),
678:
679: // from register interface
680: .we (regen_we),
681: .wd (regen_wd),
682:
683: // from internal hardware
684: .de (1'b0),
685: .d ('0 ),
686:
687: // to internal hardware
688: .qe (),
689: .q (reg2hw.regen.q ),
690:
691: // to register interface (read)
692: .qs (regen_qs)
693: );
694:
695:
696: // R[ping_timeout_cyc]: V(False)
697:
698: prim_subreg #(
699: .DW (24),
700: .SWACCESS("RW"),
701: .RESVAL (24'h20)
702: ) u_ping_timeout_cyc (
703: .clk_i (clk_i ),
704: .rst_ni (rst_ni ),
705:
706: // from register interface (qualified with register enable)
707: .we (ping_timeout_cyc_we & regen_qs),
708: .wd (ping_timeout_cyc_wd),
709:
710: // from internal hardware
711: .de (1'b0),
712: .d ('0 ),
713:
714: // to internal hardware
715: .qe (),
716: .q (reg2hw.ping_timeout_cyc.q ),
717:
718: // to register interface (read)
719: .qs (ping_timeout_cyc_qs)
720: );
721:
722:
723:
724: // Subregister 0 of Multireg alert_en
725: // R[alert_en]: V(False)
726:
727: prim_subreg #(
728: .DW (1),
729: .SWACCESS("RW"),
730: .RESVAL (1'h0)
731: ) u_alert_en (
732: .clk_i (clk_i ),
733: .rst_ni (rst_ni ),
734:
735: // from register interface (qualified with register enable)
736: .we (alert_en_we & regen_qs),
737: .wd (alert_en_wd),
738:
739: // from internal hardware
740: .de (1'b0),
741: .d ('0 ),
742:
743: // to internal hardware
744: .qe (),
745: .q (reg2hw.alert_en[0].q ),
746:
747: // to register interface (read)
748: .qs (alert_en_qs)
749: );
750:
751:
752:
753: // Subregister 0 of Multireg alert_class
754: // R[alert_class]: V(False)
755:
756: prim_subreg #(
757: .DW (2),
758: .SWACCESS("RW"),
759: .RESVAL (2'h0)
760: ) u_alert_class (
761: .clk_i (clk_i ),
762: .rst_ni (rst_ni ),
763:
764: // from register interface (qualified with register enable)
765: .we (alert_class_we & regen_qs),
766: .wd (alert_class_wd),
767:
768: // from internal hardware
769: .de (1'b0),
770: .d ('0 ),
771:
772: // to internal hardware
773: .qe (),
774: .q (reg2hw.alert_class[0].q ),
775:
776: // to register interface (read)
777: .qs (alert_class_qs)
778: );
779:
780:
781:
782: // Subregister 0 of Multireg alert_cause
783: // R[alert_cause]: V(False)
784:
785: prim_subreg #(
786: .DW (1),
787: .SWACCESS("W1C"),
788: .RESVAL (1'h0)
789: ) u_alert_cause (
790: .clk_i (clk_i ),
791: .rst_ni (rst_ni ),
792:
793: // from register interface
794: .we (alert_cause_we),
795: .wd (alert_cause_wd),
796:
797: // from internal hardware
798: .de (hw2reg.alert_cause[0].de),
799: .d (hw2reg.alert_cause[0].d ),
800:
801: // to internal hardware
802: .qe (),
803: .q (reg2hw.alert_cause[0].q ),
804:
805: // to register interface (read)
806: .qs (alert_cause_qs)
807: );
808:
809:
810:
811: // Subregister 0 of Multireg loc_alert_en
812: // R[loc_alert_en]: V(False)
813:
814: // F[en_la0]: 0:0
815: prim_subreg #(
816: .DW (1),
817: .SWACCESS("RW"),
818: .RESVAL (1'h0)
819: ) u_loc_alert_en_en_la0 (
820: .clk_i (clk_i ),
821: .rst_ni (rst_ni ),
822:
823: // from register interface (qualified with register enable)
824: .we (loc_alert_en_en_la0_we & regen_qs),
825: .wd (loc_alert_en_en_la0_wd),
826:
827: // from internal hardware
828: .de (1'b0),
829: .d ('0 ),
830:
831: // to internal hardware
832: .qe (),
833: .q (reg2hw.loc_alert_en[0].q ),
834:
835: // to register interface (read)
836: .qs (loc_alert_en_en_la0_qs)
837: );
838:
839:
840: // F[en_la1]: 1:1
841: prim_subreg #(
842: .DW (1),
843: .SWACCESS("RW"),
844: .RESVAL (1'h0)
845: ) u_loc_alert_en_en_la1 (
846: .clk_i (clk_i ),
847: .rst_ni (rst_ni ),
848:
849: // from register interface (qualified with register enable)
850: .we (loc_alert_en_en_la1_we & regen_qs),
851: .wd (loc_alert_en_en_la1_wd),
852:
853: // from internal hardware
854: .de (1'b0),
855: .d ('0 ),
856:
857: // to internal hardware
858: .qe (),
859: .q (reg2hw.loc_alert_en[1].q ),
860:
861: // to register interface (read)
862: .qs (loc_alert_en_en_la1_qs)
863: );
864:
865:
866: // F[en_la2]: 2:2
867: prim_subreg #(
868: .DW (1),
869: .SWACCESS("RW"),
870: .RESVAL (1'h0)
871: ) u_loc_alert_en_en_la2 (
872: .clk_i (clk_i ),
873: .rst_ni (rst_ni ),
874:
875: // from register interface (qualified with register enable)
876: .we (loc_alert_en_en_la2_we & regen_qs),
877: .wd (loc_alert_en_en_la2_wd),
878:
879: // from internal hardware
880: .de (1'b0),
881: .d ('0 ),
882:
883: // to internal hardware
884: .qe (),
885: .q (reg2hw.loc_alert_en[2].q ),
886:
887: // to register interface (read)
888: .qs (loc_alert_en_en_la2_qs)
889: );
890:
891:
892: // F[en_la3]: 3:3
893: prim_subreg #(
894: .DW (1),
895: .SWACCESS("RW"),
896: .RESVAL (1'h0)
897: ) u_loc_alert_en_en_la3 (
898: .clk_i (clk_i ),
899: .rst_ni (rst_ni ),
900:
901: // from register interface (qualified with register enable)
902: .we (loc_alert_en_en_la3_we & regen_qs),
903: .wd (loc_alert_en_en_la3_wd),
904:
905: // from internal hardware
906: .de (1'b0),
907: .d ('0 ),
908:
909: // to internal hardware
910: .qe (),
911: .q (reg2hw.loc_alert_en[3].q ),
912:
913: // to register interface (read)
914: .qs (loc_alert_en_en_la3_qs)
915: );
916:
917:
918:
919:
920: // Subregister 0 of Multireg loc_alert_class
921: // R[loc_alert_class]: V(False)
922:
923: // F[class_la0]: 1:0
924: prim_subreg #(
925: .DW (2),
926: .SWACCESS("RW"),
927: .RESVAL (2'h0)
928: ) u_loc_alert_class_class_la0 (
929: .clk_i (clk_i ),
930: .rst_ni (rst_ni ),
931:
932: // from register interface (qualified with register enable)
933: .we (loc_alert_class_class_la0_we & regen_qs),
934: .wd (loc_alert_class_class_la0_wd),
935:
936: // from internal hardware
937: .de (1'b0),
938: .d ('0 ),
939:
940: // to internal hardware
941: .qe (),
942: .q (reg2hw.loc_alert_class[0].q ),
943:
944: // to register interface (read)
945: .qs (loc_alert_class_class_la0_qs)
946: );
947:
948:
949: // F[class_la1]: 3:2
950: prim_subreg #(
951: .DW (2),
952: .SWACCESS("RW"),
953: .RESVAL (2'h0)
954: ) u_loc_alert_class_class_la1 (
955: .clk_i (clk_i ),
956: .rst_ni (rst_ni ),
957:
958: // from register interface (qualified with register enable)
959: .we (loc_alert_class_class_la1_we & regen_qs),
960: .wd (loc_alert_class_class_la1_wd),
961:
962: // from internal hardware
963: .de (1'b0),
964: .d ('0 ),
965:
966: // to internal hardware
967: .qe (),
968: .q (reg2hw.loc_alert_class[1].q ),
969:
970: // to register interface (read)
971: .qs (loc_alert_class_class_la1_qs)
972: );
973:
974:
975: // F[class_la2]: 5:4
976: prim_subreg #(
977: .DW (2),
978: .SWACCESS("RW"),
979: .RESVAL (2'h0)
980: ) u_loc_alert_class_class_la2 (
981: .clk_i (clk_i ),
982: .rst_ni (rst_ni ),
983:
984: // from register interface (qualified with register enable)
985: .we (loc_alert_class_class_la2_we & regen_qs),
986: .wd (loc_alert_class_class_la2_wd),
987:
988: // from internal hardware
989: .de (1'b0),
990: .d ('0 ),
991:
992: // to internal hardware
993: .qe (),
994: .q (reg2hw.loc_alert_class[2].q ),
995:
996: // to register interface (read)
997: .qs (loc_alert_class_class_la2_qs)
998: );
999:
1000:
1001: // F[class_la3]: 7:6
1002: prim_subreg #(
1003: .DW (2),
1004: .SWACCESS("RW"),
1005: .RESVAL (2'h0)
1006: ) u_loc_alert_class_class_la3 (
1007: .clk_i (clk_i ),
1008: .rst_ni (rst_ni ),
1009:
1010: // from register interface (qualified with register enable)
1011: .we (loc_alert_class_class_la3_we & regen_qs),
1012: .wd (loc_alert_class_class_la3_wd),
1013:
1014: // from internal hardware
1015: .de (1'b0),
1016: .d ('0 ),
1017:
1018: // to internal hardware
1019: .qe (),
1020: .q (reg2hw.loc_alert_class[3].q ),
1021:
1022: // to register interface (read)
1023: .qs (loc_alert_class_class_la3_qs)
1024: );
1025:
1026:
1027:
1028:
1029: // Subregister 0 of Multireg loc_alert_cause
1030: // R[loc_alert_cause]: V(False)
1031:
1032: // F[la0]: 0:0
1033: prim_subreg #(
1034: .DW (1),
1035: .SWACCESS("W1C"),
1036: .RESVAL (1'h0)
1037: ) u_loc_alert_cause_la0 (
1038: .clk_i (clk_i ),
1039: .rst_ni (rst_ni ),
1040:
1041: // from register interface
1042: .we (loc_alert_cause_la0_we),
1043: .wd (loc_alert_cause_la0_wd),
1044:
1045: // from internal hardware
1046: .de (hw2reg.loc_alert_cause[0].de),
1047: .d (hw2reg.loc_alert_cause[0].d ),
1048:
1049: // to internal hardware
1050: .qe (),
1051: .q (reg2hw.loc_alert_cause[0].q ),
1052:
1053: // to register interface (read)
1054: .qs (loc_alert_cause_la0_qs)
1055: );
1056:
1057:
1058: // F[la1]: 1:1
1059: prim_subreg #(
1060: .DW (1),
1061: .SWACCESS("W1C"),
1062: .RESVAL (1'h0)
1063: ) u_loc_alert_cause_la1 (
1064: .clk_i (clk_i ),
1065: .rst_ni (rst_ni ),
1066:
1067: // from register interface
1068: .we (loc_alert_cause_la1_we),
1069: .wd (loc_alert_cause_la1_wd),
1070:
1071: // from internal hardware
1072: .de (hw2reg.loc_alert_cause[1].de),
1073: .d (hw2reg.loc_alert_cause[1].d ),
1074:
1075: // to internal hardware
1076: .qe (),
1077: .q (reg2hw.loc_alert_cause[1].q ),
1078:
1079: // to register interface (read)
1080: .qs (loc_alert_cause_la1_qs)
1081: );
1082:
1083:
1084: // F[la2]: 2:2
1085: prim_subreg #(
1086: .DW (1),
1087: .SWACCESS("W1C"),
1088: .RESVAL (1'h0)
1089: ) u_loc_alert_cause_la2 (
1090: .clk_i (clk_i ),
1091: .rst_ni (rst_ni ),
1092:
1093: // from register interface
1094: .we (loc_alert_cause_la2_we),
1095: .wd (loc_alert_cause_la2_wd),
1096:
1097: // from internal hardware
1098: .de (hw2reg.loc_alert_cause[2].de),
1099: .d (hw2reg.loc_alert_cause[2].d ),
1100:
1101: // to internal hardware
1102: .qe (),
1103: .q (reg2hw.loc_alert_cause[2].q ),
1104:
1105: // to register interface (read)
1106: .qs (loc_alert_cause_la2_qs)
1107: );
1108:
1109:
1110: // F[la3]: 3:3
1111: prim_subreg #(
1112: .DW (1),
1113: .SWACCESS("W1C"),
1114: .RESVAL (1'h0)
1115: ) u_loc_alert_cause_la3 (
1116: .clk_i (clk_i ),
1117: .rst_ni (rst_ni ),
1118:
1119: // from register interface
1120: .we (loc_alert_cause_la3_we),
1121: .wd (loc_alert_cause_la3_wd),
1122:
1123: // from internal hardware
1124: .de (hw2reg.loc_alert_cause[3].de),
1125: .d (hw2reg.loc_alert_cause[3].d ),
1126:
1127: // to internal hardware
1128: .qe (),
1129: .q (reg2hw.loc_alert_cause[3].q ),
1130:
1131: // to register interface (read)
1132: .qs (loc_alert_cause_la3_qs)
1133: );
1134:
1135:
1136:
1137: // R[classa_ctrl]: V(False)
1138:
1139: // F[en]: 0:0
1140: prim_subreg #(
1141: .DW (1),
1142: .SWACCESS("RW"),
1143: .RESVAL (1'h0)
1144: ) u_classa_ctrl_en (
1145: .clk_i (clk_i ),
1146: .rst_ni (rst_ni ),
1147:
1148: // from register interface (qualified with register enable)
1149: .we (classa_ctrl_en_we & regen_qs),
1150: .wd (classa_ctrl_en_wd),
1151:
1152: // from internal hardware
1153: .de (1'b0),
1154: .d ('0 ),
1155:
1156: // to internal hardware
1157: .qe (),
1158: .q (reg2hw.classa_ctrl.en.q ),
1159:
1160: // to register interface (read)
1161: .qs (classa_ctrl_en_qs)
1162: );
1163:
1164:
1165: // F[lock]: 1:1
1166: prim_subreg #(
1167: .DW (1),
1168: .SWACCESS("RW"),
1169: .RESVAL (1'h0)
1170: ) u_classa_ctrl_lock (
1171: .clk_i (clk_i ),
1172: .rst_ni (rst_ni ),
1173:
1174: // from register interface (qualified with register enable)
1175: .we (classa_ctrl_lock_we & regen_qs),
1176: .wd (classa_ctrl_lock_wd),
1177:
1178: // from internal hardware
1179: .de (1'b0),
1180: .d ('0 ),
1181:
1182: // to internal hardware
1183: .qe (),
1184: .q (reg2hw.classa_ctrl.lock.q ),
1185:
1186: // to register interface (read)
1187: .qs (classa_ctrl_lock_qs)
1188: );
1189:
1190:
1191: // F[en_e0]: 2:2
1192: prim_subreg #(
1193: .DW (1),
1194: .SWACCESS("RW"),
1195: .RESVAL (1'h1)
1196: ) u_classa_ctrl_en_e0 (
1197: .clk_i (clk_i ),
1198: .rst_ni (rst_ni ),
1199:
1200: // from register interface (qualified with register enable)
1201: .we (classa_ctrl_en_e0_we & regen_qs),
1202: .wd (classa_ctrl_en_e0_wd),
1203:
1204: // from internal hardware
1205: .de (1'b0),
1206: .d ('0 ),
1207:
1208: // to internal hardware
1209: .qe (),
1210: .q (reg2hw.classa_ctrl.en_e0.q ),
1211:
1212: // to register interface (read)
1213: .qs (classa_ctrl_en_e0_qs)
1214: );
1215:
1216:
1217: // F[en_e1]: 3:3
1218: prim_subreg #(
1219: .DW (1),
1220: .SWACCESS("RW"),
1221: .RESVAL (1'h1)
1222: ) u_classa_ctrl_en_e1 (
1223: .clk_i (clk_i ),
1224: .rst_ni (rst_ni ),
1225:
1226: // from register interface (qualified with register enable)
1227: .we (classa_ctrl_en_e1_we & regen_qs),
1228: .wd (classa_ctrl_en_e1_wd),
1229:
1230: // from internal hardware
1231: .de (1'b0),
1232: .d ('0 ),
1233:
1234: // to internal hardware
1235: .qe (),
1236: .q (reg2hw.classa_ctrl.en_e1.q ),
1237:
1238: // to register interface (read)
1239: .qs (classa_ctrl_en_e1_qs)
1240: );
1241:
1242:
1243: // F[en_e2]: 4:4
1244: prim_subreg #(
1245: .DW (1),
1246: .SWACCESS("RW"),
1247: .RESVAL (1'h1)
1248: ) u_classa_ctrl_en_e2 (
1249: .clk_i (clk_i ),
1250: .rst_ni (rst_ni ),
1251:
1252: // from register interface (qualified with register enable)
1253: .we (classa_ctrl_en_e2_we & regen_qs),
1254: .wd (classa_ctrl_en_e2_wd),
1255:
1256: // from internal hardware
1257: .de (1'b0),
1258: .d ('0 ),
1259:
1260: // to internal hardware
1261: .qe (),
1262: .q (reg2hw.classa_ctrl.en_e2.q ),
1263:
1264: // to register interface (read)
1265: .qs (classa_ctrl_en_e2_qs)
1266: );
1267:
1268:
1269: // F[en_e3]: 5:5
1270: prim_subreg #(
1271: .DW (1),
1272: .SWACCESS("RW"),
1273: .RESVAL (1'h1)
1274: ) u_classa_ctrl_en_e3 (
1275: .clk_i (clk_i ),
1276: .rst_ni (rst_ni ),
1277:
1278: // from register interface (qualified with register enable)
1279: .we (classa_ctrl_en_e3_we & regen_qs),
1280: .wd (classa_ctrl_en_e3_wd),
1281:
1282: // from internal hardware
1283: .de (1'b0),
1284: .d ('0 ),
1285:
1286: // to internal hardware
1287: .qe (),
1288: .q (reg2hw.classa_ctrl.en_e3.q ),
1289:
1290: // to register interface (read)
1291: .qs (classa_ctrl_en_e3_qs)
1292: );
1293:
1294:
1295: // F[map_e0]: 7:6
1296: prim_subreg #(
1297: .DW (2),
1298: .SWACCESS("RW"),
1299: .RESVAL (2'h0)
1300: ) u_classa_ctrl_map_e0 (
1301: .clk_i (clk_i ),
1302: .rst_ni (rst_ni ),
1303:
1304: // from register interface (qualified with register enable)
1305: .we (classa_ctrl_map_e0_we & regen_qs),
1306: .wd (classa_ctrl_map_e0_wd),
1307:
1308: // from internal hardware
1309: .de (1'b0),
1310: .d ('0 ),
1311:
1312: // to internal hardware
1313: .qe (),
1314: .q (reg2hw.classa_ctrl.map_e0.q ),
1315:
1316: // to register interface (read)
1317: .qs (classa_ctrl_map_e0_qs)
1318: );
1319:
1320:
1321: // F[map_e1]: 9:8
1322: prim_subreg #(
1323: .DW (2),
1324: .SWACCESS("RW"),
1325: .RESVAL (2'h1)
1326: ) u_classa_ctrl_map_e1 (
1327: .clk_i (clk_i ),
1328: .rst_ni (rst_ni ),
1329:
1330: // from register interface (qualified with register enable)
1331: .we (classa_ctrl_map_e1_we & regen_qs),
1332: .wd (classa_ctrl_map_e1_wd),
1333:
1334: // from internal hardware
1335: .de (1'b0),
1336: .d ('0 ),
1337:
1338: // to internal hardware
1339: .qe (),
1340: .q (reg2hw.classa_ctrl.map_e1.q ),
1341:
1342: // to register interface (read)
1343: .qs (classa_ctrl_map_e1_qs)
1344: );
1345:
1346:
1347: // F[map_e2]: 11:10
1348: prim_subreg #(
1349: .DW (2),
1350: .SWACCESS("RW"),
1351: .RESVAL (2'h2)
1352: ) u_classa_ctrl_map_e2 (
1353: .clk_i (clk_i ),
1354: .rst_ni (rst_ni ),
1355:
1356: // from register interface (qualified with register enable)
1357: .we (classa_ctrl_map_e2_we & regen_qs),
1358: .wd (classa_ctrl_map_e2_wd),
1359:
1360: // from internal hardware
1361: .de (1'b0),
1362: .d ('0 ),
1363:
1364: // to internal hardware
1365: .qe (),
1366: .q (reg2hw.classa_ctrl.map_e2.q ),
1367:
1368: // to register interface (read)
1369: .qs (classa_ctrl_map_e2_qs)
1370: );
1371:
1372:
1373: // F[map_e3]: 13:12
1374: prim_subreg #(
1375: .DW (2),
1376: .SWACCESS("RW"),
1377: .RESVAL (2'h3)
1378: ) u_classa_ctrl_map_e3 (
1379: .clk_i (clk_i ),
1380: .rst_ni (rst_ni ),
1381:
1382: // from register interface (qualified with register enable)
1383: .we (classa_ctrl_map_e3_we & regen_qs),
1384: .wd (classa_ctrl_map_e3_wd),
1385:
1386: // from internal hardware
1387: .de (1'b0),
1388: .d ('0 ),
1389:
1390: // to internal hardware
1391: .qe (),
1392: .q (reg2hw.classa_ctrl.map_e3.q ),
1393:
1394: // to register interface (read)
1395: .qs (classa_ctrl_map_e3_qs)
1396: );
1397:
1398:
1399: // R[classa_clren]: V(False)
1400:
1401: prim_subreg #(
1402: .DW (1),
1403: .SWACCESS("W1C"),
1404: .RESVAL (1'h1)
1405: ) u_classa_clren (
1406: .clk_i (clk_i ),
1407: .rst_ni (rst_ni ),
1408:
1409: // from register interface
1410: .we (classa_clren_we),
1411: .wd (classa_clren_wd),
1412:
1413: // from internal hardware
1414: .de (hw2reg.classa_clren.de),
1415: .d (hw2reg.classa_clren.d ),
1416:
1417: // to internal hardware
1418: .qe (),
1419: .q (),
1420:
1421: // to register interface (read)
1422: .qs (classa_clren_qs)
1423: );
1424:
1425:
1426: // R[classa_clr]: V(False)
1427:
1428: prim_subreg #(
1429: .DW (1),
1430: .SWACCESS("WO"),
1431: .RESVAL (1'h0)
1432: ) u_classa_clr (
1433: .clk_i (clk_i ),
1434: .rst_ni (rst_ni ),
1435:
1436: // from register interface (qualified with register enable)
1437: .we (classa_clr_we & classa_clren_qs),
1438: .wd (classa_clr_wd),
1439:
1440: // from internal hardware
1441: .de (1'b0),
1442: .d ('0 ),
1443:
1444: // to internal hardware
1445: .qe (reg2hw.classa_clr.qe),
1446: .q (reg2hw.classa_clr.q ),
1447:
1448: .qs ()
1449: );
1450:
1451:
1452: // R[classa_accum_cnt]: V(True)
1453:
1454: prim_subreg_ext #(
1455: .DW (16)
1456: ) u_classa_accum_cnt (
1457: .re (classa_accum_cnt_re),
1458: .we (1'b0),
1459: .wd ('0),
1460: .d (hw2reg.classa_accum_cnt.d),
1461: .qre (),
1462: .qe (),
1463: .q (),
1464: .qs (classa_accum_cnt_qs)
1465: );
1466:
1467:
1468: // R[classa_accum_thresh]: V(False)
1469:
1470: prim_subreg #(
1471: .DW (16),
1472: .SWACCESS("RW"),
1473: .RESVAL (16'h0)
1474: ) u_classa_accum_thresh (
1475: .clk_i (clk_i ),
1476: .rst_ni (rst_ni ),
1477:
1478: // from register interface (qualified with register enable)
1479: .we (classa_accum_thresh_we & regen_qs),
1480: .wd (classa_accum_thresh_wd),
1481:
1482: // from internal hardware
1483: .de (1'b0),
1484: .d ('0 ),
1485:
1486: // to internal hardware
1487: .qe (),
1488: .q (reg2hw.classa_accum_thresh.q ),
1489:
1490: // to register interface (read)
1491: .qs (classa_accum_thresh_qs)
1492: );
1493:
1494:
1495: // R[classa_timeout_cyc]: V(False)
1496:
1497: prim_subreg #(
1498: .DW (32),
1499: .SWACCESS("RW"),
1500: .RESVAL (32'h0)
1501: ) u_classa_timeout_cyc (
1502: .clk_i (clk_i ),
1503: .rst_ni (rst_ni ),
1504:
1505: // from register interface (qualified with register enable)
1506: .we (classa_timeout_cyc_we & regen_qs),
1507: .wd (classa_timeout_cyc_wd),
1508:
1509: // from internal hardware
1510: .de (1'b0),
1511: .d ('0 ),
1512:
1513: // to internal hardware
1514: .qe (),
1515: .q (reg2hw.classa_timeout_cyc.q ),
1516:
1517: // to register interface (read)
1518: .qs (classa_timeout_cyc_qs)
1519: );
1520:
1521:
1522: // R[classa_phase0_cyc]: V(False)
1523:
1524: prim_subreg #(
1525: .DW (32),
1526: .SWACCESS("RW"),
1527: .RESVAL (32'h0)
1528: ) u_classa_phase0_cyc (
1529: .clk_i (clk_i ),
1530: .rst_ni (rst_ni ),
1531:
1532: // from register interface (qualified with register enable)
1533: .we (classa_phase0_cyc_we & regen_qs),
1534: .wd (classa_phase0_cyc_wd),
1535:
1536: // from internal hardware
1537: .de (1'b0),
1538: .d ('0 ),
1539:
1540: // to internal hardware
1541: .qe (),
1542: .q (reg2hw.classa_phase0_cyc.q ),
1543:
1544: // to register interface (read)
1545: .qs (classa_phase0_cyc_qs)
1546: );
1547:
1548:
1549: // R[classa_phase1_cyc]: V(False)
1550:
1551: prim_subreg #(
1552: .DW (32),
1553: .SWACCESS("RW"),
1554: .RESVAL (32'h0)
1555: ) u_classa_phase1_cyc (
1556: .clk_i (clk_i ),
1557: .rst_ni (rst_ni ),
1558:
1559: // from register interface (qualified with register enable)
1560: .we (classa_phase1_cyc_we & regen_qs),
1561: .wd (classa_phase1_cyc_wd),
1562:
1563: // from internal hardware
1564: .de (1'b0),
1565: .d ('0 ),
1566:
1567: // to internal hardware
1568: .qe (),
1569: .q (reg2hw.classa_phase1_cyc.q ),
1570:
1571: // to register interface (read)
1572: .qs (classa_phase1_cyc_qs)
1573: );
1574:
1575:
1576: // R[classa_phase2_cyc]: V(False)
1577:
1578: prim_subreg #(
1579: .DW (32),
1580: .SWACCESS("RW"),
1581: .RESVAL (32'h0)
1582: ) u_classa_phase2_cyc (
1583: .clk_i (clk_i ),
1584: .rst_ni (rst_ni ),
1585:
1586: // from register interface (qualified with register enable)
1587: .we (classa_phase2_cyc_we & regen_qs),
1588: .wd (classa_phase2_cyc_wd),
1589:
1590: // from internal hardware
1591: .de (1'b0),
1592: .d ('0 ),
1593:
1594: // to internal hardware
1595: .qe (),
1596: .q (reg2hw.classa_phase2_cyc.q ),
1597:
1598: // to register interface (read)
1599: .qs (classa_phase2_cyc_qs)
1600: );
1601:
1602:
1603: // R[classa_phase3_cyc]: V(False)
1604:
1605: prim_subreg #(
1606: .DW (32),
1607: .SWACCESS("RW"),
1608: .RESVAL (32'h0)
1609: ) u_classa_phase3_cyc (
1610: .clk_i (clk_i ),
1611: .rst_ni (rst_ni ),
1612:
1613: // from register interface (qualified with register enable)
1614: .we (classa_phase3_cyc_we & regen_qs),
1615: .wd (classa_phase3_cyc_wd),
1616:
1617: // from internal hardware
1618: .de (1'b0),
1619: .d ('0 ),
1620:
1621: // to internal hardware
1622: .qe (),
1623: .q (reg2hw.classa_phase3_cyc.q ),
1624:
1625: // to register interface (read)
1626: .qs (classa_phase3_cyc_qs)
1627: );
1628:
1629:
1630: // R[classa_esc_cnt]: V(True)
1631:
1632: prim_subreg_ext #(
1633: .DW (32)
1634: ) u_classa_esc_cnt (
1635: .re (classa_esc_cnt_re),
1636: .we (1'b0),
1637: .wd ('0),
1638: .d (hw2reg.classa_esc_cnt.d),
1639: .qre (),
1640: .qe (),
1641: .q (),
1642: .qs (classa_esc_cnt_qs)
1643: );
1644:
1645:
1646: // R[classa_state]: V(True)
1647:
1648: prim_subreg_ext #(
1649: .DW (3)
1650: ) u_classa_state (
1651: .re (classa_state_re),
1652: .we (1'b0),
1653: .wd ('0),
1654: .d (hw2reg.classa_state.d),
1655: .qre (),
1656: .qe (),
1657: .q (),
1658: .qs (classa_state_qs)
1659: );
1660:
1661:
1662: // R[classb_ctrl]: V(False)
1663:
1664: // F[en]: 0:0
1665: prim_subreg #(
1666: .DW (1),
1667: .SWACCESS("RW"),
1668: .RESVAL (1'h0)
1669: ) u_classb_ctrl_en (
1670: .clk_i (clk_i ),
1671: .rst_ni (rst_ni ),
1672:
1673: // from register interface (qualified with register enable)
1674: .we (classb_ctrl_en_we & regen_qs),
1675: .wd (classb_ctrl_en_wd),
1676:
1677: // from internal hardware
1678: .de (1'b0),
1679: .d ('0 ),
1680:
1681: // to internal hardware
1682: .qe (),
1683: .q (reg2hw.classb_ctrl.en.q ),
1684:
1685: // to register interface (read)
1686: .qs (classb_ctrl_en_qs)
1687: );
1688:
1689:
1690: // F[lock]: 1:1
1691: prim_subreg #(
1692: .DW (1),
1693: .SWACCESS("RW"),
1694: .RESVAL (1'h0)
1695: ) u_classb_ctrl_lock (
1696: .clk_i (clk_i ),
1697: .rst_ni (rst_ni ),
1698:
1699: // from register interface (qualified with register enable)
1700: .we (classb_ctrl_lock_we & regen_qs),
1701: .wd (classb_ctrl_lock_wd),
1702:
1703: // from internal hardware
1704: .de (1'b0),
1705: .d ('0 ),
1706:
1707: // to internal hardware
1708: .qe (),
1709: .q (reg2hw.classb_ctrl.lock.q ),
1710:
1711: // to register interface (read)
1712: .qs (classb_ctrl_lock_qs)
1713: );
1714:
1715:
1716: // F[en_e0]: 2:2
1717: prim_subreg #(
1718: .DW (1),
1719: .SWACCESS("RW"),
1720: .RESVAL (1'h1)
1721: ) u_classb_ctrl_en_e0 (
1722: .clk_i (clk_i ),
1723: .rst_ni (rst_ni ),
1724:
1725: // from register interface (qualified with register enable)
1726: .we (classb_ctrl_en_e0_we & regen_qs),
1727: .wd (classb_ctrl_en_e0_wd),
1728:
1729: // from internal hardware
1730: .de (1'b0),
1731: .d ('0 ),
1732:
1733: // to internal hardware
1734: .qe (),
1735: .q (reg2hw.classb_ctrl.en_e0.q ),
1736:
1737: // to register interface (read)
1738: .qs (classb_ctrl_en_e0_qs)
1739: );
1740:
1741:
1742: // F[en_e1]: 3:3
1743: prim_subreg #(
1744: .DW (1),
1745: .SWACCESS("RW"),
1746: .RESVAL (1'h1)
1747: ) u_classb_ctrl_en_e1 (
1748: .clk_i (clk_i ),
1749: .rst_ni (rst_ni ),
1750:
1751: // from register interface (qualified with register enable)
1752: .we (classb_ctrl_en_e1_we & regen_qs),
1753: .wd (classb_ctrl_en_e1_wd),
1754:
1755: // from internal hardware
1756: .de (1'b0),
1757: .d ('0 ),
1758:
1759: // to internal hardware
1760: .qe (),
1761: .q (reg2hw.classb_ctrl.en_e1.q ),
1762:
1763: // to register interface (read)
1764: .qs (classb_ctrl_en_e1_qs)
1765: );
1766:
1767:
1768: // F[en_e2]: 4:4
1769: prim_subreg #(
1770: .DW (1),
1771: .SWACCESS("RW"),
1772: .RESVAL (1'h1)
1773: ) u_classb_ctrl_en_e2 (
1774: .clk_i (clk_i ),
1775: .rst_ni (rst_ni ),
1776:
1777: // from register interface (qualified with register enable)
1778: .we (classb_ctrl_en_e2_we & regen_qs),
1779: .wd (classb_ctrl_en_e2_wd),
1780:
1781: // from internal hardware
1782: .de (1'b0),
1783: .d ('0 ),
1784:
1785: // to internal hardware
1786: .qe (),
1787: .q (reg2hw.classb_ctrl.en_e2.q ),
1788:
1789: // to register interface (read)
1790: .qs (classb_ctrl_en_e2_qs)
1791: );
1792:
1793:
1794: // F[en_e3]: 5:5
1795: prim_subreg #(
1796: .DW (1),
1797: .SWACCESS("RW"),
1798: .RESVAL (1'h1)
1799: ) u_classb_ctrl_en_e3 (
1800: .clk_i (clk_i ),
1801: .rst_ni (rst_ni ),
1802:
1803: // from register interface (qualified with register enable)
1804: .we (classb_ctrl_en_e3_we & regen_qs),
1805: .wd (classb_ctrl_en_e3_wd),
1806:
1807: // from internal hardware
1808: .de (1'b0),
1809: .d ('0 ),
1810:
1811: // to internal hardware
1812: .qe (),
1813: .q (reg2hw.classb_ctrl.en_e3.q ),
1814:
1815: // to register interface (read)
1816: .qs (classb_ctrl_en_e3_qs)
1817: );
1818:
1819:
1820: // F[map_e0]: 7:6
1821: prim_subreg #(
1822: .DW (2),
1823: .SWACCESS("RW"),
1824: .RESVAL (2'h0)
1825: ) u_classb_ctrl_map_e0 (
1826: .clk_i (clk_i ),
1827: .rst_ni (rst_ni ),
1828:
1829: // from register interface (qualified with register enable)
1830: .we (classb_ctrl_map_e0_we & regen_qs),
1831: .wd (classb_ctrl_map_e0_wd),
1832:
1833: // from internal hardware
1834: .de (1'b0),
1835: .d ('0 ),
1836:
1837: // to internal hardware
1838: .qe (),
1839: .q (reg2hw.classb_ctrl.map_e0.q ),
1840:
1841: // to register interface (read)
1842: .qs (classb_ctrl_map_e0_qs)
1843: );
1844:
1845:
1846: // F[map_e1]: 9:8
1847: prim_subreg #(
1848: .DW (2),
1849: .SWACCESS("RW"),
1850: .RESVAL (2'h1)
1851: ) u_classb_ctrl_map_e1 (
1852: .clk_i (clk_i ),
1853: .rst_ni (rst_ni ),
1854:
1855: // from register interface (qualified with register enable)
1856: .we (classb_ctrl_map_e1_we & regen_qs),
1857: .wd (classb_ctrl_map_e1_wd),
1858:
1859: // from internal hardware
1860: .de (1'b0),
1861: .d ('0 ),
1862:
1863: // to internal hardware
1864: .qe (),
1865: .q (reg2hw.classb_ctrl.map_e1.q ),
1866:
1867: // to register interface (read)
1868: .qs (classb_ctrl_map_e1_qs)
1869: );
1870:
1871:
1872: // F[map_e2]: 11:10
1873: prim_subreg #(
1874: .DW (2),
1875: .SWACCESS("RW"),
1876: .RESVAL (2'h2)
1877: ) u_classb_ctrl_map_e2 (
1878: .clk_i (clk_i ),
1879: .rst_ni (rst_ni ),
1880:
1881: // from register interface (qualified with register enable)
1882: .we (classb_ctrl_map_e2_we & regen_qs),
1883: .wd (classb_ctrl_map_e2_wd),
1884:
1885: // from internal hardware
1886: .de (1'b0),
1887: .d ('0 ),
1888:
1889: // to internal hardware
1890: .qe (),
1891: .q (reg2hw.classb_ctrl.map_e2.q ),
1892:
1893: // to register interface (read)
1894: .qs (classb_ctrl_map_e2_qs)
1895: );
1896:
1897:
1898: // F[map_e3]: 13:12
1899: prim_subreg #(
1900: .DW (2),
1901: .SWACCESS("RW"),
1902: .RESVAL (2'h3)
1903: ) u_classb_ctrl_map_e3 (
1904: .clk_i (clk_i ),
1905: .rst_ni (rst_ni ),
1906:
1907: // from register interface (qualified with register enable)
1908: .we (classb_ctrl_map_e3_we & regen_qs),
1909: .wd (classb_ctrl_map_e3_wd),
1910:
1911: // from internal hardware
1912: .de (1'b0),
1913: .d ('0 ),
1914:
1915: // to internal hardware
1916: .qe (),
1917: .q (reg2hw.classb_ctrl.map_e3.q ),
1918:
1919: // to register interface (read)
1920: .qs (classb_ctrl_map_e3_qs)
1921: );
1922:
1923:
1924: // R[classb_clren]: V(False)
1925:
1926: prim_subreg #(
1927: .DW (1),
1928: .SWACCESS("W1C"),
1929: .RESVAL (1'h1)
1930: ) u_classb_clren (
1931: .clk_i (clk_i ),
1932: .rst_ni (rst_ni ),
1933:
1934: // from register interface
1935: .we (classb_clren_we),
1936: .wd (classb_clren_wd),
1937:
1938: // from internal hardware
1939: .de (hw2reg.classb_clren.de),
1940: .d (hw2reg.classb_clren.d ),
1941:
1942: // to internal hardware
1943: .qe (),
1944: .q (),
1945:
1946: // to register interface (read)
1947: .qs (classb_clren_qs)
1948: );
1949:
1950:
1951: // R[classb_clr]: V(False)
1952:
1953: prim_subreg #(
1954: .DW (1),
1955: .SWACCESS("WO"),
1956: .RESVAL (1'h0)
1957: ) u_classb_clr (
1958: .clk_i (clk_i ),
1959: .rst_ni (rst_ni ),
1960:
1961: // from register interface (qualified with register enable)
1962: .we (classb_clr_we & classb_clren_qs),
1963: .wd (classb_clr_wd),
1964:
1965: // from internal hardware
1966: .de (1'b0),
1967: .d ('0 ),
1968:
1969: // to internal hardware
1970: .qe (reg2hw.classb_clr.qe),
1971: .q (reg2hw.classb_clr.q ),
1972:
1973: .qs ()
1974: );
1975:
1976:
1977: // R[classb_accum_cnt]: V(True)
1978:
1979: prim_subreg_ext #(
1980: .DW (16)
1981: ) u_classb_accum_cnt (
1982: .re (classb_accum_cnt_re),
1983: .we (1'b0),
1984: .wd ('0),
1985: .d (hw2reg.classb_accum_cnt.d),
1986: .qre (),
1987: .qe (),
1988: .q (),
1989: .qs (classb_accum_cnt_qs)
1990: );
1991:
1992:
1993: // R[classb_accum_thresh]: V(False)
1994:
1995: prim_subreg #(
1996: .DW (16),
1997: .SWACCESS("RW"),
1998: .RESVAL (16'h0)
1999: ) u_classb_accum_thresh (
2000: .clk_i (clk_i ),
2001: .rst_ni (rst_ni ),
2002:
2003: // from register interface (qualified with register enable)
2004: .we (classb_accum_thresh_we & regen_qs),
2005: .wd (classb_accum_thresh_wd),
2006:
2007: // from internal hardware
2008: .de (1'b0),
2009: .d ('0 ),
2010:
2011: // to internal hardware
2012: .qe (),
2013: .q (reg2hw.classb_accum_thresh.q ),
2014:
2015: // to register interface (read)
2016: .qs (classb_accum_thresh_qs)
2017: );
2018:
2019:
2020: // R[classb_timeout_cyc]: V(False)
2021:
2022: prim_subreg #(
2023: .DW (32),
2024: .SWACCESS("RW"),
2025: .RESVAL (32'h0)
2026: ) u_classb_timeout_cyc (
2027: .clk_i (clk_i ),
2028: .rst_ni (rst_ni ),
2029:
2030: // from register interface (qualified with register enable)
2031: .we (classb_timeout_cyc_we & regen_qs),
2032: .wd (classb_timeout_cyc_wd),
2033:
2034: // from internal hardware
2035: .de (1'b0),
2036: .d ('0 ),
2037:
2038: // to internal hardware
2039: .qe (),
2040: .q (reg2hw.classb_timeout_cyc.q ),
2041:
2042: // to register interface (read)
2043: .qs (classb_timeout_cyc_qs)
2044: );
2045:
2046:
2047: // R[classb_phase0_cyc]: V(False)
2048:
2049: prim_subreg #(
2050: .DW (32),
2051: .SWACCESS("RW"),
2052: .RESVAL (32'h0)
2053: ) u_classb_phase0_cyc (
2054: .clk_i (clk_i ),
2055: .rst_ni (rst_ni ),
2056:
2057: // from register interface (qualified with register enable)
2058: .we (classb_phase0_cyc_we & regen_qs),
2059: .wd (classb_phase0_cyc_wd),
2060:
2061: // from internal hardware
2062: .de (1'b0),
2063: .d ('0 ),
2064:
2065: // to internal hardware
2066: .qe (),
2067: .q (reg2hw.classb_phase0_cyc.q ),
2068:
2069: // to register interface (read)
2070: .qs (classb_phase0_cyc_qs)
2071: );
2072:
2073:
2074: // R[classb_phase1_cyc]: V(False)
2075:
2076: prim_subreg #(
2077: .DW (32),
2078: .SWACCESS("RW"),
2079: .RESVAL (32'h0)
2080: ) u_classb_phase1_cyc (
2081: .clk_i (clk_i ),
2082: .rst_ni (rst_ni ),
2083:
2084: // from register interface (qualified with register enable)
2085: .we (classb_phase1_cyc_we & regen_qs),
2086: .wd (classb_phase1_cyc_wd),
2087:
2088: // from internal hardware
2089: .de (1'b0),
2090: .d ('0 ),
2091:
2092: // to internal hardware
2093: .qe (),
2094: .q (reg2hw.classb_phase1_cyc.q ),
2095:
2096: // to register interface (read)
2097: .qs (classb_phase1_cyc_qs)
2098: );
2099:
2100:
2101: // R[classb_phase2_cyc]: V(False)
2102:
2103: prim_subreg #(
2104: .DW (32),
2105: .SWACCESS("RW"),
2106: .RESVAL (32'h0)
2107: ) u_classb_phase2_cyc (
2108: .clk_i (clk_i ),
2109: .rst_ni (rst_ni ),
2110:
2111: // from register interface (qualified with register enable)
2112: .we (classb_phase2_cyc_we & regen_qs),
2113: .wd (classb_phase2_cyc_wd),
2114:
2115: // from internal hardware
2116: .de (1'b0),
2117: .d ('0 ),
2118:
2119: // to internal hardware
2120: .qe (),
2121: .q (reg2hw.classb_phase2_cyc.q ),
2122:
2123: // to register interface (read)
2124: .qs (classb_phase2_cyc_qs)
2125: );
2126:
2127:
2128: // R[classb_phase3_cyc]: V(False)
2129:
2130: prim_subreg #(
2131: .DW (32),
2132: .SWACCESS("RW"),
2133: .RESVAL (32'h0)
2134: ) u_classb_phase3_cyc (
2135: .clk_i (clk_i ),
2136: .rst_ni (rst_ni ),
2137:
2138: // from register interface (qualified with register enable)
2139: .we (classb_phase3_cyc_we & regen_qs),
2140: .wd (classb_phase3_cyc_wd),
2141:
2142: // from internal hardware
2143: .de (1'b0),
2144: .d ('0 ),
2145:
2146: // to internal hardware
2147: .qe (),
2148: .q (reg2hw.classb_phase3_cyc.q ),
2149:
2150: // to register interface (read)
2151: .qs (classb_phase3_cyc_qs)
2152: );
2153:
2154:
2155: // R[classb_esc_cnt]: V(True)
2156:
2157: prim_subreg_ext #(
2158: .DW (32)
2159: ) u_classb_esc_cnt (
2160: .re (classb_esc_cnt_re),
2161: .we (1'b0),
2162: .wd ('0),
2163: .d (hw2reg.classb_esc_cnt.d),
2164: .qre (),
2165: .qe (),
2166: .q (),
2167: .qs (classb_esc_cnt_qs)
2168: );
2169:
2170:
2171: // R[classb_state]: V(True)
2172:
2173: prim_subreg_ext #(
2174: .DW (3)
2175: ) u_classb_state (
2176: .re (classb_state_re),
2177: .we (1'b0),
2178: .wd ('0),
2179: .d (hw2reg.classb_state.d),
2180: .qre (),
2181: .qe (),
2182: .q (),
2183: .qs (classb_state_qs)
2184: );
2185:
2186:
2187: // R[classc_ctrl]: V(False)
2188:
2189: // F[en]: 0:0
2190: prim_subreg #(
2191: .DW (1),
2192: .SWACCESS("RW"),
2193: .RESVAL (1'h0)
2194: ) u_classc_ctrl_en (
2195: .clk_i (clk_i ),
2196: .rst_ni (rst_ni ),
2197:
2198: // from register interface (qualified with register enable)
2199: .we (classc_ctrl_en_we & regen_qs),
2200: .wd (classc_ctrl_en_wd),
2201:
2202: // from internal hardware
2203: .de (1'b0),
2204: .d ('0 ),
2205:
2206: // to internal hardware
2207: .qe (),
2208: .q (reg2hw.classc_ctrl.en.q ),
2209:
2210: // to register interface (read)
2211: .qs (classc_ctrl_en_qs)
2212: );
2213:
2214:
2215: // F[lock]: 1:1
2216: prim_subreg #(
2217: .DW (1),
2218: .SWACCESS("RW"),
2219: .RESVAL (1'h0)
2220: ) u_classc_ctrl_lock (
2221: .clk_i (clk_i ),
2222: .rst_ni (rst_ni ),
2223:
2224: // from register interface (qualified with register enable)
2225: .we (classc_ctrl_lock_we & regen_qs),
2226: .wd (classc_ctrl_lock_wd),
2227:
2228: // from internal hardware
2229: .de (1'b0),
2230: .d ('0 ),
2231:
2232: // to internal hardware
2233: .qe (),
2234: .q (reg2hw.classc_ctrl.lock.q ),
2235:
2236: // to register interface (read)
2237: .qs (classc_ctrl_lock_qs)
2238: );
2239:
2240:
2241: // F[en_e0]: 2:2
2242: prim_subreg #(
2243: .DW (1),
2244: .SWACCESS("RW"),
2245: .RESVAL (1'h1)
2246: ) u_classc_ctrl_en_e0 (
2247: .clk_i (clk_i ),
2248: .rst_ni (rst_ni ),
2249:
2250: // from register interface (qualified with register enable)
2251: .we (classc_ctrl_en_e0_we & regen_qs),
2252: .wd (classc_ctrl_en_e0_wd),
2253:
2254: // from internal hardware
2255: .de (1'b0),
2256: .d ('0 ),
2257:
2258: // to internal hardware
2259: .qe (),
2260: .q (reg2hw.classc_ctrl.en_e0.q ),
2261:
2262: // to register interface (read)
2263: .qs (classc_ctrl_en_e0_qs)
2264: );
2265:
2266:
2267: // F[en_e1]: 3:3
2268: prim_subreg #(
2269: .DW (1),
2270: .SWACCESS("RW"),
2271: .RESVAL (1'h1)
2272: ) u_classc_ctrl_en_e1 (
2273: .clk_i (clk_i ),
2274: .rst_ni (rst_ni ),
2275:
2276: // from register interface (qualified with register enable)
2277: .we (classc_ctrl_en_e1_we & regen_qs),
2278: .wd (classc_ctrl_en_e1_wd),
2279:
2280: // from internal hardware
2281: .de (1'b0),
2282: .d ('0 ),
2283:
2284: // to internal hardware
2285: .qe (),
2286: .q (reg2hw.classc_ctrl.en_e1.q ),
2287:
2288: // to register interface (read)
2289: .qs (classc_ctrl_en_e1_qs)
2290: );
2291:
2292:
2293: // F[en_e2]: 4:4
2294: prim_subreg #(
2295: .DW (1),
2296: .SWACCESS("RW"),
2297: .RESVAL (1'h1)
2298: ) u_classc_ctrl_en_e2 (
2299: .clk_i (clk_i ),
2300: .rst_ni (rst_ni ),
2301:
2302: // from register interface (qualified with register enable)
2303: .we (classc_ctrl_en_e2_we & regen_qs),
2304: .wd (classc_ctrl_en_e2_wd),
2305:
2306: // from internal hardware
2307: .de (1'b0),
2308: .d ('0 ),
2309:
2310: // to internal hardware
2311: .qe (),
2312: .q (reg2hw.classc_ctrl.en_e2.q ),
2313:
2314: // to register interface (read)
2315: .qs (classc_ctrl_en_e2_qs)
2316: );
2317:
2318:
2319: // F[en_e3]: 5:5
2320: prim_subreg #(
2321: .DW (1),
2322: .SWACCESS("RW"),
2323: .RESVAL (1'h1)
2324: ) u_classc_ctrl_en_e3 (
2325: .clk_i (clk_i ),
2326: .rst_ni (rst_ni ),
2327:
2328: // from register interface (qualified with register enable)
2329: .we (classc_ctrl_en_e3_we & regen_qs),
2330: .wd (classc_ctrl_en_e3_wd),
2331:
2332: // from internal hardware
2333: .de (1'b0),
2334: .d ('0 ),
2335:
2336: // to internal hardware
2337: .qe (),
2338: .q (reg2hw.classc_ctrl.en_e3.q ),
2339:
2340: // to register interface (read)
2341: .qs (classc_ctrl_en_e3_qs)
2342: );
2343:
2344:
2345: // F[map_e0]: 7:6
2346: prim_subreg #(
2347: .DW (2),
2348: .SWACCESS("RW"),
2349: .RESVAL (2'h0)
2350: ) u_classc_ctrl_map_e0 (
2351: .clk_i (clk_i ),
2352: .rst_ni (rst_ni ),
2353:
2354: // from register interface (qualified with register enable)
2355: .we (classc_ctrl_map_e0_we & regen_qs),
2356: .wd (classc_ctrl_map_e0_wd),
2357:
2358: // from internal hardware
2359: .de (1'b0),
2360: .d ('0 ),
2361:
2362: // to internal hardware
2363: .qe (),
2364: .q (reg2hw.classc_ctrl.map_e0.q ),
2365:
2366: // to register interface (read)
2367: .qs (classc_ctrl_map_e0_qs)
2368: );
2369:
2370:
2371: // F[map_e1]: 9:8
2372: prim_subreg #(
2373: .DW (2),
2374: .SWACCESS("RW"),
2375: .RESVAL (2'h1)
2376: ) u_classc_ctrl_map_e1 (
2377: .clk_i (clk_i ),
2378: .rst_ni (rst_ni ),
2379:
2380: // from register interface (qualified with register enable)
2381: .we (classc_ctrl_map_e1_we & regen_qs),
2382: .wd (classc_ctrl_map_e1_wd),
2383:
2384: // from internal hardware
2385: .de (1'b0),
2386: .d ('0 ),
2387:
2388: // to internal hardware
2389: .qe (),
2390: .q (reg2hw.classc_ctrl.map_e1.q ),
2391:
2392: // to register interface (read)
2393: .qs (classc_ctrl_map_e1_qs)
2394: );
2395:
2396:
2397: // F[map_e2]: 11:10
2398: prim_subreg #(
2399: .DW (2),
2400: .SWACCESS("RW"),
2401: .RESVAL (2'h2)
2402: ) u_classc_ctrl_map_e2 (
2403: .clk_i (clk_i ),
2404: .rst_ni (rst_ni ),
2405:
2406: // from register interface (qualified with register enable)
2407: .we (classc_ctrl_map_e2_we & regen_qs),
2408: .wd (classc_ctrl_map_e2_wd),
2409:
2410: // from internal hardware
2411: .de (1'b0),
2412: .d ('0 ),
2413:
2414: // to internal hardware
2415: .qe (),
2416: .q (reg2hw.classc_ctrl.map_e2.q ),
2417:
2418: // to register interface (read)
2419: .qs (classc_ctrl_map_e2_qs)
2420: );
2421:
2422:
2423: // F[map_e3]: 13:12
2424: prim_subreg #(
2425: .DW (2),
2426: .SWACCESS("RW"),
2427: .RESVAL (2'h3)
2428: ) u_classc_ctrl_map_e3 (
2429: .clk_i (clk_i ),
2430: .rst_ni (rst_ni ),
2431:
2432: // from register interface (qualified with register enable)
2433: .we (classc_ctrl_map_e3_we & regen_qs),
2434: .wd (classc_ctrl_map_e3_wd),
2435:
2436: // from internal hardware
2437: .de (1'b0),
2438: .d ('0 ),
2439:
2440: // to internal hardware
2441: .qe (),
2442: .q (reg2hw.classc_ctrl.map_e3.q ),
2443:
2444: // to register interface (read)
2445: .qs (classc_ctrl_map_e3_qs)
2446: );
2447:
2448:
2449: // R[classc_clren]: V(False)
2450:
2451: prim_subreg #(
2452: .DW (1),
2453: .SWACCESS("W1C"),
2454: .RESVAL (1'h1)
2455: ) u_classc_clren (
2456: .clk_i (clk_i ),
2457: .rst_ni (rst_ni ),
2458:
2459: // from register interface
2460: .we (classc_clren_we),
2461: .wd (classc_clren_wd),
2462:
2463: // from internal hardware
2464: .de (hw2reg.classc_clren.de),
2465: .d (hw2reg.classc_clren.d ),
2466:
2467: // to internal hardware
2468: .qe (),
2469: .q (),
2470:
2471: // to register interface (read)
2472: .qs (classc_clren_qs)
2473: );
2474:
2475:
2476: // R[classc_clr]: V(False)
2477:
2478: prim_subreg #(
2479: .DW (1),
2480: .SWACCESS("WO"),
2481: .RESVAL (1'h0)
2482: ) u_classc_clr (
2483: .clk_i (clk_i ),
2484: .rst_ni (rst_ni ),
2485:
2486: // from register interface (qualified with register enable)
2487: .we (classc_clr_we & classc_clren_qs),
2488: .wd (classc_clr_wd),
2489:
2490: // from internal hardware
2491: .de (1'b0),
2492: .d ('0 ),
2493:
2494: // to internal hardware
2495: .qe (reg2hw.classc_clr.qe),
2496: .q (reg2hw.classc_clr.q ),
2497:
2498: .qs ()
2499: );
2500:
2501:
2502: // R[classc_accum_cnt]: V(True)
2503:
2504: prim_subreg_ext #(
2505: .DW (16)
2506: ) u_classc_accum_cnt (
2507: .re (classc_accum_cnt_re),
2508: .we (1'b0),
2509: .wd ('0),
2510: .d (hw2reg.classc_accum_cnt.d),
2511: .qre (),
2512: .qe (),
2513: .q (),
2514: .qs (classc_accum_cnt_qs)
2515: );
2516:
2517:
2518: // R[classc_accum_thresh]: V(False)
2519:
2520: prim_subreg #(
2521: .DW (16),
2522: .SWACCESS("RW"),
2523: .RESVAL (16'h0)
2524: ) u_classc_accum_thresh (
2525: .clk_i (clk_i ),
2526: .rst_ni (rst_ni ),
2527:
2528: // from register interface (qualified with register enable)
2529: .we (classc_accum_thresh_we & regen_qs),
2530: .wd (classc_accum_thresh_wd),
2531:
2532: // from internal hardware
2533: .de (1'b0),
2534: .d ('0 ),
2535:
2536: // to internal hardware
2537: .qe (),
2538: .q (reg2hw.classc_accum_thresh.q ),
2539:
2540: // to register interface (read)
2541: .qs (classc_accum_thresh_qs)
2542: );
2543:
2544:
2545: // R[classc_timeout_cyc]: V(False)
2546:
2547: prim_subreg #(
2548: .DW (32),
2549: .SWACCESS("RW"),
2550: .RESVAL (32'h0)
2551: ) u_classc_timeout_cyc (
2552: .clk_i (clk_i ),
2553: .rst_ni (rst_ni ),
2554:
2555: // from register interface (qualified with register enable)
2556: .we (classc_timeout_cyc_we & regen_qs),
2557: .wd (classc_timeout_cyc_wd),
2558:
2559: // from internal hardware
2560: .de (1'b0),
2561: .d ('0 ),
2562:
2563: // to internal hardware
2564: .qe (),
2565: .q (reg2hw.classc_timeout_cyc.q ),
2566:
2567: // to register interface (read)
2568: .qs (classc_timeout_cyc_qs)
2569: );
2570:
2571:
2572: // R[classc_phase0_cyc]: V(False)
2573:
2574: prim_subreg #(
2575: .DW (32),
2576: .SWACCESS("RW"),
2577: .RESVAL (32'h0)
2578: ) u_classc_phase0_cyc (
2579: .clk_i (clk_i ),
2580: .rst_ni (rst_ni ),
2581:
2582: // from register interface (qualified with register enable)
2583: .we (classc_phase0_cyc_we & regen_qs),
2584: .wd (classc_phase0_cyc_wd),
2585:
2586: // from internal hardware
2587: .de (1'b0),
2588: .d ('0 ),
2589:
2590: // to internal hardware
2591: .qe (),
2592: .q (reg2hw.classc_phase0_cyc.q ),
2593:
2594: // to register interface (read)
2595: .qs (classc_phase0_cyc_qs)
2596: );
2597:
2598:
2599: // R[classc_phase1_cyc]: V(False)
2600:
2601: prim_subreg #(
2602: .DW (32),
2603: .SWACCESS("RW"),
2604: .RESVAL (32'h0)
2605: ) u_classc_phase1_cyc (
2606: .clk_i (clk_i ),
2607: .rst_ni (rst_ni ),
2608:
2609: // from register interface (qualified with register enable)
2610: .we (classc_phase1_cyc_we & regen_qs),
2611: .wd (classc_phase1_cyc_wd),
2612:
2613: // from internal hardware
2614: .de (1'b0),
2615: .d ('0 ),
2616:
2617: // to internal hardware
2618: .qe (),
2619: .q (reg2hw.classc_phase1_cyc.q ),
2620:
2621: // to register interface (read)
2622: .qs (classc_phase1_cyc_qs)
2623: );
2624:
2625:
2626: // R[classc_phase2_cyc]: V(False)
2627:
2628: prim_subreg #(
2629: .DW (32),
2630: .SWACCESS("RW"),
2631: .RESVAL (32'h0)
2632: ) u_classc_phase2_cyc (
2633: .clk_i (clk_i ),
2634: .rst_ni (rst_ni ),
2635:
2636: // from register interface (qualified with register enable)
2637: .we (classc_phase2_cyc_we & regen_qs),
2638: .wd (classc_phase2_cyc_wd),
2639:
2640: // from internal hardware
2641: .de (1'b0),
2642: .d ('0 ),
2643:
2644: // to internal hardware
2645: .qe (),
2646: .q (reg2hw.classc_phase2_cyc.q ),
2647:
2648: // to register interface (read)
2649: .qs (classc_phase2_cyc_qs)
2650: );
2651:
2652:
2653: // R[classc_phase3_cyc]: V(False)
2654:
2655: prim_subreg #(
2656: .DW (32),
2657: .SWACCESS("RW"),
2658: .RESVAL (32'h0)
2659: ) u_classc_phase3_cyc (
2660: .clk_i (clk_i ),
2661: .rst_ni (rst_ni ),
2662:
2663: // from register interface (qualified with register enable)
2664: .we (classc_phase3_cyc_we & regen_qs),
2665: .wd (classc_phase3_cyc_wd),
2666:
2667: // from internal hardware
2668: .de (1'b0),
2669: .d ('0 ),
2670:
2671: // to internal hardware
2672: .qe (),
2673: .q (reg2hw.classc_phase3_cyc.q ),
2674:
2675: // to register interface (read)
2676: .qs (classc_phase3_cyc_qs)
2677: );
2678:
2679:
2680: // R[classc_esc_cnt]: V(True)
2681:
2682: prim_subreg_ext #(
2683: .DW (32)
2684: ) u_classc_esc_cnt (
2685: .re (classc_esc_cnt_re),
2686: .we (1'b0),
2687: .wd ('0),
2688: .d (hw2reg.classc_esc_cnt.d),
2689: .qre (),
2690: .qe (),
2691: .q (),
2692: .qs (classc_esc_cnt_qs)
2693: );
2694:
2695:
2696: // R[classc_state]: V(True)
2697:
2698: prim_subreg_ext #(
2699: .DW (3)
2700: ) u_classc_state (
2701: .re (classc_state_re),
2702: .we (1'b0),
2703: .wd ('0),
2704: .d (hw2reg.classc_state.d),
2705: .qre (),
2706: .qe (),
2707: .q (),
2708: .qs (classc_state_qs)
2709: );
2710:
2711:
2712: // R[classd_ctrl]: V(False)
2713:
2714: // F[en]: 0:0
2715: prim_subreg #(
2716: .DW (1),
2717: .SWACCESS("RW"),
2718: .RESVAL (1'h0)
2719: ) u_classd_ctrl_en (
2720: .clk_i (clk_i ),
2721: .rst_ni (rst_ni ),
2722:
2723: // from register interface (qualified with register enable)
2724: .we (classd_ctrl_en_we & regen_qs),
2725: .wd (classd_ctrl_en_wd),
2726:
2727: // from internal hardware
2728: .de (1'b0),
2729: .d ('0 ),
2730:
2731: // to internal hardware
2732: .qe (),
2733: .q (reg2hw.classd_ctrl.en.q ),
2734:
2735: // to register interface (read)
2736: .qs (classd_ctrl_en_qs)
2737: );
2738:
2739:
2740: // F[lock]: 1:1
2741: prim_subreg #(
2742: .DW (1),
2743: .SWACCESS("RW"),
2744: .RESVAL (1'h0)
2745: ) u_classd_ctrl_lock (
2746: .clk_i (clk_i ),
2747: .rst_ni (rst_ni ),
2748:
2749: // from register interface (qualified with register enable)
2750: .we (classd_ctrl_lock_we & regen_qs),
2751: .wd (classd_ctrl_lock_wd),
2752:
2753: // from internal hardware
2754: .de (1'b0),
2755: .d ('0 ),
2756:
2757: // to internal hardware
2758: .qe (),
2759: .q (reg2hw.classd_ctrl.lock.q ),
2760:
2761: // to register interface (read)
2762: .qs (classd_ctrl_lock_qs)
2763: );
2764:
2765:
2766: // F[en_e0]: 2:2
2767: prim_subreg #(
2768: .DW (1),
2769: .SWACCESS("RW"),
2770: .RESVAL (1'h1)
2771: ) u_classd_ctrl_en_e0 (
2772: .clk_i (clk_i ),
2773: .rst_ni (rst_ni ),
2774:
2775: // from register interface (qualified with register enable)
2776: .we (classd_ctrl_en_e0_we & regen_qs),
2777: .wd (classd_ctrl_en_e0_wd),
2778:
2779: // from internal hardware
2780: .de (1'b0),
2781: .d ('0 ),
2782:
2783: // to internal hardware
2784: .qe (),
2785: .q (reg2hw.classd_ctrl.en_e0.q ),
2786:
2787: // to register interface (read)
2788: .qs (classd_ctrl_en_e0_qs)
2789: );
2790:
2791:
2792: // F[en_e1]: 3:3
2793: prim_subreg #(
2794: .DW (1),
2795: .SWACCESS("RW"),
2796: .RESVAL (1'h1)
2797: ) u_classd_ctrl_en_e1 (
2798: .clk_i (clk_i ),
2799: .rst_ni (rst_ni ),
2800:
2801: // from register interface (qualified with register enable)
2802: .we (classd_ctrl_en_e1_we & regen_qs),
2803: .wd (classd_ctrl_en_e1_wd),
2804:
2805: // from internal hardware
2806: .de (1'b0),
2807: .d ('0 ),
2808:
2809: // to internal hardware
2810: .qe (),
2811: .q (reg2hw.classd_ctrl.en_e1.q ),
2812:
2813: // to register interface (read)
2814: .qs (classd_ctrl_en_e1_qs)
2815: );
2816:
2817:
2818: // F[en_e2]: 4:4
2819: prim_subreg #(
2820: .DW (1),
2821: .SWACCESS("RW"),
2822: .RESVAL (1'h1)
2823: ) u_classd_ctrl_en_e2 (
2824: .clk_i (clk_i ),
2825: .rst_ni (rst_ni ),
2826:
2827: // from register interface (qualified with register enable)
2828: .we (classd_ctrl_en_e2_we & regen_qs),
2829: .wd (classd_ctrl_en_e2_wd),
2830:
2831: // from internal hardware
2832: .de (1'b0),
2833: .d ('0 ),
2834:
2835: // to internal hardware
2836: .qe (),
2837: .q (reg2hw.classd_ctrl.en_e2.q ),
2838:
2839: // to register interface (read)
2840: .qs (classd_ctrl_en_e2_qs)
2841: );
2842:
2843:
2844: // F[en_e3]: 5:5
2845: prim_subreg #(
2846: .DW (1),
2847: .SWACCESS("RW"),
2848: .RESVAL (1'h1)
2849: ) u_classd_ctrl_en_e3 (
2850: .clk_i (clk_i ),
2851: .rst_ni (rst_ni ),
2852:
2853: // from register interface (qualified with register enable)
2854: .we (classd_ctrl_en_e3_we & regen_qs),
2855: .wd (classd_ctrl_en_e3_wd),
2856:
2857: // from internal hardware
2858: .de (1'b0),
2859: .d ('0 ),
2860:
2861: // to internal hardware
2862: .qe (),
2863: .q (reg2hw.classd_ctrl.en_e3.q ),
2864:
2865: // to register interface (read)
2866: .qs (classd_ctrl_en_e3_qs)
2867: );
2868:
2869:
2870: // F[map_e0]: 7:6
2871: prim_subreg #(
2872: .DW (2),
2873: .SWACCESS("RW"),
2874: .RESVAL (2'h0)
2875: ) u_classd_ctrl_map_e0 (
2876: .clk_i (clk_i ),
2877: .rst_ni (rst_ni ),
2878:
2879: // from register interface (qualified with register enable)
2880: .we (classd_ctrl_map_e0_we & regen_qs),
2881: .wd (classd_ctrl_map_e0_wd),
2882:
2883: // from internal hardware
2884: .de (1'b0),
2885: .d ('0 ),
2886:
2887: // to internal hardware
2888: .qe (),
2889: .q (reg2hw.classd_ctrl.map_e0.q ),
2890:
2891: // to register interface (read)
2892: .qs (classd_ctrl_map_e0_qs)
2893: );
2894:
2895:
2896: // F[map_e1]: 9:8
2897: prim_subreg #(
2898: .DW (2),
2899: .SWACCESS("RW"),
2900: .RESVAL (2'h1)
2901: ) u_classd_ctrl_map_e1 (
2902: .clk_i (clk_i ),
2903: .rst_ni (rst_ni ),
2904:
2905: // from register interface (qualified with register enable)
2906: .we (classd_ctrl_map_e1_we & regen_qs),
2907: .wd (classd_ctrl_map_e1_wd),
2908:
2909: // from internal hardware
2910: .de (1'b0),
2911: .d ('0 ),
2912:
2913: // to internal hardware
2914: .qe (),
2915: .q (reg2hw.classd_ctrl.map_e1.q ),
2916:
2917: // to register interface (read)
2918: .qs (classd_ctrl_map_e1_qs)
2919: );
2920:
2921:
2922: // F[map_e2]: 11:10
2923: prim_subreg #(
2924: .DW (2),
2925: .SWACCESS("RW"),
2926: .RESVAL (2'h2)
2927: ) u_classd_ctrl_map_e2 (
2928: .clk_i (clk_i ),
2929: .rst_ni (rst_ni ),
2930:
2931: // from register interface (qualified with register enable)
2932: .we (classd_ctrl_map_e2_we & regen_qs),
2933: .wd (classd_ctrl_map_e2_wd),
2934:
2935: // from internal hardware
2936: .de (1'b0),
2937: .d ('0 ),
2938:
2939: // to internal hardware
2940: .qe (),
2941: .q (reg2hw.classd_ctrl.map_e2.q ),
2942:
2943: // to register interface (read)
2944: .qs (classd_ctrl_map_e2_qs)
2945: );
2946:
2947:
2948: // F[map_e3]: 13:12
2949: prim_subreg #(
2950: .DW (2),
2951: .SWACCESS("RW"),
2952: .RESVAL (2'h3)
2953: ) u_classd_ctrl_map_e3 (
2954: .clk_i (clk_i ),
2955: .rst_ni (rst_ni ),
2956:
2957: // from register interface (qualified with register enable)
2958: .we (classd_ctrl_map_e3_we & regen_qs),
2959: .wd (classd_ctrl_map_e3_wd),
2960:
2961: // from internal hardware
2962: .de (1'b0),
2963: .d ('0 ),
2964:
2965: // to internal hardware
2966: .qe (),
2967: .q (reg2hw.classd_ctrl.map_e3.q ),
2968:
2969: // to register interface (read)
2970: .qs (classd_ctrl_map_e3_qs)
2971: );
2972:
2973:
2974: // R[classd_clren]: V(False)
2975:
2976: prim_subreg #(
2977: .DW (1),
2978: .SWACCESS("W1C"),
2979: .RESVAL (1'h1)
2980: ) u_classd_clren (
2981: .clk_i (clk_i ),
2982: .rst_ni (rst_ni ),
2983:
2984: // from register interface
2985: .we (classd_clren_we),
2986: .wd (classd_clren_wd),
2987:
2988: // from internal hardware
2989: .de (hw2reg.classd_clren.de),
2990: .d (hw2reg.classd_clren.d ),
2991:
2992: // to internal hardware
2993: .qe (),
2994: .q (),
2995:
2996: // to register interface (read)
2997: .qs (classd_clren_qs)
2998: );
2999:
3000:
3001: // R[classd_clr]: V(False)
3002:
3003: prim_subreg #(
3004: .DW (1),
3005: .SWACCESS("WO"),
3006: .RESVAL (1'h0)
3007: ) u_classd_clr (
3008: .clk_i (clk_i ),
3009: .rst_ni (rst_ni ),
3010:
3011: // from register interface (qualified with register enable)
3012: .we (classd_clr_we & classd_clren_qs),
3013: .wd (classd_clr_wd),
3014:
3015: // from internal hardware
3016: .de (1'b0),
3017: .d ('0 ),
3018:
3019: // to internal hardware
3020: .qe (reg2hw.classd_clr.qe),
3021: .q (reg2hw.classd_clr.q ),
3022:
3023: .qs ()
3024: );
3025:
3026:
3027: // R[classd_accum_cnt]: V(True)
3028:
3029: prim_subreg_ext #(
3030: .DW (16)
3031: ) u_classd_accum_cnt (
3032: .re (classd_accum_cnt_re),
3033: .we (1'b0),
3034: .wd ('0),
3035: .d (hw2reg.classd_accum_cnt.d),
3036: .qre (),
3037: .qe (),
3038: .q (),
3039: .qs (classd_accum_cnt_qs)
3040: );
3041:
3042:
3043: // R[classd_accum_thresh]: V(False)
3044:
3045: prim_subreg #(
3046: .DW (16),
3047: .SWACCESS("RW"),
3048: .RESVAL (16'h0)
3049: ) u_classd_accum_thresh (
3050: .clk_i (clk_i ),
3051: .rst_ni (rst_ni ),
3052:
3053: // from register interface (qualified with register enable)
3054: .we (classd_accum_thresh_we & regen_qs),
3055: .wd (classd_accum_thresh_wd),
3056:
3057: // from internal hardware
3058: .de (1'b0),
3059: .d ('0 ),
3060:
3061: // to internal hardware
3062: .qe (),
3063: .q (reg2hw.classd_accum_thresh.q ),
3064:
3065: // to register interface (read)
3066: .qs (classd_accum_thresh_qs)
3067: );
3068:
3069:
3070: // R[classd_timeout_cyc]: V(False)
3071:
3072: prim_subreg #(
3073: .DW (32),
3074: .SWACCESS("RW"),
3075: .RESVAL (32'h0)
3076: ) u_classd_timeout_cyc (
3077: .clk_i (clk_i ),
3078: .rst_ni (rst_ni ),
3079:
3080: // from register interface (qualified with register enable)
3081: .we (classd_timeout_cyc_we & regen_qs),
3082: .wd (classd_timeout_cyc_wd),
3083:
3084: // from internal hardware
3085: .de (1'b0),
3086: .d ('0 ),
3087:
3088: // to internal hardware
3089: .qe (),
3090: .q (reg2hw.classd_timeout_cyc.q ),
3091:
3092: // to register interface (read)
3093: .qs (classd_timeout_cyc_qs)
3094: );
3095:
3096:
3097: // R[classd_phase0_cyc]: V(False)
3098:
3099: prim_subreg #(
3100: .DW (32),
3101: .SWACCESS("RW"),
3102: .RESVAL (32'h0)
3103: ) u_classd_phase0_cyc (
3104: .clk_i (clk_i ),
3105: .rst_ni (rst_ni ),
3106:
3107: // from register interface (qualified with register enable)
3108: .we (classd_phase0_cyc_we & regen_qs),
3109: .wd (classd_phase0_cyc_wd),
3110:
3111: // from internal hardware
3112: .de (1'b0),
3113: .d ('0 ),
3114:
3115: // to internal hardware
3116: .qe (),
3117: .q (reg2hw.classd_phase0_cyc.q ),
3118:
3119: // to register interface (read)
3120: .qs (classd_phase0_cyc_qs)
3121: );
3122:
3123:
3124: // R[classd_phase1_cyc]: V(False)
3125:
3126: prim_subreg #(
3127: .DW (32),
3128: .SWACCESS("RW"),
3129: .RESVAL (32'h0)
3130: ) u_classd_phase1_cyc (
3131: .clk_i (clk_i ),
3132: .rst_ni (rst_ni ),
3133:
3134: // from register interface (qualified with register enable)
3135: .we (classd_phase1_cyc_we & regen_qs),
3136: .wd (classd_phase1_cyc_wd),
3137:
3138: // from internal hardware
3139: .de (1'b0),
3140: .d ('0 ),
3141:
3142: // to internal hardware
3143: .qe (),
3144: .q (reg2hw.classd_phase1_cyc.q ),
3145:
3146: // to register interface (read)
3147: .qs (classd_phase1_cyc_qs)
3148: );
3149:
3150:
3151: // R[classd_phase2_cyc]: V(False)
3152:
3153: prim_subreg #(
3154: .DW (32),
3155: .SWACCESS("RW"),
3156: .RESVAL (32'h0)
3157: ) u_classd_phase2_cyc (
3158: .clk_i (clk_i ),
3159: .rst_ni (rst_ni ),
3160:
3161: // from register interface (qualified with register enable)
3162: .we (classd_phase2_cyc_we & regen_qs),
3163: .wd (classd_phase2_cyc_wd),
3164:
3165: // from internal hardware
3166: .de (1'b0),
3167: .d ('0 ),
3168:
3169: // to internal hardware
3170: .qe (),
3171: .q (reg2hw.classd_phase2_cyc.q ),
3172:
3173: // to register interface (read)
3174: .qs (classd_phase2_cyc_qs)
3175: );
3176:
3177:
3178: // R[classd_phase3_cyc]: V(False)
3179:
3180: prim_subreg #(
3181: .DW (32),
3182: .SWACCESS("RW"),
3183: .RESVAL (32'h0)
3184: ) u_classd_phase3_cyc (
3185: .clk_i (clk_i ),
3186: .rst_ni (rst_ni ),
3187:
3188: // from register interface (qualified with register enable)
3189: .we (classd_phase3_cyc_we & regen_qs),
3190: .wd (classd_phase3_cyc_wd),
3191:
3192: // from internal hardware
3193: .de (1'b0),
3194: .d ('0 ),
3195:
3196: // to internal hardware
3197: .qe (),
3198: .q (reg2hw.classd_phase3_cyc.q ),
3199:
3200: // to register interface (read)
3201: .qs (classd_phase3_cyc_qs)
3202: );
3203:
3204:
3205: // R[classd_esc_cnt]: V(True)
3206:
3207: prim_subreg_ext #(
3208: .DW (32)
3209: ) u_classd_esc_cnt (
3210: .re (classd_esc_cnt_re),
3211: .we (1'b0),
3212: .wd ('0),
3213: .d (hw2reg.classd_esc_cnt.d),
3214: .qre (),
3215: .qe (),
3216: .q (),
3217: .qs (classd_esc_cnt_qs)
3218: );
3219:
3220:
3221: // R[classd_state]: V(True)
3222:
3223: prim_subreg_ext #(
3224: .DW (3)
3225: ) u_classd_state (
3226: .re (classd_state_re),
3227: .we (1'b0),
3228: .wd ('0),
3229: .d (hw2reg.classd_state.d),
3230: .qre (),
3231: .qe (),
3232: .q (),
3233: .qs (classd_state_qs)
3234: );
3235:
3236:
3237:
3238:
3239: logic [58:0] addr_hit;
3240: always_comb begin
3241: addr_hit = '0;
3242: addr_hit[ 0] = (reg_addr == ALERT_HANDLER_INTR_STATE_OFFSET);
3243: addr_hit[ 1] = (reg_addr == ALERT_HANDLER_INTR_ENABLE_OFFSET);
3244: addr_hit[ 2] = (reg_addr == ALERT_HANDLER_INTR_TEST_OFFSET);
3245: addr_hit[ 3] = (reg_addr == ALERT_HANDLER_REGEN_OFFSET);
3246: addr_hit[ 4] = (reg_addr == ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET);
3247: addr_hit[ 5] = (reg_addr == ALERT_HANDLER_ALERT_EN_OFFSET);
3248: addr_hit[ 6] = (reg_addr == ALERT_HANDLER_ALERT_CLASS_OFFSET);
3249: addr_hit[ 7] = (reg_addr == ALERT_HANDLER_ALERT_CAUSE_OFFSET);
3250: addr_hit[ 8] = (reg_addr == ALERT_HANDLER_LOC_ALERT_EN_OFFSET);
3251: addr_hit[ 9] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET);
3252: addr_hit[10] = (reg_addr == ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET);
3253: addr_hit[11] = (reg_addr == ALERT_HANDLER_CLASSA_CTRL_OFFSET);
3254: addr_hit[12] = (reg_addr == ALERT_HANDLER_CLASSA_CLREN_OFFSET);
3255: addr_hit[13] = (reg_addr == ALERT_HANDLER_CLASSA_CLR_OFFSET);
3256: addr_hit[14] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET);
3257: addr_hit[15] = (reg_addr == ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET);
3258: addr_hit[16] = (reg_addr == ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET);
3259: addr_hit[17] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET);
3260: addr_hit[18] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET);
3261: addr_hit[19] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET);
3262: addr_hit[20] = (reg_addr == ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET);
3263: addr_hit[21] = (reg_addr == ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET);
3264: addr_hit[22] = (reg_addr == ALERT_HANDLER_CLASSA_STATE_OFFSET);
3265: addr_hit[23] = (reg_addr == ALERT_HANDLER_CLASSB_CTRL_OFFSET);
3266: addr_hit[24] = (reg_addr == ALERT_HANDLER_CLASSB_CLREN_OFFSET);
3267: addr_hit[25] = (reg_addr == ALERT_HANDLER_CLASSB_CLR_OFFSET);
3268: addr_hit[26] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET);
3269: addr_hit[27] = (reg_addr == ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET);
3270: addr_hit[28] = (reg_addr == ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET);
3271: addr_hit[29] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET);
3272: addr_hit[30] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET);
3273: addr_hit[31] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET);
3274: addr_hit[32] = (reg_addr == ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET);
3275: addr_hit[33] = (reg_addr == ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET);
3276: addr_hit[34] = (reg_addr == ALERT_HANDLER_CLASSB_STATE_OFFSET);
3277: addr_hit[35] = (reg_addr == ALERT_HANDLER_CLASSC_CTRL_OFFSET);
3278: addr_hit[36] = (reg_addr == ALERT_HANDLER_CLASSC_CLREN_OFFSET);
3279: addr_hit[37] = (reg_addr == ALERT_HANDLER_CLASSC_CLR_OFFSET);
3280: addr_hit[38] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET);
3281: addr_hit[39] = (reg_addr == ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET);
3282: addr_hit[40] = (reg_addr == ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET);
3283: addr_hit[41] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET);
3284: addr_hit[42] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET);
3285: addr_hit[43] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET);
3286: addr_hit[44] = (reg_addr == ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET);
3287: addr_hit[45] = (reg_addr == ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET);
3288: addr_hit[46] = (reg_addr == ALERT_HANDLER_CLASSC_STATE_OFFSET);
3289: addr_hit[47] = (reg_addr == ALERT_HANDLER_CLASSD_CTRL_OFFSET);
3290: addr_hit[48] = (reg_addr == ALERT_HANDLER_CLASSD_CLREN_OFFSET);
3291: addr_hit[49] = (reg_addr == ALERT_HANDLER_CLASSD_CLR_OFFSET);
3292: addr_hit[50] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET);
3293: addr_hit[51] = (reg_addr == ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET);
3294: addr_hit[52] = (reg_addr == ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET);
3295: addr_hit[53] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET);
3296: addr_hit[54] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET);
3297: addr_hit[55] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET);
3298: addr_hit[56] = (reg_addr == ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET);
3299: addr_hit[57] = (reg_addr == ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET);
3300: addr_hit[58] = (reg_addr == ALERT_HANDLER_CLASSD_STATE_OFFSET);
3301: end
3302:
3303: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
3304:
3305: // Check sub-word write is permitted
3306: always_comb begin
3307: wr_err = 1'b0;
3308: if (addr_hit[ 0] && reg_we && (ALERT_HANDLER_PERMIT[ 0] != (ALERT_HANDLER_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
3309: if (addr_hit[ 1] && reg_we && (ALERT_HANDLER_PERMIT[ 1] != (ALERT_HANDLER_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
3310: if (addr_hit[ 2] && reg_we && (ALERT_HANDLER_PERMIT[ 2] != (ALERT_HANDLER_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
3311: if (addr_hit[ 3] && reg_we && (ALERT_HANDLER_PERMIT[ 3] != (ALERT_HANDLER_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
3312: if (addr_hit[ 4] && reg_we && (ALERT_HANDLER_PERMIT[ 4] != (ALERT_HANDLER_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
3313: if (addr_hit[ 5] && reg_we && (ALERT_HANDLER_PERMIT[ 5] != (ALERT_HANDLER_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
3314: if (addr_hit[ 6] && reg_we && (ALERT_HANDLER_PERMIT[ 6] != (ALERT_HANDLER_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
3315: if (addr_hit[ 7] && reg_we && (ALERT_HANDLER_PERMIT[ 7] != (ALERT_HANDLER_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
3316: if (addr_hit[ 8] && reg_we && (ALERT_HANDLER_PERMIT[ 8] != (ALERT_HANDLER_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
3317: if (addr_hit[ 9] && reg_we && (ALERT_HANDLER_PERMIT[ 9] != (ALERT_HANDLER_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
3318: if (addr_hit[10] && reg_we && (ALERT_HANDLER_PERMIT[10] != (ALERT_HANDLER_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
3319: if (addr_hit[11] && reg_we && (ALERT_HANDLER_PERMIT[11] != (ALERT_HANDLER_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
3320: if (addr_hit[12] && reg_we && (ALERT_HANDLER_PERMIT[12] != (ALERT_HANDLER_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
3321: if (addr_hit[13] && reg_we && (ALERT_HANDLER_PERMIT[13] != (ALERT_HANDLER_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
3322: if (addr_hit[14] && reg_we && (ALERT_HANDLER_PERMIT[14] != (ALERT_HANDLER_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
3323: if (addr_hit[15] && reg_we && (ALERT_HANDLER_PERMIT[15] != (ALERT_HANDLER_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
3324: if (addr_hit[16] && reg_we && (ALERT_HANDLER_PERMIT[16] != (ALERT_HANDLER_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
3325: if (addr_hit[17] && reg_we && (ALERT_HANDLER_PERMIT[17] != (ALERT_HANDLER_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
3326: if (addr_hit[18] && reg_we && (ALERT_HANDLER_PERMIT[18] != (ALERT_HANDLER_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
3327: if (addr_hit[19] && reg_we && (ALERT_HANDLER_PERMIT[19] != (ALERT_HANDLER_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
3328: if (addr_hit[20] && reg_we && (ALERT_HANDLER_PERMIT[20] != (ALERT_HANDLER_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
3329: if (addr_hit[21] && reg_we && (ALERT_HANDLER_PERMIT[21] != (ALERT_HANDLER_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
3330: if (addr_hit[22] && reg_we && (ALERT_HANDLER_PERMIT[22] != (ALERT_HANDLER_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
3331: if (addr_hit[23] && reg_we && (ALERT_HANDLER_PERMIT[23] != (ALERT_HANDLER_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
3332: if (addr_hit[24] && reg_we && (ALERT_HANDLER_PERMIT[24] != (ALERT_HANDLER_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
3333: if (addr_hit[25] && reg_we && (ALERT_HANDLER_PERMIT[25] != (ALERT_HANDLER_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
3334: if (addr_hit[26] && reg_we && (ALERT_HANDLER_PERMIT[26] != (ALERT_HANDLER_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
3335: if (addr_hit[27] && reg_we && (ALERT_HANDLER_PERMIT[27] != (ALERT_HANDLER_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
3336: if (addr_hit[28] && reg_we && (ALERT_HANDLER_PERMIT[28] != (ALERT_HANDLER_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
3337: if (addr_hit[29] && reg_we && (ALERT_HANDLER_PERMIT[29] != (ALERT_HANDLER_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
3338: if (addr_hit[30] && reg_we && (ALERT_HANDLER_PERMIT[30] != (ALERT_HANDLER_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
3339: if (addr_hit[31] && reg_we && (ALERT_HANDLER_PERMIT[31] != (ALERT_HANDLER_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
3340: if (addr_hit[32] && reg_we && (ALERT_HANDLER_PERMIT[32] != (ALERT_HANDLER_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
3341: if (addr_hit[33] && reg_we && (ALERT_HANDLER_PERMIT[33] != (ALERT_HANDLER_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
3342: if (addr_hit[34] && reg_we && (ALERT_HANDLER_PERMIT[34] != (ALERT_HANDLER_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
3343: if (addr_hit[35] && reg_we && (ALERT_HANDLER_PERMIT[35] != (ALERT_HANDLER_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
3344: if (addr_hit[36] && reg_we && (ALERT_HANDLER_PERMIT[36] != (ALERT_HANDLER_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
3345: if (addr_hit[37] && reg_we && (ALERT_HANDLER_PERMIT[37] != (ALERT_HANDLER_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
3346: if (addr_hit[38] && reg_we && (ALERT_HANDLER_PERMIT[38] != (ALERT_HANDLER_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
3347: if (addr_hit[39] && reg_we && (ALERT_HANDLER_PERMIT[39] != (ALERT_HANDLER_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
3348: if (addr_hit[40] && reg_we && (ALERT_HANDLER_PERMIT[40] != (ALERT_HANDLER_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
3349: if (addr_hit[41] && reg_we && (ALERT_HANDLER_PERMIT[41] != (ALERT_HANDLER_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
3350: if (addr_hit[42] && reg_we && (ALERT_HANDLER_PERMIT[42] != (ALERT_HANDLER_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
3351: if (addr_hit[43] && reg_we && (ALERT_HANDLER_PERMIT[43] != (ALERT_HANDLER_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
3352: if (addr_hit[44] && reg_we && (ALERT_HANDLER_PERMIT[44] != (ALERT_HANDLER_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
3353: if (addr_hit[45] && reg_we && (ALERT_HANDLER_PERMIT[45] != (ALERT_HANDLER_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
3354: if (addr_hit[46] && reg_we && (ALERT_HANDLER_PERMIT[46] != (ALERT_HANDLER_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
3355: if (addr_hit[47] && reg_we && (ALERT_HANDLER_PERMIT[47] != (ALERT_HANDLER_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
3356: if (addr_hit[48] && reg_we && (ALERT_HANDLER_PERMIT[48] != (ALERT_HANDLER_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
3357: if (addr_hit[49] && reg_we && (ALERT_HANDLER_PERMIT[49] != (ALERT_HANDLER_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
3358: if (addr_hit[50] && reg_we && (ALERT_HANDLER_PERMIT[50] != (ALERT_HANDLER_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
3359: if (addr_hit[51] && reg_we && (ALERT_HANDLER_PERMIT[51] != (ALERT_HANDLER_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
3360: if (addr_hit[52] && reg_we && (ALERT_HANDLER_PERMIT[52] != (ALERT_HANDLER_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
3361: if (addr_hit[53] && reg_we && (ALERT_HANDLER_PERMIT[53] != (ALERT_HANDLER_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
3362: if (addr_hit[54] && reg_we && (ALERT_HANDLER_PERMIT[54] != (ALERT_HANDLER_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
3363: if (addr_hit[55] && reg_we && (ALERT_HANDLER_PERMIT[55] != (ALERT_HANDLER_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
3364: if (addr_hit[56] && reg_we && (ALERT_HANDLER_PERMIT[56] != (ALERT_HANDLER_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
3365: if (addr_hit[57] && reg_we && (ALERT_HANDLER_PERMIT[57] != (ALERT_HANDLER_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
3366: if (addr_hit[58] && reg_we && (ALERT_HANDLER_PERMIT[58] != (ALERT_HANDLER_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
3367: end
3368:
3369: assign intr_state_classa_we = addr_hit[0] & reg_we & ~wr_err;
3370: assign intr_state_classa_wd = reg_wdata[0];
3371:
3372: assign intr_state_classb_we = addr_hit[0] & reg_we & ~wr_err;
3373: assign intr_state_classb_wd = reg_wdata[1];
3374:
3375: assign intr_state_classc_we = addr_hit[0] & reg_we & ~wr_err;
3376: assign intr_state_classc_wd = reg_wdata[2];
3377:
3378: assign intr_state_classd_we = addr_hit[0] & reg_we & ~wr_err;
3379: assign intr_state_classd_wd = reg_wdata[3];
3380:
3381: assign intr_enable_classa_we = addr_hit[1] & reg_we & ~wr_err;
3382: assign intr_enable_classa_wd = reg_wdata[0];
3383:
3384: assign intr_enable_classb_we = addr_hit[1] & reg_we & ~wr_err;
3385: assign intr_enable_classb_wd = reg_wdata[1];
3386:
3387: assign intr_enable_classc_we = addr_hit[1] & reg_we & ~wr_err;
3388: assign intr_enable_classc_wd = reg_wdata[2];
3389:
3390: assign intr_enable_classd_we = addr_hit[1] & reg_we & ~wr_err;
3391: assign intr_enable_classd_wd = reg_wdata[3];
3392:
3393: assign intr_test_classa_we = addr_hit[2] & reg_we & ~wr_err;
3394: assign intr_test_classa_wd = reg_wdata[0];
3395:
3396: assign intr_test_classb_we = addr_hit[2] & reg_we & ~wr_err;
3397: assign intr_test_classb_wd = reg_wdata[1];
3398:
3399: assign intr_test_classc_we = addr_hit[2] & reg_we & ~wr_err;
3400: assign intr_test_classc_wd = reg_wdata[2];
3401:
3402: assign intr_test_classd_we = addr_hit[2] & reg_we & ~wr_err;
3403: assign intr_test_classd_wd = reg_wdata[3];
3404:
3405: assign regen_we = addr_hit[3] & reg_we & ~wr_err;
3406: assign regen_wd = reg_wdata[0];
3407:
3408: assign ping_timeout_cyc_we = addr_hit[4] & reg_we & ~wr_err;
3409: assign ping_timeout_cyc_wd = reg_wdata[23:0];
3410:
3411: assign alert_en_we = addr_hit[5] & reg_we & ~wr_err;
3412: assign alert_en_wd = reg_wdata[0];
3413:
3414: assign alert_class_we = addr_hit[6] & reg_we & ~wr_err;
3415: assign alert_class_wd = reg_wdata[1:0];
3416:
3417: assign alert_cause_we = addr_hit[7] & reg_we & ~wr_err;
3418: assign alert_cause_wd = reg_wdata[0];
3419:
3420: assign loc_alert_en_en_la0_we = addr_hit[8] & reg_we & ~wr_err;
3421: assign loc_alert_en_en_la0_wd = reg_wdata[0];
3422:
3423: assign loc_alert_en_en_la1_we = addr_hit[8] & reg_we & ~wr_err;
3424: assign loc_alert_en_en_la1_wd = reg_wdata[1];
3425:
3426: assign loc_alert_en_en_la2_we = addr_hit[8] & reg_we & ~wr_err;
3427: assign loc_alert_en_en_la2_wd = reg_wdata[2];
3428:
3429: assign loc_alert_en_en_la3_we = addr_hit[8] & reg_we & ~wr_err;
3430: assign loc_alert_en_en_la3_wd = reg_wdata[3];
3431:
3432: assign loc_alert_class_class_la0_we = addr_hit[9] & reg_we & ~wr_err;
3433: assign loc_alert_class_class_la0_wd = reg_wdata[1:0];
3434:
3435: assign loc_alert_class_class_la1_we = addr_hit[9] & reg_we & ~wr_err;
3436: assign loc_alert_class_class_la1_wd = reg_wdata[3:2];
3437:
3438: assign loc_alert_class_class_la2_we = addr_hit[9] & reg_we & ~wr_err;
3439: assign loc_alert_class_class_la2_wd = reg_wdata[5:4];
3440:
3441: assign loc_alert_class_class_la3_we = addr_hit[9] & reg_we & ~wr_err;
3442: assign loc_alert_class_class_la3_wd = reg_wdata[7:6];
3443:
3444: assign loc_alert_cause_la0_we = addr_hit[10] & reg_we & ~wr_err;
3445: assign loc_alert_cause_la0_wd = reg_wdata[0];
3446:
3447: assign loc_alert_cause_la1_we = addr_hit[10] & reg_we & ~wr_err;
3448: assign loc_alert_cause_la1_wd = reg_wdata[1];
3449:
3450: assign loc_alert_cause_la2_we = addr_hit[10] & reg_we & ~wr_err;
3451: assign loc_alert_cause_la2_wd = reg_wdata[2];
3452:
3453: assign loc_alert_cause_la3_we = addr_hit[10] & reg_we & ~wr_err;
3454: assign loc_alert_cause_la3_wd = reg_wdata[3];
3455:
3456: assign classa_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
3457: assign classa_ctrl_en_wd = reg_wdata[0];
3458:
3459: assign classa_ctrl_lock_we = addr_hit[11] & reg_we & ~wr_err;
3460: assign classa_ctrl_lock_wd = reg_wdata[1];
3461:
3462: assign classa_ctrl_en_e0_we = addr_hit[11] & reg_we & ~wr_err;
3463: assign classa_ctrl_en_e0_wd = reg_wdata[2];
3464:
3465: assign classa_ctrl_en_e1_we = addr_hit[11] & reg_we & ~wr_err;
3466: assign classa_ctrl_en_e1_wd = reg_wdata[3];
3467:
3468: assign classa_ctrl_en_e2_we = addr_hit[11] & reg_we & ~wr_err;
3469: assign classa_ctrl_en_e2_wd = reg_wdata[4];
3470:
3471: assign classa_ctrl_en_e3_we = addr_hit[11] & reg_we & ~wr_err;
3472: assign classa_ctrl_en_e3_wd = reg_wdata[5];
3473:
3474: assign classa_ctrl_map_e0_we = addr_hit[11] & reg_we & ~wr_err;
3475: assign classa_ctrl_map_e0_wd = reg_wdata[7:6];
3476:
3477: assign classa_ctrl_map_e1_we = addr_hit[11] & reg_we & ~wr_err;
3478: assign classa_ctrl_map_e1_wd = reg_wdata[9:8];
3479:
3480: assign classa_ctrl_map_e2_we = addr_hit[11] & reg_we & ~wr_err;
3481: assign classa_ctrl_map_e2_wd = reg_wdata[11:10];
3482:
3483: assign classa_ctrl_map_e3_we = addr_hit[11] & reg_we & ~wr_err;
3484: assign classa_ctrl_map_e3_wd = reg_wdata[13:12];
3485:
3486: assign classa_clren_we = addr_hit[12] & reg_we & ~wr_err;
3487: assign classa_clren_wd = reg_wdata[0];
3488:
3489: assign classa_clr_we = addr_hit[13] & reg_we & ~wr_err;
3490: assign classa_clr_wd = reg_wdata[0];
3491:
3492: assign classa_accum_cnt_re = addr_hit[14] && reg_re;
3493:
3494: assign classa_accum_thresh_we = addr_hit[15] & reg_we & ~wr_err;
3495: assign classa_accum_thresh_wd = reg_wdata[15:0];
3496:
3497: assign classa_timeout_cyc_we = addr_hit[16] & reg_we & ~wr_err;
3498: assign classa_timeout_cyc_wd = reg_wdata[31:0];
3499:
3500: assign classa_phase0_cyc_we = addr_hit[17] & reg_we & ~wr_err;
3501: assign classa_phase0_cyc_wd = reg_wdata[31:0];
3502:
3503: assign classa_phase1_cyc_we = addr_hit[18] & reg_we & ~wr_err;
3504: assign classa_phase1_cyc_wd = reg_wdata[31:0];
3505:
3506: assign classa_phase2_cyc_we = addr_hit[19] & reg_we & ~wr_err;
3507: assign classa_phase2_cyc_wd = reg_wdata[31:0];
3508:
3509: assign classa_phase3_cyc_we = addr_hit[20] & reg_we & ~wr_err;
3510: assign classa_phase3_cyc_wd = reg_wdata[31:0];
3511:
3512: assign classa_esc_cnt_re = addr_hit[21] && reg_re;
3513:
3514: assign classa_state_re = addr_hit[22] && reg_re;
3515:
3516: assign classb_ctrl_en_we = addr_hit[23] & reg_we & ~wr_err;
3517: assign classb_ctrl_en_wd = reg_wdata[0];
3518:
3519: assign classb_ctrl_lock_we = addr_hit[23] & reg_we & ~wr_err;
3520: assign classb_ctrl_lock_wd = reg_wdata[1];
3521:
3522: assign classb_ctrl_en_e0_we = addr_hit[23] & reg_we & ~wr_err;
3523: assign classb_ctrl_en_e0_wd = reg_wdata[2];
3524:
3525: assign classb_ctrl_en_e1_we = addr_hit[23] & reg_we & ~wr_err;
3526: assign classb_ctrl_en_e1_wd = reg_wdata[3];
3527:
3528: assign classb_ctrl_en_e2_we = addr_hit[23] & reg_we & ~wr_err;
3529: assign classb_ctrl_en_e2_wd = reg_wdata[4];
3530:
3531: assign classb_ctrl_en_e3_we = addr_hit[23] & reg_we & ~wr_err;
3532: assign classb_ctrl_en_e3_wd = reg_wdata[5];
3533:
3534: assign classb_ctrl_map_e0_we = addr_hit[23] & reg_we & ~wr_err;
3535: assign classb_ctrl_map_e0_wd = reg_wdata[7:6];
3536:
3537: assign classb_ctrl_map_e1_we = addr_hit[23] & reg_we & ~wr_err;
3538: assign classb_ctrl_map_e1_wd = reg_wdata[9:8];
3539:
3540: assign classb_ctrl_map_e2_we = addr_hit[23] & reg_we & ~wr_err;
3541: assign classb_ctrl_map_e2_wd = reg_wdata[11:10];
3542:
3543: assign classb_ctrl_map_e3_we = addr_hit[23] & reg_we & ~wr_err;
3544: assign classb_ctrl_map_e3_wd = reg_wdata[13:12];
3545:
3546: assign classb_clren_we = addr_hit[24] & reg_we & ~wr_err;
3547: assign classb_clren_wd = reg_wdata[0];
3548:
3549: assign classb_clr_we = addr_hit[25] & reg_we & ~wr_err;
3550: assign classb_clr_wd = reg_wdata[0];
3551:
3552: assign classb_accum_cnt_re = addr_hit[26] && reg_re;
3553:
3554: assign classb_accum_thresh_we = addr_hit[27] & reg_we & ~wr_err;
3555: assign classb_accum_thresh_wd = reg_wdata[15:0];
3556:
3557: assign classb_timeout_cyc_we = addr_hit[28] & reg_we & ~wr_err;
3558: assign classb_timeout_cyc_wd = reg_wdata[31:0];
3559:
3560: assign classb_phase0_cyc_we = addr_hit[29] & reg_we & ~wr_err;
3561: assign classb_phase0_cyc_wd = reg_wdata[31:0];
3562:
3563: assign classb_phase1_cyc_we = addr_hit[30] & reg_we & ~wr_err;
3564: assign classb_phase1_cyc_wd = reg_wdata[31:0];
3565:
3566: assign classb_phase2_cyc_we = addr_hit[31] & reg_we & ~wr_err;
3567: assign classb_phase2_cyc_wd = reg_wdata[31:0];
3568:
3569: assign classb_phase3_cyc_we = addr_hit[32] & reg_we & ~wr_err;
3570: assign classb_phase3_cyc_wd = reg_wdata[31:0];
3571:
3572: assign classb_esc_cnt_re = addr_hit[33] && reg_re;
3573:
3574: assign classb_state_re = addr_hit[34] && reg_re;
3575:
3576: assign classc_ctrl_en_we = addr_hit[35] & reg_we & ~wr_err;
3577: assign classc_ctrl_en_wd = reg_wdata[0];
3578:
3579: assign classc_ctrl_lock_we = addr_hit[35] & reg_we & ~wr_err;
3580: assign classc_ctrl_lock_wd = reg_wdata[1];
3581:
3582: assign classc_ctrl_en_e0_we = addr_hit[35] & reg_we & ~wr_err;
3583: assign classc_ctrl_en_e0_wd = reg_wdata[2];
3584:
3585: assign classc_ctrl_en_e1_we = addr_hit[35] & reg_we & ~wr_err;
3586: assign classc_ctrl_en_e1_wd = reg_wdata[3];
3587:
3588: assign classc_ctrl_en_e2_we = addr_hit[35] & reg_we & ~wr_err;
3589: assign classc_ctrl_en_e2_wd = reg_wdata[4];
3590:
3591: assign classc_ctrl_en_e3_we = addr_hit[35] & reg_we & ~wr_err;
3592: assign classc_ctrl_en_e3_wd = reg_wdata[5];
3593:
3594: assign classc_ctrl_map_e0_we = addr_hit[35] & reg_we & ~wr_err;
3595: assign classc_ctrl_map_e0_wd = reg_wdata[7:6];
3596:
3597: assign classc_ctrl_map_e1_we = addr_hit[35] & reg_we & ~wr_err;
3598: assign classc_ctrl_map_e1_wd = reg_wdata[9:8];
3599:
3600: assign classc_ctrl_map_e2_we = addr_hit[35] & reg_we & ~wr_err;
3601: assign classc_ctrl_map_e2_wd = reg_wdata[11:10];
3602:
3603: assign classc_ctrl_map_e3_we = addr_hit[35] & reg_we & ~wr_err;
3604: assign classc_ctrl_map_e3_wd = reg_wdata[13:12];
3605:
3606: assign classc_clren_we = addr_hit[36] & reg_we & ~wr_err;
3607: assign classc_clren_wd = reg_wdata[0];
3608:
3609: assign classc_clr_we = addr_hit[37] & reg_we & ~wr_err;
3610: assign classc_clr_wd = reg_wdata[0];
3611:
3612: assign classc_accum_cnt_re = addr_hit[38] && reg_re;
3613:
3614: assign classc_accum_thresh_we = addr_hit[39] & reg_we & ~wr_err;
3615: assign classc_accum_thresh_wd = reg_wdata[15:0];
3616:
3617: assign classc_timeout_cyc_we = addr_hit[40] & reg_we & ~wr_err;
3618: assign classc_timeout_cyc_wd = reg_wdata[31:0];
3619:
3620: assign classc_phase0_cyc_we = addr_hit[41] & reg_we & ~wr_err;
3621: assign classc_phase0_cyc_wd = reg_wdata[31:0];
3622:
3623: assign classc_phase1_cyc_we = addr_hit[42] & reg_we & ~wr_err;
3624: assign classc_phase1_cyc_wd = reg_wdata[31:0];
3625:
3626: assign classc_phase2_cyc_we = addr_hit[43] & reg_we & ~wr_err;
3627: assign classc_phase2_cyc_wd = reg_wdata[31:0];
3628:
3629: assign classc_phase3_cyc_we = addr_hit[44] & reg_we & ~wr_err;
3630: assign classc_phase3_cyc_wd = reg_wdata[31:0];
3631:
3632: assign classc_esc_cnt_re = addr_hit[45] && reg_re;
3633:
3634: assign classc_state_re = addr_hit[46] && reg_re;
3635:
3636: assign classd_ctrl_en_we = addr_hit[47] & reg_we & ~wr_err;
3637: assign classd_ctrl_en_wd = reg_wdata[0];
3638:
3639: assign classd_ctrl_lock_we = addr_hit[47] & reg_we & ~wr_err;
3640: assign classd_ctrl_lock_wd = reg_wdata[1];
3641:
3642: assign classd_ctrl_en_e0_we = addr_hit[47] & reg_we & ~wr_err;
3643: assign classd_ctrl_en_e0_wd = reg_wdata[2];
3644:
3645: assign classd_ctrl_en_e1_we = addr_hit[47] & reg_we & ~wr_err;
3646: assign classd_ctrl_en_e1_wd = reg_wdata[3];
3647:
3648: assign classd_ctrl_en_e2_we = addr_hit[47] & reg_we & ~wr_err;
3649: assign classd_ctrl_en_e2_wd = reg_wdata[4];
3650:
3651: assign classd_ctrl_en_e3_we = addr_hit[47] & reg_we & ~wr_err;
3652: assign classd_ctrl_en_e3_wd = reg_wdata[5];
3653:
3654: assign classd_ctrl_map_e0_we = addr_hit[47] & reg_we & ~wr_err;
3655: assign classd_ctrl_map_e0_wd = reg_wdata[7:6];
3656:
3657: assign classd_ctrl_map_e1_we = addr_hit[47] & reg_we & ~wr_err;
3658: assign classd_ctrl_map_e1_wd = reg_wdata[9:8];
3659:
3660: assign classd_ctrl_map_e2_we = addr_hit[47] & reg_we & ~wr_err;
3661: assign classd_ctrl_map_e2_wd = reg_wdata[11:10];
3662:
3663: assign classd_ctrl_map_e3_we = addr_hit[47] & reg_we & ~wr_err;
3664: assign classd_ctrl_map_e3_wd = reg_wdata[13:12];
3665:
3666: assign classd_clren_we = addr_hit[48] & reg_we & ~wr_err;
3667: assign classd_clren_wd = reg_wdata[0];
3668:
3669: assign classd_clr_we = addr_hit[49] & reg_we & ~wr_err;
3670: assign classd_clr_wd = reg_wdata[0];
3671:
3672: assign classd_accum_cnt_re = addr_hit[50] && reg_re;
3673:
3674: assign classd_accum_thresh_we = addr_hit[51] & reg_we & ~wr_err;
3675: assign classd_accum_thresh_wd = reg_wdata[15:0];
3676:
3677: assign classd_timeout_cyc_we = addr_hit[52] & reg_we & ~wr_err;
3678: assign classd_timeout_cyc_wd = reg_wdata[31:0];
3679:
3680: assign classd_phase0_cyc_we = addr_hit[53] & reg_we & ~wr_err;
3681: assign classd_phase0_cyc_wd = reg_wdata[31:0];
3682:
3683: assign classd_phase1_cyc_we = addr_hit[54] & reg_we & ~wr_err;
3684: assign classd_phase1_cyc_wd = reg_wdata[31:0];
3685:
3686: assign classd_phase2_cyc_we = addr_hit[55] & reg_we & ~wr_err;
3687: assign classd_phase2_cyc_wd = reg_wdata[31:0];
3688:
3689: assign classd_phase3_cyc_we = addr_hit[56] & reg_we & ~wr_err;
3690: assign classd_phase3_cyc_wd = reg_wdata[31:0];
3691:
3692: assign classd_esc_cnt_re = addr_hit[57] && reg_re;
3693:
3694: assign classd_state_re = addr_hit[58] && reg_re;
3695:
3696: // Read data return
3697: always_comb begin
3698: reg_rdata_next = '0;
3699: unique case (1'b1)
3700: addr_hit[0]: begin
3701: reg_rdata_next[0] = intr_state_classa_qs;
3702: reg_rdata_next[1] = intr_state_classb_qs;
3703: reg_rdata_next[2] = intr_state_classc_qs;
3704: reg_rdata_next[3] = intr_state_classd_qs;
3705: end
3706:
3707: addr_hit[1]: begin
3708: reg_rdata_next[0] = intr_enable_classa_qs;
3709: reg_rdata_next[1] = intr_enable_classb_qs;
3710: reg_rdata_next[2] = intr_enable_classc_qs;
3711: reg_rdata_next[3] = intr_enable_classd_qs;
3712: end
3713:
3714: addr_hit[2]: begin
3715: reg_rdata_next[0] = '0;
3716: reg_rdata_next[1] = '0;
3717: reg_rdata_next[2] = '0;
3718: reg_rdata_next[3] = '0;
3719: end
3720:
3721: addr_hit[3]: begin
3722: reg_rdata_next[0] = regen_qs;
3723: end
3724:
3725: addr_hit[4]: begin
3726: reg_rdata_next[23:0] = ping_timeout_cyc_qs;
3727: end
3728:
3729: addr_hit[5]: begin
3730: reg_rdata_next[0] = alert_en_qs;
3731: end
3732:
3733: addr_hit[6]: begin
3734: reg_rdata_next[1:0] = alert_class_qs;
3735: end
3736:
3737: addr_hit[7]: begin
3738: reg_rdata_next[0] = alert_cause_qs;
3739: end
3740:
3741: addr_hit[8]: begin
3742: reg_rdata_next[0] = loc_alert_en_en_la0_qs;
3743: reg_rdata_next[1] = loc_alert_en_en_la1_qs;
3744: reg_rdata_next[2] = loc_alert_en_en_la2_qs;
3745: reg_rdata_next[3] = loc_alert_en_en_la3_qs;
3746: end
3747:
3748: addr_hit[9]: begin
3749: reg_rdata_next[1:0] = loc_alert_class_class_la0_qs;
3750: reg_rdata_next[3:2] = loc_alert_class_class_la1_qs;
3751: reg_rdata_next[5:4] = loc_alert_class_class_la2_qs;
3752: reg_rdata_next[7:6] = loc_alert_class_class_la3_qs;
3753: end
3754:
3755: addr_hit[10]: begin
3756: reg_rdata_next[0] = loc_alert_cause_la0_qs;
3757: reg_rdata_next[1] = loc_alert_cause_la1_qs;
3758: reg_rdata_next[2] = loc_alert_cause_la2_qs;
3759: reg_rdata_next[3] = loc_alert_cause_la3_qs;
3760: end
3761:
3762: addr_hit[11]: begin
3763: reg_rdata_next[0] = classa_ctrl_en_qs;
3764: reg_rdata_next[1] = classa_ctrl_lock_qs;
3765: reg_rdata_next[2] = classa_ctrl_en_e0_qs;
3766: reg_rdata_next[3] = classa_ctrl_en_e1_qs;
3767: reg_rdata_next[4] = classa_ctrl_en_e2_qs;
3768: reg_rdata_next[5] = classa_ctrl_en_e3_qs;
3769: reg_rdata_next[7:6] = classa_ctrl_map_e0_qs;
3770: reg_rdata_next[9:8] = classa_ctrl_map_e1_qs;
3771: reg_rdata_next[11:10] = classa_ctrl_map_e2_qs;
3772: reg_rdata_next[13:12] = classa_ctrl_map_e3_qs;
3773: end
3774:
3775: addr_hit[12]: begin
3776: reg_rdata_next[0] = classa_clren_qs;
3777: end
3778:
3779: addr_hit[13]: begin
3780: reg_rdata_next[0] = '0;
3781: end
3782:
3783: addr_hit[14]: begin
3784: reg_rdata_next[15:0] = classa_accum_cnt_qs;
3785: end
3786:
3787: addr_hit[15]: begin
3788: reg_rdata_next[15:0] = classa_accum_thresh_qs;
3789: end
3790:
3791: addr_hit[16]: begin
3792: reg_rdata_next[31:0] = classa_timeout_cyc_qs;
3793: end
3794:
3795: addr_hit[17]: begin
3796: reg_rdata_next[31:0] = classa_phase0_cyc_qs;
3797: end
3798:
3799: addr_hit[18]: begin
3800: reg_rdata_next[31:0] = classa_phase1_cyc_qs;
3801: end
3802:
3803: addr_hit[19]: begin
3804: reg_rdata_next[31:0] = classa_phase2_cyc_qs;
3805: end
3806:
3807: addr_hit[20]: begin
3808: reg_rdata_next[31:0] = classa_phase3_cyc_qs;
3809: end
3810:
3811: addr_hit[21]: begin
3812: reg_rdata_next[31:0] = classa_esc_cnt_qs;
3813: end
3814:
3815: addr_hit[22]: begin
3816: reg_rdata_next[2:0] = classa_state_qs;
3817: end
3818:
3819: addr_hit[23]: begin
3820: reg_rdata_next[0] = classb_ctrl_en_qs;
3821: reg_rdata_next[1] = classb_ctrl_lock_qs;
3822: reg_rdata_next[2] = classb_ctrl_en_e0_qs;
3823: reg_rdata_next[3] = classb_ctrl_en_e1_qs;
3824: reg_rdata_next[4] = classb_ctrl_en_e2_qs;
3825: reg_rdata_next[5] = classb_ctrl_en_e3_qs;
3826: reg_rdata_next[7:6] = classb_ctrl_map_e0_qs;
3827: reg_rdata_next[9:8] = classb_ctrl_map_e1_qs;
3828: reg_rdata_next[11:10] = classb_ctrl_map_e2_qs;
3829: reg_rdata_next[13:12] = classb_ctrl_map_e3_qs;
3830: end
3831:
3832: addr_hit[24]: begin
3833: reg_rdata_next[0] = classb_clren_qs;
3834: end
3835:
3836: addr_hit[25]: begin
3837: reg_rdata_next[0] = '0;
3838: end
3839:
3840: addr_hit[26]: begin
3841: reg_rdata_next[15:0] = classb_accum_cnt_qs;
3842: end
3843:
3844: addr_hit[27]: begin
3845: reg_rdata_next[15:0] = classb_accum_thresh_qs;
3846: end
3847:
3848: addr_hit[28]: begin
3849: reg_rdata_next[31:0] = classb_timeout_cyc_qs;
3850: end
3851:
3852: addr_hit[29]: begin
3853: reg_rdata_next[31:0] = classb_phase0_cyc_qs;
3854: end
3855:
3856: addr_hit[30]: begin
3857: reg_rdata_next[31:0] = classb_phase1_cyc_qs;
3858: end
3859:
3860: addr_hit[31]: begin
3861: reg_rdata_next[31:0] = classb_phase2_cyc_qs;
3862: end
3863:
3864: addr_hit[32]: begin
3865: reg_rdata_next[31:0] = classb_phase3_cyc_qs;
3866: end
3867:
3868: addr_hit[33]: begin
3869: reg_rdata_next[31:0] = classb_esc_cnt_qs;
3870: end
3871:
3872: addr_hit[34]: begin
3873: reg_rdata_next[2:0] = classb_state_qs;
3874: end
3875:
3876: addr_hit[35]: begin
3877: reg_rdata_next[0] = classc_ctrl_en_qs;
3878: reg_rdata_next[1] = classc_ctrl_lock_qs;
3879: reg_rdata_next[2] = classc_ctrl_en_e0_qs;
3880: reg_rdata_next[3] = classc_ctrl_en_e1_qs;
3881: reg_rdata_next[4] = classc_ctrl_en_e2_qs;
3882: reg_rdata_next[5] = classc_ctrl_en_e3_qs;
3883: reg_rdata_next[7:6] = classc_ctrl_map_e0_qs;
3884: reg_rdata_next[9:8] = classc_ctrl_map_e1_qs;
3885: reg_rdata_next[11:10] = classc_ctrl_map_e2_qs;
3886: reg_rdata_next[13:12] = classc_ctrl_map_e3_qs;
3887: end
3888:
3889: addr_hit[36]: begin
3890: reg_rdata_next[0] = classc_clren_qs;
3891: end
3892:
3893: addr_hit[37]: begin
3894: reg_rdata_next[0] = '0;
3895: end
3896:
3897: addr_hit[38]: begin
3898: reg_rdata_next[15:0] = classc_accum_cnt_qs;
3899: end
3900:
3901: addr_hit[39]: begin
3902: reg_rdata_next[15:0] = classc_accum_thresh_qs;
3903: end
3904:
3905: addr_hit[40]: begin
3906: reg_rdata_next[31:0] = classc_timeout_cyc_qs;
3907: end
3908:
3909: addr_hit[41]: begin
3910: reg_rdata_next[31:0] = classc_phase0_cyc_qs;
3911: end
3912:
3913: addr_hit[42]: begin
3914: reg_rdata_next[31:0] = classc_phase1_cyc_qs;
3915: end
3916:
3917: addr_hit[43]: begin
3918: reg_rdata_next[31:0] = classc_phase2_cyc_qs;
3919: end
3920:
3921: addr_hit[44]: begin
3922: reg_rdata_next[31:0] = classc_phase3_cyc_qs;
3923: end
3924:
3925: addr_hit[45]: begin
3926: reg_rdata_next[31:0] = classc_esc_cnt_qs;
3927: end
3928:
3929: addr_hit[46]: begin
3930: reg_rdata_next[2:0] = classc_state_qs;
3931: end
3932:
3933: addr_hit[47]: begin
3934: reg_rdata_next[0] = classd_ctrl_en_qs;
3935: reg_rdata_next[1] = classd_ctrl_lock_qs;
3936: reg_rdata_next[2] = classd_ctrl_en_e0_qs;
3937: reg_rdata_next[3] = classd_ctrl_en_e1_qs;
3938: reg_rdata_next[4] = classd_ctrl_en_e2_qs;
3939: reg_rdata_next[5] = classd_ctrl_en_e3_qs;
3940: reg_rdata_next[7:6] = classd_ctrl_map_e0_qs;
3941: reg_rdata_next[9:8] = classd_ctrl_map_e1_qs;
3942: reg_rdata_next[11:10] = classd_ctrl_map_e2_qs;
3943: reg_rdata_next[13:12] = classd_ctrl_map_e3_qs;
3944: end
3945:
3946: addr_hit[48]: begin
3947: reg_rdata_next[0] = classd_clren_qs;
3948: end
3949:
3950: addr_hit[49]: begin
3951: reg_rdata_next[0] = '0;
3952: end
3953:
3954: addr_hit[50]: begin
3955: reg_rdata_next[15:0] = classd_accum_cnt_qs;
3956: end
3957:
3958: addr_hit[51]: begin
3959: reg_rdata_next[15:0] = classd_accum_thresh_qs;
3960: end
3961:
3962: addr_hit[52]: begin
3963: reg_rdata_next[31:0] = classd_timeout_cyc_qs;
3964: end
3965:
3966: addr_hit[53]: begin
3967: reg_rdata_next[31:0] = classd_phase0_cyc_qs;
3968: end
3969:
3970: addr_hit[54]: begin
3971: reg_rdata_next[31:0] = classd_phase1_cyc_qs;
3972: end
3973:
3974: addr_hit[55]: begin
3975: reg_rdata_next[31:0] = classd_phase2_cyc_qs;
3976: end
3977:
3978: addr_hit[56]: begin
3979: reg_rdata_next[31:0] = classd_phase3_cyc_qs;
3980: end
3981:
3982: addr_hit[57]: begin
3983: reg_rdata_next[31:0] = classd_esc_cnt_qs;
3984: end
3985:
3986: addr_hit[58]: begin
3987: reg_rdata_next[2:0] = classd_state_qs;
3988: end
3989:
3990: default: begin
3991: reg_rdata_next = '1;
3992: end
3993: endcase
3994: end
3995:
3996: // Assertions for Register Interface
3997: `ASSERT_PULSE(wePulse, reg_we)
3998: `ASSERT_PULSE(rePulse, reg_re)
3999:
4000: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
4001:
4002: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
4003:
4004: // this is formulated as an assumption such that the FPV testbenches do disprove this
4005: // property by mistake
4006: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
4007:
4008: endmodule
4009: