../src/lowrisc_ip_spi_device_0.1/rtl/spi_device_reg_pkg.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Package auto-generated by `reggen` containing data structure
   6: 
   7: package spi_device_reg_pkg;
   8: 
   9:   ////////////////////////////
  10:   // Typedefs for registers //
  11:   ////////////////////////////
  12:   typedef struct packed {
  13:     struct packed {
  14:       logic        q;
  15:     } rxf;
  16:     struct packed {
  17:       logic        q;
  18:     } rxlvl;
  19:     struct packed {
  20:       logic        q;
  21:     } txlvl;
  22:     struct packed {
  23:       logic        q;
  24:     } rxerr;
  25:     struct packed {
  26:       logic        q;
  27:     } rxoverflow;
  28:     struct packed {
  29:       logic        q;
  30:     } txunderflow;
  31:   } spi_device_reg2hw_intr_state_reg_t;
  32: 
  33:   typedef struct packed {
  34:     struct packed {
  35:       logic        q;
  36:     } rxf;
  37:     struct packed {
  38:       logic        q;
  39:     } rxlvl;
  40:     struct packed {
  41:       logic        q;
  42:     } txlvl;
  43:     struct packed {
  44:       logic        q;
  45:     } rxerr;
  46:     struct packed {
  47:       logic        q;
  48:     } rxoverflow;
  49:     struct packed {
  50:       logic        q;
  51:     } txunderflow;
  52:   } spi_device_reg2hw_intr_enable_reg_t;
  53: 
  54:   typedef struct packed {
  55:     struct packed {
  56:       logic        q;
  57:       logic        qe;
  58:     } rxf;
  59:     struct packed {
  60:       logic        q;
  61:       logic        qe;
  62:     } rxlvl;
  63:     struct packed {
  64:       logic        q;
  65:       logic        qe;
  66:     } txlvl;
  67:     struct packed {
  68:       logic        q;
  69:       logic        qe;
  70:     } rxerr;
  71:     struct packed {
  72:       logic        q;
  73:       logic        qe;
  74:     } rxoverflow;
  75:     struct packed {
  76:       logic        q;
  77:       logic        qe;
  78:     } txunderflow;
  79:   } spi_device_reg2hw_intr_test_reg_t;
  80: 
  81:   typedef struct packed {
  82:     struct packed {
  83:       logic        q;
  84:     } abort;
  85:     struct packed {
  86:       logic [1:0]  q;
  87:     } mode;
  88:     struct packed {
  89:       logic        q;
  90:     } rst_txfifo;
  91:     struct packed {
  92:       logic        q;
  93:     } rst_rxfifo;
  94:   } spi_device_reg2hw_control_reg_t;
  95: 
  96:   typedef struct packed {
  97:     struct packed {
  98:       logic        q;
  99:     } cpol;
 100:     struct packed {
 101:       logic        q;
 102:     } cpha;
 103:     struct packed {
 104:       logic        q;
 105:     } tx_order;
 106:     struct packed {
 107:       logic        q;
 108:     } rx_order;
 109:     struct packed {
 110:       logic [7:0]  q;
 111:     } timer_v;
 112:   } spi_device_reg2hw_cfg_reg_t;
 113: 
 114:   typedef struct packed {
 115:     struct packed {
 116:       logic [15:0] q;
 117:     } rxlvl;
 118:     struct packed {
 119:       logic [15:0] q;
 120:     } txlvl;
 121:   } spi_device_reg2hw_fifo_level_reg_t;
 122: 
 123:   typedef struct packed {
 124:     struct packed {
 125:       logic [15:0] q;
 126:     } rptr;
 127:   } spi_device_reg2hw_rxf_ptr_reg_t;
 128: 
 129:   typedef struct packed {
 130:     struct packed {
 131:       logic [15:0] q;
 132:     } wptr;
 133:   } spi_device_reg2hw_txf_ptr_reg_t;
 134: 
 135:   typedef struct packed {
 136:     struct packed {
 137:       logic [15:0] q;
 138:     } base;
 139:     struct packed {
 140:       logic [15:0] q;
 141:     } limit;
 142:   } spi_device_reg2hw_rxf_addr_reg_t;
 143: 
 144:   typedef struct packed {
 145:     struct packed {
 146:       logic [15:0] q;
 147:     } base;
 148:     struct packed {
 149:       logic [15:0] q;
 150:     } limit;
 151:   } spi_device_reg2hw_txf_addr_reg_t;
 152: 
 153: 
 154:   typedef struct packed {
 155:     struct packed {
 156:       logic        d;
 157:       logic        de;
 158:     } rxf;
 159:     struct packed {
 160:       logic        d;
 161:       logic        de;
 162:     } rxlvl;
 163:     struct packed {
 164:       logic        d;
 165:       logic        de;
 166:     } txlvl;
 167:     struct packed {
 168:       logic        d;
 169:       logic        de;
 170:     } rxerr;
 171:     struct packed {
 172:       logic        d;
 173:       logic        de;
 174:     } rxoverflow;
 175:     struct packed {
 176:       logic        d;
 177:       logic        de;
 178:     } txunderflow;
 179:   } spi_device_hw2reg_intr_state_reg_t;
 180: 
 181:   typedef struct packed {
 182:     struct packed {
 183:       logic [7:0]  d;
 184:     } rxlvl;
 185:     struct packed {
 186:       logic [7:0]  d;
 187:     } txlvl;
 188:   } spi_device_hw2reg_async_fifo_level_reg_t;
 189: 
 190:   typedef struct packed {
 191:     struct packed {
 192:       logic        d;
 193:     } rxf_full;
 194:     struct packed {
 195:       logic        d;
 196:     } rxf_empty;
 197:     struct packed {
 198:       logic        d;
 199:     } txf_full;
 200:     struct packed {
 201:       logic        d;
 202:     } txf_empty;
 203:     struct packed {
 204:       logic        d;
 205:     } abort_done;
 206:     struct packed {
 207:       logic        d;
 208:     } csb;
 209:   } spi_device_hw2reg_status_reg_t;
 210: 
 211:   typedef struct packed {
 212:     struct packed {
 213:       logic [15:0] d;
 214:       logic        de;
 215:     } wptr;
 216:   } spi_device_hw2reg_rxf_ptr_reg_t;
 217: 
 218:   typedef struct packed {
 219:     struct packed {
 220:       logic [15:0] d;
 221:       logic        de;
 222:     } rptr;
 223:   } spi_device_hw2reg_txf_ptr_reg_t;
 224: 
 225: 
 226:   ///////////////////////////////////////
 227:   // Register to internal design logic //
 228:   ///////////////////////////////////////
 229:   typedef struct packed {
 230:     spi_device_reg2hw_intr_state_reg_t intr_state; // [168:163]
 231:     spi_device_reg2hw_intr_enable_reg_t intr_enable; // [162:157]
 232:     spi_device_reg2hw_intr_test_reg_t intr_test; // [156:145]
 233:     spi_device_reg2hw_control_reg_t control; // [144:140]
 234:     spi_device_reg2hw_cfg_reg_t cfg; // [139:128]
 235:     spi_device_reg2hw_fifo_level_reg_t fifo_level; // [127:96]
 236:     spi_device_reg2hw_rxf_ptr_reg_t rxf_ptr; // [95:80]
 237:     spi_device_reg2hw_txf_ptr_reg_t txf_ptr; // [79:64]
 238:     spi_device_reg2hw_rxf_addr_reg_t rxf_addr; // [63:32]
 239:     spi_device_reg2hw_txf_addr_reg_t txf_addr; // [31:0]
 240:   } spi_device_reg2hw_t;
 241: 
 242:   ///////////////////////////////////////
 243:   // Internal design logic to register //
 244:   ///////////////////////////////////////
 245:   typedef struct packed {
 246:     spi_device_hw2reg_intr_state_reg_t intr_state; // [67:62]
 247:     spi_device_hw2reg_async_fifo_level_reg_t async_fifo_level; // [61:62]
 248:     spi_device_hw2reg_status_reg_t status; // [61:62]
 249:     spi_device_hw2reg_rxf_ptr_reg_t rxf_ptr; // [61:46]
 250:     spi_device_hw2reg_txf_ptr_reg_t txf_ptr; // [45:30]
 251:   } spi_device_hw2reg_t;
 252: 
 253:   // Register Address
 254:   parameter logic [11:0] SPI_DEVICE_INTR_STATE_OFFSET = 12'h 0;
 255:   parameter logic [11:0] SPI_DEVICE_INTR_ENABLE_OFFSET = 12'h 4;
 256:   parameter logic [11:0] SPI_DEVICE_INTR_TEST_OFFSET = 12'h 8;
 257:   parameter logic [11:0] SPI_DEVICE_CONTROL_OFFSET = 12'h c;
 258:   parameter logic [11:0] SPI_DEVICE_CFG_OFFSET = 12'h 10;
 259:   parameter logic [11:0] SPI_DEVICE_FIFO_LEVEL_OFFSET = 12'h 14;
 260:   parameter logic [11:0] SPI_DEVICE_ASYNC_FIFO_LEVEL_OFFSET = 12'h 18;
 261:   parameter logic [11:0] SPI_DEVICE_STATUS_OFFSET = 12'h 1c;
 262:   parameter logic [11:0] SPI_DEVICE_RXF_PTR_OFFSET = 12'h 20;
 263:   parameter logic [11:0] SPI_DEVICE_TXF_PTR_OFFSET = 12'h 24;
 264:   parameter logic [11:0] SPI_DEVICE_RXF_ADDR_OFFSET = 12'h 28;
 265:   parameter logic [11:0] SPI_DEVICE_TXF_ADDR_OFFSET = 12'h 2c;
 266: 
 267:   // Window parameter
 268:   parameter logic [11:0] SPI_DEVICE_BUFFER_OFFSET = 12'h 800;
 269:   parameter logic [11:0] SPI_DEVICE_BUFFER_SIZE   = 12'h 800;
 270: 
 271:   // Register Index
 272:   typedef enum int {
 273:     SPI_DEVICE_INTR_STATE,
 274:     SPI_DEVICE_INTR_ENABLE,
 275:     SPI_DEVICE_INTR_TEST,
 276:     SPI_DEVICE_CONTROL,
 277:     SPI_DEVICE_CFG,
 278:     SPI_DEVICE_FIFO_LEVEL,
 279:     SPI_DEVICE_ASYNC_FIFO_LEVEL,
 280:     SPI_DEVICE_STATUS,
 281:     SPI_DEVICE_RXF_PTR,
 282:     SPI_DEVICE_TXF_PTR,
 283:     SPI_DEVICE_RXF_ADDR,
 284:     SPI_DEVICE_TXF_ADDR
 285:   } spi_device_id_e;
 286: 
 287:   // Register width information to check illegal writes
 288:   parameter logic [3:0] SPI_DEVICE_PERMIT [12] = '{
 289:     4'b 0001, // index[ 0] SPI_DEVICE_INTR_STATE
 290:     4'b 0001, // index[ 1] SPI_DEVICE_INTR_ENABLE
 291:     4'b 0001, // index[ 2] SPI_DEVICE_INTR_TEST
 292:     4'b 0111, // index[ 3] SPI_DEVICE_CONTROL
 293:     4'b 0011, // index[ 4] SPI_DEVICE_CFG
 294:     4'b 1111, // index[ 5] SPI_DEVICE_FIFO_LEVEL
 295:     4'b 0111, // index[ 6] SPI_DEVICE_ASYNC_FIFO_LEVEL
 296:     4'b 0001, // index[ 7] SPI_DEVICE_STATUS
 297:     4'b 1111, // index[ 8] SPI_DEVICE_RXF_PTR
 298:     4'b 1111, // index[ 9] SPI_DEVICE_TXF_PTR
 299:     4'b 1111, // index[10] SPI_DEVICE_RXF_ADDR
 300:     4'b 1111  // index[11] SPI_DEVICE_TXF_ADDR
 301:   };
 302: endpackage
 303: 
 304: