hw/ip/tlul/rtl/tlul_err_resp.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // TL-UL error responder module, used by tlul_socket_1n to help response
   6: // to requests to no correct address space. Responses are always one cycle
   7: // after request with no stalling unless response is stuck on the way out.
   8: 
   9: module tlul_err_resp (
  10:   input                     clk_i,
  11:   input                     rst_ni,
  12:   input  tlul_pkg::tl_h2d_t tl_h_i,
  13:   output tlul_pkg::tl_d2h_t tl_h_o
  14: );
  15:   import tlul_pkg::*;
  16: 
  17:   tl_a_op_e                          err_opcode;
  18:   logic [$bits(tl_h_i.a_source)-1:0] err_source;
  19:   logic [$bits(tl_h_i.a_size)-1:0]   err_size;
  20:   logic                              err_req_pending, err_rsp_pending;
  21: 
  22:   always_ff @(posedge clk_i or negedge rst_ni) begin
  23:     if (!rst_ni) begin
  24:       err_req_pending <= 1'b0;
  25:       err_source      <= {top_pkg::TL_AIW{1'b0}};
  26:       err_opcode      <= Get;
  27:       err_size        <= '0;
  28:     end else if (tl_h_i.a_valid && tl_h_o.a_ready) begin
  29:       err_req_pending <= 1'b1;
  30:       err_source      <= tl_h_i.a_source;
  31:       err_opcode      <= tl_h_i.a_opcode;
  32:       err_size        <= tl_h_i.a_size;
  33:     end else if (!err_rsp_pending) begin
  34:       err_req_pending <= 1'b0;
  35:     end
  36:   end
  37: 
  38:   assign tl_h_o.a_ready  = ~err_rsp_pending & ~(err_req_pending & ~tl_h_i.d_ready);
  39:   assign tl_h_o.d_valid  = err_req_pending | err_rsp_pending;
  40:   assign tl_h_o.d_data   = '1; // Return all F
  41:   assign tl_h_o.d_source = err_source;
  42:   assign tl_h_o.d_sink   = '0;
  43:   assign tl_h_o.d_param  = '0;
  44:   assign tl_h_o.d_size   = err_size;
  45:   assign tl_h_o.d_opcode = (err_opcode == Get) ? AccessAckData : AccessAck;
  46:   assign tl_h_o.d_user   = '0;
  47:   assign tl_h_o.d_error  = 1'b1;
  48: 
  49:   always_ff @(posedge clk_i or negedge rst_ni) begin
  50:     if (!rst_ni) begin
  51:       err_rsp_pending <= 1'b0;
  52:     end else if ((err_req_pending || err_rsp_pending) && !tl_h_i.d_ready) begin
  53:       err_rsp_pending <= 1'b1;
  54:     end else begin
  55:       err_rsp_pending <= 1'b0;
  56:     end
  57:   end
  58: 
  59: endmodule
  60: