hw/top_earlgrey/ip/alert_handler/rtl/autogen/alert_handler_reg_pkg.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Package auto-generated by `reggen` containing data structure
   6: 
   7: package alert_handler_reg_pkg;
   8: 
   9:   // Param list
  10:   localparam int NAlerts = 1;
  11:   localparam int EscCntDw = 32;
  12:   localparam int AccuCntDw = 16;
  13:   localparam int LfsrSeed = 2147483647;
  14:   localparam logic [NAlerts-1:0] AsyncOn = 1'b0;
  15:   localparam int N_CLASSES = 4;
  16:   localparam int N_ESC_SEV = 4;
  17:   localparam int N_PHASES = 4;
  18:   localparam int N_LOC_ALERT = 4;
  19:   localparam int PING_CNT_DW = 24;
  20:   localparam int PHASE_DW = 2;
  21:   localparam int CLASS_DW = 2;
  22: 
  23:   ////////////////////////////
  24:   // Typedefs for registers //
  25:   ////////////////////////////
  26:   typedef struct packed {
  27:     struct packed {
  28:       logic        q;
  29:     } classa;
  30:     struct packed {
  31:       logic        q;
  32:     } classb;
  33:     struct packed {
  34:       logic        q;
  35:     } classc;
  36:     struct packed {
  37:       logic        q;
  38:     } classd;
  39:   } alert_handler_reg2hw_intr_state_reg_t;
  40: 
  41:   typedef struct packed {
  42:     struct packed {
  43:       logic        q;
  44:     } classa;
  45:     struct packed {
  46:       logic        q;
  47:     } classb;
  48:     struct packed {
  49:       logic        q;
  50:     } classc;
  51:     struct packed {
  52:       logic        q;
  53:     } classd;
  54:   } alert_handler_reg2hw_intr_enable_reg_t;
  55: 
  56:   typedef struct packed {
  57:     struct packed {
  58:       logic        q;
  59:       logic        qe;
  60:     } classa;
  61:     struct packed {
  62:       logic        q;
  63:       logic        qe;
  64:     } classb;
  65:     struct packed {
  66:       logic        q;
  67:       logic        qe;
  68:     } classc;
  69:     struct packed {
  70:       logic        q;
  71:       logic        qe;
  72:     } classd;
  73:   } alert_handler_reg2hw_intr_test_reg_t;
  74: 
  75:   typedef struct packed {
  76:     logic        q;
  77:   } alert_handler_reg2hw_regen_reg_t;
  78: 
  79:   typedef struct packed {
  80:     logic [23:0] q;
  81:   } alert_handler_reg2hw_ping_timeout_cyc_reg_t;
  82: 
  83:   typedef struct packed {
  84:     logic        q;
  85:   } alert_handler_reg2hw_alert_en_mreg_t;
  86: 
  87:   typedef struct packed {
  88:     logic [1:0]  q;
  89:   } alert_handler_reg2hw_alert_class_mreg_t;
  90: 
  91:   typedef struct packed {
  92:     logic        q;
  93:   } alert_handler_reg2hw_alert_cause_mreg_t;
  94: 
  95:   typedef struct packed {
  96:     logic        q;
  97:   } alert_handler_reg2hw_loc_alert_en_mreg_t;
  98: 
  99:   typedef struct packed {
 100:     logic [1:0]  q;
 101:   } alert_handler_reg2hw_loc_alert_class_mreg_t;
 102: 
 103:   typedef struct packed {
 104:     logic        q;
 105:   } alert_handler_reg2hw_loc_alert_cause_mreg_t;
 106: 
 107:   typedef struct packed {
 108:     struct packed {
 109:       logic        q;
 110:     } en;
 111:     struct packed {
 112:       logic        q;
 113:     } lock;
 114:     struct packed {
 115:       logic        q;
 116:     } en_e0;
 117:     struct packed {
 118:       logic        q;
 119:     } en_e1;
 120:     struct packed {
 121:       logic        q;
 122:     } en_e2;
 123:     struct packed {
 124:       logic        q;
 125:     } en_e3;
 126:     struct packed {
 127:       logic [1:0]  q;
 128:     } map_e0;
 129:     struct packed {
 130:       logic [1:0]  q;
 131:     } map_e1;
 132:     struct packed {
 133:       logic [1:0]  q;
 134:     } map_e2;
 135:     struct packed {
 136:       logic [1:0]  q;
 137:     } map_e3;
 138:   } alert_handler_reg2hw_classa_ctrl_reg_t;
 139: 
 140:   typedef struct packed {
 141:     logic        q;
 142:     logic        qe;
 143:   } alert_handler_reg2hw_classa_clr_reg_t;
 144: 
 145:   typedef struct packed {
 146:     logic [15:0] q;
 147:   } alert_handler_reg2hw_classa_accum_thresh_reg_t;
 148: 
 149:   typedef struct packed {
 150:     logic [31:0] q;
 151:   } alert_handler_reg2hw_classa_timeout_cyc_reg_t;
 152: 
 153:   typedef struct packed {
 154:     logic [31:0] q;
 155:   } alert_handler_reg2hw_classa_phase0_cyc_reg_t;
 156: 
 157:   typedef struct packed {
 158:     logic [31:0] q;
 159:   } alert_handler_reg2hw_classa_phase1_cyc_reg_t;
 160: 
 161:   typedef struct packed {
 162:     logic [31:0] q;
 163:   } alert_handler_reg2hw_classa_phase2_cyc_reg_t;
 164: 
 165:   typedef struct packed {
 166:     logic [31:0] q;
 167:   } alert_handler_reg2hw_classa_phase3_cyc_reg_t;
 168: 
 169:   typedef struct packed {
 170:     struct packed {
 171:       logic        q;
 172:     } en;
 173:     struct packed {
 174:       logic        q;
 175:     } lock;
 176:     struct packed {
 177:       logic        q;
 178:     } en_e0;
 179:     struct packed {
 180:       logic        q;
 181:     } en_e1;
 182:     struct packed {
 183:       logic        q;
 184:     } en_e2;
 185:     struct packed {
 186:       logic        q;
 187:     } en_e3;
 188:     struct packed {
 189:       logic [1:0]  q;
 190:     } map_e0;
 191:     struct packed {
 192:       logic [1:0]  q;
 193:     } map_e1;
 194:     struct packed {
 195:       logic [1:0]  q;
 196:     } map_e2;
 197:     struct packed {
 198:       logic [1:0]  q;
 199:     } map_e3;
 200:   } alert_handler_reg2hw_classb_ctrl_reg_t;
 201: 
 202:   typedef struct packed {
 203:     logic        q;
 204:     logic        qe;
 205:   } alert_handler_reg2hw_classb_clr_reg_t;
 206: 
 207:   typedef struct packed {
 208:     logic [15:0] q;
 209:   } alert_handler_reg2hw_classb_accum_thresh_reg_t;
 210: 
 211:   typedef struct packed {
 212:     logic [31:0] q;
 213:   } alert_handler_reg2hw_classb_timeout_cyc_reg_t;
 214: 
 215:   typedef struct packed {
 216:     logic [31:0] q;
 217:   } alert_handler_reg2hw_classb_phase0_cyc_reg_t;
 218: 
 219:   typedef struct packed {
 220:     logic [31:0] q;
 221:   } alert_handler_reg2hw_classb_phase1_cyc_reg_t;
 222: 
 223:   typedef struct packed {
 224:     logic [31:0] q;
 225:   } alert_handler_reg2hw_classb_phase2_cyc_reg_t;
 226: 
 227:   typedef struct packed {
 228:     logic [31:0] q;
 229:   } alert_handler_reg2hw_classb_phase3_cyc_reg_t;
 230: 
 231:   typedef struct packed {
 232:     struct packed {
 233:       logic        q;
 234:     } en;
 235:     struct packed {
 236:       logic        q;
 237:     } lock;
 238:     struct packed {
 239:       logic        q;
 240:     } en_e0;
 241:     struct packed {
 242:       logic        q;
 243:     } en_e1;
 244:     struct packed {
 245:       logic        q;
 246:     } en_e2;
 247:     struct packed {
 248:       logic        q;
 249:     } en_e3;
 250:     struct packed {
 251:       logic [1:0]  q;
 252:     } map_e0;
 253:     struct packed {
 254:       logic [1:0]  q;
 255:     } map_e1;
 256:     struct packed {
 257:       logic [1:0]  q;
 258:     } map_e2;
 259:     struct packed {
 260:       logic [1:0]  q;
 261:     } map_e3;
 262:   } alert_handler_reg2hw_classc_ctrl_reg_t;
 263: 
 264:   typedef struct packed {
 265:     logic        q;
 266:     logic        qe;
 267:   } alert_handler_reg2hw_classc_clr_reg_t;
 268: 
 269:   typedef struct packed {
 270:     logic [15:0] q;
 271:   } alert_handler_reg2hw_classc_accum_thresh_reg_t;
 272: 
 273:   typedef struct packed {
 274:     logic [31:0] q;
 275:   } alert_handler_reg2hw_classc_timeout_cyc_reg_t;
 276: 
 277:   typedef struct packed {
 278:     logic [31:0] q;
 279:   } alert_handler_reg2hw_classc_phase0_cyc_reg_t;
 280: 
 281:   typedef struct packed {
 282:     logic [31:0] q;
 283:   } alert_handler_reg2hw_classc_phase1_cyc_reg_t;
 284: 
 285:   typedef struct packed {
 286:     logic [31:0] q;
 287:   } alert_handler_reg2hw_classc_phase2_cyc_reg_t;
 288: 
 289:   typedef struct packed {
 290:     logic [31:0] q;
 291:   } alert_handler_reg2hw_classc_phase3_cyc_reg_t;
 292: 
 293:   typedef struct packed {
 294:     struct packed {
 295:       logic        q;
 296:     } en;
 297:     struct packed {
 298:       logic        q;
 299:     } lock;
 300:     struct packed {
 301:       logic        q;
 302:     } en_e0;
 303:     struct packed {
 304:       logic        q;
 305:     } en_e1;
 306:     struct packed {
 307:       logic        q;
 308:     } en_e2;
 309:     struct packed {
 310:       logic        q;
 311:     } en_e3;
 312:     struct packed {
 313:       logic [1:0]  q;
 314:     } map_e0;
 315:     struct packed {
 316:       logic [1:0]  q;
 317:     } map_e1;
 318:     struct packed {
 319:       logic [1:0]  q;
 320:     } map_e2;
 321:     struct packed {
 322:       logic [1:0]  q;
 323:     } map_e3;
 324:   } alert_handler_reg2hw_classd_ctrl_reg_t;
 325: 
 326:   typedef struct packed {
 327:     logic        q;
 328:     logic        qe;
 329:   } alert_handler_reg2hw_classd_clr_reg_t;
 330: 
 331:   typedef struct packed {
 332:     logic [15:0] q;
 333:   } alert_handler_reg2hw_classd_accum_thresh_reg_t;
 334: 
 335:   typedef struct packed {
 336:     logic [31:0] q;
 337:   } alert_handler_reg2hw_classd_timeout_cyc_reg_t;
 338: 
 339:   typedef struct packed {
 340:     logic [31:0] q;
 341:   } alert_handler_reg2hw_classd_phase0_cyc_reg_t;
 342: 
 343:   typedef struct packed {
 344:     logic [31:0] q;
 345:   } alert_handler_reg2hw_classd_phase1_cyc_reg_t;
 346: 
 347:   typedef struct packed {
 348:     logic [31:0] q;
 349:   } alert_handler_reg2hw_classd_phase2_cyc_reg_t;
 350: 
 351:   typedef struct packed {
 352:     logic [31:0] q;
 353:   } alert_handler_reg2hw_classd_phase3_cyc_reg_t;
 354: 
 355: 
 356:   typedef struct packed {
 357:     struct packed {
 358:       logic        d;
 359:       logic        de;
 360:     } classa;
 361:     struct packed {
 362:       logic        d;
 363:       logic        de;
 364:     } classb;
 365:     struct packed {
 366:       logic        d;
 367:       logic        de;
 368:     } classc;
 369:     struct packed {
 370:       logic        d;
 371:       logic        de;
 372:     } classd;
 373:   } alert_handler_hw2reg_intr_state_reg_t;
 374: 
 375:   typedef struct packed {
 376:     logic        d;
 377:     logic        de;
 378:   } alert_handler_hw2reg_alert_cause_mreg_t;
 379: 
 380:   typedef struct packed {
 381:     logic        d;
 382:     logic        de;
 383:   } alert_handler_hw2reg_loc_alert_cause_mreg_t;
 384: 
 385:   typedef struct packed {
 386:     logic        d;
 387:     logic        de;
 388:   } alert_handler_hw2reg_classa_clren_reg_t;
 389: 
 390:   typedef struct packed {
 391:     logic [15:0] d;
 392:   } alert_handler_hw2reg_classa_accum_cnt_reg_t;
 393: 
 394:   typedef struct packed {
 395:     logic [31:0] d;
 396:   } alert_handler_hw2reg_classa_esc_cnt_reg_t;
 397: 
 398:   typedef struct packed {
 399:     logic [2:0]  d;
 400:   } alert_handler_hw2reg_classa_state_reg_t;
 401: 
 402:   typedef struct packed {
 403:     logic        d;
 404:     logic        de;
 405:   } alert_handler_hw2reg_classb_clren_reg_t;
 406: 
 407:   typedef struct packed {
 408:     logic [15:0] d;
 409:   } alert_handler_hw2reg_classb_accum_cnt_reg_t;
 410: 
 411:   typedef struct packed {
 412:     logic [31:0] d;
 413:   } alert_handler_hw2reg_classb_esc_cnt_reg_t;
 414: 
 415:   typedef struct packed {
 416:     logic [2:0]  d;
 417:   } alert_handler_hw2reg_classb_state_reg_t;
 418: 
 419:   typedef struct packed {
 420:     logic        d;
 421:     logic        de;
 422:   } alert_handler_hw2reg_classc_clren_reg_t;
 423: 
 424:   typedef struct packed {
 425:     logic [15:0] d;
 426:   } alert_handler_hw2reg_classc_accum_cnt_reg_t;
 427: 
 428:   typedef struct packed {
 429:     logic [31:0] d;
 430:   } alert_handler_hw2reg_classc_esc_cnt_reg_t;
 431: 
 432:   typedef struct packed {
 433:     logic [2:0]  d;
 434:   } alert_handler_hw2reg_classc_state_reg_t;
 435: 
 436:   typedef struct packed {
 437:     logic        d;
 438:     logic        de;
 439:   } alert_handler_hw2reg_classd_clren_reg_t;
 440: 
 441:   typedef struct packed {
 442:     logic [15:0] d;
 443:   } alert_handler_hw2reg_classd_accum_cnt_reg_t;
 444: 
 445:   typedef struct packed {
 446:     logic [31:0] d;
 447:   } alert_handler_hw2reg_classd_esc_cnt_reg_t;
 448: 
 449:   typedef struct packed {
 450:     logic [2:0]  d;
 451:   } alert_handler_hw2reg_classd_state_reg_t;
 452: 
 453: 
 454:   ///////////////////////////////////////
 455:   // Register to internal design logic //
 456:   ///////////////////////////////////////
 457:   typedef struct packed {
 458:     alert_handler_reg2hw_intr_state_reg_t intr_state; // [828:825]
 459:     alert_handler_reg2hw_intr_enable_reg_t intr_enable; // [824:821]
 460:     alert_handler_reg2hw_intr_test_reg_t intr_test; // [820:813]
 461:     alert_handler_reg2hw_regen_reg_t regen; // [812:812]
 462:     alert_handler_reg2hw_ping_timeout_cyc_reg_t ping_timeout_cyc; // [811:788]
 463:     alert_handler_reg2hw_alert_en_mreg_t [0:0] alert_en; // [787:787]
 464:     alert_handler_reg2hw_alert_class_mreg_t [0:0] alert_class; // [786:785]
 465:     alert_handler_reg2hw_alert_cause_mreg_t [0:0] alert_cause; // [784:784]
 466:     alert_handler_reg2hw_loc_alert_en_mreg_t [3:0] loc_alert_en; // [783:780]
 467:     alert_handler_reg2hw_loc_alert_class_mreg_t [3:0] loc_alert_class; // [779:772]
 468:     alert_handler_reg2hw_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [771:768]
 469:     alert_handler_reg2hw_classa_ctrl_reg_t classa_ctrl; // [767:754]
 470:     alert_handler_reg2hw_classa_clr_reg_t classa_clr; // [753:752]
 471:     alert_handler_reg2hw_classa_accum_thresh_reg_t classa_accum_thresh; // [751:736]
 472:     alert_handler_reg2hw_classa_timeout_cyc_reg_t classa_timeout_cyc; // [735:704]
 473:     alert_handler_reg2hw_classa_phase0_cyc_reg_t classa_phase0_cyc; // [703:672]
 474:     alert_handler_reg2hw_classa_phase1_cyc_reg_t classa_phase1_cyc; // [671:640]
 475:     alert_handler_reg2hw_classa_phase2_cyc_reg_t classa_phase2_cyc; // [639:608]
 476:     alert_handler_reg2hw_classa_phase3_cyc_reg_t classa_phase3_cyc; // [607:576]
 477:     alert_handler_reg2hw_classb_ctrl_reg_t classb_ctrl; // [575:562]
 478:     alert_handler_reg2hw_classb_clr_reg_t classb_clr; // [561:560]
 479:     alert_handler_reg2hw_classb_accum_thresh_reg_t classb_accum_thresh; // [559:544]
 480:     alert_handler_reg2hw_classb_timeout_cyc_reg_t classb_timeout_cyc; // [543:512]
 481:     alert_handler_reg2hw_classb_phase0_cyc_reg_t classb_phase0_cyc; // [511:480]
 482:     alert_handler_reg2hw_classb_phase1_cyc_reg_t classb_phase1_cyc; // [479:448]
 483:     alert_handler_reg2hw_classb_phase2_cyc_reg_t classb_phase2_cyc; // [447:416]
 484:     alert_handler_reg2hw_classb_phase3_cyc_reg_t classb_phase3_cyc; // [415:384]
 485:     alert_handler_reg2hw_classc_ctrl_reg_t classc_ctrl; // [383:370]
 486:     alert_handler_reg2hw_classc_clr_reg_t classc_clr; // [369:368]
 487:     alert_handler_reg2hw_classc_accum_thresh_reg_t classc_accum_thresh; // [367:352]
 488:     alert_handler_reg2hw_classc_timeout_cyc_reg_t classc_timeout_cyc; // [351:320]
 489:     alert_handler_reg2hw_classc_phase0_cyc_reg_t classc_phase0_cyc; // [319:288]
 490:     alert_handler_reg2hw_classc_phase1_cyc_reg_t classc_phase1_cyc; // [287:256]
 491:     alert_handler_reg2hw_classc_phase2_cyc_reg_t classc_phase2_cyc; // [255:224]
 492:     alert_handler_reg2hw_classc_phase3_cyc_reg_t classc_phase3_cyc; // [223:192]
 493:     alert_handler_reg2hw_classd_ctrl_reg_t classd_ctrl; // [191:178]
 494:     alert_handler_reg2hw_classd_clr_reg_t classd_clr; // [177:176]
 495:     alert_handler_reg2hw_classd_accum_thresh_reg_t classd_accum_thresh; // [175:160]
 496:     alert_handler_reg2hw_classd_timeout_cyc_reg_t classd_timeout_cyc; // [159:128]
 497:     alert_handler_reg2hw_classd_phase0_cyc_reg_t classd_phase0_cyc; // [127:96]
 498:     alert_handler_reg2hw_classd_phase1_cyc_reg_t classd_phase1_cyc; // [95:64]
 499:     alert_handler_reg2hw_classd_phase2_cyc_reg_t classd_phase2_cyc; // [63:32]
 500:     alert_handler_reg2hw_classd_phase3_cyc_reg_t classd_phase3_cyc; // [31:0]
 501:   } alert_handler_reg2hw_t;
 502: 
 503:   ///////////////////////////////////////
 504:   // Internal design logic to register //
 505:   ///////////////////////////////////////
 506:   typedef struct packed {
 507:     alert_handler_hw2reg_intr_state_reg_t intr_state; // [229:226]
 508:     alert_handler_hw2reg_alert_cause_mreg_t [0:0] alert_cause; // [225:224]
 509:     alert_handler_hw2reg_loc_alert_cause_mreg_t [3:0] loc_alert_cause; // [223:216]
 510:     alert_handler_hw2reg_classa_clren_reg_t classa_clren; // [215:216]
 511:     alert_handler_hw2reg_classa_accum_cnt_reg_t classa_accum_cnt; // [215:216]
 512:     alert_handler_hw2reg_classa_esc_cnt_reg_t classa_esc_cnt; // [215:216]
 513:     alert_handler_hw2reg_classa_state_reg_t classa_state; // [215:216]
 514:     alert_handler_hw2reg_classb_clren_reg_t classb_clren; // [215:216]
 515:     alert_handler_hw2reg_classb_accum_cnt_reg_t classb_accum_cnt; // [215:216]
 516:     alert_handler_hw2reg_classb_esc_cnt_reg_t classb_esc_cnt; // [215:216]
 517:     alert_handler_hw2reg_classb_state_reg_t classb_state; // [215:216]
 518:     alert_handler_hw2reg_classc_clren_reg_t classc_clren; // [215:216]
 519:     alert_handler_hw2reg_classc_accum_cnt_reg_t classc_accum_cnt; // [215:216]
 520:     alert_handler_hw2reg_classc_esc_cnt_reg_t classc_esc_cnt; // [215:216]
 521:     alert_handler_hw2reg_classc_state_reg_t classc_state; // [215:216]
 522:     alert_handler_hw2reg_classd_clren_reg_t classd_clren; // [215:216]
 523:     alert_handler_hw2reg_classd_accum_cnt_reg_t classd_accum_cnt; // [215:216]
 524:     alert_handler_hw2reg_classd_esc_cnt_reg_t classd_esc_cnt; // [215:216]
 525:     alert_handler_hw2reg_classd_state_reg_t classd_state; // [215:216]
 526:   } alert_handler_hw2reg_t;
 527: 
 528:   // Register Address
 529:   parameter ALERT_HANDLER_INTR_STATE_OFFSET = 8'h 0;
 530:   parameter ALERT_HANDLER_INTR_ENABLE_OFFSET = 8'h 4;
 531:   parameter ALERT_HANDLER_INTR_TEST_OFFSET = 8'h 8;
 532:   parameter ALERT_HANDLER_REGEN_OFFSET = 8'h c;
 533:   parameter ALERT_HANDLER_PING_TIMEOUT_CYC_OFFSET = 8'h 10;
 534:   parameter ALERT_HANDLER_ALERT_EN_OFFSET = 8'h 14;
 535:   parameter ALERT_HANDLER_ALERT_CLASS_OFFSET = 8'h 18;
 536:   parameter ALERT_HANDLER_ALERT_CAUSE_OFFSET = 8'h 1c;
 537:   parameter ALERT_HANDLER_LOC_ALERT_EN_OFFSET = 8'h 20;
 538:   parameter ALERT_HANDLER_LOC_ALERT_CLASS_OFFSET = 8'h 24;
 539:   parameter ALERT_HANDLER_LOC_ALERT_CAUSE_OFFSET = 8'h 28;
 540:   parameter ALERT_HANDLER_CLASSA_CTRL_OFFSET = 8'h 2c;
 541:   parameter ALERT_HANDLER_CLASSA_CLREN_OFFSET = 8'h 30;
 542:   parameter ALERT_HANDLER_CLASSA_CLR_OFFSET = 8'h 34;
 543:   parameter ALERT_HANDLER_CLASSA_ACCUM_CNT_OFFSET = 8'h 38;
 544:   parameter ALERT_HANDLER_CLASSA_ACCUM_THRESH_OFFSET = 8'h 3c;
 545:   parameter ALERT_HANDLER_CLASSA_TIMEOUT_CYC_OFFSET = 8'h 40;
 546:   parameter ALERT_HANDLER_CLASSA_PHASE0_CYC_OFFSET = 8'h 44;
 547:   parameter ALERT_HANDLER_CLASSA_PHASE1_CYC_OFFSET = 8'h 48;
 548:   parameter ALERT_HANDLER_CLASSA_PHASE2_CYC_OFFSET = 8'h 4c;
 549:   parameter ALERT_HANDLER_CLASSA_PHASE3_CYC_OFFSET = 8'h 50;
 550:   parameter ALERT_HANDLER_CLASSA_ESC_CNT_OFFSET = 8'h 54;
 551:   parameter ALERT_HANDLER_CLASSA_STATE_OFFSET = 8'h 58;
 552:   parameter ALERT_HANDLER_CLASSB_CTRL_OFFSET = 8'h 5c;
 553:   parameter ALERT_HANDLER_CLASSB_CLREN_OFFSET = 8'h 60;
 554:   parameter ALERT_HANDLER_CLASSB_CLR_OFFSET = 8'h 64;
 555:   parameter ALERT_HANDLER_CLASSB_ACCUM_CNT_OFFSET = 8'h 68;
 556:   parameter ALERT_HANDLER_CLASSB_ACCUM_THRESH_OFFSET = 8'h 6c;
 557:   parameter ALERT_HANDLER_CLASSB_TIMEOUT_CYC_OFFSET = 8'h 70;
 558:   parameter ALERT_HANDLER_CLASSB_PHASE0_CYC_OFFSET = 8'h 74;
 559:   parameter ALERT_HANDLER_CLASSB_PHASE1_CYC_OFFSET = 8'h 78;
 560:   parameter ALERT_HANDLER_CLASSB_PHASE2_CYC_OFFSET = 8'h 7c;
 561:   parameter ALERT_HANDLER_CLASSB_PHASE3_CYC_OFFSET = 8'h 80;
 562:   parameter ALERT_HANDLER_CLASSB_ESC_CNT_OFFSET = 8'h 84;
 563:   parameter ALERT_HANDLER_CLASSB_STATE_OFFSET = 8'h 88;
 564:   parameter ALERT_HANDLER_CLASSC_CTRL_OFFSET = 8'h 8c;
 565:   parameter ALERT_HANDLER_CLASSC_CLREN_OFFSET = 8'h 90;
 566:   parameter ALERT_HANDLER_CLASSC_CLR_OFFSET = 8'h 94;
 567:   parameter ALERT_HANDLER_CLASSC_ACCUM_CNT_OFFSET = 8'h 98;
 568:   parameter ALERT_HANDLER_CLASSC_ACCUM_THRESH_OFFSET = 8'h 9c;
 569:   parameter ALERT_HANDLER_CLASSC_TIMEOUT_CYC_OFFSET = 8'h a0;
 570:   parameter ALERT_HANDLER_CLASSC_PHASE0_CYC_OFFSET = 8'h a4;
 571:   parameter ALERT_HANDLER_CLASSC_PHASE1_CYC_OFFSET = 8'h a8;
 572:   parameter ALERT_HANDLER_CLASSC_PHASE2_CYC_OFFSET = 8'h ac;
 573:   parameter ALERT_HANDLER_CLASSC_PHASE3_CYC_OFFSET = 8'h b0;
 574:   parameter ALERT_HANDLER_CLASSC_ESC_CNT_OFFSET = 8'h b4;
 575:   parameter ALERT_HANDLER_CLASSC_STATE_OFFSET = 8'h b8;
 576:   parameter ALERT_HANDLER_CLASSD_CTRL_OFFSET = 8'h bc;
 577:   parameter ALERT_HANDLER_CLASSD_CLREN_OFFSET = 8'h c0;
 578:   parameter ALERT_HANDLER_CLASSD_CLR_OFFSET = 8'h c4;
 579:   parameter ALERT_HANDLER_CLASSD_ACCUM_CNT_OFFSET = 8'h c8;
 580:   parameter ALERT_HANDLER_CLASSD_ACCUM_THRESH_OFFSET = 8'h cc;
 581:   parameter ALERT_HANDLER_CLASSD_TIMEOUT_CYC_OFFSET = 8'h d0;
 582:   parameter ALERT_HANDLER_CLASSD_PHASE0_CYC_OFFSET = 8'h d4;
 583:   parameter ALERT_HANDLER_CLASSD_PHASE1_CYC_OFFSET = 8'h d8;
 584:   parameter ALERT_HANDLER_CLASSD_PHASE2_CYC_OFFSET = 8'h dc;
 585:   parameter ALERT_HANDLER_CLASSD_PHASE3_CYC_OFFSET = 8'h e0;
 586:   parameter ALERT_HANDLER_CLASSD_ESC_CNT_OFFSET = 8'h e4;
 587:   parameter ALERT_HANDLER_CLASSD_STATE_OFFSET = 8'h e8;
 588: 
 589: 
 590:   // Register Index
 591:   typedef enum int {
 592:     ALERT_HANDLER_INTR_STATE,
 593:     ALERT_HANDLER_INTR_ENABLE,
 594:     ALERT_HANDLER_INTR_TEST,
 595:     ALERT_HANDLER_REGEN,
 596:     ALERT_HANDLER_PING_TIMEOUT_CYC,
 597:     ALERT_HANDLER_ALERT_EN,
 598:     ALERT_HANDLER_ALERT_CLASS,
 599:     ALERT_HANDLER_ALERT_CAUSE,
 600:     ALERT_HANDLER_LOC_ALERT_EN,
 601:     ALERT_HANDLER_LOC_ALERT_CLASS,
 602:     ALERT_HANDLER_LOC_ALERT_CAUSE,
 603:     ALERT_HANDLER_CLASSA_CTRL,
 604:     ALERT_HANDLER_CLASSA_CLREN,
 605:     ALERT_HANDLER_CLASSA_CLR,
 606:     ALERT_HANDLER_CLASSA_ACCUM_CNT,
 607:     ALERT_HANDLER_CLASSA_ACCUM_THRESH,
 608:     ALERT_HANDLER_CLASSA_TIMEOUT_CYC,
 609:     ALERT_HANDLER_CLASSA_PHASE0_CYC,
 610:     ALERT_HANDLER_CLASSA_PHASE1_CYC,
 611:     ALERT_HANDLER_CLASSA_PHASE2_CYC,
 612:     ALERT_HANDLER_CLASSA_PHASE3_CYC,
 613:     ALERT_HANDLER_CLASSA_ESC_CNT,
 614:     ALERT_HANDLER_CLASSA_STATE,
 615:     ALERT_HANDLER_CLASSB_CTRL,
 616:     ALERT_HANDLER_CLASSB_CLREN,
 617:     ALERT_HANDLER_CLASSB_CLR,
 618:     ALERT_HANDLER_CLASSB_ACCUM_CNT,
 619:     ALERT_HANDLER_CLASSB_ACCUM_THRESH,
 620:     ALERT_HANDLER_CLASSB_TIMEOUT_CYC,
 621:     ALERT_HANDLER_CLASSB_PHASE0_CYC,
 622:     ALERT_HANDLER_CLASSB_PHASE1_CYC,
 623:     ALERT_HANDLER_CLASSB_PHASE2_CYC,
 624:     ALERT_HANDLER_CLASSB_PHASE3_CYC,
 625:     ALERT_HANDLER_CLASSB_ESC_CNT,
 626:     ALERT_HANDLER_CLASSB_STATE,
 627:     ALERT_HANDLER_CLASSC_CTRL,
 628:     ALERT_HANDLER_CLASSC_CLREN,
 629:     ALERT_HANDLER_CLASSC_CLR,
 630:     ALERT_HANDLER_CLASSC_ACCUM_CNT,
 631:     ALERT_HANDLER_CLASSC_ACCUM_THRESH,
 632:     ALERT_HANDLER_CLASSC_TIMEOUT_CYC,
 633:     ALERT_HANDLER_CLASSC_PHASE0_CYC,
 634:     ALERT_HANDLER_CLASSC_PHASE1_CYC,
 635:     ALERT_HANDLER_CLASSC_PHASE2_CYC,
 636:     ALERT_HANDLER_CLASSC_PHASE3_CYC,
 637:     ALERT_HANDLER_CLASSC_ESC_CNT,
 638:     ALERT_HANDLER_CLASSC_STATE,
 639:     ALERT_HANDLER_CLASSD_CTRL,
 640:     ALERT_HANDLER_CLASSD_CLREN,
 641:     ALERT_HANDLER_CLASSD_CLR,
 642:     ALERT_HANDLER_CLASSD_ACCUM_CNT,
 643:     ALERT_HANDLER_CLASSD_ACCUM_THRESH,
 644:     ALERT_HANDLER_CLASSD_TIMEOUT_CYC,
 645:     ALERT_HANDLER_CLASSD_PHASE0_CYC,
 646:     ALERT_HANDLER_CLASSD_PHASE1_CYC,
 647:     ALERT_HANDLER_CLASSD_PHASE2_CYC,
 648:     ALERT_HANDLER_CLASSD_PHASE3_CYC,
 649:     ALERT_HANDLER_CLASSD_ESC_CNT,
 650:     ALERT_HANDLER_CLASSD_STATE
 651:   } alert_handler_id_e;
 652: 
 653:   // Register width information to check illegal writes
 654:   localparam logic [3:0] ALERT_HANDLER_PERMIT [59] = '{
 655:     4'b 0001, // index[ 0] ALERT_HANDLER_INTR_STATE
 656:     4'b 0001, // index[ 1] ALERT_HANDLER_INTR_ENABLE
 657:     4'b 0001, // index[ 2] ALERT_HANDLER_INTR_TEST
 658:     4'b 0001, // index[ 3] ALERT_HANDLER_REGEN
 659:     4'b 0111, // index[ 4] ALERT_HANDLER_PING_TIMEOUT_CYC
 660:     4'b 0001, // index[ 5] ALERT_HANDLER_ALERT_EN
 661:     4'b 0001, // index[ 6] ALERT_HANDLER_ALERT_CLASS
 662:     4'b 0001, // index[ 7] ALERT_HANDLER_ALERT_CAUSE
 663:     4'b 0001, // index[ 8] ALERT_HANDLER_LOC_ALERT_EN
 664:     4'b 0001, // index[ 9] ALERT_HANDLER_LOC_ALERT_CLASS
 665:     4'b 0001, // index[10] ALERT_HANDLER_LOC_ALERT_CAUSE
 666:     4'b 0011, // index[11] ALERT_HANDLER_CLASSA_CTRL
 667:     4'b 0001, // index[12] ALERT_HANDLER_CLASSA_CLREN
 668:     4'b 0001, // index[13] ALERT_HANDLER_CLASSA_CLR
 669:     4'b 0011, // index[14] ALERT_HANDLER_CLASSA_ACCUM_CNT
 670:     4'b 0011, // index[15] ALERT_HANDLER_CLASSA_ACCUM_THRESH
 671:     4'b 1111, // index[16] ALERT_HANDLER_CLASSA_TIMEOUT_CYC
 672:     4'b 1111, // index[17] ALERT_HANDLER_CLASSA_PHASE0_CYC
 673:     4'b 1111, // index[18] ALERT_HANDLER_CLASSA_PHASE1_CYC
 674:     4'b 1111, // index[19] ALERT_HANDLER_CLASSA_PHASE2_CYC
 675:     4'b 1111, // index[20] ALERT_HANDLER_CLASSA_PHASE3_CYC
 676:     4'b 1111, // index[21] ALERT_HANDLER_CLASSA_ESC_CNT
 677:     4'b 0001, // index[22] ALERT_HANDLER_CLASSA_STATE
 678:     4'b 0011, // index[23] ALERT_HANDLER_CLASSB_CTRL
 679:     4'b 0001, // index[24] ALERT_HANDLER_CLASSB_CLREN
 680:     4'b 0001, // index[25] ALERT_HANDLER_CLASSB_CLR
 681:     4'b 0011, // index[26] ALERT_HANDLER_CLASSB_ACCUM_CNT
 682:     4'b 0011, // index[27] ALERT_HANDLER_CLASSB_ACCUM_THRESH
 683:     4'b 1111, // index[28] ALERT_HANDLER_CLASSB_TIMEOUT_CYC
 684:     4'b 1111, // index[29] ALERT_HANDLER_CLASSB_PHASE0_CYC
 685:     4'b 1111, // index[30] ALERT_HANDLER_CLASSB_PHASE1_CYC
 686:     4'b 1111, // index[31] ALERT_HANDLER_CLASSB_PHASE2_CYC
 687:     4'b 1111, // index[32] ALERT_HANDLER_CLASSB_PHASE3_CYC
 688:     4'b 1111, // index[33] ALERT_HANDLER_CLASSB_ESC_CNT
 689:     4'b 0001, // index[34] ALERT_HANDLER_CLASSB_STATE
 690:     4'b 0011, // index[35] ALERT_HANDLER_CLASSC_CTRL
 691:     4'b 0001, // index[36] ALERT_HANDLER_CLASSC_CLREN
 692:     4'b 0001, // index[37] ALERT_HANDLER_CLASSC_CLR
 693:     4'b 0011, // index[38] ALERT_HANDLER_CLASSC_ACCUM_CNT
 694:     4'b 0011, // index[39] ALERT_HANDLER_CLASSC_ACCUM_THRESH
 695:     4'b 1111, // index[40] ALERT_HANDLER_CLASSC_TIMEOUT_CYC
 696:     4'b 1111, // index[41] ALERT_HANDLER_CLASSC_PHASE0_CYC
 697:     4'b 1111, // index[42] ALERT_HANDLER_CLASSC_PHASE1_CYC
 698:     4'b 1111, // index[43] ALERT_HANDLER_CLASSC_PHASE2_CYC
 699:     4'b 1111, // index[44] ALERT_HANDLER_CLASSC_PHASE3_CYC
 700:     4'b 1111, // index[45] ALERT_HANDLER_CLASSC_ESC_CNT
 701:     4'b 0001, // index[46] ALERT_HANDLER_CLASSC_STATE
 702:     4'b 0011, // index[47] ALERT_HANDLER_CLASSD_CTRL
 703:     4'b 0001, // index[48] ALERT_HANDLER_CLASSD_CLREN
 704:     4'b 0001, // index[49] ALERT_HANDLER_CLASSD_CLR
 705:     4'b 0011, // index[50] ALERT_HANDLER_CLASSD_ACCUM_CNT
 706:     4'b 0011, // index[51] ALERT_HANDLER_CLASSD_ACCUM_THRESH
 707:     4'b 1111, // index[52] ALERT_HANDLER_CLASSD_TIMEOUT_CYC
 708:     4'b 1111, // index[53] ALERT_HANDLER_CLASSD_PHASE0_CYC
 709:     4'b 1111, // index[54] ALERT_HANDLER_CLASSD_PHASE1_CYC
 710:     4'b 1111, // index[55] ALERT_HANDLER_CLASSD_PHASE2_CYC
 711:     4'b 1111, // index[56] ALERT_HANDLER_CLASSD_PHASE3_CYC
 712:     4'b 1111, // index[57] ALERT_HANDLER_CLASSD_ESC_CNT
 713:     4'b 0001  // index[58] ALERT_HANDLER_CLASSD_STATE
 714:   };
 715: endpackage
 716: 
 717: