../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_ctrl_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module flash_ctrl_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16:
17: // Output port for window
18: output tlul_pkg::tl_h2d_t tl_win_o [2],
19: input tlul_pkg::tl_d2h_t tl_win_i [2],
20:
21: // To HW
22: output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_t reg2hw, // Write
23: input flash_ctrl_reg_pkg::flash_ctrl_hw2reg_t hw2reg, // Read
24:
25: // Config
26: input devmode_i // If 1, explicit error return for unmapped register access
27: );
28:
29: import flash_ctrl_reg_pkg::* ;
30:
31: localparam int AW = 7;
32: localparam int DW = 32;
33: localparam int DBW = DW/8; // Byte Width
34:
35: // register signals
36: logic reg_we;
37: logic reg_re;
38: logic [AW-1:0] reg_addr;
39: logic [DW-1:0] reg_wdata;
40: logic [DBW-1:0] reg_be;
41: logic [DW-1:0] reg_rdata;
42: logic reg_error;
43:
44: logic addrmiss, wr_err;
45:
46: logic [DW-1:0] reg_rdata_next;
47:
48: tlul_pkg::tl_h2d_t tl_reg_h2d;
49: tlul_pkg::tl_d2h_t tl_reg_d2h;
50:
51: tlul_pkg::tl_h2d_t tl_socket_h2d [3];
52: tlul_pkg::tl_d2h_t tl_socket_d2h [3];
53:
54: logic [1:0] reg_steer;
55:
56: // socket_1n connection
57: assign tl_reg_h2d = tl_socket_h2d[2];
58: assign tl_socket_d2h[2] = tl_reg_d2h;
59:
60: assign tl_win_o[0] = tl_socket_h2d[0];
61: assign tl_socket_d2h[0] = tl_win_i[0];
62: assign tl_win_o[1] = tl_socket_h2d[1];
63: assign tl_socket_d2h[1] = tl_win_i[1];
64:
65: // Create Socket_1n
66: tlul_socket_1n #(
67: .N (3),
68: .HReqPass (1'b1),
69: .HRspPass (1'b1),
70: .DReqPass ({3{1'b1}}),
71: .DRspPass ({3{1'b1}}),
72: .HReqDepth (4'h0),
73: .HRspDepth (4'h0),
74: .DReqDepth ({3{4'h0}}),
75: .DRspDepth ({3{4'h0}})
76: ) u_socket (
77: .clk_i,
78: .rst_ni,
79: .tl_h_i (tl_i),
80: .tl_h_o (tl_o),
81: .tl_d_o (tl_socket_h2d),
82: .tl_d_i (tl_socket_d2h),
83: .dev_select (reg_steer)
84: );
85:
86: // Create steering logic
87: always_comb begin
88: reg_steer = 2; // Default set to register
89:
90: // TODO: Can below codes be unique case () inside ?
91: if (tl_i.a_address[AW-1:0] >= 84 && tl_i.a_address[AW-1:0] < 88) begin
92: reg_steer = 0;
93: end
94: if (tl_i.a_address[AW-1:0] >= 88 && tl_i.a_address[AW-1:0] < 92) begin
95: reg_steer = 1;
96: end
97: end
98:
99: tlul_adapter_reg #(
100: .RegAw(AW),
101: .RegDw(DW)
102: ) u_reg_if (
103: .clk_i,
104: .rst_ni,
105:
106: .tl_i (tl_reg_h2d),
107: .tl_o (tl_reg_d2h),
108:
109: .we_o (reg_we),
110: .re_o (reg_re),
111: .addr_o (reg_addr),
112: .wdata_o (reg_wdata),
113: .be_o (reg_be),
114: .rdata_i (reg_rdata),
115: .error_i (reg_error)
116: );
117:
118: assign reg_rdata = reg_rdata_next ;
119: assign reg_error = (devmode_i & addrmiss) | wr_err ;
120:
121: // Define SW related signals
122: // Format: __{wd|we|qs}
123: // or _{wd|we|qs} if field == 1 or 0
124: logic intr_state_prog_empty_qs;
125: logic intr_state_prog_empty_wd;
126: logic intr_state_prog_empty_we;
127: logic intr_state_prog_lvl_qs;
128: logic intr_state_prog_lvl_wd;
129: logic intr_state_prog_lvl_we;
130: logic intr_state_rd_full_qs;
131: logic intr_state_rd_full_wd;
132: logic intr_state_rd_full_we;
133: logic intr_state_rd_lvl_qs;
134: logic intr_state_rd_lvl_wd;
135: logic intr_state_rd_lvl_we;
136: logic intr_state_op_done_qs;
137: logic intr_state_op_done_wd;
138: logic intr_state_op_done_we;
139: logic intr_state_op_error_qs;
140: logic intr_state_op_error_wd;
141: logic intr_state_op_error_we;
142: logic intr_enable_prog_empty_qs;
143: logic intr_enable_prog_empty_wd;
144: logic intr_enable_prog_empty_we;
145: logic intr_enable_prog_lvl_qs;
146: logic intr_enable_prog_lvl_wd;
147: logic intr_enable_prog_lvl_we;
148: logic intr_enable_rd_full_qs;
149: logic intr_enable_rd_full_wd;
150: logic intr_enable_rd_full_we;
151: logic intr_enable_rd_lvl_qs;
152: logic intr_enable_rd_lvl_wd;
153: logic intr_enable_rd_lvl_we;
154: logic intr_enable_op_done_qs;
155: logic intr_enable_op_done_wd;
156: logic intr_enable_op_done_we;
157: logic intr_enable_op_error_qs;
158: logic intr_enable_op_error_wd;
159: logic intr_enable_op_error_we;
160: logic intr_test_prog_empty_wd;
161: logic intr_test_prog_empty_we;
162: logic intr_test_prog_lvl_wd;
163: logic intr_test_prog_lvl_we;
164: logic intr_test_rd_full_wd;
165: logic intr_test_rd_full_we;
166: logic intr_test_rd_lvl_wd;
167: logic intr_test_rd_lvl_we;
168: logic intr_test_op_done_wd;
169: logic intr_test_op_done_we;
170: logic intr_test_op_error_wd;
171: logic intr_test_op_error_we;
172: logic control_start_qs;
173: logic control_start_wd;
174: logic control_start_we;
175: logic [1:0] control_op_qs;
176: logic [1:0] control_op_wd;
177: logic control_op_we;
178: logic control_erase_sel_qs;
179: logic control_erase_sel_wd;
180: logic control_erase_sel_we;
181: logic control_fifo_rst_qs;
182: logic control_fifo_rst_wd;
183: logic control_fifo_rst_we;
184: logic [11:0] control_num_qs;
185: logic [11:0] control_num_wd;
186: logic control_num_we;
187: logic [31:0] addr_qs;
188: logic [31:0] addr_wd;
189: logic addr_we;
190: logic region_cfg_regwen_qs;
191: logic region_cfg_regwen_wd;
192: logic region_cfg_regwen_we;
193: logic mp_region_cfg0_en0_qs;
194: logic mp_region_cfg0_en0_wd;
195: logic mp_region_cfg0_en0_we;
196: logic mp_region_cfg0_rd_en0_qs;
197: logic mp_region_cfg0_rd_en0_wd;
198: logic mp_region_cfg0_rd_en0_we;
199: logic mp_region_cfg0_prog_en0_qs;
200: logic mp_region_cfg0_prog_en0_wd;
201: logic mp_region_cfg0_prog_en0_we;
202: logic mp_region_cfg0_erase_en0_qs;
203: logic mp_region_cfg0_erase_en0_wd;
204: logic mp_region_cfg0_erase_en0_we;
205: logic [8:0] mp_region_cfg0_base0_qs;
206: logic [8:0] mp_region_cfg0_base0_wd;
207: logic mp_region_cfg0_base0_we;
208: logic [8:0] mp_region_cfg0_size0_qs;
209: logic [8:0] mp_region_cfg0_size0_wd;
210: logic mp_region_cfg0_size0_we;
211: logic mp_region_cfg1_en1_qs;
212: logic mp_region_cfg1_en1_wd;
213: logic mp_region_cfg1_en1_we;
214: logic mp_region_cfg1_rd_en1_qs;
215: logic mp_region_cfg1_rd_en1_wd;
216: logic mp_region_cfg1_rd_en1_we;
217: logic mp_region_cfg1_prog_en1_qs;
218: logic mp_region_cfg1_prog_en1_wd;
219: logic mp_region_cfg1_prog_en1_we;
220: logic mp_region_cfg1_erase_en1_qs;
221: logic mp_region_cfg1_erase_en1_wd;
222: logic mp_region_cfg1_erase_en1_we;
223: logic [8:0] mp_region_cfg1_base1_qs;
224: logic [8:0] mp_region_cfg1_base1_wd;
225: logic mp_region_cfg1_base1_we;
226: logic [8:0] mp_region_cfg1_size1_qs;
227: logic [8:0] mp_region_cfg1_size1_wd;
228: logic mp_region_cfg1_size1_we;
229: logic mp_region_cfg2_en2_qs;
230: logic mp_region_cfg2_en2_wd;
231: logic mp_region_cfg2_en2_we;
232: logic mp_region_cfg2_rd_en2_qs;
233: logic mp_region_cfg2_rd_en2_wd;
234: logic mp_region_cfg2_rd_en2_we;
235: logic mp_region_cfg2_prog_en2_qs;
236: logic mp_region_cfg2_prog_en2_wd;
237: logic mp_region_cfg2_prog_en2_we;
238: logic mp_region_cfg2_erase_en2_qs;
239: logic mp_region_cfg2_erase_en2_wd;
240: logic mp_region_cfg2_erase_en2_we;
241: logic [8:0] mp_region_cfg2_base2_qs;
242: logic [8:0] mp_region_cfg2_base2_wd;
243: logic mp_region_cfg2_base2_we;
244: logic [8:0] mp_region_cfg2_size2_qs;
245: logic [8:0] mp_region_cfg2_size2_wd;
246: logic mp_region_cfg2_size2_we;
247: logic mp_region_cfg3_en3_qs;
248: logic mp_region_cfg3_en3_wd;
249: logic mp_region_cfg3_en3_we;
250: logic mp_region_cfg3_rd_en3_qs;
251: logic mp_region_cfg3_rd_en3_wd;
252: logic mp_region_cfg3_rd_en3_we;
253: logic mp_region_cfg3_prog_en3_qs;
254: logic mp_region_cfg3_prog_en3_wd;
255: logic mp_region_cfg3_prog_en3_we;
256: logic mp_region_cfg3_erase_en3_qs;
257: logic mp_region_cfg3_erase_en3_wd;
258: logic mp_region_cfg3_erase_en3_we;
259: logic [8:0] mp_region_cfg3_base3_qs;
260: logic [8:0] mp_region_cfg3_base3_wd;
261: logic mp_region_cfg3_base3_we;
262: logic [8:0] mp_region_cfg3_size3_qs;
263: logic [8:0] mp_region_cfg3_size3_wd;
264: logic mp_region_cfg3_size3_we;
265: logic mp_region_cfg4_en4_qs;
266: logic mp_region_cfg4_en4_wd;
267: logic mp_region_cfg4_en4_we;
268: logic mp_region_cfg4_rd_en4_qs;
269: logic mp_region_cfg4_rd_en4_wd;
270: logic mp_region_cfg4_rd_en4_we;
271: logic mp_region_cfg4_prog_en4_qs;
272: logic mp_region_cfg4_prog_en4_wd;
273: logic mp_region_cfg4_prog_en4_we;
274: logic mp_region_cfg4_erase_en4_qs;
275: logic mp_region_cfg4_erase_en4_wd;
276: logic mp_region_cfg4_erase_en4_we;
277: logic [8:0] mp_region_cfg4_base4_qs;
278: logic [8:0] mp_region_cfg4_base4_wd;
279: logic mp_region_cfg4_base4_we;
280: logic [8:0] mp_region_cfg4_size4_qs;
281: logic [8:0] mp_region_cfg4_size4_wd;
282: logic mp_region_cfg4_size4_we;
283: logic mp_region_cfg5_en5_qs;
284: logic mp_region_cfg5_en5_wd;
285: logic mp_region_cfg5_en5_we;
286: logic mp_region_cfg5_rd_en5_qs;
287: logic mp_region_cfg5_rd_en5_wd;
288: logic mp_region_cfg5_rd_en5_we;
289: logic mp_region_cfg5_prog_en5_qs;
290: logic mp_region_cfg5_prog_en5_wd;
291: logic mp_region_cfg5_prog_en5_we;
292: logic mp_region_cfg5_erase_en5_qs;
293: logic mp_region_cfg5_erase_en5_wd;
294: logic mp_region_cfg5_erase_en5_we;
295: logic [8:0] mp_region_cfg5_base5_qs;
296: logic [8:0] mp_region_cfg5_base5_wd;
297: logic mp_region_cfg5_base5_we;
298: logic [8:0] mp_region_cfg5_size5_qs;
299: logic [8:0] mp_region_cfg5_size5_wd;
300: logic mp_region_cfg5_size5_we;
301: logic mp_region_cfg6_en6_qs;
302: logic mp_region_cfg6_en6_wd;
303: logic mp_region_cfg6_en6_we;
304: logic mp_region_cfg6_rd_en6_qs;
305: logic mp_region_cfg6_rd_en6_wd;
306: logic mp_region_cfg6_rd_en6_we;
307: logic mp_region_cfg6_prog_en6_qs;
308: logic mp_region_cfg6_prog_en6_wd;
309: logic mp_region_cfg6_prog_en6_we;
310: logic mp_region_cfg6_erase_en6_qs;
311: logic mp_region_cfg6_erase_en6_wd;
312: logic mp_region_cfg6_erase_en6_we;
313: logic [8:0] mp_region_cfg6_base6_qs;
314: logic [8:0] mp_region_cfg6_base6_wd;
315: logic mp_region_cfg6_base6_we;
316: logic [8:0] mp_region_cfg6_size6_qs;
317: logic [8:0] mp_region_cfg6_size6_wd;
318: logic mp_region_cfg6_size6_we;
319: logic mp_region_cfg7_en7_qs;
320: logic mp_region_cfg7_en7_wd;
321: logic mp_region_cfg7_en7_we;
322: logic mp_region_cfg7_rd_en7_qs;
323: logic mp_region_cfg7_rd_en7_wd;
324: logic mp_region_cfg7_rd_en7_we;
325: logic mp_region_cfg7_prog_en7_qs;
326: logic mp_region_cfg7_prog_en7_wd;
327: logic mp_region_cfg7_prog_en7_we;
328: logic mp_region_cfg7_erase_en7_qs;
329: logic mp_region_cfg7_erase_en7_wd;
330: logic mp_region_cfg7_erase_en7_we;
331: logic [8:0] mp_region_cfg7_base7_qs;
332: logic [8:0] mp_region_cfg7_base7_wd;
333: logic mp_region_cfg7_base7_we;
334: logic [8:0] mp_region_cfg7_size7_qs;
335: logic [8:0] mp_region_cfg7_size7_wd;
336: logic mp_region_cfg7_size7_we;
337: logic default_region_rd_en_qs;
338: logic default_region_rd_en_wd;
339: logic default_region_rd_en_we;
340: logic default_region_prog_en_qs;
341: logic default_region_prog_en_wd;
342: logic default_region_prog_en_we;
343: logic default_region_erase_en_qs;
344: logic default_region_erase_en_wd;
345: logic default_region_erase_en_we;
346: logic bank_cfg_regwen_qs;
347: logic bank_cfg_regwen_wd;
348: logic bank_cfg_regwen_we;
349: logic mp_bank_cfg_erase_en0_qs;
350: logic mp_bank_cfg_erase_en0_wd;
351: logic mp_bank_cfg_erase_en0_we;
352: logic mp_bank_cfg_erase_en1_qs;
353: logic mp_bank_cfg_erase_en1_wd;
354: logic mp_bank_cfg_erase_en1_we;
355: logic op_status_done_qs;
356: logic op_status_done_wd;
357: logic op_status_done_we;
358: logic op_status_err_qs;
359: logic op_status_err_wd;
360: logic op_status_err_we;
361: logic status_rd_full_qs;
362: logic status_rd_full_re;
363: logic status_rd_empty_qs;
364: logic status_rd_empty_re;
365: logic status_prog_full_qs;
366: logic status_prog_full_re;
367: logic status_prog_empty_qs;
368: logic status_prog_empty_re;
369: logic status_init_wip_qs;
370: logic status_init_wip_re;
371: logic [8:0] status_error_page_qs;
372: logic status_error_page_re;
373: logic status_error_bank_qs;
374: logic status_error_bank_re;
375: logic [31:0] scratch_qs;
376: logic [31:0] scratch_wd;
377: logic scratch_we;
378: logic [4:0] fifo_lvl_prog_qs;
379: logic [4:0] fifo_lvl_prog_wd;
380: logic fifo_lvl_prog_we;
381: logic [4:0] fifo_lvl_rd_qs;
382: logic [4:0] fifo_lvl_rd_wd;
383: logic fifo_lvl_rd_we;
384:
385: // Register instances
386: // R[intr_state]: V(False)
387:
388: // F[prog_empty]: 0:0
389: prim_subreg #(
390: .DW (1),
391: .SWACCESS("W1C"),
392: .RESVAL (1'h0)
393: ) u_intr_state_prog_empty (
394: .clk_i (clk_i ),
395: .rst_ni (rst_ni ),
396:
397: // from register interface
398: .we (intr_state_prog_empty_we),
399: .wd (intr_state_prog_empty_wd),
400:
401: // from internal hardware
402: .de (hw2reg.intr_state.prog_empty.de),
403: .d (hw2reg.intr_state.prog_empty.d ),
404:
405: // to internal hardware
406: .qe (),
407: .q (reg2hw.intr_state.prog_empty.q ),
408:
409: // to register interface (read)
410: .qs (intr_state_prog_empty_qs)
411: );
412:
413:
414: // F[prog_lvl]: 1:1
415: prim_subreg #(
416: .DW (1),
417: .SWACCESS("W1C"),
418: .RESVAL (1'h0)
419: ) u_intr_state_prog_lvl (
420: .clk_i (clk_i ),
421: .rst_ni (rst_ni ),
422:
423: // from register interface
424: .we (intr_state_prog_lvl_we),
425: .wd (intr_state_prog_lvl_wd),
426:
427: // from internal hardware
428: .de (hw2reg.intr_state.prog_lvl.de),
429: .d (hw2reg.intr_state.prog_lvl.d ),
430:
431: // to internal hardware
432: .qe (),
433: .q (reg2hw.intr_state.prog_lvl.q ),
434:
435: // to register interface (read)
436: .qs (intr_state_prog_lvl_qs)
437: );
438:
439:
440: // F[rd_full]: 2:2
441: prim_subreg #(
442: .DW (1),
443: .SWACCESS("W1C"),
444: .RESVAL (1'h0)
445: ) u_intr_state_rd_full (
446: .clk_i (clk_i ),
447: .rst_ni (rst_ni ),
448:
449: // from register interface
450: .we (intr_state_rd_full_we),
451: .wd (intr_state_rd_full_wd),
452:
453: // from internal hardware
454: .de (hw2reg.intr_state.rd_full.de),
455: .d (hw2reg.intr_state.rd_full.d ),
456:
457: // to internal hardware
458: .qe (),
459: .q (reg2hw.intr_state.rd_full.q ),
460:
461: // to register interface (read)
462: .qs (intr_state_rd_full_qs)
463: );
464:
465:
466: // F[rd_lvl]: 3:3
467: prim_subreg #(
468: .DW (1),
469: .SWACCESS("W1C"),
470: .RESVAL (1'h0)
471: ) u_intr_state_rd_lvl (
472: .clk_i (clk_i ),
473: .rst_ni (rst_ni ),
474:
475: // from register interface
476: .we (intr_state_rd_lvl_we),
477: .wd (intr_state_rd_lvl_wd),
478:
479: // from internal hardware
480: .de (hw2reg.intr_state.rd_lvl.de),
481: .d (hw2reg.intr_state.rd_lvl.d ),
482:
483: // to internal hardware
484: .qe (),
485: .q (reg2hw.intr_state.rd_lvl.q ),
486:
487: // to register interface (read)
488: .qs (intr_state_rd_lvl_qs)
489: );
490:
491:
492: // F[op_done]: 4:4
493: prim_subreg #(
494: .DW (1),
495: .SWACCESS("W1C"),
496: .RESVAL (1'h0)
497: ) u_intr_state_op_done (
498: .clk_i (clk_i ),
499: .rst_ni (rst_ni ),
500:
501: // from register interface
502: .we (intr_state_op_done_we),
503: .wd (intr_state_op_done_wd),
504:
505: // from internal hardware
506: .de (hw2reg.intr_state.op_done.de),
507: .d (hw2reg.intr_state.op_done.d ),
508:
509: // to internal hardware
510: .qe (),
511: .q (reg2hw.intr_state.op_done.q ),
512:
513: // to register interface (read)
514: .qs (intr_state_op_done_qs)
515: );
516:
517:
518: // F[op_error]: 5:5
519: prim_subreg #(
520: .DW (1),
521: .SWACCESS("W1C"),
522: .RESVAL (1'h0)
523: ) u_intr_state_op_error (
524: .clk_i (clk_i ),
525: .rst_ni (rst_ni ),
526:
527: // from register interface
528: .we (intr_state_op_error_we),
529: .wd (intr_state_op_error_wd),
530:
531: // from internal hardware
532: .de (hw2reg.intr_state.op_error.de),
533: .d (hw2reg.intr_state.op_error.d ),
534:
535: // to internal hardware
536: .qe (),
537: .q (reg2hw.intr_state.op_error.q ),
538:
539: // to register interface (read)
540: .qs (intr_state_op_error_qs)
541: );
542:
543:
544: // R[intr_enable]: V(False)
545:
546: // F[prog_empty]: 0:0
547: prim_subreg #(
548: .DW (1),
549: .SWACCESS("RW"),
550: .RESVAL (1'h0)
551: ) u_intr_enable_prog_empty (
552: .clk_i (clk_i ),
553: .rst_ni (rst_ni ),
554:
555: // from register interface
556: .we (intr_enable_prog_empty_we),
557: .wd (intr_enable_prog_empty_wd),
558:
559: // from internal hardware
560: .de (1'b0),
561: .d ('0 ),
562:
563: // to internal hardware
564: .qe (),
565: .q (reg2hw.intr_enable.prog_empty.q ),
566:
567: // to register interface (read)
568: .qs (intr_enable_prog_empty_qs)
569: );
570:
571:
572: // F[prog_lvl]: 1:1
573: prim_subreg #(
574: .DW (1),
575: .SWACCESS("RW"),
576: .RESVAL (1'h0)
577: ) u_intr_enable_prog_lvl (
578: .clk_i (clk_i ),
579: .rst_ni (rst_ni ),
580:
581: // from register interface
582: .we (intr_enable_prog_lvl_we),
583: .wd (intr_enable_prog_lvl_wd),
584:
585: // from internal hardware
586: .de (1'b0),
587: .d ('0 ),
588:
589: // to internal hardware
590: .qe (),
591: .q (reg2hw.intr_enable.prog_lvl.q ),
592:
593: // to register interface (read)
594: .qs (intr_enable_prog_lvl_qs)
595: );
596:
597:
598: // F[rd_full]: 2:2
599: prim_subreg #(
600: .DW (1),
601: .SWACCESS("RW"),
602: .RESVAL (1'h0)
603: ) u_intr_enable_rd_full (
604: .clk_i (clk_i ),
605: .rst_ni (rst_ni ),
606:
607: // from register interface
608: .we (intr_enable_rd_full_we),
609: .wd (intr_enable_rd_full_wd),
610:
611: // from internal hardware
612: .de (1'b0),
613: .d ('0 ),
614:
615: // to internal hardware
616: .qe (),
617: .q (reg2hw.intr_enable.rd_full.q ),
618:
619: // to register interface (read)
620: .qs (intr_enable_rd_full_qs)
621: );
622:
623:
624: // F[rd_lvl]: 3:3
625: prim_subreg #(
626: .DW (1),
627: .SWACCESS("RW"),
628: .RESVAL (1'h0)
629: ) u_intr_enable_rd_lvl (
630: .clk_i (clk_i ),
631: .rst_ni (rst_ni ),
632:
633: // from register interface
634: .we (intr_enable_rd_lvl_we),
635: .wd (intr_enable_rd_lvl_wd),
636:
637: // from internal hardware
638: .de (1'b0),
639: .d ('0 ),
640:
641: // to internal hardware
642: .qe (),
643: .q (reg2hw.intr_enable.rd_lvl.q ),
644:
645: // to register interface (read)
646: .qs (intr_enable_rd_lvl_qs)
647: );
648:
649:
650: // F[op_done]: 4:4
651: prim_subreg #(
652: .DW (1),
653: .SWACCESS("RW"),
654: .RESVAL (1'h0)
655: ) u_intr_enable_op_done (
656: .clk_i (clk_i ),
657: .rst_ni (rst_ni ),
658:
659: // from register interface
660: .we (intr_enable_op_done_we),
661: .wd (intr_enable_op_done_wd),
662:
663: // from internal hardware
664: .de (1'b0),
665: .d ('0 ),
666:
667: // to internal hardware
668: .qe (),
669: .q (reg2hw.intr_enable.op_done.q ),
670:
671: // to register interface (read)
672: .qs (intr_enable_op_done_qs)
673: );
674:
675:
676: // F[op_error]: 5:5
677: prim_subreg #(
678: .DW (1),
679: .SWACCESS("RW"),
680: .RESVAL (1'h0)
681: ) u_intr_enable_op_error (
682: .clk_i (clk_i ),
683: .rst_ni (rst_ni ),
684:
685: // from register interface
686: .we (intr_enable_op_error_we),
687: .wd (intr_enable_op_error_wd),
688:
689: // from internal hardware
690: .de (1'b0),
691: .d ('0 ),
692:
693: // to internal hardware
694: .qe (),
695: .q (reg2hw.intr_enable.op_error.q ),
696:
697: // to register interface (read)
698: .qs (intr_enable_op_error_qs)
699: );
700:
701:
702: // R[intr_test]: V(True)
703:
704: // F[prog_empty]: 0:0
705: prim_subreg_ext #(
706: .DW (1)
707: ) u_intr_test_prog_empty (
708: .re (1'b0),
709: .we (intr_test_prog_empty_we),
710: .wd (intr_test_prog_empty_wd),
711: .d ('0),
712: .qre (),
713: .qe (reg2hw.intr_test.prog_empty.qe),
714: .q (reg2hw.intr_test.prog_empty.q ),
715: .qs ()
716: );
717:
718:
719: // F[prog_lvl]: 1:1
720: prim_subreg_ext #(
721: .DW (1)
722: ) u_intr_test_prog_lvl (
723: .re (1'b0),
724: .we (intr_test_prog_lvl_we),
725: .wd (intr_test_prog_lvl_wd),
726: .d ('0),
727: .qre (),
728: .qe (reg2hw.intr_test.prog_lvl.qe),
729: .q (reg2hw.intr_test.prog_lvl.q ),
730: .qs ()
731: );
732:
733:
734: // F[rd_full]: 2:2
735: prim_subreg_ext #(
736: .DW (1)
737: ) u_intr_test_rd_full (
738: .re (1'b0),
739: .we (intr_test_rd_full_we),
740: .wd (intr_test_rd_full_wd),
741: .d ('0),
742: .qre (),
743: .qe (reg2hw.intr_test.rd_full.qe),
744: .q (reg2hw.intr_test.rd_full.q ),
745: .qs ()
746: );
747:
748:
749: // F[rd_lvl]: 3:3
750: prim_subreg_ext #(
751: .DW (1)
752: ) u_intr_test_rd_lvl (
753: .re (1'b0),
754: .we (intr_test_rd_lvl_we),
755: .wd (intr_test_rd_lvl_wd),
756: .d ('0),
757: .qre (),
758: .qe (reg2hw.intr_test.rd_lvl.qe),
759: .q (reg2hw.intr_test.rd_lvl.q ),
760: .qs ()
761: );
762:
763:
764: // F[op_done]: 4:4
765: prim_subreg_ext #(
766: .DW (1)
767: ) u_intr_test_op_done (
768: .re (1'b0),
769: .we (intr_test_op_done_we),
770: .wd (intr_test_op_done_wd),
771: .d ('0),
772: .qre (),
773: .qe (reg2hw.intr_test.op_done.qe),
774: .q (reg2hw.intr_test.op_done.q ),
775: .qs ()
776: );
777:
778:
779: // F[op_error]: 5:5
780: prim_subreg_ext #(
781: .DW (1)
782: ) u_intr_test_op_error (
783: .re (1'b0),
784: .we (intr_test_op_error_we),
785: .wd (intr_test_op_error_wd),
786: .d ('0),
787: .qre (),
788: .qe (reg2hw.intr_test.op_error.qe),
789: .q (reg2hw.intr_test.op_error.q ),
790: .qs ()
791: );
792:
793:
794: // R[control]: V(False)
795:
796: // F[start]: 0:0
797: prim_subreg #(
798: .DW (1),
799: .SWACCESS("RW"),
800: .RESVAL (1'h0)
801: ) u_control_start (
802: .clk_i (clk_i ),
803: .rst_ni (rst_ni ),
804:
805: // from register interface
806: .we (control_start_we),
807: .wd (control_start_wd),
808:
809: // from internal hardware
810: .de (hw2reg.control.start.de),
811: .d (hw2reg.control.start.d ),
812:
813: // to internal hardware
814: .qe (),
815: .q (reg2hw.control.start.q ),
816:
817: // to register interface (read)
818: .qs (control_start_qs)
819: );
820:
821:
822: // F[op]: 5:4
823: prim_subreg #(
824: .DW (2),
825: .SWACCESS("RW"),
826: .RESVAL (2'h0)
827: ) u_control_op (
828: .clk_i (clk_i ),
829: .rst_ni (rst_ni ),
830:
831: // from register interface
832: .we (control_op_we),
833: .wd (control_op_wd),
834:
835: // from internal hardware
836: .de (1'b0),
837: .d ('0 ),
838:
839: // to internal hardware
840: .qe (),
841: .q (reg2hw.control.op.q ),
842:
843: // to register interface (read)
844: .qs (control_op_qs)
845: );
846:
847:
848: // F[erase_sel]: 6:6
849: prim_subreg #(
850: .DW (1),
851: .SWACCESS("RW"),
852: .RESVAL (1'h0)
853: ) u_control_erase_sel (
854: .clk_i (clk_i ),
855: .rst_ni (rst_ni ),
856:
857: // from register interface
858: .we (control_erase_sel_we),
859: .wd (control_erase_sel_wd),
860:
861: // from internal hardware
862: .de (1'b0),
863: .d ('0 ),
864:
865: // to internal hardware
866: .qe (),
867: .q (reg2hw.control.erase_sel.q ),
868:
869: // to register interface (read)
870: .qs (control_erase_sel_qs)
871: );
872:
873:
874: // F[fifo_rst]: 7:7
875: prim_subreg #(
876: .DW (1),
877: .SWACCESS("RW"),
878: .RESVAL (1'h0)
879: ) u_control_fifo_rst (
880: .clk_i (clk_i ),
881: .rst_ni (rst_ni ),
882:
883: // from register interface
884: .we (control_fifo_rst_we),
885: .wd (control_fifo_rst_wd),
886:
887: // from internal hardware
888: .de (1'b0),
889: .d ('0 ),
890:
891: // to internal hardware
892: .qe (),
893: .q (reg2hw.control.fifo_rst.q ),
894:
895: // to register interface (read)
896: .qs (control_fifo_rst_qs)
897: );
898:
899:
900: // F[num]: 27:16
901: prim_subreg #(
902: .DW (12),
903: .SWACCESS("RW"),
904: .RESVAL (12'h0)
905: ) u_control_num (
906: .clk_i (clk_i ),
907: .rst_ni (rst_ni ),
908:
909: // from register interface
910: .we (control_num_we),
911: .wd (control_num_wd),
912:
913: // from internal hardware
914: .de (1'b0),
915: .d ('0 ),
916:
917: // to internal hardware
918: .qe (),
919: .q (reg2hw.control.num.q ),
920:
921: // to register interface (read)
922: .qs (control_num_qs)
923: );
924:
925:
926: // R[addr]: V(False)
927:
928: prim_subreg #(
929: .DW (32),
930: .SWACCESS("RW"),
931: .RESVAL (32'h0)
932: ) u_addr (
933: .clk_i (clk_i ),
934: .rst_ni (rst_ni ),
935:
936: // from register interface
937: .we (addr_we),
938: .wd (addr_wd),
939:
940: // from internal hardware
941: .de (1'b0),
942: .d ('0 ),
943:
944: // to internal hardware
945: .qe (),
946: .q (reg2hw.addr.q ),
947:
948: // to register interface (read)
949: .qs (addr_qs)
950: );
951:
952:
953: // R[region_cfg_regwen]: V(False)
954:
955: prim_subreg #(
956: .DW (1),
957: .SWACCESS("W0C"),
958: .RESVAL (1'h1)
959: ) u_region_cfg_regwen (
960: .clk_i (clk_i ),
961: .rst_ni (rst_ni ),
962:
963: // from register interface
964: .we (region_cfg_regwen_we),
965: .wd (region_cfg_regwen_wd),
966:
967: // from internal hardware
968: .de (1'b0),
969: .d ('0 ),
970:
971: // to internal hardware
972: .qe (),
973: .q (),
974:
975: // to register interface (read)
976: .qs (region_cfg_regwen_qs)
977: );
978:
979:
980:
981: // Subregister 0 of Multireg mp_region_cfg
982: // R[mp_region_cfg0]: V(False)
983:
984: // F[en0]: 0:0
985: prim_subreg #(
986: .DW (1),
987: .SWACCESS("RW"),
988: .RESVAL (1'h0)
989: ) u_mp_region_cfg0_en0 (
990: .clk_i (clk_i ),
991: .rst_ni (rst_ni ),
992:
993: // from register interface (qualified with register enable)
994: .we (mp_region_cfg0_en0_we & region_cfg_regwen_qs),
995: .wd (mp_region_cfg0_en0_wd),
996:
997: // from internal hardware
998: .de (1'b0),
999: .d ('0 ),
1000:
1001: // to internal hardware
1002: .qe (),
1003: .q (reg2hw.mp_region_cfg[0].en.q ),
1004:
1005: // to register interface (read)
1006: .qs (mp_region_cfg0_en0_qs)
1007: );
1008:
1009:
1010: // F[rd_en0]: 1:1
1011: prim_subreg #(
1012: .DW (1),
1013: .SWACCESS("RW"),
1014: .RESVAL (1'h0)
1015: ) u_mp_region_cfg0_rd_en0 (
1016: .clk_i (clk_i ),
1017: .rst_ni (rst_ni ),
1018:
1019: // from register interface (qualified with register enable)
1020: .we (mp_region_cfg0_rd_en0_we & region_cfg_regwen_qs),
1021: .wd (mp_region_cfg0_rd_en0_wd),
1022:
1023: // from internal hardware
1024: .de (1'b0),
1025: .d ('0 ),
1026:
1027: // to internal hardware
1028: .qe (),
1029: .q (reg2hw.mp_region_cfg[0].rd_en.q ),
1030:
1031: // to register interface (read)
1032: .qs (mp_region_cfg0_rd_en0_qs)
1033: );
1034:
1035:
1036: // F[prog_en0]: 2:2
1037: prim_subreg #(
1038: .DW (1),
1039: .SWACCESS("RW"),
1040: .RESVAL (1'h0)
1041: ) u_mp_region_cfg0_prog_en0 (
1042: .clk_i (clk_i ),
1043: .rst_ni (rst_ni ),
1044:
1045: // from register interface (qualified with register enable)
1046: .we (mp_region_cfg0_prog_en0_we & region_cfg_regwen_qs),
1047: .wd (mp_region_cfg0_prog_en0_wd),
1048:
1049: // from internal hardware
1050: .de (1'b0),
1051: .d ('0 ),
1052:
1053: // to internal hardware
1054: .qe (),
1055: .q (reg2hw.mp_region_cfg[0].prog_en.q ),
1056:
1057: // to register interface (read)
1058: .qs (mp_region_cfg0_prog_en0_qs)
1059: );
1060:
1061:
1062: // F[erase_en0]: 3:3
1063: prim_subreg #(
1064: .DW (1),
1065: .SWACCESS("RW"),
1066: .RESVAL (1'h0)
1067: ) u_mp_region_cfg0_erase_en0 (
1068: .clk_i (clk_i ),
1069: .rst_ni (rst_ni ),
1070:
1071: // from register interface (qualified with register enable)
1072: .we (mp_region_cfg0_erase_en0_we & region_cfg_regwen_qs),
1073: .wd (mp_region_cfg0_erase_en0_wd),
1074:
1075: // from internal hardware
1076: .de (1'b0),
1077: .d ('0 ),
1078:
1079: // to internal hardware
1080: .qe (),
1081: .q (reg2hw.mp_region_cfg[0].erase_en.q ),
1082:
1083: // to register interface (read)
1084: .qs (mp_region_cfg0_erase_en0_qs)
1085: );
1086:
1087:
1088: // F[base0]: 12:4
1089: prim_subreg #(
1090: .DW (9),
1091: .SWACCESS("RW"),
1092: .RESVAL (9'h0)
1093: ) u_mp_region_cfg0_base0 (
1094: .clk_i (clk_i ),
1095: .rst_ni (rst_ni ),
1096:
1097: // from register interface (qualified with register enable)
1098: .we (mp_region_cfg0_base0_we & region_cfg_regwen_qs),
1099: .wd (mp_region_cfg0_base0_wd),
1100:
1101: // from internal hardware
1102: .de (1'b0),
1103: .d ('0 ),
1104:
1105: // to internal hardware
1106: .qe (),
1107: .q (reg2hw.mp_region_cfg[0].base.q ),
1108:
1109: // to register interface (read)
1110: .qs (mp_region_cfg0_base0_qs)
1111: );
1112:
1113:
1114: // F[size0]: 24:16
1115: prim_subreg #(
1116: .DW (9),
1117: .SWACCESS("RW"),
1118: .RESVAL (9'h0)
1119: ) u_mp_region_cfg0_size0 (
1120: .clk_i (clk_i ),
1121: .rst_ni (rst_ni ),
1122:
1123: // from register interface (qualified with register enable)
1124: .we (mp_region_cfg0_size0_we & region_cfg_regwen_qs),
1125: .wd (mp_region_cfg0_size0_wd),
1126:
1127: // from internal hardware
1128: .de (1'b0),
1129: .d ('0 ),
1130:
1131: // to internal hardware
1132: .qe (),
1133: .q (reg2hw.mp_region_cfg[0].size.q ),
1134:
1135: // to register interface (read)
1136: .qs (mp_region_cfg0_size0_qs)
1137: );
1138:
1139:
1140: // Subregister 1 of Multireg mp_region_cfg
1141: // R[mp_region_cfg1]: V(False)
1142:
1143: // F[en1]: 0:0
1144: prim_subreg #(
1145: .DW (1),
1146: .SWACCESS("RW"),
1147: .RESVAL (1'h0)
1148: ) u_mp_region_cfg1_en1 (
1149: .clk_i (clk_i ),
1150: .rst_ni (rst_ni ),
1151:
1152: // from register interface (qualified with register enable)
1153: .we (mp_region_cfg1_en1_we & region_cfg_regwen_qs),
1154: .wd (mp_region_cfg1_en1_wd),
1155:
1156: // from internal hardware
1157: .de (1'b0),
1158: .d ('0 ),
1159:
1160: // to internal hardware
1161: .qe (),
1162: .q (reg2hw.mp_region_cfg[1].en.q ),
1163:
1164: // to register interface (read)
1165: .qs (mp_region_cfg1_en1_qs)
1166: );
1167:
1168:
1169: // F[rd_en1]: 1:1
1170: prim_subreg #(
1171: .DW (1),
1172: .SWACCESS("RW"),
1173: .RESVAL (1'h0)
1174: ) u_mp_region_cfg1_rd_en1 (
1175: .clk_i (clk_i ),
1176: .rst_ni (rst_ni ),
1177:
1178: // from register interface (qualified with register enable)
1179: .we (mp_region_cfg1_rd_en1_we & region_cfg_regwen_qs),
1180: .wd (mp_region_cfg1_rd_en1_wd),
1181:
1182: // from internal hardware
1183: .de (1'b0),
1184: .d ('0 ),
1185:
1186: // to internal hardware
1187: .qe (),
1188: .q (reg2hw.mp_region_cfg[1].rd_en.q ),
1189:
1190: // to register interface (read)
1191: .qs (mp_region_cfg1_rd_en1_qs)
1192: );
1193:
1194:
1195: // F[prog_en1]: 2:2
1196: prim_subreg #(
1197: .DW (1),
1198: .SWACCESS("RW"),
1199: .RESVAL (1'h0)
1200: ) u_mp_region_cfg1_prog_en1 (
1201: .clk_i (clk_i ),
1202: .rst_ni (rst_ni ),
1203:
1204: // from register interface (qualified with register enable)
1205: .we (mp_region_cfg1_prog_en1_we & region_cfg_regwen_qs),
1206: .wd (mp_region_cfg1_prog_en1_wd),
1207:
1208: // from internal hardware
1209: .de (1'b0),
1210: .d ('0 ),
1211:
1212: // to internal hardware
1213: .qe (),
1214: .q (reg2hw.mp_region_cfg[1].prog_en.q ),
1215:
1216: // to register interface (read)
1217: .qs (mp_region_cfg1_prog_en1_qs)
1218: );
1219:
1220:
1221: // F[erase_en1]: 3:3
1222: prim_subreg #(
1223: .DW (1),
1224: .SWACCESS("RW"),
1225: .RESVAL (1'h0)
1226: ) u_mp_region_cfg1_erase_en1 (
1227: .clk_i (clk_i ),
1228: .rst_ni (rst_ni ),
1229:
1230: // from register interface (qualified with register enable)
1231: .we (mp_region_cfg1_erase_en1_we & region_cfg_regwen_qs),
1232: .wd (mp_region_cfg1_erase_en1_wd),
1233:
1234: // from internal hardware
1235: .de (1'b0),
1236: .d ('0 ),
1237:
1238: // to internal hardware
1239: .qe (),
1240: .q (reg2hw.mp_region_cfg[1].erase_en.q ),
1241:
1242: // to register interface (read)
1243: .qs (mp_region_cfg1_erase_en1_qs)
1244: );
1245:
1246:
1247: // F[base1]: 12:4
1248: prim_subreg #(
1249: .DW (9),
1250: .SWACCESS("RW"),
1251: .RESVAL (9'h0)
1252: ) u_mp_region_cfg1_base1 (
1253: .clk_i (clk_i ),
1254: .rst_ni (rst_ni ),
1255:
1256: // from register interface (qualified with register enable)
1257: .we (mp_region_cfg1_base1_we & region_cfg_regwen_qs),
1258: .wd (mp_region_cfg1_base1_wd),
1259:
1260: // from internal hardware
1261: .de (1'b0),
1262: .d ('0 ),
1263:
1264: // to internal hardware
1265: .qe (),
1266: .q (reg2hw.mp_region_cfg[1].base.q ),
1267:
1268: // to register interface (read)
1269: .qs (mp_region_cfg1_base1_qs)
1270: );
1271:
1272:
1273: // F[size1]: 24:16
1274: prim_subreg #(
1275: .DW (9),
1276: .SWACCESS("RW"),
1277: .RESVAL (9'h0)
1278: ) u_mp_region_cfg1_size1 (
1279: .clk_i (clk_i ),
1280: .rst_ni (rst_ni ),
1281:
1282: // from register interface (qualified with register enable)
1283: .we (mp_region_cfg1_size1_we & region_cfg_regwen_qs),
1284: .wd (mp_region_cfg1_size1_wd),
1285:
1286: // from internal hardware
1287: .de (1'b0),
1288: .d ('0 ),
1289:
1290: // to internal hardware
1291: .qe (),
1292: .q (reg2hw.mp_region_cfg[1].size.q ),
1293:
1294: // to register interface (read)
1295: .qs (mp_region_cfg1_size1_qs)
1296: );
1297:
1298:
1299: // Subregister 2 of Multireg mp_region_cfg
1300: // R[mp_region_cfg2]: V(False)
1301:
1302: // F[en2]: 0:0
1303: prim_subreg #(
1304: .DW (1),
1305: .SWACCESS("RW"),
1306: .RESVAL (1'h0)
1307: ) u_mp_region_cfg2_en2 (
1308: .clk_i (clk_i ),
1309: .rst_ni (rst_ni ),
1310:
1311: // from register interface (qualified with register enable)
1312: .we (mp_region_cfg2_en2_we & region_cfg_regwen_qs),
1313: .wd (mp_region_cfg2_en2_wd),
1314:
1315: // from internal hardware
1316: .de (1'b0),
1317: .d ('0 ),
1318:
1319: // to internal hardware
1320: .qe (),
1321: .q (reg2hw.mp_region_cfg[2].en.q ),
1322:
1323: // to register interface (read)
1324: .qs (mp_region_cfg2_en2_qs)
1325: );
1326:
1327:
1328: // F[rd_en2]: 1:1
1329: prim_subreg #(
1330: .DW (1),
1331: .SWACCESS("RW"),
1332: .RESVAL (1'h0)
1333: ) u_mp_region_cfg2_rd_en2 (
1334: .clk_i (clk_i ),
1335: .rst_ni (rst_ni ),
1336:
1337: // from register interface (qualified with register enable)
1338: .we (mp_region_cfg2_rd_en2_we & region_cfg_regwen_qs),
1339: .wd (mp_region_cfg2_rd_en2_wd),
1340:
1341: // from internal hardware
1342: .de (1'b0),
1343: .d ('0 ),
1344:
1345: // to internal hardware
1346: .qe (),
1347: .q (reg2hw.mp_region_cfg[2].rd_en.q ),
1348:
1349: // to register interface (read)
1350: .qs (mp_region_cfg2_rd_en2_qs)
1351: );
1352:
1353:
1354: // F[prog_en2]: 2:2
1355: prim_subreg #(
1356: .DW (1),
1357: .SWACCESS("RW"),
1358: .RESVAL (1'h0)
1359: ) u_mp_region_cfg2_prog_en2 (
1360: .clk_i (clk_i ),
1361: .rst_ni (rst_ni ),
1362:
1363: // from register interface (qualified with register enable)
1364: .we (mp_region_cfg2_prog_en2_we & region_cfg_regwen_qs),
1365: .wd (mp_region_cfg2_prog_en2_wd),
1366:
1367: // from internal hardware
1368: .de (1'b0),
1369: .d ('0 ),
1370:
1371: // to internal hardware
1372: .qe (),
1373: .q (reg2hw.mp_region_cfg[2].prog_en.q ),
1374:
1375: // to register interface (read)
1376: .qs (mp_region_cfg2_prog_en2_qs)
1377: );
1378:
1379:
1380: // F[erase_en2]: 3:3
1381: prim_subreg #(
1382: .DW (1),
1383: .SWACCESS("RW"),
1384: .RESVAL (1'h0)
1385: ) u_mp_region_cfg2_erase_en2 (
1386: .clk_i (clk_i ),
1387: .rst_ni (rst_ni ),
1388:
1389: // from register interface (qualified with register enable)
1390: .we (mp_region_cfg2_erase_en2_we & region_cfg_regwen_qs),
1391: .wd (mp_region_cfg2_erase_en2_wd),
1392:
1393: // from internal hardware
1394: .de (1'b0),
1395: .d ('0 ),
1396:
1397: // to internal hardware
1398: .qe (),
1399: .q (reg2hw.mp_region_cfg[2].erase_en.q ),
1400:
1401: // to register interface (read)
1402: .qs (mp_region_cfg2_erase_en2_qs)
1403: );
1404:
1405:
1406: // F[base2]: 12:4
1407: prim_subreg #(
1408: .DW (9),
1409: .SWACCESS("RW"),
1410: .RESVAL (9'h0)
1411: ) u_mp_region_cfg2_base2 (
1412: .clk_i (clk_i ),
1413: .rst_ni (rst_ni ),
1414:
1415: // from register interface (qualified with register enable)
1416: .we (mp_region_cfg2_base2_we & region_cfg_regwen_qs),
1417: .wd (mp_region_cfg2_base2_wd),
1418:
1419: // from internal hardware
1420: .de (1'b0),
1421: .d ('0 ),
1422:
1423: // to internal hardware
1424: .qe (),
1425: .q (reg2hw.mp_region_cfg[2].base.q ),
1426:
1427: // to register interface (read)
1428: .qs (mp_region_cfg2_base2_qs)
1429: );
1430:
1431:
1432: // F[size2]: 24:16
1433: prim_subreg #(
1434: .DW (9),
1435: .SWACCESS("RW"),
1436: .RESVAL (9'h0)
1437: ) u_mp_region_cfg2_size2 (
1438: .clk_i (clk_i ),
1439: .rst_ni (rst_ni ),
1440:
1441: // from register interface (qualified with register enable)
1442: .we (mp_region_cfg2_size2_we & region_cfg_regwen_qs),
1443: .wd (mp_region_cfg2_size2_wd),
1444:
1445: // from internal hardware
1446: .de (1'b0),
1447: .d ('0 ),
1448:
1449: // to internal hardware
1450: .qe (),
1451: .q (reg2hw.mp_region_cfg[2].size.q ),
1452:
1453: // to register interface (read)
1454: .qs (mp_region_cfg2_size2_qs)
1455: );
1456:
1457:
1458: // Subregister 3 of Multireg mp_region_cfg
1459: // R[mp_region_cfg3]: V(False)
1460:
1461: // F[en3]: 0:0
1462: prim_subreg #(
1463: .DW (1),
1464: .SWACCESS("RW"),
1465: .RESVAL (1'h0)
1466: ) u_mp_region_cfg3_en3 (
1467: .clk_i (clk_i ),
1468: .rst_ni (rst_ni ),
1469:
1470: // from register interface (qualified with register enable)
1471: .we (mp_region_cfg3_en3_we & region_cfg_regwen_qs),
1472: .wd (mp_region_cfg3_en3_wd),
1473:
1474: // from internal hardware
1475: .de (1'b0),
1476: .d ('0 ),
1477:
1478: // to internal hardware
1479: .qe (),
1480: .q (reg2hw.mp_region_cfg[3].en.q ),
1481:
1482: // to register interface (read)
1483: .qs (mp_region_cfg3_en3_qs)
1484: );
1485:
1486:
1487: // F[rd_en3]: 1:1
1488: prim_subreg #(
1489: .DW (1),
1490: .SWACCESS("RW"),
1491: .RESVAL (1'h0)
1492: ) u_mp_region_cfg3_rd_en3 (
1493: .clk_i (clk_i ),
1494: .rst_ni (rst_ni ),
1495:
1496: // from register interface (qualified with register enable)
1497: .we (mp_region_cfg3_rd_en3_we & region_cfg_regwen_qs),
1498: .wd (mp_region_cfg3_rd_en3_wd),
1499:
1500: // from internal hardware
1501: .de (1'b0),
1502: .d ('0 ),
1503:
1504: // to internal hardware
1505: .qe (),
1506: .q (reg2hw.mp_region_cfg[3].rd_en.q ),
1507:
1508: // to register interface (read)
1509: .qs (mp_region_cfg3_rd_en3_qs)
1510: );
1511:
1512:
1513: // F[prog_en3]: 2:2
1514: prim_subreg #(
1515: .DW (1),
1516: .SWACCESS("RW"),
1517: .RESVAL (1'h0)
1518: ) u_mp_region_cfg3_prog_en3 (
1519: .clk_i (clk_i ),
1520: .rst_ni (rst_ni ),
1521:
1522: // from register interface (qualified with register enable)
1523: .we (mp_region_cfg3_prog_en3_we & region_cfg_regwen_qs),
1524: .wd (mp_region_cfg3_prog_en3_wd),
1525:
1526: // from internal hardware
1527: .de (1'b0),
1528: .d ('0 ),
1529:
1530: // to internal hardware
1531: .qe (),
1532: .q (reg2hw.mp_region_cfg[3].prog_en.q ),
1533:
1534: // to register interface (read)
1535: .qs (mp_region_cfg3_prog_en3_qs)
1536: );
1537:
1538:
1539: // F[erase_en3]: 3:3
1540: prim_subreg #(
1541: .DW (1),
1542: .SWACCESS("RW"),
1543: .RESVAL (1'h0)
1544: ) u_mp_region_cfg3_erase_en3 (
1545: .clk_i (clk_i ),
1546: .rst_ni (rst_ni ),
1547:
1548: // from register interface (qualified with register enable)
1549: .we (mp_region_cfg3_erase_en3_we & region_cfg_regwen_qs),
1550: .wd (mp_region_cfg3_erase_en3_wd),
1551:
1552: // from internal hardware
1553: .de (1'b0),
1554: .d ('0 ),
1555:
1556: // to internal hardware
1557: .qe (),
1558: .q (reg2hw.mp_region_cfg[3].erase_en.q ),
1559:
1560: // to register interface (read)
1561: .qs (mp_region_cfg3_erase_en3_qs)
1562: );
1563:
1564:
1565: // F[base3]: 12:4
1566: prim_subreg #(
1567: .DW (9),
1568: .SWACCESS("RW"),
1569: .RESVAL (9'h0)
1570: ) u_mp_region_cfg3_base3 (
1571: .clk_i (clk_i ),
1572: .rst_ni (rst_ni ),
1573:
1574: // from register interface (qualified with register enable)
1575: .we (mp_region_cfg3_base3_we & region_cfg_regwen_qs),
1576: .wd (mp_region_cfg3_base3_wd),
1577:
1578: // from internal hardware
1579: .de (1'b0),
1580: .d ('0 ),
1581:
1582: // to internal hardware
1583: .qe (),
1584: .q (reg2hw.mp_region_cfg[3].base.q ),
1585:
1586: // to register interface (read)
1587: .qs (mp_region_cfg3_base3_qs)
1588: );
1589:
1590:
1591: // F[size3]: 24:16
1592: prim_subreg #(
1593: .DW (9),
1594: .SWACCESS("RW"),
1595: .RESVAL (9'h0)
1596: ) u_mp_region_cfg3_size3 (
1597: .clk_i (clk_i ),
1598: .rst_ni (rst_ni ),
1599:
1600: // from register interface (qualified with register enable)
1601: .we (mp_region_cfg3_size3_we & region_cfg_regwen_qs),
1602: .wd (mp_region_cfg3_size3_wd),
1603:
1604: // from internal hardware
1605: .de (1'b0),
1606: .d ('0 ),
1607:
1608: // to internal hardware
1609: .qe (),
1610: .q (reg2hw.mp_region_cfg[3].size.q ),
1611:
1612: // to register interface (read)
1613: .qs (mp_region_cfg3_size3_qs)
1614: );
1615:
1616:
1617: // Subregister 4 of Multireg mp_region_cfg
1618: // R[mp_region_cfg4]: V(False)
1619:
1620: // F[en4]: 0:0
1621: prim_subreg #(
1622: .DW (1),
1623: .SWACCESS("RW"),
1624: .RESVAL (1'h0)
1625: ) u_mp_region_cfg4_en4 (
1626: .clk_i (clk_i ),
1627: .rst_ni (rst_ni ),
1628:
1629: // from register interface (qualified with register enable)
1630: .we (mp_region_cfg4_en4_we & region_cfg_regwen_qs),
1631: .wd (mp_region_cfg4_en4_wd),
1632:
1633: // from internal hardware
1634: .de (1'b0),
1635: .d ('0 ),
1636:
1637: // to internal hardware
1638: .qe (),
1639: .q (reg2hw.mp_region_cfg[4].en.q ),
1640:
1641: // to register interface (read)
1642: .qs (mp_region_cfg4_en4_qs)
1643: );
1644:
1645:
1646: // F[rd_en4]: 1:1
1647: prim_subreg #(
1648: .DW (1),
1649: .SWACCESS("RW"),
1650: .RESVAL (1'h0)
1651: ) u_mp_region_cfg4_rd_en4 (
1652: .clk_i (clk_i ),
1653: .rst_ni (rst_ni ),
1654:
1655: // from register interface (qualified with register enable)
1656: .we (mp_region_cfg4_rd_en4_we & region_cfg_regwen_qs),
1657: .wd (mp_region_cfg4_rd_en4_wd),
1658:
1659: // from internal hardware
1660: .de (1'b0),
1661: .d ('0 ),
1662:
1663: // to internal hardware
1664: .qe (),
1665: .q (reg2hw.mp_region_cfg[4].rd_en.q ),
1666:
1667: // to register interface (read)
1668: .qs (mp_region_cfg4_rd_en4_qs)
1669: );
1670:
1671:
1672: // F[prog_en4]: 2:2
1673: prim_subreg #(
1674: .DW (1),
1675: .SWACCESS("RW"),
1676: .RESVAL (1'h0)
1677: ) u_mp_region_cfg4_prog_en4 (
1678: .clk_i (clk_i ),
1679: .rst_ni (rst_ni ),
1680:
1681: // from register interface (qualified with register enable)
1682: .we (mp_region_cfg4_prog_en4_we & region_cfg_regwen_qs),
1683: .wd (mp_region_cfg4_prog_en4_wd),
1684:
1685: // from internal hardware
1686: .de (1'b0),
1687: .d ('0 ),
1688:
1689: // to internal hardware
1690: .qe (),
1691: .q (reg2hw.mp_region_cfg[4].prog_en.q ),
1692:
1693: // to register interface (read)
1694: .qs (mp_region_cfg4_prog_en4_qs)
1695: );
1696:
1697:
1698: // F[erase_en4]: 3:3
1699: prim_subreg #(
1700: .DW (1),
1701: .SWACCESS("RW"),
1702: .RESVAL (1'h0)
1703: ) u_mp_region_cfg4_erase_en4 (
1704: .clk_i (clk_i ),
1705: .rst_ni (rst_ni ),
1706:
1707: // from register interface (qualified with register enable)
1708: .we (mp_region_cfg4_erase_en4_we & region_cfg_regwen_qs),
1709: .wd (mp_region_cfg4_erase_en4_wd),
1710:
1711: // from internal hardware
1712: .de (1'b0),
1713: .d ('0 ),
1714:
1715: // to internal hardware
1716: .qe (),
1717: .q (reg2hw.mp_region_cfg[4].erase_en.q ),
1718:
1719: // to register interface (read)
1720: .qs (mp_region_cfg4_erase_en4_qs)
1721: );
1722:
1723:
1724: // F[base4]: 12:4
1725: prim_subreg #(
1726: .DW (9),
1727: .SWACCESS("RW"),
1728: .RESVAL (9'h0)
1729: ) u_mp_region_cfg4_base4 (
1730: .clk_i (clk_i ),
1731: .rst_ni (rst_ni ),
1732:
1733: // from register interface (qualified with register enable)
1734: .we (mp_region_cfg4_base4_we & region_cfg_regwen_qs),
1735: .wd (mp_region_cfg4_base4_wd),
1736:
1737: // from internal hardware
1738: .de (1'b0),
1739: .d ('0 ),
1740:
1741: // to internal hardware
1742: .qe (),
1743: .q (reg2hw.mp_region_cfg[4].base.q ),
1744:
1745: // to register interface (read)
1746: .qs (mp_region_cfg4_base4_qs)
1747: );
1748:
1749:
1750: // F[size4]: 24:16
1751: prim_subreg #(
1752: .DW (9),
1753: .SWACCESS("RW"),
1754: .RESVAL (9'h0)
1755: ) u_mp_region_cfg4_size4 (
1756: .clk_i (clk_i ),
1757: .rst_ni (rst_ni ),
1758:
1759: // from register interface (qualified with register enable)
1760: .we (mp_region_cfg4_size4_we & region_cfg_regwen_qs),
1761: .wd (mp_region_cfg4_size4_wd),
1762:
1763: // from internal hardware
1764: .de (1'b0),
1765: .d ('0 ),
1766:
1767: // to internal hardware
1768: .qe (),
1769: .q (reg2hw.mp_region_cfg[4].size.q ),
1770:
1771: // to register interface (read)
1772: .qs (mp_region_cfg4_size4_qs)
1773: );
1774:
1775:
1776: // Subregister 5 of Multireg mp_region_cfg
1777: // R[mp_region_cfg5]: V(False)
1778:
1779: // F[en5]: 0:0
1780: prim_subreg #(
1781: .DW (1),
1782: .SWACCESS("RW"),
1783: .RESVAL (1'h0)
1784: ) u_mp_region_cfg5_en5 (
1785: .clk_i (clk_i ),
1786: .rst_ni (rst_ni ),
1787:
1788: // from register interface (qualified with register enable)
1789: .we (mp_region_cfg5_en5_we & region_cfg_regwen_qs),
1790: .wd (mp_region_cfg5_en5_wd),
1791:
1792: // from internal hardware
1793: .de (1'b0),
1794: .d ('0 ),
1795:
1796: // to internal hardware
1797: .qe (),
1798: .q (reg2hw.mp_region_cfg[5].en.q ),
1799:
1800: // to register interface (read)
1801: .qs (mp_region_cfg5_en5_qs)
1802: );
1803:
1804:
1805: // F[rd_en5]: 1:1
1806: prim_subreg #(
1807: .DW (1),
1808: .SWACCESS("RW"),
1809: .RESVAL (1'h0)
1810: ) u_mp_region_cfg5_rd_en5 (
1811: .clk_i (clk_i ),
1812: .rst_ni (rst_ni ),
1813:
1814: // from register interface (qualified with register enable)
1815: .we (mp_region_cfg5_rd_en5_we & region_cfg_regwen_qs),
1816: .wd (mp_region_cfg5_rd_en5_wd),
1817:
1818: // from internal hardware
1819: .de (1'b0),
1820: .d ('0 ),
1821:
1822: // to internal hardware
1823: .qe (),
1824: .q (reg2hw.mp_region_cfg[5].rd_en.q ),
1825:
1826: // to register interface (read)
1827: .qs (mp_region_cfg5_rd_en5_qs)
1828: );
1829:
1830:
1831: // F[prog_en5]: 2:2
1832: prim_subreg #(
1833: .DW (1),
1834: .SWACCESS("RW"),
1835: .RESVAL (1'h0)
1836: ) u_mp_region_cfg5_prog_en5 (
1837: .clk_i (clk_i ),
1838: .rst_ni (rst_ni ),
1839:
1840: // from register interface (qualified with register enable)
1841: .we (mp_region_cfg5_prog_en5_we & region_cfg_regwen_qs),
1842: .wd (mp_region_cfg5_prog_en5_wd),
1843:
1844: // from internal hardware
1845: .de (1'b0),
1846: .d ('0 ),
1847:
1848: // to internal hardware
1849: .qe (),
1850: .q (reg2hw.mp_region_cfg[5].prog_en.q ),
1851:
1852: // to register interface (read)
1853: .qs (mp_region_cfg5_prog_en5_qs)
1854: );
1855:
1856:
1857: // F[erase_en5]: 3:3
1858: prim_subreg #(
1859: .DW (1),
1860: .SWACCESS("RW"),
1861: .RESVAL (1'h0)
1862: ) u_mp_region_cfg5_erase_en5 (
1863: .clk_i (clk_i ),
1864: .rst_ni (rst_ni ),
1865:
1866: // from register interface (qualified with register enable)
1867: .we (mp_region_cfg5_erase_en5_we & region_cfg_regwen_qs),
1868: .wd (mp_region_cfg5_erase_en5_wd),
1869:
1870: // from internal hardware
1871: .de (1'b0),
1872: .d ('0 ),
1873:
1874: // to internal hardware
1875: .qe (),
1876: .q (reg2hw.mp_region_cfg[5].erase_en.q ),
1877:
1878: // to register interface (read)
1879: .qs (mp_region_cfg5_erase_en5_qs)
1880: );
1881:
1882:
1883: // F[base5]: 12:4
1884: prim_subreg #(
1885: .DW (9),
1886: .SWACCESS("RW"),
1887: .RESVAL (9'h0)
1888: ) u_mp_region_cfg5_base5 (
1889: .clk_i (clk_i ),
1890: .rst_ni (rst_ni ),
1891:
1892: // from register interface (qualified with register enable)
1893: .we (mp_region_cfg5_base5_we & region_cfg_regwen_qs),
1894: .wd (mp_region_cfg5_base5_wd),
1895:
1896: // from internal hardware
1897: .de (1'b0),
1898: .d ('0 ),
1899:
1900: // to internal hardware
1901: .qe (),
1902: .q (reg2hw.mp_region_cfg[5].base.q ),
1903:
1904: // to register interface (read)
1905: .qs (mp_region_cfg5_base5_qs)
1906: );
1907:
1908:
1909: // F[size5]: 24:16
1910: prim_subreg #(
1911: .DW (9),
1912: .SWACCESS("RW"),
1913: .RESVAL (9'h0)
1914: ) u_mp_region_cfg5_size5 (
1915: .clk_i (clk_i ),
1916: .rst_ni (rst_ni ),
1917:
1918: // from register interface (qualified with register enable)
1919: .we (mp_region_cfg5_size5_we & region_cfg_regwen_qs),
1920: .wd (mp_region_cfg5_size5_wd),
1921:
1922: // from internal hardware
1923: .de (1'b0),
1924: .d ('0 ),
1925:
1926: // to internal hardware
1927: .qe (),
1928: .q (reg2hw.mp_region_cfg[5].size.q ),
1929:
1930: // to register interface (read)
1931: .qs (mp_region_cfg5_size5_qs)
1932: );
1933:
1934:
1935: // Subregister 6 of Multireg mp_region_cfg
1936: // R[mp_region_cfg6]: V(False)
1937:
1938: // F[en6]: 0:0
1939: prim_subreg #(
1940: .DW (1),
1941: .SWACCESS("RW"),
1942: .RESVAL (1'h0)
1943: ) u_mp_region_cfg6_en6 (
1944: .clk_i (clk_i ),
1945: .rst_ni (rst_ni ),
1946:
1947: // from register interface (qualified with register enable)
1948: .we (mp_region_cfg6_en6_we & region_cfg_regwen_qs),
1949: .wd (mp_region_cfg6_en6_wd),
1950:
1951: // from internal hardware
1952: .de (1'b0),
1953: .d ('0 ),
1954:
1955: // to internal hardware
1956: .qe (),
1957: .q (reg2hw.mp_region_cfg[6].en.q ),
1958:
1959: // to register interface (read)
1960: .qs (mp_region_cfg6_en6_qs)
1961: );
1962:
1963:
1964: // F[rd_en6]: 1:1
1965: prim_subreg #(
1966: .DW (1),
1967: .SWACCESS("RW"),
1968: .RESVAL (1'h0)
1969: ) u_mp_region_cfg6_rd_en6 (
1970: .clk_i (clk_i ),
1971: .rst_ni (rst_ni ),
1972:
1973: // from register interface (qualified with register enable)
1974: .we (mp_region_cfg6_rd_en6_we & region_cfg_regwen_qs),
1975: .wd (mp_region_cfg6_rd_en6_wd),
1976:
1977: // from internal hardware
1978: .de (1'b0),
1979: .d ('0 ),
1980:
1981: // to internal hardware
1982: .qe (),
1983: .q (reg2hw.mp_region_cfg[6].rd_en.q ),
1984:
1985: // to register interface (read)
1986: .qs (mp_region_cfg6_rd_en6_qs)
1987: );
1988:
1989:
1990: // F[prog_en6]: 2:2
1991: prim_subreg #(
1992: .DW (1),
1993: .SWACCESS("RW"),
1994: .RESVAL (1'h0)
1995: ) u_mp_region_cfg6_prog_en6 (
1996: .clk_i (clk_i ),
1997: .rst_ni (rst_ni ),
1998:
1999: // from register interface (qualified with register enable)
2000: .we (mp_region_cfg6_prog_en6_we & region_cfg_regwen_qs),
2001: .wd (mp_region_cfg6_prog_en6_wd),
2002:
2003: // from internal hardware
2004: .de (1'b0),
2005: .d ('0 ),
2006:
2007: // to internal hardware
2008: .qe (),
2009: .q (reg2hw.mp_region_cfg[6].prog_en.q ),
2010:
2011: // to register interface (read)
2012: .qs (mp_region_cfg6_prog_en6_qs)
2013: );
2014:
2015:
2016: // F[erase_en6]: 3:3
2017: prim_subreg #(
2018: .DW (1),
2019: .SWACCESS("RW"),
2020: .RESVAL (1'h0)
2021: ) u_mp_region_cfg6_erase_en6 (
2022: .clk_i (clk_i ),
2023: .rst_ni (rst_ni ),
2024:
2025: // from register interface (qualified with register enable)
2026: .we (mp_region_cfg6_erase_en6_we & region_cfg_regwen_qs),
2027: .wd (mp_region_cfg6_erase_en6_wd),
2028:
2029: // from internal hardware
2030: .de (1'b0),
2031: .d ('0 ),
2032:
2033: // to internal hardware
2034: .qe (),
2035: .q (reg2hw.mp_region_cfg[6].erase_en.q ),
2036:
2037: // to register interface (read)
2038: .qs (mp_region_cfg6_erase_en6_qs)
2039: );
2040:
2041:
2042: // F[base6]: 12:4
2043: prim_subreg #(
2044: .DW (9),
2045: .SWACCESS("RW"),
2046: .RESVAL (9'h0)
2047: ) u_mp_region_cfg6_base6 (
2048: .clk_i (clk_i ),
2049: .rst_ni (rst_ni ),
2050:
2051: // from register interface (qualified with register enable)
2052: .we (mp_region_cfg6_base6_we & region_cfg_regwen_qs),
2053: .wd (mp_region_cfg6_base6_wd),
2054:
2055: // from internal hardware
2056: .de (1'b0),
2057: .d ('0 ),
2058:
2059: // to internal hardware
2060: .qe (),
2061: .q (reg2hw.mp_region_cfg[6].base.q ),
2062:
2063: // to register interface (read)
2064: .qs (mp_region_cfg6_base6_qs)
2065: );
2066:
2067:
2068: // F[size6]: 24:16
2069: prim_subreg #(
2070: .DW (9),
2071: .SWACCESS("RW"),
2072: .RESVAL (9'h0)
2073: ) u_mp_region_cfg6_size6 (
2074: .clk_i (clk_i ),
2075: .rst_ni (rst_ni ),
2076:
2077: // from register interface (qualified with register enable)
2078: .we (mp_region_cfg6_size6_we & region_cfg_regwen_qs),
2079: .wd (mp_region_cfg6_size6_wd),
2080:
2081: // from internal hardware
2082: .de (1'b0),
2083: .d ('0 ),
2084:
2085: // to internal hardware
2086: .qe (),
2087: .q (reg2hw.mp_region_cfg[6].size.q ),
2088:
2089: // to register interface (read)
2090: .qs (mp_region_cfg6_size6_qs)
2091: );
2092:
2093:
2094: // Subregister 7 of Multireg mp_region_cfg
2095: // R[mp_region_cfg7]: V(False)
2096:
2097: // F[en7]: 0:0
2098: prim_subreg #(
2099: .DW (1),
2100: .SWACCESS("RW"),
2101: .RESVAL (1'h0)
2102: ) u_mp_region_cfg7_en7 (
2103: .clk_i (clk_i ),
2104: .rst_ni (rst_ni ),
2105:
2106: // from register interface (qualified with register enable)
2107: .we (mp_region_cfg7_en7_we & region_cfg_regwen_qs),
2108: .wd (mp_region_cfg7_en7_wd),
2109:
2110: // from internal hardware
2111: .de (1'b0),
2112: .d ('0 ),
2113:
2114: // to internal hardware
2115: .qe (),
2116: .q (reg2hw.mp_region_cfg[7].en.q ),
2117:
2118: // to register interface (read)
2119: .qs (mp_region_cfg7_en7_qs)
2120: );
2121:
2122:
2123: // F[rd_en7]: 1:1
2124: prim_subreg #(
2125: .DW (1),
2126: .SWACCESS("RW"),
2127: .RESVAL (1'h0)
2128: ) u_mp_region_cfg7_rd_en7 (
2129: .clk_i (clk_i ),
2130: .rst_ni (rst_ni ),
2131:
2132: // from register interface (qualified with register enable)
2133: .we (mp_region_cfg7_rd_en7_we & region_cfg_regwen_qs),
2134: .wd (mp_region_cfg7_rd_en7_wd),
2135:
2136: // from internal hardware
2137: .de (1'b0),
2138: .d ('0 ),
2139:
2140: // to internal hardware
2141: .qe (),
2142: .q (reg2hw.mp_region_cfg[7].rd_en.q ),
2143:
2144: // to register interface (read)
2145: .qs (mp_region_cfg7_rd_en7_qs)
2146: );
2147:
2148:
2149: // F[prog_en7]: 2:2
2150: prim_subreg #(
2151: .DW (1),
2152: .SWACCESS("RW"),
2153: .RESVAL (1'h0)
2154: ) u_mp_region_cfg7_prog_en7 (
2155: .clk_i (clk_i ),
2156: .rst_ni (rst_ni ),
2157:
2158: // from register interface (qualified with register enable)
2159: .we (mp_region_cfg7_prog_en7_we & region_cfg_regwen_qs),
2160: .wd (mp_region_cfg7_prog_en7_wd),
2161:
2162: // from internal hardware
2163: .de (1'b0),
2164: .d ('0 ),
2165:
2166: // to internal hardware
2167: .qe (),
2168: .q (reg2hw.mp_region_cfg[7].prog_en.q ),
2169:
2170: // to register interface (read)
2171: .qs (mp_region_cfg7_prog_en7_qs)
2172: );
2173:
2174:
2175: // F[erase_en7]: 3:3
2176: prim_subreg #(
2177: .DW (1),
2178: .SWACCESS("RW"),
2179: .RESVAL (1'h0)
2180: ) u_mp_region_cfg7_erase_en7 (
2181: .clk_i (clk_i ),
2182: .rst_ni (rst_ni ),
2183:
2184: // from register interface (qualified with register enable)
2185: .we (mp_region_cfg7_erase_en7_we & region_cfg_regwen_qs),
2186: .wd (mp_region_cfg7_erase_en7_wd),
2187:
2188: // from internal hardware
2189: .de (1'b0),
2190: .d ('0 ),
2191:
2192: // to internal hardware
2193: .qe (),
2194: .q (reg2hw.mp_region_cfg[7].erase_en.q ),
2195:
2196: // to register interface (read)
2197: .qs (mp_region_cfg7_erase_en7_qs)
2198: );
2199:
2200:
2201: // F[base7]: 12:4
2202: prim_subreg #(
2203: .DW (9),
2204: .SWACCESS("RW"),
2205: .RESVAL (9'h0)
2206: ) u_mp_region_cfg7_base7 (
2207: .clk_i (clk_i ),
2208: .rst_ni (rst_ni ),
2209:
2210: // from register interface (qualified with register enable)
2211: .we (mp_region_cfg7_base7_we & region_cfg_regwen_qs),
2212: .wd (mp_region_cfg7_base7_wd),
2213:
2214: // from internal hardware
2215: .de (1'b0),
2216: .d ('0 ),
2217:
2218: // to internal hardware
2219: .qe (),
2220: .q (reg2hw.mp_region_cfg[7].base.q ),
2221:
2222: // to register interface (read)
2223: .qs (mp_region_cfg7_base7_qs)
2224: );
2225:
2226:
2227: // F[size7]: 24:16
2228: prim_subreg #(
2229: .DW (9),
2230: .SWACCESS("RW"),
2231: .RESVAL (9'h0)
2232: ) u_mp_region_cfg7_size7 (
2233: .clk_i (clk_i ),
2234: .rst_ni (rst_ni ),
2235:
2236: // from register interface (qualified with register enable)
2237: .we (mp_region_cfg7_size7_we & region_cfg_regwen_qs),
2238: .wd (mp_region_cfg7_size7_wd),
2239:
2240: // from internal hardware
2241: .de (1'b0),
2242: .d ('0 ),
2243:
2244: // to internal hardware
2245: .qe (),
2246: .q (reg2hw.mp_region_cfg[7].size.q ),
2247:
2248: // to register interface (read)
2249: .qs (mp_region_cfg7_size7_qs)
2250: );
2251:
2252:
2253:
2254: // R[default_region]: V(False)
2255:
2256: // F[rd_en]: 0:0
2257: prim_subreg #(
2258: .DW (1),
2259: .SWACCESS("RW"),
2260: .RESVAL (1'h0)
2261: ) u_default_region_rd_en (
2262: .clk_i (clk_i ),
2263: .rst_ni (rst_ni ),
2264:
2265: // from register interface
2266: .we (default_region_rd_en_we),
2267: .wd (default_region_rd_en_wd),
2268:
2269: // from internal hardware
2270: .de (1'b0),
2271: .d ('0 ),
2272:
2273: // to internal hardware
2274: .qe (),
2275: .q (reg2hw.default_region.rd_en.q ),
2276:
2277: // to register interface (read)
2278: .qs (default_region_rd_en_qs)
2279: );
2280:
2281:
2282: // F[prog_en]: 1:1
2283: prim_subreg #(
2284: .DW (1),
2285: .SWACCESS("RW"),
2286: .RESVAL (1'h0)
2287: ) u_default_region_prog_en (
2288: .clk_i (clk_i ),
2289: .rst_ni (rst_ni ),
2290:
2291: // from register interface
2292: .we (default_region_prog_en_we),
2293: .wd (default_region_prog_en_wd),
2294:
2295: // from internal hardware
2296: .de (1'b0),
2297: .d ('0 ),
2298:
2299: // to internal hardware
2300: .qe (),
2301: .q (reg2hw.default_region.prog_en.q ),
2302:
2303: // to register interface (read)
2304: .qs (default_region_prog_en_qs)
2305: );
2306:
2307:
2308: // F[erase_en]: 2:2
2309: prim_subreg #(
2310: .DW (1),
2311: .SWACCESS("RW"),
2312: .RESVAL (1'h0)
2313: ) u_default_region_erase_en (
2314: .clk_i (clk_i ),
2315: .rst_ni (rst_ni ),
2316:
2317: // from register interface
2318: .we (default_region_erase_en_we),
2319: .wd (default_region_erase_en_wd),
2320:
2321: // from internal hardware
2322: .de (1'b0),
2323: .d ('0 ),
2324:
2325: // to internal hardware
2326: .qe (),
2327: .q (reg2hw.default_region.erase_en.q ),
2328:
2329: // to register interface (read)
2330: .qs (default_region_erase_en_qs)
2331: );
2332:
2333:
2334: // R[bank_cfg_regwen]: V(False)
2335:
2336: prim_subreg #(
2337: .DW (1),
2338: .SWACCESS("W0C"),
2339: .RESVAL (1'h1)
2340: ) u_bank_cfg_regwen (
2341: .clk_i (clk_i ),
2342: .rst_ni (rst_ni ),
2343:
2344: // from register interface
2345: .we (bank_cfg_regwen_we),
2346: .wd (bank_cfg_regwen_wd),
2347:
2348: // from internal hardware
2349: .de (1'b0),
2350: .d ('0 ),
2351:
2352: // to internal hardware
2353: .qe (),
2354: .q (),
2355:
2356: // to register interface (read)
2357: .qs (bank_cfg_regwen_qs)
2358: );
2359:
2360:
2361:
2362: // Subregister 0 of Multireg mp_bank_cfg
2363: // R[mp_bank_cfg]: V(False)
2364:
2365: // F[erase_en0]: 0:0
2366: prim_subreg #(
2367: .DW (1),
2368: .SWACCESS("RW"),
2369: .RESVAL (1'h0)
2370: ) u_mp_bank_cfg_erase_en0 (
2371: .clk_i (clk_i ),
2372: .rst_ni (rst_ni ),
2373:
2374: // from register interface (qualified with register enable)
2375: .we (mp_bank_cfg_erase_en0_we & bank_cfg_regwen_qs),
2376: .wd (mp_bank_cfg_erase_en0_wd),
2377:
2378: // from internal hardware
2379: .de (1'b0),
2380: .d ('0 ),
2381:
2382: // to internal hardware
2383: .qe (),
2384: .q (reg2hw.mp_bank_cfg[0].q ),
2385:
2386: // to register interface (read)
2387: .qs (mp_bank_cfg_erase_en0_qs)
2388: );
2389:
2390:
2391: // F[erase_en1]: 1:1
2392: prim_subreg #(
2393: .DW (1),
2394: .SWACCESS("RW"),
2395: .RESVAL (1'h0)
2396: ) u_mp_bank_cfg_erase_en1 (
2397: .clk_i (clk_i ),
2398: .rst_ni (rst_ni ),
2399:
2400: // from register interface (qualified with register enable)
2401: .we (mp_bank_cfg_erase_en1_we & bank_cfg_regwen_qs),
2402: .wd (mp_bank_cfg_erase_en1_wd),
2403:
2404: // from internal hardware
2405: .de (1'b0),
2406: .d ('0 ),
2407:
2408: // to internal hardware
2409: .qe (),
2410: .q (reg2hw.mp_bank_cfg[1].q ),
2411:
2412: // to register interface (read)
2413: .qs (mp_bank_cfg_erase_en1_qs)
2414: );
2415:
2416:
2417:
2418: // R[op_status]: V(False)
2419:
2420: // F[done]: 0:0
2421: prim_subreg #(
2422: .DW (1),
2423: .SWACCESS("RW"),
2424: .RESVAL (1'h0)
2425: ) u_op_status_done (
2426: .clk_i (clk_i ),
2427: .rst_ni (rst_ni ),
2428:
2429: // from register interface
2430: .we (op_status_done_we),
2431: .wd (op_status_done_wd),
2432:
2433: // from internal hardware
2434: .de (hw2reg.op_status.done.de),
2435: .d (hw2reg.op_status.done.d ),
2436:
2437: // to internal hardware
2438: .qe (),
2439: .q (),
2440:
2441: // to register interface (read)
2442: .qs (op_status_done_qs)
2443: );
2444:
2445:
2446: // F[err]: 1:1
2447: prim_subreg #(
2448: .DW (1),
2449: .SWACCESS("RW"),
2450: .RESVAL (1'h0)
2451: ) u_op_status_err (
2452: .clk_i (clk_i ),
2453: .rst_ni (rst_ni ),
2454:
2455: // from register interface
2456: .we (op_status_err_we),
2457: .wd (op_status_err_wd),
2458:
2459: // from internal hardware
2460: .de (hw2reg.op_status.err.de),
2461: .d (hw2reg.op_status.err.d ),
2462:
2463: // to internal hardware
2464: .qe (),
2465: .q (),
2466:
2467: // to register interface (read)
2468: .qs (op_status_err_qs)
2469: );
2470:
2471:
2472: // R[status]: V(True)
2473:
2474: // F[rd_full]: 0:0
2475: prim_subreg_ext #(
2476: .DW (1)
2477: ) u_status_rd_full (
2478: .re (status_rd_full_re),
2479: .we (1'b0),
2480: .wd ('0),
2481: .d (hw2reg.status.rd_full.d),
2482: .qre (),
2483: .qe (),
2484: .q (),
2485: .qs (status_rd_full_qs)
2486: );
2487:
2488:
2489: // F[rd_empty]: 1:1
2490: prim_subreg_ext #(
2491: .DW (1)
2492: ) u_status_rd_empty (
2493: .re (status_rd_empty_re),
2494: .we (1'b0),
2495: .wd ('0),
2496: .d (hw2reg.status.rd_empty.d),
2497: .qre (),
2498: .qe (),
2499: .q (),
2500: .qs (status_rd_empty_qs)
2501: );
2502:
2503:
2504: // F[prog_full]: 2:2
2505: prim_subreg_ext #(
2506: .DW (1)
2507: ) u_status_prog_full (
2508: .re (status_prog_full_re),
2509: .we (1'b0),
2510: .wd ('0),
2511: .d (hw2reg.status.prog_full.d),
2512: .qre (),
2513: .qe (),
2514: .q (),
2515: .qs (status_prog_full_qs)
2516: );
2517:
2518:
2519: // F[prog_empty]: 3:3
2520: prim_subreg_ext #(
2521: .DW (1)
2522: ) u_status_prog_empty (
2523: .re (status_prog_empty_re),
2524: .we (1'b0),
2525: .wd ('0),
2526: .d (hw2reg.status.prog_empty.d),
2527: .qre (),
2528: .qe (),
2529: .q (),
2530: .qs (status_prog_empty_qs)
2531: );
2532:
2533:
2534: // F[init_wip]: 4:4
2535: prim_subreg_ext #(
2536: .DW (1)
2537: ) u_status_init_wip (
2538: .re (status_init_wip_re),
2539: .we (1'b0),
2540: .wd ('0),
2541: .d (hw2reg.status.init_wip.d),
2542: .qre (),
2543: .qe (),
2544: .q (),
2545: .qs (status_init_wip_qs)
2546: );
2547:
2548:
2549: // F[error_page]: 16:8
2550: prim_subreg_ext #(
2551: .DW (9)
2552: ) u_status_error_page (
2553: .re (status_error_page_re),
2554: .we (1'b0),
2555: .wd ('0),
2556: .d (hw2reg.status.error_page.d),
2557: .qre (),
2558: .qe (),
2559: .q (),
2560: .qs (status_error_page_qs)
2561: );
2562:
2563:
2564: // F[error_bank]: 17:17
2565: prim_subreg_ext #(
2566: .DW (1)
2567: ) u_status_error_bank (
2568: .re (status_error_bank_re),
2569: .we (1'b0),
2570: .wd ('0),
2571: .d (hw2reg.status.error_bank.d),
2572: .qre (),
2573: .qe (),
2574: .q (),
2575: .qs (status_error_bank_qs)
2576: );
2577:
2578:
2579: // R[scratch]: V(False)
2580:
2581: prim_subreg #(
2582: .DW (32),
2583: .SWACCESS("RW"),
2584: .RESVAL (32'h0)
2585: ) u_scratch (
2586: .clk_i (clk_i ),
2587: .rst_ni (rst_ni ),
2588:
2589: // from register interface
2590: .we (scratch_we),
2591: .wd (scratch_wd),
2592:
2593: // from internal hardware
2594: .de (1'b0),
2595: .d ('0 ),
2596:
2597: // to internal hardware
2598: .qe (),
2599: .q (reg2hw.scratch.q ),
2600:
2601: // to register interface (read)
2602: .qs (scratch_qs)
2603: );
2604:
2605:
2606: // R[fifo_lvl]: V(False)
2607:
2608: // F[prog]: 4:0
2609: prim_subreg #(
2610: .DW (5),
2611: .SWACCESS("RW"),
2612: .RESVAL (5'hf)
2613: ) u_fifo_lvl_prog (
2614: .clk_i (clk_i ),
2615: .rst_ni (rst_ni ),
2616:
2617: // from register interface
2618: .we (fifo_lvl_prog_we),
2619: .wd (fifo_lvl_prog_wd),
2620:
2621: // from internal hardware
2622: .de (1'b0),
2623: .d ('0 ),
2624:
2625: // to internal hardware
2626: .qe (),
2627: .q (reg2hw.fifo_lvl.prog.q ),
2628:
2629: // to register interface (read)
2630: .qs (fifo_lvl_prog_qs)
2631: );
2632:
2633:
2634: // F[rd]: 12:8
2635: prim_subreg #(
2636: .DW (5),
2637: .SWACCESS("RW"),
2638: .RESVAL (5'hf)
2639: ) u_fifo_lvl_rd (
2640: .clk_i (clk_i ),
2641: .rst_ni (rst_ni ),
2642:
2643: // from register interface
2644: .we (fifo_lvl_rd_we),
2645: .wd (fifo_lvl_rd_wd),
2646:
2647: // from internal hardware
2648: .de (1'b0),
2649: .d ('0 ),
2650:
2651: // to internal hardware
2652: .qe (),
2653: .q (reg2hw.fifo_lvl.rd.q ),
2654:
2655: // to register interface (read)
2656: .qs (fifo_lvl_rd_qs)
2657: );
2658:
2659:
2660:
2661:
2662: logic [20:0] addr_hit;
2663: always_comb begin
2664: addr_hit = '0;
2665: addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
2666: addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
2667: addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
2668: addr_hit[ 3] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
2669: addr_hit[ 4] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
2670: addr_hit[ 5] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_OFFSET);
2671: addr_hit[ 6] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET);
2672: addr_hit[ 7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET);
2673: addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET);
2674: addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET);
2675: addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET);
2676: addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET);
2677: addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET);
2678: addr_hit[13] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET);
2679: addr_hit[14] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
2680: addr_hit[15] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
2681: addr_hit[16] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
2682: addr_hit[17] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
2683: addr_hit[18] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
2684: addr_hit[19] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
2685: addr_hit[20] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
2686: end
2687:
2688: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
2689:
2690: // Check sub-word write is permitted
2691: always_comb begin
2692: wr_err = 1'b0;
2693: if (addr_hit[ 0] && reg_we && (FLASH_CTRL_PERMIT[ 0] != (FLASH_CTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
2694: if (addr_hit[ 1] && reg_we && (FLASH_CTRL_PERMIT[ 1] != (FLASH_CTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
2695: if (addr_hit[ 2] && reg_we && (FLASH_CTRL_PERMIT[ 2] != (FLASH_CTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
2696: if (addr_hit[ 3] && reg_we && (FLASH_CTRL_PERMIT[ 3] != (FLASH_CTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
2697: if (addr_hit[ 4] && reg_we && (FLASH_CTRL_PERMIT[ 4] != (FLASH_CTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
2698: if (addr_hit[ 5] && reg_we && (FLASH_CTRL_PERMIT[ 5] != (FLASH_CTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
2699: if (addr_hit[ 6] && reg_we && (FLASH_CTRL_PERMIT[ 6] != (FLASH_CTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
2700: if (addr_hit[ 7] && reg_we && (FLASH_CTRL_PERMIT[ 7] != (FLASH_CTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
2701: if (addr_hit[ 8] && reg_we && (FLASH_CTRL_PERMIT[ 8] != (FLASH_CTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
2702: if (addr_hit[ 9] && reg_we && (FLASH_CTRL_PERMIT[ 9] != (FLASH_CTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
2703: if (addr_hit[10] && reg_we && (FLASH_CTRL_PERMIT[10] != (FLASH_CTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
2704: if (addr_hit[11] && reg_we && (FLASH_CTRL_PERMIT[11] != (FLASH_CTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
2705: if (addr_hit[12] && reg_we && (FLASH_CTRL_PERMIT[12] != (FLASH_CTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
2706: if (addr_hit[13] && reg_we && (FLASH_CTRL_PERMIT[13] != (FLASH_CTRL_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
2707: if (addr_hit[14] && reg_we && (FLASH_CTRL_PERMIT[14] != (FLASH_CTRL_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
2708: if (addr_hit[15] && reg_we && (FLASH_CTRL_PERMIT[15] != (FLASH_CTRL_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
2709: if (addr_hit[16] && reg_we && (FLASH_CTRL_PERMIT[16] != (FLASH_CTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
2710: if (addr_hit[17] && reg_we && (FLASH_CTRL_PERMIT[17] != (FLASH_CTRL_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
2711: if (addr_hit[18] && reg_we && (FLASH_CTRL_PERMIT[18] != (FLASH_CTRL_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
2712: if (addr_hit[19] && reg_we && (FLASH_CTRL_PERMIT[19] != (FLASH_CTRL_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
2713: if (addr_hit[20] && reg_we && (FLASH_CTRL_PERMIT[20] != (FLASH_CTRL_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
2714: end
2715:
2716: assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
2717: assign intr_state_prog_empty_wd = reg_wdata[0];
2718:
2719: assign intr_state_prog_lvl_we = addr_hit[0] & reg_we & ~wr_err;
2720: assign intr_state_prog_lvl_wd = reg_wdata[1];
2721:
2722: assign intr_state_rd_full_we = addr_hit[0] & reg_we & ~wr_err;
2723: assign intr_state_rd_full_wd = reg_wdata[2];
2724:
2725: assign intr_state_rd_lvl_we = addr_hit[0] & reg_we & ~wr_err;
2726: assign intr_state_rd_lvl_wd = reg_wdata[3];
2727:
2728: assign intr_state_op_done_we = addr_hit[0] & reg_we & ~wr_err;
2729: assign intr_state_op_done_wd = reg_wdata[4];
2730:
2731: assign intr_state_op_error_we = addr_hit[0] & reg_we & ~wr_err;
2732: assign intr_state_op_error_wd = reg_wdata[5];
2733:
2734: assign intr_enable_prog_empty_we = addr_hit[1] & reg_we & ~wr_err;
2735: assign intr_enable_prog_empty_wd = reg_wdata[0];
2736:
2737: assign intr_enable_prog_lvl_we = addr_hit[1] & reg_we & ~wr_err;
2738: assign intr_enable_prog_lvl_wd = reg_wdata[1];
2739:
2740: assign intr_enable_rd_full_we = addr_hit[1] & reg_we & ~wr_err;
2741: assign intr_enable_rd_full_wd = reg_wdata[2];
2742:
2743: assign intr_enable_rd_lvl_we = addr_hit[1] & reg_we & ~wr_err;
2744: assign intr_enable_rd_lvl_wd = reg_wdata[3];
2745:
2746: assign intr_enable_op_done_we = addr_hit[1] & reg_we & ~wr_err;
2747: assign intr_enable_op_done_wd = reg_wdata[4];
2748:
2749: assign intr_enable_op_error_we = addr_hit[1] & reg_we & ~wr_err;
2750: assign intr_enable_op_error_wd = reg_wdata[5];
2751:
2752: assign intr_test_prog_empty_we = addr_hit[2] & reg_we & ~wr_err;
2753: assign intr_test_prog_empty_wd = reg_wdata[0];
2754:
2755: assign intr_test_prog_lvl_we = addr_hit[2] & reg_we & ~wr_err;
2756: assign intr_test_prog_lvl_wd = reg_wdata[1];
2757:
2758: assign intr_test_rd_full_we = addr_hit[2] & reg_we & ~wr_err;
2759: assign intr_test_rd_full_wd = reg_wdata[2];
2760:
2761: assign intr_test_rd_lvl_we = addr_hit[2] & reg_we & ~wr_err;
2762: assign intr_test_rd_lvl_wd = reg_wdata[3];
2763:
2764: assign intr_test_op_done_we = addr_hit[2] & reg_we & ~wr_err;
2765: assign intr_test_op_done_wd = reg_wdata[4];
2766:
2767: assign intr_test_op_error_we = addr_hit[2] & reg_we & ~wr_err;
2768: assign intr_test_op_error_wd = reg_wdata[5];
2769:
2770: assign control_start_we = addr_hit[3] & reg_we & ~wr_err;
2771: assign control_start_wd = reg_wdata[0];
2772:
2773: assign control_op_we = addr_hit[3] & reg_we & ~wr_err;
2774: assign control_op_wd = reg_wdata[5:4];
2775:
2776: assign control_erase_sel_we = addr_hit[3] & reg_we & ~wr_err;
2777: assign control_erase_sel_wd = reg_wdata[6];
2778:
2779: assign control_fifo_rst_we = addr_hit[3] & reg_we & ~wr_err;
2780: assign control_fifo_rst_wd = reg_wdata[7];
2781:
2782: assign control_num_we = addr_hit[3] & reg_we & ~wr_err;
2783: assign control_num_wd = reg_wdata[27:16];
2784:
2785: assign addr_we = addr_hit[4] & reg_we & ~wr_err;
2786: assign addr_wd = reg_wdata[31:0];
2787:
2788: assign region_cfg_regwen_we = addr_hit[5] & reg_we & ~wr_err;
2789: assign region_cfg_regwen_wd = reg_wdata[0];
2790:
2791: assign mp_region_cfg0_en0_we = addr_hit[6] & reg_we & ~wr_err;
2792: assign mp_region_cfg0_en0_wd = reg_wdata[0];
2793:
2794: assign mp_region_cfg0_rd_en0_we = addr_hit[6] & reg_we & ~wr_err;
2795: assign mp_region_cfg0_rd_en0_wd = reg_wdata[1];
2796:
2797: assign mp_region_cfg0_prog_en0_we = addr_hit[6] & reg_we & ~wr_err;
2798: assign mp_region_cfg0_prog_en0_wd = reg_wdata[2];
2799:
2800: assign mp_region_cfg0_erase_en0_we = addr_hit[6] & reg_we & ~wr_err;
2801: assign mp_region_cfg0_erase_en0_wd = reg_wdata[3];
2802:
2803: assign mp_region_cfg0_base0_we = addr_hit[6] & reg_we & ~wr_err;
2804: assign mp_region_cfg0_base0_wd = reg_wdata[12:4];
2805:
2806: assign mp_region_cfg0_size0_we = addr_hit[6] & reg_we & ~wr_err;
2807: assign mp_region_cfg0_size0_wd = reg_wdata[24:16];
2808:
2809: assign mp_region_cfg1_en1_we = addr_hit[7] & reg_we & ~wr_err;
2810: assign mp_region_cfg1_en1_wd = reg_wdata[0];
2811:
2812: assign mp_region_cfg1_rd_en1_we = addr_hit[7] & reg_we & ~wr_err;
2813: assign mp_region_cfg1_rd_en1_wd = reg_wdata[1];
2814:
2815: assign mp_region_cfg1_prog_en1_we = addr_hit[7] & reg_we & ~wr_err;
2816: assign mp_region_cfg1_prog_en1_wd = reg_wdata[2];
2817:
2818: assign mp_region_cfg1_erase_en1_we = addr_hit[7] & reg_we & ~wr_err;
2819: assign mp_region_cfg1_erase_en1_wd = reg_wdata[3];
2820:
2821: assign mp_region_cfg1_base1_we = addr_hit[7] & reg_we & ~wr_err;
2822: assign mp_region_cfg1_base1_wd = reg_wdata[12:4];
2823:
2824: assign mp_region_cfg1_size1_we = addr_hit[7] & reg_we & ~wr_err;
2825: assign mp_region_cfg1_size1_wd = reg_wdata[24:16];
2826:
2827: assign mp_region_cfg2_en2_we = addr_hit[8] & reg_we & ~wr_err;
2828: assign mp_region_cfg2_en2_wd = reg_wdata[0];
2829:
2830: assign mp_region_cfg2_rd_en2_we = addr_hit[8] & reg_we & ~wr_err;
2831: assign mp_region_cfg2_rd_en2_wd = reg_wdata[1];
2832:
2833: assign mp_region_cfg2_prog_en2_we = addr_hit[8] & reg_we & ~wr_err;
2834: assign mp_region_cfg2_prog_en2_wd = reg_wdata[2];
2835:
2836: assign mp_region_cfg2_erase_en2_we = addr_hit[8] & reg_we & ~wr_err;
2837: assign mp_region_cfg2_erase_en2_wd = reg_wdata[3];
2838:
2839: assign mp_region_cfg2_base2_we = addr_hit[8] & reg_we & ~wr_err;
2840: assign mp_region_cfg2_base2_wd = reg_wdata[12:4];
2841:
2842: assign mp_region_cfg2_size2_we = addr_hit[8] & reg_we & ~wr_err;
2843: assign mp_region_cfg2_size2_wd = reg_wdata[24:16];
2844:
2845: assign mp_region_cfg3_en3_we = addr_hit[9] & reg_we & ~wr_err;
2846: assign mp_region_cfg3_en3_wd = reg_wdata[0];
2847:
2848: assign mp_region_cfg3_rd_en3_we = addr_hit[9] & reg_we & ~wr_err;
2849: assign mp_region_cfg3_rd_en3_wd = reg_wdata[1];
2850:
2851: assign mp_region_cfg3_prog_en3_we = addr_hit[9] & reg_we & ~wr_err;
2852: assign mp_region_cfg3_prog_en3_wd = reg_wdata[2];
2853:
2854: assign mp_region_cfg3_erase_en3_we = addr_hit[9] & reg_we & ~wr_err;
2855: assign mp_region_cfg3_erase_en3_wd = reg_wdata[3];
2856:
2857: assign mp_region_cfg3_base3_we = addr_hit[9] & reg_we & ~wr_err;
2858: assign mp_region_cfg3_base3_wd = reg_wdata[12:4];
2859:
2860: assign mp_region_cfg3_size3_we = addr_hit[9] & reg_we & ~wr_err;
2861: assign mp_region_cfg3_size3_wd = reg_wdata[24:16];
2862:
2863: assign mp_region_cfg4_en4_we = addr_hit[10] & reg_we & ~wr_err;
2864: assign mp_region_cfg4_en4_wd = reg_wdata[0];
2865:
2866: assign mp_region_cfg4_rd_en4_we = addr_hit[10] & reg_we & ~wr_err;
2867: assign mp_region_cfg4_rd_en4_wd = reg_wdata[1];
2868:
2869: assign mp_region_cfg4_prog_en4_we = addr_hit[10] & reg_we & ~wr_err;
2870: assign mp_region_cfg4_prog_en4_wd = reg_wdata[2];
2871:
2872: assign mp_region_cfg4_erase_en4_we = addr_hit[10] & reg_we & ~wr_err;
2873: assign mp_region_cfg4_erase_en4_wd = reg_wdata[3];
2874:
2875: assign mp_region_cfg4_base4_we = addr_hit[10] & reg_we & ~wr_err;
2876: assign mp_region_cfg4_base4_wd = reg_wdata[12:4];
2877:
2878: assign mp_region_cfg4_size4_we = addr_hit[10] & reg_we & ~wr_err;
2879: assign mp_region_cfg4_size4_wd = reg_wdata[24:16];
2880:
2881: assign mp_region_cfg5_en5_we = addr_hit[11] & reg_we & ~wr_err;
2882: assign mp_region_cfg5_en5_wd = reg_wdata[0];
2883:
2884: assign mp_region_cfg5_rd_en5_we = addr_hit[11] & reg_we & ~wr_err;
2885: assign mp_region_cfg5_rd_en5_wd = reg_wdata[1];
2886:
2887: assign mp_region_cfg5_prog_en5_we = addr_hit[11] & reg_we & ~wr_err;
2888: assign mp_region_cfg5_prog_en5_wd = reg_wdata[2];
2889:
2890: assign mp_region_cfg5_erase_en5_we = addr_hit[11] & reg_we & ~wr_err;
2891: assign mp_region_cfg5_erase_en5_wd = reg_wdata[3];
2892:
2893: assign mp_region_cfg5_base5_we = addr_hit[11] & reg_we & ~wr_err;
2894: assign mp_region_cfg5_base5_wd = reg_wdata[12:4];
2895:
2896: assign mp_region_cfg5_size5_we = addr_hit[11] & reg_we & ~wr_err;
2897: assign mp_region_cfg5_size5_wd = reg_wdata[24:16];
2898:
2899: assign mp_region_cfg6_en6_we = addr_hit[12] & reg_we & ~wr_err;
2900: assign mp_region_cfg6_en6_wd = reg_wdata[0];
2901:
2902: assign mp_region_cfg6_rd_en6_we = addr_hit[12] & reg_we & ~wr_err;
2903: assign mp_region_cfg6_rd_en6_wd = reg_wdata[1];
2904:
2905: assign mp_region_cfg6_prog_en6_we = addr_hit[12] & reg_we & ~wr_err;
2906: assign mp_region_cfg6_prog_en6_wd = reg_wdata[2];
2907:
2908: assign mp_region_cfg6_erase_en6_we = addr_hit[12] & reg_we & ~wr_err;
2909: assign mp_region_cfg6_erase_en6_wd = reg_wdata[3];
2910:
2911: assign mp_region_cfg6_base6_we = addr_hit[12] & reg_we & ~wr_err;
2912: assign mp_region_cfg6_base6_wd = reg_wdata[12:4];
2913:
2914: assign mp_region_cfg6_size6_we = addr_hit[12] & reg_we & ~wr_err;
2915: assign mp_region_cfg6_size6_wd = reg_wdata[24:16];
2916:
2917: assign mp_region_cfg7_en7_we = addr_hit[13] & reg_we & ~wr_err;
2918: assign mp_region_cfg7_en7_wd = reg_wdata[0];
2919:
2920: assign mp_region_cfg7_rd_en7_we = addr_hit[13] & reg_we & ~wr_err;
2921: assign mp_region_cfg7_rd_en7_wd = reg_wdata[1];
2922:
2923: assign mp_region_cfg7_prog_en7_we = addr_hit[13] & reg_we & ~wr_err;
2924: assign mp_region_cfg7_prog_en7_wd = reg_wdata[2];
2925:
2926: assign mp_region_cfg7_erase_en7_we = addr_hit[13] & reg_we & ~wr_err;
2927: assign mp_region_cfg7_erase_en7_wd = reg_wdata[3];
2928:
2929: assign mp_region_cfg7_base7_we = addr_hit[13] & reg_we & ~wr_err;
2930: assign mp_region_cfg7_base7_wd = reg_wdata[12:4];
2931:
2932: assign mp_region_cfg7_size7_we = addr_hit[13] & reg_we & ~wr_err;
2933: assign mp_region_cfg7_size7_wd = reg_wdata[24:16];
2934:
2935: assign default_region_rd_en_we = addr_hit[14] & reg_we & ~wr_err;
2936: assign default_region_rd_en_wd = reg_wdata[0];
2937:
2938: assign default_region_prog_en_we = addr_hit[14] & reg_we & ~wr_err;
2939: assign default_region_prog_en_wd = reg_wdata[1];
2940:
2941: assign default_region_erase_en_we = addr_hit[14] & reg_we & ~wr_err;
2942: assign default_region_erase_en_wd = reg_wdata[2];
2943:
2944: assign bank_cfg_regwen_we = addr_hit[15] & reg_we & ~wr_err;
2945: assign bank_cfg_regwen_wd = reg_wdata[0];
2946:
2947: assign mp_bank_cfg_erase_en0_we = addr_hit[16] & reg_we & ~wr_err;
2948: assign mp_bank_cfg_erase_en0_wd = reg_wdata[0];
2949:
2950: assign mp_bank_cfg_erase_en1_we = addr_hit[16] & reg_we & ~wr_err;
2951: assign mp_bank_cfg_erase_en1_wd = reg_wdata[1];
2952:
2953: assign op_status_done_we = addr_hit[17] & reg_we & ~wr_err;
2954: assign op_status_done_wd = reg_wdata[0];
2955:
2956: assign op_status_err_we = addr_hit[17] & reg_we & ~wr_err;
2957: assign op_status_err_wd = reg_wdata[1];
2958:
2959: assign status_rd_full_re = addr_hit[18] && reg_re;
2960:
2961: assign status_rd_empty_re = addr_hit[18] && reg_re;
2962:
2963: assign status_prog_full_re = addr_hit[18] && reg_re;
2964:
2965: assign status_prog_empty_re = addr_hit[18] && reg_re;
2966:
2967: assign status_init_wip_re = addr_hit[18] && reg_re;
2968:
2969: assign status_error_page_re = addr_hit[18] && reg_re;
2970:
2971: assign status_error_bank_re = addr_hit[18] && reg_re;
2972:
2973: assign scratch_we = addr_hit[19] & reg_we & ~wr_err;
2974: assign scratch_wd = reg_wdata[31:0];
2975:
2976: assign fifo_lvl_prog_we = addr_hit[20] & reg_we & ~wr_err;
2977: assign fifo_lvl_prog_wd = reg_wdata[4:0];
2978:
2979: assign fifo_lvl_rd_we = addr_hit[20] & reg_we & ~wr_err;
2980: assign fifo_lvl_rd_wd = reg_wdata[12:8];
2981:
2982: // Read data return
2983: always_comb begin
2984: reg_rdata_next = '0;
2985: unique case (1'b1)
2986: addr_hit[0]: begin
2987: reg_rdata_next[0] = intr_state_prog_empty_qs;
2988: reg_rdata_next[1] = intr_state_prog_lvl_qs;
2989: reg_rdata_next[2] = intr_state_rd_full_qs;
2990: reg_rdata_next[3] = intr_state_rd_lvl_qs;
2991: reg_rdata_next[4] = intr_state_op_done_qs;
2992: reg_rdata_next[5] = intr_state_op_error_qs;
2993: end
2994:
2995: addr_hit[1]: begin
2996: reg_rdata_next[0] = intr_enable_prog_empty_qs;
2997: reg_rdata_next[1] = intr_enable_prog_lvl_qs;
2998: reg_rdata_next[2] = intr_enable_rd_full_qs;
2999: reg_rdata_next[3] = intr_enable_rd_lvl_qs;
3000: reg_rdata_next[4] = intr_enable_op_done_qs;
3001: reg_rdata_next[5] = intr_enable_op_error_qs;
3002: end
3003:
3004: addr_hit[2]: begin
3005: reg_rdata_next[0] = '0;
3006: reg_rdata_next[1] = '0;
3007: reg_rdata_next[2] = '0;
3008: reg_rdata_next[3] = '0;
3009: reg_rdata_next[4] = '0;
3010: reg_rdata_next[5] = '0;
3011: end
3012:
3013: addr_hit[3]: begin
3014: reg_rdata_next[0] = control_start_qs;
3015: reg_rdata_next[5:4] = control_op_qs;
3016: reg_rdata_next[6] = control_erase_sel_qs;
3017: reg_rdata_next[7] = control_fifo_rst_qs;
3018: reg_rdata_next[27:16] = control_num_qs;
3019: end
3020:
3021: addr_hit[4]: begin
3022: reg_rdata_next[31:0] = addr_qs;
3023: end
3024:
3025: addr_hit[5]: begin
3026: reg_rdata_next[0] = region_cfg_regwen_qs;
3027: end
3028:
3029: addr_hit[6]: begin
3030: reg_rdata_next[0] = mp_region_cfg0_en0_qs;
3031: reg_rdata_next[1] = mp_region_cfg0_rd_en0_qs;
3032: reg_rdata_next[2] = mp_region_cfg0_prog_en0_qs;
3033: reg_rdata_next[3] = mp_region_cfg0_erase_en0_qs;
3034: reg_rdata_next[12:4] = mp_region_cfg0_base0_qs;
3035: reg_rdata_next[24:16] = mp_region_cfg0_size0_qs;
3036: end
3037:
3038: addr_hit[7]: begin
3039: reg_rdata_next[0] = mp_region_cfg1_en1_qs;
3040: reg_rdata_next[1] = mp_region_cfg1_rd_en1_qs;
3041: reg_rdata_next[2] = mp_region_cfg1_prog_en1_qs;
3042: reg_rdata_next[3] = mp_region_cfg1_erase_en1_qs;
3043: reg_rdata_next[12:4] = mp_region_cfg1_base1_qs;
3044: reg_rdata_next[24:16] = mp_region_cfg1_size1_qs;
3045: end
3046:
3047: addr_hit[8]: begin
3048: reg_rdata_next[0] = mp_region_cfg2_en2_qs;
3049: reg_rdata_next[1] = mp_region_cfg2_rd_en2_qs;
3050: reg_rdata_next[2] = mp_region_cfg2_prog_en2_qs;
3051: reg_rdata_next[3] = mp_region_cfg2_erase_en2_qs;
3052: reg_rdata_next[12:4] = mp_region_cfg2_base2_qs;
3053: reg_rdata_next[24:16] = mp_region_cfg2_size2_qs;
3054: end
3055:
3056: addr_hit[9]: begin
3057: reg_rdata_next[0] = mp_region_cfg3_en3_qs;
3058: reg_rdata_next[1] = mp_region_cfg3_rd_en3_qs;
3059: reg_rdata_next[2] = mp_region_cfg3_prog_en3_qs;
3060: reg_rdata_next[3] = mp_region_cfg3_erase_en3_qs;
3061: reg_rdata_next[12:4] = mp_region_cfg3_base3_qs;
3062: reg_rdata_next[24:16] = mp_region_cfg3_size3_qs;
3063: end
3064:
3065: addr_hit[10]: begin
3066: reg_rdata_next[0] = mp_region_cfg4_en4_qs;
3067: reg_rdata_next[1] = mp_region_cfg4_rd_en4_qs;
3068: reg_rdata_next[2] = mp_region_cfg4_prog_en4_qs;
3069: reg_rdata_next[3] = mp_region_cfg4_erase_en4_qs;
3070: reg_rdata_next[12:4] = mp_region_cfg4_base4_qs;
3071: reg_rdata_next[24:16] = mp_region_cfg4_size4_qs;
3072: end
3073:
3074: addr_hit[11]: begin
3075: reg_rdata_next[0] = mp_region_cfg5_en5_qs;
3076: reg_rdata_next[1] = mp_region_cfg5_rd_en5_qs;
3077: reg_rdata_next[2] = mp_region_cfg5_prog_en5_qs;
3078: reg_rdata_next[3] = mp_region_cfg5_erase_en5_qs;
3079: reg_rdata_next[12:4] = mp_region_cfg5_base5_qs;
3080: reg_rdata_next[24:16] = mp_region_cfg5_size5_qs;
3081: end
3082:
3083: addr_hit[12]: begin
3084: reg_rdata_next[0] = mp_region_cfg6_en6_qs;
3085: reg_rdata_next[1] = mp_region_cfg6_rd_en6_qs;
3086: reg_rdata_next[2] = mp_region_cfg6_prog_en6_qs;
3087: reg_rdata_next[3] = mp_region_cfg6_erase_en6_qs;
3088: reg_rdata_next[12:4] = mp_region_cfg6_base6_qs;
3089: reg_rdata_next[24:16] = mp_region_cfg6_size6_qs;
3090: end
3091:
3092: addr_hit[13]: begin
3093: reg_rdata_next[0] = mp_region_cfg7_en7_qs;
3094: reg_rdata_next[1] = mp_region_cfg7_rd_en7_qs;
3095: reg_rdata_next[2] = mp_region_cfg7_prog_en7_qs;
3096: reg_rdata_next[3] = mp_region_cfg7_erase_en7_qs;
3097: reg_rdata_next[12:4] = mp_region_cfg7_base7_qs;
3098: reg_rdata_next[24:16] = mp_region_cfg7_size7_qs;
3099: end
3100:
3101: addr_hit[14]: begin
3102: reg_rdata_next[0] = default_region_rd_en_qs;
3103: reg_rdata_next[1] = default_region_prog_en_qs;
3104: reg_rdata_next[2] = default_region_erase_en_qs;
3105: end
3106:
3107: addr_hit[15]: begin
3108: reg_rdata_next[0] = bank_cfg_regwen_qs;
3109: end
3110:
3111: addr_hit[16]: begin
3112: reg_rdata_next[0] = mp_bank_cfg_erase_en0_qs;
3113: reg_rdata_next[1] = mp_bank_cfg_erase_en1_qs;
3114: end
3115:
3116: addr_hit[17]: begin
3117: reg_rdata_next[0] = op_status_done_qs;
3118: reg_rdata_next[1] = op_status_err_qs;
3119: end
3120:
3121: addr_hit[18]: begin
3122: reg_rdata_next[0] = status_rd_full_qs;
3123: reg_rdata_next[1] = status_rd_empty_qs;
3124: reg_rdata_next[2] = status_prog_full_qs;
3125: reg_rdata_next[3] = status_prog_empty_qs;
3126: reg_rdata_next[4] = status_init_wip_qs;
3127: reg_rdata_next[16:8] = status_error_page_qs;
3128: reg_rdata_next[17] = status_error_bank_qs;
3129: end
3130:
3131: addr_hit[19]: begin
3132: reg_rdata_next[31:0] = scratch_qs;
3133: end
3134:
3135: addr_hit[20]: begin
3136: reg_rdata_next[4:0] = fifo_lvl_prog_qs;
3137: reg_rdata_next[12:8] = fifo_lvl_rd_qs;
3138: end
3139:
3140: default: begin
3141: reg_rdata_next = '1;
3142: end
3143: endcase
3144: end
3145:
3146: // Assertions for Register Interface
3147: `ASSERT_PULSE(wePulse, reg_we)
3148: `ASSERT_PULSE(rePulse, reg_re)
3149:
3150: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
3151:
3152: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
3153:
3154: // this is formulated as an assumption such that the FPV testbenches do disprove this
3155: // property by mistake
3156: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
3157:
3158: endmodule
3159: