../src/lowrisc_ip_uart_0.1/rtl/uart.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Description: UART top level wrapper file
6:
7: `include "prim_assert.sv"
8:
9: module uart (
10: input clk_i,
11: input rst_ni,
12:
13: // Bus Interface
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16:
17: // Generic IO
18: input cio_rx_i,
19: output logic cio_tx_o,
20: output logic cio_tx_en_o,
21:
22: // Interrupts
23: output logic intr_tx_watermark_o ,
24: output logic intr_rx_watermark_o ,
25: output logic intr_tx_empty_o ,
26: output logic intr_rx_overflow_o ,
27: output logic intr_rx_frame_err_o ,
28: output logic intr_rx_break_err_o ,
29: output logic intr_rx_timeout_o ,
30: output logic intr_rx_parity_err_o
31: );
32:
33: import uart_reg_pkg::*;
34:
35: uart_reg2hw_t reg2hw;
36: uart_hw2reg_t hw2reg;
37:
38: uart_reg_top u_reg (
39: .clk_i,
40: .rst_ni,
41: .tl_i,
42: .tl_o,
43: .reg2hw,
44: .hw2reg,
45:
46: .devmode_i (1'b1)
47: );
48:
49: uart_core uart_core (
50: .clk_i,
51: .rst_ni,
52: .reg2hw,
53: .hw2reg,
54:
55: .rx (cio_rx_i ),
56: .tx (cio_tx_o ),
57:
58: .intr_tx_watermark_o,
59: .intr_rx_watermark_o,
60: .intr_tx_empty_o,
61: .intr_rx_overflow_o,
62: .intr_rx_frame_err_o,
63: .intr_rx_break_err_o,
64: .intr_rx_timeout_o,
65: .intr_rx_parity_err_o
66: );
67:
68: // always enable the driving out of TX
69: assign cio_tx_en_o = 1'b1;
70:
71: // Assert Known for outputs
72: `ASSERT_KNOWN(txenKnown, cio_tx_en_o)
73: `ASSERT_KNOWN(txKnown, cio_tx_o, clk_i, !rst_ni || !cio_tx_en_o)
74:
75: // Assert Known for interrupts
76: `ASSERT_KNOWN(txWatermarkKnown, intr_tx_watermark_o)
77: `ASSERT_KNOWN(rxWatermarkKnown, intr_rx_watermark_o)
78: `ASSERT_KNOWN(txEmptyKnown, intr_tx_empty_o)
79: `ASSERT_KNOWN(rxOverflowKnown, intr_rx_overflow_o)
80: `ASSERT_KNOWN(rxFrameErrKnown, intr_rx_frame_err_o)
81: `ASSERT_KNOWN(rxBreakErrKnown, intr_rx_break_err_o)
82: `ASSERT_KNOWN(rxTimeoutKnown, intr_rx_timeout_o)
83: `ASSERT_KNOWN(rxParityErrKnown, intr_rx_parity_err_o)
84:
85: endmodule
86: