../src/lowrisc_prim_xilinx_pad_wrapper_0/rtl/prim_xilinx_pad_wrapper.sv Cov: 80%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Bidirectional IO buffer for Xilinx FPGAs. Implements inversion and
   6: // virtual open drain feature.
   7: 
   8: 
   9: module prim_xilinx_pad_wrapper #(
  10:   parameter int unsigned AttrDw = 2
  11: ) (
  12:   inout wire         inout_io, // bidirectional pad
  13:   output logic       in_o,     // input data
  14:   input              out_i,    // output data
  15:   input              oe_i,     // output enable
  16:   // additional attributes
  17:   input [AttrDw-1:0] attr_i
  18: );
  19: 
  20:   // get pad attributes
  21:   logic od, inv;
  22:   assign {od, inv} = attr_i[1:0];
  23: 
  24:   // input inversion
  25:   logic in;
  26:   assign in_o     = inv ^ in;
  27: 
  28:   // virtual open drain emulation
  29:   logic oe_n, out;
  30:   assign out      = out_i ^ inv;
  31:   // oe_n = 0: enable driver
  32:   // oe_n = 1: disable driver
  33:   assign oe_n     = ~oe_i | (out & od);
  34: 
  35:   // driver
  36:   IOBUF i_iobuf (
  37:     .T(oe_n),
  38:     .I(out),
  39:     .O(in),
  40:     .IO(inout_io)
  41:   );
  42: 
  43: endmodule : prim_xilinx_pad_wrapper
  44: