hw/ip/prim/abstract/prim_ram_2p.sv Cov: 67.3%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4:
5: // TODO: This module is a hard-coded stopgap to select an implementation of an
6: // "abstract module". This module is to be replaced by generated code.
7:
8:
9: `ifndef PRIM_DEFAULT_IMPL
10: `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
11: `endif
12:
13: module prim_ram_2p #(
14: parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL,
15:
16: parameter int Width = 32, // bit
17: parameter int Depth = 128,
18:
19: localparam int Aw = $clog2(Depth) // derived parameter
20: ) (
21: input clk_a_i,
22: input clk_b_i,
23:
24: input a_req_i,
25: input a_write_i,
26: input [Aw-1:0] a_addr_i,
27: input [Width-1:0] a_wdata_i,
28: output logic [Width-1:0] a_rdata_o,
29:
30: input b_req_i,
31: input b_write_i,
32: input [Aw-1:0] b_addr_i,
33: input [Width-1:0] b_wdata_i,
34: output logic [Width-1:0] b_rdata_o
35: );
36:
37: import prim_pkg::*;
38:
39: if (Impl == ImplGeneric) begin : gen_mem_generic
40: prim_generic_ram_2p #(
41: .Width(Width),
42: .Depth(Depth)
43: ) u_impl_generic (
44: .clk_a_i,
45: .clk_b_i,
46: .a_req_i,
47: .a_write_i,
48: .a_addr_i,
49: .a_wdata_i,
50: .a_rdata_o,
51: .b_req_i,
52: .b_write_i,
53: .b_addr_i,
54: .b_wdata_i,
55: .b_rdata_o
56: );
57: end else if (Impl == ImplXilinx) begin : gen_mem_xilinx
58: prim_xilinx_ram_2p #(
59: .Width(Width),
60: .Depth(Depth)
61: ) u_impl_xilinx (
62: .clk_a_i,
63: .clk_b_i,
64: .a_req_i,
65: .a_write_i,
66: .a_addr_i,
67: .a_wdata_i,
68: .a_rdata_o,
69: .b_req_i,
70: .b_write_i,
71: .b_addr_i,
72: .b_wdata_i,
73: .b_rdata_o
74: );
75: end else begin : gen_failure
76: // TODO: Find code that works across tools and causes a compile failure
77: end
78:
79: endmodule
80: