../src/lowrisc_prim_rom_adv_0.1/rtl/prim_rom_adv.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // ROM wrapper with rvalid register
6:
7: `include "prim_assert.sv"
8:
9: module prim_rom_adv #(
10: // Parameters passed on the the ROM primitive.
11: parameter int Width = 32,
12: parameter int Depth = 2048, // 8kB default
13: parameter MemInitFile = "", // VMEM file to initialize the memory with
14:
15: parameter int CfgW = 8, // WTC, RTC, etc
16:
17: localparam int Aw = $clog2(Depth)
18: ) (
19: input logic clk_i,
20: input logic rst_ni,
21: input logic req_i,
22: input logic [Aw-1:0] addr_i,
23: output logic rvalid_o,
24: output logic [Width-1:0] rdata_o,
25:
26: input [CfgW-1:0] cfg_i
27: );
28:
29: // We will eventually use cfg_i for RTC/WTC or other memory parameters.
30: logic [CfgW-1:0] unused_cfg;
31: assign unused_cfg = cfg_i;
32:
33: prim_rom #(
34: .Width(Width),
35: .Depth(Depth),
36: .MemInitFile(MemInitFile)
37: ) u_prim_rom (
38: .clk_i,
39: .req_i,
40: .addr_i,
41: .rdata_o
42: );
43:
44: always_ff @(posedge clk_i or negedge rst_ni) begin
45: if (!rst_ni) begin
46: rvalid_o <= 1'b0;
47: end else begin
48: rvalid_o <= req_i;
49: end
50: end
51:
52: ////////////////
53: // ASSERTIONS //
54: ////////////////
55:
56: // Control Signals should never be X
57: `ASSERT(noXOnCsI, !$isunknown(req_i), clk_i, '0)
58: endmodule : prim_rom_adv
59: