../src/lowrisc_ip_spi_device_0.1/rtl/spi_device_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module spi_device_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16:
17: // Output port for window
18: output tlul_pkg::tl_h2d_t tl_win_o [1],
19: input tlul_pkg::tl_d2h_t tl_win_i [1],
20:
21: // To HW
22: output spi_device_reg_pkg::spi_device_reg2hw_t reg2hw, // Write
23: input spi_device_reg_pkg::spi_device_hw2reg_t hw2reg, // Read
24:
25: // Config
26: input devmode_i // If 1, explicit error return for unmapped register access
27: );
28:
29: import spi_device_reg_pkg::* ;
30:
31: localparam int AW = 12;
32: localparam int DW = 32;
33: localparam int DBW = DW/8; // Byte Width
34:
35: // register signals
36: logic reg_we;
37: logic reg_re;
38: logic [AW-1:0] reg_addr;
39: logic [DW-1:0] reg_wdata;
40: logic [DBW-1:0] reg_be;
41: logic [DW-1:0] reg_rdata;
42: logic reg_error;
43:
44: logic addrmiss, wr_err;
45:
46: logic [DW-1:0] reg_rdata_next;
47:
48: tlul_pkg::tl_h2d_t tl_reg_h2d;
49: tlul_pkg::tl_d2h_t tl_reg_d2h;
50:
51: tlul_pkg::tl_h2d_t tl_socket_h2d [2];
52: tlul_pkg::tl_d2h_t tl_socket_d2h [2];
53:
54: logic [1:0] reg_steer;
55:
56: // socket_1n connection
57: assign tl_reg_h2d = tl_socket_h2d[1];
58: assign tl_socket_d2h[1] = tl_reg_d2h;
59:
60: assign tl_win_o[0] = tl_socket_h2d[0];
61: assign tl_socket_d2h[0] = tl_win_i[0];
62:
63: // Create Socket_1n
64: tlul_socket_1n #(
65: .N (2),
66: .HReqPass (1'b1),
67: .HRspPass (1'b1),
68: .DReqPass ({2{1'b1}}),
69: .DRspPass ({2{1'b1}}),
70: .HReqDepth (4'h0),
71: .HRspDepth (4'h0),
72: .DReqDepth ({2{4'h0}}),
73: .DRspDepth ({2{4'h0}})
74: ) u_socket (
75: .clk_i,
76: .rst_ni,
77: .tl_h_i (tl_i),
78: .tl_h_o (tl_o),
79: .tl_d_o (tl_socket_h2d),
80: .tl_d_i (tl_socket_d2h),
81: .dev_select (reg_steer)
82: );
83:
84: // Create steering logic
85: always_comb begin
86: reg_steer = 1; // Default set to register
87:
88: // TODO: Can below codes be unique case () inside ?
89: if (tl_i.a_address[AW-1:0] >= 2048) begin
90: // Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
91: reg_steer = 0;
92: end
93: end
94:
95: tlul_adapter_reg #(
96: .RegAw(AW),
97: .RegDw(DW)
98: ) u_reg_if (
99: .clk_i,
100: .rst_ni,
101:
102: .tl_i (tl_reg_h2d),
103: .tl_o (tl_reg_d2h),
104:
105: .we_o (reg_we),
106: .re_o (reg_re),
107: .addr_o (reg_addr),
108: .wdata_o (reg_wdata),
109: .be_o (reg_be),
110: .rdata_i (reg_rdata),
111: .error_i (reg_error)
112: );
113:
114: assign reg_rdata = reg_rdata_next ;
115: assign reg_error = (devmode_i & addrmiss) | wr_err ;
116:
117: // Define SW related signals
118: // Format: __{wd|we|qs}
119: // or _{wd|we|qs} if field == 1 or 0
120: logic intr_state_rxf_qs;
121: logic intr_state_rxf_wd;
122: logic intr_state_rxf_we;
123: logic intr_state_rxlvl_qs;
124: logic intr_state_rxlvl_wd;
125: logic intr_state_rxlvl_we;
126: logic intr_state_txlvl_qs;
127: logic intr_state_txlvl_wd;
128: logic intr_state_txlvl_we;
129: logic intr_state_rxerr_qs;
130: logic intr_state_rxerr_wd;
131: logic intr_state_rxerr_we;
132: logic intr_state_rxoverflow_qs;
133: logic intr_state_rxoverflow_wd;
134: logic intr_state_rxoverflow_we;
135: logic intr_state_txunderflow_qs;
136: logic intr_state_txunderflow_wd;
137: logic intr_state_txunderflow_we;
138: logic intr_enable_rxf_qs;
139: logic intr_enable_rxf_wd;
140: logic intr_enable_rxf_we;
141: logic intr_enable_rxlvl_qs;
142: logic intr_enable_rxlvl_wd;
143: logic intr_enable_rxlvl_we;
144: logic intr_enable_txlvl_qs;
145: logic intr_enable_txlvl_wd;
146: logic intr_enable_txlvl_we;
147: logic intr_enable_rxerr_qs;
148: logic intr_enable_rxerr_wd;
149: logic intr_enable_rxerr_we;
150: logic intr_enable_rxoverflow_qs;
151: logic intr_enable_rxoverflow_wd;
152: logic intr_enable_rxoverflow_we;
153: logic intr_enable_txunderflow_qs;
154: logic intr_enable_txunderflow_wd;
155: logic intr_enable_txunderflow_we;
156: logic intr_test_rxf_wd;
157: logic intr_test_rxf_we;
158: logic intr_test_rxlvl_wd;
159: logic intr_test_rxlvl_we;
160: logic intr_test_txlvl_wd;
161: logic intr_test_txlvl_we;
162: logic intr_test_rxerr_wd;
163: logic intr_test_rxerr_we;
164: logic intr_test_rxoverflow_wd;
165: logic intr_test_rxoverflow_we;
166: logic intr_test_txunderflow_wd;
167: logic intr_test_txunderflow_we;
168: logic control_abort_qs;
169: logic control_abort_wd;
170: logic control_abort_we;
171: logic [1:0] control_mode_qs;
172: logic [1:0] control_mode_wd;
173: logic control_mode_we;
174: logic control_rst_txfifo_qs;
175: logic control_rst_txfifo_wd;
176: logic control_rst_txfifo_we;
177: logic control_rst_rxfifo_qs;
178: logic control_rst_rxfifo_wd;
179: logic control_rst_rxfifo_we;
180: logic cfg_cpol_qs;
181: logic cfg_cpol_wd;
182: logic cfg_cpol_we;
183: logic cfg_cpha_qs;
184: logic cfg_cpha_wd;
185: logic cfg_cpha_we;
186: logic cfg_tx_order_qs;
187: logic cfg_tx_order_wd;
188: logic cfg_tx_order_we;
189: logic cfg_rx_order_qs;
190: logic cfg_rx_order_wd;
191: logic cfg_rx_order_we;
192: logic [7:0] cfg_timer_v_qs;
193: logic [7:0] cfg_timer_v_wd;
194: logic cfg_timer_v_we;
195: logic [15:0] fifo_level_rxlvl_qs;
196: logic [15:0] fifo_level_rxlvl_wd;
197: logic fifo_level_rxlvl_we;
198: logic [15:0] fifo_level_txlvl_qs;
199: logic [15:0] fifo_level_txlvl_wd;
200: logic fifo_level_txlvl_we;
201: logic [7:0] async_fifo_level_rxlvl_qs;
202: logic async_fifo_level_rxlvl_re;
203: logic [7:0] async_fifo_level_txlvl_qs;
204: logic async_fifo_level_txlvl_re;
205: logic status_rxf_full_qs;
206: logic status_rxf_full_re;
207: logic status_rxf_empty_qs;
208: logic status_rxf_empty_re;
209: logic status_txf_full_qs;
210: logic status_txf_full_re;
211: logic status_txf_empty_qs;
212: logic status_txf_empty_re;
213: logic status_abort_done_qs;
214: logic status_abort_done_re;
215: logic status_csb_qs;
216: logic status_csb_re;
217: logic [15:0] rxf_ptr_rptr_qs;
218: logic [15:0] rxf_ptr_rptr_wd;
219: logic rxf_ptr_rptr_we;
220: logic [15:0] rxf_ptr_wptr_qs;
221: logic [15:0] txf_ptr_rptr_qs;
222: logic [15:0] txf_ptr_wptr_qs;
223: logic [15:0] txf_ptr_wptr_wd;
224: logic txf_ptr_wptr_we;
225: logic [15:0] rxf_addr_base_qs;
226: logic [15:0] rxf_addr_base_wd;
227: logic rxf_addr_base_we;
228: logic [15:0] rxf_addr_limit_qs;
229: logic [15:0] rxf_addr_limit_wd;
230: logic rxf_addr_limit_we;
231: logic [15:0] txf_addr_base_qs;
232: logic [15:0] txf_addr_base_wd;
233: logic txf_addr_base_we;
234: logic [15:0] txf_addr_limit_qs;
235: logic [15:0] txf_addr_limit_wd;
236: logic txf_addr_limit_we;
237:
238: // Register instances
239: // R[intr_state]: V(False)
240:
241: // F[rxf]: 0:0
242: prim_subreg #(
243: .DW (1),
244: .SWACCESS("W1C"),
245: .RESVAL (1'h0)
246: ) u_intr_state_rxf (
247: .clk_i (clk_i ),
248: .rst_ni (rst_ni ),
249:
250: // from register interface
251: .we (intr_state_rxf_we),
252: .wd (intr_state_rxf_wd),
253:
254: // from internal hardware
255: .de (hw2reg.intr_state.rxf.de),
256: .d (hw2reg.intr_state.rxf.d ),
257:
258: // to internal hardware
259: .qe (),
260: .q (reg2hw.intr_state.rxf.q ),
261:
262: // to register interface (read)
263: .qs (intr_state_rxf_qs)
264: );
265:
266:
267: // F[rxlvl]: 1:1
268: prim_subreg #(
269: .DW (1),
270: .SWACCESS("W1C"),
271: .RESVAL (1'h0)
272: ) u_intr_state_rxlvl (
273: .clk_i (clk_i ),
274: .rst_ni (rst_ni ),
275:
276: // from register interface
277: .we (intr_state_rxlvl_we),
278: .wd (intr_state_rxlvl_wd),
279:
280: // from internal hardware
281: .de (hw2reg.intr_state.rxlvl.de),
282: .d (hw2reg.intr_state.rxlvl.d ),
283:
284: // to internal hardware
285: .qe (),
286: .q (reg2hw.intr_state.rxlvl.q ),
287:
288: // to register interface (read)
289: .qs (intr_state_rxlvl_qs)
290: );
291:
292:
293: // F[txlvl]: 2:2
294: prim_subreg #(
295: .DW (1),
296: .SWACCESS("W1C"),
297: .RESVAL (1'h0)
298: ) u_intr_state_txlvl (
299: .clk_i (clk_i ),
300: .rst_ni (rst_ni ),
301:
302: // from register interface
303: .we (intr_state_txlvl_we),
304: .wd (intr_state_txlvl_wd),
305:
306: // from internal hardware
307: .de (hw2reg.intr_state.txlvl.de),
308: .d (hw2reg.intr_state.txlvl.d ),
309:
310: // to internal hardware
311: .qe (),
312: .q (reg2hw.intr_state.txlvl.q ),
313:
314: // to register interface (read)
315: .qs (intr_state_txlvl_qs)
316: );
317:
318:
319: // F[rxerr]: 3:3
320: prim_subreg #(
321: .DW (1),
322: .SWACCESS("W1C"),
323: .RESVAL (1'h0)
324: ) u_intr_state_rxerr (
325: .clk_i (clk_i ),
326: .rst_ni (rst_ni ),
327:
328: // from register interface
329: .we (intr_state_rxerr_we),
330: .wd (intr_state_rxerr_wd),
331:
332: // from internal hardware
333: .de (hw2reg.intr_state.rxerr.de),
334: .d (hw2reg.intr_state.rxerr.d ),
335:
336: // to internal hardware
337: .qe (),
338: .q (reg2hw.intr_state.rxerr.q ),
339:
340: // to register interface (read)
341: .qs (intr_state_rxerr_qs)
342: );
343:
344:
345: // F[rxoverflow]: 4:4
346: prim_subreg #(
347: .DW (1),
348: .SWACCESS("W1C"),
349: .RESVAL (1'h0)
350: ) u_intr_state_rxoverflow (
351: .clk_i (clk_i ),
352: .rst_ni (rst_ni ),
353:
354: // from register interface
355: .we (intr_state_rxoverflow_we),
356: .wd (intr_state_rxoverflow_wd),
357:
358: // from internal hardware
359: .de (hw2reg.intr_state.rxoverflow.de),
360: .d (hw2reg.intr_state.rxoverflow.d ),
361:
362: // to internal hardware
363: .qe (),
364: .q (reg2hw.intr_state.rxoverflow.q ),
365:
366: // to register interface (read)
367: .qs (intr_state_rxoverflow_qs)
368: );
369:
370:
371: // F[txunderflow]: 5:5
372: prim_subreg #(
373: .DW (1),
374: .SWACCESS("W1C"),
375: .RESVAL (1'h0)
376: ) u_intr_state_txunderflow (
377: .clk_i (clk_i ),
378: .rst_ni (rst_ni ),
379:
380: // from register interface
381: .we (intr_state_txunderflow_we),
382: .wd (intr_state_txunderflow_wd),
383:
384: // from internal hardware
385: .de (hw2reg.intr_state.txunderflow.de),
386: .d (hw2reg.intr_state.txunderflow.d ),
387:
388: // to internal hardware
389: .qe (),
390: .q (reg2hw.intr_state.txunderflow.q ),
391:
392: // to register interface (read)
393: .qs (intr_state_txunderflow_qs)
394: );
395:
396:
397: // R[intr_enable]: V(False)
398:
399: // F[rxf]: 0:0
400: prim_subreg #(
401: .DW (1),
402: .SWACCESS("RW"),
403: .RESVAL (1'h0)
404: ) u_intr_enable_rxf (
405: .clk_i (clk_i ),
406: .rst_ni (rst_ni ),
407:
408: // from register interface
409: .we (intr_enable_rxf_we),
410: .wd (intr_enable_rxf_wd),
411:
412: // from internal hardware
413: .de (1'b0),
414: .d ('0 ),
415:
416: // to internal hardware
417: .qe (),
418: .q (reg2hw.intr_enable.rxf.q ),
419:
420: // to register interface (read)
421: .qs (intr_enable_rxf_qs)
422: );
423:
424:
425: // F[rxlvl]: 1:1
426: prim_subreg #(
427: .DW (1),
428: .SWACCESS("RW"),
429: .RESVAL (1'h0)
430: ) u_intr_enable_rxlvl (
431: .clk_i (clk_i ),
432: .rst_ni (rst_ni ),
433:
434: // from register interface
435: .we (intr_enable_rxlvl_we),
436: .wd (intr_enable_rxlvl_wd),
437:
438: // from internal hardware
439: .de (1'b0),
440: .d ('0 ),
441:
442: // to internal hardware
443: .qe (),
444: .q (reg2hw.intr_enable.rxlvl.q ),
445:
446: // to register interface (read)
447: .qs (intr_enable_rxlvl_qs)
448: );
449:
450:
451: // F[txlvl]: 2:2
452: prim_subreg #(
453: .DW (1),
454: .SWACCESS("RW"),
455: .RESVAL (1'h0)
456: ) u_intr_enable_txlvl (
457: .clk_i (clk_i ),
458: .rst_ni (rst_ni ),
459:
460: // from register interface
461: .we (intr_enable_txlvl_we),
462: .wd (intr_enable_txlvl_wd),
463:
464: // from internal hardware
465: .de (1'b0),
466: .d ('0 ),
467:
468: // to internal hardware
469: .qe (),
470: .q (reg2hw.intr_enable.txlvl.q ),
471:
472: // to register interface (read)
473: .qs (intr_enable_txlvl_qs)
474: );
475:
476:
477: // F[rxerr]: 3:3
478: prim_subreg #(
479: .DW (1),
480: .SWACCESS("RW"),
481: .RESVAL (1'h0)
482: ) u_intr_enable_rxerr (
483: .clk_i (clk_i ),
484: .rst_ni (rst_ni ),
485:
486: // from register interface
487: .we (intr_enable_rxerr_we),
488: .wd (intr_enable_rxerr_wd),
489:
490: // from internal hardware
491: .de (1'b0),
492: .d ('0 ),
493:
494: // to internal hardware
495: .qe (),
496: .q (reg2hw.intr_enable.rxerr.q ),
497:
498: // to register interface (read)
499: .qs (intr_enable_rxerr_qs)
500: );
501:
502:
503: // F[rxoverflow]: 4:4
504: prim_subreg #(
505: .DW (1),
506: .SWACCESS("RW"),
507: .RESVAL (1'h0)
508: ) u_intr_enable_rxoverflow (
509: .clk_i (clk_i ),
510: .rst_ni (rst_ni ),
511:
512: // from register interface
513: .we (intr_enable_rxoverflow_we),
514: .wd (intr_enable_rxoverflow_wd),
515:
516: // from internal hardware
517: .de (1'b0),
518: .d ('0 ),
519:
520: // to internal hardware
521: .qe (),
522: .q (reg2hw.intr_enable.rxoverflow.q ),
523:
524: // to register interface (read)
525: .qs (intr_enable_rxoverflow_qs)
526: );
527:
528:
529: // F[txunderflow]: 5:5
530: prim_subreg #(
531: .DW (1),
532: .SWACCESS("RW"),
533: .RESVAL (1'h0)
534: ) u_intr_enable_txunderflow (
535: .clk_i (clk_i ),
536: .rst_ni (rst_ni ),
537:
538: // from register interface
539: .we (intr_enable_txunderflow_we),
540: .wd (intr_enable_txunderflow_wd),
541:
542: // from internal hardware
543: .de (1'b0),
544: .d ('0 ),
545:
546: // to internal hardware
547: .qe (),
548: .q (reg2hw.intr_enable.txunderflow.q ),
549:
550: // to register interface (read)
551: .qs (intr_enable_txunderflow_qs)
552: );
553:
554:
555: // R[intr_test]: V(True)
556:
557: // F[rxf]: 0:0
558: prim_subreg_ext #(
559: .DW (1)
560: ) u_intr_test_rxf (
561: .re (1'b0),
562: .we (intr_test_rxf_we),
563: .wd (intr_test_rxf_wd),
564: .d ('0),
565: .qre (),
566: .qe (reg2hw.intr_test.rxf.qe),
567: .q (reg2hw.intr_test.rxf.q ),
568: .qs ()
569: );
570:
571:
572: // F[rxlvl]: 1:1
573: prim_subreg_ext #(
574: .DW (1)
575: ) u_intr_test_rxlvl (
576: .re (1'b0),
577: .we (intr_test_rxlvl_we),
578: .wd (intr_test_rxlvl_wd),
579: .d ('0),
580: .qre (),
581: .qe (reg2hw.intr_test.rxlvl.qe),
582: .q (reg2hw.intr_test.rxlvl.q ),
583: .qs ()
584: );
585:
586:
587: // F[txlvl]: 2:2
588: prim_subreg_ext #(
589: .DW (1)
590: ) u_intr_test_txlvl (
591: .re (1'b0),
592: .we (intr_test_txlvl_we),
593: .wd (intr_test_txlvl_wd),
594: .d ('0),
595: .qre (),
596: .qe (reg2hw.intr_test.txlvl.qe),
597: .q (reg2hw.intr_test.txlvl.q ),
598: .qs ()
599: );
600:
601:
602: // F[rxerr]: 3:3
603: prim_subreg_ext #(
604: .DW (1)
605: ) u_intr_test_rxerr (
606: .re (1'b0),
607: .we (intr_test_rxerr_we),
608: .wd (intr_test_rxerr_wd),
609: .d ('0),
610: .qre (),
611: .qe (reg2hw.intr_test.rxerr.qe),
612: .q (reg2hw.intr_test.rxerr.q ),
613: .qs ()
614: );
615:
616:
617: // F[rxoverflow]: 4:4
618: prim_subreg_ext #(
619: .DW (1)
620: ) u_intr_test_rxoverflow (
621: .re (1'b0),
622: .we (intr_test_rxoverflow_we),
623: .wd (intr_test_rxoverflow_wd),
624: .d ('0),
625: .qre (),
626: .qe (reg2hw.intr_test.rxoverflow.qe),
627: .q (reg2hw.intr_test.rxoverflow.q ),
628: .qs ()
629: );
630:
631:
632: // F[txunderflow]: 5:5
633: prim_subreg_ext #(
634: .DW (1)
635: ) u_intr_test_txunderflow (
636: .re (1'b0),
637: .we (intr_test_txunderflow_we),
638: .wd (intr_test_txunderflow_wd),
639: .d ('0),
640: .qre (),
641: .qe (reg2hw.intr_test.txunderflow.qe),
642: .q (reg2hw.intr_test.txunderflow.q ),
643: .qs ()
644: );
645:
646:
647: // R[control]: V(False)
648:
649: // F[abort]: 0:0
650: prim_subreg #(
651: .DW (1),
652: .SWACCESS("RW"),
653: .RESVAL (1'h0)
654: ) u_control_abort (
655: .clk_i (clk_i ),
656: .rst_ni (rst_ni ),
657:
658: // from register interface
659: .we (control_abort_we),
660: .wd (control_abort_wd),
661:
662: // from internal hardware
663: .de (1'b0),
664: .d ('0 ),
665:
666: // to internal hardware
667: .qe (),
668: .q (reg2hw.control.abort.q ),
669:
670: // to register interface (read)
671: .qs (control_abort_qs)
672: );
673:
674:
675: // F[mode]: 5:4
676: prim_subreg #(
677: .DW (2),
678: .SWACCESS("RW"),
679: .RESVAL (2'h0)
680: ) u_control_mode (
681: .clk_i (clk_i ),
682: .rst_ni (rst_ni ),
683:
684: // from register interface
685: .we (control_mode_we),
686: .wd (control_mode_wd),
687:
688: // from internal hardware
689: .de (1'b0),
690: .d ('0 ),
691:
692: // to internal hardware
693: .qe (),
694: .q (reg2hw.control.mode.q ),
695:
696: // to register interface (read)
697: .qs (control_mode_qs)
698: );
699:
700:
701: // F[rst_txfifo]: 16:16
702: prim_subreg #(
703: .DW (1),
704: .SWACCESS("RW"),
705: .RESVAL (1'h0)
706: ) u_control_rst_txfifo (
707: .clk_i (clk_i ),
708: .rst_ni (rst_ni ),
709:
710: // from register interface
711: .we (control_rst_txfifo_we),
712: .wd (control_rst_txfifo_wd),
713:
714: // from internal hardware
715: .de (1'b0),
716: .d ('0 ),
717:
718: // to internal hardware
719: .qe (),
720: .q (reg2hw.control.rst_txfifo.q ),
721:
722: // to register interface (read)
723: .qs (control_rst_txfifo_qs)
724: );
725:
726:
727: // F[rst_rxfifo]: 17:17
728: prim_subreg #(
729: .DW (1),
730: .SWACCESS("RW"),
731: .RESVAL (1'h0)
732: ) u_control_rst_rxfifo (
733: .clk_i (clk_i ),
734: .rst_ni (rst_ni ),
735:
736: // from register interface
737: .we (control_rst_rxfifo_we),
738: .wd (control_rst_rxfifo_wd),
739:
740: // from internal hardware
741: .de (1'b0),
742: .d ('0 ),
743:
744: // to internal hardware
745: .qe (),
746: .q (reg2hw.control.rst_rxfifo.q ),
747:
748: // to register interface (read)
749: .qs (control_rst_rxfifo_qs)
750: );
751:
752:
753: // R[cfg]: V(False)
754:
755: // F[cpol]: 0:0
756: prim_subreg #(
757: .DW (1),
758: .SWACCESS("RW"),
759: .RESVAL (1'h0)
760: ) u_cfg_cpol (
761: .clk_i (clk_i ),
762: .rst_ni (rst_ni ),
763:
764: // from register interface
765: .we (cfg_cpol_we),
766: .wd (cfg_cpol_wd),
767:
768: // from internal hardware
769: .de (1'b0),
770: .d ('0 ),
771:
772: // to internal hardware
773: .qe (),
774: .q (reg2hw.cfg.cpol.q ),
775:
776: // to register interface (read)
777: .qs (cfg_cpol_qs)
778: );
779:
780:
781: // F[cpha]: 1:1
782: prim_subreg #(
783: .DW (1),
784: .SWACCESS("RW"),
785: .RESVAL (1'h0)
786: ) u_cfg_cpha (
787: .clk_i (clk_i ),
788: .rst_ni (rst_ni ),
789:
790: // from register interface
791: .we (cfg_cpha_we),
792: .wd (cfg_cpha_wd),
793:
794: // from internal hardware
795: .de (1'b0),
796: .d ('0 ),
797:
798: // to internal hardware
799: .qe (),
800: .q (reg2hw.cfg.cpha.q ),
801:
802: // to register interface (read)
803: .qs (cfg_cpha_qs)
804: );
805:
806:
807: // F[tx_order]: 2:2
808: prim_subreg #(
809: .DW (1),
810: .SWACCESS("RW"),
811: .RESVAL (1'h0)
812: ) u_cfg_tx_order (
813: .clk_i (clk_i ),
814: .rst_ni (rst_ni ),
815:
816: // from register interface
817: .we (cfg_tx_order_we),
818: .wd (cfg_tx_order_wd),
819:
820: // from internal hardware
821: .de (1'b0),
822: .d ('0 ),
823:
824: // to internal hardware
825: .qe (),
826: .q (reg2hw.cfg.tx_order.q ),
827:
828: // to register interface (read)
829: .qs (cfg_tx_order_qs)
830: );
831:
832:
833: // F[rx_order]: 3:3
834: prim_subreg #(
835: .DW (1),
836: .SWACCESS("RW"),
837: .RESVAL (1'h0)
838: ) u_cfg_rx_order (
839: .clk_i (clk_i ),
840: .rst_ni (rst_ni ),
841:
842: // from register interface
843: .we (cfg_rx_order_we),
844: .wd (cfg_rx_order_wd),
845:
846: // from internal hardware
847: .de (1'b0),
848: .d ('0 ),
849:
850: // to internal hardware
851: .qe (),
852: .q (reg2hw.cfg.rx_order.q ),
853:
854: // to register interface (read)
855: .qs (cfg_rx_order_qs)
856: );
857:
858:
859: // F[timer_v]: 15:8
860: prim_subreg #(
861: .DW (8),
862: .SWACCESS("RW"),
863: .RESVAL (8'h7f)
864: ) u_cfg_timer_v (
865: .clk_i (clk_i ),
866: .rst_ni (rst_ni ),
867:
868: // from register interface
869: .we (cfg_timer_v_we),
870: .wd (cfg_timer_v_wd),
871:
872: // from internal hardware
873: .de (1'b0),
874: .d ('0 ),
875:
876: // to internal hardware
877: .qe (),
878: .q (reg2hw.cfg.timer_v.q ),
879:
880: // to register interface (read)
881: .qs (cfg_timer_v_qs)
882: );
883:
884:
885: // R[fifo_level]: V(False)
886:
887: // F[rxlvl]: 15:0
888: prim_subreg #(
889: .DW (16),
890: .SWACCESS("RW"),
891: .RESVAL (16'h80)
892: ) u_fifo_level_rxlvl (
893: .clk_i (clk_i ),
894: .rst_ni (rst_ni ),
895:
896: // from register interface
897: .we (fifo_level_rxlvl_we),
898: .wd (fifo_level_rxlvl_wd),
899:
900: // from internal hardware
901: .de (1'b0),
902: .d ('0 ),
903:
904: // to internal hardware
905: .qe (),
906: .q (reg2hw.fifo_level.rxlvl.q ),
907:
908: // to register interface (read)
909: .qs (fifo_level_rxlvl_qs)
910: );
911:
912:
913: // F[txlvl]: 31:16
914: prim_subreg #(
915: .DW (16),
916: .SWACCESS("RW"),
917: .RESVAL (16'h0)
918: ) u_fifo_level_txlvl (
919: .clk_i (clk_i ),
920: .rst_ni (rst_ni ),
921:
922: // from register interface
923: .we (fifo_level_txlvl_we),
924: .wd (fifo_level_txlvl_wd),
925:
926: // from internal hardware
927: .de (1'b0),
928: .d ('0 ),
929:
930: // to internal hardware
931: .qe (),
932: .q (reg2hw.fifo_level.txlvl.q ),
933:
934: // to register interface (read)
935: .qs (fifo_level_txlvl_qs)
936: );
937:
938:
939: // R[async_fifo_level]: V(True)
940:
941: // F[rxlvl]: 7:0
942: prim_subreg_ext #(
943: .DW (8)
944: ) u_async_fifo_level_rxlvl (
945: .re (async_fifo_level_rxlvl_re),
946: .we (1'b0),
947: .wd ('0),
948: .d (hw2reg.async_fifo_level.rxlvl.d),
949: .qre (),
950: .qe (),
951: .q (),
952: .qs (async_fifo_level_rxlvl_qs)
953: );
954:
955:
956: // F[txlvl]: 23:16
957: prim_subreg_ext #(
958: .DW (8)
959: ) u_async_fifo_level_txlvl (
960: .re (async_fifo_level_txlvl_re),
961: .we (1'b0),
962: .wd ('0),
963: .d (hw2reg.async_fifo_level.txlvl.d),
964: .qre (),
965: .qe (),
966: .q (),
967: .qs (async_fifo_level_txlvl_qs)
968: );
969:
970:
971: // R[status]: V(True)
972:
973: // F[rxf_full]: 0:0
974: prim_subreg_ext #(
975: .DW (1)
976: ) u_status_rxf_full (
977: .re (status_rxf_full_re),
978: .we (1'b0),
979: .wd ('0),
980: .d (hw2reg.status.rxf_full.d),
981: .qre (),
982: .qe (),
983: .q (),
984: .qs (status_rxf_full_qs)
985: );
986:
987:
988: // F[rxf_empty]: 1:1
989: prim_subreg_ext #(
990: .DW (1)
991: ) u_status_rxf_empty (
992: .re (status_rxf_empty_re),
993: .we (1'b0),
994: .wd ('0),
995: .d (hw2reg.status.rxf_empty.d),
996: .qre (),
997: .qe (),
998: .q (),
999: .qs (status_rxf_empty_qs)
1000: );
1001:
1002:
1003: // F[txf_full]: 2:2
1004: prim_subreg_ext #(
1005: .DW (1)
1006: ) u_status_txf_full (
1007: .re (status_txf_full_re),
1008: .we (1'b0),
1009: .wd ('0),
1010: .d (hw2reg.status.txf_full.d),
1011: .qre (),
1012: .qe (),
1013: .q (),
1014: .qs (status_txf_full_qs)
1015: );
1016:
1017:
1018: // F[txf_empty]: 3:3
1019: prim_subreg_ext #(
1020: .DW (1)
1021: ) u_status_txf_empty (
1022: .re (status_txf_empty_re),
1023: .we (1'b0),
1024: .wd ('0),
1025: .d (hw2reg.status.txf_empty.d),
1026: .qre (),
1027: .qe (),
1028: .q (),
1029: .qs (status_txf_empty_qs)
1030: );
1031:
1032:
1033: // F[abort_done]: 4:4
1034: prim_subreg_ext #(
1035: .DW (1)
1036: ) u_status_abort_done (
1037: .re (status_abort_done_re),
1038: .we (1'b0),
1039: .wd ('0),
1040: .d (hw2reg.status.abort_done.d),
1041: .qre (),
1042: .qe (),
1043: .q (),
1044: .qs (status_abort_done_qs)
1045: );
1046:
1047:
1048: // F[csb]: 5:5
1049: prim_subreg_ext #(
1050: .DW (1)
1051: ) u_status_csb (
1052: .re (status_csb_re),
1053: .we (1'b0),
1054: .wd ('0),
1055: .d (hw2reg.status.csb.d),
1056: .qre (),
1057: .qe (),
1058: .q (),
1059: .qs (status_csb_qs)
1060: );
1061:
1062:
1063: // R[rxf_ptr]: V(False)
1064:
1065: // F[rptr]: 15:0
1066: prim_subreg #(
1067: .DW (16),
1068: .SWACCESS("RW"),
1069: .RESVAL (16'h0)
1070: ) u_rxf_ptr_rptr (
1071: .clk_i (clk_i ),
1072: .rst_ni (rst_ni ),
1073:
1074: // from register interface
1075: .we (rxf_ptr_rptr_we),
1076: .wd (rxf_ptr_rptr_wd),
1077:
1078: // from internal hardware
1079: .de (1'b0),
1080: .d ('0 ),
1081:
1082: // to internal hardware
1083: .qe (),
1084: .q (reg2hw.rxf_ptr.rptr.q ),
1085:
1086: // to register interface (read)
1087: .qs (rxf_ptr_rptr_qs)
1088: );
1089:
1090:
1091: // F[wptr]: 31:16
1092: prim_subreg #(
1093: .DW (16),
1094: .SWACCESS("RO"),
1095: .RESVAL (16'h0)
1096: ) u_rxf_ptr_wptr (
1097: .clk_i (clk_i ),
1098: .rst_ni (rst_ni ),
1099:
1100: .we (1'b0),
1101: .wd ('0 ),
1102:
1103: // from internal hardware
1104: .de (hw2reg.rxf_ptr.wptr.de),
1105: .d (hw2reg.rxf_ptr.wptr.d ),
1106:
1107: // to internal hardware
1108: .qe (),
1109: .q (),
1110:
1111: // to register interface (read)
1112: .qs (rxf_ptr_wptr_qs)
1113: );
1114:
1115:
1116: // R[txf_ptr]: V(False)
1117:
1118: // F[rptr]: 15:0
1119: prim_subreg #(
1120: .DW (16),
1121: .SWACCESS("RO"),
1122: .RESVAL (16'h0)
1123: ) u_txf_ptr_rptr (
1124: .clk_i (clk_i ),
1125: .rst_ni (rst_ni ),
1126:
1127: .we (1'b0),
1128: .wd ('0 ),
1129:
1130: // from internal hardware
1131: .de (hw2reg.txf_ptr.rptr.de),
1132: .d (hw2reg.txf_ptr.rptr.d ),
1133:
1134: // to internal hardware
1135: .qe (),
1136: .q (),
1137:
1138: // to register interface (read)
1139: .qs (txf_ptr_rptr_qs)
1140: );
1141:
1142:
1143: // F[wptr]: 31:16
1144: prim_subreg #(
1145: .DW (16),
1146: .SWACCESS("RW"),
1147: .RESVAL (16'h0)
1148: ) u_txf_ptr_wptr (
1149: .clk_i (clk_i ),
1150: .rst_ni (rst_ni ),
1151:
1152: // from register interface
1153: .we (txf_ptr_wptr_we),
1154: .wd (txf_ptr_wptr_wd),
1155:
1156: // from internal hardware
1157: .de (1'b0),
1158: .d ('0 ),
1159:
1160: // to internal hardware
1161: .qe (),
1162: .q (reg2hw.txf_ptr.wptr.q ),
1163:
1164: // to register interface (read)
1165: .qs (txf_ptr_wptr_qs)
1166: );
1167:
1168:
1169: // R[rxf_addr]: V(False)
1170:
1171: // F[base]: 15:0
1172: prim_subreg #(
1173: .DW (16),
1174: .SWACCESS("RW"),
1175: .RESVAL (16'h0)
1176: ) u_rxf_addr_base (
1177: .clk_i (clk_i ),
1178: .rst_ni (rst_ni ),
1179:
1180: // from register interface
1181: .we (rxf_addr_base_we),
1182: .wd (rxf_addr_base_wd),
1183:
1184: // from internal hardware
1185: .de (1'b0),
1186: .d ('0 ),
1187:
1188: // to internal hardware
1189: .qe (),
1190: .q (reg2hw.rxf_addr.base.q ),
1191:
1192: // to register interface (read)
1193: .qs (rxf_addr_base_qs)
1194: );
1195:
1196:
1197: // F[limit]: 31:16
1198: prim_subreg #(
1199: .DW (16),
1200: .SWACCESS("RW"),
1201: .RESVAL (16'h1fc)
1202: ) u_rxf_addr_limit (
1203: .clk_i (clk_i ),
1204: .rst_ni (rst_ni ),
1205:
1206: // from register interface
1207: .we (rxf_addr_limit_we),
1208: .wd (rxf_addr_limit_wd),
1209:
1210: // from internal hardware
1211: .de (1'b0),
1212: .d ('0 ),
1213:
1214: // to internal hardware
1215: .qe (),
1216: .q (reg2hw.rxf_addr.limit.q ),
1217:
1218: // to register interface (read)
1219: .qs (rxf_addr_limit_qs)
1220: );
1221:
1222:
1223: // R[txf_addr]: V(False)
1224:
1225: // F[base]: 15:0
1226: prim_subreg #(
1227: .DW (16),
1228: .SWACCESS("RW"),
1229: .RESVAL (16'h200)
1230: ) u_txf_addr_base (
1231: .clk_i (clk_i ),
1232: .rst_ni (rst_ni ),
1233:
1234: // from register interface
1235: .we (txf_addr_base_we),
1236: .wd (txf_addr_base_wd),
1237:
1238: // from internal hardware
1239: .de (1'b0),
1240: .d ('0 ),
1241:
1242: // to internal hardware
1243: .qe (),
1244: .q (reg2hw.txf_addr.base.q ),
1245:
1246: // to register interface (read)
1247: .qs (txf_addr_base_qs)
1248: );
1249:
1250:
1251: // F[limit]: 31:16
1252: prim_subreg #(
1253: .DW (16),
1254: .SWACCESS("RW"),
1255: .RESVAL (16'h3fc)
1256: ) u_txf_addr_limit (
1257: .clk_i (clk_i ),
1258: .rst_ni (rst_ni ),
1259:
1260: // from register interface
1261: .we (txf_addr_limit_we),
1262: .wd (txf_addr_limit_wd),
1263:
1264: // from internal hardware
1265: .de (1'b0),
1266: .d ('0 ),
1267:
1268: // to internal hardware
1269: .qe (),
1270: .q (reg2hw.txf_addr.limit.q ),
1271:
1272: // to register interface (read)
1273: .qs (txf_addr_limit_qs)
1274: );
1275:
1276:
1277:
1278:
1279: logic [11:0] addr_hit;
1280: always_comb begin
1281: addr_hit = '0;
1282: addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
1283: addr_hit[ 1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET);
1284: addr_hit[ 2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET);
1285: addr_hit[ 3] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET);
1286: addr_hit[ 4] = (reg_addr == SPI_DEVICE_CFG_OFFSET);
1287: addr_hit[ 5] = (reg_addr == SPI_DEVICE_FIFO_LEVEL_OFFSET);
1288: addr_hit[ 6] = (reg_addr == SPI_DEVICE_ASYNC_FIFO_LEVEL_OFFSET);
1289: addr_hit[ 7] = (reg_addr == SPI_DEVICE_STATUS_OFFSET);
1290: addr_hit[ 8] = (reg_addr == SPI_DEVICE_RXF_PTR_OFFSET);
1291: addr_hit[ 9] = (reg_addr == SPI_DEVICE_TXF_PTR_OFFSET);
1292: addr_hit[10] = (reg_addr == SPI_DEVICE_RXF_ADDR_OFFSET);
1293: addr_hit[11] = (reg_addr == SPI_DEVICE_TXF_ADDR_OFFSET);
1294: end
1295:
1296: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
1297:
1298: // Check sub-word write is permitted
1299: always_comb begin
1300: wr_err = 1'b0;
1301: if (addr_hit[ 0] && reg_we && (SPI_DEVICE_PERMIT[ 0] != (SPI_DEVICE_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
1302: if (addr_hit[ 1] && reg_we && (SPI_DEVICE_PERMIT[ 1] != (SPI_DEVICE_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
1303: if (addr_hit[ 2] && reg_we && (SPI_DEVICE_PERMIT[ 2] != (SPI_DEVICE_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
1304: if (addr_hit[ 3] && reg_we && (SPI_DEVICE_PERMIT[ 3] != (SPI_DEVICE_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
1305: if (addr_hit[ 4] && reg_we && (SPI_DEVICE_PERMIT[ 4] != (SPI_DEVICE_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
1306: if (addr_hit[ 5] && reg_we && (SPI_DEVICE_PERMIT[ 5] != (SPI_DEVICE_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
1307: if (addr_hit[ 6] && reg_we && (SPI_DEVICE_PERMIT[ 6] != (SPI_DEVICE_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
1308: if (addr_hit[ 7] && reg_we && (SPI_DEVICE_PERMIT[ 7] != (SPI_DEVICE_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
1309: if (addr_hit[ 8] && reg_we && (SPI_DEVICE_PERMIT[ 8] != (SPI_DEVICE_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
1310: if (addr_hit[ 9] && reg_we && (SPI_DEVICE_PERMIT[ 9] != (SPI_DEVICE_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
1311: if (addr_hit[10] && reg_we && (SPI_DEVICE_PERMIT[10] != (SPI_DEVICE_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
1312: if (addr_hit[11] && reg_we && (SPI_DEVICE_PERMIT[11] != (SPI_DEVICE_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
1313: end
1314:
1315: assign intr_state_rxf_we = addr_hit[0] & reg_we & ~wr_err;
1316: assign intr_state_rxf_wd = reg_wdata[0];
1317:
1318: assign intr_state_rxlvl_we = addr_hit[0] & reg_we & ~wr_err;
1319: assign intr_state_rxlvl_wd = reg_wdata[1];
1320:
1321: assign intr_state_txlvl_we = addr_hit[0] & reg_we & ~wr_err;
1322: assign intr_state_txlvl_wd = reg_wdata[2];
1323:
1324: assign intr_state_rxerr_we = addr_hit[0] & reg_we & ~wr_err;
1325: assign intr_state_rxerr_wd = reg_wdata[3];
1326:
1327: assign intr_state_rxoverflow_we = addr_hit[0] & reg_we & ~wr_err;
1328: assign intr_state_rxoverflow_wd = reg_wdata[4];
1329:
1330: assign intr_state_txunderflow_we = addr_hit[0] & reg_we & ~wr_err;
1331: assign intr_state_txunderflow_wd = reg_wdata[5];
1332:
1333: assign intr_enable_rxf_we = addr_hit[1] & reg_we & ~wr_err;
1334: assign intr_enable_rxf_wd = reg_wdata[0];
1335:
1336: assign intr_enable_rxlvl_we = addr_hit[1] & reg_we & ~wr_err;
1337: assign intr_enable_rxlvl_wd = reg_wdata[1];
1338:
1339: assign intr_enable_txlvl_we = addr_hit[1] & reg_we & ~wr_err;
1340: assign intr_enable_txlvl_wd = reg_wdata[2];
1341:
1342: assign intr_enable_rxerr_we = addr_hit[1] & reg_we & ~wr_err;
1343: assign intr_enable_rxerr_wd = reg_wdata[3];
1344:
1345: assign intr_enable_rxoverflow_we = addr_hit[1] & reg_we & ~wr_err;
1346: assign intr_enable_rxoverflow_wd = reg_wdata[4];
1347:
1348: assign intr_enable_txunderflow_we = addr_hit[1] & reg_we & ~wr_err;
1349: assign intr_enable_txunderflow_wd = reg_wdata[5];
1350:
1351: assign intr_test_rxf_we = addr_hit[2] & reg_we & ~wr_err;
1352: assign intr_test_rxf_wd = reg_wdata[0];
1353:
1354: assign intr_test_rxlvl_we = addr_hit[2] & reg_we & ~wr_err;
1355: assign intr_test_rxlvl_wd = reg_wdata[1];
1356:
1357: assign intr_test_txlvl_we = addr_hit[2] & reg_we & ~wr_err;
1358: assign intr_test_txlvl_wd = reg_wdata[2];
1359:
1360: assign intr_test_rxerr_we = addr_hit[2] & reg_we & ~wr_err;
1361: assign intr_test_rxerr_wd = reg_wdata[3];
1362:
1363: assign intr_test_rxoverflow_we = addr_hit[2] & reg_we & ~wr_err;
1364: assign intr_test_rxoverflow_wd = reg_wdata[4];
1365:
1366: assign intr_test_txunderflow_we = addr_hit[2] & reg_we & ~wr_err;
1367: assign intr_test_txunderflow_wd = reg_wdata[5];
1368:
1369: assign control_abort_we = addr_hit[3] & reg_we & ~wr_err;
1370: assign control_abort_wd = reg_wdata[0];
1371:
1372: assign control_mode_we = addr_hit[3] & reg_we & ~wr_err;
1373: assign control_mode_wd = reg_wdata[5:4];
1374:
1375: assign control_rst_txfifo_we = addr_hit[3] & reg_we & ~wr_err;
1376: assign control_rst_txfifo_wd = reg_wdata[16];
1377:
1378: assign control_rst_rxfifo_we = addr_hit[3] & reg_we & ~wr_err;
1379: assign control_rst_rxfifo_wd = reg_wdata[17];
1380:
1381: assign cfg_cpol_we = addr_hit[4] & reg_we & ~wr_err;
1382: assign cfg_cpol_wd = reg_wdata[0];
1383:
1384: assign cfg_cpha_we = addr_hit[4] & reg_we & ~wr_err;
1385: assign cfg_cpha_wd = reg_wdata[1];
1386:
1387: assign cfg_tx_order_we = addr_hit[4] & reg_we & ~wr_err;
1388: assign cfg_tx_order_wd = reg_wdata[2];
1389:
1390: assign cfg_rx_order_we = addr_hit[4] & reg_we & ~wr_err;
1391: assign cfg_rx_order_wd = reg_wdata[3];
1392:
1393: assign cfg_timer_v_we = addr_hit[4] & reg_we & ~wr_err;
1394: assign cfg_timer_v_wd = reg_wdata[15:8];
1395:
1396: assign fifo_level_rxlvl_we = addr_hit[5] & reg_we & ~wr_err;
1397: assign fifo_level_rxlvl_wd = reg_wdata[15:0];
1398:
1399: assign fifo_level_txlvl_we = addr_hit[5] & reg_we & ~wr_err;
1400: assign fifo_level_txlvl_wd = reg_wdata[31:16];
1401:
1402: assign async_fifo_level_rxlvl_re = addr_hit[6] && reg_re;
1403:
1404: assign async_fifo_level_txlvl_re = addr_hit[6] && reg_re;
1405:
1406: assign status_rxf_full_re = addr_hit[7] && reg_re;
1407:
1408: assign status_rxf_empty_re = addr_hit[7] && reg_re;
1409:
1410: assign status_txf_full_re = addr_hit[7] && reg_re;
1411:
1412: assign status_txf_empty_re = addr_hit[7] && reg_re;
1413:
1414: assign status_abort_done_re = addr_hit[7] && reg_re;
1415:
1416: assign status_csb_re = addr_hit[7] && reg_re;
1417:
1418: assign rxf_ptr_rptr_we = addr_hit[8] & reg_we & ~wr_err;
1419: assign rxf_ptr_rptr_wd = reg_wdata[15:0];
1420:
1421:
1422:
1423: assign txf_ptr_wptr_we = addr_hit[9] & reg_we & ~wr_err;
1424: assign txf_ptr_wptr_wd = reg_wdata[31:16];
1425:
1426: assign rxf_addr_base_we = addr_hit[10] & reg_we & ~wr_err;
1427: assign rxf_addr_base_wd = reg_wdata[15:0];
1428:
1429: assign rxf_addr_limit_we = addr_hit[10] & reg_we & ~wr_err;
1430: assign rxf_addr_limit_wd = reg_wdata[31:16];
1431:
1432: assign txf_addr_base_we = addr_hit[11] & reg_we & ~wr_err;
1433: assign txf_addr_base_wd = reg_wdata[15:0];
1434:
1435: assign txf_addr_limit_we = addr_hit[11] & reg_we & ~wr_err;
1436: assign txf_addr_limit_wd = reg_wdata[31:16];
1437:
1438: // Read data return
1439: always_comb begin
1440: reg_rdata_next = '0;
1441: unique case (1'b1)
1442: addr_hit[0]: begin
1443: reg_rdata_next[0] = intr_state_rxf_qs;
1444: reg_rdata_next[1] = intr_state_rxlvl_qs;
1445: reg_rdata_next[2] = intr_state_txlvl_qs;
1446: reg_rdata_next[3] = intr_state_rxerr_qs;
1447: reg_rdata_next[4] = intr_state_rxoverflow_qs;
1448: reg_rdata_next[5] = intr_state_txunderflow_qs;
1449: end
1450:
1451: addr_hit[1]: begin
1452: reg_rdata_next[0] = intr_enable_rxf_qs;
1453: reg_rdata_next[1] = intr_enable_rxlvl_qs;
1454: reg_rdata_next[2] = intr_enable_txlvl_qs;
1455: reg_rdata_next[3] = intr_enable_rxerr_qs;
1456: reg_rdata_next[4] = intr_enable_rxoverflow_qs;
1457: reg_rdata_next[5] = intr_enable_txunderflow_qs;
1458: end
1459:
1460: addr_hit[2]: begin
1461: reg_rdata_next[0] = '0;
1462: reg_rdata_next[1] = '0;
1463: reg_rdata_next[2] = '0;
1464: reg_rdata_next[3] = '0;
1465: reg_rdata_next[4] = '0;
1466: reg_rdata_next[5] = '0;
1467: end
1468:
1469: addr_hit[3]: begin
1470: reg_rdata_next[0] = control_abort_qs;
1471: reg_rdata_next[5:4] = control_mode_qs;
1472: reg_rdata_next[16] = control_rst_txfifo_qs;
1473: reg_rdata_next[17] = control_rst_rxfifo_qs;
1474: end
1475:
1476: addr_hit[4]: begin
1477: reg_rdata_next[0] = cfg_cpol_qs;
1478: reg_rdata_next[1] = cfg_cpha_qs;
1479: reg_rdata_next[2] = cfg_tx_order_qs;
1480: reg_rdata_next[3] = cfg_rx_order_qs;
1481: reg_rdata_next[15:8] = cfg_timer_v_qs;
1482: end
1483:
1484: addr_hit[5]: begin
1485: reg_rdata_next[15:0] = fifo_level_rxlvl_qs;
1486: reg_rdata_next[31:16] = fifo_level_txlvl_qs;
1487: end
1488:
1489: addr_hit[6]: begin
1490: reg_rdata_next[7:0] = async_fifo_level_rxlvl_qs;
1491: reg_rdata_next[23:16] = async_fifo_level_txlvl_qs;
1492: end
1493:
1494: addr_hit[7]: begin
1495: reg_rdata_next[0] = status_rxf_full_qs;
1496: reg_rdata_next[1] = status_rxf_empty_qs;
1497: reg_rdata_next[2] = status_txf_full_qs;
1498: reg_rdata_next[3] = status_txf_empty_qs;
1499: reg_rdata_next[4] = status_abort_done_qs;
1500: reg_rdata_next[5] = status_csb_qs;
1501: end
1502:
1503: addr_hit[8]: begin
1504: reg_rdata_next[15:0] = rxf_ptr_rptr_qs;
1505: reg_rdata_next[31:16] = rxf_ptr_wptr_qs;
1506: end
1507:
1508: addr_hit[9]: begin
1509: reg_rdata_next[15:0] = txf_ptr_rptr_qs;
1510: reg_rdata_next[31:16] = txf_ptr_wptr_qs;
1511: end
1512:
1513: addr_hit[10]: begin
1514: reg_rdata_next[15:0] = rxf_addr_base_qs;
1515: reg_rdata_next[31:16] = rxf_addr_limit_qs;
1516: end
1517:
1518: addr_hit[11]: begin
1519: reg_rdata_next[15:0] = txf_addr_base_qs;
1520: reg_rdata_next[31:16] = txf_addr_limit_qs;
1521: end
1522:
1523: default: begin
1524: reg_rdata_next = '1;
1525: end
1526: endcase
1527: end
1528:
1529: // Assertions for Register Interface
1530: `ASSERT_PULSE(wePulse, reg_we)
1531: `ASSERT_PULSE(rePulse, reg_re)
1532:
1533: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
1534:
1535: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
1536:
1537: // this is formulated as an assumption such that the FPV testbenches do disprove this
1538: // property by mistake
1539: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
1540:
1541: endmodule
1542: