../src/lowrisc_ip_uart_0.1/rtl/uart_reg_pkg.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Package auto-generated by `reggen` containing data structure
   6: 
   7: package uart_reg_pkg;
   8: 
   9:   ////////////////////////////
  10:   // Typedefs for registers //
  11:   ////////////////////////////
  12:   typedef struct packed {
  13:     struct packed {
  14:       logic        q;
  15:     } tx_watermark;
  16:     struct packed {
  17:       logic        q;
  18:     } rx_watermark;
  19:     struct packed {
  20:       logic        q;
  21:     } tx_empty;
  22:     struct packed {
  23:       logic        q;
  24:     } rx_overflow;
  25:     struct packed {
  26:       logic        q;
  27:     } rx_frame_err;
  28:     struct packed {
  29:       logic        q;
  30:     } rx_break_err;
  31:     struct packed {
  32:       logic        q;
  33:     } rx_timeout;
  34:     struct packed {
  35:       logic        q;
  36:     } rx_parity_err;
  37:   } uart_reg2hw_intr_state_reg_t;
  38: 
  39:   typedef struct packed {
  40:     struct packed {
  41:       logic        q;
  42:     } tx_watermark;
  43:     struct packed {
  44:       logic        q;
  45:     } rx_watermark;
  46:     struct packed {
  47:       logic        q;
  48:     } tx_empty;
  49:     struct packed {
  50:       logic        q;
  51:     } rx_overflow;
  52:     struct packed {
  53:       logic        q;
  54:     } rx_frame_err;
  55:     struct packed {
  56:       logic        q;
  57:     } rx_break_err;
  58:     struct packed {
  59:       logic        q;
  60:     } rx_timeout;
  61:     struct packed {
  62:       logic        q;
  63:     } rx_parity_err;
  64:   } uart_reg2hw_intr_enable_reg_t;
  65: 
  66:   typedef struct packed {
  67:     struct packed {
  68:       logic        q;
  69:       logic        qe;
  70:     } tx_watermark;
  71:     struct packed {
  72:       logic        q;
  73:       logic        qe;
  74:     } rx_watermark;
  75:     struct packed {
  76:       logic        q;
  77:       logic        qe;
  78:     } tx_empty;
  79:     struct packed {
  80:       logic        q;
  81:       logic        qe;
  82:     } rx_overflow;
  83:     struct packed {
  84:       logic        q;
  85:       logic        qe;
  86:     } rx_frame_err;
  87:     struct packed {
  88:       logic        q;
  89:       logic        qe;
  90:     } rx_break_err;
  91:     struct packed {
  92:       logic        q;
  93:       logic        qe;
  94:     } rx_timeout;
  95:     struct packed {
  96:       logic        q;
  97:       logic        qe;
  98:     } rx_parity_err;
  99:   } uart_reg2hw_intr_test_reg_t;
 100: 
 101:   typedef struct packed {
 102:     struct packed {
 103:       logic        q;
 104:     } tx;
 105:     struct packed {
 106:       logic        q;
 107:     } rx;
 108:     struct packed {
 109:       logic        q;
 110:     } nf;
 111:     struct packed {
 112:       logic        q;
 113:     } slpbk;
 114:     struct packed {
 115:       logic        q;
 116:     } llpbk;
 117:     struct packed {
 118:       logic        q;
 119:     } parity_en;
 120:     struct packed {
 121:       logic        q;
 122:     } parity_odd;
 123:     struct packed {
 124:       logic [1:0]  q;
 125:     } rxblvl;
 126:     struct packed {
 127:       logic [15:0] q;
 128:     } nco;
 129:   } uart_reg2hw_ctrl_reg_t;
 130: 
 131:   typedef struct packed {
 132:     struct packed {
 133:       logic        q;
 134:       logic        re;
 135:     } txfull;
 136:     struct packed {
 137:       logic        q;
 138:       logic        re;
 139:     } rxfull;
 140:     struct packed {
 141:       logic        q;
 142:       logic        re;
 143:     } txempty;
 144:     struct packed {
 145:       logic        q;
 146:       logic        re;
 147:     } txidle;
 148:     struct packed {
 149:       logic        q;
 150:       logic        re;
 151:     } rxidle;
 152:     struct packed {
 153:       logic        q;
 154:       logic        re;
 155:     } rxempty;
 156:   } uart_reg2hw_status_reg_t;
 157: 
 158:   typedef struct packed {
 159:     logic [7:0]  q;
 160:     logic        re;
 161:   } uart_reg2hw_rdata_reg_t;
 162: 
 163:   typedef struct packed {
 164:     logic [7:0]  q;
 165:     logic        qe;
 166:   } uart_reg2hw_wdata_reg_t;
 167: 
 168:   typedef struct packed {
 169:     struct packed {
 170:       logic        q;
 171:       logic        qe;
 172:     } rxrst;
 173:     struct packed {
 174:       logic        q;
 175:       logic        qe;
 176:     } txrst;
 177:     struct packed {
 178:       logic [2:0]  q;
 179:       logic        qe;
 180:     } rxilvl;
 181:     struct packed {
 182:       logic [1:0]  q;
 183:       logic        qe;
 184:     } txilvl;
 185:   } uart_reg2hw_fifo_ctrl_reg_t;
 186: 
 187:   typedef struct packed {
 188:     struct packed {
 189:       logic        q;
 190:     } txen;
 191:     struct packed {
 192:       logic        q;
 193:     } txval;
 194:   } uart_reg2hw_ovrd_reg_t;
 195: 
 196:   typedef struct packed {
 197:     struct packed {
 198:       logic [23:0] q;
 199:     } val;
 200:     struct packed {
 201:       logic        q;
 202:     } en;
 203:   } uart_reg2hw_timeout_ctrl_reg_t;
 204: 
 205: 
 206:   typedef struct packed {
 207:     struct packed {
 208:       logic        d;
 209:       logic        de;
 210:     } tx_watermark;
 211:     struct packed {
 212:       logic        d;
 213:       logic        de;
 214:     } rx_watermark;
 215:     struct packed {
 216:       logic        d;
 217:       logic        de;
 218:     } tx_empty;
 219:     struct packed {
 220:       logic        d;
 221:       logic        de;
 222:     } rx_overflow;
 223:     struct packed {
 224:       logic        d;
 225:       logic        de;
 226:     } rx_frame_err;
 227:     struct packed {
 228:       logic        d;
 229:       logic        de;
 230:     } rx_break_err;
 231:     struct packed {
 232:       logic        d;
 233:       logic        de;
 234:     } rx_timeout;
 235:     struct packed {
 236:       logic        d;
 237:       logic        de;
 238:     } rx_parity_err;
 239:   } uart_hw2reg_intr_state_reg_t;
 240: 
 241:   typedef struct packed {
 242:     struct packed {
 243:       logic        d;
 244:     } txfull;
 245:     struct packed {
 246:       logic        d;
 247:     } rxfull;
 248:     struct packed {
 249:       logic        d;
 250:     } txempty;
 251:     struct packed {
 252:       logic        d;
 253:     } txidle;
 254:     struct packed {
 255:       logic        d;
 256:     } rxidle;
 257:     struct packed {
 258:       logic        d;
 259:     } rxempty;
 260:   } uart_hw2reg_status_reg_t;
 261: 
 262:   typedef struct packed {
 263:     logic [7:0]  d;
 264:   } uart_hw2reg_rdata_reg_t;
 265: 
 266:   typedef struct packed {
 267:     struct packed {
 268:       logic [2:0]  d;
 269:       logic        de;
 270:     } rxilvl;
 271:     struct packed {
 272:       logic [1:0]  d;
 273:       logic        de;
 274:     } txilvl;
 275:   } uart_hw2reg_fifo_ctrl_reg_t;
 276: 
 277:   typedef struct packed {
 278:     struct packed {
 279:       logic [5:0]  d;
 280:     } txlvl;
 281:     struct packed {
 282:       logic [5:0]  d;
 283:     } rxlvl;
 284:   } uart_hw2reg_fifo_status_reg_t;
 285: 
 286:   typedef struct packed {
 287:     logic [15:0] d;
 288:   } uart_hw2reg_val_reg_t;
 289: 
 290: 
 291:   ///////////////////////////////////////
 292:   // Register to internal design logic //
 293:   ///////////////////////////////////////
 294:   typedef struct packed {
 295:     uart_reg2hw_intr_state_reg_t intr_state; // [124:117]
 296:     uart_reg2hw_intr_enable_reg_t intr_enable; // [116:109]
 297:     uart_reg2hw_intr_test_reg_t intr_test; // [108:93]
 298:     uart_reg2hw_ctrl_reg_t ctrl; // [92:68]
 299:     uart_reg2hw_status_reg_t status; // [67:56]
 300:     uart_reg2hw_rdata_reg_t rdata; // [55:47]
 301:     uart_reg2hw_wdata_reg_t wdata; // [46:38]
 302:     uart_reg2hw_fifo_ctrl_reg_t fifo_ctrl; // [37:27]
 303:     uart_reg2hw_ovrd_reg_t ovrd; // [26:25]
 304:     uart_reg2hw_timeout_ctrl_reg_t timeout_ctrl; // [24:0]
 305:   } uart_reg2hw_t;
 306: 
 307:   ///////////////////////////////////////
 308:   // Internal design logic to register //
 309:   ///////////////////////////////////////
 310:   typedef struct packed {
 311:     uart_hw2reg_intr_state_reg_t intr_state; // [64:57]
 312:     uart_hw2reg_status_reg_t status; // [56:45]
 313:     uart_hw2reg_rdata_reg_t rdata; // [44:36]
 314:     uart_hw2reg_fifo_ctrl_reg_t fifo_ctrl; // [35:25]
 315:     uart_hw2reg_fifo_status_reg_t fifo_status; // [24:25]
 316:     uart_hw2reg_val_reg_t val; // [24:25]
 317:   } uart_hw2reg_t;
 318: 
 319:   // Register Address
 320:   parameter logic [5:0] UART_INTR_STATE_OFFSET = 6'h 0;
 321:   parameter logic [5:0] UART_INTR_ENABLE_OFFSET = 6'h 4;
 322:   parameter logic [5:0] UART_INTR_TEST_OFFSET = 6'h 8;
 323:   parameter logic [5:0] UART_CTRL_OFFSET = 6'h c;
 324:   parameter logic [5:0] UART_STATUS_OFFSET = 6'h 10;
 325:   parameter logic [5:0] UART_RDATA_OFFSET = 6'h 14;
 326:   parameter logic [5:0] UART_WDATA_OFFSET = 6'h 18;
 327:   parameter logic [5:0] UART_FIFO_CTRL_OFFSET = 6'h 1c;
 328:   parameter logic [5:0] UART_FIFO_STATUS_OFFSET = 6'h 20;
 329:   parameter logic [5:0] UART_OVRD_OFFSET = 6'h 24;
 330:   parameter logic [5:0] UART_VAL_OFFSET = 6'h 28;
 331:   parameter logic [5:0] UART_TIMEOUT_CTRL_OFFSET = 6'h 2c;
 332: 
 333: 
 334:   // Register Index
 335:   typedef enum int {
 336:     UART_INTR_STATE,
 337:     UART_INTR_ENABLE,
 338:     UART_INTR_TEST,
 339:     UART_CTRL,
 340:     UART_STATUS,
 341:     UART_RDATA,
 342:     UART_WDATA,
 343:     UART_FIFO_CTRL,
 344:     UART_FIFO_STATUS,
 345:     UART_OVRD,
 346:     UART_VAL,
 347:     UART_TIMEOUT_CTRL
 348:   } uart_id_e;
 349: 
 350:   // Register width information to check illegal writes
 351:   parameter logic [3:0] UART_PERMIT [12] = '{
 352:     4'b 0001, // index[ 0] UART_INTR_STATE
 353:     4'b 0001, // index[ 1] UART_INTR_ENABLE
 354:     4'b 0001, // index[ 2] UART_INTR_TEST
 355:     4'b 1111, // index[ 3] UART_CTRL
 356:     4'b 0001, // index[ 4] UART_STATUS
 357:     4'b 0001, // index[ 5] UART_RDATA
 358:     4'b 0001, // index[ 6] UART_WDATA
 359:     4'b 0001, // index[ 7] UART_FIFO_CTRL
 360:     4'b 0111, // index[ 8] UART_FIFO_STATUS
 361:     4'b 0001, // index[ 9] UART_OVRD
 362:     4'b 0011, // index[10] UART_VAL
 363:     4'b 1111  // index[11] UART_TIMEOUT_CTRL
 364:   };
 365: endpackage
 366: 
 367: