hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package rv_plic_reg_pkg;
8:
9: // Param list
10: localparam int NumSrc = 63;
11: localparam int NumTarget = 1;
12:
13: ////////////////////////////
14: // Typedefs for registers //
15: ////////////////////////////
16: typedef struct packed {
17: logic q;
18: } rv_plic_reg2hw_le_mreg_t;
19:
20: typedef struct packed {
21: logic [1:0] q;
22: } rv_plic_reg2hw_prio0_reg_t;
23:
24: typedef struct packed {
25: logic [1:0] q;
26: } rv_plic_reg2hw_prio1_reg_t;
27:
28: typedef struct packed {
29: logic [1:0] q;
30: } rv_plic_reg2hw_prio2_reg_t;
31:
32: typedef struct packed {
33: logic [1:0] q;
34: } rv_plic_reg2hw_prio3_reg_t;
35:
36: typedef struct packed {
37: logic [1:0] q;
38: } rv_plic_reg2hw_prio4_reg_t;
39:
40: typedef struct packed {
41: logic [1:0] q;
42: } rv_plic_reg2hw_prio5_reg_t;
43:
44: typedef struct packed {
45: logic [1:0] q;
46: } rv_plic_reg2hw_prio6_reg_t;
47:
48: typedef struct packed {
49: logic [1:0] q;
50: } rv_plic_reg2hw_prio7_reg_t;
51:
52: typedef struct packed {
53: logic [1:0] q;
54: } rv_plic_reg2hw_prio8_reg_t;
55:
56: typedef struct packed {
57: logic [1:0] q;
58: } rv_plic_reg2hw_prio9_reg_t;
59:
60: typedef struct packed {
61: logic [1:0] q;
62: } rv_plic_reg2hw_prio10_reg_t;
63:
64: typedef struct packed {
65: logic [1:0] q;
66: } rv_plic_reg2hw_prio11_reg_t;
67:
68: typedef struct packed {
69: logic [1:0] q;
70: } rv_plic_reg2hw_prio12_reg_t;
71:
72: typedef struct packed {
73: logic [1:0] q;
74: } rv_plic_reg2hw_prio13_reg_t;
75:
76: typedef struct packed {
77: logic [1:0] q;
78: } rv_plic_reg2hw_prio14_reg_t;
79:
80: typedef struct packed {
81: logic [1:0] q;
82: } rv_plic_reg2hw_prio15_reg_t;
83:
84: typedef struct packed {
85: logic [1:0] q;
86: } rv_plic_reg2hw_prio16_reg_t;
87:
88: typedef struct packed {
89: logic [1:0] q;
90: } rv_plic_reg2hw_prio17_reg_t;
91:
92: typedef struct packed {
93: logic [1:0] q;
94: } rv_plic_reg2hw_prio18_reg_t;
95:
96: typedef struct packed {
97: logic [1:0] q;
98: } rv_plic_reg2hw_prio19_reg_t;
99:
100: typedef struct packed {
101: logic [1:0] q;
102: } rv_plic_reg2hw_prio20_reg_t;
103:
104: typedef struct packed {
105: logic [1:0] q;
106: } rv_plic_reg2hw_prio21_reg_t;
107:
108: typedef struct packed {
109: logic [1:0] q;
110: } rv_plic_reg2hw_prio22_reg_t;
111:
112: typedef struct packed {
113: logic [1:0] q;
114: } rv_plic_reg2hw_prio23_reg_t;
115:
116: typedef struct packed {
117: logic [1:0] q;
118: } rv_plic_reg2hw_prio24_reg_t;
119:
120: typedef struct packed {
121: logic [1:0] q;
122: } rv_plic_reg2hw_prio25_reg_t;
123:
124: typedef struct packed {
125: logic [1:0] q;
126: } rv_plic_reg2hw_prio26_reg_t;
127:
128: typedef struct packed {
129: logic [1:0] q;
130: } rv_plic_reg2hw_prio27_reg_t;
131:
132: typedef struct packed {
133: logic [1:0] q;
134: } rv_plic_reg2hw_prio28_reg_t;
135:
136: typedef struct packed {
137: logic [1:0] q;
138: } rv_plic_reg2hw_prio29_reg_t;
139:
140: typedef struct packed {
141: logic [1:0] q;
142: } rv_plic_reg2hw_prio30_reg_t;
143:
144: typedef struct packed {
145: logic [1:0] q;
146: } rv_plic_reg2hw_prio31_reg_t;
147:
148: typedef struct packed {
149: logic [1:0] q;
150: } rv_plic_reg2hw_prio32_reg_t;
151:
152: typedef struct packed {
153: logic [1:0] q;
154: } rv_plic_reg2hw_prio33_reg_t;
155:
156: typedef struct packed {
157: logic [1:0] q;
158: } rv_plic_reg2hw_prio34_reg_t;
159:
160: typedef struct packed {
161: logic [1:0] q;
162: } rv_plic_reg2hw_prio35_reg_t;
163:
164: typedef struct packed {
165: logic [1:0] q;
166: } rv_plic_reg2hw_prio36_reg_t;
167:
168: typedef struct packed {
169: logic [1:0] q;
170: } rv_plic_reg2hw_prio37_reg_t;
171:
172: typedef struct packed {
173: logic [1:0] q;
174: } rv_plic_reg2hw_prio38_reg_t;
175:
176: typedef struct packed {
177: logic [1:0] q;
178: } rv_plic_reg2hw_prio39_reg_t;
179:
180: typedef struct packed {
181: logic [1:0] q;
182: } rv_plic_reg2hw_prio40_reg_t;
183:
184: typedef struct packed {
185: logic [1:0] q;
186: } rv_plic_reg2hw_prio41_reg_t;
187:
188: typedef struct packed {
189: logic [1:0] q;
190: } rv_plic_reg2hw_prio42_reg_t;
191:
192: typedef struct packed {
193: logic [1:0] q;
194: } rv_plic_reg2hw_prio43_reg_t;
195:
196: typedef struct packed {
197: logic [1:0] q;
198: } rv_plic_reg2hw_prio44_reg_t;
199:
200: typedef struct packed {
201: logic [1:0] q;
202: } rv_plic_reg2hw_prio45_reg_t;
203:
204: typedef struct packed {
205: logic [1:0] q;
206: } rv_plic_reg2hw_prio46_reg_t;
207:
208: typedef struct packed {
209: logic [1:0] q;
210: } rv_plic_reg2hw_prio47_reg_t;
211:
212: typedef struct packed {
213: logic [1:0] q;
214: } rv_plic_reg2hw_prio48_reg_t;
215:
216: typedef struct packed {
217: logic [1:0] q;
218: } rv_plic_reg2hw_prio49_reg_t;
219:
220: typedef struct packed {
221: logic [1:0] q;
222: } rv_plic_reg2hw_prio50_reg_t;
223:
224: typedef struct packed {
225: logic [1:0] q;
226: } rv_plic_reg2hw_prio51_reg_t;
227:
228: typedef struct packed {
229: logic [1:0] q;
230: } rv_plic_reg2hw_prio52_reg_t;
231:
232: typedef struct packed {
233: logic [1:0] q;
234: } rv_plic_reg2hw_prio53_reg_t;
235:
236: typedef struct packed {
237: logic [1:0] q;
238: } rv_plic_reg2hw_prio54_reg_t;
239:
240: typedef struct packed {
241: logic [1:0] q;
242: } rv_plic_reg2hw_prio55_reg_t;
243:
244: typedef struct packed {
245: logic [1:0] q;
246: } rv_plic_reg2hw_prio56_reg_t;
247:
248: typedef struct packed {
249: logic [1:0] q;
250: } rv_plic_reg2hw_prio57_reg_t;
251:
252: typedef struct packed {
253: logic [1:0] q;
254: } rv_plic_reg2hw_prio58_reg_t;
255:
256: typedef struct packed {
257: logic [1:0] q;
258: } rv_plic_reg2hw_prio59_reg_t;
259:
260: typedef struct packed {
261: logic [1:0] q;
262: } rv_plic_reg2hw_prio60_reg_t;
263:
264: typedef struct packed {
265: logic [1:0] q;
266: } rv_plic_reg2hw_prio61_reg_t;
267:
268: typedef struct packed {
269: logic [1:0] q;
270: } rv_plic_reg2hw_prio62_reg_t;
271:
272: typedef struct packed {
273: logic q;
274: } rv_plic_reg2hw_ie0_mreg_t;
275:
276: typedef struct packed {
277: logic [1:0] q;
278: } rv_plic_reg2hw_threshold0_reg_t;
279:
280: typedef struct packed {
281: logic [5:0] q;
282: logic qe;
283: logic re;
284: } rv_plic_reg2hw_cc0_reg_t;
285:
286: typedef struct packed {
287: logic q;
288: } rv_plic_reg2hw_msip0_reg_t;
289:
290:
291: typedef struct packed {
292: logic d;
293: logic de;
294: } rv_plic_hw2reg_ip_mreg_t;
295:
296: typedef struct packed {
297: logic [5:0] d;
298: } rv_plic_hw2reg_cc0_reg_t;
299:
300:
301: ///////////////////////////////////////
302: // Register to internal design logic //
303: ///////////////////////////////////////
304: typedef struct packed {
305: rv_plic_reg2hw_le_mreg_t [62:0] le; // [262:200]
306: rv_plic_reg2hw_prio0_reg_t prio0; // [199:198]
307: rv_plic_reg2hw_prio1_reg_t prio1; // [197:196]
308: rv_plic_reg2hw_prio2_reg_t prio2; // [195:194]
309: rv_plic_reg2hw_prio3_reg_t prio3; // [193:192]
310: rv_plic_reg2hw_prio4_reg_t prio4; // [191:190]
311: rv_plic_reg2hw_prio5_reg_t prio5; // [189:188]
312: rv_plic_reg2hw_prio6_reg_t prio6; // [187:186]
313: rv_plic_reg2hw_prio7_reg_t prio7; // [185:184]
314: rv_plic_reg2hw_prio8_reg_t prio8; // [183:182]
315: rv_plic_reg2hw_prio9_reg_t prio9; // [181:180]
316: rv_plic_reg2hw_prio10_reg_t prio10; // [179:178]
317: rv_plic_reg2hw_prio11_reg_t prio11; // [177:176]
318: rv_plic_reg2hw_prio12_reg_t prio12; // [175:174]
319: rv_plic_reg2hw_prio13_reg_t prio13; // [173:172]
320: rv_plic_reg2hw_prio14_reg_t prio14; // [171:170]
321: rv_plic_reg2hw_prio15_reg_t prio15; // [169:168]
322: rv_plic_reg2hw_prio16_reg_t prio16; // [167:166]
323: rv_plic_reg2hw_prio17_reg_t prio17; // [165:164]
324: rv_plic_reg2hw_prio18_reg_t prio18; // [163:162]
325: rv_plic_reg2hw_prio19_reg_t prio19; // [161:160]
326: rv_plic_reg2hw_prio20_reg_t prio20; // [159:158]
327: rv_plic_reg2hw_prio21_reg_t prio21; // [157:156]
328: rv_plic_reg2hw_prio22_reg_t prio22; // [155:154]
329: rv_plic_reg2hw_prio23_reg_t prio23; // [153:152]
330: rv_plic_reg2hw_prio24_reg_t prio24; // [151:150]
331: rv_plic_reg2hw_prio25_reg_t prio25; // [149:148]
332: rv_plic_reg2hw_prio26_reg_t prio26; // [147:146]
333: rv_plic_reg2hw_prio27_reg_t prio27; // [145:144]
334: rv_plic_reg2hw_prio28_reg_t prio28; // [143:142]
335: rv_plic_reg2hw_prio29_reg_t prio29; // [141:140]
336: rv_plic_reg2hw_prio30_reg_t prio30; // [139:138]
337: rv_plic_reg2hw_prio31_reg_t prio31; // [137:136]
338: rv_plic_reg2hw_prio32_reg_t prio32; // [135:134]
339: rv_plic_reg2hw_prio33_reg_t prio33; // [133:132]
340: rv_plic_reg2hw_prio34_reg_t prio34; // [131:130]
341: rv_plic_reg2hw_prio35_reg_t prio35; // [129:128]
342: rv_plic_reg2hw_prio36_reg_t prio36; // [127:126]
343: rv_plic_reg2hw_prio37_reg_t prio37; // [125:124]
344: rv_plic_reg2hw_prio38_reg_t prio38; // [123:122]
345: rv_plic_reg2hw_prio39_reg_t prio39; // [121:120]
346: rv_plic_reg2hw_prio40_reg_t prio40; // [119:118]
347: rv_plic_reg2hw_prio41_reg_t prio41; // [117:116]
348: rv_plic_reg2hw_prio42_reg_t prio42; // [115:114]
349: rv_plic_reg2hw_prio43_reg_t prio43; // [113:112]
350: rv_plic_reg2hw_prio44_reg_t prio44; // [111:110]
351: rv_plic_reg2hw_prio45_reg_t prio45; // [109:108]
352: rv_plic_reg2hw_prio46_reg_t prio46; // [107:106]
353: rv_plic_reg2hw_prio47_reg_t prio47; // [105:104]
354: rv_plic_reg2hw_prio48_reg_t prio48; // [103:102]
355: rv_plic_reg2hw_prio49_reg_t prio49; // [101:100]
356: rv_plic_reg2hw_prio50_reg_t prio50; // [99:98]
357: rv_plic_reg2hw_prio51_reg_t prio51; // [97:96]
358: rv_plic_reg2hw_prio52_reg_t prio52; // [95:94]
359: rv_plic_reg2hw_prio53_reg_t prio53; // [93:92]
360: rv_plic_reg2hw_prio54_reg_t prio54; // [91:90]
361: rv_plic_reg2hw_prio55_reg_t prio55; // [89:88]
362: rv_plic_reg2hw_prio56_reg_t prio56; // [87:86]
363: rv_plic_reg2hw_prio57_reg_t prio57; // [85:84]
364: rv_plic_reg2hw_prio58_reg_t prio58; // [83:82]
365: rv_plic_reg2hw_prio59_reg_t prio59; // [81:80]
366: rv_plic_reg2hw_prio60_reg_t prio60; // [79:78]
367: rv_plic_reg2hw_prio61_reg_t prio61; // [77:76]
368: rv_plic_reg2hw_prio62_reg_t prio62; // [75:74]
369: rv_plic_reg2hw_ie0_mreg_t [62:0] ie0; // [73:11]
370: rv_plic_reg2hw_threshold0_reg_t threshold0; // [10:9]
371: rv_plic_reg2hw_cc0_reg_t cc0; // [8:1]
372: rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
373: } rv_plic_reg2hw_t;
374:
375: ///////////////////////////////////////
376: // Internal design logic to register //
377: ///////////////////////////////////////
378: typedef struct packed {
379: rv_plic_hw2reg_ip_mreg_t [62:0] ip; // [131:6]
380: rv_plic_hw2reg_cc0_reg_t cc0; // [5:-2]
381: } rv_plic_hw2reg_t;
382:
383: // Register Address
384: parameter RV_PLIC_IP0_OFFSET = 10'h 0;
385: parameter RV_PLIC_IP1_OFFSET = 10'h 4;
386: parameter RV_PLIC_LE0_OFFSET = 10'h 8;
387: parameter RV_PLIC_LE1_OFFSET = 10'h c;
388: parameter RV_PLIC_PRIO0_OFFSET = 10'h 10;
389: parameter RV_PLIC_PRIO1_OFFSET = 10'h 14;
390: parameter RV_PLIC_PRIO2_OFFSET = 10'h 18;
391: parameter RV_PLIC_PRIO3_OFFSET = 10'h 1c;
392: parameter RV_PLIC_PRIO4_OFFSET = 10'h 20;
393: parameter RV_PLIC_PRIO5_OFFSET = 10'h 24;
394: parameter RV_PLIC_PRIO6_OFFSET = 10'h 28;
395: parameter RV_PLIC_PRIO7_OFFSET = 10'h 2c;
396: parameter RV_PLIC_PRIO8_OFFSET = 10'h 30;
397: parameter RV_PLIC_PRIO9_OFFSET = 10'h 34;
398: parameter RV_PLIC_PRIO10_OFFSET = 10'h 38;
399: parameter RV_PLIC_PRIO11_OFFSET = 10'h 3c;
400: parameter RV_PLIC_PRIO12_OFFSET = 10'h 40;
401: parameter RV_PLIC_PRIO13_OFFSET = 10'h 44;
402: parameter RV_PLIC_PRIO14_OFFSET = 10'h 48;
403: parameter RV_PLIC_PRIO15_OFFSET = 10'h 4c;
404: parameter RV_PLIC_PRIO16_OFFSET = 10'h 50;
405: parameter RV_PLIC_PRIO17_OFFSET = 10'h 54;
406: parameter RV_PLIC_PRIO18_OFFSET = 10'h 58;
407: parameter RV_PLIC_PRIO19_OFFSET = 10'h 5c;
408: parameter RV_PLIC_PRIO20_OFFSET = 10'h 60;
409: parameter RV_PLIC_PRIO21_OFFSET = 10'h 64;
410: parameter RV_PLIC_PRIO22_OFFSET = 10'h 68;
411: parameter RV_PLIC_PRIO23_OFFSET = 10'h 6c;
412: parameter RV_PLIC_PRIO24_OFFSET = 10'h 70;
413: parameter RV_PLIC_PRIO25_OFFSET = 10'h 74;
414: parameter RV_PLIC_PRIO26_OFFSET = 10'h 78;
415: parameter RV_PLIC_PRIO27_OFFSET = 10'h 7c;
416: parameter RV_PLIC_PRIO28_OFFSET = 10'h 80;
417: parameter RV_PLIC_PRIO29_OFFSET = 10'h 84;
418: parameter RV_PLIC_PRIO30_OFFSET = 10'h 88;
419: parameter RV_PLIC_PRIO31_OFFSET = 10'h 8c;
420: parameter RV_PLIC_PRIO32_OFFSET = 10'h 90;
421: parameter RV_PLIC_PRIO33_OFFSET = 10'h 94;
422: parameter RV_PLIC_PRIO34_OFFSET = 10'h 98;
423: parameter RV_PLIC_PRIO35_OFFSET = 10'h 9c;
424: parameter RV_PLIC_PRIO36_OFFSET = 10'h a0;
425: parameter RV_PLIC_PRIO37_OFFSET = 10'h a4;
426: parameter RV_PLIC_PRIO38_OFFSET = 10'h a8;
427: parameter RV_PLIC_PRIO39_OFFSET = 10'h ac;
428: parameter RV_PLIC_PRIO40_OFFSET = 10'h b0;
429: parameter RV_PLIC_PRIO41_OFFSET = 10'h b4;
430: parameter RV_PLIC_PRIO42_OFFSET = 10'h b8;
431: parameter RV_PLIC_PRIO43_OFFSET = 10'h bc;
432: parameter RV_PLIC_PRIO44_OFFSET = 10'h c0;
433: parameter RV_PLIC_PRIO45_OFFSET = 10'h c4;
434: parameter RV_PLIC_PRIO46_OFFSET = 10'h c8;
435: parameter RV_PLIC_PRIO47_OFFSET = 10'h cc;
436: parameter RV_PLIC_PRIO48_OFFSET = 10'h d0;
437: parameter RV_PLIC_PRIO49_OFFSET = 10'h d4;
438: parameter RV_PLIC_PRIO50_OFFSET = 10'h d8;
439: parameter RV_PLIC_PRIO51_OFFSET = 10'h dc;
440: parameter RV_PLIC_PRIO52_OFFSET = 10'h e0;
441: parameter RV_PLIC_PRIO53_OFFSET = 10'h e4;
442: parameter RV_PLIC_PRIO54_OFFSET = 10'h e8;
443: parameter RV_PLIC_PRIO55_OFFSET = 10'h ec;
444: parameter RV_PLIC_PRIO56_OFFSET = 10'h f0;
445: parameter RV_PLIC_PRIO57_OFFSET = 10'h f4;
446: parameter RV_PLIC_PRIO58_OFFSET = 10'h f8;
447: parameter RV_PLIC_PRIO59_OFFSET = 10'h fc;
448: parameter RV_PLIC_PRIO60_OFFSET = 10'h 100;
449: parameter RV_PLIC_PRIO61_OFFSET = 10'h 104;
450: parameter RV_PLIC_PRIO62_OFFSET = 10'h 108;
451: parameter RV_PLIC_IE00_OFFSET = 10'h 200;
452: parameter RV_PLIC_IE01_OFFSET = 10'h 204;
453: parameter RV_PLIC_THRESHOLD0_OFFSET = 10'h 208;
454: parameter RV_PLIC_CC0_OFFSET = 10'h 20c;
455: parameter RV_PLIC_MSIP0_OFFSET = 10'h 210;
456:
457:
458: // Register Index
459: typedef enum int {
460: RV_PLIC_IP0,
461: RV_PLIC_IP1,
462: RV_PLIC_LE0,
463: RV_PLIC_LE1,
464: RV_PLIC_PRIO0,
465: RV_PLIC_PRIO1,
466: RV_PLIC_PRIO2,
467: RV_PLIC_PRIO3,
468: RV_PLIC_PRIO4,
469: RV_PLIC_PRIO5,
470: RV_PLIC_PRIO6,
471: RV_PLIC_PRIO7,
472: RV_PLIC_PRIO8,
473: RV_PLIC_PRIO9,
474: RV_PLIC_PRIO10,
475: RV_PLIC_PRIO11,
476: RV_PLIC_PRIO12,
477: RV_PLIC_PRIO13,
478: RV_PLIC_PRIO14,
479: RV_PLIC_PRIO15,
480: RV_PLIC_PRIO16,
481: RV_PLIC_PRIO17,
482: RV_PLIC_PRIO18,
483: RV_PLIC_PRIO19,
484: RV_PLIC_PRIO20,
485: RV_PLIC_PRIO21,
486: RV_PLIC_PRIO22,
487: RV_PLIC_PRIO23,
488: RV_PLIC_PRIO24,
489: RV_PLIC_PRIO25,
490: RV_PLIC_PRIO26,
491: RV_PLIC_PRIO27,
492: RV_PLIC_PRIO28,
493: RV_PLIC_PRIO29,
494: RV_PLIC_PRIO30,
495: RV_PLIC_PRIO31,
496: RV_PLIC_PRIO32,
497: RV_PLIC_PRIO33,
498: RV_PLIC_PRIO34,
499: RV_PLIC_PRIO35,
500: RV_PLIC_PRIO36,
501: RV_PLIC_PRIO37,
502: RV_PLIC_PRIO38,
503: RV_PLIC_PRIO39,
504: RV_PLIC_PRIO40,
505: RV_PLIC_PRIO41,
506: RV_PLIC_PRIO42,
507: RV_PLIC_PRIO43,
508: RV_PLIC_PRIO44,
509: RV_PLIC_PRIO45,
510: RV_PLIC_PRIO46,
511: RV_PLIC_PRIO47,
512: RV_PLIC_PRIO48,
513: RV_PLIC_PRIO49,
514: RV_PLIC_PRIO50,
515: RV_PLIC_PRIO51,
516: RV_PLIC_PRIO52,
517: RV_PLIC_PRIO53,
518: RV_PLIC_PRIO54,
519: RV_PLIC_PRIO55,
520: RV_PLIC_PRIO56,
521: RV_PLIC_PRIO57,
522: RV_PLIC_PRIO58,
523: RV_PLIC_PRIO59,
524: RV_PLIC_PRIO60,
525: RV_PLIC_PRIO61,
526: RV_PLIC_PRIO62,
527: RV_PLIC_IE00,
528: RV_PLIC_IE01,
529: RV_PLIC_THRESHOLD0,
530: RV_PLIC_CC0,
531: RV_PLIC_MSIP0
532: } rv_plic_id_e;
533:
534: // Register width information to check illegal writes
535: localparam logic [3:0] RV_PLIC_PERMIT [72] = '{
536: 4'b 1111, // index[ 0] RV_PLIC_IP0
537: 4'b 1111, // index[ 1] RV_PLIC_IP1
538: 4'b 1111, // index[ 2] RV_PLIC_LE0
539: 4'b 1111, // index[ 3] RV_PLIC_LE1
540: 4'b 0001, // index[ 4] RV_PLIC_PRIO0
541: 4'b 0001, // index[ 5] RV_PLIC_PRIO1
542: 4'b 0001, // index[ 6] RV_PLIC_PRIO2
543: 4'b 0001, // index[ 7] RV_PLIC_PRIO3
544: 4'b 0001, // index[ 8] RV_PLIC_PRIO4
545: 4'b 0001, // index[ 9] RV_PLIC_PRIO5
546: 4'b 0001, // index[10] RV_PLIC_PRIO6
547: 4'b 0001, // index[11] RV_PLIC_PRIO7
548: 4'b 0001, // index[12] RV_PLIC_PRIO8
549: 4'b 0001, // index[13] RV_PLIC_PRIO9
550: 4'b 0001, // index[14] RV_PLIC_PRIO10
551: 4'b 0001, // index[15] RV_PLIC_PRIO11
552: 4'b 0001, // index[16] RV_PLIC_PRIO12
553: 4'b 0001, // index[17] RV_PLIC_PRIO13
554: 4'b 0001, // index[18] RV_PLIC_PRIO14
555: 4'b 0001, // index[19] RV_PLIC_PRIO15
556: 4'b 0001, // index[20] RV_PLIC_PRIO16
557: 4'b 0001, // index[21] RV_PLIC_PRIO17
558: 4'b 0001, // index[22] RV_PLIC_PRIO18
559: 4'b 0001, // index[23] RV_PLIC_PRIO19
560: 4'b 0001, // index[24] RV_PLIC_PRIO20
561: 4'b 0001, // index[25] RV_PLIC_PRIO21
562: 4'b 0001, // index[26] RV_PLIC_PRIO22
563: 4'b 0001, // index[27] RV_PLIC_PRIO23
564: 4'b 0001, // index[28] RV_PLIC_PRIO24
565: 4'b 0001, // index[29] RV_PLIC_PRIO25
566: 4'b 0001, // index[30] RV_PLIC_PRIO26
567: 4'b 0001, // index[31] RV_PLIC_PRIO27
568: 4'b 0001, // index[32] RV_PLIC_PRIO28
569: 4'b 0001, // index[33] RV_PLIC_PRIO29
570: 4'b 0001, // index[34] RV_PLIC_PRIO30
571: 4'b 0001, // index[35] RV_PLIC_PRIO31
572: 4'b 0001, // index[36] RV_PLIC_PRIO32
573: 4'b 0001, // index[37] RV_PLIC_PRIO33
574: 4'b 0001, // index[38] RV_PLIC_PRIO34
575: 4'b 0001, // index[39] RV_PLIC_PRIO35
576: 4'b 0001, // index[40] RV_PLIC_PRIO36
577: 4'b 0001, // index[41] RV_PLIC_PRIO37
578: 4'b 0001, // index[42] RV_PLIC_PRIO38
579: 4'b 0001, // index[43] RV_PLIC_PRIO39
580: 4'b 0001, // index[44] RV_PLIC_PRIO40
581: 4'b 0001, // index[45] RV_PLIC_PRIO41
582: 4'b 0001, // index[46] RV_PLIC_PRIO42
583: 4'b 0001, // index[47] RV_PLIC_PRIO43
584: 4'b 0001, // index[48] RV_PLIC_PRIO44
585: 4'b 0001, // index[49] RV_PLIC_PRIO45
586: 4'b 0001, // index[50] RV_PLIC_PRIO46
587: 4'b 0001, // index[51] RV_PLIC_PRIO47
588: 4'b 0001, // index[52] RV_PLIC_PRIO48
589: 4'b 0001, // index[53] RV_PLIC_PRIO49
590: 4'b 0001, // index[54] RV_PLIC_PRIO50
591: 4'b 0001, // index[55] RV_PLIC_PRIO51
592: 4'b 0001, // index[56] RV_PLIC_PRIO52
593: 4'b 0001, // index[57] RV_PLIC_PRIO53
594: 4'b 0001, // index[58] RV_PLIC_PRIO54
595: 4'b 0001, // index[59] RV_PLIC_PRIO55
596: 4'b 0001, // index[60] RV_PLIC_PRIO56
597: 4'b 0001, // index[61] RV_PLIC_PRIO57
598: 4'b 0001, // index[62] RV_PLIC_PRIO58
599: 4'b 0001, // index[63] RV_PLIC_PRIO59
600: 4'b 0001, // index[64] RV_PLIC_PRIO60
601: 4'b 0001, // index[65] RV_PLIC_PRIO61
602: 4'b 0001, // index[66] RV_PLIC_PRIO62
603: 4'b 1111, // index[67] RV_PLIC_IE00
604: 4'b 1111, // index[68] RV_PLIC_IE01
605: 4'b 0001, // index[69] RV_PLIC_THRESHOLD0
606: 4'b 0001, // index[70] RV_PLIC_CC0
607: 4'b 0001 // index[71] RV_PLIC_MSIP0
608: };
609: endpackage
610:
611: