hw/ip/tlul/rtl/sram2tlul.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // SRAM interface to TL-UL converter
   6: //      Current version only supports if TL-UL width and SRAM width are same
   7: //      If SRAM interface requests more than MaxOutstanding cap, it generates
   8: //      error in simulation but not in Silicon.
   9: 
  10: module sram2tlul #(
  11:   parameter int                        SramAw = 12,
  12:   parameter int                        SramDw = 32,
  13:   parameter logic [top_pkg::TL_AW-1:0] TlBaseAddr = 'h0  // Base address of SRAM request
  14: ) (
  15:   input clk_i,
  16:   input rst_ni,
  17: 
  18:   output tlul_pkg::tl_h2d_t tl_o,
  19:   input  tlul_pkg::tl_d2h_t tl_i,
  20: 
  21:   // SRAM
  22:   input                     mem_req,
  23:   input                     mem_write,
  24:   input        [SramAw-1:0] mem_addr,
  25:   input        [SramDw-1:0] mem_wdata,
  26:   output logic              mem_rvalid,
  27:   output logic [SramDw-1:0] mem_rdata,
  28:   output logic        [1:0] mem_error
  29: );
  30: 
  31:   import tlul_pkg::*;
  32: 
  33:   `ifndef SYNTHESIS
  34:   if (SramDw != top_pkg::TL_DW) $fatal("SRAM_DW should be same as TL-UL DW");
  35:   `endif
  36: 
  37:   localparam int unsigned SRAM_DWB = $clog2(SramDw/8);
  38: 
  39:   assign tl_o.a_valid   = mem_req;
  40:   assign tl_o.a_opcode  = (mem_write) ? PutFullData : Get;
  41:   assign tl_o.a_param   = '0;
  42:   assign tl_o.a_size    = top_pkg::TL_SZW'(SRAM_DWB); // Max Size always
  43:   assign tl_o.a_source  = '0;
  44:   assign tl_o.a_address = TlBaseAddr |
  45:                           {{(top_pkg::TL_AW-SramAw-SRAM_DWB){1'b0}},mem_addr,{(SRAM_DWB){1'b0}}};
  46:   assign tl_o.a_mask    = '1;
  47:   assign tl_o.a_data    = mem_wdata;
  48:   assign tl_o.a_user    = '0;
  49: 
  50:   assign tl_o.d_ready   = 1'b1;
  51: 
  52:   assign mem_rvalid     = tl_i.d_valid && (tl_i.d_opcode == AccessAckData);
  53:   assign mem_rdata      = tl_i.d_data;
  54:   assign mem_error      = {2{tl_i.d_error}};
  55: 
  56:   // below assertion fails when TL-UL doesn't accept request in a cycle,
  57:   // which is currently not supported by sram2tlul
  58:   `ASSERT(validNotReady, tl_o.a_valid |-> tl_i.a_ready, clk_i, !rst_ni)
  59: 
  60: endmodule
  61: