../src/lowrisc_top_earlgrey_rv_plic_0.1/rtl/autogen/rv_plic_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: `include "prim_assert.sv"
   8: 
   9: module rv_plic_reg_top (
  10:   input clk_i,
  11:   input rst_ni,
  12: 
  13:   // Below Regster interface can be changed
  14:   input  tlul_pkg::tl_h2d_t tl_i,
  15:   output tlul_pkg::tl_d2h_t tl_o,
  16:   // To HW
  17:   output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
  18:   input  rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read
  19: 
  20:   // Config
  21:   input devmode_i // If 1, explicit error return for unmapped register access
  22: );
  23: 
  24:   import rv_plic_reg_pkg::* ;
  25: 
  26:   localparam int AW = 10;
  27:   localparam int DW = 32;
  28:   localparam int DBW = DW/8;                    // Byte Width
  29: 
  30:   // register signals
  31:   logic           reg_we;
  32:   logic           reg_re;
  33:   logic [AW-1:0]  reg_addr;
  34:   logic [DW-1:0]  reg_wdata;
  35:   logic [DBW-1:0] reg_be;
  36:   logic [DW-1:0]  reg_rdata;
  37:   logic           reg_error;
  38: 
  39:   logic          addrmiss, wr_err;
  40: 
  41:   logic [DW-1:0] reg_rdata_next;
  42: 
  43:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  44:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  45: 
  46:   assign tl_reg_h2d = tl_i;
  47:   assign tl_o       = tl_reg_d2h;
  48: 
  49:   tlul_adapter_reg #(
  50:     .RegAw(AW),
  51:     .RegDw(DW)
  52:   ) u_reg_if (
  53:     .clk_i,
  54:     .rst_ni,
  55: 
  56:     .tl_i (tl_reg_h2d),
  57:     .tl_o (tl_reg_d2h),
  58: 
  59:     .we_o    (reg_we),
  60:     .re_o    (reg_re),
  61:     .addr_o  (reg_addr),
  62:     .wdata_o (reg_wdata),
  63:     .be_o    (reg_be),
  64:     .rdata_i (reg_rdata),
  65:     .error_i (reg_error)
  66:   );
  67: 
  68:   assign reg_rdata = reg_rdata_next ;
  69:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  70: 
  71:   // Define SW related signals
  72:   // Format: __{wd|we|qs}
  73:   //        or _{wd|we|qs} if field == 1 or 0
  74:   logic ip0_p0_qs;
  75:   logic ip0_p1_qs;
  76:   logic ip0_p2_qs;
  77:   logic ip0_p3_qs;
  78:   logic ip0_p4_qs;
  79:   logic ip0_p5_qs;
  80:   logic ip0_p6_qs;
  81:   logic ip0_p7_qs;
  82:   logic ip0_p8_qs;
  83:   logic ip0_p9_qs;
  84:   logic ip0_p10_qs;
  85:   logic ip0_p11_qs;
  86:   logic ip0_p12_qs;
  87:   logic ip0_p13_qs;
  88:   logic ip0_p14_qs;
  89:   logic ip0_p15_qs;
  90:   logic ip0_p16_qs;
  91:   logic ip0_p17_qs;
  92:   logic ip0_p18_qs;
  93:   logic ip0_p19_qs;
  94:   logic ip0_p20_qs;
  95:   logic ip0_p21_qs;
  96:   logic ip0_p22_qs;
  97:   logic ip0_p23_qs;
  98:   logic ip0_p24_qs;
  99:   logic ip0_p25_qs;
 100:   logic ip0_p26_qs;
 101:   logic ip0_p27_qs;
 102:   logic ip0_p28_qs;
 103:   logic ip0_p29_qs;
 104:   logic ip0_p30_qs;
 105:   logic ip0_p31_qs;
 106:   logic ip1_p32_qs;
 107:   logic ip1_p33_qs;
 108:   logic ip1_p34_qs;
 109:   logic ip1_p35_qs;
 110:   logic ip1_p36_qs;
 111:   logic ip1_p37_qs;
 112:   logic ip1_p38_qs;
 113:   logic ip1_p39_qs;
 114:   logic ip1_p40_qs;
 115:   logic ip1_p41_qs;
 116:   logic ip1_p42_qs;
 117:   logic ip1_p43_qs;
 118:   logic ip1_p44_qs;
 119:   logic ip1_p45_qs;
 120:   logic ip1_p46_qs;
 121:   logic ip1_p47_qs;
 122:   logic ip1_p48_qs;
 123:   logic ip1_p49_qs;
 124:   logic ip1_p50_qs;
 125:   logic ip1_p51_qs;
 126:   logic ip1_p52_qs;
 127:   logic ip1_p53_qs;
 128:   logic ip1_p54_qs;
 129:   logic ip1_p55_qs;
 130:   logic ip1_p56_qs;
 131:   logic ip1_p57_qs;
 132:   logic ip1_p58_qs;
 133:   logic ip1_p59_qs;
 134:   logic ip1_p60_qs;
 135:   logic ip1_p61_qs;
 136:   logic ip1_p62_qs;
 137:   logic ip1_p63_qs;
 138:   logic ip2_p64_qs;
 139:   logic ip2_p65_qs;
 140:   logic ip2_p66_qs;
 141:   logic ip2_p67_qs;
 142:   logic ip2_p68_qs;
 143:   logic ip2_p69_qs;
 144:   logic ip2_p70_qs;
 145:   logic ip2_p71_qs;
 146:   logic ip2_p72_qs;
 147:   logic ip2_p73_qs;
 148:   logic ip2_p74_qs;
 149:   logic ip2_p75_qs;
 150:   logic ip2_p76_qs;
 151:   logic ip2_p77_qs;
 152:   logic ip2_p78_qs;
 153:   logic ip2_p79_qs;
 154:   logic ip2_p80_qs;
 155:   logic le0_le0_qs;
 156:   logic le0_le0_wd;
 157:   logic le0_le0_we;
 158:   logic le0_le1_qs;
 159:   logic le0_le1_wd;
 160:   logic le0_le1_we;
 161:   logic le0_le2_qs;
 162:   logic le0_le2_wd;
 163:   logic le0_le2_we;
 164:   logic le0_le3_qs;
 165:   logic le0_le3_wd;
 166:   logic le0_le3_we;
 167:   logic le0_le4_qs;
 168:   logic le0_le4_wd;
 169:   logic le0_le4_we;
 170:   logic le0_le5_qs;
 171:   logic le0_le5_wd;
 172:   logic le0_le5_we;
 173:   logic le0_le6_qs;
 174:   logic le0_le6_wd;
 175:   logic le0_le6_we;
 176:   logic le0_le7_qs;
 177:   logic le0_le7_wd;
 178:   logic le0_le7_we;
 179:   logic le0_le8_qs;
 180:   logic le0_le8_wd;
 181:   logic le0_le8_we;
 182:   logic le0_le9_qs;
 183:   logic le0_le9_wd;
 184:   logic le0_le9_we;
 185:   logic le0_le10_qs;
 186:   logic le0_le10_wd;
 187:   logic le0_le10_we;
 188:   logic le0_le11_qs;
 189:   logic le0_le11_wd;
 190:   logic le0_le11_we;
 191:   logic le0_le12_qs;
 192:   logic le0_le12_wd;
 193:   logic le0_le12_we;
 194:   logic le0_le13_qs;
 195:   logic le0_le13_wd;
 196:   logic le0_le13_we;
 197:   logic le0_le14_qs;
 198:   logic le0_le14_wd;
 199:   logic le0_le14_we;
 200:   logic le0_le15_qs;
 201:   logic le0_le15_wd;
 202:   logic le0_le15_we;
 203:   logic le0_le16_qs;
 204:   logic le0_le16_wd;
 205:   logic le0_le16_we;
 206:   logic le0_le17_qs;
 207:   logic le0_le17_wd;
 208:   logic le0_le17_we;
 209:   logic le0_le18_qs;
 210:   logic le0_le18_wd;
 211:   logic le0_le18_we;
 212:   logic le0_le19_qs;
 213:   logic le0_le19_wd;
 214:   logic le0_le19_we;
 215:   logic le0_le20_qs;
 216:   logic le0_le20_wd;
 217:   logic le0_le20_we;
 218:   logic le0_le21_qs;
 219:   logic le0_le21_wd;
 220:   logic le0_le21_we;
 221:   logic le0_le22_qs;
 222:   logic le0_le22_wd;
 223:   logic le0_le22_we;
 224:   logic le0_le23_qs;
 225:   logic le0_le23_wd;
 226:   logic le0_le23_we;
 227:   logic le0_le24_qs;
 228:   logic le0_le24_wd;
 229:   logic le0_le24_we;
 230:   logic le0_le25_qs;
 231:   logic le0_le25_wd;
 232:   logic le0_le25_we;
 233:   logic le0_le26_qs;
 234:   logic le0_le26_wd;
 235:   logic le0_le26_we;
 236:   logic le0_le27_qs;
 237:   logic le0_le27_wd;
 238:   logic le0_le27_we;
 239:   logic le0_le28_qs;
 240:   logic le0_le28_wd;
 241:   logic le0_le28_we;
 242:   logic le0_le29_qs;
 243:   logic le0_le29_wd;
 244:   logic le0_le29_we;
 245:   logic le0_le30_qs;
 246:   logic le0_le30_wd;
 247:   logic le0_le30_we;
 248:   logic le0_le31_qs;
 249:   logic le0_le31_wd;
 250:   logic le0_le31_we;
 251:   logic le1_le32_qs;
 252:   logic le1_le32_wd;
 253:   logic le1_le32_we;
 254:   logic le1_le33_qs;
 255:   logic le1_le33_wd;
 256:   logic le1_le33_we;
 257:   logic le1_le34_qs;
 258:   logic le1_le34_wd;
 259:   logic le1_le34_we;
 260:   logic le1_le35_qs;
 261:   logic le1_le35_wd;
 262:   logic le1_le35_we;
 263:   logic le1_le36_qs;
 264:   logic le1_le36_wd;
 265:   logic le1_le36_we;
 266:   logic le1_le37_qs;
 267:   logic le1_le37_wd;
 268:   logic le1_le37_we;
 269:   logic le1_le38_qs;
 270:   logic le1_le38_wd;
 271:   logic le1_le38_we;
 272:   logic le1_le39_qs;
 273:   logic le1_le39_wd;
 274:   logic le1_le39_we;
 275:   logic le1_le40_qs;
 276:   logic le1_le40_wd;
 277:   logic le1_le40_we;
 278:   logic le1_le41_qs;
 279:   logic le1_le41_wd;
 280:   logic le1_le41_we;
 281:   logic le1_le42_qs;
 282:   logic le1_le42_wd;
 283:   logic le1_le42_we;
 284:   logic le1_le43_qs;
 285:   logic le1_le43_wd;
 286:   logic le1_le43_we;
 287:   logic le1_le44_qs;
 288:   logic le1_le44_wd;
 289:   logic le1_le44_we;
 290:   logic le1_le45_qs;
 291:   logic le1_le45_wd;
 292:   logic le1_le45_we;
 293:   logic le1_le46_qs;
 294:   logic le1_le46_wd;
 295:   logic le1_le46_we;
 296:   logic le1_le47_qs;
 297:   logic le1_le47_wd;
 298:   logic le1_le47_we;
 299:   logic le1_le48_qs;
 300:   logic le1_le48_wd;
 301:   logic le1_le48_we;
 302:   logic le1_le49_qs;
 303:   logic le1_le49_wd;
 304:   logic le1_le49_we;
 305:   logic le1_le50_qs;
 306:   logic le1_le50_wd;
 307:   logic le1_le50_we;
 308:   logic le1_le51_qs;
 309:   logic le1_le51_wd;
 310:   logic le1_le51_we;
 311:   logic le1_le52_qs;
 312:   logic le1_le52_wd;
 313:   logic le1_le52_we;
 314:   logic le1_le53_qs;
 315:   logic le1_le53_wd;
 316:   logic le1_le53_we;
 317:   logic le1_le54_qs;
 318:   logic le1_le54_wd;
 319:   logic le1_le54_we;
 320:   logic le1_le55_qs;
 321:   logic le1_le55_wd;
 322:   logic le1_le55_we;
 323:   logic le1_le56_qs;
 324:   logic le1_le56_wd;
 325:   logic le1_le56_we;
 326:   logic le1_le57_qs;
 327:   logic le1_le57_wd;
 328:   logic le1_le57_we;
 329:   logic le1_le58_qs;
 330:   logic le1_le58_wd;
 331:   logic le1_le58_we;
 332:   logic le1_le59_qs;
 333:   logic le1_le59_wd;
 334:   logic le1_le59_we;
 335:   logic le1_le60_qs;
 336:   logic le1_le60_wd;
 337:   logic le1_le60_we;
 338:   logic le1_le61_qs;
 339:   logic le1_le61_wd;
 340:   logic le1_le61_we;
 341:   logic le1_le62_qs;
 342:   logic le1_le62_wd;
 343:   logic le1_le62_we;
 344:   logic le1_le63_qs;
 345:   logic le1_le63_wd;
 346:   logic le1_le63_we;
 347:   logic le2_le64_qs;
 348:   logic le2_le64_wd;
 349:   logic le2_le64_we;
 350:   logic le2_le65_qs;
 351:   logic le2_le65_wd;
 352:   logic le2_le65_we;
 353:   logic le2_le66_qs;
 354:   logic le2_le66_wd;
 355:   logic le2_le66_we;
 356:   logic le2_le67_qs;
 357:   logic le2_le67_wd;
 358:   logic le2_le67_we;
 359:   logic le2_le68_qs;
 360:   logic le2_le68_wd;
 361:   logic le2_le68_we;
 362:   logic le2_le69_qs;
 363:   logic le2_le69_wd;
 364:   logic le2_le69_we;
 365:   logic le2_le70_qs;
 366:   logic le2_le70_wd;
 367:   logic le2_le70_we;
 368:   logic le2_le71_qs;
 369:   logic le2_le71_wd;
 370:   logic le2_le71_we;
 371:   logic le2_le72_qs;
 372:   logic le2_le72_wd;
 373:   logic le2_le72_we;
 374:   logic le2_le73_qs;
 375:   logic le2_le73_wd;
 376:   logic le2_le73_we;
 377:   logic le2_le74_qs;
 378:   logic le2_le74_wd;
 379:   logic le2_le74_we;
 380:   logic le2_le75_qs;
 381:   logic le2_le75_wd;
 382:   logic le2_le75_we;
 383:   logic le2_le76_qs;
 384:   logic le2_le76_wd;
 385:   logic le2_le76_we;
 386:   logic le2_le77_qs;
 387:   logic le2_le77_wd;
 388:   logic le2_le77_we;
 389:   logic le2_le78_qs;
 390:   logic le2_le78_wd;
 391:   logic le2_le78_we;
 392:   logic le2_le79_qs;
 393:   logic le2_le79_wd;
 394:   logic le2_le79_we;
 395:   logic le2_le80_qs;
 396:   logic le2_le80_wd;
 397:   logic le2_le80_we;
 398:   logic [1:0] prio0_qs;
 399:   logic [1:0] prio0_wd;
 400:   logic prio0_we;
 401:   logic [1:0] prio1_qs;
 402:   logic [1:0] prio1_wd;
 403:   logic prio1_we;
 404:   logic [1:0] prio2_qs;
 405:   logic [1:0] prio2_wd;
 406:   logic prio2_we;
 407:   logic [1:0] prio3_qs;
 408:   logic [1:0] prio3_wd;
 409:   logic prio3_we;
 410:   logic [1:0] prio4_qs;
 411:   logic [1:0] prio4_wd;
 412:   logic prio4_we;
 413:   logic [1:0] prio5_qs;
 414:   logic [1:0] prio5_wd;
 415:   logic prio5_we;
 416:   logic [1:0] prio6_qs;
 417:   logic [1:0] prio6_wd;
 418:   logic prio6_we;
 419:   logic [1:0] prio7_qs;
 420:   logic [1:0] prio7_wd;
 421:   logic prio7_we;
 422:   logic [1:0] prio8_qs;
 423:   logic [1:0] prio8_wd;
 424:   logic prio8_we;
 425:   logic [1:0] prio9_qs;
 426:   logic [1:0] prio9_wd;
 427:   logic prio9_we;
 428:   logic [1:0] prio10_qs;
 429:   logic [1:0] prio10_wd;
 430:   logic prio10_we;
 431:   logic [1:0] prio11_qs;
 432:   logic [1:0] prio11_wd;
 433:   logic prio11_we;
 434:   logic [1:0] prio12_qs;
 435:   logic [1:0] prio12_wd;
 436:   logic prio12_we;
 437:   logic [1:0] prio13_qs;
 438:   logic [1:0] prio13_wd;
 439:   logic prio13_we;
 440:   logic [1:0] prio14_qs;
 441:   logic [1:0] prio14_wd;
 442:   logic prio14_we;
 443:   logic [1:0] prio15_qs;
 444:   logic [1:0] prio15_wd;
 445:   logic prio15_we;
 446:   logic [1:0] prio16_qs;
 447:   logic [1:0] prio16_wd;
 448:   logic prio16_we;
 449:   logic [1:0] prio17_qs;
 450:   logic [1:0] prio17_wd;
 451:   logic prio17_we;
 452:   logic [1:0] prio18_qs;
 453:   logic [1:0] prio18_wd;
 454:   logic prio18_we;
 455:   logic [1:0] prio19_qs;
 456:   logic [1:0] prio19_wd;
 457:   logic prio19_we;
 458:   logic [1:0] prio20_qs;
 459:   logic [1:0] prio20_wd;
 460:   logic prio20_we;
 461:   logic [1:0] prio21_qs;
 462:   logic [1:0] prio21_wd;
 463:   logic prio21_we;
 464:   logic [1:0] prio22_qs;
 465:   logic [1:0] prio22_wd;
 466:   logic prio22_we;
 467:   logic [1:0] prio23_qs;
 468:   logic [1:0] prio23_wd;
 469:   logic prio23_we;
 470:   logic [1:0] prio24_qs;
 471:   logic [1:0] prio24_wd;
 472:   logic prio24_we;
 473:   logic [1:0] prio25_qs;
 474:   logic [1:0] prio25_wd;
 475:   logic prio25_we;
 476:   logic [1:0] prio26_qs;
 477:   logic [1:0] prio26_wd;
 478:   logic prio26_we;
 479:   logic [1:0] prio27_qs;
 480:   logic [1:0] prio27_wd;
 481:   logic prio27_we;
 482:   logic [1:0] prio28_qs;
 483:   logic [1:0] prio28_wd;
 484:   logic prio28_we;
 485:   logic [1:0] prio29_qs;
 486:   logic [1:0] prio29_wd;
 487:   logic prio29_we;
 488:   logic [1:0] prio30_qs;
 489:   logic [1:0] prio30_wd;
 490:   logic prio30_we;
 491:   logic [1:0] prio31_qs;
 492:   logic [1:0] prio31_wd;
 493:   logic prio31_we;
 494:   logic [1:0] prio32_qs;
 495:   logic [1:0] prio32_wd;
 496:   logic prio32_we;
 497:   logic [1:0] prio33_qs;
 498:   logic [1:0] prio33_wd;
 499:   logic prio33_we;
 500:   logic [1:0] prio34_qs;
 501:   logic [1:0] prio34_wd;
 502:   logic prio34_we;
 503:   logic [1:0] prio35_qs;
 504:   logic [1:0] prio35_wd;
 505:   logic prio35_we;
 506:   logic [1:0] prio36_qs;
 507:   logic [1:0] prio36_wd;
 508:   logic prio36_we;
 509:   logic [1:0] prio37_qs;
 510:   logic [1:0] prio37_wd;
 511:   logic prio37_we;
 512:   logic [1:0] prio38_qs;
 513:   logic [1:0] prio38_wd;
 514:   logic prio38_we;
 515:   logic [1:0] prio39_qs;
 516:   logic [1:0] prio39_wd;
 517:   logic prio39_we;
 518:   logic [1:0] prio40_qs;
 519:   logic [1:0] prio40_wd;
 520:   logic prio40_we;
 521:   logic [1:0] prio41_qs;
 522:   logic [1:0] prio41_wd;
 523:   logic prio41_we;
 524:   logic [1:0] prio42_qs;
 525:   logic [1:0] prio42_wd;
 526:   logic prio42_we;
 527:   logic [1:0] prio43_qs;
 528:   logic [1:0] prio43_wd;
 529:   logic prio43_we;
 530:   logic [1:0] prio44_qs;
 531:   logic [1:0] prio44_wd;
 532:   logic prio44_we;
 533:   logic [1:0] prio45_qs;
 534:   logic [1:0] prio45_wd;
 535:   logic prio45_we;
 536:   logic [1:0] prio46_qs;
 537:   logic [1:0] prio46_wd;
 538:   logic prio46_we;
 539:   logic [1:0] prio47_qs;
 540:   logic [1:0] prio47_wd;
 541:   logic prio47_we;
 542:   logic [1:0] prio48_qs;
 543:   logic [1:0] prio48_wd;
 544:   logic prio48_we;
 545:   logic [1:0] prio49_qs;
 546:   logic [1:0] prio49_wd;
 547:   logic prio49_we;
 548:   logic [1:0] prio50_qs;
 549:   logic [1:0] prio50_wd;
 550:   logic prio50_we;
 551:   logic [1:0] prio51_qs;
 552:   logic [1:0] prio51_wd;
 553:   logic prio51_we;
 554:   logic [1:0] prio52_qs;
 555:   logic [1:0] prio52_wd;
 556:   logic prio52_we;
 557:   logic [1:0] prio53_qs;
 558:   logic [1:0] prio53_wd;
 559:   logic prio53_we;
 560:   logic [1:0] prio54_qs;
 561:   logic [1:0] prio54_wd;
 562:   logic prio54_we;
 563:   logic [1:0] prio55_qs;
 564:   logic [1:0] prio55_wd;
 565:   logic prio55_we;
 566:   logic [1:0] prio56_qs;
 567:   logic [1:0] prio56_wd;
 568:   logic prio56_we;
 569:   logic [1:0] prio57_qs;
 570:   logic [1:0] prio57_wd;
 571:   logic prio57_we;
 572:   logic [1:0] prio58_qs;
 573:   logic [1:0] prio58_wd;
 574:   logic prio58_we;
 575:   logic [1:0] prio59_qs;
 576:   logic [1:0] prio59_wd;
 577:   logic prio59_we;
 578:   logic [1:0] prio60_qs;
 579:   logic [1:0] prio60_wd;
 580:   logic prio60_we;
 581:   logic [1:0] prio61_qs;
 582:   logic [1:0] prio61_wd;
 583:   logic prio61_we;
 584:   logic [1:0] prio62_qs;
 585:   logic [1:0] prio62_wd;
 586:   logic prio62_we;
 587:   logic [1:0] prio63_qs;
 588:   logic [1:0] prio63_wd;
 589:   logic prio63_we;
 590:   logic [1:0] prio64_qs;
 591:   logic [1:0] prio64_wd;
 592:   logic prio64_we;
 593:   logic [1:0] prio65_qs;
 594:   logic [1:0] prio65_wd;
 595:   logic prio65_we;
 596:   logic [1:0] prio66_qs;
 597:   logic [1:0] prio66_wd;
 598:   logic prio66_we;
 599:   logic [1:0] prio67_qs;
 600:   logic [1:0] prio67_wd;
 601:   logic prio67_we;
 602:   logic [1:0] prio68_qs;
 603:   logic [1:0] prio68_wd;
 604:   logic prio68_we;
 605:   logic [1:0] prio69_qs;
 606:   logic [1:0] prio69_wd;
 607:   logic prio69_we;
 608:   logic [1:0] prio70_qs;
 609:   logic [1:0] prio70_wd;
 610:   logic prio70_we;
 611:   logic [1:0] prio71_qs;
 612:   logic [1:0] prio71_wd;
 613:   logic prio71_we;
 614:   logic [1:0] prio72_qs;
 615:   logic [1:0] prio72_wd;
 616:   logic prio72_we;
 617:   logic [1:0] prio73_qs;
 618:   logic [1:0] prio73_wd;
 619:   logic prio73_we;
 620:   logic [1:0] prio74_qs;
 621:   logic [1:0] prio74_wd;
 622:   logic prio74_we;
 623:   logic [1:0] prio75_qs;
 624:   logic [1:0] prio75_wd;
 625:   logic prio75_we;
 626:   logic [1:0] prio76_qs;
 627:   logic [1:0] prio76_wd;
 628:   logic prio76_we;
 629:   logic [1:0] prio77_qs;
 630:   logic [1:0] prio77_wd;
 631:   logic prio77_we;
 632:   logic [1:0] prio78_qs;
 633:   logic [1:0] prio78_wd;
 634:   logic prio78_we;
 635:   logic [1:0] prio79_qs;
 636:   logic [1:0] prio79_wd;
 637:   logic prio79_we;
 638:   logic [1:0] prio80_qs;
 639:   logic [1:0] prio80_wd;
 640:   logic prio80_we;
 641:   logic ie00_e0_qs;
 642:   logic ie00_e0_wd;
 643:   logic ie00_e0_we;
 644:   logic ie00_e1_qs;
 645:   logic ie00_e1_wd;
 646:   logic ie00_e1_we;
 647:   logic ie00_e2_qs;
 648:   logic ie00_e2_wd;
 649:   logic ie00_e2_we;
 650:   logic ie00_e3_qs;
 651:   logic ie00_e3_wd;
 652:   logic ie00_e3_we;
 653:   logic ie00_e4_qs;
 654:   logic ie00_e4_wd;
 655:   logic ie00_e4_we;
 656:   logic ie00_e5_qs;
 657:   logic ie00_e5_wd;
 658:   logic ie00_e5_we;
 659:   logic ie00_e6_qs;
 660:   logic ie00_e6_wd;
 661:   logic ie00_e6_we;
 662:   logic ie00_e7_qs;
 663:   logic ie00_e7_wd;
 664:   logic ie00_e7_we;
 665:   logic ie00_e8_qs;
 666:   logic ie00_e8_wd;
 667:   logic ie00_e8_we;
 668:   logic ie00_e9_qs;
 669:   logic ie00_e9_wd;
 670:   logic ie00_e9_we;
 671:   logic ie00_e10_qs;
 672:   logic ie00_e10_wd;
 673:   logic ie00_e10_we;
 674:   logic ie00_e11_qs;
 675:   logic ie00_e11_wd;
 676:   logic ie00_e11_we;
 677:   logic ie00_e12_qs;
 678:   logic ie00_e12_wd;
 679:   logic ie00_e12_we;
 680:   logic ie00_e13_qs;
 681:   logic ie00_e13_wd;
 682:   logic ie00_e13_we;
 683:   logic ie00_e14_qs;
 684:   logic ie00_e14_wd;
 685:   logic ie00_e14_we;
 686:   logic ie00_e15_qs;
 687:   logic ie00_e15_wd;
 688:   logic ie00_e15_we;
 689:   logic ie00_e16_qs;
 690:   logic ie00_e16_wd;
 691:   logic ie00_e16_we;
 692:   logic ie00_e17_qs;
 693:   logic ie00_e17_wd;
 694:   logic ie00_e17_we;
 695:   logic ie00_e18_qs;
 696:   logic ie00_e18_wd;
 697:   logic ie00_e18_we;
 698:   logic ie00_e19_qs;
 699:   logic ie00_e19_wd;
 700:   logic ie00_e19_we;
 701:   logic ie00_e20_qs;
 702:   logic ie00_e20_wd;
 703:   logic ie00_e20_we;
 704:   logic ie00_e21_qs;
 705:   logic ie00_e21_wd;
 706:   logic ie00_e21_we;
 707:   logic ie00_e22_qs;
 708:   logic ie00_e22_wd;
 709:   logic ie00_e22_we;
 710:   logic ie00_e23_qs;
 711:   logic ie00_e23_wd;
 712:   logic ie00_e23_we;
 713:   logic ie00_e24_qs;
 714:   logic ie00_e24_wd;
 715:   logic ie00_e24_we;
 716:   logic ie00_e25_qs;
 717:   logic ie00_e25_wd;
 718:   logic ie00_e25_we;
 719:   logic ie00_e26_qs;
 720:   logic ie00_e26_wd;
 721:   logic ie00_e26_we;
 722:   logic ie00_e27_qs;
 723:   logic ie00_e27_wd;
 724:   logic ie00_e27_we;
 725:   logic ie00_e28_qs;
 726:   logic ie00_e28_wd;
 727:   logic ie00_e28_we;
 728:   logic ie00_e29_qs;
 729:   logic ie00_e29_wd;
 730:   logic ie00_e29_we;
 731:   logic ie00_e30_qs;
 732:   logic ie00_e30_wd;
 733:   logic ie00_e30_we;
 734:   logic ie00_e31_qs;
 735:   logic ie00_e31_wd;
 736:   logic ie00_e31_we;
 737:   logic ie01_e32_qs;
 738:   logic ie01_e32_wd;
 739:   logic ie01_e32_we;
 740:   logic ie01_e33_qs;
 741:   logic ie01_e33_wd;
 742:   logic ie01_e33_we;
 743:   logic ie01_e34_qs;
 744:   logic ie01_e34_wd;
 745:   logic ie01_e34_we;
 746:   logic ie01_e35_qs;
 747:   logic ie01_e35_wd;
 748:   logic ie01_e35_we;
 749:   logic ie01_e36_qs;
 750:   logic ie01_e36_wd;
 751:   logic ie01_e36_we;
 752:   logic ie01_e37_qs;
 753:   logic ie01_e37_wd;
 754:   logic ie01_e37_we;
 755:   logic ie01_e38_qs;
 756:   logic ie01_e38_wd;
 757:   logic ie01_e38_we;
 758:   logic ie01_e39_qs;
 759:   logic ie01_e39_wd;
 760:   logic ie01_e39_we;
 761:   logic ie01_e40_qs;
 762:   logic ie01_e40_wd;
 763:   logic ie01_e40_we;
 764:   logic ie01_e41_qs;
 765:   logic ie01_e41_wd;
 766:   logic ie01_e41_we;
 767:   logic ie01_e42_qs;
 768:   logic ie01_e42_wd;
 769:   logic ie01_e42_we;
 770:   logic ie01_e43_qs;
 771:   logic ie01_e43_wd;
 772:   logic ie01_e43_we;
 773:   logic ie01_e44_qs;
 774:   logic ie01_e44_wd;
 775:   logic ie01_e44_we;
 776:   logic ie01_e45_qs;
 777:   logic ie01_e45_wd;
 778:   logic ie01_e45_we;
 779:   logic ie01_e46_qs;
 780:   logic ie01_e46_wd;
 781:   logic ie01_e46_we;
 782:   logic ie01_e47_qs;
 783:   logic ie01_e47_wd;
 784:   logic ie01_e47_we;
 785:   logic ie01_e48_qs;
 786:   logic ie01_e48_wd;
 787:   logic ie01_e48_we;
 788:   logic ie01_e49_qs;
 789:   logic ie01_e49_wd;
 790:   logic ie01_e49_we;
 791:   logic ie01_e50_qs;
 792:   logic ie01_e50_wd;
 793:   logic ie01_e50_we;
 794:   logic ie01_e51_qs;
 795:   logic ie01_e51_wd;
 796:   logic ie01_e51_we;
 797:   logic ie01_e52_qs;
 798:   logic ie01_e52_wd;
 799:   logic ie01_e52_we;
 800:   logic ie01_e53_qs;
 801:   logic ie01_e53_wd;
 802:   logic ie01_e53_we;
 803:   logic ie01_e54_qs;
 804:   logic ie01_e54_wd;
 805:   logic ie01_e54_we;
 806:   logic ie01_e55_qs;
 807:   logic ie01_e55_wd;
 808:   logic ie01_e55_we;
 809:   logic ie01_e56_qs;
 810:   logic ie01_e56_wd;
 811:   logic ie01_e56_we;
 812:   logic ie01_e57_qs;
 813:   logic ie01_e57_wd;
 814:   logic ie01_e57_we;
 815:   logic ie01_e58_qs;
 816:   logic ie01_e58_wd;
 817:   logic ie01_e58_we;
 818:   logic ie01_e59_qs;
 819:   logic ie01_e59_wd;
 820:   logic ie01_e59_we;
 821:   logic ie01_e60_qs;
 822:   logic ie01_e60_wd;
 823:   logic ie01_e60_we;
 824:   logic ie01_e61_qs;
 825:   logic ie01_e61_wd;
 826:   logic ie01_e61_we;
 827:   logic ie01_e62_qs;
 828:   logic ie01_e62_wd;
 829:   logic ie01_e62_we;
 830:   logic ie01_e63_qs;
 831:   logic ie01_e63_wd;
 832:   logic ie01_e63_we;
 833:   logic ie02_e64_qs;
 834:   logic ie02_e64_wd;
 835:   logic ie02_e64_we;
 836:   logic ie02_e65_qs;
 837:   logic ie02_e65_wd;
 838:   logic ie02_e65_we;
 839:   logic ie02_e66_qs;
 840:   logic ie02_e66_wd;
 841:   logic ie02_e66_we;
 842:   logic ie02_e67_qs;
 843:   logic ie02_e67_wd;
 844:   logic ie02_e67_we;
 845:   logic ie02_e68_qs;
 846:   logic ie02_e68_wd;
 847:   logic ie02_e68_we;
 848:   logic ie02_e69_qs;
 849:   logic ie02_e69_wd;
 850:   logic ie02_e69_we;
 851:   logic ie02_e70_qs;
 852:   logic ie02_e70_wd;
 853:   logic ie02_e70_we;
 854:   logic ie02_e71_qs;
 855:   logic ie02_e71_wd;
 856:   logic ie02_e71_we;
 857:   logic ie02_e72_qs;
 858:   logic ie02_e72_wd;
 859:   logic ie02_e72_we;
 860:   logic ie02_e73_qs;
 861:   logic ie02_e73_wd;
 862:   logic ie02_e73_we;
 863:   logic ie02_e74_qs;
 864:   logic ie02_e74_wd;
 865:   logic ie02_e74_we;
 866:   logic ie02_e75_qs;
 867:   logic ie02_e75_wd;
 868:   logic ie02_e75_we;
 869:   logic ie02_e76_qs;
 870:   logic ie02_e76_wd;
 871:   logic ie02_e76_we;
 872:   logic ie02_e77_qs;
 873:   logic ie02_e77_wd;
 874:   logic ie02_e77_we;
 875:   logic ie02_e78_qs;
 876:   logic ie02_e78_wd;
 877:   logic ie02_e78_we;
 878:   logic ie02_e79_qs;
 879:   logic ie02_e79_wd;
 880:   logic ie02_e79_we;
 881:   logic ie02_e80_qs;
 882:   logic ie02_e80_wd;
 883:   logic ie02_e80_we;
 884:   logic [1:0] threshold0_qs;
 885:   logic [1:0] threshold0_wd;
 886:   logic threshold0_we;
 887:   logic [6:0] cc0_qs;
 888:   logic [6:0] cc0_wd;
 889:   logic cc0_we;
 890:   logic cc0_re;
 891:   logic msip0_qs;
 892:   logic msip0_wd;
 893:   logic msip0_we;
 894: 
 895:   // Register instances
 896: 
 897:   // Subregister 0 of Multireg ip
 898:   // R[ip0]: V(False)
 899: 
 900:   // F[p0]: 0:0
 901:   prim_subreg #(
 902:     .DW      (1),
 903:     .SWACCESS("RO"),
 904:     .RESVAL  (1'h0)
 905:   ) u_ip0_p0 (
 906:     .clk_i   (clk_i    ),
 907:     .rst_ni  (rst_ni  ),
 908: 
 909:     .we     (1'b0),
 910:     .wd     ('0  ),
 911: 
 912:     // from internal hardware
 913:     .de     (hw2reg.ip[0].de),
 914:     .d      (hw2reg.ip[0].d ),
 915: 
 916:     // to internal hardware
 917:     .qe     (),
 918:     .q      (),
 919: 
 920:     // to register interface (read)
 921:     .qs     (ip0_p0_qs)
 922:   );
 923: 
 924: 
 925:   // F[p1]: 1:1
 926:   prim_subreg #(
 927:     .DW      (1),
 928:     .SWACCESS("RO"),
 929:     .RESVAL  (1'h0)
 930:   ) u_ip0_p1 (
 931:     .clk_i   (clk_i    ),
 932:     .rst_ni  (rst_ni  ),
 933: 
 934:     .we     (1'b0),
 935:     .wd     ('0  ),
 936: 
 937:     // from internal hardware
 938:     .de     (hw2reg.ip[1].de),
 939:     .d      (hw2reg.ip[1].d ),
 940: 
 941:     // to internal hardware
 942:     .qe     (),
 943:     .q      (),
 944: 
 945:     // to register interface (read)
 946:     .qs     (ip0_p1_qs)
 947:   );
 948: 
 949: 
 950:   // F[p2]: 2:2
 951:   prim_subreg #(
 952:     .DW      (1),
 953:     .SWACCESS("RO"),
 954:     .RESVAL  (1'h0)
 955:   ) u_ip0_p2 (
 956:     .clk_i   (clk_i    ),
 957:     .rst_ni  (rst_ni  ),
 958: 
 959:     .we     (1'b0),
 960:     .wd     ('0  ),
 961: 
 962:     // from internal hardware
 963:     .de     (hw2reg.ip[2].de),
 964:     .d      (hw2reg.ip[2].d ),
 965: 
 966:     // to internal hardware
 967:     .qe     (),
 968:     .q      (),
 969: 
 970:     // to register interface (read)
 971:     .qs     (ip0_p2_qs)
 972:   );
 973: 
 974: 
 975:   // F[p3]: 3:3
 976:   prim_subreg #(
 977:     .DW      (1),
 978:     .SWACCESS("RO"),
 979:     .RESVAL  (1'h0)
 980:   ) u_ip0_p3 (
 981:     .clk_i   (clk_i    ),
 982:     .rst_ni  (rst_ni  ),
 983: 
 984:     .we     (1'b0),
 985:     .wd     ('0  ),
 986: 
 987:     // from internal hardware
 988:     .de     (hw2reg.ip[3].de),
 989:     .d      (hw2reg.ip[3].d ),
 990: 
 991:     // to internal hardware
 992:     .qe     (),
 993:     .q      (),
 994: 
 995:     // to register interface (read)
 996:     .qs     (ip0_p3_qs)
 997:   );
 998: 
 999: 
1000:   // F[p4]: 4:4
1001:   prim_subreg #(
1002:     .DW      (1),
1003:     .SWACCESS("RO"),
1004:     .RESVAL  (1'h0)
1005:   ) u_ip0_p4 (
1006:     .clk_i   (clk_i    ),
1007:     .rst_ni  (rst_ni  ),
1008: 
1009:     .we     (1'b0),
1010:     .wd     ('0  ),
1011: 
1012:     // from internal hardware
1013:     .de     (hw2reg.ip[4].de),
1014:     .d      (hw2reg.ip[4].d ),
1015: 
1016:     // to internal hardware
1017:     .qe     (),
1018:     .q      (),
1019: 
1020:     // to register interface (read)
1021:     .qs     (ip0_p4_qs)
1022:   );
1023: 
1024: 
1025:   // F[p5]: 5:5
1026:   prim_subreg #(
1027:     .DW      (1),
1028:     .SWACCESS("RO"),
1029:     .RESVAL  (1'h0)
1030:   ) u_ip0_p5 (
1031:     .clk_i   (clk_i    ),
1032:     .rst_ni  (rst_ni  ),
1033: 
1034:     .we     (1'b0),
1035:     .wd     ('0  ),
1036: 
1037:     // from internal hardware
1038:     .de     (hw2reg.ip[5].de),
1039:     .d      (hw2reg.ip[5].d ),
1040: 
1041:     // to internal hardware
1042:     .qe     (),
1043:     .q      (),
1044: 
1045:     // to register interface (read)
1046:     .qs     (ip0_p5_qs)
1047:   );
1048: 
1049: 
1050:   // F[p6]: 6:6
1051:   prim_subreg #(
1052:     .DW      (1),
1053:     .SWACCESS("RO"),
1054:     .RESVAL  (1'h0)
1055:   ) u_ip0_p6 (
1056:     .clk_i   (clk_i    ),
1057:     .rst_ni  (rst_ni  ),
1058: 
1059:     .we     (1'b0),
1060:     .wd     ('0  ),
1061: 
1062:     // from internal hardware
1063:     .de     (hw2reg.ip[6].de),
1064:     .d      (hw2reg.ip[6].d ),
1065: 
1066:     // to internal hardware
1067:     .qe     (),
1068:     .q      (),
1069: 
1070:     // to register interface (read)
1071:     .qs     (ip0_p6_qs)
1072:   );
1073: 
1074: 
1075:   // F[p7]: 7:7
1076:   prim_subreg #(
1077:     .DW      (1),
1078:     .SWACCESS("RO"),
1079:     .RESVAL  (1'h0)
1080:   ) u_ip0_p7 (
1081:     .clk_i   (clk_i    ),
1082:     .rst_ni  (rst_ni  ),
1083: 
1084:     .we     (1'b0),
1085:     .wd     ('0  ),
1086: 
1087:     // from internal hardware
1088:     .de     (hw2reg.ip[7].de),
1089:     .d      (hw2reg.ip[7].d ),
1090: 
1091:     // to internal hardware
1092:     .qe     (),
1093:     .q      (),
1094: 
1095:     // to register interface (read)
1096:     .qs     (ip0_p7_qs)
1097:   );
1098: 
1099: 
1100:   // F[p8]: 8:8
1101:   prim_subreg #(
1102:     .DW      (1),
1103:     .SWACCESS("RO"),
1104:     .RESVAL  (1'h0)
1105:   ) u_ip0_p8 (
1106:     .clk_i   (clk_i    ),
1107:     .rst_ni  (rst_ni  ),
1108: 
1109:     .we     (1'b0),
1110:     .wd     ('0  ),
1111: 
1112:     // from internal hardware
1113:     .de     (hw2reg.ip[8].de),
1114:     .d      (hw2reg.ip[8].d ),
1115: 
1116:     // to internal hardware
1117:     .qe     (),
1118:     .q      (),
1119: 
1120:     // to register interface (read)
1121:     .qs     (ip0_p8_qs)
1122:   );
1123: 
1124: 
1125:   // F[p9]: 9:9
1126:   prim_subreg #(
1127:     .DW      (1),
1128:     .SWACCESS("RO"),
1129:     .RESVAL  (1'h0)
1130:   ) u_ip0_p9 (
1131:     .clk_i   (clk_i    ),
1132:     .rst_ni  (rst_ni  ),
1133: 
1134:     .we     (1'b0),
1135:     .wd     ('0  ),
1136: 
1137:     // from internal hardware
1138:     .de     (hw2reg.ip[9].de),
1139:     .d      (hw2reg.ip[9].d ),
1140: 
1141:     // to internal hardware
1142:     .qe     (),
1143:     .q      (),
1144: 
1145:     // to register interface (read)
1146:     .qs     (ip0_p9_qs)
1147:   );
1148: 
1149: 
1150:   // F[p10]: 10:10
1151:   prim_subreg #(
1152:     .DW      (1),
1153:     .SWACCESS("RO"),
1154:     .RESVAL  (1'h0)
1155:   ) u_ip0_p10 (
1156:     .clk_i   (clk_i    ),
1157:     .rst_ni  (rst_ni  ),
1158: 
1159:     .we     (1'b0),
1160:     .wd     ('0  ),
1161: 
1162:     // from internal hardware
1163:     .de     (hw2reg.ip[10].de),
1164:     .d      (hw2reg.ip[10].d ),
1165: 
1166:     // to internal hardware
1167:     .qe     (),
1168:     .q      (),
1169: 
1170:     // to register interface (read)
1171:     .qs     (ip0_p10_qs)
1172:   );
1173: 
1174: 
1175:   // F[p11]: 11:11
1176:   prim_subreg #(
1177:     .DW      (1),
1178:     .SWACCESS("RO"),
1179:     .RESVAL  (1'h0)
1180:   ) u_ip0_p11 (
1181:     .clk_i   (clk_i    ),
1182:     .rst_ni  (rst_ni  ),
1183: 
1184:     .we     (1'b0),
1185:     .wd     ('0  ),
1186: 
1187:     // from internal hardware
1188:     .de     (hw2reg.ip[11].de),
1189:     .d      (hw2reg.ip[11].d ),
1190: 
1191:     // to internal hardware
1192:     .qe     (),
1193:     .q      (),
1194: 
1195:     // to register interface (read)
1196:     .qs     (ip0_p11_qs)
1197:   );
1198: 
1199: 
1200:   // F[p12]: 12:12
1201:   prim_subreg #(
1202:     .DW      (1),
1203:     .SWACCESS("RO"),
1204:     .RESVAL  (1'h0)
1205:   ) u_ip0_p12 (
1206:     .clk_i   (clk_i    ),
1207:     .rst_ni  (rst_ni  ),
1208: 
1209:     .we     (1'b0),
1210:     .wd     ('0  ),
1211: 
1212:     // from internal hardware
1213:     .de     (hw2reg.ip[12].de),
1214:     .d      (hw2reg.ip[12].d ),
1215: 
1216:     // to internal hardware
1217:     .qe     (),
1218:     .q      (),
1219: 
1220:     // to register interface (read)
1221:     .qs     (ip0_p12_qs)
1222:   );
1223: 
1224: 
1225:   // F[p13]: 13:13
1226:   prim_subreg #(
1227:     .DW      (1),
1228:     .SWACCESS("RO"),
1229:     .RESVAL  (1'h0)
1230:   ) u_ip0_p13 (
1231:     .clk_i   (clk_i    ),
1232:     .rst_ni  (rst_ni  ),
1233: 
1234:     .we     (1'b0),
1235:     .wd     ('0  ),
1236: 
1237:     // from internal hardware
1238:     .de     (hw2reg.ip[13].de),
1239:     .d      (hw2reg.ip[13].d ),
1240: 
1241:     // to internal hardware
1242:     .qe     (),
1243:     .q      (),
1244: 
1245:     // to register interface (read)
1246:     .qs     (ip0_p13_qs)
1247:   );
1248: 
1249: 
1250:   // F[p14]: 14:14
1251:   prim_subreg #(
1252:     .DW      (1),
1253:     .SWACCESS("RO"),
1254:     .RESVAL  (1'h0)
1255:   ) u_ip0_p14 (
1256:     .clk_i   (clk_i    ),
1257:     .rst_ni  (rst_ni  ),
1258: 
1259:     .we     (1'b0),
1260:     .wd     ('0  ),
1261: 
1262:     // from internal hardware
1263:     .de     (hw2reg.ip[14].de),
1264:     .d      (hw2reg.ip[14].d ),
1265: 
1266:     // to internal hardware
1267:     .qe     (),
1268:     .q      (),
1269: 
1270:     // to register interface (read)
1271:     .qs     (ip0_p14_qs)
1272:   );
1273: 
1274: 
1275:   // F[p15]: 15:15
1276:   prim_subreg #(
1277:     .DW      (1),
1278:     .SWACCESS("RO"),
1279:     .RESVAL  (1'h0)
1280:   ) u_ip0_p15 (
1281:     .clk_i   (clk_i    ),
1282:     .rst_ni  (rst_ni  ),
1283: 
1284:     .we     (1'b0),
1285:     .wd     ('0  ),
1286: 
1287:     // from internal hardware
1288:     .de     (hw2reg.ip[15].de),
1289:     .d      (hw2reg.ip[15].d ),
1290: 
1291:     // to internal hardware
1292:     .qe     (),
1293:     .q      (),
1294: 
1295:     // to register interface (read)
1296:     .qs     (ip0_p15_qs)
1297:   );
1298: 
1299: 
1300:   // F[p16]: 16:16
1301:   prim_subreg #(
1302:     .DW      (1),
1303:     .SWACCESS("RO"),
1304:     .RESVAL  (1'h0)
1305:   ) u_ip0_p16 (
1306:     .clk_i   (clk_i    ),
1307:     .rst_ni  (rst_ni  ),
1308: 
1309:     .we     (1'b0),
1310:     .wd     ('0  ),
1311: 
1312:     // from internal hardware
1313:     .de     (hw2reg.ip[16].de),
1314:     .d      (hw2reg.ip[16].d ),
1315: 
1316:     // to internal hardware
1317:     .qe     (),
1318:     .q      (),
1319: 
1320:     // to register interface (read)
1321:     .qs     (ip0_p16_qs)
1322:   );
1323: 
1324: 
1325:   // F[p17]: 17:17
1326:   prim_subreg #(
1327:     .DW      (1),
1328:     .SWACCESS("RO"),
1329:     .RESVAL  (1'h0)
1330:   ) u_ip0_p17 (
1331:     .clk_i   (clk_i    ),
1332:     .rst_ni  (rst_ni  ),
1333: 
1334:     .we     (1'b0),
1335:     .wd     ('0  ),
1336: 
1337:     // from internal hardware
1338:     .de     (hw2reg.ip[17].de),
1339:     .d      (hw2reg.ip[17].d ),
1340: 
1341:     // to internal hardware
1342:     .qe     (),
1343:     .q      (),
1344: 
1345:     // to register interface (read)
1346:     .qs     (ip0_p17_qs)
1347:   );
1348: 
1349: 
1350:   // F[p18]: 18:18
1351:   prim_subreg #(
1352:     .DW      (1),
1353:     .SWACCESS("RO"),
1354:     .RESVAL  (1'h0)
1355:   ) u_ip0_p18 (
1356:     .clk_i   (clk_i    ),
1357:     .rst_ni  (rst_ni  ),
1358: 
1359:     .we     (1'b0),
1360:     .wd     ('0  ),
1361: 
1362:     // from internal hardware
1363:     .de     (hw2reg.ip[18].de),
1364:     .d      (hw2reg.ip[18].d ),
1365: 
1366:     // to internal hardware
1367:     .qe     (),
1368:     .q      (),
1369: 
1370:     // to register interface (read)
1371:     .qs     (ip0_p18_qs)
1372:   );
1373: 
1374: 
1375:   // F[p19]: 19:19
1376:   prim_subreg #(
1377:     .DW      (1),
1378:     .SWACCESS("RO"),
1379:     .RESVAL  (1'h0)
1380:   ) u_ip0_p19 (
1381:     .clk_i   (clk_i    ),
1382:     .rst_ni  (rst_ni  ),
1383: 
1384:     .we     (1'b0),
1385:     .wd     ('0  ),
1386: 
1387:     // from internal hardware
1388:     .de     (hw2reg.ip[19].de),
1389:     .d      (hw2reg.ip[19].d ),
1390: 
1391:     // to internal hardware
1392:     .qe     (),
1393:     .q      (),
1394: 
1395:     // to register interface (read)
1396:     .qs     (ip0_p19_qs)
1397:   );
1398: 
1399: 
1400:   // F[p20]: 20:20
1401:   prim_subreg #(
1402:     .DW      (1),
1403:     .SWACCESS("RO"),
1404:     .RESVAL  (1'h0)
1405:   ) u_ip0_p20 (
1406:     .clk_i   (clk_i    ),
1407:     .rst_ni  (rst_ni  ),
1408: 
1409:     .we     (1'b0),
1410:     .wd     ('0  ),
1411: 
1412:     // from internal hardware
1413:     .de     (hw2reg.ip[20].de),
1414:     .d      (hw2reg.ip[20].d ),
1415: 
1416:     // to internal hardware
1417:     .qe     (),
1418:     .q      (),
1419: 
1420:     // to register interface (read)
1421:     .qs     (ip0_p20_qs)
1422:   );
1423: 
1424: 
1425:   // F[p21]: 21:21
1426:   prim_subreg #(
1427:     .DW      (1),
1428:     .SWACCESS("RO"),
1429:     .RESVAL  (1'h0)
1430:   ) u_ip0_p21 (
1431:     .clk_i   (clk_i    ),
1432:     .rst_ni  (rst_ni  ),
1433: 
1434:     .we     (1'b0),
1435:     .wd     ('0  ),
1436: 
1437:     // from internal hardware
1438:     .de     (hw2reg.ip[21].de),
1439:     .d      (hw2reg.ip[21].d ),
1440: 
1441:     // to internal hardware
1442:     .qe     (),
1443:     .q      (),
1444: 
1445:     // to register interface (read)
1446:     .qs     (ip0_p21_qs)
1447:   );
1448: 
1449: 
1450:   // F[p22]: 22:22
1451:   prim_subreg #(
1452:     .DW      (1),
1453:     .SWACCESS("RO"),
1454:     .RESVAL  (1'h0)
1455:   ) u_ip0_p22 (
1456:     .clk_i   (clk_i    ),
1457:     .rst_ni  (rst_ni  ),
1458: 
1459:     .we     (1'b0),
1460:     .wd     ('0  ),
1461: 
1462:     // from internal hardware
1463:     .de     (hw2reg.ip[22].de),
1464:     .d      (hw2reg.ip[22].d ),
1465: 
1466:     // to internal hardware
1467:     .qe     (),
1468:     .q      (),
1469: 
1470:     // to register interface (read)
1471:     .qs     (ip0_p22_qs)
1472:   );
1473: 
1474: 
1475:   // F[p23]: 23:23
1476:   prim_subreg #(
1477:     .DW      (1),
1478:     .SWACCESS("RO"),
1479:     .RESVAL  (1'h0)
1480:   ) u_ip0_p23 (
1481:     .clk_i   (clk_i    ),
1482:     .rst_ni  (rst_ni  ),
1483: 
1484:     .we     (1'b0),
1485:     .wd     ('0  ),
1486: 
1487:     // from internal hardware
1488:     .de     (hw2reg.ip[23].de),
1489:     .d      (hw2reg.ip[23].d ),
1490: 
1491:     // to internal hardware
1492:     .qe     (),
1493:     .q      (),
1494: 
1495:     // to register interface (read)
1496:     .qs     (ip0_p23_qs)
1497:   );
1498: 
1499: 
1500:   // F[p24]: 24:24
1501:   prim_subreg #(
1502:     .DW      (1),
1503:     .SWACCESS("RO"),
1504:     .RESVAL  (1'h0)
1505:   ) u_ip0_p24 (
1506:     .clk_i   (clk_i    ),
1507:     .rst_ni  (rst_ni  ),
1508: 
1509:     .we     (1'b0),
1510:     .wd     ('0  ),
1511: 
1512:     // from internal hardware
1513:     .de     (hw2reg.ip[24].de),
1514:     .d      (hw2reg.ip[24].d ),
1515: 
1516:     // to internal hardware
1517:     .qe     (),
1518:     .q      (),
1519: 
1520:     // to register interface (read)
1521:     .qs     (ip0_p24_qs)
1522:   );
1523: 
1524: 
1525:   // F[p25]: 25:25
1526:   prim_subreg #(
1527:     .DW      (1),
1528:     .SWACCESS("RO"),
1529:     .RESVAL  (1'h0)
1530:   ) u_ip0_p25 (
1531:     .clk_i   (clk_i    ),
1532:     .rst_ni  (rst_ni  ),
1533: 
1534:     .we     (1'b0),
1535:     .wd     ('0  ),
1536: 
1537:     // from internal hardware
1538:     .de     (hw2reg.ip[25].de),
1539:     .d      (hw2reg.ip[25].d ),
1540: 
1541:     // to internal hardware
1542:     .qe     (),
1543:     .q      (),
1544: 
1545:     // to register interface (read)
1546:     .qs     (ip0_p25_qs)
1547:   );
1548: 
1549: 
1550:   // F[p26]: 26:26
1551:   prim_subreg #(
1552:     .DW      (1),
1553:     .SWACCESS("RO"),
1554:     .RESVAL  (1'h0)
1555:   ) u_ip0_p26 (
1556:     .clk_i   (clk_i    ),
1557:     .rst_ni  (rst_ni  ),
1558: 
1559:     .we     (1'b0),
1560:     .wd     ('0  ),
1561: 
1562:     // from internal hardware
1563:     .de     (hw2reg.ip[26].de),
1564:     .d      (hw2reg.ip[26].d ),
1565: 
1566:     // to internal hardware
1567:     .qe     (),
1568:     .q      (),
1569: 
1570:     // to register interface (read)
1571:     .qs     (ip0_p26_qs)
1572:   );
1573: 
1574: 
1575:   // F[p27]: 27:27
1576:   prim_subreg #(
1577:     .DW      (1),
1578:     .SWACCESS("RO"),
1579:     .RESVAL  (1'h0)
1580:   ) u_ip0_p27 (
1581:     .clk_i   (clk_i    ),
1582:     .rst_ni  (rst_ni  ),
1583: 
1584:     .we     (1'b0),
1585:     .wd     ('0  ),
1586: 
1587:     // from internal hardware
1588:     .de     (hw2reg.ip[27].de),
1589:     .d      (hw2reg.ip[27].d ),
1590: 
1591:     // to internal hardware
1592:     .qe     (),
1593:     .q      (),
1594: 
1595:     // to register interface (read)
1596:     .qs     (ip0_p27_qs)
1597:   );
1598: 
1599: 
1600:   // F[p28]: 28:28
1601:   prim_subreg #(
1602:     .DW      (1),
1603:     .SWACCESS("RO"),
1604:     .RESVAL  (1'h0)
1605:   ) u_ip0_p28 (
1606:     .clk_i   (clk_i    ),
1607:     .rst_ni  (rst_ni  ),
1608: 
1609:     .we     (1'b0),
1610:     .wd     ('0  ),
1611: 
1612:     // from internal hardware
1613:     .de     (hw2reg.ip[28].de),
1614:     .d      (hw2reg.ip[28].d ),
1615: 
1616:     // to internal hardware
1617:     .qe     (),
1618:     .q      (),
1619: 
1620:     // to register interface (read)
1621:     .qs     (ip0_p28_qs)
1622:   );
1623: 
1624: 
1625:   // F[p29]: 29:29
1626:   prim_subreg #(
1627:     .DW      (1),
1628:     .SWACCESS("RO"),
1629:     .RESVAL  (1'h0)
1630:   ) u_ip0_p29 (
1631:     .clk_i   (clk_i    ),
1632:     .rst_ni  (rst_ni  ),
1633: 
1634:     .we     (1'b0),
1635:     .wd     ('0  ),
1636: 
1637:     // from internal hardware
1638:     .de     (hw2reg.ip[29].de),
1639:     .d      (hw2reg.ip[29].d ),
1640: 
1641:     // to internal hardware
1642:     .qe     (),
1643:     .q      (),
1644: 
1645:     // to register interface (read)
1646:     .qs     (ip0_p29_qs)
1647:   );
1648: 
1649: 
1650:   // F[p30]: 30:30
1651:   prim_subreg #(
1652:     .DW      (1),
1653:     .SWACCESS("RO"),
1654:     .RESVAL  (1'h0)
1655:   ) u_ip0_p30 (
1656:     .clk_i   (clk_i    ),
1657:     .rst_ni  (rst_ni  ),
1658: 
1659:     .we     (1'b0),
1660:     .wd     ('0  ),
1661: 
1662:     // from internal hardware
1663:     .de     (hw2reg.ip[30].de),
1664:     .d      (hw2reg.ip[30].d ),
1665: 
1666:     // to internal hardware
1667:     .qe     (),
1668:     .q      (),
1669: 
1670:     // to register interface (read)
1671:     .qs     (ip0_p30_qs)
1672:   );
1673: 
1674: 
1675:   // F[p31]: 31:31
1676:   prim_subreg #(
1677:     .DW      (1),
1678:     .SWACCESS("RO"),
1679:     .RESVAL  (1'h0)
1680:   ) u_ip0_p31 (
1681:     .clk_i   (clk_i    ),
1682:     .rst_ni  (rst_ni  ),
1683: 
1684:     .we     (1'b0),
1685:     .wd     ('0  ),
1686: 
1687:     // from internal hardware
1688:     .de     (hw2reg.ip[31].de),
1689:     .d      (hw2reg.ip[31].d ),
1690: 
1691:     // to internal hardware
1692:     .qe     (),
1693:     .q      (),
1694: 
1695:     // to register interface (read)
1696:     .qs     (ip0_p31_qs)
1697:   );
1698: 
1699: 
1700:   // Subregister 32 of Multireg ip
1701:   // R[ip1]: V(False)
1702: 
1703:   // F[p32]: 0:0
1704:   prim_subreg #(
1705:     .DW      (1),
1706:     .SWACCESS("RO"),
1707:     .RESVAL  (1'h0)
1708:   ) u_ip1_p32 (
1709:     .clk_i   (clk_i    ),
1710:     .rst_ni  (rst_ni  ),
1711: 
1712:     .we     (1'b0),
1713:     .wd     ('0  ),
1714: 
1715:     // from internal hardware
1716:     .de     (hw2reg.ip[32].de),
1717:     .d      (hw2reg.ip[32].d ),
1718: 
1719:     // to internal hardware
1720:     .qe     (),
1721:     .q      (),
1722: 
1723:     // to register interface (read)
1724:     .qs     (ip1_p32_qs)
1725:   );
1726: 
1727: 
1728:   // F[p33]: 1:1
1729:   prim_subreg #(
1730:     .DW      (1),
1731:     .SWACCESS("RO"),
1732:     .RESVAL  (1'h0)
1733:   ) u_ip1_p33 (
1734:     .clk_i   (clk_i    ),
1735:     .rst_ni  (rst_ni  ),
1736: 
1737:     .we     (1'b0),
1738:     .wd     ('0  ),
1739: 
1740:     // from internal hardware
1741:     .de     (hw2reg.ip[33].de),
1742:     .d      (hw2reg.ip[33].d ),
1743: 
1744:     // to internal hardware
1745:     .qe     (),
1746:     .q      (),
1747: 
1748:     // to register interface (read)
1749:     .qs     (ip1_p33_qs)
1750:   );
1751: 
1752: 
1753:   // F[p34]: 2:2
1754:   prim_subreg #(
1755:     .DW      (1),
1756:     .SWACCESS("RO"),
1757:     .RESVAL  (1'h0)
1758:   ) u_ip1_p34 (
1759:     .clk_i   (clk_i    ),
1760:     .rst_ni  (rst_ni  ),
1761: 
1762:     .we     (1'b0),
1763:     .wd     ('0  ),
1764: 
1765:     // from internal hardware
1766:     .de     (hw2reg.ip[34].de),
1767:     .d      (hw2reg.ip[34].d ),
1768: 
1769:     // to internal hardware
1770:     .qe     (),
1771:     .q      (),
1772: 
1773:     // to register interface (read)
1774:     .qs     (ip1_p34_qs)
1775:   );
1776: 
1777: 
1778:   // F[p35]: 3:3
1779:   prim_subreg #(
1780:     .DW      (1),
1781:     .SWACCESS("RO"),
1782:     .RESVAL  (1'h0)
1783:   ) u_ip1_p35 (
1784:     .clk_i   (clk_i    ),
1785:     .rst_ni  (rst_ni  ),
1786: 
1787:     .we     (1'b0),
1788:     .wd     ('0  ),
1789: 
1790:     // from internal hardware
1791:     .de     (hw2reg.ip[35].de),
1792:     .d      (hw2reg.ip[35].d ),
1793: 
1794:     // to internal hardware
1795:     .qe     (),
1796:     .q      (),
1797: 
1798:     // to register interface (read)
1799:     .qs     (ip1_p35_qs)
1800:   );
1801: 
1802: 
1803:   // F[p36]: 4:4
1804:   prim_subreg #(
1805:     .DW      (1),
1806:     .SWACCESS("RO"),
1807:     .RESVAL  (1'h0)
1808:   ) u_ip1_p36 (
1809:     .clk_i   (clk_i    ),
1810:     .rst_ni  (rst_ni  ),
1811: 
1812:     .we     (1'b0),
1813:     .wd     ('0  ),
1814: 
1815:     // from internal hardware
1816:     .de     (hw2reg.ip[36].de),
1817:     .d      (hw2reg.ip[36].d ),
1818: 
1819:     // to internal hardware
1820:     .qe     (),
1821:     .q      (),
1822: 
1823:     // to register interface (read)
1824:     .qs     (ip1_p36_qs)
1825:   );
1826: 
1827: 
1828:   // F[p37]: 5:5
1829:   prim_subreg #(
1830:     .DW      (1),
1831:     .SWACCESS("RO"),
1832:     .RESVAL  (1'h0)
1833:   ) u_ip1_p37 (
1834:     .clk_i   (clk_i    ),
1835:     .rst_ni  (rst_ni  ),
1836: 
1837:     .we     (1'b0),
1838:     .wd     ('0  ),
1839: 
1840:     // from internal hardware
1841:     .de     (hw2reg.ip[37].de),
1842:     .d      (hw2reg.ip[37].d ),
1843: 
1844:     // to internal hardware
1845:     .qe     (),
1846:     .q      (),
1847: 
1848:     // to register interface (read)
1849:     .qs     (ip1_p37_qs)
1850:   );
1851: 
1852: 
1853:   // F[p38]: 6:6
1854:   prim_subreg #(
1855:     .DW      (1),
1856:     .SWACCESS("RO"),
1857:     .RESVAL  (1'h0)
1858:   ) u_ip1_p38 (
1859:     .clk_i   (clk_i    ),
1860:     .rst_ni  (rst_ni  ),
1861: 
1862:     .we     (1'b0),
1863:     .wd     ('0  ),
1864: 
1865:     // from internal hardware
1866:     .de     (hw2reg.ip[38].de),
1867:     .d      (hw2reg.ip[38].d ),
1868: 
1869:     // to internal hardware
1870:     .qe     (),
1871:     .q      (),
1872: 
1873:     // to register interface (read)
1874:     .qs     (ip1_p38_qs)
1875:   );
1876: 
1877: 
1878:   // F[p39]: 7:7
1879:   prim_subreg #(
1880:     .DW      (1),
1881:     .SWACCESS("RO"),
1882:     .RESVAL  (1'h0)
1883:   ) u_ip1_p39 (
1884:     .clk_i   (clk_i    ),
1885:     .rst_ni  (rst_ni  ),
1886: 
1887:     .we     (1'b0),
1888:     .wd     ('0  ),
1889: 
1890:     // from internal hardware
1891:     .de     (hw2reg.ip[39].de),
1892:     .d      (hw2reg.ip[39].d ),
1893: 
1894:     // to internal hardware
1895:     .qe     (),
1896:     .q      (),
1897: 
1898:     // to register interface (read)
1899:     .qs     (ip1_p39_qs)
1900:   );
1901: 
1902: 
1903:   // F[p40]: 8:8
1904:   prim_subreg #(
1905:     .DW      (1),
1906:     .SWACCESS("RO"),
1907:     .RESVAL  (1'h0)
1908:   ) u_ip1_p40 (
1909:     .clk_i   (clk_i    ),
1910:     .rst_ni  (rst_ni  ),
1911: 
1912:     .we     (1'b0),
1913:     .wd     ('0  ),
1914: 
1915:     // from internal hardware
1916:     .de     (hw2reg.ip[40].de),
1917:     .d      (hw2reg.ip[40].d ),
1918: 
1919:     // to internal hardware
1920:     .qe     (),
1921:     .q      (),
1922: 
1923:     // to register interface (read)
1924:     .qs     (ip1_p40_qs)
1925:   );
1926: 
1927: 
1928:   // F[p41]: 9:9
1929:   prim_subreg #(
1930:     .DW      (1),
1931:     .SWACCESS("RO"),
1932:     .RESVAL  (1'h0)
1933:   ) u_ip1_p41 (
1934:     .clk_i   (clk_i    ),
1935:     .rst_ni  (rst_ni  ),
1936: 
1937:     .we     (1'b0),
1938:     .wd     ('0  ),
1939: 
1940:     // from internal hardware
1941:     .de     (hw2reg.ip[41].de),
1942:     .d      (hw2reg.ip[41].d ),
1943: 
1944:     // to internal hardware
1945:     .qe     (),
1946:     .q      (),
1947: 
1948:     // to register interface (read)
1949:     .qs     (ip1_p41_qs)
1950:   );
1951: 
1952: 
1953:   // F[p42]: 10:10
1954:   prim_subreg #(
1955:     .DW      (1),
1956:     .SWACCESS("RO"),
1957:     .RESVAL  (1'h0)
1958:   ) u_ip1_p42 (
1959:     .clk_i   (clk_i    ),
1960:     .rst_ni  (rst_ni  ),
1961: 
1962:     .we     (1'b0),
1963:     .wd     ('0  ),
1964: 
1965:     // from internal hardware
1966:     .de     (hw2reg.ip[42].de),
1967:     .d      (hw2reg.ip[42].d ),
1968: 
1969:     // to internal hardware
1970:     .qe     (),
1971:     .q      (),
1972: 
1973:     // to register interface (read)
1974:     .qs     (ip1_p42_qs)
1975:   );
1976: 
1977: 
1978:   // F[p43]: 11:11
1979:   prim_subreg #(
1980:     .DW      (1),
1981:     .SWACCESS("RO"),
1982:     .RESVAL  (1'h0)
1983:   ) u_ip1_p43 (
1984:     .clk_i   (clk_i    ),
1985:     .rst_ni  (rst_ni  ),
1986: 
1987:     .we     (1'b0),
1988:     .wd     ('0  ),
1989: 
1990:     // from internal hardware
1991:     .de     (hw2reg.ip[43].de),
1992:     .d      (hw2reg.ip[43].d ),
1993: 
1994:     // to internal hardware
1995:     .qe     (),
1996:     .q      (),
1997: 
1998:     // to register interface (read)
1999:     .qs     (ip1_p43_qs)
2000:   );
2001: 
2002: 
2003:   // F[p44]: 12:12
2004:   prim_subreg #(
2005:     .DW      (1),
2006:     .SWACCESS("RO"),
2007:     .RESVAL  (1'h0)
2008:   ) u_ip1_p44 (
2009:     .clk_i   (clk_i    ),
2010:     .rst_ni  (rst_ni  ),
2011: 
2012:     .we     (1'b0),
2013:     .wd     ('0  ),
2014: 
2015:     // from internal hardware
2016:     .de     (hw2reg.ip[44].de),
2017:     .d      (hw2reg.ip[44].d ),
2018: 
2019:     // to internal hardware
2020:     .qe     (),
2021:     .q      (),
2022: 
2023:     // to register interface (read)
2024:     .qs     (ip1_p44_qs)
2025:   );
2026: 
2027: 
2028:   // F[p45]: 13:13
2029:   prim_subreg #(
2030:     .DW      (1),
2031:     .SWACCESS("RO"),
2032:     .RESVAL  (1'h0)
2033:   ) u_ip1_p45 (
2034:     .clk_i   (clk_i    ),
2035:     .rst_ni  (rst_ni  ),
2036: 
2037:     .we     (1'b0),
2038:     .wd     ('0  ),
2039: 
2040:     // from internal hardware
2041:     .de     (hw2reg.ip[45].de),
2042:     .d      (hw2reg.ip[45].d ),
2043: 
2044:     // to internal hardware
2045:     .qe     (),
2046:     .q      (),
2047: 
2048:     // to register interface (read)
2049:     .qs     (ip1_p45_qs)
2050:   );
2051: 
2052: 
2053:   // F[p46]: 14:14
2054:   prim_subreg #(
2055:     .DW      (1),
2056:     .SWACCESS("RO"),
2057:     .RESVAL  (1'h0)
2058:   ) u_ip1_p46 (
2059:     .clk_i   (clk_i    ),
2060:     .rst_ni  (rst_ni  ),
2061: 
2062:     .we     (1'b0),
2063:     .wd     ('0  ),
2064: 
2065:     // from internal hardware
2066:     .de     (hw2reg.ip[46].de),
2067:     .d      (hw2reg.ip[46].d ),
2068: 
2069:     // to internal hardware
2070:     .qe     (),
2071:     .q      (),
2072: 
2073:     // to register interface (read)
2074:     .qs     (ip1_p46_qs)
2075:   );
2076: 
2077: 
2078:   // F[p47]: 15:15
2079:   prim_subreg #(
2080:     .DW      (1),
2081:     .SWACCESS("RO"),
2082:     .RESVAL  (1'h0)
2083:   ) u_ip1_p47 (
2084:     .clk_i   (clk_i    ),
2085:     .rst_ni  (rst_ni  ),
2086: 
2087:     .we     (1'b0),
2088:     .wd     ('0  ),
2089: 
2090:     // from internal hardware
2091:     .de     (hw2reg.ip[47].de),
2092:     .d      (hw2reg.ip[47].d ),
2093: 
2094:     // to internal hardware
2095:     .qe     (),
2096:     .q      (),
2097: 
2098:     // to register interface (read)
2099:     .qs     (ip1_p47_qs)
2100:   );
2101: 
2102: 
2103:   // F[p48]: 16:16
2104:   prim_subreg #(
2105:     .DW      (1),
2106:     .SWACCESS("RO"),
2107:     .RESVAL  (1'h0)
2108:   ) u_ip1_p48 (
2109:     .clk_i   (clk_i    ),
2110:     .rst_ni  (rst_ni  ),
2111: 
2112:     .we     (1'b0),
2113:     .wd     ('0  ),
2114: 
2115:     // from internal hardware
2116:     .de     (hw2reg.ip[48].de),
2117:     .d      (hw2reg.ip[48].d ),
2118: 
2119:     // to internal hardware
2120:     .qe     (),
2121:     .q      (),
2122: 
2123:     // to register interface (read)
2124:     .qs     (ip1_p48_qs)
2125:   );
2126: 
2127: 
2128:   // F[p49]: 17:17
2129:   prim_subreg #(
2130:     .DW      (1),
2131:     .SWACCESS("RO"),
2132:     .RESVAL  (1'h0)
2133:   ) u_ip1_p49 (
2134:     .clk_i   (clk_i    ),
2135:     .rst_ni  (rst_ni  ),
2136: 
2137:     .we     (1'b0),
2138:     .wd     ('0  ),
2139: 
2140:     // from internal hardware
2141:     .de     (hw2reg.ip[49].de),
2142:     .d      (hw2reg.ip[49].d ),
2143: 
2144:     // to internal hardware
2145:     .qe     (),
2146:     .q      (),
2147: 
2148:     // to register interface (read)
2149:     .qs     (ip1_p49_qs)
2150:   );
2151: 
2152: 
2153:   // F[p50]: 18:18
2154:   prim_subreg #(
2155:     .DW      (1),
2156:     .SWACCESS("RO"),
2157:     .RESVAL  (1'h0)
2158:   ) u_ip1_p50 (
2159:     .clk_i   (clk_i    ),
2160:     .rst_ni  (rst_ni  ),
2161: 
2162:     .we     (1'b0),
2163:     .wd     ('0  ),
2164: 
2165:     // from internal hardware
2166:     .de     (hw2reg.ip[50].de),
2167:     .d      (hw2reg.ip[50].d ),
2168: 
2169:     // to internal hardware
2170:     .qe     (),
2171:     .q      (),
2172: 
2173:     // to register interface (read)
2174:     .qs     (ip1_p50_qs)
2175:   );
2176: 
2177: 
2178:   // F[p51]: 19:19
2179:   prim_subreg #(
2180:     .DW      (1),
2181:     .SWACCESS("RO"),
2182:     .RESVAL  (1'h0)
2183:   ) u_ip1_p51 (
2184:     .clk_i   (clk_i    ),
2185:     .rst_ni  (rst_ni  ),
2186: 
2187:     .we     (1'b0),
2188:     .wd     ('0  ),
2189: 
2190:     // from internal hardware
2191:     .de     (hw2reg.ip[51].de),
2192:     .d      (hw2reg.ip[51].d ),
2193: 
2194:     // to internal hardware
2195:     .qe     (),
2196:     .q      (),
2197: 
2198:     // to register interface (read)
2199:     .qs     (ip1_p51_qs)
2200:   );
2201: 
2202: 
2203:   // F[p52]: 20:20
2204:   prim_subreg #(
2205:     .DW      (1),
2206:     .SWACCESS("RO"),
2207:     .RESVAL  (1'h0)
2208:   ) u_ip1_p52 (
2209:     .clk_i   (clk_i    ),
2210:     .rst_ni  (rst_ni  ),
2211: 
2212:     .we     (1'b0),
2213:     .wd     ('0  ),
2214: 
2215:     // from internal hardware
2216:     .de     (hw2reg.ip[52].de),
2217:     .d      (hw2reg.ip[52].d ),
2218: 
2219:     // to internal hardware
2220:     .qe     (),
2221:     .q      (),
2222: 
2223:     // to register interface (read)
2224:     .qs     (ip1_p52_qs)
2225:   );
2226: 
2227: 
2228:   // F[p53]: 21:21
2229:   prim_subreg #(
2230:     .DW      (1),
2231:     .SWACCESS("RO"),
2232:     .RESVAL  (1'h0)
2233:   ) u_ip1_p53 (
2234:     .clk_i   (clk_i    ),
2235:     .rst_ni  (rst_ni  ),
2236: 
2237:     .we     (1'b0),
2238:     .wd     ('0  ),
2239: 
2240:     // from internal hardware
2241:     .de     (hw2reg.ip[53].de),
2242:     .d      (hw2reg.ip[53].d ),
2243: 
2244:     // to internal hardware
2245:     .qe     (),
2246:     .q      (),
2247: 
2248:     // to register interface (read)
2249:     .qs     (ip1_p53_qs)
2250:   );
2251: 
2252: 
2253:   // F[p54]: 22:22
2254:   prim_subreg #(
2255:     .DW      (1),
2256:     .SWACCESS("RO"),
2257:     .RESVAL  (1'h0)
2258:   ) u_ip1_p54 (
2259:     .clk_i   (clk_i    ),
2260:     .rst_ni  (rst_ni  ),
2261: 
2262:     .we     (1'b0),
2263:     .wd     ('0  ),
2264: 
2265:     // from internal hardware
2266:     .de     (hw2reg.ip[54].de),
2267:     .d      (hw2reg.ip[54].d ),
2268: 
2269:     // to internal hardware
2270:     .qe     (),
2271:     .q      (),
2272: 
2273:     // to register interface (read)
2274:     .qs     (ip1_p54_qs)
2275:   );
2276: 
2277: 
2278:   // F[p55]: 23:23
2279:   prim_subreg #(
2280:     .DW      (1),
2281:     .SWACCESS("RO"),
2282:     .RESVAL  (1'h0)
2283:   ) u_ip1_p55 (
2284:     .clk_i   (clk_i    ),
2285:     .rst_ni  (rst_ni  ),
2286: 
2287:     .we     (1'b0),
2288:     .wd     ('0  ),
2289: 
2290:     // from internal hardware
2291:     .de     (hw2reg.ip[55].de),
2292:     .d      (hw2reg.ip[55].d ),
2293: 
2294:     // to internal hardware
2295:     .qe     (),
2296:     .q      (),
2297: 
2298:     // to register interface (read)
2299:     .qs     (ip1_p55_qs)
2300:   );
2301: 
2302: 
2303:   // F[p56]: 24:24
2304:   prim_subreg #(
2305:     .DW      (1),
2306:     .SWACCESS("RO"),
2307:     .RESVAL  (1'h0)
2308:   ) u_ip1_p56 (
2309:     .clk_i   (clk_i    ),
2310:     .rst_ni  (rst_ni  ),
2311: 
2312:     .we     (1'b0),
2313:     .wd     ('0  ),
2314: 
2315:     // from internal hardware
2316:     .de     (hw2reg.ip[56].de),
2317:     .d      (hw2reg.ip[56].d ),
2318: 
2319:     // to internal hardware
2320:     .qe     (),
2321:     .q      (),
2322: 
2323:     // to register interface (read)
2324:     .qs     (ip1_p56_qs)
2325:   );
2326: 
2327: 
2328:   // F[p57]: 25:25
2329:   prim_subreg #(
2330:     .DW      (1),
2331:     .SWACCESS("RO"),
2332:     .RESVAL  (1'h0)
2333:   ) u_ip1_p57 (
2334:     .clk_i   (clk_i    ),
2335:     .rst_ni  (rst_ni  ),
2336: 
2337:     .we     (1'b0),
2338:     .wd     ('0  ),
2339: 
2340:     // from internal hardware
2341:     .de     (hw2reg.ip[57].de),
2342:     .d      (hw2reg.ip[57].d ),
2343: 
2344:     // to internal hardware
2345:     .qe     (),
2346:     .q      (),
2347: 
2348:     // to register interface (read)
2349:     .qs     (ip1_p57_qs)
2350:   );
2351: 
2352: 
2353:   // F[p58]: 26:26
2354:   prim_subreg #(
2355:     .DW      (1),
2356:     .SWACCESS("RO"),
2357:     .RESVAL  (1'h0)
2358:   ) u_ip1_p58 (
2359:     .clk_i   (clk_i    ),
2360:     .rst_ni  (rst_ni  ),
2361: 
2362:     .we     (1'b0),
2363:     .wd     ('0  ),
2364: 
2365:     // from internal hardware
2366:     .de     (hw2reg.ip[58].de),
2367:     .d      (hw2reg.ip[58].d ),
2368: 
2369:     // to internal hardware
2370:     .qe     (),
2371:     .q      (),
2372: 
2373:     // to register interface (read)
2374:     .qs     (ip1_p58_qs)
2375:   );
2376: 
2377: 
2378:   // F[p59]: 27:27
2379:   prim_subreg #(
2380:     .DW      (1),
2381:     .SWACCESS("RO"),
2382:     .RESVAL  (1'h0)
2383:   ) u_ip1_p59 (
2384:     .clk_i   (clk_i    ),
2385:     .rst_ni  (rst_ni  ),
2386: 
2387:     .we     (1'b0),
2388:     .wd     ('0  ),
2389: 
2390:     // from internal hardware
2391:     .de     (hw2reg.ip[59].de),
2392:     .d      (hw2reg.ip[59].d ),
2393: 
2394:     // to internal hardware
2395:     .qe     (),
2396:     .q      (),
2397: 
2398:     // to register interface (read)
2399:     .qs     (ip1_p59_qs)
2400:   );
2401: 
2402: 
2403:   // F[p60]: 28:28
2404:   prim_subreg #(
2405:     .DW      (1),
2406:     .SWACCESS("RO"),
2407:     .RESVAL  (1'h0)
2408:   ) u_ip1_p60 (
2409:     .clk_i   (clk_i    ),
2410:     .rst_ni  (rst_ni  ),
2411: 
2412:     .we     (1'b0),
2413:     .wd     ('0  ),
2414: 
2415:     // from internal hardware
2416:     .de     (hw2reg.ip[60].de),
2417:     .d      (hw2reg.ip[60].d ),
2418: 
2419:     // to internal hardware
2420:     .qe     (),
2421:     .q      (),
2422: 
2423:     // to register interface (read)
2424:     .qs     (ip1_p60_qs)
2425:   );
2426: 
2427: 
2428:   // F[p61]: 29:29
2429:   prim_subreg #(
2430:     .DW      (1),
2431:     .SWACCESS("RO"),
2432:     .RESVAL  (1'h0)
2433:   ) u_ip1_p61 (
2434:     .clk_i   (clk_i    ),
2435:     .rst_ni  (rst_ni  ),
2436: 
2437:     .we     (1'b0),
2438:     .wd     ('0  ),
2439: 
2440:     // from internal hardware
2441:     .de     (hw2reg.ip[61].de),
2442:     .d      (hw2reg.ip[61].d ),
2443: 
2444:     // to internal hardware
2445:     .qe     (),
2446:     .q      (),
2447: 
2448:     // to register interface (read)
2449:     .qs     (ip1_p61_qs)
2450:   );
2451: 
2452: 
2453:   // F[p62]: 30:30
2454:   prim_subreg #(
2455:     .DW      (1),
2456:     .SWACCESS("RO"),
2457:     .RESVAL  (1'h0)
2458:   ) u_ip1_p62 (
2459:     .clk_i   (clk_i    ),
2460:     .rst_ni  (rst_ni  ),
2461: 
2462:     .we     (1'b0),
2463:     .wd     ('0  ),
2464: 
2465:     // from internal hardware
2466:     .de     (hw2reg.ip[62].de),
2467:     .d      (hw2reg.ip[62].d ),
2468: 
2469:     // to internal hardware
2470:     .qe     (),
2471:     .q      (),
2472: 
2473:     // to register interface (read)
2474:     .qs     (ip1_p62_qs)
2475:   );
2476: 
2477: 
2478:   // F[p63]: 31:31
2479:   prim_subreg #(
2480:     .DW      (1),
2481:     .SWACCESS("RO"),
2482:     .RESVAL  (1'h0)
2483:   ) u_ip1_p63 (
2484:     .clk_i   (clk_i    ),
2485:     .rst_ni  (rst_ni  ),
2486: 
2487:     .we     (1'b0),
2488:     .wd     ('0  ),
2489: 
2490:     // from internal hardware
2491:     .de     (hw2reg.ip[63].de),
2492:     .d      (hw2reg.ip[63].d ),
2493: 
2494:     // to internal hardware
2495:     .qe     (),
2496:     .q      (),
2497: 
2498:     // to register interface (read)
2499:     .qs     (ip1_p63_qs)
2500:   );
2501: 
2502: 
2503:   // Subregister 64 of Multireg ip
2504:   // R[ip2]: V(False)
2505: 
2506:   // F[p64]: 0:0
2507:   prim_subreg #(
2508:     .DW      (1),
2509:     .SWACCESS("RO"),
2510:     .RESVAL  (1'h0)
2511:   ) u_ip2_p64 (
2512:     .clk_i   (clk_i    ),
2513:     .rst_ni  (rst_ni  ),
2514: 
2515:     .we     (1'b0),
2516:     .wd     ('0  ),
2517: 
2518:     // from internal hardware
2519:     .de     (hw2reg.ip[64].de),
2520:     .d      (hw2reg.ip[64].d ),
2521: 
2522:     // to internal hardware
2523:     .qe     (),
2524:     .q      (),
2525: 
2526:     // to register interface (read)
2527:     .qs     (ip2_p64_qs)
2528:   );
2529: 
2530: 
2531:   // F[p65]: 1:1
2532:   prim_subreg #(
2533:     .DW      (1),
2534:     .SWACCESS("RO"),
2535:     .RESVAL  (1'h0)
2536:   ) u_ip2_p65 (
2537:     .clk_i   (clk_i    ),
2538:     .rst_ni  (rst_ni  ),
2539: 
2540:     .we     (1'b0),
2541:     .wd     ('0  ),
2542: 
2543:     // from internal hardware
2544:     .de     (hw2reg.ip[65].de),
2545:     .d      (hw2reg.ip[65].d ),
2546: 
2547:     // to internal hardware
2548:     .qe     (),
2549:     .q      (),
2550: 
2551:     // to register interface (read)
2552:     .qs     (ip2_p65_qs)
2553:   );
2554: 
2555: 
2556:   // F[p66]: 2:2
2557:   prim_subreg #(
2558:     .DW      (1),
2559:     .SWACCESS("RO"),
2560:     .RESVAL  (1'h0)
2561:   ) u_ip2_p66 (
2562:     .clk_i   (clk_i    ),
2563:     .rst_ni  (rst_ni  ),
2564: 
2565:     .we     (1'b0),
2566:     .wd     ('0  ),
2567: 
2568:     // from internal hardware
2569:     .de     (hw2reg.ip[66].de),
2570:     .d      (hw2reg.ip[66].d ),
2571: 
2572:     // to internal hardware
2573:     .qe     (),
2574:     .q      (),
2575: 
2576:     // to register interface (read)
2577:     .qs     (ip2_p66_qs)
2578:   );
2579: 
2580: 
2581:   // F[p67]: 3:3
2582:   prim_subreg #(
2583:     .DW      (1),
2584:     .SWACCESS("RO"),
2585:     .RESVAL  (1'h0)
2586:   ) u_ip2_p67 (
2587:     .clk_i   (clk_i    ),
2588:     .rst_ni  (rst_ni  ),
2589: 
2590:     .we     (1'b0),
2591:     .wd     ('0  ),
2592: 
2593:     // from internal hardware
2594:     .de     (hw2reg.ip[67].de),
2595:     .d      (hw2reg.ip[67].d ),
2596: 
2597:     // to internal hardware
2598:     .qe     (),
2599:     .q      (),
2600: 
2601:     // to register interface (read)
2602:     .qs     (ip2_p67_qs)
2603:   );
2604: 
2605: 
2606:   // F[p68]: 4:4
2607:   prim_subreg #(
2608:     .DW      (1),
2609:     .SWACCESS("RO"),
2610:     .RESVAL  (1'h0)
2611:   ) u_ip2_p68 (
2612:     .clk_i   (clk_i    ),
2613:     .rst_ni  (rst_ni  ),
2614: 
2615:     .we     (1'b0),
2616:     .wd     ('0  ),
2617: 
2618:     // from internal hardware
2619:     .de     (hw2reg.ip[68].de),
2620:     .d      (hw2reg.ip[68].d ),
2621: 
2622:     // to internal hardware
2623:     .qe     (),
2624:     .q      (),
2625: 
2626:     // to register interface (read)
2627:     .qs     (ip2_p68_qs)
2628:   );
2629: 
2630: 
2631:   // F[p69]: 5:5
2632:   prim_subreg #(
2633:     .DW      (1),
2634:     .SWACCESS("RO"),
2635:     .RESVAL  (1'h0)
2636:   ) u_ip2_p69 (
2637:     .clk_i   (clk_i    ),
2638:     .rst_ni  (rst_ni  ),
2639: 
2640:     .we     (1'b0),
2641:     .wd     ('0  ),
2642: 
2643:     // from internal hardware
2644:     .de     (hw2reg.ip[69].de),
2645:     .d      (hw2reg.ip[69].d ),
2646: 
2647:     // to internal hardware
2648:     .qe     (),
2649:     .q      (),
2650: 
2651:     // to register interface (read)
2652:     .qs     (ip2_p69_qs)
2653:   );
2654: 
2655: 
2656:   // F[p70]: 6:6
2657:   prim_subreg #(
2658:     .DW      (1),
2659:     .SWACCESS("RO"),
2660:     .RESVAL  (1'h0)
2661:   ) u_ip2_p70 (
2662:     .clk_i   (clk_i    ),
2663:     .rst_ni  (rst_ni  ),
2664: 
2665:     .we     (1'b0),
2666:     .wd     ('0  ),
2667: 
2668:     // from internal hardware
2669:     .de     (hw2reg.ip[70].de),
2670:     .d      (hw2reg.ip[70].d ),
2671: 
2672:     // to internal hardware
2673:     .qe     (),
2674:     .q      (),
2675: 
2676:     // to register interface (read)
2677:     .qs     (ip2_p70_qs)
2678:   );
2679: 
2680: 
2681:   // F[p71]: 7:7
2682:   prim_subreg #(
2683:     .DW      (1),
2684:     .SWACCESS("RO"),
2685:     .RESVAL  (1'h0)
2686:   ) u_ip2_p71 (
2687:     .clk_i   (clk_i    ),
2688:     .rst_ni  (rst_ni  ),
2689: 
2690:     .we     (1'b0),
2691:     .wd     ('0  ),
2692: 
2693:     // from internal hardware
2694:     .de     (hw2reg.ip[71].de),
2695:     .d      (hw2reg.ip[71].d ),
2696: 
2697:     // to internal hardware
2698:     .qe     (),
2699:     .q      (),
2700: 
2701:     // to register interface (read)
2702:     .qs     (ip2_p71_qs)
2703:   );
2704: 
2705: 
2706:   // F[p72]: 8:8
2707:   prim_subreg #(
2708:     .DW      (1),
2709:     .SWACCESS("RO"),
2710:     .RESVAL  (1'h0)
2711:   ) u_ip2_p72 (
2712:     .clk_i   (clk_i    ),
2713:     .rst_ni  (rst_ni  ),
2714: 
2715:     .we     (1'b0),
2716:     .wd     ('0  ),
2717: 
2718:     // from internal hardware
2719:     .de     (hw2reg.ip[72].de),
2720:     .d      (hw2reg.ip[72].d ),
2721: 
2722:     // to internal hardware
2723:     .qe     (),
2724:     .q      (),
2725: 
2726:     // to register interface (read)
2727:     .qs     (ip2_p72_qs)
2728:   );
2729: 
2730: 
2731:   // F[p73]: 9:9
2732:   prim_subreg #(
2733:     .DW      (1),
2734:     .SWACCESS("RO"),
2735:     .RESVAL  (1'h0)
2736:   ) u_ip2_p73 (
2737:     .clk_i   (clk_i    ),
2738:     .rst_ni  (rst_ni  ),
2739: 
2740:     .we     (1'b0),
2741:     .wd     ('0  ),
2742: 
2743:     // from internal hardware
2744:     .de     (hw2reg.ip[73].de),
2745:     .d      (hw2reg.ip[73].d ),
2746: 
2747:     // to internal hardware
2748:     .qe     (),
2749:     .q      (),
2750: 
2751:     // to register interface (read)
2752:     .qs     (ip2_p73_qs)
2753:   );
2754: 
2755: 
2756:   // F[p74]: 10:10
2757:   prim_subreg #(
2758:     .DW      (1),
2759:     .SWACCESS("RO"),
2760:     .RESVAL  (1'h0)
2761:   ) u_ip2_p74 (
2762:     .clk_i   (clk_i    ),
2763:     .rst_ni  (rst_ni  ),
2764: 
2765:     .we     (1'b0),
2766:     .wd     ('0  ),
2767: 
2768:     // from internal hardware
2769:     .de     (hw2reg.ip[74].de),
2770:     .d      (hw2reg.ip[74].d ),
2771: 
2772:     // to internal hardware
2773:     .qe     (),
2774:     .q      (),
2775: 
2776:     // to register interface (read)
2777:     .qs     (ip2_p74_qs)
2778:   );
2779: 
2780: 
2781:   // F[p75]: 11:11
2782:   prim_subreg #(
2783:     .DW      (1),
2784:     .SWACCESS("RO"),
2785:     .RESVAL  (1'h0)
2786:   ) u_ip2_p75 (
2787:     .clk_i   (clk_i    ),
2788:     .rst_ni  (rst_ni  ),
2789: 
2790:     .we     (1'b0),
2791:     .wd     ('0  ),
2792: 
2793:     // from internal hardware
2794:     .de     (hw2reg.ip[75].de),
2795:     .d      (hw2reg.ip[75].d ),
2796: 
2797:     // to internal hardware
2798:     .qe     (),
2799:     .q      (),
2800: 
2801:     // to register interface (read)
2802:     .qs     (ip2_p75_qs)
2803:   );
2804: 
2805: 
2806:   // F[p76]: 12:12
2807:   prim_subreg #(
2808:     .DW      (1),
2809:     .SWACCESS("RO"),
2810:     .RESVAL  (1'h0)
2811:   ) u_ip2_p76 (
2812:     .clk_i   (clk_i    ),
2813:     .rst_ni  (rst_ni  ),
2814: 
2815:     .we     (1'b0),
2816:     .wd     ('0  ),
2817: 
2818:     // from internal hardware
2819:     .de     (hw2reg.ip[76].de),
2820:     .d      (hw2reg.ip[76].d ),
2821: 
2822:     // to internal hardware
2823:     .qe     (),
2824:     .q      (),
2825: 
2826:     // to register interface (read)
2827:     .qs     (ip2_p76_qs)
2828:   );
2829: 
2830: 
2831:   // F[p77]: 13:13
2832:   prim_subreg #(
2833:     .DW      (1),
2834:     .SWACCESS("RO"),
2835:     .RESVAL  (1'h0)
2836:   ) u_ip2_p77 (
2837:     .clk_i   (clk_i    ),
2838:     .rst_ni  (rst_ni  ),
2839: 
2840:     .we     (1'b0),
2841:     .wd     ('0  ),
2842: 
2843:     // from internal hardware
2844:     .de     (hw2reg.ip[77].de),
2845:     .d      (hw2reg.ip[77].d ),
2846: 
2847:     // to internal hardware
2848:     .qe     (),
2849:     .q      (),
2850: 
2851:     // to register interface (read)
2852:     .qs     (ip2_p77_qs)
2853:   );
2854: 
2855: 
2856:   // F[p78]: 14:14
2857:   prim_subreg #(
2858:     .DW      (1),
2859:     .SWACCESS("RO"),
2860:     .RESVAL  (1'h0)
2861:   ) u_ip2_p78 (
2862:     .clk_i   (clk_i    ),
2863:     .rst_ni  (rst_ni  ),
2864: 
2865:     .we     (1'b0),
2866:     .wd     ('0  ),
2867: 
2868:     // from internal hardware
2869:     .de     (hw2reg.ip[78].de),
2870:     .d      (hw2reg.ip[78].d ),
2871: 
2872:     // to internal hardware
2873:     .qe     (),
2874:     .q      (),
2875: 
2876:     // to register interface (read)
2877:     .qs     (ip2_p78_qs)
2878:   );
2879: 
2880: 
2881:   // F[p79]: 15:15
2882:   prim_subreg #(
2883:     .DW      (1),
2884:     .SWACCESS("RO"),
2885:     .RESVAL  (1'h0)
2886:   ) u_ip2_p79 (
2887:     .clk_i   (clk_i    ),
2888:     .rst_ni  (rst_ni  ),
2889: 
2890:     .we     (1'b0),
2891:     .wd     ('0  ),
2892: 
2893:     // from internal hardware
2894:     .de     (hw2reg.ip[79].de),
2895:     .d      (hw2reg.ip[79].d ),
2896: 
2897:     // to internal hardware
2898:     .qe     (),
2899:     .q      (),
2900: 
2901:     // to register interface (read)
2902:     .qs     (ip2_p79_qs)
2903:   );
2904: 
2905: 
2906:   // F[p80]: 16:16
2907:   prim_subreg #(
2908:     .DW      (1),
2909:     .SWACCESS("RO"),
2910:     .RESVAL  (1'h0)
2911:   ) u_ip2_p80 (
2912:     .clk_i   (clk_i    ),
2913:     .rst_ni  (rst_ni  ),
2914: 
2915:     .we     (1'b0),
2916:     .wd     ('0  ),
2917: 
2918:     // from internal hardware
2919:     .de     (hw2reg.ip[80].de),
2920:     .d      (hw2reg.ip[80].d ),
2921: 
2922:     // to internal hardware
2923:     .qe     (),
2924:     .q      (),
2925: 
2926:     // to register interface (read)
2927:     .qs     (ip2_p80_qs)
2928:   );
2929: 
2930: 
2931: 
2932: 
2933:   // Subregister 0 of Multireg le
2934:   // R[le0]: V(False)
2935: 
2936:   // F[le0]: 0:0
2937:   prim_subreg #(
2938:     .DW      (1),
2939:     .SWACCESS("RW"),
2940:     .RESVAL  (1'h0)
2941:   ) u_le0_le0 (
2942:     .clk_i   (clk_i    ),
2943:     .rst_ni  (rst_ni  ),
2944: 
2945:     // from register interface
2946:     .we     (le0_le0_we),
2947:     .wd     (le0_le0_wd),
2948: 
2949:     // from internal hardware
2950:     .de     (1'b0),
2951:     .d      ('0  ),
2952: 
2953:     // to internal hardware
2954:     .qe     (),
2955:     .q      (reg2hw.le[0].q ),
2956: 
2957:     // to register interface (read)
2958:     .qs     (le0_le0_qs)
2959:   );
2960: 
2961: 
2962:   // F[le1]: 1:1
2963:   prim_subreg #(
2964:     .DW      (1),
2965:     .SWACCESS("RW"),
2966:     .RESVAL  (1'h0)
2967:   ) u_le0_le1 (
2968:     .clk_i   (clk_i    ),
2969:     .rst_ni  (rst_ni  ),
2970: 
2971:     // from register interface
2972:     .we     (le0_le1_we),
2973:     .wd     (le0_le1_wd),
2974: 
2975:     // from internal hardware
2976:     .de     (1'b0),
2977:     .d      ('0  ),
2978: 
2979:     // to internal hardware
2980:     .qe     (),
2981:     .q      (reg2hw.le[1].q ),
2982: 
2983:     // to register interface (read)
2984:     .qs     (le0_le1_qs)
2985:   );
2986: 
2987: 
2988:   // F[le2]: 2:2
2989:   prim_subreg #(
2990:     .DW      (1),
2991:     .SWACCESS("RW"),
2992:     .RESVAL  (1'h0)
2993:   ) u_le0_le2 (
2994:     .clk_i   (clk_i    ),
2995:     .rst_ni  (rst_ni  ),
2996: 
2997:     // from register interface
2998:     .we     (le0_le2_we),
2999:     .wd     (le0_le2_wd),
3000: 
3001:     // from internal hardware
3002:     .de     (1'b0),
3003:     .d      ('0  ),
3004: 
3005:     // to internal hardware
3006:     .qe     (),
3007:     .q      (reg2hw.le[2].q ),
3008: 
3009:     // to register interface (read)
3010:     .qs     (le0_le2_qs)
3011:   );
3012: 
3013: 
3014:   // F[le3]: 3:3
3015:   prim_subreg #(
3016:     .DW      (1),
3017:     .SWACCESS("RW"),
3018:     .RESVAL  (1'h0)
3019:   ) u_le0_le3 (
3020:     .clk_i   (clk_i    ),
3021:     .rst_ni  (rst_ni  ),
3022: 
3023:     // from register interface
3024:     .we     (le0_le3_we),
3025:     .wd     (le0_le3_wd),
3026: 
3027:     // from internal hardware
3028:     .de     (1'b0),
3029:     .d      ('0  ),
3030: 
3031:     // to internal hardware
3032:     .qe     (),
3033:     .q      (reg2hw.le[3].q ),
3034: 
3035:     // to register interface (read)
3036:     .qs     (le0_le3_qs)
3037:   );
3038: 
3039: 
3040:   // F[le4]: 4:4
3041:   prim_subreg #(
3042:     .DW      (1),
3043:     .SWACCESS("RW"),
3044:     .RESVAL  (1'h0)
3045:   ) u_le0_le4 (
3046:     .clk_i   (clk_i    ),
3047:     .rst_ni  (rst_ni  ),
3048: 
3049:     // from register interface
3050:     .we     (le0_le4_we),
3051:     .wd     (le0_le4_wd),
3052: 
3053:     // from internal hardware
3054:     .de     (1'b0),
3055:     .d      ('0  ),
3056: 
3057:     // to internal hardware
3058:     .qe     (),
3059:     .q      (reg2hw.le[4].q ),
3060: 
3061:     // to register interface (read)
3062:     .qs     (le0_le4_qs)
3063:   );
3064: 
3065: 
3066:   // F[le5]: 5:5
3067:   prim_subreg #(
3068:     .DW      (1),
3069:     .SWACCESS("RW"),
3070:     .RESVAL  (1'h0)
3071:   ) u_le0_le5 (
3072:     .clk_i   (clk_i    ),
3073:     .rst_ni  (rst_ni  ),
3074: 
3075:     // from register interface
3076:     .we     (le0_le5_we),
3077:     .wd     (le0_le5_wd),
3078: 
3079:     // from internal hardware
3080:     .de     (1'b0),
3081:     .d      ('0  ),
3082: 
3083:     // to internal hardware
3084:     .qe     (),
3085:     .q      (reg2hw.le[5].q ),
3086: 
3087:     // to register interface (read)
3088:     .qs     (le0_le5_qs)
3089:   );
3090: 
3091: 
3092:   // F[le6]: 6:6
3093:   prim_subreg #(
3094:     .DW      (1),
3095:     .SWACCESS("RW"),
3096:     .RESVAL  (1'h0)
3097:   ) u_le0_le6 (
3098:     .clk_i   (clk_i    ),
3099:     .rst_ni  (rst_ni  ),
3100: 
3101:     // from register interface
3102:     .we     (le0_le6_we),
3103:     .wd     (le0_le6_wd),
3104: 
3105:     // from internal hardware
3106:     .de     (1'b0),
3107:     .d      ('0  ),
3108: 
3109:     // to internal hardware
3110:     .qe     (),
3111:     .q      (reg2hw.le[6].q ),
3112: 
3113:     // to register interface (read)
3114:     .qs     (le0_le6_qs)
3115:   );
3116: 
3117: 
3118:   // F[le7]: 7:7
3119:   prim_subreg #(
3120:     .DW      (1),
3121:     .SWACCESS("RW"),
3122:     .RESVAL  (1'h0)
3123:   ) u_le0_le7 (
3124:     .clk_i   (clk_i    ),
3125:     .rst_ni  (rst_ni  ),
3126: 
3127:     // from register interface
3128:     .we     (le0_le7_we),
3129:     .wd     (le0_le7_wd),
3130: 
3131:     // from internal hardware
3132:     .de     (1'b0),
3133:     .d      ('0  ),
3134: 
3135:     // to internal hardware
3136:     .qe     (),
3137:     .q      (reg2hw.le[7].q ),
3138: 
3139:     // to register interface (read)
3140:     .qs     (le0_le7_qs)
3141:   );
3142: 
3143: 
3144:   // F[le8]: 8:8
3145:   prim_subreg #(
3146:     .DW      (1),
3147:     .SWACCESS("RW"),
3148:     .RESVAL  (1'h0)
3149:   ) u_le0_le8 (
3150:     .clk_i   (clk_i    ),
3151:     .rst_ni  (rst_ni  ),
3152: 
3153:     // from register interface
3154:     .we     (le0_le8_we),
3155:     .wd     (le0_le8_wd),
3156: 
3157:     // from internal hardware
3158:     .de     (1'b0),
3159:     .d      ('0  ),
3160: 
3161:     // to internal hardware
3162:     .qe     (),
3163:     .q      (reg2hw.le[8].q ),
3164: 
3165:     // to register interface (read)
3166:     .qs     (le0_le8_qs)
3167:   );
3168: 
3169: 
3170:   // F[le9]: 9:9
3171:   prim_subreg #(
3172:     .DW      (1),
3173:     .SWACCESS("RW"),
3174:     .RESVAL  (1'h0)
3175:   ) u_le0_le9 (
3176:     .clk_i   (clk_i    ),
3177:     .rst_ni  (rst_ni  ),
3178: 
3179:     // from register interface
3180:     .we     (le0_le9_we),
3181:     .wd     (le0_le9_wd),
3182: 
3183:     // from internal hardware
3184:     .de     (1'b0),
3185:     .d      ('0  ),
3186: 
3187:     // to internal hardware
3188:     .qe     (),
3189:     .q      (reg2hw.le[9].q ),
3190: 
3191:     // to register interface (read)
3192:     .qs     (le0_le9_qs)
3193:   );
3194: 
3195: 
3196:   // F[le10]: 10:10
3197:   prim_subreg #(
3198:     .DW      (1),
3199:     .SWACCESS("RW"),
3200:     .RESVAL  (1'h0)
3201:   ) u_le0_le10 (
3202:     .clk_i   (clk_i    ),
3203:     .rst_ni  (rst_ni  ),
3204: 
3205:     // from register interface
3206:     .we     (le0_le10_we),
3207:     .wd     (le0_le10_wd),
3208: 
3209:     // from internal hardware
3210:     .de     (1'b0),
3211:     .d      ('0  ),
3212: 
3213:     // to internal hardware
3214:     .qe     (),
3215:     .q      (reg2hw.le[10].q ),
3216: 
3217:     // to register interface (read)
3218:     .qs     (le0_le10_qs)
3219:   );
3220: 
3221: 
3222:   // F[le11]: 11:11
3223:   prim_subreg #(
3224:     .DW      (1),
3225:     .SWACCESS("RW"),
3226:     .RESVAL  (1'h0)
3227:   ) u_le0_le11 (
3228:     .clk_i   (clk_i    ),
3229:     .rst_ni  (rst_ni  ),
3230: 
3231:     // from register interface
3232:     .we     (le0_le11_we),
3233:     .wd     (le0_le11_wd),
3234: 
3235:     // from internal hardware
3236:     .de     (1'b0),
3237:     .d      ('0  ),
3238: 
3239:     // to internal hardware
3240:     .qe     (),
3241:     .q      (reg2hw.le[11].q ),
3242: 
3243:     // to register interface (read)
3244:     .qs     (le0_le11_qs)
3245:   );
3246: 
3247: 
3248:   // F[le12]: 12:12
3249:   prim_subreg #(
3250:     .DW      (1),
3251:     .SWACCESS("RW"),
3252:     .RESVAL  (1'h0)
3253:   ) u_le0_le12 (
3254:     .clk_i   (clk_i    ),
3255:     .rst_ni  (rst_ni  ),
3256: 
3257:     // from register interface
3258:     .we     (le0_le12_we),
3259:     .wd     (le0_le12_wd),
3260: 
3261:     // from internal hardware
3262:     .de     (1'b0),
3263:     .d      ('0  ),
3264: 
3265:     // to internal hardware
3266:     .qe     (),
3267:     .q      (reg2hw.le[12].q ),
3268: 
3269:     // to register interface (read)
3270:     .qs     (le0_le12_qs)
3271:   );
3272: 
3273: 
3274:   // F[le13]: 13:13
3275:   prim_subreg #(
3276:     .DW      (1),
3277:     .SWACCESS("RW"),
3278:     .RESVAL  (1'h0)
3279:   ) u_le0_le13 (
3280:     .clk_i   (clk_i    ),
3281:     .rst_ni  (rst_ni  ),
3282: 
3283:     // from register interface
3284:     .we     (le0_le13_we),
3285:     .wd     (le0_le13_wd),
3286: 
3287:     // from internal hardware
3288:     .de     (1'b0),
3289:     .d      ('0  ),
3290: 
3291:     // to internal hardware
3292:     .qe     (),
3293:     .q      (reg2hw.le[13].q ),
3294: 
3295:     // to register interface (read)
3296:     .qs     (le0_le13_qs)
3297:   );
3298: 
3299: 
3300:   // F[le14]: 14:14
3301:   prim_subreg #(
3302:     .DW      (1),
3303:     .SWACCESS("RW"),
3304:     .RESVAL  (1'h0)
3305:   ) u_le0_le14 (
3306:     .clk_i   (clk_i    ),
3307:     .rst_ni  (rst_ni  ),
3308: 
3309:     // from register interface
3310:     .we     (le0_le14_we),
3311:     .wd     (le0_le14_wd),
3312: 
3313:     // from internal hardware
3314:     .de     (1'b0),
3315:     .d      ('0  ),
3316: 
3317:     // to internal hardware
3318:     .qe     (),
3319:     .q      (reg2hw.le[14].q ),
3320: 
3321:     // to register interface (read)
3322:     .qs     (le0_le14_qs)
3323:   );
3324: 
3325: 
3326:   // F[le15]: 15:15
3327:   prim_subreg #(
3328:     .DW      (1),
3329:     .SWACCESS("RW"),
3330:     .RESVAL  (1'h0)
3331:   ) u_le0_le15 (
3332:     .clk_i   (clk_i    ),
3333:     .rst_ni  (rst_ni  ),
3334: 
3335:     // from register interface
3336:     .we     (le0_le15_we),
3337:     .wd     (le0_le15_wd),
3338: 
3339:     // from internal hardware
3340:     .de     (1'b0),
3341:     .d      ('0  ),
3342: 
3343:     // to internal hardware
3344:     .qe     (),
3345:     .q      (reg2hw.le[15].q ),
3346: 
3347:     // to register interface (read)
3348:     .qs     (le0_le15_qs)
3349:   );
3350: 
3351: 
3352:   // F[le16]: 16:16
3353:   prim_subreg #(
3354:     .DW      (1),
3355:     .SWACCESS("RW"),
3356:     .RESVAL  (1'h0)
3357:   ) u_le0_le16 (
3358:     .clk_i   (clk_i    ),
3359:     .rst_ni  (rst_ni  ),
3360: 
3361:     // from register interface
3362:     .we     (le0_le16_we),
3363:     .wd     (le0_le16_wd),
3364: 
3365:     // from internal hardware
3366:     .de     (1'b0),
3367:     .d      ('0  ),
3368: 
3369:     // to internal hardware
3370:     .qe     (),
3371:     .q      (reg2hw.le[16].q ),
3372: 
3373:     // to register interface (read)
3374:     .qs     (le0_le16_qs)
3375:   );
3376: 
3377: 
3378:   // F[le17]: 17:17
3379:   prim_subreg #(
3380:     .DW      (1),
3381:     .SWACCESS("RW"),
3382:     .RESVAL  (1'h0)
3383:   ) u_le0_le17 (
3384:     .clk_i   (clk_i    ),
3385:     .rst_ni  (rst_ni  ),
3386: 
3387:     // from register interface
3388:     .we     (le0_le17_we),
3389:     .wd     (le0_le17_wd),
3390: 
3391:     // from internal hardware
3392:     .de     (1'b0),
3393:     .d      ('0  ),
3394: 
3395:     // to internal hardware
3396:     .qe     (),
3397:     .q      (reg2hw.le[17].q ),
3398: 
3399:     // to register interface (read)
3400:     .qs     (le0_le17_qs)
3401:   );
3402: 
3403: 
3404:   // F[le18]: 18:18
3405:   prim_subreg #(
3406:     .DW      (1),
3407:     .SWACCESS("RW"),
3408:     .RESVAL  (1'h0)
3409:   ) u_le0_le18 (
3410:     .clk_i   (clk_i    ),
3411:     .rst_ni  (rst_ni  ),
3412: 
3413:     // from register interface
3414:     .we     (le0_le18_we),
3415:     .wd     (le0_le18_wd),
3416: 
3417:     // from internal hardware
3418:     .de     (1'b0),
3419:     .d      ('0  ),
3420: 
3421:     // to internal hardware
3422:     .qe     (),
3423:     .q      (reg2hw.le[18].q ),
3424: 
3425:     // to register interface (read)
3426:     .qs     (le0_le18_qs)
3427:   );
3428: 
3429: 
3430:   // F[le19]: 19:19
3431:   prim_subreg #(
3432:     .DW      (1),
3433:     .SWACCESS("RW"),
3434:     .RESVAL  (1'h0)
3435:   ) u_le0_le19 (
3436:     .clk_i   (clk_i    ),
3437:     .rst_ni  (rst_ni  ),
3438: 
3439:     // from register interface
3440:     .we     (le0_le19_we),
3441:     .wd     (le0_le19_wd),
3442: 
3443:     // from internal hardware
3444:     .de     (1'b0),
3445:     .d      ('0  ),
3446: 
3447:     // to internal hardware
3448:     .qe     (),
3449:     .q      (reg2hw.le[19].q ),
3450: 
3451:     // to register interface (read)
3452:     .qs     (le0_le19_qs)
3453:   );
3454: 
3455: 
3456:   // F[le20]: 20:20
3457:   prim_subreg #(
3458:     .DW      (1),
3459:     .SWACCESS("RW"),
3460:     .RESVAL  (1'h0)
3461:   ) u_le0_le20 (
3462:     .clk_i   (clk_i    ),
3463:     .rst_ni  (rst_ni  ),
3464: 
3465:     // from register interface
3466:     .we     (le0_le20_we),
3467:     .wd     (le0_le20_wd),
3468: 
3469:     // from internal hardware
3470:     .de     (1'b0),
3471:     .d      ('0  ),
3472: 
3473:     // to internal hardware
3474:     .qe     (),
3475:     .q      (reg2hw.le[20].q ),
3476: 
3477:     // to register interface (read)
3478:     .qs     (le0_le20_qs)
3479:   );
3480: 
3481: 
3482:   // F[le21]: 21:21
3483:   prim_subreg #(
3484:     .DW      (1),
3485:     .SWACCESS("RW"),
3486:     .RESVAL  (1'h0)
3487:   ) u_le0_le21 (
3488:     .clk_i   (clk_i    ),
3489:     .rst_ni  (rst_ni  ),
3490: 
3491:     // from register interface
3492:     .we     (le0_le21_we),
3493:     .wd     (le0_le21_wd),
3494: 
3495:     // from internal hardware
3496:     .de     (1'b0),
3497:     .d      ('0  ),
3498: 
3499:     // to internal hardware
3500:     .qe     (),
3501:     .q      (reg2hw.le[21].q ),
3502: 
3503:     // to register interface (read)
3504:     .qs     (le0_le21_qs)
3505:   );
3506: 
3507: 
3508:   // F[le22]: 22:22
3509:   prim_subreg #(
3510:     .DW      (1),
3511:     .SWACCESS("RW"),
3512:     .RESVAL  (1'h0)
3513:   ) u_le0_le22 (
3514:     .clk_i   (clk_i    ),
3515:     .rst_ni  (rst_ni  ),
3516: 
3517:     // from register interface
3518:     .we     (le0_le22_we),
3519:     .wd     (le0_le22_wd),
3520: 
3521:     // from internal hardware
3522:     .de     (1'b0),
3523:     .d      ('0  ),
3524: 
3525:     // to internal hardware
3526:     .qe     (),
3527:     .q      (reg2hw.le[22].q ),
3528: 
3529:     // to register interface (read)
3530:     .qs     (le0_le22_qs)
3531:   );
3532: 
3533: 
3534:   // F[le23]: 23:23
3535:   prim_subreg #(
3536:     .DW      (1),
3537:     .SWACCESS("RW"),
3538:     .RESVAL  (1'h0)
3539:   ) u_le0_le23 (
3540:     .clk_i   (clk_i    ),
3541:     .rst_ni  (rst_ni  ),
3542: 
3543:     // from register interface
3544:     .we     (le0_le23_we),
3545:     .wd     (le0_le23_wd),
3546: 
3547:     // from internal hardware
3548:     .de     (1'b0),
3549:     .d      ('0  ),
3550: 
3551:     // to internal hardware
3552:     .qe     (),
3553:     .q      (reg2hw.le[23].q ),
3554: 
3555:     // to register interface (read)
3556:     .qs     (le0_le23_qs)
3557:   );
3558: 
3559: 
3560:   // F[le24]: 24:24
3561:   prim_subreg #(
3562:     .DW      (1),
3563:     .SWACCESS("RW"),
3564:     .RESVAL  (1'h0)
3565:   ) u_le0_le24 (
3566:     .clk_i   (clk_i    ),
3567:     .rst_ni  (rst_ni  ),
3568: 
3569:     // from register interface
3570:     .we     (le0_le24_we),
3571:     .wd     (le0_le24_wd),
3572: 
3573:     // from internal hardware
3574:     .de     (1'b0),
3575:     .d      ('0  ),
3576: 
3577:     // to internal hardware
3578:     .qe     (),
3579:     .q      (reg2hw.le[24].q ),
3580: 
3581:     // to register interface (read)
3582:     .qs     (le0_le24_qs)
3583:   );
3584: 
3585: 
3586:   // F[le25]: 25:25
3587:   prim_subreg #(
3588:     .DW      (1),
3589:     .SWACCESS("RW"),
3590:     .RESVAL  (1'h0)
3591:   ) u_le0_le25 (
3592:     .clk_i   (clk_i    ),
3593:     .rst_ni  (rst_ni  ),
3594: 
3595:     // from register interface
3596:     .we     (le0_le25_we),
3597:     .wd     (le0_le25_wd),
3598: 
3599:     // from internal hardware
3600:     .de     (1'b0),
3601:     .d      ('0  ),
3602: 
3603:     // to internal hardware
3604:     .qe     (),
3605:     .q      (reg2hw.le[25].q ),
3606: 
3607:     // to register interface (read)
3608:     .qs     (le0_le25_qs)
3609:   );
3610: 
3611: 
3612:   // F[le26]: 26:26
3613:   prim_subreg #(
3614:     .DW      (1),
3615:     .SWACCESS("RW"),
3616:     .RESVAL  (1'h0)
3617:   ) u_le0_le26 (
3618:     .clk_i   (clk_i    ),
3619:     .rst_ni  (rst_ni  ),
3620: 
3621:     // from register interface
3622:     .we     (le0_le26_we),
3623:     .wd     (le0_le26_wd),
3624: 
3625:     // from internal hardware
3626:     .de     (1'b0),
3627:     .d      ('0  ),
3628: 
3629:     // to internal hardware
3630:     .qe     (),
3631:     .q      (reg2hw.le[26].q ),
3632: 
3633:     // to register interface (read)
3634:     .qs     (le0_le26_qs)
3635:   );
3636: 
3637: 
3638:   // F[le27]: 27:27
3639:   prim_subreg #(
3640:     .DW      (1),
3641:     .SWACCESS("RW"),
3642:     .RESVAL  (1'h0)
3643:   ) u_le0_le27 (
3644:     .clk_i   (clk_i    ),
3645:     .rst_ni  (rst_ni  ),
3646: 
3647:     // from register interface
3648:     .we     (le0_le27_we),
3649:     .wd     (le0_le27_wd),
3650: 
3651:     // from internal hardware
3652:     .de     (1'b0),
3653:     .d      ('0  ),
3654: 
3655:     // to internal hardware
3656:     .qe     (),
3657:     .q      (reg2hw.le[27].q ),
3658: 
3659:     // to register interface (read)
3660:     .qs     (le0_le27_qs)
3661:   );
3662: 
3663: 
3664:   // F[le28]: 28:28
3665:   prim_subreg #(
3666:     .DW      (1),
3667:     .SWACCESS("RW"),
3668:     .RESVAL  (1'h0)
3669:   ) u_le0_le28 (
3670:     .clk_i   (clk_i    ),
3671:     .rst_ni  (rst_ni  ),
3672: 
3673:     // from register interface
3674:     .we     (le0_le28_we),
3675:     .wd     (le0_le28_wd),
3676: 
3677:     // from internal hardware
3678:     .de     (1'b0),
3679:     .d      ('0  ),
3680: 
3681:     // to internal hardware
3682:     .qe     (),
3683:     .q      (reg2hw.le[28].q ),
3684: 
3685:     // to register interface (read)
3686:     .qs     (le0_le28_qs)
3687:   );
3688: 
3689: 
3690:   // F[le29]: 29:29
3691:   prim_subreg #(
3692:     .DW      (1),
3693:     .SWACCESS("RW"),
3694:     .RESVAL  (1'h0)
3695:   ) u_le0_le29 (
3696:     .clk_i   (clk_i    ),
3697:     .rst_ni  (rst_ni  ),
3698: 
3699:     // from register interface
3700:     .we     (le0_le29_we),
3701:     .wd     (le0_le29_wd),
3702: 
3703:     // from internal hardware
3704:     .de     (1'b0),
3705:     .d      ('0  ),
3706: 
3707:     // to internal hardware
3708:     .qe     (),
3709:     .q      (reg2hw.le[29].q ),
3710: 
3711:     // to register interface (read)
3712:     .qs     (le0_le29_qs)
3713:   );
3714: 
3715: 
3716:   // F[le30]: 30:30
3717:   prim_subreg #(
3718:     .DW      (1),
3719:     .SWACCESS("RW"),
3720:     .RESVAL  (1'h0)
3721:   ) u_le0_le30 (
3722:     .clk_i   (clk_i    ),
3723:     .rst_ni  (rst_ni  ),
3724: 
3725:     // from register interface
3726:     .we     (le0_le30_we),
3727:     .wd     (le0_le30_wd),
3728: 
3729:     // from internal hardware
3730:     .de     (1'b0),
3731:     .d      ('0  ),
3732: 
3733:     // to internal hardware
3734:     .qe     (),
3735:     .q      (reg2hw.le[30].q ),
3736: 
3737:     // to register interface (read)
3738:     .qs     (le0_le30_qs)
3739:   );
3740: 
3741: 
3742:   // F[le31]: 31:31
3743:   prim_subreg #(
3744:     .DW      (1),
3745:     .SWACCESS("RW"),
3746:     .RESVAL  (1'h0)
3747:   ) u_le0_le31 (
3748:     .clk_i   (clk_i    ),
3749:     .rst_ni  (rst_ni  ),
3750: 
3751:     // from register interface
3752:     .we     (le0_le31_we),
3753:     .wd     (le0_le31_wd),
3754: 
3755:     // from internal hardware
3756:     .de     (1'b0),
3757:     .d      ('0  ),
3758: 
3759:     // to internal hardware
3760:     .qe     (),
3761:     .q      (reg2hw.le[31].q ),
3762: 
3763:     // to register interface (read)
3764:     .qs     (le0_le31_qs)
3765:   );
3766: 
3767: 
3768:   // Subregister 32 of Multireg le
3769:   // R[le1]: V(False)
3770: 
3771:   // F[le32]: 0:0
3772:   prim_subreg #(
3773:     .DW      (1),
3774:     .SWACCESS("RW"),
3775:     .RESVAL  (1'h0)
3776:   ) u_le1_le32 (
3777:     .clk_i   (clk_i    ),
3778:     .rst_ni  (rst_ni  ),
3779: 
3780:     // from register interface
3781:     .we     (le1_le32_we),
3782:     .wd     (le1_le32_wd),
3783: 
3784:     // from internal hardware
3785:     .de     (1'b0),
3786:     .d      ('0  ),
3787: 
3788:     // to internal hardware
3789:     .qe     (),
3790:     .q      (reg2hw.le[32].q ),
3791: 
3792:     // to register interface (read)
3793:     .qs     (le1_le32_qs)
3794:   );
3795: 
3796: 
3797:   // F[le33]: 1:1
3798:   prim_subreg #(
3799:     .DW      (1),
3800:     .SWACCESS("RW"),
3801:     .RESVAL  (1'h0)
3802:   ) u_le1_le33 (
3803:     .clk_i   (clk_i    ),
3804:     .rst_ni  (rst_ni  ),
3805: 
3806:     // from register interface
3807:     .we     (le1_le33_we),
3808:     .wd     (le1_le33_wd),
3809: 
3810:     // from internal hardware
3811:     .de     (1'b0),
3812:     .d      ('0  ),
3813: 
3814:     // to internal hardware
3815:     .qe     (),
3816:     .q      (reg2hw.le[33].q ),
3817: 
3818:     // to register interface (read)
3819:     .qs     (le1_le33_qs)
3820:   );
3821: 
3822: 
3823:   // F[le34]: 2:2
3824:   prim_subreg #(
3825:     .DW      (1),
3826:     .SWACCESS("RW"),
3827:     .RESVAL  (1'h0)
3828:   ) u_le1_le34 (
3829:     .clk_i   (clk_i    ),
3830:     .rst_ni  (rst_ni  ),
3831: 
3832:     // from register interface
3833:     .we     (le1_le34_we),
3834:     .wd     (le1_le34_wd),
3835: 
3836:     // from internal hardware
3837:     .de     (1'b0),
3838:     .d      ('0  ),
3839: 
3840:     // to internal hardware
3841:     .qe     (),
3842:     .q      (reg2hw.le[34].q ),
3843: 
3844:     // to register interface (read)
3845:     .qs     (le1_le34_qs)
3846:   );
3847: 
3848: 
3849:   // F[le35]: 3:3
3850:   prim_subreg #(
3851:     .DW      (1),
3852:     .SWACCESS("RW"),
3853:     .RESVAL  (1'h0)
3854:   ) u_le1_le35 (
3855:     .clk_i   (clk_i    ),
3856:     .rst_ni  (rst_ni  ),
3857: 
3858:     // from register interface
3859:     .we     (le1_le35_we),
3860:     .wd     (le1_le35_wd),
3861: 
3862:     // from internal hardware
3863:     .de     (1'b0),
3864:     .d      ('0  ),
3865: 
3866:     // to internal hardware
3867:     .qe     (),
3868:     .q      (reg2hw.le[35].q ),
3869: 
3870:     // to register interface (read)
3871:     .qs     (le1_le35_qs)
3872:   );
3873: 
3874: 
3875:   // F[le36]: 4:4
3876:   prim_subreg #(
3877:     .DW      (1),
3878:     .SWACCESS("RW"),
3879:     .RESVAL  (1'h0)
3880:   ) u_le1_le36 (
3881:     .clk_i   (clk_i    ),
3882:     .rst_ni  (rst_ni  ),
3883: 
3884:     // from register interface
3885:     .we     (le1_le36_we),
3886:     .wd     (le1_le36_wd),
3887: 
3888:     // from internal hardware
3889:     .de     (1'b0),
3890:     .d      ('0  ),
3891: 
3892:     // to internal hardware
3893:     .qe     (),
3894:     .q      (reg2hw.le[36].q ),
3895: 
3896:     // to register interface (read)
3897:     .qs     (le1_le36_qs)
3898:   );
3899: 
3900: 
3901:   // F[le37]: 5:5
3902:   prim_subreg #(
3903:     .DW      (1),
3904:     .SWACCESS("RW"),
3905:     .RESVAL  (1'h0)
3906:   ) u_le1_le37 (
3907:     .clk_i   (clk_i    ),
3908:     .rst_ni  (rst_ni  ),
3909: 
3910:     // from register interface
3911:     .we     (le1_le37_we),
3912:     .wd     (le1_le37_wd),
3913: 
3914:     // from internal hardware
3915:     .de     (1'b0),
3916:     .d      ('0  ),
3917: 
3918:     // to internal hardware
3919:     .qe     (),
3920:     .q      (reg2hw.le[37].q ),
3921: 
3922:     // to register interface (read)
3923:     .qs     (le1_le37_qs)
3924:   );
3925: 
3926: 
3927:   // F[le38]: 6:6
3928:   prim_subreg #(
3929:     .DW      (1),
3930:     .SWACCESS("RW"),
3931:     .RESVAL  (1'h0)
3932:   ) u_le1_le38 (
3933:     .clk_i   (clk_i    ),
3934:     .rst_ni  (rst_ni  ),
3935: 
3936:     // from register interface
3937:     .we     (le1_le38_we),
3938:     .wd     (le1_le38_wd),
3939: 
3940:     // from internal hardware
3941:     .de     (1'b0),
3942:     .d      ('0  ),
3943: 
3944:     // to internal hardware
3945:     .qe     (),
3946:     .q      (reg2hw.le[38].q ),
3947: 
3948:     // to register interface (read)
3949:     .qs     (le1_le38_qs)
3950:   );
3951: 
3952: 
3953:   // F[le39]: 7:7
3954:   prim_subreg #(
3955:     .DW      (1),
3956:     .SWACCESS("RW"),
3957:     .RESVAL  (1'h0)
3958:   ) u_le1_le39 (
3959:     .clk_i   (clk_i    ),
3960:     .rst_ni  (rst_ni  ),
3961: 
3962:     // from register interface
3963:     .we     (le1_le39_we),
3964:     .wd     (le1_le39_wd),
3965: 
3966:     // from internal hardware
3967:     .de     (1'b0),
3968:     .d      ('0  ),
3969: 
3970:     // to internal hardware
3971:     .qe     (),
3972:     .q      (reg2hw.le[39].q ),
3973: 
3974:     // to register interface (read)
3975:     .qs     (le1_le39_qs)
3976:   );
3977: 
3978: 
3979:   // F[le40]: 8:8
3980:   prim_subreg #(
3981:     .DW      (1),
3982:     .SWACCESS("RW"),
3983:     .RESVAL  (1'h0)
3984:   ) u_le1_le40 (
3985:     .clk_i   (clk_i    ),
3986:     .rst_ni  (rst_ni  ),
3987: 
3988:     // from register interface
3989:     .we     (le1_le40_we),
3990:     .wd     (le1_le40_wd),
3991: 
3992:     // from internal hardware
3993:     .de     (1'b0),
3994:     .d      ('0  ),
3995: 
3996:     // to internal hardware
3997:     .qe     (),
3998:     .q      (reg2hw.le[40].q ),
3999: 
4000:     // to register interface (read)
4001:     .qs     (le1_le40_qs)
4002:   );
4003: 
4004: 
4005:   // F[le41]: 9:9
4006:   prim_subreg #(
4007:     .DW      (1),
4008:     .SWACCESS("RW"),
4009:     .RESVAL  (1'h0)
4010:   ) u_le1_le41 (
4011:     .clk_i   (clk_i    ),
4012:     .rst_ni  (rst_ni  ),
4013: 
4014:     // from register interface
4015:     .we     (le1_le41_we),
4016:     .wd     (le1_le41_wd),
4017: 
4018:     // from internal hardware
4019:     .de     (1'b0),
4020:     .d      ('0  ),
4021: 
4022:     // to internal hardware
4023:     .qe     (),
4024:     .q      (reg2hw.le[41].q ),
4025: 
4026:     // to register interface (read)
4027:     .qs     (le1_le41_qs)
4028:   );
4029: 
4030: 
4031:   // F[le42]: 10:10
4032:   prim_subreg #(
4033:     .DW      (1),
4034:     .SWACCESS("RW"),
4035:     .RESVAL  (1'h0)
4036:   ) u_le1_le42 (
4037:     .clk_i   (clk_i    ),
4038:     .rst_ni  (rst_ni  ),
4039: 
4040:     // from register interface
4041:     .we     (le1_le42_we),
4042:     .wd     (le1_le42_wd),
4043: 
4044:     // from internal hardware
4045:     .de     (1'b0),
4046:     .d      ('0  ),
4047: 
4048:     // to internal hardware
4049:     .qe     (),
4050:     .q      (reg2hw.le[42].q ),
4051: 
4052:     // to register interface (read)
4053:     .qs     (le1_le42_qs)
4054:   );
4055: 
4056: 
4057:   // F[le43]: 11:11
4058:   prim_subreg #(
4059:     .DW      (1),
4060:     .SWACCESS("RW"),
4061:     .RESVAL  (1'h0)
4062:   ) u_le1_le43 (
4063:     .clk_i   (clk_i    ),
4064:     .rst_ni  (rst_ni  ),
4065: 
4066:     // from register interface
4067:     .we     (le1_le43_we),
4068:     .wd     (le1_le43_wd),
4069: 
4070:     // from internal hardware
4071:     .de     (1'b0),
4072:     .d      ('0  ),
4073: 
4074:     // to internal hardware
4075:     .qe     (),
4076:     .q      (reg2hw.le[43].q ),
4077: 
4078:     // to register interface (read)
4079:     .qs     (le1_le43_qs)
4080:   );
4081: 
4082: 
4083:   // F[le44]: 12:12
4084:   prim_subreg #(
4085:     .DW      (1),
4086:     .SWACCESS("RW"),
4087:     .RESVAL  (1'h0)
4088:   ) u_le1_le44 (
4089:     .clk_i   (clk_i    ),
4090:     .rst_ni  (rst_ni  ),
4091: 
4092:     // from register interface
4093:     .we     (le1_le44_we),
4094:     .wd     (le1_le44_wd),
4095: 
4096:     // from internal hardware
4097:     .de     (1'b0),
4098:     .d      ('0  ),
4099: 
4100:     // to internal hardware
4101:     .qe     (),
4102:     .q      (reg2hw.le[44].q ),
4103: 
4104:     // to register interface (read)
4105:     .qs     (le1_le44_qs)
4106:   );
4107: 
4108: 
4109:   // F[le45]: 13:13
4110:   prim_subreg #(
4111:     .DW      (1),
4112:     .SWACCESS("RW"),
4113:     .RESVAL  (1'h0)
4114:   ) u_le1_le45 (
4115:     .clk_i   (clk_i    ),
4116:     .rst_ni  (rst_ni  ),
4117: 
4118:     // from register interface
4119:     .we     (le1_le45_we),
4120:     .wd     (le1_le45_wd),
4121: 
4122:     // from internal hardware
4123:     .de     (1'b0),
4124:     .d      ('0  ),
4125: 
4126:     // to internal hardware
4127:     .qe     (),
4128:     .q      (reg2hw.le[45].q ),
4129: 
4130:     // to register interface (read)
4131:     .qs     (le1_le45_qs)
4132:   );
4133: 
4134: 
4135:   // F[le46]: 14:14
4136:   prim_subreg #(
4137:     .DW      (1),
4138:     .SWACCESS("RW"),
4139:     .RESVAL  (1'h0)
4140:   ) u_le1_le46 (
4141:     .clk_i   (clk_i    ),
4142:     .rst_ni  (rst_ni  ),
4143: 
4144:     // from register interface
4145:     .we     (le1_le46_we),
4146:     .wd     (le1_le46_wd),
4147: 
4148:     // from internal hardware
4149:     .de     (1'b0),
4150:     .d      ('0  ),
4151: 
4152:     // to internal hardware
4153:     .qe     (),
4154:     .q      (reg2hw.le[46].q ),
4155: 
4156:     // to register interface (read)
4157:     .qs     (le1_le46_qs)
4158:   );
4159: 
4160: 
4161:   // F[le47]: 15:15
4162:   prim_subreg #(
4163:     .DW      (1),
4164:     .SWACCESS("RW"),
4165:     .RESVAL  (1'h0)
4166:   ) u_le1_le47 (
4167:     .clk_i   (clk_i    ),
4168:     .rst_ni  (rst_ni  ),
4169: 
4170:     // from register interface
4171:     .we     (le1_le47_we),
4172:     .wd     (le1_le47_wd),
4173: 
4174:     // from internal hardware
4175:     .de     (1'b0),
4176:     .d      ('0  ),
4177: 
4178:     // to internal hardware
4179:     .qe     (),
4180:     .q      (reg2hw.le[47].q ),
4181: 
4182:     // to register interface (read)
4183:     .qs     (le1_le47_qs)
4184:   );
4185: 
4186: 
4187:   // F[le48]: 16:16
4188:   prim_subreg #(
4189:     .DW      (1),
4190:     .SWACCESS("RW"),
4191:     .RESVAL  (1'h0)
4192:   ) u_le1_le48 (
4193:     .clk_i   (clk_i    ),
4194:     .rst_ni  (rst_ni  ),
4195: 
4196:     // from register interface
4197:     .we     (le1_le48_we),
4198:     .wd     (le1_le48_wd),
4199: 
4200:     // from internal hardware
4201:     .de     (1'b0),
4202:     .d      ('0  ),
4203: 
4204:     // to internal hardware
4205:     .qe     (),
4206:     .q      (reg2hw.le[48].q ),
4207: 
4208:     // to register interface (read)
4209:     .qs     (le1_le48_qs)
4210:   );
4211: 
4212: 
4213:   // F[le49]: 17:17
4214:   prim_subreg #(
4215:     .DW      (1),
4216:     .SWACCESS("RW"),
4217:     .RESVAL  (1'h0)
4218:   ) u_le1_le49 (
4219:     .clk_i   (clk_i    ),
4220:     .rst_ni  (rst_ni  ),
4221: 
4222:     // from register interface
4223:     .we     (le1_le49_we),
4224:     .wd     (le1_le49_wd),
4225: 
4226:     // from internal hardware
4227:     .de     (1'b0),
4228:     .d      ('0  ),
4229: 
4230:     // to internal hardware
4231:     .qe     (),
4232:     .q      (reg2hw.le[49].q ),
4233: 
4234:     // to register interface (read)
4235:     .qs     (le1_le49_qs)
4236:   );
4237: 
4238: 
4239:   // F[le50]: 18:18
4240:   prim_subreg #(
4241:     .DW      (1),
4242:     .SWACCESS("RW"),
4243:     .RESVAL  (1'h0)
4244:   ) u_le1_le50 (
4245:     .clk_i   (clk_i    ),
4246:     .rst_ni  (rst_ni  ),
4247: 
4248:     // from register interface
4249:     .we     (le1_le50_we),
4250:     .wd     (le1_le50_wd),
4251: 
4252:     // from internal hardware
4253:     .de     (1'b0),
4254:     .d      ('0  ),
4255: 
4256:     // to internal hardware
4257:     .qe     (),
4258:     .q      (reg2hw.le[50].q ),
4259: 
4260:     // to register interface (read)
4261:     .qs     (le1_le50_qs)
4262:   );
4263: 
4264: 
4265:   // F[le51]: 19:19
4266:   prim_subreg #(
4267:     .DW      (1),
4268:     .SWACCESS("RW"),
4269:     .RESVAL  (1'h0)
4270:   ) u_le1_le51 (
4271:     .clk_i   (clk_i    ),
4272:     .rst_ni  (rst_ni  ),
4273: 
4274:     // from register interface
4275:     .we     (le1_le51_we),
4276:     .wd     (le1_le51_wd),
4277: 
4278:     // from internal hardware
4279:     .de     (1'b0),
4280:     .d      ('0  ),
4281: 
4282:     // to internal hardware
4283:     .qe     (),
4284:     .q      (reg2hw.le[51].q ),
4285: 
4286:     // to register interface (read)
4287:     .qs     (le1_le51_qs)
4288:   );
4289: 
4290: 
4291:   // F[le52]: 20:20
4292:   prim_subreg #(
4293:     .DW      (1),
4294:     .SWACCESS("RW"),
4295:     .RESVAL  (1'h0)
4296:   ) u_le1_le52 (
4297:     .clk_i   (clk_i    ),
4298:     .rst_ni  (rst_ni  ),
4299: 
4300:     // from register interface
4301:     .we     (le1_le52_we),
4302:     .wd     (le1_le52_wd),
4303: 
4304:     // from internal hardware
4305:     .de     (1'b0),
4306:     .d      ('0  ),
4307: 
4308:     // to internal hardware
4309:     .qe     (),
4310:     .q      (reg2hw.le[52].q ),
4311: 
4312:     // to register interface (read)
4313:     .qs     (le1_le52_qs)
4314:   );
4315: 
4316: 
4317:   // F[le53]: 21:21
4318:   prim_subreg #(
4319:     .DW      (1),
4320:     .SWACCESS("RW"),
4321:     .RESVAL  (1'h0)
4322:   ) u_le1_le53 (
4323:     .clk_i   (clk_i    ),
4324:     .rst_ni  (rst_ni  ),
4325: 
4326:     // from register interface
4327:     .we     (le1_le53_we),
4328:     .wd     (le1_le53_wd),
4329: 
4330:     // from internal hardware
4331:     .de     (1'b0),
4332:     .d      ('0  ),
4333: 
4334:     // to internal hardware
4335:     .qe     (),
4336:     .q      (reg2hw.le[53].q ),
4337: 
4338:     // to register interface (read)
4339:     .qs     (le1_le53_qs)
4340:   );
4341: 
4342: 
4343:   // F[le54]: 22:22
4344:   prim_subreg #(
4345:     .DW      (1),
4346:     .SWACCESS("RW"),
4347:     .RESVAL  (1'h0)
4348:   ) u_le1_le54 (
4349:     .clk_i   (clk_i    ),
4350:     .rst_ni  (rst_ni  ),
4351: 
4352:     // from register interface
4353:     .we     (le1_le54_we),
4354:     .wd     (le1_le54_wd),
4355: 
4356:     // from internal hardware
4357:     .de     (1'b0),
4358:     .d      ('0  ),
4359: 
4360:     // to internal hardware
4361:     .qe     (),
4362:     .q      (reg2hw.le[54].q ),
4363: 
4364:     // to register interface (read)
4365:     .qs     (le1_le54_qs)
4366:   );
4367: 
4368: 
4369:   // F[le55]: 23:23
4370:   prim_subreg #(
4371:     .DW      (1),
4372:     .SWACCESS("RW"),
4373:     .RESVAL  (1'h0)
4374:   ) u_le1_le55 (
4375:     .clk_i   (clk_i    ),
4376:     .rst_ni  (rst_ni  ),
4377: 
4378:     // from register interface
4379:     .we     (le1_le55_we),
4380:     .wd     (le1_le55_wd),
4381: 
4382:     // from internal hardware
4383:     .de     (1'b0),
4384:     .d      ('0  ),
4385: 
4386:     // to internal hardware
4387:     .qe     (),
4388:     .q      (reg2hw.le[55].q ),
4389: 
4390:     // to register interface (read)
4391:     .qs     (le1_le55_qs)
4392:   );
4393: 
4394: 
4395:   // F[le56]: 24:24
4396:   prim_subreg #(
4397:     .DW      (1),
4398:     .SWACCESS("RW"),
4399:     .RESVAL  (1'h0)
4400:   ) u_le1_le56 (
4401:     .clk_i   (clk_i    ),
4402:     .rst_ni  (rst_ni  ),
4403: 
4404:     // from register interface
4405:     .we     (le1_le56_we),
4406:     .wd     (le1_le56_wd),
4407: 
4408:     // from internal hardware
4409:     .de     (1'b0),
4410:     .d      ('0  ),
4411: 
4412:     // to internal hardware
4413:     .qe     (),
4414:     .q      (reg2hw.le[56].q ),
4415: 
4416:     // to register interface (read)
4417:     .qs     (le1_le56_qs)
4418:   );
4419: 
4420: 
4421:   // F[le57]: 25:25
4422:   prim_subreg #(
4423:     .DW      (1),
4424:     .SWACCESS("RW"),
4425:     .RESVAL  (1'h0)
4426:   ) u_le1_le57 (
4427:     .clk_i   (clk_i    ),
4428:     .rst_ni  (rst_ni  ),
4429: 
4430:     // from register interface
4431:     .we     (le1_le57_we),
4432:     .wd     (le1_le57_wd),
4433: 
4434:     // from internal hardware
4435:     .de     (1'b0),
4436:     .d      ('0  ),
4437: 
4438:     // to internal hardware
4439:     .qe     (),
4440:     .q      (reg2hw.le[57].q ),
4441: 
4442:     // to register interface (read)
4443:     .qs     (le1_le57_qs)
4444:   );
4445: 
4446: 
4447:   // F[le58]: 26:26
4448:   prim_subreg #(
4449:     .DW      (1),
4450:     .SWACCESS("RW"),
4451:     .RESVAL  (1'h0)
4452:   ) u_le1_le58 (
4453:     .clk_i   (clk_i    ),
4454:     .rst_ni  (rst_ni  ),
4455: 
4456:     // from register interface
4457:     .we     (le1_le58_we),
4458:     .wd     (le1_le58_wd),
4459: 
4460:     // from internal hardware
4461:     .de     (1'b0),
4462:     .d      ('0  ),
4463: 
4464:     // to internal hardware
4465:     .qe     (),
4466:     .q      (reg2hw.le[58].q ),
4467: 
4468:     // to register interface (read)
4469:     .qs     (le1_le58_qs)
4470:   );
4471: 
4472: 
4473:   // F[le59]: 27:27
4474:   prim_subreg #(
4475:     .DW      (1),
4476:     .SWACCESS("RW"),
4477:     .RESVAL  (1'h0)
4478:   ) u_le1_le59 (
4479:     .clk_i   (clk_i    ),
4480:     .rst_ni  (rst_ni  ),
4481: 
4482:     // from register interface
4483:     .we     (le1_le59_we),
4484:     .wd     (le1_le59_wd),
4485: 
4486:     // from internal hardware
4487:     .de     (1'b0),
4488:     .d      ('0  ),
4489: 
4490:     // to internal hardware
4491:     .qe     (),
4492:     .q      (reg2hw.le[59].q ),
4493: 
4494:     // to register interface (read)
4495:     .qs     (le1_le59_qs)
4496:   );
4497: 
4498: 
4499:   // F[le60]: 28:28
4500:   prim_subreg #(
4501:     .DW      (1),
4502:     .SWACCESS("RW"),
4503:     .RESVAL  (1'h0)
4504:   ) u_le1_le60 (
4505:     .clk_i   (clk_i    ),
4506:     .rst_ni  (rst_ni  ),
4507: 
4508:     // from register interface
4509:     .we     (le1_le60_we),
4510:     .wd     (le1_le60_wd),
4511: 
4512:     // from internal hardware
4513:     .de     (1'b0),
4514:     .d      ('0  ),
4515: 
4516:     // to internal hardware
4517:     .qe     (),
4518:     .q      (reg2hw.le[60].q ),
4519: 
4520:     // to register interface (read)
4521:     .qs     (le1_le60_qs)
4522:   );
4523: 
4524: 
4525:   // F[le61]: 29:29
4526:   prim_subreg #(
4527:     .DW      (1),
4528:     .SWACCESS("RW"),
4529:     .RESVAL  (1'h0)
4530:   ) u_le1_le61 (
4531:     .clk_i   (clk_i    ),
4532:     .rst_ni  (rst_ni  ),
4533: 
4534:     // from register interface
4535:     .we     (le1_le61_we),
4536:     .wd     (le1_le61_wd),
4537: 
4538:     // from internal hardware
4539:     .de     (1'b0),
4540:     .d      ('0  ),
4541: 
4542:     // to internal hardware
4543:     .qe     (),
4544:     .q      (reg2hw.le[61].q ),
4545: 
4546:     // to register interface (read)
4547:     .qs     (le1_le61_qs)
4548:   );
4549: 
4550: 
4551:   // F[le62]: 30:30
4552:   prim_subreg #(
4553:     .DW      (1),
4554:     .SWACCESS("RW"),
4555:     .RESVAL  (1'h0)
4556:   ) u_le1_le62 (
4557:     .clk_i   (clk_i    ),
4558:     .rst_ni  (rst_ni  ),
4559: 
4560:     // from register interface
4561:     .we     (le1_le62_we),
4562:     .wd     (le1_le62_wd),
4563: 
4564:     // from internal hardware
4565:     .de     (1'b0),
4566:     .d      ('0  ),
4567: 
4568:     // to internal hardware
4569:     .qe     (),
4570:     .q      (reg2hw.le[62].q ),
4571: 
4572:     // to register interface (read)
4573:     .qs     (le1_le62_qs)
4574:   );
4575: 
4576: 
4577:   // F[le63]: 31:31
4578:   prim_subreg #(
4579:     .DW      (1),
4580:     .SWACCESS("RW"),
4581:     .RESVAL  (1'h0)
4582:   ) u_le1_le63 (
4583:     .clk_i   (clk_i    ),
4584:     .rst_ni  (rst_ni  ),
4585: 
4586:     // from register interface
4587:     .we     (le1_le63_we),
4588:     .wd     (le1_le63_wd),
4589: 
4590:     // from internal hardware
4591:     .de     (1'b0),
4592:     .d      ('0  ),
4593: 
4594:     // to internal hardware
4595:     .qe     (),
4596:     .q      (reg2hw.le[63].q ),
4597: 
4598:     // to register interface (read)
4599:     .qs     (le1_le63_qs)
4600:   );
4601: 
4602: 
4603:   // Subregister 64 of Multireg le
4604:   // R[le2]: V(False)
4605: 
4606:   // F[le64]: 0:0
4607:   prim_subreg #(
4608:     .DW      (1),
4609:     .SWACCESS("RW"),
4610:     .RESVAL  (1'h0)
4611:   ) u_le2_le64 (
4612:     .clk_i   (clk_i    ),
4613:     .rst_ni  (rst_ni  ),
4614: 
4615:     // from register interface
4616:     .we     (le2_le64_we),
4617:     .wd     (le2_le64_wd),
4618: 
4619:     // from internal hardware
4620:     .de     (1'b0),
4621:     .d      ('0  ),
4622: 
4623:     // to internal hardware
4624:     .qe     (),
4625:     .q      (reg2hw.le[64].q ),
4626: 
4627:     // to register interface (read)
4628:     .qs     (le2_le64_qs)
4629:   );
4630: 
4631: 
4632:   // F[le65]: 1:1
4633:   prim_subreg #(
4634:     .DW      (1),
4635:     .SWACCESS("RW"),
4636:     .RESVAL  (1'h0)
4637:   ) u_le2_le65 (
4638:     .clk_i   (clk_i    ),
4639:     .rst_ni  (rst_ni  ),
4640: 
4641:     // from register interface
4642:     .we     (le2_le65_we),
4643:     .wd     (le2_le65_wd),
4644: 
4645:     // from internal hardware
4646:     .de     (1'b0),
4647:     .d      ('0  ),
4648: 
4649:     // to internal hardware
4650:     .qe     (),
4651:     .q      (reg2hw.le[65].q ),
4652: 
4653:     // to register interface (read)
4654:     .qs     (le2_le65_qs)
4655:   );
4656: 
4657: 
4658:   // F[le66]: 2:2
4659:   prim_subreg #(
4660:     .DW      (1),
4661:     .SWACCESS("RW"),
4662:     .RESVAL  (1'h0)
4663:   ) u_le2_le66 (
4664:     .clk_i   (clk_i    ),
4665:     .rst_ni  (rst_ni  ),
4666: 
4667:     // from register interface
4668:     .we     (le2_le66_we),
4669:     .wd     (le2_le66_wd),
4670: 
4671:     // from internal hardware
4672:     .de     (1'b0),
4673:     .d      ('0  ),
4674: 
4675:     // to internal hardware
4676:     .qe     (),
4677:     .q      (reg2hw.le[66].q ),
4678: 
4679:     // to register interface (read)
4680:     .qs     (le2_le66_qs)
4681:   );
4682: 
4683: 
4684:   // F[le67]: 3:3
4685:   prim_subreg #(
4686:     .DW      (1),
4687:     .SWACCESS("RW"),
4688:     .RESVAL  (1'h0)
4689:   ) u_le2_le67 (
4690:     .clk_i   (clk_i    ),
4691:     .rst_ni  (rst_ni  ),
4692: 
4693:     // from register interface
4694:     .we     (le2_le67_we),
4695:     .wd     (le2_le67_wd),
4696: 
4697:     // from internal hardware
4698:     .de     (1'b0),
4699:     .d      ('0  ),
4700: 
4701:     // to internal hardware
4702:     .qe     (),
4703:     .q      (reg2hw.le[67].q ),
4704: 
4705:     // to register interface (read)
4706:     .qs     (le2_le67_qs)
4707:   );
4708: 
4709: 
4710:   // F[le68]: 4:4
4711:   prim_subreg #(
4712:     .DW      (1),
4713:     .SWACCESS("RW"),
4714:     .RESVAL  (1'h0)
4715:   ) u_le2_le68 (
4716:     .clk_i   (clk_i    ),
4717:     .rst_ni  (rst_ni  ),
4718: 
4719:     // from register interface
4720:     .we     (le2_le68_we),
4721:     .wd     (le2_le68_wd),
4722: 
4723:     // from internal hardware
4724:     .de     (1'b0),
4725:     .d      ('0  ),
4726: 
4727:     // to internal hardware
4728:     .qe     (),
4729:     .q      (reg2hw.le[68].q ),
4730: 
4731:     // to register interface (read)
4732:     .qs     (le2_le68_qs)
4733:   );
4734: 
4735: 
4736:   // F[le69]: 5:5
4737:   prim_subreg #(
4738:     .DW      (1),
4739:     .SWACCESS("RW"),
4740:     .RESVAL  (1'h0)
4741:   ) u_le2_le69 (
4742:     .clk_i   (clk_i    ),
4743:     .rst_ni  (rst_ni  ),
4744: 
4745:     // from register interface
4746:     .we     (le2_le69_we),
4747:     .wd     (le2_le69_wd),
4748: 
4749:     // from internal hardware
4750:     .de     (1'b0),
4751:     .d      ('0  ),
4752: 
4753:     // to internal hardware
4754:     .qe     (),
4755:     .q      (reg2hw.le[69].q ),
4756: 
4757:     // to register interface (read)
4758:     .qs     (le2_le69_qs)
4759:   );
4760: 
4761: 
4762:   // F[le70]: 6:6
4763:   prim_subreg #(
4764:     .DW      (1),
4765:     .SWACCESS("RW"),
4766:     .RESVAL  (1'h0)
4767:   ) u_le2_le70 (
4768:     .clk_i   (clk_i    ),
4769:     .rst_ni  (rst_ni  ),
4770: 
4771:     // from register interface
4772:     .we     (le2_le70_we),
4773:     .wd     (le2_le70_wd),
4774: 
4775:     // from internal hardware
4776:     .de     (1'b0),
4777:     .d      ('0  ),
4778: 
4779:     // to internal hardware
4780:     .qe     (),
4781:     .q      (reg2hw.le[70].q ),
4782: 
4783:     // to register interface (read)
4784:     .qs     (le2_le70_qs)
4785:   );
4786: 
4787: 
4788:   // F[le71]: 7:7
4789:   prim_subreg #(
4790:     .DW      (1),
4791:     .SWACCESS("RW"),
4792:     .RESVAL  (1'h0)
4793:   ) u_le2_le71 (
4794:     .clk_i   (clk_i    ),
4795:     .rst_ni  (rst_ni  ),
4796: 
4797:     // from register interface
4798:     .we     (le2_le71_we),
4799:     .wd     (le2_le71_wd),
4800: 
4801:     // from internal hardware
4802:     .de     (1'b0),
4803:     .d      ('0  ),
4804: 
4805:     // to internal hardware
4806:     .qe     (),
4807:     .q      (reg2hw.le[71].q ),
4808: 
4809:     // to register interface (read)
4810:     .qs     (le2_le71_qs)
4811:   );
4812: 
4813: 
4814:   // F[le72]: 8:8
4815:   prim_subreg #(
4816:     .DW      (1),
4817:     .SWACCESS("RW"),
4818:     .RESVAL  (1'h0)
4819:   ) u_le2_le72 (
4820:     .clk_i   (clk_i    ),
4821:     .rst_ni  (rst_ni  ),
4822: 
4823:     // from register interface
4824:     .we     (le2_le72_we),
4825:     .wd     (le2_le72_wd),
4826: 
4827:     // from internal hardware
4828:     .de     (1'b0),
4829:     .d      ('0  ),
4830: 
4831:     // to internal hardware
4832:     .qe     (),
4833:     .q      (reg2hw.le[72].q ),
4834: 
4835:     // to register interface (read)
4836:     .qs     (le2_le72_qs)
4837:   );
4838: 
4839: 
4840:   // F[le73]: 9:9
4841:   prim_subreg #(
4842:     .DW      (1),
4843:     .SWACCESS("RW"),
4844:     .RESVAL  (1'h0)
4845:   ) u_le2_le73 (
4846:     .clk_i   (clk_i    ),
4847:     .rst_ni  (rst_ni  ),
4848: 
4849:     // from register interface
4850:     .we     (le2_le73_we),
4851:     .wd     (le2_le73_wd),
4852: 
4853:     // from internal hardware
4854:     .de     (1'b0),
4855:     .d      ('0  ),
4856: 
4857:     // to internal hardware
4858:     .qe     (),
4859:     .q      (reg2hw.le[73].q ),
4860: 
4861:     // to register interface (read)
4862:     .qs     (le2_le73_qs)
4863:   );
4864: 
4865: 
4866:   // F[le74]: 10:10
4867:   prim_subreg #(
4868:     .DW      (1),
4869:     .SWACCESS("RW"),
4870:     .RESVAL  (1'h0)
4871:   ) u_le2_le74 (
4872:     .clk_i   (clk_i    ),
4873:     .rst_ni  (rst_ni  ),
4874: 
4875:     // from register interface
4876:     .we     (le2_le74_we),
4877:     .wd     (le2_le74_wd),
4878: 
4879:     // from internal hardware
4880:     .de     (1'b0),
4881:     .d      ('0  ),
4882: 
4883:     // to internal hardware
4884:     .qe     (),
4885:     .q      (reg2hw.le[74].q ),
4886: 
4887:     // to register interface (read)
4888:     .qs     (le2_le74_qs)
4889:   );
4890: 
4891: 
4892:   // F[le75]: 11:11
4893:   prim_subreg #(
4894:     .DW      (1),
4895:     .SWACCESS("RW"),
4896:     .RESVAL  (1'h0)
4897:   ) u_le2_le75 (
4898:     .clk_i   (clk_i    ),
4899:     .rst_ni  (rst_ni  ),
4900: 
4901:     // from register interface
4902:     .we     (le2_le75_we),
4903:     .wd     (le2_le75_wd),
4904: 
4905:     // from internal hardware
4906:     .de     (1'b0),
4907:     .d      ('0  ),
4908: 
4909:     // to internal hardware
4910:     .qe     (),
4911:     .q      (reg2hw.le[75].q ),
4912: 
4913:     // to register interface (read)
4914:     .qs     (le2_le75_qs)
4915:   );
4916: 
4917: 
4918:   // F[le76]: 12:12
4919:   prim_subreg #(
4920:     .DW      (1),
4921:     .SWACCESS("RW"),
4922:     .RESVAL  (1'h0)
4923:   ) u_le2_le76 (
4924:     .clk_i   (clk_i    ),
4925:     .rst_ni  (rst_ni  ),
4926: 
4927:     // from register interface
4928:     .we     (le2_le76_we),
4929:     .wd     (le2_le76_wd),
4930: 
4931:     // from internal hardware
4932:     .de     (1'b0),
4933:     .d      ('0  ),
4934: 
4935:     // to internal hardware
4936:     .qe     (),
4937:     .q      (reg2hw.le[76].q ),
4938: 
4939:     // to register interface (read)
4940:     .qs     (le2_le76_qs)
4941:   );
4942: 
4943: 
4944:   // F[le77]: 13:13
4945:   prim_subreg #(
4946:     .DW      (1),
4947:     .SWACCESS("RW"),
4948:     .RESVAL  (1'h0)
4949:   ) u_le2_le77 (
4950:     .clk_i   (clk_i    ),
4951:     .rst_ni  (rst_ni  ),
4952: 
4953:     // from register interface
4954:     .we     (le2_le77_we),
4955:     .wd     (le2_le77_wd),
4956: 
4957:     // from internal hardware
4958:     .de     (1'b0),
4959:     .d      ('0  ),
4960: 
4961:     // to internal hardware
4962:     .qe     (),
4963:     .q      (reg2hw.le[77].q ),
4964: 
4965:     // to register interface (read)
4966:     .qs     (le2_le77_qs)
4967:   );
4968: 
4969: 
4970:   // F[le78]: 14:14
4971:   prim_subreg #(
4972:     .DW      (1),
4973:     .SWACCESS("RW"),
4974:     .RESVAL  (1'h0)
4975:   ) u_le2_le78 (
4976:     .clk_i   (clk_i    ),
4977:     .rst_ni  (rst_ni  ),
4978: 
4979:     // from register interface
4980:     .we     (le2_le78_we),
4981:     .wd     (le2_le78_wd),
4982: 
4983:     // from internal hardware
4984:     .de     (1'b0),
4985:     .d      ('0  ),
4986: 
4987:     // to internal hardware
4988:     .qe     (),
4989:     .q      (reg2hw.le[78].q ),
4990: 
4991:     // to register interface (read)
4992:     .qs     (le2_le78_qs)
4993:   );
4994: 
4995: 
4996:   // F[le79]: 15:15
4997:   prim_subreg #(
4998:     .DW      (1),
4999:     .SWACCESS("RW"),
5000:     .RESVAL  (1'h0)
5001:   ) u_le2_le79 (
5002:     .clk_i   (clk_i    ),
5003:     .rst_ni  (rst_ni  ),
5004: 
5005:     // from register interface
5006:     .we     (le2_le79_we),
5007:     .wd     (le2_le79_wd),
5008: 
5009:     // from internal hardware
5010:     .de     (1'b0),
5011:     .d      ('0  ),
5012: 
5013:     // to internal hardware
5014:     .qe     (),
5015:     .q      (reg2hw.le[79].q ),
5016: 
5017:     // to register interface (read)
5018:     .qs     (le2_le79_qs)
5019:   );
5020: 
5021: 
5022:   // F[le80]: 16:16
5023:   prim_subreg #(
5024:     .DW      (1),
5025:     .SWACCESS("RW"),
5026:     .RESVAL  (1'h0)
5027:   ) u_le2_le80 (
5028:     .clk_i   (clk_i    ),
5029:     .rst_ni  (rst_ni  ),
5030: 
5031:     // from register interface
5032:     .we     (le2_le80_we),
5033:     .wd     (le2_le80_wd),
5034: 
5035:     // from internal hardware
5036:     .de     (1'b0),
5037:     .d      ('0  ),
5038: 
5039:     // to internal hardware
5040:     .qe     (),
5041:     .q      (reg2hw.le[80].q ),
5042: 
5043:     // to register interface (read)
5044:     .qs     (le2_le80_qs)
5045:   );
5046: 
5047: 
5048: 
5049:   // R[prio0]: V(False)
5050: 
5051:   prim_subreg #(
5052:     .DW      (2),
5053:     .SWACCESS("RW"),
5054:     .RESVAL  (2'h0)
5055:   ) u_prio0 (
5056:     .clk_i   (clk_i    ),
5057:     .rst_ni  (rst_ni  ),
5058: 
5059:     // from register interface
5060:     .we     (prio0_we),
5061:     .wd     (prio0_wd),
5062: 
5063:     // from internal hardware
5064:     .de     (1'b0),
5065:     .d      ('0  ),
5066: 
5067:     // to internal hardware
5068:     .qe     (),
5069:     .q      (reg2hw.prio0.q ),
5070: 
5071:     // to register interface (read)
5072:     .qs     (prio0_qs)
5073:   );
5074: 
5075: 
5076:   // R[prio1]: V(False)
5077: 
5078:   prim_subreg #(
5079:     .DW      (2),
5080:     .SWACCESS("RW"),
5081:     .RESVAL  (2'h0)
5082:   ) u_prio1 (
5083:     .clk_i   (clk_i    ),
5084:     .rst_ni  (rst_ni  ),
5085: 
5086:     // from register interface
5087:     .we     (prio1_we),
5088:     .wd     (prio1_wd),
5089: 
5090:     // from internal hardware
5091:     .de     (1'b0),
5092:     .d      ('0  ),
5093: 
5094:     // to internal hardware
5095:     .qe     (),
5096:     .q      (reg2hw.prio1.q ),
5097: 
5098:     // to register interface (read)
5099:     .qs     (prio1_qs)
5100:   );
5101: 
5102: 
5103:   // R[prio2]: V(False)
5104: 
5105:   prim_subreg #(
5106:     .DW      (2),
5107:     .SWACCESS("RW"),
5108:     .RESVAL  (2'h0)
5109:   ) u_prio2 (
5110:     .clk_i   (clk_i    ),
5111:     .rst_ni  (rst_ni  ),
5112: 
5113:     // from register interface
5114:     .we     (prio2_we),
5115:     .wd     (prio2_wd),
5116: 
5117:     // from internal hardware
5118:     .de     (1'b0),
5119:     .d      ('0  ),
5120: 
5121:     // to internal hardware
5122:     .qe     (),
5123:     .q      (reg2hw.prio2.q ),
5124: 
5125:     // to register interface (read)
5126:     .qs     (prio2_qs)
5127:   );
5128: 
5129: 
5130:   // R[prio3]: V(False)
5131: 
5132:   prim_subreg #(
5133:     .DW      (2),
5134:     .SWACCESS("RW"),
5135:     .RESVAL  (2'h0)
5136:   ) u_prio3 (
5137:     .clk_i   (clk_i    ),
5138:     .rst_ni  (rst_ni  ),
5139: 
5140:     // from register interface
5141:     .we     (prio3_we),
5142:     .wd     (prio3_wd),
5143: 
5144:     // from internal hardware
5145:     .de     (1'b0),
5146:     .d      ('0  ),
5147: 
5148:     // to internal hardware
5149:     .qe     (),
5150:     .q      (reg2hw.prio3.q ),
5151: 
5152:     // to register interface (read)
5153:     .qs     (prio3_qs)
5154:   );
5155: 
5156: 
5157:   // R[prio4]: V(False)
5158: 
5159:   prim_subreg #(
5160:     .DW      (2),
5161:     .SWACCESS("RW"),
5162:     .RESVAL  (2'h0)
5163:   ) u_prio4 (
5164:     .clk_i   (clk_i    ),
5165:     .rst_ni  (rst_ni  ),
5166: 
5167:     // from register interface
5168:     .we     (prio4_we),
5169:     .wd     (prio4_wd),
5170: 
5171:     // from internal hardware
5172:     .de     (1'b0),
5173:     .d      ('0  ),
5174: 
5175:     // to internal hardware
5176:     .qe     (),
5177:     .q      (reg2hw.prio4.q ),
5178: 
5179:     // to register interface (read)
5180:     .qs     (prio4_qs)
5181:   );
5182: 
5183: 
5184:   // R[prio5]: V(False)
5185: 
5186:   prim_subreg #(
5187:     .DW      (2),
5188:     .SWACCESS("RW"),
5189:     .RESVAL  (2'h0)
5190:   ) u_prio5 (
5191:     .clk_i   (clk_i    ),
5192:     .rst_ni  (rst_ni  ),
5193: 
5194:     // from register interface
5195:     .we     (prio5_we),
5196:     .wd     (prio5_wd),
5197: 
5198:     // from internal hardware
5199:     .de     (1'b0),
5200:     .d      ('0  ),
5201: 
5202:     // to internal hardware
5203:     .qe     (),
5204:     .q      (reg2hw.prio5.q ),
5205: 
5206:     // to register interface (read)
5207:     .qs     (prio5_qs)
5208:   );
5209: 
5210: 
5211:   // R[prio6]: V(False)
5212: 
5213:   prim_subreg #(
5214:     .DW      (2),
5215:     .SWACCESS("RW"),
5216:     .RESVAL  (2'h0)
5217:   ) u_prio6 (
5218:     .clk_i   (clk_i    ),
5219:     .rst_ni  (rst_ni  ),
5220: 
5221:     // from register interface
5222:     .we     (prio6_we),
5223:     .wd     (prio6_wd),
5224: 
5225:     // from internal hardware
5226:     .de     (1'b0),
5227:     .d      ('0  ),
5228: 
5229:     // to internal hardware
5230:     .qe     (),
5231:     .q      (reg2hw.prio6.q ),
5232: 
5233:     // to register interface (read)
5234:     .qs     (prio6_qs)
5235:   );
5236: 
5237: 
5238:   // R[prio7]: V(False)
5239: 
5240:   prim_subreg #(
5241:     .DW      (2),
5242:     .SWACCESS("RW"),
5243:     .RESVAL  (2'h0)
5244:   ) u_prio7 (
5245:     .clk_i   (clk_i    ),
5246:     .rst_ni  (rst_ni  ),
5247: 
5248:     // from register interface
5249:     .we     (prio7_we),
5250:     .wd     (prio7_wd),
5251: 
5252:     // from internal hardware
5253:     .de     (1'b0),
5254:     .d      ('0  ),
5255: 
5256:     // to internal hardware
5257:     .qe     (),
5258:     .q      (reg2hw.prio7.q ),
5259: 
5260:     // to register interface (read)
5261:     .qs     (prio7_qs)
5262:   );
5263: 
5264: 
5265:   // R[prio8]: V(False)
5266: 
5267:   prim_subreg #(
5268:     .DW      (2),
5269:     .SWACCESS("RW"),
5270:     .RESVAL  (2'h0)
5271:   ) u_prio8 (
5272:     .clk_i   (clk_i    ),
5273:     .rst_ni  (rst_ni  ),
5274: 
5275:     // from register interface
5276:     .we     (prio8_we),
5277:     .wd     (prio8_wd),
5278: 
5279:     // from internal hardware
5280:     .de     (1'b0),
5281:     .d      ('0  ),
5282: 
5283:     // to internal hardware
5284:     .qe     (),
5285:     .q      (reg2hw.prio8.q ),
5286: 
5287:     // to register interface (read)
5288:     .qs     (prio8_qs)
5289:   );
5290: 
5291: 
5292:   // R[prio9]: V(False)
5293: 
5294:   prim_subreg #(
5295:     .DW      (2),
5296:     .SWACCESS("RW"),
5297:     .RESVAL  (2'h0)
5298:   ) u_prio9 (
5299:     .clk_i   (clk_i    ),
5300:     .rst_ni  (rst_ni  ),
5301: 
5302:     // from register interface
5303:     .we     (prio9_we),
5304:     .wd     (prio9_wd),
5305: 
5306:     // from internal hardware
5307:     .de     (1'b0),
5308:     .d      ('0  ),
5309: 
5310:     // to internal hardware
5311:     .qe     (),
5312:     .q      (reg2hw.prio9.q ),
5313: 
5314:     // to register interface (read)
5315:     .qs     (prio9_qs)
5316:   );
5317: 
5318: 
5319:   // R[prio10]: V(False)
5320: 
5321:   prim_subreg #(
5322:     .DW      (2),
5323:     .SWACCESS("RW"),
5324:     .RESVAL  (2'h0)
5325:   ) u_prio10 (
5326:     .clk_i   (clk_i    ),
5327:     .rst_ni  (rst_ni  ),
5328: 
5329:     // from register interface
5330:     .we     (prio10_we),
5331:     .wd     (prio10_wd),
5332: 
5333:     // from internal hardware
5334:     .de     (1'b0),
5335:     .d      ('0  ),
5336: 
5337:     // to internal hardware
5338:     .qe     (),
5339:     .q      (reg2hw.prio10.q ),
5340: 
5341:     // to register interface (read)
5342:     .qs     (prio10_qs)
5343:   );
5344: 
5345: 
5346:   // R[prio11]: V(False)
5347: 
5348:   prim_subreg #(
5349:     .DW      (2),
5350:     .SWACCESS("RW"),
5351:     .RESVAL  (2'h0)
5352:   ) u_prio11 (
5353:     .clk_i   (clk_i    ),
5354:     .rst_ni  (rst_ni  ),
5355: 
5356:     // from register interface
5357:     .we     (prio11_we),
5358:     .wd     (prio11_wd),
5359: 
5360:     // from internal hardware
5361:     .de     (1'b0),
5362:     .d      ('0  ),
5363: 
5364:     // to internal hardware
5365:     .qe     (),
5366:     .q      (reg2hw.prio11.q ),
5367: 
5368:     // to register interface (read)
5369:     .qs     (prio11_qs)
5370:   );
5371: 
5372: 
5373:   // R[prio12]: V(False)
5374: 
5375:   prim_subreg #(
5376:     .DW      (2),
5377:     .SWACCESS("RW"),
5378:     .RESVAL  (2'h0)
5379:   ) u_prio12 (
5380:     .clk_i   (clk_i    ),
5381:     .rst_ni  (rst_ni  ),
5382: 
5383:     // from register interface
5384:     .we     (prio12_we),
5385:     .wd     (prio12_wd),
5386: 
5387:     // from internal hardware
5388:     .de     (1'b0),
5389:     .d      ('0  ),
5390: 
5391:     // to internal hardware
5392:     .qe     (),
5393:     .q      (reg2hw.prio12.q ),
5394: 
5395:     // to register interface (read)
5396:     .qs     (prio12_qs)
5397:   );
5398: 
5399: 
5400:   // R[prio13]: V(False)
5401: 
5402:   prim_subreg #(
5403:     .DW      (2),
5404:     .SWACCESS("RW"),
5405:     .RESVAL  (2'h0)
5406:   ) u_prio13 (
5407:     .clk_i   (clk_i    ),
5408:     .rst_ni  (rst_ni  ),
5409: 
5410:     // from register interface
5411:     .we     (prio13_we),
5412:     .wd     (prio13_wd),
5413: 
5414:     // from internal hardware
5415:     .de     (1'b0),
5416:     .d      ('0  ),
5417: 
5418:     // to internal hardware
5419:     .qe     (),
5420:     .q      (reg2hw.prio13.q ),
5421: 
5422:     // to register interface (read)
5423:     .qs     (prio13_qs)
5424:   );
5425: 
5426: 
5427:   // R[prio14]: V(False)
5428: 
5429:   prim_subreg #(
5430:     .DW      (2),
5431:     .SWACCESS("RW"),
5432:     .RESVAL  (2'h0)
5433:   ) u_prio14 (
5434:     .clk_i   (clk_i    ),
5435:     .rst_ni  (rst_ni  ),
5436: 
5437:     // from register interface
5438:     .we     (prio14_we),
5439:     .wd     (prio14_wd),
5440: 
5441:     // from internal hardware
5442:     .de     (1'b0),
5443:     .d      ('0  ),
5444: 
5445:     // to internal hardware
5446:     .qe     (),
5447:     .q      (reg2hw.prio14.q ),
5448: 
5449:     // to register interface (read)
5450:     .qs     (prio14_qs)
5451:   );
5452: 
5453: 
5454:   // R[prio15]: V(False)
5455: 
5456:   prim_subreg #(
5457:     .DW      (2),
5458:     .SWACCESS("RW"),
5459:     .RESVAL  (2'h0)
5460:   ) u_prio15 (
5461:     .clk_i   (clk_i    ),
5462:     .rst_ni  (rst_ni  ),
5463: 
5464:     // from register interface
5465:     .we     (prio15_we),
5466:     .wd     (prio15_wd),
5467: 
5468:     // from internal hardware
5469:     .de     (1'b0),
5470:     .d      ('0  ),
5471: 
5472:     // to internal hardware
5473:     .qe     (),
5474:     .q      (reg2hw.prio15.q ),
5475: 
5476:     // to register interface (read)
5477:     .qs     (prio15_qs)
5478:   );
5479: 
5480: 
5481:   // R[prio16]: V(False)
5482: 
5483:   prim_subreg #(
5484:     .DW      (2),
5485:     .SWACCESS("RW"),
5486:     .RESVAL  (2'h0)
5487:   ) u_prio16 (
5488:     .clk_i   (clk_i    ),
5489:     .rst_ni  (rst_ni  ),
5490: 
5491:     // from register interface
5492:     .we     (prio16_we),
5493:     .wd     (prio16_wd),
5494: 
5495:     // from internal hardware
5496:     .de     (1'b0),
5497:     .d      ('0  ),
5498: 
5499:     // to internal hardware
5500:     .qe     (),
5501:     .q      (reg2hw.prio16.q ),
5502: 
5503:     // to register interface (read)
5504:     .qs     (prio16_qs)
5505:   );
5506: 
5507: 
5508:   // R[prio17]: V(False)
5509: 
5510:   prim_subreg #(
5511:     .DW      (2),
5512:     .SWACCESS("RW"),
5513:     .RESVAL  (2'h0)
5514:   ) u_prio17 (
5515:     .clk_i   (clk_i    ),
5516:     .rst_ni  (rst_ni  ),
5517: 
5518:     // from register interface
5519:     .we     (prio17_we),
5520:     .wd     (prio17_wd),
5521: 
5522:     // from internal hardware
5523:     .de     (1'b0),
5524:     .d      ('0  ),
5525: 
5526:     // to internal hardware
5527:     .qe     (),
5528:     .q      (reg2hw.prio17.q ),
5529: 
5530:     // to register interface (read)
5531:     .qs     (prio17_qs)
5532:   );
5533: 
5534: 
5535:   // R[prio18]: V(False)
5536: 
5537:   prim_subreg #(
5538:     .DW      (2),
5539:     .SWACCESS("RW"),
5540:     .RESVAL  (2'h0)
5541:   ) u_prio18 (
5542:     .clk_i   (clk_i    ),
5543:     .rst_ni  (rst_ni  ),
5544: 
5545:     // from register interface
5546:     .we     (prio18_we),
5547:     .wd     (prio18_wd),
5548: 
5549:     // from internal hardware
5550:     .de     (1'b0),
5551:     .d      ('0  ),
5552: 
5553:     // to internal hardware
5554:     .qe     (),
5555:     .q      (reg2hw.prio18.q ),
5556: 
5557:     // to register interface (read)
5558:     .qs     (prio18_qs)
5559:   );
5560: 
5561: 
5562:   // R[prio19]: V(False)
5563: 
5564:   prim_subreg #(
5565:     .DW      (2),
5566:     .SWACCESS("RW"),
5567:     .RESVAL  (2'h0)
5568:   ) u_prio19 (
5569:     .clk_i   (clk_i    ),
5570:     .rst_ni  (rst_ni  ),
5571: 
5572:     // from register interface
5573:     .we     (prio19_we),
5574:     .wd     (prio19_wd),
5575: 
5576:     // from internal hardware
5577:     .de     (1'b0),
5578:     .d      ('0  ),
5579: 
5580:     // to internal hardware
5581:     .qe     (),
5582:     .q      (reg2hw.prio19.q ),
5583: 
5584:     // to register interface (read)
5585:     .qs     (prio19_qs)
5586:   );
5587: 
5588: 
5589:   // R[prio20]: V(False)
5590: 
5591:   prim_subreg #(
5592:     .DW      (2),
5593:     .SWACCESS("RW"),
5594:     .RESVAL  (2'h0)
5595:   ) u_prio20 (
5596:     .clk_i   (clk_i    ),
5597:     .rst_ni  (rst_ni  ),
5598: 
5599:     // from register interface
5600:     .we     (prio20_we),
5601:     .wd     (prio20_wd),
5602: 
5603:     // from internal hardware
5604:     .de     (1'b0),
5605:     .d      ('0  ),
5606: 
5607:     // to internal hardware
5608:     .qe     (),
5609:     .q      (reg2hw.prio20.q ),
5610: 
5611:     // to register interface (read)
5612:     .qs     (prio20_qs)
5613:   );
5614: 
5615: 
5616:   // R[prio21]: V(False)
5617: 
5618:   prim_subreg #(
5619:     .DW      (2),
5620:     .SWACCESS("RW"),
5621:     .RESVAL  (2'h0)
5622:   ) u_prio21 (
5623:     .clk_i   (clk_i    ),
5624:     .rst_ni  (rst_ni  ),
5625: 
5626:     // from register interface
5627:     .we     (prio21_we),
5628:     .wd     (prio21_wd),
5629: 
5630:     // from internal hardware
5631:     .de     (1'b0),
5632:     .d      ('0  ),
5633: 
5634:     // to internal hardware
5635:     .qe     (),
5636:     .q      (reg2hw.prio21.q ),
5637: 
5638:     // to register interface (read)
5639:     .qs     (prio21_qs)
5640:   );
5641: 
5642: 
5643:   // R[prio22]: V(False)
5644: 
5645:   prim_subreg #(
5646:     .DW      (2),
5647:     .SWACCESS("RW"),
5648:     .RESVAL  (2'h0)
5649:   ) u_prio22 (
5650:     .clk_i   (clk_i    ),
5651:     .rst_ni  (rst_ni  ),
5652: 
5653:     // from register interface
5654:     .we     (prio22_we),
5655:     .wd     (prio22_wd),
5656: 
5657:     // from internal hardware
5658:     .de     (1'b0),
5659:     .d      ('0  ),
5660: 
5661:     // to internal hardware
5662:     .qe     (),
5663:     .q      (reg2hw.prio22.q ),
5664: 
5665:     // to register interface (read)
5666:     .qs     (prio22_qs)
5667:   );
5668: 
5669: 
5670:   // R[prio23]: V(False)
5671: 
5672:   prim_subreg #(
5673:     .DW      (2),
5674:     .SWACCESS("RW"),
5675:     .RESVAL  (2'h0)
5676:   ) u_prio23 (
5677:     .clk_i   (clk_i    ),
5678:     .rst_ni  (rst_ni  ),
5679: 
5680:     // from register interface
5681:     .we     (prio23_we),
5682:     .wd     (prio23_wd),
5683: 
5684:     // from internal hardware
5685:     .de     (1'b0),
5686:     .d      ('0  ),
5687: 
5688:     // to internal hardware
5689:     .qe     (),
5690:     .q      (reg2hw.prio23.q ),
5691: 
5692:     // to register interface (read)
5693:     .qs     (prio23_qs)
5694:   );
5695: 
5696: 
5697:   // R[prio24]: V(False)
5698: 
5699:   prim_subreg #(
5700:     .DW      (2),
5701:     .SWACCESS("RW"),
5702:     .RESVAL  (2'h0)
5703:   ) u_prio24 (
5704:     .clk_i   (clk_i    ),
5705:     .rst_ni  (rst_ni  ),
5706: 
5707:     // from register interface
5708:     .we     (prio24_we),
5709:     .wd     (prio24_wd),
5710: 
5711:     // from internal hardware
5712:     .de     (1'b0),
5713:     .d      ('0  ),
5714: 
5715:     // to internal hardware
5716:     .qe     (),
5717:     .q      (reg2hw.prio24.q ),
5718: 
5719:     // to register interface (read)
5720:     .qs     (prio24_qs)
5721:   );
5722: 
5723: 
5724:   // R[prio25]: V(False)
5725: 
5726:   prim_subreg #(
5727:     .DW      (2),
5728:     .SWACCESS("RW"),
5729:     .RESVAL  (2'h0)
5730:   ) u_prio25 (
5731:     .clk_i   (clk_i    ),
5732:     .rst_ni  (rst_ni  ),
5733: 
5734:     // from register interface
5735:     .we     (prio25_we),
5736:     .wd     (prio25_wd),
5737: 
5738:     // from internal hardware
5739:     .de     (1'b0),
5740:     .d      ('0  ),
5741: 
5742:     // to internal hardware
5743:     .qe     (),
5744:     .q      (reg2hw.prio25.q ),
5745: 
5746:     // to register interface (read)
5747:     .qs     (prio25_qs)
5748:   );
5749: 
5750: 
5751:   // R[prio26]: V(False)
5752: 
5753:   prim_subreg #(
5754:     .DW      (2),
5755:     .SWACCESS("RW"),
5756:     .RESVAL  (2'h0)
5757:   ) u_prio26 (
5758:     .clk_i   (clk_i    ),
5759:     .rst_ni  (rst_ni  ),
5760: 
5761:     // from register interface
5762:     .we     (prio26_we),
5763:     .wd     (prio26_wd),
5764: 
5765:     // from internal hardware
5766:     .de     (1'b0),
5767:     .d      ('0  ),
5768: 
5769:     // to internal hardware
5770:     .qe     (),
5771:     .q      (reg2hw.prio26.q ),
5772: 
5773:     // to register interface (read)
5774:     .qs     (prio26_qs)
5775:   );
5776: 
5777: 
5778:   // R[prio27]: V(False)
5779: 
5780:   prim_subreg #(
5781:     .DW      (2),
5782:     .SWACCESS("RW"),
5783:     .RESVAL  (2'h0)
5784:   ) u_prio27 (
5785:     .clk_i   (clk_i    ),
5786:     .rst_ni  (rst_ni  ),
5787: 
5788:     // from register interface
5789:     .we     (prio27_we),
5790:     .wd     (prio27_wd),
5791: 
5792:     // from internal hardware
5793:     .de     (1'b0),
5794:     .d      ('0  ),
5795: 
5796:     // to internal hardware
5797:     .qe     (),
5798:     .q      (reg2hw.prio27.q ),
5799: 
5800:     // to register interface (read)
5801:     .qs     (prio27_qs)
5802:   );
5803: 
5804: 
5805:   // R[prio28]: V(False)
5806: 
5807:   prim_subreg #(
5808:     .DW      (2),
5809:     .SWACCESS("RW"),
5810:     .RESVAL  (2'h0)
5811:   ) u_prio28 (
5812:     .clk_i   (clk_i    ),
5813:     .rst_ni  (rst_ni  ),
5814: 
5815:     // from register interface
5816:     .we     (prio28_we),
5817:     .wd     (prio28_wd),
5818: 
5819:     // from internal hardware
5820:     .de     (1'b0),
5821:     .d      ('0  ),
5822: 
5823:     // to internal hardware
5824:     .qe     (),
5825:     .q      (reg2hw.prio28.q ),
5826: 
5827:     // to register interface (read)
5828:     .qs     (prio28_qs)
5829:   );
5830: 
5831: 
5832:   // R[prio29]: V(False)
5833: 
5834:   prim_subreg #(
5835:     .DW      (2),
5836:     .SWACCESS("RW"),
5837:     .RESVAL  (2'h0)
5838:   ) u_prio29 (
5839:     .clk_i   (clk_i    ),
5840:     .rst_ni  (rst_ni  ),
5841: 
5842:     // from register interface
5843:     .we     (prio29_we),
5844:     .wd     (prio29_wd),
5845: 
5846:     // from internal hardware
5847:     .de     (1'b0),
5848:     .d      ('0  ),
5849: 
5850:     // to internal hardware
5851:     .qe     (),
5852:     .q      (reg2hw.prio29.q ),
5853: 
5854:     // to register interface (read)
5855:     .qs     (prio29_qs)
5856:   );
5857: 
5858: 
5859:   // R[prio30]: V(False)
5860: 
5861:   prim_subreg #(
5862:     .DW      (2),
5863:     .SWACCESS("RW"),
5864:     .RESVAL  (2'h0)
5865:   ) u_prio30 (
5866:     .clk_i   (clk_i    ),
5867:     .rst_ni  (rst_ni  ),
5868: 
5869:     // from register interface
5870:     .we     (prio30_we),
5871:     .wd     (prio30_wd),
5872: 
5873:     // from internal hardware
5874:     .de     (1'b0),
5875:     .d      ('0  ),
5876: 
5877:     // to internal hardware
5878:     .qe     (),
5879:     .q      (reg2hw.prio30.q ),
5880: 
5881:     // to register interface (read)
5882:     .qs     (prio30_qs)
5883:   );
5884: 
5885: 
5886:   // R[prio31]: V(False)
5887: 
5888:   prim_subreg #(
5889:     .DW      (2),
5890:     .SWACCESS("RW"),
5891:     .RESVAL  (2'h0)
5892:   ) u_prio31 (
5893:     .clk_i   (clk_i    ),
5894:     .rst_ni  (rst_ni  ),
5895: 
5896:     // from register interface
5897:     .we     (prio31_we),
5898:     .wd     (prio31_wd),
5899: 
5900:     // from internal hardware
5901:     .de     (1'b0),
5902:     .d      ('0  ),
5903: 
5904:     // to internal hardware
5905:     .qe     (),
5906:     .q      (reg2hw.prio31.q ),
5907: 
5908:     // to register interface (read)
5909:     .qs     (prio31_qs)
5910:   );
5911: 
5912: 
5913:   // R[prio32]: V(False)
5914: 
5915:   prim_subreg #(
5916:     .DW      (2),
5917:     .SWACCESS("RW"),
5918:     .RESVAL  (2'h0)
5919:   ) u_prio32 (
5920:     .clk_i   (clk_i    ),
5921:     .rst_ni  (rst_ni  ),
5922: 
5923:     // from register interface
5924:     .we     (prio32_we),
5925:     .wd     (prio32_wd),
5926: 
5927:     // from internal hardware
5928:     .de     (1'b0),
5929:     .d      ('0  ),
5930: 
5931:     // to internal hardware
5932:     .qe     (),
5933:     .q      (reg2hw.prio32.q ),
5934: 
5935:     // to register interface (read)
5936:     .qs     (prio32_qs)
5937:   );
5938: 
5939: 
5940:   // R[prio33]: V(False)
5941: 
5942:   prim_subreg #(
5943:     .DW      (2),
5944:     .SWACCESS("RW"),
5945:     .RESVAL  (2'h0)
5946:   ) u_prio33 (
5947:     .clk_i   (clk_i    ),
5948:     .rst_ni  (rst_ni  ),
5949: 
5950:     // from register interface
5951:     .we     (prio33_we),
5952:     .wd     (prio33_wd),
5953: 
5954:     // from internal hardware
5955:     .de     (1'b0),
5956:     .d      ('0  ),
5957: 
5958:     // to internal hardware
5959:     .qe     (),
5960:     .q      (reg2hw.prio33.q ),
5961: 
5962:     // to register interface (read)
5963:     .qs     (prio33_qs)
5964:   );
5965: 
5966: 
5967:   // R[prio34]: V(False)
5968: 
5969:   prim_subreg #(
5970:     .DW      (2),
5971:     .SWACCESS("RW"),
5972:     .RESVAL  (2'h0)
5973:   ) u_prio34 (
5974:     .clk_i   (clk_i    ),
5975:     .rst_ni  (rst_ni  ),
5976: 
5977:     // from register interface
5978:     .we     (prio34_we),
5979:     .wd     (prio34_wd),
5980: 
5981:     // from internal hardware
5982:     .de     (1'b0),
5983:     .d      ('0  ),
5984: 
5985:     // to internal hardware
5986:     .qe     (),
5987:     .q      (reg2hw.prio34.q ),
5988: 
5989:     // to register interface (read)
5990:     .qs     (prio34_qs)
5991:   );
5992: 
5993: 
5994:   // R[prio35]: V(False)
5995: 
5996:   prim_subreg #(
5997:     .DW      (2),
5998:     .SWACCESS("RW"),
5999:     .RESVAL  (2'h0)
6000:   ) u_prio35 (
6001:     .clk_i   (clk_i    ),
6002:     .rst_ni  (rst_ni  ),
6003: 
6004:     // from register interface
6005:     .we     (prio35_we),
6006:     .wd     (prio35_wd),
6007: 
6008:     // from internal hardware
6009:     .de     (1'b0),
6010:     .d      ('0  ),
6011: 
6012:     // to internal hardware
6013:     .qe     (),
6014:     .q      (reg2hw.prio35.q ),
6015: 
6016:     // to register interface (read)
6017:     .qs     (prio35_qs)
6018:   );
6019: 
6020: 
6021:   // R[prio36]: V(False)
6022: 
6023:   prim_subreg #(
6024:     .DW      (2),
6025:     .SWACCESS("RW"),
6026:     .RESVAL  (2'h0)
6027:   ) u_prio36 (
6028:     .clk_i   (clk_i    ),
6029:     .rst_ni  (rst_ni  ),
6030: 
6031:     // from register interface
6032:     .we     (prio36_we),
6033:     .wd     (prio36_wd),
6034: 
6035:     // from internal hardware
6036:     .de     (1'b0),
6037:     .d      ('0  ),
6038: 
6039:     // to internal hardware
6040:     .qe     (),
6041:     .q      (reg2hw.prio36.q ),
6042: 
6043:     // to register interface (read)
6044:     .qs     (prio36_qs)
6045:   );
6046: 
6047: 
6048:   // R[prio37]: V(False)
6049: 
6050:   prim_subreg #(
6051:     .DW      (2),
6052:     .SWACCESS("RW"),
6053:     .RESVAL  (2'h0)
6054:   ) u_prio37 (
6055:     .clk_i   (clk_i    ),
6056:     .rst_ni  (rst_ni  ),
6057: 
6058:     // from register interface
6059:     .we     (prio37_we),
6060:     .wd     (prio37_wd),
6061: 
6062:     // from internal hardware
6063:     .de     (1'b0),
6064:     .d      ('0  ),
6065: 
6066:     // to internal hardware
6067:     .qe     (),
6068:     .q      (reg2hw.prio37.q ),
6069: 
6070:     // to register interface (read)
6071:     .qs     (prio37_qs)
6072:   );
6073: 
6074: 
6075:   // R[prio38]: V(False)
6076: 
6077:   prim_subreg #(
6078:     .DW      (2),
6079:     .SWACCESS("RW"),
6080:     .RESVAL  (2'h0)
6081:   ) u_prio38 (
6082:     .clk_i   (clk_i    ),
6083:     .rst_ni  (rst_ni  ),
6084: 
6085:     // from register interface
6086:     .we     (prio38_we),
6087:     .wd     (prio38_wd),
6088: 
6089:     // from internal hardware
6090:     .de     (1'b0),
6091:     .d      ('0  ),
6092: 
6093:     // to internal hardware
6094:     .qe     (),
6095:     .q      (reg2hw.prio38.q ),
6096: 
6097:     // to register interface (read)
6098:     .qs     (prio38_qs)
6099:   );
6100: 
6101: 
6102:   // R[prio39]: V(False)
6103: 
6104:   prim_subreg #(
6105:     .DW      (2),
6106:     .SWACCESS("RW"),
6107:     .RESVAL  (2'h0)
6108:   ) u_prio39 (
6109:     .clk_i   (clk_i    ),
6110:     .rst_ni  (rst_ni  ),
6111: 
6112:     // from register interface
6113:     .we     (prio39_we),
6114:     .wd     (prio39_wd),
6115: 
6116:     // from internal hardware
6117:     .de     (1'b0),
6118:     .d      ('0  ),
6119: 
6120:     // to internal hardware
6121:     .qe     (),
6122:     .q      (reg2hw.prio39.q ),
6123: 
6124:     // to register interface (read)
6125:     .qs     (prio39_qs)
6126:   );
6127: 
6128: 
6129:   // R[prio40]: V(False)
6130: 
6131:   prim_subreg #(
6132:     .DW      (2),
6133:     .SWACCESS("RW"),
6134:     .RESVAL  (2'h0)
6135:   ) u_prio40 (
6136:     .clk_i   (clk_i    ),
6137:     .rst_ni  (rst_ni  ),
6138: 
6139:     // from register interface
6140:     .we     (prio40_we),
6141:     .wd     (prio40_wd),
6142: 
6143:     // from internal hardware
6144:     .de     (1'b0),
6145:     .d      ('0  ),
6146: 
6147:     // to internal hardware
6148:     .qe     (),
6149:     .q      (reg2hw.prio40.q ),
6150: 
6151:     // to register interface (read)
6152:     .qs     (prio40_qs)
6153:   );
6154: 
6155: 
6156:   // R[prio41]: V(False)
6157: 
6158:   prim_subreg #(
6159:     .DW      (2),
6160:     .SWACCESS("RW"),
6161:     .RESVAL  (2'h0)
6162:   ) u_prio41 (
6163:     .clk_i   (clk_i    ),
6164:     .rst_ni  (rst_ni  ),
6165: 
6166:     // from register interface
6167:     .we     (prio41_we),
6168:     .wd     (prio41_wd),
6169: 
6170:     // from internal hardware
6171:     .de     (1'b0),
6172:     .d      ('0  ),
6173: 
6174:     // to internal hardware
6175:     .qe     (),
6176:     .q      (reg2hw.prio41.q ),
6177: 
6178:     // to register interface (read)
6179:     .qs     (prio41_qs)
6180:   );
6181: 
6182: 
6183:   // R[prio42]: V(False)
6184: 
6185:   prim_subreg #(
6186:     .DW      (2),
6187:     .SWACCESS("RW"),
6188:     .RESVAL  (2'h0)
6189:   ) u_prio42 (
6190:     .clk_i   (clk_i    ),
6191:     .rst_ni  (rst_ni  ),
6192: 
6193:     // from register interface
6194:     .we     (prio42_we),
6195:     .wd     (prio42_wd),
6196: 
6197:     // from internal hardware
6198:     .de     (1'b0),
6199:     .d      ('0  ),
6200: 
6201:     // to internal hardware
6202:     .qe     (),
6203:     .q      (reg2hw.prio42.q ),
6204: 
6205:     // to register interface (read)
6206:     .qs     (prio42_qs)
6207:   );
6208: 
6209: 
6210:   // R[prio43]: V(False)
6211: 
6212:   prim_subreg #(
6213:     .DW      (2),
6214:     .SWACCESS("RW"),
6215:     .RESVAL  (2'h0)
6216:   ) u_prio43 (
6217:     .clk_i   (clk_i    ),
6218:     .rst_ni  (rst_ni  ),
6219: 
6220:     // from register interface
6221:     .we     (prio43_we),
6222:     .wd     (prio43_wd),
6223: 
6224:     // from internal hardware
6225:     .de     (1'b0),
6226:     .d      ('0  ),
6227: 
6228:     // to internal hardware
6229:     .qe     (),
6230:     .q      (reg2hw.prio43.q ),
6231: 
6232:     // to register interface (read)
6233:     .qs     (prio43_qs)
6234:   );
6235: 
6236: 
6237:   // R[prio44]: V(False)
6238: 
6239:   prim_subreg #(
6240:     .DW      (2),
6241:     .SWACCESS("RW"),
6242:     .RESVAL  (2'h0)
6243:   ) u_prio44 (
6244:     .clk_i   (clk_i    ),
6245:     .rst_ni  (rst_ni  ),
6246: 
6247:     // from register interface
6248:     .we     (prio44_we),
6249:     .wd     (prio44_wd),
6250: 
6251:     // from internal hardware
6252:     .de     (1'b0),
6253:     .d      ('0  ),
6254: 
6255:     // to internal hardware
6256:     .qe     (),
6257:     .q      (reg2hw.prio44.q ),
6258: 
6259:     // to register interface (read)
6260:     .qs     (prio44_qs)
6261:   );
6262: 
6263: 
6264:   // R[prio45]: V(False)
6265: 
6266:   prim_subreg #(
6267:     .DW      (2),
6268:     .SWACCESS("RW"),
6269:     .RESVAL  (2'h0)
6270:   ) u_prio45 (
6271:     .clk_i   (clk_i    ),
6272:     .rst_ni  (rst_ni  ),
6273: 
6274:     // from register interface
6275:     .we     (prio45_we),
6276:     .wd     (prio45_wd),
6277: 
6278:     // from internal hardware
6279:     .de     (1'b0),
6280:     .d      ('0  ),
6281: 
6282:     // to internal hardware
6283:     .qe     (),
6284:     .q      (reg2hw.prio45.q ),
6285: 
6286:     // to register interface (read)
6287:     .qs     (prio45_qs)
6288:   );
6289: 
6290: 
6291:   // R[prio46]: V(False)
6292: 
6293:   prim_subreg #(
6294:     .DW      (2),
6295:     .SWACCESS("RW"),
6296:     .RESVAL  (2'h0)
6297:   ) u_prio46 (
6298:     .clk_i   (clk_i    ),
6299:     .rst_ni  (rst_ni  ),
6300: 
6301:     // from register interface
6302:     .we     (prio46_we),
6303:     .wd     (prio46_wd),
6304: 
6305:     // from internal hardware
6306:     .de     (1'b0),
6307:     .d      ('0  ),
6308: 
6309:     // to internal hardware
6310:     .qe     (),
6311:     .q      (reg2hw.prio46.q ),
6312: 
6313:     // to register interface (read)
6314:     .qs     (prio46_qs)
6315:   );
6316: 
6317: 
6318:   // R[prio47]: V(False)
6319: 
6320:   prim_subreg #(
6321:     .DW      (2),
6322:     .SWACCESS("RW"),
6323:     .RESVAL  (2'h0)
6324:   ) u_prio47 (
6325:     .clk_i   (clk_i    ),
6326:     .rst_ni  (rst_ni  ),
6327: 
6328:     // from register interface
6329:     .we     (prio47_we),
6330:     .wd     (prio47_wd),
6331: 
6332:     // from internal hardware
6333:     .de     (1'b0),
6334:     .d      ('0  ),
6335: 
6336:     // to internal hardware
6337:     .qe     (),
6338:     .q      (reg2hw.prio47.q ),
6339: 
6340:     // to register interface (read)
6341:     .qs     (prio47_qs)
6342:   );
6343: 
6344: 
6345:   // R[prio48]: V(False)
6346: 
6347:   prim_subreg #(
6348:     .DW      (2),
6349:     .SWACCESS("RW"),
6350:     .RESVAL  (2'h0)
6351:   ) u_prio48 (
6352:     .clk_i   (clk_i    ),
6353:     .rst_ni  (rst_ni  ),
6354: 
6355:     // from register interface
6356:     .we     (prio48_we),
6357:     .wd     (prio48_wd),
6358: 
6359:     // from internal hardware
6360:     .de     (1'b0),
6361:     .d      ('0  ),
6362: 
6363:     // to internal hardware
6364:     .qe     (),
6365:     .q      (reg2hw.prio48.q ),
6366: 
6367:     // to register interface (read)
6368:     .qs     (prio48_qs)
6369:   );
6370: 
6371: 
6372:   // R[prio49]: V(False)
6373: 
6374:   prim_subreg #(
6375:     .DW      (2),
6376:     .SWACCESS("RW"),
6377:     .RESVAL  (2'h0)
6378:   ) u_prio49 (
6379:     .clk_i   (clk_i    ),
6380:     .rst_ni  (rst_ni  ),
6381: 
6382:     // from register interface
6383:     .we     (prio49_we),
6384:     .wd     (prio49_wd),
6385: 
6386:     // from internal hardware
6387:     .de     (1'b0),
6388:     .d      ('0  ),
6389: 
6390:     // to internal hardware
6391:     .qe     (),
6392:     .q      (reg2hw.prio49.q ),
6393: 
6394:     // to register interface (read)
6395:     .qs     (prio49_qs)
6396:   );
6397: 
6398: 
6399:   // R[prio50]: V(False)
6400: 
6401:   prim_subreg #(
6402:     .DW      (2),
6403:     .SWACCESS("RW"),
6404:     .RESVAL  (2'h0)
6405:   ) u_prio50 (
6406:     .clk_i   (clk_i    ),
6407:     .rst_ni  (rst_ni  ),
6408: 
6409:     // from register interface
6410:     .we     (prio50_we),
6411:     .wd     (prio50_wd),
6412: 
6413:     // from internal hardware
6414:     .de     (1'b0),
6415:     .d      ('0  ),
6416: 
6417:     // to internal hardware
6418:     .qe     (),
6419:     .q      (reg2hw.prio50.q ),
6420: 
6421:     // to register interface (read)
6422:     .qs     (prio50_qs)
6423:   );
6424: 
6425: 
6426:   // R[prio51]: V(False)
6427: 
6428:   prim_subreg #(
6429:     .DW      (2),
6430:     .SWACCESS("RW"),
6431:     .RESVAL  (2'h0)
6432:   ) u_prio51 (
6433:     .clk_i   (clk_i    ),
6434:     .rst_ni  (rst_ni  ),
6435: 
6436:     // from register interface
6437:     .we     (prio51_we),
6438:     .wd     (prio51_wd),
6439: 
6440:     // from internal hardware
6441:     .de     (1'b0),
6442:     .d      ('0  ),
6443: 
6444:     // to internal hardware
6445:     .qe     (),
6446:     .q      (reg2hw.prio51.q ),
6447: 
6448:     // to register interface (read)
6449:     .qs     (prio51_qs)
6450:   );
6451: 
6452: 
6453:   // R[prio52]: V(False)
6454: 
6455:   prim_subreg #(
6456:     .DW      (2),
6457:     .SWACCESS("RW"),
6458:     .RESVAL  (2'h0)
6459:   ) u_prio52 (
6460:     .clk_i   (clk_i    ),
6461:     .rst_ni  (rst_ni  ),
6462: 
6463:     // from register interface
6464:     .we     (prio52_we),
6465:     .wd     (prio52_wd),
6466: 
6467:     // from internal hardware
6468:     .de     (1'b0),
6469:     .d      ('0  ),
6470: 
6471:     // to internal hardware
6472:     .qe     (),
6473:     .q      (reg2hw.prio52.q ),
6474: 
6475:     // to register interface (read)
6476:     .qs     (prio52_qs)
6477:   );
6478: 
6479: 
6480:   // R[prio53]: V(False)
6481: 
6482:   prim_subreg #(
6483:     .DW      (2),
6484:     .SWACCESS("RW"),
6485:     .RESVAL  (2'h0)
6486:   ) u_prio53 (
6487:     .clk_i   (clk_i    ),
6488:     .rst_ni  (rst_ni  ),
6489: 
6490:     // from register interface
6491:     .we     (prio53_we),
6492:     .wd     (prio53_wd),
6493: 
6494:     // from internal hardware
6495:     .de     (1'b0),
6496:     .d      ('0  ),
6497: 
6498:     // to internal hardware
6499:     .qe     (),
6500:     .q      (reg2hw.prio53.q ),
6501: 
6502:     // to register interface (read)
6503:     .qs     (prio53_qs)
6504:   );
6505: 
6506: 
6507:   // R[prio54]: V(False)
6508: 
6509:   prim_subreg #(
6510:     .DW      (2),
6511:     .SWACCESS("RW"),
6512:     .RESVAL  (2'h0)
6513:   ) u_prio54 (
6514:     .clk_i   (clk_i    ),
6515:     .rst_ni  (rst_ni  ),
6516: 
6517:     // from register interface
6518:     .we     (prio54_we),
6519:     .wd     (prio54_wd),
6520: 
6521:     // from internal hardware
6522:     .de     (1'b0),
6523:     .d      ('0  ),
6524: 
6525:     // to internal hardware
6526:     .qe     (),
6527:     .q      (reg2hw.prio54.q ),
6528: 
6529:     // to register interface (read)
6530:     .qs     (prio54_qs)
6531:   );
6532: 
6533: 
6534:   // R[prio55]: V(False)
6535: 
6536:   prim_subreg #(
6537:     .DW      (2),
6538:     .SWACCESS("RW"),
6539:     .RESVAL  (2'h0)
6540:   ) u_prio55 (
6541:     .clk_i   (clk_i    ),
6542:     .rst_ni  (rst_ni  ),
6543: 
6544:     // from register interface
6545:     .we     (prio55_we),
6546:     .wd     (prio55_wd),
6547: 
6548:     // from internal hardware
6549:     .de     (1'b0),
6550:     .d      ('0  ),
6551: 
6552:     // to internal hardware
6553:     .qe     (),
6554:     .q      (reg2hw.prio55.q ),
6555: 
6556:     // to register interface (read)
6557:     .qs     (prio55_qs)
6558:   );
6559: 
6560: 
6561:   // R[prio56]: V(False)
6562: 
6563:   prim_subreg #(
6564:     .DW      (2),
6565:     .SWACCESS("RW"),
6566:     .RESVAL  (2'h0)
6567:   ) u_prio56 (
6568:     .clk_i   (clk_i    ),
6569:     .rst_ni  (rst_ni  ),
6570: 
6571:     // from register interface
6572:     .we     (prio56_we),
6573:     .wd     (prio56_wd),
6574: 
6575:     // from internal hardware
6576:     .de     (1'b0),
6577:     .d      ('0  ),
6578: 
6579:     // to internal hardware
6580:     .qe     (),
6581:     .q      (reg2hw.prio56.q ),
6582: 
6583:     // to register interface (read)
6584:     .qs     (prio56_qs)
6585:   );
6586: 
6587: 
6588:   // R[prio57]: V(False)
6589: 
6590:   prim_subreg #(
6591:     .DW      (2),
6592:     .SWACCESS("RW"),
6593:     .RESVAL  (2'h0)
6594:   ) u_prio57 (
6595:     .clk_i   (clk_i    ),
6596:     .rst_ni  (rst_ni  ),
6597: 
6598:     // from register interface
6599:     .we     (prio57_we),
6600:     .wd     (prio57_wd),
6601: 
6602:     // from internal hardware
6603:     .de     (1'b0),
6604:     .d      ('0  ),
6605: 
6606:     // to internal hardware
6607:     .qe     (),
6608:     .q      (reg2hw.prio57.q ),
6609: 
6610:     // to register interface (read)
6611:     .qs     (prio57_qs)
6612:   );
6613: 
6614: 
6615:   // R[prio58]: V(False)
6616: 
6617:   prim_subreg #(
6618:     .DW      (2),
6619:     .SWACCESS("RW"),
6620:     .RESVAL  (2'h0)
6621:   ) u_prio58 (
6622:     .clk_i   (clk_i    ),
6623:     .rst_ni  (rst_ni  ),
6624: 
6625:     // from register interface
6626:     .we     (prio58_we),
6627:     .wd     (prio58_wd),
6628: 
6629:     // from internal hardware
6630:     .de     (1'b0),
6631:     .d      ('0  ),
6632: 
6633:     // to internal hardware
6634:     .qe     (),
6635:     .q      (reg2hw.prio58.q ),
6636: 
6637:     // to register interface (read)
6638:     .qs     (prio58_qs)
6639:   );
6640: 
6641: 
6642:   // R[prio59]: V(False)
6643: 
6644:   prim_subreg #(
6645:     .DW      (2),
6646:     .SWACCESS("RW"),
6647:     .RESVAL  (2'h0)
6648:   ) u_prio59 (
6649:     .clk_i   (clk_i    ),
6650:     .rst_ni  (rst_ni  ),
6651: 
6652:     // from register interface
6653:     .we     (prio59_we),
6654:     .wd     (prio59_wd),
6655: 
6656:     // from internal hardware
6657:     .de     (1'b0),
6658:     .d      ('0  ),
6659: 
6660:     // to internal hardware
6661:     .qe     (),
6662:     .q      (reg2hw.prio59.q ),
6663: 
6664:     // to register interface (read)
6665:     .qs     (prio59_qs)
6666:   );
6667: 
6668: 
6669:   // R[prio60]: V(False)
6670: 
6671:   prim_subreg #(
6672:     .DW      (2),
6673:     .SWACCESS("RW"),
6674:     .RESVAL  (2'h0)
6675:   ) u_prio60 (
6676:     .clk_i   (clk_i    ),
6677:     .rst_ni  (rst_ni  ),
6678: 
6679:     // from register interface
6680:     .we     (prio60_we),
6681:     .wd     (prio60_wd),
6682: 
6683:     // from internal hardware
6684:     .de     (1'b0),
6685:     .d      ('0  ),
6686: 
6687:     // to internal hardware
6688:     .qe     (),
6689:     .q      (reg2hw.prio60.q ),
6690: 
6691:     // to register interface (read)
6692:     .qs     (prio60_qs)
6693:   );
6694: 
6695: 
6696:   // R[prio61]: V(False)
6697: 
6698:   prim_subreg #(
6699:     .DW      (2),
6700:     .SWACCESS("RW"),
6701:     .RESVAL  (2'h0)
6702:   ) u_prio61 (
6703:     .clk_i   (clk_i    ),
6704:     .rst_ni  (rst_ni  ),
6705: 
6706:     // from register interface
6707:     .we     (prio61_we),
6708:     .wd     (prio61_wd),
6709: 
6710:     // from internal hardware
6711:     .de     (1'b0),
6712:     .d      ('0  ),
6713: 
6714:     // to internal hardware
6715:     .qe     (),
6716:     .q      (reg2hw.prio61.q ),
6717: 
6718:     // to register interface (read)
6719:     .qs     (prio61_qs)
6720:   );
6721: 
6722: 
6723:   // R[prio62]: V(False)
6724: 
6725:   prim_subreg #(
6726:     .DW      (2),
6727:     .SWACCESS("RW"),
6728:     .RESVAL  (2'h0)
6729:   ) u_prio62 (
6730:     .clk_i   (clk_i    ),
6731:     .rst_ni  (rst_ni  ),
6732: 
6733:     // from register interface
6734:     .we     (prio62_we),
6735:     .wd     (prio62_wd),
6736: 
6737:     // from internal hardware
6738:     .de     (1'b0),
6739:     .d      ('0  ),
6740: 
6741:     // to internal hardware
6742:     .qe     (),
6743:     .q      (reg2hw.prio62.q ),
6744: 
6745:     // to register interface (read)
6746:     .qs     (prio62_qs)
6747:   );
6748: 
6749: 
6750:   // R[prio63]: V(False)
6751: 
6752:   prim_subreg #(
6753:     .DW      (2),
6754:     .SWACCESS("RW"),
6755:     .RESVAL  (2'h0)
6756:   ) u_prio63 (
6757:     .clk_i   (clk_i    ),
6758:     .rst_ni  (rst_ni  ),
6759: 
6760:     // from register interface
6761:     .we     (prio63_we),
6762:     .wd     (prio63_wd),
6763: 
6764:     // from internal hardware
6765:     .de     (1'b0),
6766:     .d      ('0  ),
6767: 
6768:     // to internal hardware
6769:     .qe     (),
6770:     .q      (reg2hw.prio63.q ),
6771: 
6772:     // to register interface (read)
6773:     .qs     (prio63_qs)
6774:   );
6775: 
6776: 
6777:   // R[prio64]: V(False)
6778: 
6779:   prim_subreg #(
6780:     .DW      (2),
6781:     .SWACCESS("RW"),
6782:     .RESVAL  (2'h0)
6783:   ) u_prio64 (
6784:     .clk_i   (clk_i    ),
6785:     .rst_ni  (rst_ni  ),
6786: 
6787:     // from register interface
6788:     .we     (prio64_we),
6789:     .wd     (prio64_wd),
6790: 
6791:     // from internal hardware
6792:     .de     (1'b0),
6793:     .d      ('0  ),
6794: 
6795:     // to internal hardware
6796:     .qe     (),
6797:     .q      (reg2hw.prio64.q ),
6798: 
6799:     // to register interface (read)
6800:     .qs     (prio64_qs)
6801:   );
6802: 
6803: 
6804:   // R[prio65]: V(False)
6805: 
6806:   prim_subreg #(
6807:     .DW      (2),
6808:     .SWACCESS("RW"),
6809:     .RESVAL  (2'h0)
6810:   ) u_prio65 (
6811:     .clk_i   (clk_i    ),
6812:     .rst_ni  (rst_ni  ),
6813: 
6814:     // from register interface
6815:     .we     (prio65_we),
6816:     .wd     (prio65_wd),
6817: 
6818:     // from internal hardware
6819:     .de     (1'b0),
6820:     .d      ('0  ),
6821: 
6822:     // to internal hardware
6823:     .qe     (),
6824:     .q      (reg2hw.prio65.q ),
6825: 
6826:     // to register interface (read)
6827:     .qs     (prio65_qs)
6828:   );
6829: 
6830: 
6831:   // R[prio66]: V(False)
6832: 
6833:   prim_subreg #(
6834:     .DW      (2),
6835:     .SWACCESS("RW"),
6836:     .RESVAL  (2'h0)
6837:   ) u_prio66 (
6838:     .clk_i   (clk_i    ),
6839:     .rst_ni  (rst_ni  ),
6840: 
6841:     // from register interface
6842:     .we     (prio66_we),
6843:     .wd     (prio66_wd),
6844: 
6845:     // from internal hardware
6846:     .de     (1'b0),
6847:     .d      ('0  ),
6848: 
6849:     // to internal hardware
6850:     .qe     (),
6851:     .q      (reg2hw.prio66.q ),
6852: 
6853:     // to register interface (read)
6854:     .qs     (prio66_qs)
6855:   );
6856: 
6857: 
6858:   // R[prio67]: V(False)
6859: 
6860:   prim_subreg #(
6861:     .DW      (2),
6862:     .SWACCESS("RW"),
6863:     .RESVAL  (2'h0)
6864:   ) u_prio67 (
6865:     .clk_i   (clk_i    ),
6866:     .rst_ni  (rst_ni  ),
6867: 
6868:     // from register interface
6869:     .we     (prio67_we),
6870:     .wd     (prio67_wd),
6871: 
6872:     // from internal hardware
6873:     .de     (1'b0),
6874:     .d      ('0  ),
6875: 
6876:     // to internal hardware
6877:     .qe     (),
6878:     .q      (reg2hw.prio67.q ),
6879: 
6880:     // to register interface (read)
6881:     .qs     (prio67_qs)
6882:   );
6883: 
6884: 
6885:   // R[prio68]: V(False)
6886: 
6887:   prim_subreg #(
6888:     .DW      (2),
6889:     .SWACCESS("RW"),
6890:     .RESVAL  (2'h0)
6891:   ) u_prio68 (
6892:     .clk_i   (clk_i    ),
6893:     .rst_ni  (rst_ni  ),
6894: 
6895:     // from register interface
6896:     .we     (prio68_we),
6897:     .wd     (prio68_wd),
6898: 
6899:     // from internal hardware
6900:     .de     (1'b0),
6901:     .d      ('0  ),
6902: 
6903:     // to internal hardware
6904:     .qe     (),
6905:     .q      (reg2hw.prio68.q ),
6906: 
6907:     // to register interface (read)
6908:     .qs     (prio68_qs)
6909:   );
6910: 
6911: 
6912:   // R[prio69]: V(False)
6913: 
6914:   prim_subreg #(
6915:     .DW      (2),
6916:     .SWACCESS("RW"),
6917:     .RESVAL  (2'h0)
6918:   ) u_prio69 (
6919:     .clk_i   (clk_i    ),
6920:     .rst_ni  (rst_ni  ),
6921: 
6922:     // from register interface
6923:     .we     (prio69_we),
6924:     .wd     (prio69_wd),
6925: 
6926:     // from internal hardware
6927:     .de     (1'b0),
6928:     .d      ('0  ),
6929: 
6930:     // to internal hardware
6931:     .qe     (),
6932:     .q      (reg2hw.prio69.q ),
6933: 
6934:     // to register interface (read)
6935:     .qs     (prio69_qs)
6936:   );
6937: 
6938: 
6939:   // R[prio70]: V(False)
6940: 
6941:   prim_subreg #(
6942:     .DW      (2),
6943:     .SWACCESS("RW"),
6944:     .RESVAL  (2'h0)
6945:   ) u_prio70 (
6946:     .clk_i   (clk_i    ),
6947:     .rst_ni  (rst_ni  ),
6948: 
6949:     // from register interface
6950:     .we     (prio70_we),
6951:     .wd     (prio70_wd),
6952: 
6953:     // from internal hardware
6954:     .de     (1'b0),
6955:     .d      ('0  ),
6956: 
6957:     // to internal hardware
6958:     .qe     (),
6959:     .q      (reg2hw.prio70.q ),
6960: 
6961:     // to register interface (read)
6962:     .qs     (prio70_qs)
6963:   );
6964: 
6965: 
6966:   // R[prio71]: V(False)
6967: 
6968:   prim_subreg #(
6969:     .DW      (2),
6970:     .SWACCESS("RW"),
6971:     .RESVAL  (2'h0)
6972:   ) u_prio71 (
6973:     .clk_i   (clk_i    ),
6974:     .rst_ni  (rst_ni  ),
6975: 
6976:     // from register interface
6977:     .we     (prio71_we),
6978:     .wd     (prio71_wd),
6979: 
6980:     // from internal hardware
6981:     .de     (1'b0),
6982:     .d      ('0  ),
6983: 
6984:     // to internal hardware
6985:     .qe     (),
6986:     .q      (reg2hw.prio71.q ),
6987: 
6988:     // to register interface (read)
6989:     .qs     (prio71_qs)
6990:   );
6991: 
6992: 
6993:   // R[prio72]: V(False)
6994: 
6995:   prim_subreg #(
6996:     .DW      (2),
6997:     .SWACCESS("RW"),
6998:     .RESVAL  (2'h0)
6999:   ) u_prio72 (
7000:     .clk_i   (clk_i    ),
7001:     .rst_ni  (rst_ni  ),
7002: 
7003:     // from register interface
7004:     .we     (prio72_we),
7005:     .wd     (prio72_wd),
7006: 
7007:     // from internal hardware
7008:     .de     (1'b0),
7009:     .d      ('0  ),
7010: 
7011:     // to internal hardware
7012:     .qe     (),
7013:     .q      (reg2hw.prio72.q ),
7014: 
7015:     // to register interface (read)
7016:     .qs     (prio72_qs)
7017:   );
7018: 
7019: 
7020:   // R[prio73]: V(False)
7021: 
7022:   prim_subreg #(
7023:     .DW      (2),
7024:     .SWACCESS("RW"),
7025:     .RESVAL  (2'h0)
7026:   ) u_prio73 (
7027:     .clk_i   (clk_i    ),
7028:     .rst_ni  (rst_ni  ),
7029: 
7030:     // from register interface
7031:     .we     (prio73_we),
7032:     .wd     (prio73_wd),
7033: 
7034:     // from internal hardware
7035:     .de     (1'b0),
7036:     .d      ('0  ),
7037: 
7038:     // to internal hardware
7039:     .qe     (),
7040:     .q      (reg2hw.prio73.q ),
7041: 
7042:     // to register interface (read)
7043:     .qs     (prio73_qs)
7044:   );
7045: 
7046: 
7047:   // R[prio74]: V(False)
7048: 
7049:   prim_subreg #(
7050:     .DW      (2),
7051:     .SWACCESS("RW"),
7052:     .RESVAL  (2'h0)
7053:   ) u_prio74 (
7054:     .clk_i   (clk_i    ),
7055:     .rst_ni  (rst_ni  ),
7056: 
7057:     // from register interface
7058:     .we     (prio74_we),
7059:     .wd     (prio74_wd),
7060: 
7061:     // from internal hardware
7062:     .de     (1'b0),
7063:     .d      ('0  ),
7064: 
7065:     // to internal hardware
7066:     .qe     (),
7067:     .q      (reg2hw.prio74.q ),
7068: 
7069:     // to register interface (read)
7070:     .qs     (prio74_qs)
7071:   );
7072: 
7073: 
7074:   // R[prio75]: V(False)
7075: 
7076:   prim_subreg #(
7077:     .DW      (2),
7078:     .SWACCESS("RW"),
7079:     .RESVAL  (2'h0)
7080:   ) u_prio75 (
7081:     .clk_i   (clk_i    ),
7082:     .rst_ni  (rst_ni  ),
7083: 
7084:     // from register interface
7085:     .we     (prio75_we),
7086:     .wd     (prio75_wd),
7087: 
7088:     // from internal hardware
7089:     .de     (1'b0),
7090:     .d      ('0  ),
7091: 
7092:     // to internal hardware
7093:     .qe     (),
7094:     .q      (reg2hw.prio75.q ),
7095: 
7096:     // to register interface (read)
7097:     .qs     (prio75_qs)
7098:   );
7099: 
7100: 
7101:   // R[prio76]: V(False)
7102: 
7103:   prim_subreg #(
7104:     .DW      (2),
7105:     .SWACCESS("RW"),
7106:     .RESVAL  (2'h0)
7107:   ) u_prio76 (
7108:     .clk_i   (clk_i    ),
7109:     .rst_ni  (rst_ni  ),
7110: 
7111:     // from register interface
7112:     .we     (prio76_we),
7113:     .wd     (prio76_wd),
7114: 
7115:     // from internal hardware
7116:     .de     (1'b0),
7117:     .d      ('0  ),
7118: 
7119:     // to internal hardware
7120:     .qe     (),
7121:     .q      (reg2hw.prio76.q ),
7122: 
7123:     // to register interface (read)
7124:     .qs     (prio76_qs)
7125:   );
7126: 
7127: 
7128:   // R[prio77]: V(False)
7129: 
7130:   prim_subreg #(
7131:     .DW      (2),
7132:     .SWACCESS("RW"),
7133:     .RESVAL  (2'h0)
7134:   ) u_prio77 (
7135:     .clk_i   (clk_i    ),
7136:     .rst_ni  (rst_ni  ),
7137: 
7138:     // from register interface
7139:     .we     (prio77_we),
7140:     .wd     (prio77_wd),
7141: 
7142:     // from internal hardware
7143:     .de     (1'b0),
7144:     .d      ('0  ),
7145: 
7146:     // to internal hardware
7147:     .qe     (),
7148:     .q      (reg2hw.prio77.q ),
7149: 
7150:     // to register interface (read)
7151:     .qs     (prio77_qs)
7152:   );
7153: 
7154: 
7155:   // R[prio78]: V(False)
7156: 
7157:   prim_subreg #(
7158:     .DW      (2),
7159:     .SWACCESS("RW"),
7160:     .RESVAL  (2'h0)
7161:   ) u_prio78 (
7162:     .clk_i   (clk_i    ),
7163:     .rst_ni  (rst_ni  ),
7164: 
7165:     // from register interface
7166:     .we     (prio78_we),
7167:     .wd     (prio78_wd),
7168: 
7169:     // from internal hardware
7170:     .de     (1'b0),
7171:     .d      ('0  ),
7172: 
7173:     // to internal hardware
7174:     .qe     (),
7175:     .q      (reg2hw.prio78.q ),
7176: 
7177:     // to register interface (read)
7178:     .qs     (prio78_qs)
7179:   );
7180: 
7181: 
7182:   // R[prio79]: V(False)
7183: 
7184:   prim_subreg #(
7185:     .DW      (2),
7186:     .SWACCESS("RW"),
7187:     .RESVAL  (2'h0)
7188:   ) u_prio79 (
7189:     .clk_i   (clk_i    ),
7190:     .rst_ni  (rst_ni  ),
7191: 
7192:     // from register interface
7193:     .we     (prio79_we),
7194:     .wd     (prio79_wd),
7195: 
7196:     // from internal hardware
7197:     .de     (1'b0),
7198:     .d      ('0  ),
7199: 
7200:     // to internal hardware
7201:     .qe     (),
7202:     .q      (reg2hw.prio79.q ),
7203: 
7204:     // to register interface (read)
7205:     .qs     (prio79_qs)
7206:   );
7207: 
7208: 
7209:   // R[prio80]: V(False)
7210: 
7211:   prim_subreg #(
7212:     .DW      (2),
7213:     .SWACCESS("RW"),
7214:     .RESVAL  (2'h0)
7215:   ) u_prio80 (
7216:     .clk_i   (clk_i    ),
7217:     .rst_ni  (rst_ni  ),
7218: 
7219:     // from register interface
7220:     .we     (prio80_we),
7221:     .wd     (prio80_wd),
7222: 
7223:     // from internal hardware
7224:     .de     (1'b0),
7225:     .d      ('0  ),
7226: 
7227:     // to internal hardware
7228:     .qe     (),
7229:     .q      (reg2hw.prio80.q ),
7230: 
7231:     // to register interface (read)
7232:     .qs     (prio80_qs)
7233:   );
7234: 
7235: 
7236: 
7237:   // Subregister 0 of Multireg ie0
7238:   // R[ie00]: V(False)
7239: 
7240:   // F[e0]: 0:0
7241:   prim_subreg #(
7242:     .DW      (1),
7243:     .SWACCESS("RW"),
7244:     .RESVAL  (1'h0)
7245:   ) u_ie00_e0 (
7246:     .clk_i   (clk_i    ),
7247:     .rst_ni  (rst_ni  ),
7248: 
7249:     // from register interface
7250:     .we     (ie00_e0_we),
7251:     .wd     (ie00_e0_wd),
7252: 
7253:     // from internal hardware
7254:     .de     (1'b0),
7255:     .d      ('0  ),
7256: 
7257:     // to internal hardware
7258:     .qe     (),
7259:     .q      (reg2hw.ie0[0].q ),
7260: 
7261:     // to register interface (read)
7262:     .qs     (ie00_e0_qs)
7263:   );
7264: 
7265: 
7266:   // F[e1]: 1:1
7267:   prim_subreg #(
7268:     .DW      (1),
7269:     .SWACCESS("RW"),
7270:     .RESVAL  (1'h0)
7271:   ) u_ie00_e1 (
7272:     .clk_i   (clk_i    ),
7273:     .rst_ni  (rst_ni  ),
7274: 
7275:     // from register interface
7276:     .we     (ie00_e1_we),
7277:     .wd     (ie00_e1_wd),
7278: 
7279:     // from internal hardware
7280:     .de     (1'b0),
7281:     .d      ('0  ),
7282: 
7283:     // to internal hardware
7284:     .qe     (),
7285:     .q      (reg2hw.ie0[1].q ),
7286: 
7287:     // to register interface (read)
7288:     .qs     (ie00_e1_qs)
7289:   );
7290: 
7291: 
7292:   // F[e2]: 2:2
7293:   prim_subreg #(
7294:     .DW      (1),
7295:     .SWACCESS("RW"),
7296:     .RESVAL  (1'h0)
7297:   ) u_ie00_e2 (
7298:     .clk_i   (clk_i    ),
7299:     .rst_ni  (rst_ni  ),
7300: 
7301:     // from register interface
7302:     .we     (ie00_e2_we),
7303:     .wd     (ie00_e2_wd),
7304: 
7305:     // from internal hardware
7306:     .de     (1'b0),
7307:     .d      ('0  ),
7308: 
7309:     // to internal hardware
7310:     .qe     (),
7311:     .q      (reg2hw.ie0[2].q ),
7312: 
7313:     // to register interface (read)
7314:     .qs     (ie00_e2_qs)
7315:   );
7316: 
7317: 
7318:   // F[e3]: 3:3
7319:   prim_subreg #(
7320:     .DW      (1),
7321:     .SWACCESS("RW"),
7322:     .RESVAL  (1'h0)
7323:   ) u_ie00_e3 (
7324:     .clk_i   (clk_i    ),
7325:     .rst_ni  (rst_ni  ),
7326: 
7327:     // from register interface
7328:     .we     (ie00_e3_we),
7329:     .wd     (ie00_e3_wd),
7330: 
7331:     // from internal hardware
7332:     .de     (1'b0),
7333:     .d      ('0  ),
7334: 
7335:     // to internal hardware
7336:     .qe     (),
7337:     .q      (reg2hw.ie0[3].q ),
7338: 
7339:     // to register interface (read)
7340:     .qs     (ie00_e3_qs)
7341:   );
7342: 
7343: 
7344:   // F[e4]: 4:4
7345:   prim_subreg #(
7346:     .DW      (1),
7347:     .SWACCESS("RW"),
7348:     .RESVAL  (1'h0)
7349:   ) u_ie00_e4 (
7350:     .clk_i   (clk_i    ),
7351:     .rst_ni  (rst_ni  ),
7352: 
7353:     // from register interface
7354:     .we     (ie00_e4_we),
7355:     .wd     (ie00_e4_wd),
7356: 
7357:     // from internal hardware
7358:     .de     (1'b0),
7359:     .d      ('0  ),
7360: 
7361:     // to internal hardware
7362:     .qe     (),
7363:     .q      (reg2hw.ie0[4].q ),
7364: 
7365:     // to register interface (read)
7366:     .qs     (ie00_e4_qs)
7367:   );
7368: 
7369: 
7370:   // F[e5]: 5:5
7371:   prim_subreg #(
7372:     .DW      (1),
7373:     .SWACCESS("RW"),
7374:     .RESVAL  (1'h0)
7375:   ) u_ie00_e5 (
7376:     .clk_i   (clk_i    ),
7377:     .rst_ni  (rst_ni  ),
7378: 
7379:     // from register interface
7380:     .we     (ie00_e5_we),
7381:     .wd     (ie00_e5_wd),
7382: 
7383:     // from internal hardware
7384:     .de     (1'b0),
7385:     .d      ('0  ),
7386: 
7387:     // to internal hardware
7388:     .qe     (),
7389:     .q      (reg2hw.ie0[5].q ),
7390: 
7391:     // to register interface (read)
7392:     .qs     (ie00_e5_qs)
7393:   );
7394: 
7395: 
7396:   // F[e6]: 6:6
7397:   prim_subreg #(
7398:     .DW      (1),
7399:     .SWACCESS("RW"),
7400:     .RESVAL  (1'h0)
7401:   ) u_ie00_e6 (
7402:     .clk_i   (clk_i    ),
7403:     .rst_ni  (rst_ni  ),
7404: 
7405:     // from register interface
7406:     .we     (ie00_e6_we),
7407:     .wd     (ie00_e6_wd),
7408: 
7409:     // from internal hardware
7410:     .de     (1'b0),
7411:     .d      ('0  ),
7412: 
7413:     // to internal hardware
7414:     .qe     (),
7415:     .q      (reg2hw.ie0[6].q ),
7416: 
7417:     // to register interface (read)
7418:     .qs     (ie00_e6_qs)
7419:   );
7420: 
7421: 
7422:   // F[e7]: 7:7
7423:   prim_subreg #(
7424:     .DW      (1),
7425:     .SWACCESS("RW"),
7426:     .RESVAL  (1'h0)
7427:   ) u_ie00_e7 (
7428:     .clk_i   (clk_i    ),
7429:     .rst_ni  (rst_ni  ),
7430: 
7431:     // from register interface
7432:     .we     (ie00_e7_we),
7433:     .wd     (ie00_e7_wd),
7434: 
7435:     // from internal hardware
7436:     .de     (1'b0),
7437:     .d      ('0  ),
7438: 
7439:     // to internal hardware
7440:     .qe     (),
7441:     .q      (reg2hw.ie0[7].q ),
7442: 
7443:     // to register interface (read)
7444:     .qs     (ie00_e7_qs)
7445:   );
7446: 
7447: 
7448:   // F[e8]: 8:8
7449:   prim_subreg #(
7450:     .DW      (1),
7451:     .SWACCESS("RW"),
7452:     .RESVAL  (1'h0)
7453:   ) u_ie00_e8 (
7454:     .clk_i   (clk_i    ),
7455:     .rst_ni  (rst_ni  ),
7456: 
7457:     // from register interface
7458:     .we     (ie00_e8_we),
7459:     .wd     (ie00_e8_wd),
7460: 
7461:     // from internal hardware
7462:     .de     (1'b0),
7463:     .d      ('0  ),
7464: 
7465:     // to internal hardware
7466:     .qe     (),
7467:     .q      (reg2hw.ie0[8].q ),
7468: 
7469:     // to register interface (read)
7470:     .qs     (ie00_e8_qs)
7471:   );
7472: 
7473: 
7474:   // F[e9]: 9:9
7475:   prim_subreg #(
7476:     .DW      (1),
7477:     .SWACCESS("RW"),
7478:     .RESVAL  (1'h0)
7479:   ) u_ie00_e9 (
7480:     .clk_i   (clk_i    ),
7481:     .rst_ni  (rst_ni  ),
7482: 
7483:     // from register interface
7484:     .we     (ie00_e9_we),
7485:     .wd     (ie00_e9_wd),
7486: 
7487:     // from internal hardware
7488:     .de     (1'b0),
7489:     .d      ('0  ),
7490: 
7491:     // to internal hardware
7492:     .qe     (),
7493:     .q      (reg2hw.ie0[9].q ),
7494: 
7495:     // to register interface (read)
7496:     .qs     (ie00_e9_qs)
7497:   );
7498: 
7499: 
7500:   // F[e10]: 10:10
7501:   prim_subreg #(
7502:     .DW      (1),
7503:     .SWACCESS("RW"),
7504:     .RESVAL  (1'h0)
7505:   ) u_ie00_e10 (
7506:     .clk_i   (clk_i    ),
7507:     .rst_ni  (rst_ni  ),
7508: 
7509:     // from register interface
7510:     .we     (ie00_e10_we),
7511:     .wd     (ie00_e10_wd),
7512: 
7513:     // from internal hardware
7514:     .de     (1'b0),
7515:     .d      ('0  ),
7516: 
7517:     // to internal hardware
7518:     .qe     (),
7519:     .q      (reg2hw.ie0[10].q ),
7520: 
7521:     // to register interface (read)
7522:     .qs     (ie00_e10_qs)
7523:   );
7524: 
7525: 
7526:   // F[e11]: 11:11
7527:   prim_subreg #(
7528:     .DW      (1),
7529:     .SWACCESS("RW"),
7530:     .RESVAL  (1'h0)
7531:   ) u_ie00_e11 (
7532:     .clk_i   (clk_i    ),
7533:     .rst_ni  (rst_ni  ),
7534: 
7535:     // from register interface
7536:     .we     (ie00_e11_we),
7537:     .wd     (ie00_e11_wd),
7538: 
7539:     // from internal hardware
7540:     .de     (1'b0),
7541:     .d      ('0  ),
7542: 
7543:     // to internal hardware
7544:     .qe     (),
7545:     .q      (reg2hw.ie0[11].q ),
7546: 
7547:     // to register interface (read)
7548:     .qs     (ie00_e11_qs)
7549:   );
7550: 
7551: 
7552:   // F[e12]: 12:12
7553:   prim_subreg #(
7554:     .DW      (1),
7555:     .SWACCESS("RW"),
7556:     .RESVAL  (1'h0)
7557:   ) u_ie00_e12 (
7558:     .clk_i   (clk_i    ),
7559:     .rst_ni  (rst_ni  ),
7560: 
7561:     // from register interface
7562:     .we     (ie00_e12_we),
7563:     .wd     (ie00_e12_wd),
7564: 
7565:     // from internal hardware
7566:     .de     (1'b0),
7567:     .d      ('0  ),
7568: 
7569:     // to internal hardware
7570:     .qe     (),
7571:     .q      (reg2hw.ie0[12].q ),
7572: 
7573:     // to register interface (read)
7574:     .qs     (ie00_e12_qs)
7575:   );
7576: 
7577: 
7578:   // F[e13]: 13:13
7579:   prim_subreg #(
7580:     .DW      (1),
7581:     .SWACCESS("RW"),
7582:     .RESVAL  (1'h0)
7583:   ) u_ie00_e13 (
7584:     .clk_i   (clk_i    ),
7585:     .rst_ni  (rst_ni  ),
7586: 
7587:     // from register interface
7588:     .we     (ie00_e13_we),
7589:     .wd     (ie00_e13_wd),
7590: 
7591:     // from internal hardware
7592:     .de     (1'b0),
7593:     .d      ('0  ),
7594: 
7595:     // to internal hardware
7596:     .qe     (),
7597:     .q      (reg2hw.ie0[13].q ),
7598: 
7599:     // to register interface (read)
7600:     .qs     (ie00_e13_qs)
7601:   );
7602: 
7603: 
7604:   // F[e14]: 14:14
7605:   prim_subreg #(
7606:     .DW      (1),
7607:     .SWACCESS("RW"),
7608:     .RESVAL  (1'h0)
7609:   ) u_ie00_e14 (
7610:     .clk_i   (clk_i    ),
7611:     .rst_ni  (rst_ni  ),
7612: 
7613:     // from register interface
7614:     .we     (ie00_e14_we),
7615:     .wd     (ie00_e14_wd),
7616: 
7617:     // from internal hardware
7618:     .de     (1'b0),
7619:     .d      ('0  ),
7620: 
7621:     // to internal hardware
7622:     .qe     (),
7623:     .q      (reg2hw.ie0[14].q ),
7624: 
7625:     // to register interface (read)
7626:     .qs     (ie00_e14_qs)
7627:   );
7628: 
7629: 
7630:   // F[e15]: 15:15
7631:   prim_subreg #(
7632:     .DW      (1),
7633:     .SWACCESS("RW"),
7634:     .RESVAL  (1'h0)
7635:   ) u_ie00_e15 (
7636:     .clk_i   (clk_i    ),
7637:     .rst_ni  (rst_ni  ),
7638: 
7639:     // from register interface
7640:     .we     (ie00_e15_we),
7641:     .wd     (ie00_e15_wd),
7642: 
7643:     // from internal hardware
7644:     .de     (1'b0),
7645:     .d      ('0  ),
7646: 
7647:     // to internal hardware
7648:     .qe     (),
7649:     .q      (reg2hw.ie0[15].q ),
7650: 
7651:     // to register interface (read)
7652:     .qs     (ie00_e15_qs)
7653:   );
7654: 
7655: 
7656:   // F[e16]: 16:16
7657:   prim_subreg #(
7658:     .DW      (1),
7659:     .SWACCESS("RW"),
7660:     .RESVAL  (1'h0)
7661:   ) u_ie00_e16 (
7662:     .clk_i   (clk_i    ),
7663:     .rst_ni  (rst_ni  ),
7664: 
7665:     // from register interface
7666:     .we     (ie00_e16_we),
7667:     .wd     (ie00_e16_wd),
7668: 
7669:     // from internal hardware
7670:     .de     (1'b0),
7671:     .d      ('0  ),
7672: 
7673:     // to internal hardware
7674:     .qe     (),
7675:     .q      (reg2hw.ie0[16].q ),
7676: 
7677:     // to register interface (read)
7678:     .qs     (ie00_e16_qs)
7679:   );
7680: 
7681: 
7682:   // F[e17]: 17:17
7683:   prim_subreg #(
7684:     .DW      (1),
7685:     .SWACCESS("RW"),
7686:     .RESVAL  (1'h0)
7687:   ) u_ie00_e17 (
7688:     .clk_i   (clk_i    ),
7689:     .rst_ni  (rst_ni  ),
7690: 
7691:     // from register interface
7692:     .we     (ie00_e17_we),
7693:     .wd     (ie00_e17_wd),
7694: 
7695:     // from internal hardware
7696:     .de     (1'b0),
7697:     .d      ('0  ),
7698: 
7699:     // to internal hardware
7700:     .qe     (),
7701:     .q      (reg2hw.ie0[17].q ),
7702: 
7703:     // to register interface (read)
7704:     .qs     (ie00_e17_qs)
7705:   );
7706: 
7707: 
7708:   // F[e18]: 18:18
7709:   prim_subreg #(
7710:     .DW      (1),
7711:     .SWACCESS("RW"),
7712:     .RESVAL  (1'h0)
7713:   ) u_ie00_e18 (
7714:     .clk_i   (clk_i    ),
7715:     .rst_ni  (rst_ni  ),
7716: 
7717:     // from register interface
7718:     .we     (ie00_e18_we),
7719:     .wd     (ie00_e18_wd),
7720: 
7721:     // from internal hardware
7722:     .de     (1'b0),
7723:     .d      ('0  ),
7724: 
7725:     // to internal hardware
7726:     .qe     (),
7727:     .q      (reg2hw.ie0[18].q ),
7728: 
7729:     // to register interface (read)
7730:     .qs     (ie00_e18_qs)
7731:   );
7732: 
7733: 
7734:   // F[e19]: 19:19
7735:   prim_subreg #(
7736:     .DW      (1),
7737:     .SWACCESS("RW"),
7738:     .RESVAL  (1'h0)
7739:   ) u_ie00_e19 (
7740:     .clk_i   (clk_i    ),
7741:     .rst_ni  (rst_ni  ),
7742: 
7743:     // from register interface
7744:     .we     (ie00_e19_we),
7745:     .wd     (ie00_e19_wd),
7746: 
7747:     // from internal hardware
7748:     .de     (1'b0),
7749:     .d      ('0  ),
7750: 
7751:     // to internal hardware
7752:     .qe     (),
7753:     .q      (reg2hw.ie0[19].q ),
7754: 
7755:     // to register interface (read)
7756:     .qs     (ie00_e19_qs)
7757:   );
7758: 
7759: 
7760:   // F[e20]: 20:20
7761:   prim_subreg #(
7762:     .DW      (1),
7763:     .SWACCESS("RW"),
7764:     .RESVAL  (1'h0)
7765:   ) u_ie00_e20 (
7766:     .clk_i   (clk_i    ),
7767:     .rst_ni  (rst_ni  ),
7768: 
7769:     // from register interface
7770:     .we     (ie00_e20_we),
7771:     .wd     (ie00_e20_wd),
7772: 
7773:     // from internal hardware
7774:     .de     (1'b0),
7775:     .d      ('0  ),
7776: 
7777:     // to internal hardware
7778:     .qe     (),
7779:     .q      (reg2hw.ie0[20].q ),
7780: 
7781:     // to register interface (read)
7782:     .qs     (ie00_e20_qs)
7783:   );
7784: 
7785: 
7786:   // F[e21]: 21:21
7787:   prim_subreg #(
7788:     .DW      (1),
7789:     .SWACCESS("RW"),
7790:     .RESVAL  (1'h0)
7791:   ) u_ie00_e21 (
7792:     .clk_i   (clk_i    ),
7793:     .rst_ni  (rst_ni  ),
7794: 
7795:     // from register interface
7796:     .we     (ie00_e21_we),
7797:     .wd     (ie00_e21_wd),
7798: 
7799:     // from internal hardware
7800:     .de     (1'b0),
7801:     .d      ('0  ),
7802: 
7803:     // to internal hardware
7804:     .qe     (),
7805:     .q      (reg2hw.ie0[21].q ),
7806: 
7807:     // to register interface (read)
7808:     .qs     (ie00_e21_qs)
7809:   );
7810: 
7811: 
7812:   // F[e22]: 22:22
7813:   prim_subreg #(
7814:     .DW      (1),
7815:     .SWACCESS("RW"),
7816:     .RESVAL  (1'h0)
7817:   ) u_ie00_e22 (
7818:     .clk_i   (clk_i    ),
7819:     .rst_ni  (rst_ni  ),
7820: 
7821:     // from register interface
7822:     .we     (ie00_e22_we),
7823:     .wd     (ie00_e22_wd),
7824: 
7825:     // from internal hardware
7826:     .de     (1'b0),
7827:     .d      ('0  ),
7828: 
7829:     // to internal hardware
7830:     .qe     (),
7831:     .q      (reg2hw.ie0[22].q ),
7832: 
7833:     // to register interface (read)
7834:     .qs     (ie00_e22_qs)
7835:   );
7836: 
7837: 
7838:   // F[e23]: 23:23
7839:   prim_subreg #(
7840:     .DW      (1),
7841:     .SWACCESS("RW"),
7842:     .RESVAL  (1'h0)
7843:   ) u_ie00_e23 (
7844:     .clk_i   (clk_i    ),
7845:     .rst_ni  (rst_ni  ),
7846: 
7847:     // from register interface
7848:     .we     (ie00_e23_we),
7849:     .wd     (ie00_e23_wd),
7850: 
7851:     // from internal hardware
7852:     .de     (1'b0),
7853:     .d      ('0  ),
7854: 
7855:     // to internal hardware
7856:     .qe     (),
7857:     .q      (reg2hw.ie0[23].q ),
7858: 
7859:     // to register interface (read)
7860:     .qs     (ie00_e23_qs)
7861:   );
7862: 
7863: 
7864:   // F[e24]: 24:24
7865:   prim_subreg #(
7866:     .DW      (1),
7867:     .SWACCESS("RW"),
7868:     .RESVAL  (1'h0)
7869:   ) u_ie00_e24 (
7870:     .clk_i   (clk_i    ),
7871:     .rst_ni  (rst_ni  ),
7872: 
7873:     // from register interface
7874:     .we     (ie00_e24_we),
7875:     .wd     (ie00_e24_wd),
7876: 
7877:     // from internal hardware
7878:     .de     (1'b0),
7879:     .d      ('0  ),
7880: 
7881:     // to internal hardware
7882:     .qe     (),
7883:     .q      (reg2hw.ie0[24].q ),
7884: 
7885:     // to register interface (read)
7886:     .qs     (ie00_e24_qs)
7887:   );
7888: 
7889: 
7890:   // F[e25]: 25:25
7891:   prim_subreg #(
7892:     .DW      (1),
7893:     .SWACCESS("RW"),
7894:     .RESVAL  (1'h0)
7895:   ) u_ie00_e25 (
7896:     .clk_i   (clk_i    ),
7897:     .rst_ni  (rst_ni  ),
7898: 
7899:     // from register interface
7900:     .we     (ie00_e25_we),
7901:     .wd     (ie00_e25_wd),
7902: 
7903:     // from internal hardware
7904:     .de     (1'b0),
7905:     .d      ('0  ),
7906: 
7907:     // to internal hardware
7908:     .qe     (),
7909:     .q      (reg2hw.ie0[25].q ),
7910: 
7911:     // to register interface (read)
7912:     .qs     (ie00_e25_qs)
7913:   );
7914: 
7915: 
7916:   // F[e26]: 26:26
7917:   prim_subreg #(
7918:     .DW      (1),
7919:     .SWACCESS("RW"),
7920:     .RESVAL  (1'h0)
7921:   ) u_ie00_e26 (
7922:     .clk_i   (clk_i    ),
7923:     .rst_ni  (rst_ni  ),
7924: 
7925:     // from register interface
7926:     .we     (ie00_e26_we),
7927:     .wd     (ie00_e26_wd),
7928: 
7929:     // from internal hardware
7930:     .de     (1'b0),
7931:     .d      ('0  ),
7932: 
7933:     // to internal hardware
7934:     .qe     (),
7935:     .q      (reg2hw.ie0[26].q ),
7936: 
7937:     // to register interface (read)
7938:     .qs     (ie00_e26_qs)
7939:   );
7940: 
7941: 
7942:   // F[e27]: 27:27
7943:   prim_subreg #(
7944:     .DW      (1),
7945:     .SWACCESS("RW"),
7946:     .RESVAL  (1'h0)
7947:   ) u_ie00_e27 (
7948:     .clk_i   (clk_i    ),
7949:     .rst_ni  (rst_ni  ),
7950: 
7951:     // from register interface
7952:     .we     (ie00_e27_we),
7953:     .wd     (ie00_e27_wd),
7954: 
7955:     // from internal hardware
7956:     .de     (1'b0),
7957:     .d      ('0  ),
7958: 
7959:     // to internal hardware
7960:     .qe     (),
7961:     .q      (reg2hw.ie0[27].q ),
7962: 
7963:     // to register interface (read)
7964:     .qs     (ie00_e27_qs)
7965:   );
7966: 
7967: 
7968:   // F[e28]: 28:28
7969:   prim_subreg #(
7970:     .DW      (1),
7971:     .SWACCESS("RW"),
7972:     .RESVAL  (1'h0)
7973:   ) u_ie00_e28 (
7974:     .clk_i   (clk_i    ),
7975:     .rst_ni  (rst_ni  ),
7976: 
7977:     // from register interface
7978:     .we     (ie00_e28_we),
7979:     .wd     (ie00_e28_wd),
7980: 
7981:     // from internal hardware
7982:     .de     (1'b0),
7983:     .d      ('0  ),
7984: 
7985:     // to internal hardware
7986:     .qe     (),
7987:     .q      (reg2hw.ie0[28].q ),
7988: 
7989:     // to register interface (read)
7990:     .qs     (ie00_e28_qs)
7991:   );
7992: 
7993: 
7994:   // F[e29]: 29:29
7995:   prim_subreg #(
7996:     .DW      (1),
7997:     .SWACCESS("RW"),
7998:     .RESVAL  (1'h0)
7999:   ) u_ie00_e29 (
8000:     .clk_i   (clk_i    ),
8001:     .rst_ni  (rst_ni  ),
8002: 
8003:     // from register interface
8004:     .we     (ie00_e29_we),
8005:     .wd     (ie00_e29_wd),
8006: 
8007:     // from internal hardware
8008:     .de     (1'b0),
8009:     .d      ('0  ),
8010: 
8011:     // to internal hardware
8012:     .qe     (),
8013:     .q      (reg2hw.ie0[29].q ),
8014: 
8015:     // to register interface (read)
8016:     .qs     (ie00_e29_qs)
8017:   );
8018: 
8019: 
8020:   // F[e30]: 30:30
8021:   prim_subreg #(
8022:     .DW      (1),
8023:     .SWACCESS("RW"),
8024:     .RESVAL  (1'h0)
8025:   ) u_ie00_e30 (
8026:     .clk_i   (clk_i    ),
8027:     .rst_ni  (rst_ni  ),
8028: 
8029:     // from register interface
8030:     .we     (ie00_e30_we),
8031:     .wd     (ie00_e30_wd),
8032: 
8033:     // from internal hardware
8034:     .de     (1'b0),
8035:     .d      ('0  ),
8036: 
8037:     // to internal hardware
8038:     .qe     (),
8039:     .q      (reg2hw.ie0[30].q ),
8040: 
8041:     // to register interface (read)
8042:     .qs     (ie00_e30_qs)
8043:   );
8044: 
8045: 
8046:   // F[e31]: 31:31
8047:   prim_subreg #(
8048:     .DW      (1),
8049:     .SWACCESS("RW"),
8050:     .RESVAL  (1'h0)
8051:   ) u_ie00_e31 (
8052:     .clk_i   (clk_i    ),
8053:     .rst_ni  (rst_ni  ),
8054: 
8055:     // from register interface
8056:     .we     (ie00_e31_we),
8057:     .wd     (ie00_e31_wd),
8058: 
8059:     // from internal hardware
8060:     .de     (1'b0),
8061:     .d      ('0  ),
8062: 
8063:     // to internal hardware
8064:     .qe     (),
8065:     .q      (reg2hw.ie0[31].q ),
8066: 
8067:     // to register interface (read)
8068:     .qs     (ie00_e31_qs)
8069:   );
8070: 
8071: 
8072:   // Subregister 32 of Multireg ie0
8073:   // R[ie01]: V(False)
8074: 
8075:   // F[e32]: 0:0
8076:   prim_subreg #(
8077:     .DW      (1),
8078:     .SWACCESS("RW"),
8079:     .RESVAL  (1'h0)
8080:   ) u_ie01_e32 (
8081:     .clk_i   (clk_i    ),
8082:     .rst_ni  (rst_ni  ),
8083: 
8084:     // from register interface
8085:     .we     (ie01_e32_we),
8086:     .wd     (ie01_e32_wd),
8087: 
8088:     // from internal hardware
8089:     .de     (1'b0),
8090:     .d      ('0  ),
8091: 
8092:     // to internal hardware
8093:     .qe     (),
8094:     .q      (reg2hw.ie0[32].q ),
8095: 
8096:     // to register interface (read)
8097:     .qs     (ie01_e32_qs)
8098:   );
8099: 
8100: 
8101:   // F[e33]: 1:1
8102:   prim_subreg #(
8103:     .DW      (1),
8104:     .SWACCESS("RW"),
8105:     .RESVAL  (1'h0)
8106:   ) u_ie01_e33 (
8107:     .clk_i   (clk_i    ),
8108:     .rst_ni  (rst_ni  ),
8109: 
8110:     // from register interface
8111:     .we     (ie01_e33_we),
8112:     .wd     (ie01_e33_wd),
8113: 
8114:     // from internal hardware
8115:     .de     (1'b0),
8116:     .d      ('0  ),
8117: 
8118:     // to internal hardware
8119:     .qe     (),
8120:     .q      (reg2hw.ie0[33].q ),
8121: 
8122:     // to register interface (read)
8123:     .qs     (ie01_e33_qs)
8124:   );
8125: 
8126: 
8127:   // F[e34]: 2:2
8128:   prim_subreg #(
8129:     .DW      (1),
8130:     .SWACCESS("RW"),
8131:     .RESVAL  (1'h0)
8132:   ) u_ie01_e34 (
8133:     .clk_i   (clk_i    ),
8134:     .rst_ni  (rst_ni  ),
8135: 
8136:     // from register interface
8137:     .we     (ie01_e34_we),
8138:     .wd     (ie01_e34_wd),
8139: 
8140:     // from internal hardware
8141:     .de     (1'b0),
8142:     .d      ('0  ),
8143: 
8144:     // to internal hardware
8145:     .qe     (),
8146:     .q      (reg2hw.ie0[34].q ),
8147: 
8148:     // to register interface (read)
8149:     .qs     (ie01_e34_qs)
8150:   );
8151: 
8152: 
8153:   // F[e35]: 3:3
8154:   prim_subreg #(
8155:     .DW      (1),
8156:     .SWACCESS("RW"),
8157:     .RESVAL  (1'h0)
8158:   ) u_ie01_e35 (
8159:     .clk_i   (clk_i    ),
8160:     .rst_ni  (rst_ni  ),
8161: 
8162:     // from register interface
8163:     .we     (ie01_e35_we),
8164:     .wd     (ie01_e35_wd),
8165: 
8166:     // from internal hardware
8167:     .de     (1'b0),
8168:     .d      ('0  ),
8169: 
8170:     // to internal hardware
8171:     .qe     (),
8172:     .q      (reg2hw.ie0[35].q ),
8173: 
8174:     // to register interface (read)
8175:     .qs     (ie01_e35_qs)
8176:   );
8177: 
8178: 
8179:   // F[e36]: 4:4
8180:   prim_subreg #(
8181:     .DW      (1),
8182:     .SWACCESS("RW"),
8183:     .RESVAL  (1'h0)
8184:   ) u_ie01_e36 (
8185:     .clk_i   (clk_i    ),
8186:     .rst_ni  (rst_ni  ),
8187: 
8188:     // from register interface
8189:     .we     (ie01_e36_we),
8190:     .wd     (ie01_e36_wd),
8191: 
8192:     // from internal hardware
8193:     .de     (1'b0),
8194:     .d      ('0  ),
8195: 
8196:     // to internal hardware
8197:     .qe     (),
8198:     .q      (reg2hw.ie0[36].q ),
8199: 
8200:     // to register interface (read)
8201:     .qs     (ie01_e36_qs)
8202:   );
8203: 
8204: 
8205:   // F[e37]: 5:5
8206:   prim_subreg #(
8207:     .DW      (1),
8208:     .SWACCESS("RW"),
8209:     .RESVAL  (1'h0)
8210:   ) u_ie01_e37 (
8211:     .clk_i   (clk_i    ),
8212:     .rst_ni  (rst_ni  ),
8213: 
8214:     // from register interface
8215:     .we     (ie01_e37_we),
8216:     .wd     (ie01_e37_wd),
8217: 
8218:     // from internal hardware
8219:     .de     (1'b0),
8220:     .d      ('0  ),
8221: 
8222:     // to internal hardware
8223:     .qe     (),
8224:     .q      (reg2hw.ie0[37].q ),
8225: 
8226:     // to register interface (read)
8227:     .qs     (ie01_e37_qs)
8228:   );
8229: 
8230: 
8231:   // F[e38]: 6:6
8232:   prim_subreg #(
8233:     .DW      (1),
8234:     .SWACCESS("RW"),
8235:     .RESVAL  (1'h0)
8236:   ) u_ie01_e38 (
8237:     .clk_i   (clk_i    ),
8238:     .rst_ni  (rst_ni  ),
8239: 
8240:     // from register interface
8241:     .we     (ie01_e38_we),
8242:     .wd     (ie01_e38_wd),
8243: 
8244:     // from internal hardware
8245:     .de     (1'b0),
8246:     .d      ('0  ),
8247: 
8248:     // to internal hardware
8249:     .qe     (),
8250:     .q      (reg2hw.ie0[38].q ),
8251: 
8252:     // to register interface (read)
8253:     .qs     (ie01_e38_qs)
8254:   );
8255: 
8256: 
8257:   // F[e39]: 7:7
8258:   prim_subreg #(
8259:     .DW      (1),
8260:     .SWACCESS("RW"),
8261:     .RESVAL  (1'h0)
8262:   ) u_ie01_e39 (
8263:     .clk_i   (clk_i    ),
8264:     .rst_ni  (rst_ni  ),
8265: 
8266:     // from register interface
8267:     .we     (ie01_e39_we),
8268:     .wd     (ie01_e39_wd),
8269: 
8270:     // from internal hardware
8271:     .de     (1'b0),
8272:     .d      ('0  ),
8273: 
8274:     // to internal hardware
8275:     .qe     (),
8276:     .q      (reg2hw.ie0[39].q ),
8277: 
8278:     // to register interface (read)
8279:     .qs     (ie01_e39_qs)
8280:   );
8281: 
8282: 
8283:   // F[e40]: 8:8
8284:   prim_subreg #(
8285:     .DW      (1),
8286:     .SWACCESS("RW"),
8287:     .RESVAL  (1'h0)
8288:   ) u_ie01_e40 (
8289:     .clk_i   (clk_i    ),
8290:     .rst_ni  (rst_ni  ),
8291: 
8292:     // from register interface
8293:     .we     (ie01_e40_we),
8294:     .wd     (ie01_e40_wd),
8295: 
8296:     // from internal hardware
8297:     .de     (1'b0),
8298:     .d      ('0  ),
8299: 
8300:     // to internal hardware
8301:     .qe     (),
8302:     .q      (reg2hw.ie0[40].q ),
8303: 
8304:     // to register interface (read)
8305:     .qs     (ie01_e40_qs)
8306:   );
8307: 
8308: 
8309:   // F[e41]: 9:9
8310:   prim_subreg #(
8311:     .DW      (1),
8312:     .SWACCESS("RW"),
8313:     .RESVAL  (1'h0)
8314:   ) u_ie01_e41 (
8315:     .clk_i   (clk_i    ),
8316:     .rst_ni  (rst_ni  ),
8317: 
8318:     // from register interface
8319:     .we     (ie01_e41_we),
8320:     .wd     (ie01_e41_wd),
8321: 
8322:     // from internal hardware
8323:     .de     (1'b0),
8324:     .d      ('0  ),
8325: 
8326:     // to internal hardware
8327:     .qe     (),
8328:     .q      (reg2hw.ie0[41].q ),
8329: 
8330:     // to register interface (read)
8331:     .qs     (ie01_e41_qs)
8332:   );
8333: 
8334: 
8335:   // F[e42]: 10:10
8336:   prim_subreg #(
8337:     .DW      (1),
8338:     .SWACCESS("RW"),
8339:     .RESVAL  (1'h0)
8340:   ) u_ie01_e42 (
8341:     .clk_i   (clk_i    ),
8342:     .rst_ni  (rst_ni  ),
8343: 
8344:     // from register interface
8345:     .we     (ie01_e42_we),
8346:     .wd     (ie01_e42_wd),
8347: 
8348:     // from internal hardware
8349:     .de     (1'b0),
8350:     .d      ('0  ),
8351: 
8352:     // to internal hardware
8353:     .qe     (),
8354:     .q      (reg2hw.ie0[42].q ),
8355: 
8356:     // to register interface (read)
8357:     .qs     (ie01_e42_qs)
8358:   );
8359: 
8360: 
8361:   // F[e43]: 11:11
8362:   prim_subreg #(
8363:     .DW      (1),
8364:     .SWACCESS("RW"),
8365:     .RESVAL  (1'h0)
8366:   ) u_ie01_e43 (
8367:     .clk_i   (clk_i    ),
8368:     .rst_ni  (rst_ni  ),
8369: 
8370:     // from register interface
8371:     .we     (ie01_e43_we),
8372:     .wd     (ie01_e43_wd),
8373: 
8374:     // from internal hardware
8375:     .de     (1'b0),
8376:     .d      ('0  ),
8377: 
8378:     // to internal hardware
8379:     .qe     (),
8380:     .q      (reg2hw.ie0[43].q ),
8381: 
8382:     // to register interface (read)
8383:     .qs     (ie01_e43_qs)
8384:   );
8385: 
8386: 
8387:   // F[e44]: 12:12
8388:   prim_subreg #(
8389:     .DW      (1),
8390:     .SWACCESS("RW"),
8391:     .RESVAL  (1'h0)
8392:   ) u_ie01_e44 (
8393:     .clk_i   (clk_i    ),
8394:     .rst_ni  (rst_ni  ),
8395: 
8396:     // from register interface
8397:     .we     (ie01_e44_we),
8398:     .wd     (ie01_e44_wd),
8399: 
8400:     // from internal hardware
8401:     .de     (1'b0),
8402:     .d      ('0  ),
8403: 
8404:     // to internal hardware
8405:     .qe     (),
8406:     .q      (reg2hw.ie0[44].q ),
8407: 
8408:     // to register interface (read)
8409:     .qs     (ie01_e44_qs)
8410:   );
8411: 
8412: 
8413:   // F[e45]: 13:13
8414:   prim_subreg #(
8415:     .DW      (1),
8416:     .SWACCESS("RW"),
8417:     .RESVAL  (1'h0)
8418:   ) u_ie01_e45 (
8419:     .clk_i   (clk_i    ),
8420:     .rst_ni  (rst_ni  ),
8421: 
8422:     // from register interface
8423:     .we     (ie01_e45_we),
8424:     .wd     (ie01_e45_wd),
8425: 
8426:     // from internal hardware
8427:     .de     (1'b0),
8428:     .d      ('0  ),
8429: 
8430:     // to internal hardware
8431:     .qe     (),
8432:     .q      (reg2hw.ie0[45].q ),
8433: 
8434:     // to register interface (read)
8435:     .qs     (ie01_e45_qs)
8436:   );
8437: 
8438: 
8439:   // F[e46]: 14:14
8440:   prim_subreg #(
8441:     .DW      (1),
8442:     .SWACCESS("RW"),
8443:     .RESVAL  (1'h0)
8444:   ) u_ie01_e46 (
8445:     .clk_i   (clk_i    ),
8446:     .rst_ni  (rst_ni  ),
8447: 
8448:     // from register interface
8449:     .we     (ie01_e46_we),
8450:     .wd     (ie01_e46_wd),
8451: 
8452:     // from internal hardware
8453:     .de     (1'b0),
8454:     .d      ('0  ),
8455: 
8456:     // to internal hardware
8457:     .qe     (),
8458:     .q      (reg2hw.ie0[46].q ),
8459: 
8460:     // to register interface (read)
8461:     .qs     (ie01_e46_qs)
8462:   );
8463: 
8464: 
8465:   // F[e47]: 15:15
8466:   prim_subreg #(
8467:     .DW      (1),
8468:     .SWACCESS("RW"),
8469:     .RESVAL  (1'h0)
8470:   ) u_ie01_e47 (
8471:     .clk_i   (clk_i    ),
8472:     .rst_ni  (rst_ni  ),
8473: 
8474:     // from register interface
8475:     .we     (ie01_e47_we),
8476:     .wd     (ie01_e47_wd),
8477: 
8478:     // from internal hardware
8479:     .de     (1'b0),
8480:     .d      ('0  ),
8481: 
8482:     // to internal hardware
8483:     .qe     (),
8484:     .q      (reg2hw.ie0[47].q ),
8485: 
8486:     // to register interface (read)
8487:     .qs     (ie01_e47_qs)
8488:   );
8489: 
8490: 
8491:   // F[e48]: 16:16
8492:   prim_subreg #(
8493:     .DW      (1),
8494:     .SWACCESS("RW"),
8495:     .RESVAL  (1'h0)
8496:   ) u_ie01_e48 (
8497:     .clk_i   (clk_i    ),
8498:     .rst_ni  (rst_ni  ),
8499: 
8500:     // from register interface
8501:     .we     (ie01_e48_we),
8502:     .wd     (ie01_e48_wd),
8503: 
8504:     // from internal hardware
8505:     .de     (1'b0),
8506:     .d      ('0  ),
8507: 
8508:     // to internal hardware
8509:     .qe     (),
8510:     .q      (reg2hw.ie0[48].q ),
8511: 
8512:     // to register interface (read)
8513:     .qs     (ie01_e48_qs)
8514:   );
8515: 
8516: 
8517:   // F[e49]: 17:17
8518:   prim_subreg #(
8519:     .DW      (1),
8520:     .SWACCESS("RW"),
8521:     .RESVAL  (1'h0)
8522:   ) u_ie01_e49 (
8523:     .clk_i   (clk_i    ),
8524:     .rst_ni  (rst_ni  ),
8525: 
8526:     // from register interface
8527:     .we     (ie01_e49_we),
8528:     .wd     (ie01_e49_wd),
8529: 
8530:     // from internal hardware
8531:     .de     (1'b0),
8532:     .d      ('0  ),
8533: 
8534:     // to internal hardware
8535:     .qe     (),
8536:     .q      (reg2hw.ie0[49].q ),
8537: 
8538:     // to register interface (read)
8539:     .qs     (ie01_e49_qs)
8540:   );
8541: 
8542: 
8543:   // F[e50]: 18:18
8544:   prim_subreg #(
8545:     .DW      (1),
8546:     .SWACCESS("RW"),
8547:     .RESVAL  (1'h0)
8548:   ) u_ie01_e50 (
8549:     .clk_i   (clk_i    ),
8550:     .rst_ni  (rst_ni  ),
8551: 
8552:     // from register interface
8553:     .we     (ie01_e50_we),
8554:     .wd     (ie01_e50_wd),
8555: 
8556:     // from internal hardware
8557:     .de     (1'b0),
8558:     .d      ('0  ),
8559: 
8560:     // to internal hardware
8561:     .qe     (),
8562:     .q      (reg2hw.ie0[50].q ),
8563: 
8564:     // to register interface (read)
8565:     .qs     (ie01_e50_qs)
8566:   );
8567: 
8568: 
8569:   // F[e51]: 19:19
8570:   prim_subreg #(
8571:     .DW      (1),
8572:     .SWACCESS("RW"),
8573:     .RESVAL  (1'h0)
8574:   ) u_ie01_e51 (
8575:     .clk_i   (clk_i    ),
8576:     .rst_ni  (rst_ni  ),
8577: 
8578:     // from register interface
8579:     .we     (ie01_e51_we),
8580:     .wd     (ie01_e51_wd),
8581: 
8582:     // from internal hardware
8583:     .de     (1'b0),
8584:     .d      ('0  ),
8585: 
8586:     // to internal hardware
8587:     .qe     (),
8588:     .q      (reg2hw.ie0[51].q ),
8589: 
8590:     // to register interface (read)
8591:     .qs     (ie01_e51_qs)
8592:   );
8593: 
8594: 
8595:   // F[e52]: 20:20
8596:   prim_subreg #(
8597:     .DW      (1),
8598:     .SWACCESS("RW"),
8599:     .RESVAL  (1'h0)
8600:   ) u_ie01_e52 (
8601:     .clk_i   (clk_i    ),
8602:     .rst_ni  (rst_ni  ),
8603: 
8604:     // from register interface
8605:     .we     (ie01_e52_we),
8606:     .wd     (ie01_e52_wd),
8607: 
8608:     // from internal hardware
8609:     .de     (1'b0),
8610:     .d      ('0  ),
8611: 
8612:     // to internal hardware
8613:     .qe     (),
8614:     .q      (reg2hw.ie0[52].q ),
8615: 
8616:     // to register interface (read)
8617:     .qs     (ie01_e52_qs)
8618:   );
8619: 
8620: 
8621:   // F[e53]: 21:21
8622:   prim_subreg #(
8623:     .DW      (1),
8624:     .SWACCESS("RW"),
8625:     .RESVAL  (1'h0)
8626:   ) u_ie01_e53 (
8627:     .clk_i   (clk_i    ),
8628:     .rst_ni  (rst_ni  ),
8629: 
8630:     // from register interface
8631:     .we     (ie01_e53_we),
8632:     .wd     (ie01_e53_wd),
8633: 
8634:     // from internal hardware
8635:     .de     (1'b0),
8636:     .d      ('0  ),
8637: 
8638:     // to internal hardware
8639:     .qe     (),
8640:     .q      (reg2hw.ie0[53].q ),
8641: 
8642:     // to register interface (read)
8643:     .qs     (ie01_e53_qs)
8644:   );
8645: 
8646: 
8647:   // F[e54]: 22:22
8648:   prim_subreg #(
8649:     .DW      (1),
8650:     .SWACCESS("RW"),
8651:     .RESVAL  (1'h0)
8652:   ) u_ie01_e54 (
8653:     .clk_i   (clk_i    ),
8654:     .rst_ni  (rst_ni  ),
8655: 
8656:     // from register interface
8657:     .we     (ie01_e54_we),
8658:     .wd     (ie01_e54_wd),
8659: 
8660:     // from internal hardware
8661:     .de     (1'b0),
8662:     .d      ('0  ),
8663: 
8664:     // to internal hardware
8665:     .qe     (),
8666:     .q      (reg2hw.ie0[54].q ),
8667: 
8668:     // to register interface (read)
8669:     .qs     (ie01_e54_qs)
8670:   );
8671: 
8672: 
8673:   // F[e55]: 23:23
8674:   prim_subreg #(
8675:     .DW      (1),
8676:     .SWACCESS("RW"),
8677:     .RESVAL  (1'h0)
8678:   ) u_ie01_e55 (
8679:     .clk_i   (clk_i    ),
8680:     .rst_ni  (rst_ni  ),
8681: 
8682:     // from register interface
8683:     .we     (ie01_e55_we),
8684:     .wd     (ie01_e55_wd),
8685: 
8686:     // from internal hardware
8687:     .de     (1'b0),
8688:     .d      ('0  ),
8689: 
8690:     // to internal hardware
8691:     .qe     (),
8692:     .q      (reg2hw.ie0[55].q ),
8693: 
8694:     // to register interface (read)
8695:     .qs     (ie01_e55_qs)
8696:   );
8697: 
8698: 
8699:   // F[e56]: 24:24
8700:   prim_subreg #(
8701:     .DW      (1),
8702:     .SWACCESS("RW"),
8703:     .RESVAL  (1'h0)
8704:   ) u_ie01_e56 (
8705:     .clk_i   (clk_i    ),
8706:     .rst_ni  (rst_ni  ),
8707: 
8708:     // from register interface
8709:     .we     (ie01_e56_we),
8710:     .wd     (ie01_e56_wd),
8711: 
8712:     // from internal hardware
8713:     .de     (1'b0),
8714:     .d      ('0  ),
8715: 
8716:     // to internal hardware
8717:     .qe     (),
8718:     .q      (reg2hw.ie0[56].q ),
8719: 
8720:     // to register interface (read)
8721:     .qs     (ie01_e56_qs)
8722:   );
8723: 
8724: 
8725:   // F[e57]: 25:25
8726:   prim_subreg #(
8727:     .DW      (1),
8728:     .SWACCESS("RW"),
8729:     .RESVAL  (1'h0)
8730:   ) u_ie01_e57 (
8731:     .clk_i   (clk_i    ),
8732:     .rst_ni  (rst_ni  ),
8733: 
8734:     // from register interface
8735:     .we     (ie01_e57_we),
8736:     .wd     (ie01_e57_wd),
8737: 
8738:     // from internal hardware
8739:     .de     (1'b0),
8740:     .d      ('0  ),
8741: 
8742:     // to internal hardware
8743:     .qe     (),
8744:     .q      (reg2hw.ie0[57].q ),
8745: 
8746:     // to register interface (read)
8747:     .qs     (ie01_e57_qs)
8748:   );
8749: 
8750: 
8751:   // F[e58]: 26:26
8752:   prim_subreg #(
8753:     .DW      (1),
8754:     .SWACCESS("RW"),
8755:     .RESVAL  (1'h0)
8756:   ) u_ie01_e58 (
8757:     .clk_i   (clk_i    ),
8758:     .rst_ni  (rst_ni  ),
8759: 
8760:     // from register interface
8761:     .we     (ie01_e58_we),
8762:     .wd     (ie01_e58_wd),
8763: 
8764:     // from internal hardware
8765:     .de     (1'b0),
8766:     .d      ('0  ),
8767: 
8768:     // to internal hardware
8769:     .qe     (),
8770:     .q      (reg2hw.ie0[58].q ),
8771: 
8772:     // to register interface (read)
8773:     .qs     (ie01_e58_qs)
8774:   );
8775: 
8776: 
8777:   // F[e59]: 27:27
8778:   prim_subreg #(
8779:     .DW      (1),
8780:     .SWACCESS("RW"),
8781:     .RESVAL  (1'h0)
8782:   ) u_ie01_e59 (
8783:     .clk_i   (clk_i    ),
8784:     .rst_ni  (rst_ni  ),
8785: 
8786:     // from register interface
8787:     .we     (ie01_e59_we),
8788:     .wd     (ie01_e59_wd),
8789: 
8790:     // from internal hardware
8791:     .de     (1'b0),
8792:     .d      ('0  ),
8793: 
8794:     // to internal hardware
8795:     .qe     (),
8796:     .q      (reg2hw.ie0[59].q ),
8797: 
8798:     // to register interface (read)
8799:     .qs     (ie01_e59_qs)
8800:   );
8801: 
8802: 
8803:   // F[e60]: 28:28
8804:   prim_subreg #(
8805:     .DW      (1),
8806:     .SWACCESS("RW"),
8807:     .RESVAL  (1'h0)
8808:   ) u_ie01_e60 (
8809:     .clk_i   (clk_i    ),
8810:     .rst_ni  (rst_ni  ),
8811: 
8812:     // from register interface
8813:     .we     (ie01_e60_we),
8814:     .wd     (ie01_e60_wd),
8815: 
8816:     // from internal hardware
8817:     .de     (1'b0),
8818:     .d      ('0  ),
8819: 
8820:     // to internal hardware
8821:     .qe     (),
8822:     .q      (reg2hw.ie0[60].q ),
8823: 
8824:     // to register interface (read)
8825:     .qs     (ie01_e60_qs)
8826:   );
8827: 
8828: 
8829:   // F[e61]: 29:29
8830:   prim_subreg #(
8831:     .DW      (1),
8832:     .SWACCESS("RW"),
8833:     .RESVAL  (1'h0)
8834:   ) u_ie01_e61 (
8835:     .clk_i   (clk_i    ),
8836:     .rst_ni  (rst_ni  ),
8837: 
8838:     // from register interface
8839:     .we     (ie01_e61_we),
8840:     .wd     (ie01_e61_wd),
8841: 
8842:     // from internal hardware
8843:     .de     (1'b0),
8844:     .d      ('0  ),
8845: 
8846:     // to internal hardware
8847:     .qe     (),
8848:     .q      (reg2hw.ie0[61].q ),
8849: 
8850:     // to register interface (read)
8851:     .qs     (ie01_e61_qs)
8852:   );
8853: 
8854: 
8855:   // F[e62]: 30:30
8856:   prim_subreg #(
8857:     .DW      (1),
8858:     .SWACCESS("RW"),
8859:     .RESVAL  (1'h0)
8860:   ) u_ie01_e62 (
8861:     .clk_i   (clk_i    ),
8862:     .rst_ni  (rst_ni  ),
8863: 
8864:     // from register interface
8865:     .we     (ie01_e62_we),
8866:     .wd     (ie01_e62_wd),
8867: 
8868:     // from internal hardware
8869:     .de     (1'b0),
8870:     .d      ('0  ),
8871: 
8872:     // to internal hardware
8873:     .qe     (),
8874:     .q      (reg2hw.ie0[62].q ),
8875: 
8876:     // to register interface (read)
8877:     .qs     (ie01_e62_qs)
8878:   );
8879: 
8880: 
8881:   // F[e63]: 31:31
8882:   prim_subreg #(
8883:     .DW      (1),
8884:     .SWACCESS("RW"),
8885:     .RESVAL  (1'h0)
8886:   ) u_ie01_e63 (
8887:     .clk_i   (clk_i    ),
8888:     .rst_ni  (rst_ni  ),
8889: 
8890:     // from register interface
8891:     .we     (ie01_e63_we),
8892:     .wd     (ie01_e63_wd),
8893: 
8894:     // from internal hardware
8895:     .de     (1'b0),
8896:     .d      ('0  ),
8897: 
8898:     // to internal hardware
8899:     .qe     (),
8900:     .q      (reg2hw.ie0[63].q ),
8901: 
8902:     // to register interface (read)
8903:     .qs     (ie01_e63_qs)
8904:   );
8905: 
8906: 
8907:   // Subregister 64 of Multireg ie0
8908:   // R[ie02]: V(False)
8909: 
8910:   // F[e64]: 0:0
8911:   prim_subreg #(
8912:     .DW      (1),
8913:     .SWACCESS("RW"),
8914:     .RESVAL  (1'h0)
8915:   ) u_ie02_e64 (
8916:     .clk_i   (clk_i    ),
8917:     .rst_ni  (rst_ni  ),
8918: 
8919:     // from register interface
8920:     .we     (ie02_e64_we),
8921:     .wd     (ie02_e64_wd),
8922: 
8923:     // from internal hardware
8924:     .de     (1'b0),
8925:     .d      ('0  ),
8926: 
8927:     // to internal hardware
8928:     .qe     (),
8929:     .q      (reg2hw.ie0[64].q ),
8930: 
8931:     // to register interface (read)
8932:     .qs     (ie02_e64_qs)
8933:   );
8934: 
8935: 
8936:   // F[e65]: 1:1
8937:   prim_subreg #(
8938:     .DW      (1),
8939:     .SWACCESS("RW"),
8940:     .RESVAL  (1'h0)
8941:   ) u_ie02_e65 (
8942:     .clk_i   (clk_i    ),
8943:     .rst_ni  (rst_ni  ),
8944: 
8945:     // from register interface
8946:     .we     (ie02_e65_we),
8947:     .wd     (ie02_e65_wd),
8948: 
8949:     // from internal hardware
8950:     .de     (1'b0),
8951:     .d      ('0  ),
8952: 
8953:     // to internal hardware
8954:     .qe     (),
8955:     .q      (reg2hw.ie0[65].q ),
8956: 
8957:     // to register interface (read)
8958:     .qs     (ie02_e65_qs)
8959:   );
8960: 
8961: 
8962:   // F[e66]: 2:2
8963:   prim_subreg #(
8964:     .DW      (1),
8965:     .SWACCESS("RW"),
8966:     .RESVAL  (1'h0)
8967:   ) u_ie02_e66 (
8968:     .clk_i   (clk_i    ),
8969:     .rst_ni  (rst_ni  ),
8970: 
8971:     // from register interface
8972:     .we     (ie02_e66_we),
8973:     .wd     (ie02_e66_wd),
8974: 
8975:     // from internal hardware
8976:     .de     (1'b0),
8977:     .d      ('0  ),
8978: 
8979:     // to internal hardware
8980:     .qe     (),
8981:     .q      (reg2hw.ie0[66].q ),
8982: 
8983:     // to register interface (read)
8984:     .qs     (ie02_e66_qs)
8985:   );
8986: 
8987: 
8988:   // F[e67]: 3:3
8989:   prim_subreg #(
8990:     .DW      (1),
8991:     .SWACCESS("RW"),
8992:     .RESVAL  (1'h0)
8993:   ) u_ie02_e67 (
8994:     .clk_i   (clk_i    ),
8995:     .rst_ni  (rst_ni  ),
8996: 
8997:     // from register interface
8998:     .we     (ie02_e67_we),
8999:     .wd     (ie02_e67_wd),
9000: 
9001:     // from internal hardware
9002:     .de     (1'b0),
9003:     .d      ('0  ),
9004: 
9005:     // to internal hardware
9006:     .qe     (),
9007:     .q      (reg2hw.ie0[67].q ),
9008: 
9009:     // to register interface (read)
9010:     .qs     (ie02_e67_qs)
9011:   );
9012: 
9013: 
9014:   // F[e68]: 4:4
9015:   prim_subreg #(
9016:     .DW      (1),
9017:     .SWACCESS("RW"),
9018:     .RESVAL  (1'h0)
9019:   ) u_ie02_e68 (
9020:     .clk_i   (clk_i    ),
9021:     .rst_ni  (rst_ni  ),
9022: 
9023:     // from register interface
9024:     .we     (ie02_e68_we),
9025:     .wd     (ie02_e68_wd),
9026: 
9027:     // from internal hardware
9028:     .de     (1'b0),
9029:     .d      ('0  ),
9030: 
9031:     // to internal hardware
9032:     .qe     (),
9033:     .q      (reg2hw.ie0[68].q ),
9034: 
9035:     // to register interface (read)
9036:     .qs     (ie02_e68_qs)
9037:   );
9038: 
9039: 
9040:   // F[e69]: 5:5
9041:   prim_subreg #(
9042:     .DW      (1),
9043:     .SWACCESS("RW"),
9044:     .RESVAL  (1'h0)
9045:   ) u_ie02_e69 (
9046:     .clk_i   (clk_i    ),
9047:     .rst_ni  (rst_ni  ),
9048: 
9049:     // from register interface
9050:     .we     (ie02_e69_we),
9051:     .wd     (ie02_e69_wd),
9052: 
9053:     // from internal hardware
9054:     .de     (1'b0),
9055:     .d      ('0  ),
9056: 
9057:     // to internal hardware
9058:     .qe     (),
9059:     .q      (reg2hw.ie0[69].q ),
9060: 
9061:     // to register interface (read)
9062:     .qs     (ie02_e69_qs)
9063:   );
9064: 
9065: 
9066:   // F[e70]: 6:6
9067:   prim_subreg #(
9068:     .DW      (1),
9069:     .SWACCESS("RW"),
9070:     .RESVAL  (1'h0)
9071:   ) u_ie02_e70 (
9072:     .clk_i   (clk_i    ),
9073:     .rst_ni  (rst_ni  ),
9074: 
9075:     // from register interface
9076:     .we     (ie02_e70_we),
9077:     .wd     (ie02_e70_wd),
9078: 
9079:     // from internal hardware
9080:     .de     (1'b0),
9081:     .d      ('0  ),
9082: 
9083:     // to internal hardware
9084:     .qe     (),
9085:     .q      (reg2hw.ie0[70].q ),
9086: 
9087:     // to register interface (read)
9088:     .qs     (ie02_e70_qs)
9089:   );
9090: 
9091: 
9092:   // F[e71]: 7:7
9093:   prim_subreg #(
9094:     .DW      (1),
9095:     .SWACCESS("RW"),
9096:     .RESVAL  (1'h0)
9097:   ) u_ie02_e71 (
9098:     .clk_i   (clk_i    ),
9099:     .rst_ni  (rst_ni  ),
9100: 
9101:     // from register interface
9102:     .we     (ie02_e71_we),
9103:     .wd     (ie02_e71_wd),
9104: 
9105:     // from internal hardware
9106:     .de     (1'b0),
9107:     .d      ('0  ),
9108: 
9109:     // to internal hardware
9110:     .qe     (),
9111:     .q      (reg2hw.ie0[71].q ),
9112: 
9113:     // to register interface (read)
9114:     .qs     (ie02_e71_qs)
9115:   );
9116: 
9117: 
9118:   // F[e72]: 8:8
9119:   prim_subreg #(
9120:     .DW      (1),
9121:     .SWACCESS("RW"),
9122:     .RESVAL  (1'h0)
9123:   ) u_ie02_e72 (
9124:     .clk_i   (clk_i    ),
9125:     .rst_ni  (rst_ni  ),
9126: 
9127:     // from register interface
9128:     .we     (ie02_e72_we),
9129:     .wd     (ie02_e72_wd),
9130: 
9131:     // from internal hardware
9132:     .de     (1'b0),
9133:     .d      ('0  ),
9134: 
9135:     // to internal hardware
9136:     .qe     (),
9137:     .q      (reg2hw.ie0[72].q ),
9138: 
9139:     // to register interface (read)
9140:     .qs     (ie02_e72_qs)
9141:   );
9142: 
9143: 
9144:   // F[e73]: 9:9
9145:   prim_subreg #(
9146:     .DW      (1),
9147:     .SWACCESS("RW"),
9148:     .RESVAL  (1'h0)
9149:   ) u_ie02_e73 (
9150:     .clk_i   (clk_i    ),
9151:     .rst_ni  (rst_ni  ),
9152: 
9153:     // from register interface
9154:     .we     (ie02_e73_we),
9155:     .wd     (ie02_e73_wd),
9156: 
9157:     // from internal hardware
9158:     .de     (1'b0),
9159:     .d      ('0  ),
9160: 
9161:     // to internal hardware
9162:     .qe     (),
9163:     .q      (reg2hw.ie0[73].q ),
9164: 
9165:     // to register interface (read)
9166:     .qs     (ie02_e73_qs)
9167:   );
9168: 
9169: 
9170:   // F[e74]: 10:10
9171:   prim_subreg #(
9172:     .DW      (1),
9173:     .SWACCESS("RW"),
9174:     .RESVAL  (1'h0)
9175:   ) u_ie02_e74 (
9176:     .clk_i   (clk_i    ),
9177:     .rst_ni  (rst_ni  ),
9178: 
9179:     // from register interface
9180:     .we     (ie02_e74_we),
9181:     .wd     (ie02_e74_wd),
9182: 
9183:     // from internal hardware
9184:     .de     (1'b0),
9185:     .d      ('0  ),
9186: 
9187:     // to internal hardware
9188:     .qe     (),
9189:     .q      (reg2hw.ie0[74].q ),
9190: 
9191:     // to register interface (read)
9192:     .qs     (ie02_e74_qs)
9193:   );
9194: 
9195: 
9196:   // F[e75]: 11:11
9197:   prim_subreg #(
9198:     .DW      (1),
9199:     .SWACCESS("RW"),
9200:     .RESVAL  (1'h0)
9201:   ) u_ie02_e75 (
9202:     .clk_i   (clk_i    ),
9203:     .rst_ni  (rst_ni  ),
9204: 
9205:     // from register interface
9206:     .we     (ie02_e75_we),
9207:     .wd     (ie02_e75_wd),
9208: 
9209:     // from internal hardware
9210:     .de     (1'b0),
9211:     .d      ('0  ),
9212: 
9213:     // to internal hardware
9214:     .qe     (),
9215:     .q      (reg2hw.ie0[75].q ),
9216: 
9217:     // to register interface (read)
9218:     .qs     (ie02_e75_qs)
9219:   );
9220: 
9221: 
9222:   // F[e76]: 12:12
9223:   prim_subreg #(
9224:     .DW      (1),
9225:     .SWACCESS("RW"),
9226:     .RESVAL  (1'h0)
9227:   ) u_ie02_e76 (
9228:     .clk_i   (clk_i    ),
9229:     .rst_ni  (rst_ni  ),
9230: 
9231:     // from register interface
9232:     .we     (ie02_e76_we),
9233:     .wd     (ie02_e76_wd),
9234: 
9235:     // from internal hardware
9236:     .de     (1'b0),
9237:     .d      ('0  ),
9238: 
9239:     // to internal hardware
9240:     .qe     (),
9241:     .q      (reg2hw.ie0[76].q ),
9242: 
9243:     // to register interface (read)
9244:     .qs     (ie02_e76_qs)
9245:   );
9246: 
9247: 
9248:   // F[e77]: 13:13
9249:   prim_subreg #(
9250:     .DW      (1),
9251:     .SWACCESS("RW"),
9252:     .RESVAL  (1'h0)
9253:   ) u_ie02_e77 (
9254:     .clk_i   (clk_i    ),
9255:     .rst_ni  (rst_ni  ),
9256: 
9257:     // from register interface
9258:     .we     (ie02_e77_we),
9259:     .wd     (ie02_e77_wd),
9260: 
9261:     // from internal hardware
9262:     .de     (1'b0),
9263:     .d      ('0  ),
9264: 
9265:     // to internal hardware
9266:     .qe     (),
9267:     .q      (reg2hw.ie0[77].q ),
9268: 
9269:     // to register interface (read)
9270:     .qs     (ie02_e77_qs)
9271:   );
9272: 
9273: 
9274:   // F[e78]: 14:14
9275:   prim_subreg #(
9276:     .DW      (1),
9277:     .SWACCESS("RW"),
9278:     .RESVAL  (1'h0)
9279:   ) u_ie02_e78 (
9280:     .clk_i   (clk_i    ),
9281:     .rst_ni  (rst_ni  ),
9282: 
9283:     // from register interface
9284:     .we     (ie02_e78_we),
9285:     .wd     (ie02_e78_wd),
9286: 
9287:     // from internal hardware
9288:     .de     (1'b0),
9289:     .d      ('0  ),
9290: 
9291:     // to internal hardware
9292:     .qe     (),
9293:     .q      (reg2hw.ie0[78].q ),
9294: 
9295:     // to register interface (read)
9296:     .qs     (ie02_e78_qs)
9297:   );
9298: 
9299: 
9300:   // F[e79]: 15:15
9301:   prim_subreg #(
9302:     .DW      (1),
9303:     .SWACCESS("RW"),
9304:     .RESVAL  (1'h0)
9305:   ) u_ie02_e79 (
9306:     .clk_i   (clk_i    ),
9307:     .rst_ni  (rst_ni  ),
9308: 
9309:     // from register interface
9310:     .we     (ie02_e79_we),
9311:     .wd     (ie02_e79_wd),
9312: 
9313:     // from internal hardware
9314:     .de     (1'b0),
9315:     .d      ('0  ),
9316: 
9317:     // to internal hardware
9318:     .qe     (),
9319:     .q      (reg2hw.ie0[79].q ),
9320: 
9321:     // to register interface (read)
9322:     .qs     (ie02_e79_qs)
9323:   );
9324: 
9325: 
9326:   // F[e80]: 16:16
9327:   prim_subreg #(
9328:     .DW      (1),
9329:     .SWACCESS("RW"),
9330:     .RESVAL  (1'h0)
9331:   ) u_ie02_e80 (
9332:     .clk_i   (clk_i    ),
9333:     .rst_ni  (rst_ni  ),
9334: 
9335:     // from register interface
9336:     .we     (ie02_e80_we),
9337:     .wd     (ie02_e80_wd),
9338: 
9339:     // from internal hardware
9340:     .de     (1'b0),
9341:     .d      ('0  ),
9342: 
9343:     // to internal hardware
9344:     .qe     (),
9345:     .q      (reg2hw.ie0[80].q ),
9346: 
9347:     // to register interface (read)
9348:     .qs     (ie02_e80_qs)
9349:   );
9350: 
9351: 
9352: 
9353:   // R[threshold0]: V(False)
9354: 
9355:   prim_subreg #(
9356:     .DW      (2),
9357:     .SWACCESS("RW"),
9358:     .RESVAL  (2'h0)
9359:   ) u_threshold0 (
9360:     .clk_i   (clk_i    ),
9361:     .rst_ni  (rst_ni  ),
9362: 
9363:     // from register interface
9364:     .we     (threshold0_we),
9365:     .wd     (threshold0_wd),
9366: 
9367:     // from internal hardware
9368:     .de     (1'b0),
9369:     .d      ('0  ),
9370: 
9371:     // to internal hardware
9372:     .qe     (),
9373:     .q      (reg2hw.threshold0.q ),
9374: 
9375:     // to register interface (read)
9376:     .qs     (threshold0_qs)
9377:   );
9378: 
9379: 
9380:   // R[cc0]: V(True)
9381: 
9382:   prim_subreg_ext #(
9383:     .DW    (7)
9384:   ) u_cc0 (
9385:     .re     (cc0_re),
9386:     .we     (cc0_we),
9387:     .wd     (cc0_wd),
9388:     .d      (hw2reg.cc0.d),
9389:     .qre    (reg2hw.cc0.re),
9390:     .qe     (reg2hw.cc0.qe),
9391:     .q      (reg2hw.cc0.q ),
9392:     .qs     (cc0_qs)
9393:   );
9394: 
9395: 
9396:   // R[msip0]: V(False)
9397: 
9398:   prim_subreg #(
9399:     .DW      (1),
9400:     .SWACCESS("RW"),
9401:     .RESVAL  (1'h0)
9402:   ) u_msip0 (
9403:     .clk_i   (clk_i    ),
9404:     .rst_ni  (rst_ni  ),
9405: 
9406:     // from register interface
9407:     .we     (msip0_we),
9408:     .wd     (msip0_wd),
9409: 
9410:     // from internal hardware
9411:     .de     (1'b0),
9412:     .d      ('0  ),
9413: 
9414:     // to internal hardware
9415:     .qe     (),
9416:     .q      (reg2hw.msip0.q ),
9417: 
9418:     // to register interface (read)
9419:     .qs     (msip0_qs)
9420:   );
9421: 
9422: 
9423: 
9424: 
9425:   logic [92:0] addr_hit;
9426:   always_comb begin
9427:     addr_hit = '0;
9428:     addr_hit[ 0] = (reg_addr == RV_PLIC_IP0_OFFSET);
9429:     addr_hit[ 1] = (reg_addr == RV_PLIC_IP1_OFFSET);
9430:     addr_hit[ 2] = (reg_addr == RV_PLIC_IP2_OFFSET);
9431:     addr_hit[ 3] = (reg_addr == RV_PLIC_LE0_OFFSET);
9432:     addr_hit[ 4] = (reg_addr == RV_PLIC_LE1_OFFSET);
9433:     addr_hit[ 5] = (reg_addr == RV_PLIC_LE2_OFFSET);
9434:     addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
9435:     addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
9436:     addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
9437:     addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
9438:     addr_hit[10] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
9439:     addr_hit[11] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
9440:     addr_hit[12] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
9441:     addr_hit[13] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
9442:     addr_hit[14] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
9443:     addr_hit[15] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
9444:     addr_hit[16] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
9445:     addr_hit[17] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
9446:     addr_hit[18] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
9447:     addr_hit[19] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
9448:     addr_hit[20] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
9449:     addr_hit[21] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
9450:     addr_hit[22] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
9451:     addr_hit[23] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
9452:     addr_hit[24] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
9453:     addr_hit[25] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
9454:     addr_hit[26] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
9455:     addr_hit[27] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
9456:     addr_hit[28] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
9457:     addr_hit[29] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
9458:     addr_hit[30] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
9459:     addr_hit[31] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
9460:     addr_hit[32] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
9461:     addr_hit[33] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
9462:     addr_hit[34] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
9463:     addr_hit[35] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
9464:     addr_hit[36] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
9465:     addr_hit[37] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
9466:     addr_hit[38] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
9467:     addr_hit[39] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
9468:     addr_hit[40] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
9469:     addr_hit[41] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
9470:     addr_hit[42] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
9471:     addr_hit[43] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
9472:     addr_hit[44] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
9473:     addr_hit[45] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
9474:     addr_hit[46] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
9475:     addr_hit[47] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
9476:     addr_hit[48] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
9477:     addr_hit[49] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
9478:     addr_hit[50] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
9479:     addr_hit[51] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
9480:     addr_hit[52] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
9481:     addr_hit[53] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
9482:     addr_hit[54] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
9483:     addr_hit[55] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
9484:     addr_hit[56] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
9485:     addr_hit[57] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
9486:     addr_hit[58] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
9487:     addr_hit[59] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
9488:     addr_hit[60] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
9489:     addr_hit[61] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
9490:     addr_hit[62] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
9491:     addr_hit[63] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
9492:     addr_hit[64] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
9493:     addr_hit[65] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
9494:     addr_hit[66] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
9495:     addr_hit[67] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
9496:     addr_hit[68] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
9497:     addr_hit[69] = (reg_addr == RV_PLIC_PRIO63_OFFSET);
9498:     addr_hit[70] = (reg_addr == RV_PLIC_PRIO64_OFFSET);
9499:     addr_hit[71] = (reg_addr == RV_PLIC_PRIO65_OFFSET);
9500:     addr_hit[72] = (reg_addr == RV_PLIC_PRIO66_OFFSET);
9501:     addr_hit[73] = (reg_addr == RV_PLIC_PRIO67_OFFSET);
9502:     addr_hit[74] = (reg_addr == RV_PLIC_PRIO68_OFFSET);
9503:     addr_hit[75] = (reg_addr == RV_PLIC_PRIO69_OFFSET);
9504:     addr_hit[76] = (reg_addr == RV_PLIC_PRIO70_OFFSET);
9505:     addr_hit[77] = (reg_addr == RV_PLIC_PRIO71_OFFSET);
9506:     addr_hit[78] = (reg_addr == RV_PLIC_PRIO72_OFFSET);
9507:     addr_hit[79] = (reg_addr == RV_PLIC_PRIO73_OFFSET);
9508:     addr_hit[80] = (reg_addr == RV_PLIC_PRIO74_OFFSET);
9509:     addr_hit[81] = (reg_addr == RV_PLIC_PRIO75_OFFSET);
9510:     addr_hit[82] = (reg_addr == RV_PLIC_PRIO76_OFFSET);
9511:     addr_hit[83] = (reg_addr == RV_PLIC_PRIO77_OFFSET);
9512:     addr_hit[84] = (reg_addr == RV_PLIC_PRIO78_OFFSET);
9513:     addr_hit[85] = (reg_addr == RV_PLIC_PRIO79_OFFSET);
9514:     addr_hit[86] = (reg_addr == RV_PLIC_PRIO80_OFFSET);
9515:     addr_hit[87] = (reg_addr == RV_PLIC_IE00_OFFSET);
9516:     addr_hit[88] = (reg_addr == RV_PLIC_IE01_OFFSET);
9517:     addr_hit[89] = (reg_addr == RV_PLIC_IE02_OFFSET);
9518:     addr_hit[90] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
9519:     addr_hit[91] = (reg_addr == RV_PLIC_CC0_OFFSET);
9520:     addr_hit[92] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
9521:   end
9522: 
9523:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
9524: 
9525:   // Check sub-word write is permitted
9526:   always_comb begin
9527:     wr_err = 1'b0;
9528:     if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
9529:     if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
9530:     if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
9531:     if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
9532:     if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
9533:     if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
9534:     if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
9535:     if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
9536:     if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
9537:     if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
9538:     if (addr_hit[10] && reg_we && (RV_PLIC_PERMIT[10] != (RV_PLIC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
9539:     if (addr_hit[11] && reg_we && (RV_PLIC_PERMIT[11] != (RV_PLIC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
9540:     if (addr_hit[12] && reg_we && (RV_PLIC_PERMIT[12] != (RV_PLIC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
9541:     if (addr_hit[13] && reg_we && (RV_PLIC_PERMIT[13] != (RV_PLIC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
9542:     if (addr_hit[14] && reg_we && (RV_PLIC_PERMIT[14] != (RV_PLIC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
9543:     if (addr_hit[15] && reg_we && (RV_PLIC_PERMIT[15] != (RV_PLIC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
9544:     if (addr_hit[16] && reg_we && (RV_PLIC_PERMIT[16] != (RV_PLIC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
9545:     if (addr_hit[17] && reg_we && (RV_PLIC_PERMIT[17] != (RV_PLIC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
9546:     if (addr_hit[18] && reg_we && (RV_PLIC_PERMIT[18] != (RV_PLIC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
9547:     if (addr_hit[19] && reg_we && (RV_PLIC_PERMIT[19] != (RV_PLIC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
9548:     if (addr_hit[20] && reg_we && (RV_PLIC_PERMIT[20] != (RV_PLIC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
9549:     if (addr_hit[21] && reg_we && (RV_PLIC_PERMIT[21] != (RV_PLIC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
9550:     if (addr_hit[22] && reg_we && (RV_PLIC_PERMIT[22] != (RV_PLIC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
9551:     if (addr_hit[23] && reg_we && (RV_PLIC_PERMIT[23] != (RV_PLIC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
9552:     if (addr_hit[24] && reg_we && (RV_PLIC_PERMIT[24] != (RV_PLIC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
9553:     if (addr_hit[25] && reg_we && (RV_PLIC_PERMIT[25] != (RV_PLIC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
9554:     if (addr_hit[26] && reg_we && (RV_PLIC_PERMIT[26] != (RV_PLIC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
9555:     if (addr_hit[27] && reg_we && (RV_PLIC_PERMIT[27] != (RV_PLIC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
9556:     if (addr_hit[28] && reg_we && (RV_PLIC_PERMIT[28] != (RV_PLIC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
9557:     if (addr_hit[29] && reg_we && (RV_PLIC_PERMIT[29] != (RV_PLIC_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
9558:     if (addr_hit[30] && reg_we && (RV_PLIC_PERMIT[30] != (RV_PLIC_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
9559:     if (addr_hit[31] && reg_we && (RV_PLIC_PERMIT[31] != (RV_PLIC_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
9560:     if (addr_hit[32] && reg_we && (RV_PLIC_PERMIT[32] != (RV_PLIC_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
9561:     if (addr_hit[33] && reg_we && (RV_PLIC_PERMIT[33] != (RV_PLIC_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
9562:     if (addr_hit[34] && reg_we && (RV_PLIC_PERMIT[34] != (RV_PLIC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
9563:     if (addr_hit[35] && reg_we && (RV_PLIC_PERMIT[35] != (RV_PLIC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
9564:     if (addr_hit[36] && reg_we && (RV_PLIC_PERMIT[36] != (RV_PLIC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
9565:     if (addr_hit[37] && reg_we && (RV_PLIC_PERMIT[37] != (RV_PLIC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
9566:     if (addr_hit[38] && reg_we && (RV_PLIC_PERMIT[38] != (RV_PLIC_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
9567:     if (addr_hit[39] && reg_we && (RV_PLIC_PERMIT[39] != (RV_PLIC_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
9568:     if (addr_hit[40] && reg_we && (RV_PLIC_PERMIT[40] != (RV_PLIC_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
9569:     if (addr_hit[41] && reg_we && (RV_PLIC_PERMIT[41] != (RV_PLIC_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
9570:     if (addr_hit[42] && reg_we && (RV_PLIC_PERMIT[42] != (RV_PLIC_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
9571:     if (addr_hit[43] && reg_we && (RV_PLIC_PERMIT[43] != (RV_PLIC_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
9572:     if (addr_hit[44] && reg_we && (RV_PLIC_PERMIT[44] != (RV_PLIC_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
9573:     if (addr_hit[45] && reg_we && (RV_PLIC_PERMIT[45] != (RV_PLIC_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
9574:     if (addr_hit[46] && reg_we && (RV_PLIC_PERMIT[46] != (RV_PLIC_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
9575:     if (addr_hit[47] && reg_we && (RV_PLIC_PERMIT[47] != (RV_PLIC_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
9576:     if (addr_hit[48] && reg_we && (RV_PLIC_PERMIT[48] != (RV_PLIC_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
9577:     if (addr_hit[49] && reg_we && (RV_PLIC_PERMIT[49] != (RV_PLIC_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
9578:     if (addr_hit[50] && reg_we && (RV_PLIC_PERMIT[50] != (RV_PLIC_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
9579:     if (addr_hit[51] && reg_we && (RV_PLIC_PERMIT[51] != (RV_PLIC_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
9580:     if (addr_hit[52] && reg_we && (RV_PLIC_PERMIT[52] != (RV_PLIC_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
9581:     if (addr_hit[53] && reg_we && (RV_PLIC_PERMIT[53] != (RV_PLIC_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
9582:     if (addr_hit[54] && reg_we && (RV_PLIC_PERMIT[54] != (RV_PLIC_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
9583:     if (addr_hit[55] && reg_we && (RV_PLIC_PERMIT[55] != (RV_PLIC_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
9584:     if (addr_hit[56] && reg_we && (RV_PLIC_PERMIT[56] != (RV_PLIC_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
9585:     if (addr_hit[57] && reg_we && (RV_PLIC_PERMIT[57] != (RV_PLIC_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
9586:     if (addr_hit[58] && reg_we && (RV_PLIC_PERMIT[58] != (RV_PLIC_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
9587:     if (addr_hit[59] && reg_we && (RV_PLIC_PERMIT[59] != (RV_PLIC_PERMIT[59] & reg_be))) wr_err = 1'b1 ;
9588:     if (addr_hit[60] && reg_we && (RV_PLIC_PERMIT[60] != (RV_PLIC_PERMIT[60] & reg_be))) wr_err = 1'b1 ;
9589:     if (addr_hit[61] && reg_we && (RV_PLIC_PERMIT[61] != (RV_PLIC_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
9590:     if (addr_hit[62] && reg_we && (RV_PLIC_PERMIT[62] != (RV_PLIC_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
9591:     if (addr_hit[63] && reg_we && (RV_PLIC_PERMIT[63] != (RV_PLIC_PERMIT[63] & reg_be))) wr_err = 1'b1 ;
9592:     if (addr_hit[64] && reg_we && (RV_PLIC_PERMIT[64] != (RV_PLIC_PERMIT[64] & reg_be))) wr_err = 1'b1 ;
9593:     if (addr_hit[65] && reg_we && (RV_PLIC_PERMIT[65] != (RV_PLIC_PERMIT[65] & reg_be))) wr_err = 1'b1 ;
9594:     if (addr_hit[66] && reg_we && (RV_PLIC_PERMIT[66] != (RV_PLIC_PERMIT[66] & reg_be))) wr_err = 1'b1 ;
9595:     if (addr_hit[67] && reg_we && (RV_PLIC_PERMIT[67] != (RV_PLIC_PERMIT[67] & reg_be))) wr_err = 1'b1 ;
9596:     if (addr_hit[68] && reg_we && (RV_PLIC_PERMIT[68] != (RV_PLIC_PERMIT[68] & reg_be))) wr_err = 1'b1 ;
9597:     if (addr_hit[69] && reg_we && (RV_PLIC_PERMIT[69] != (RV_PLIC_PERMIT[69] & reg_be))) wr_err = 1'b1 ;
9598:     if (addr_hit[70] && reg_we && (RV_PLIC_PERMIT[70] != (RV_PLIC_PERMIT[70] & reg_be))) wr_err = 1'b1 ;
9599:     if (addr_hit[71] && reg_we && (RV_PLIC_PERMIT[71] != (RV_PLIC_PERMIT[71] & reg_be))) wr_err = 1'b1 ;
9600:     if (addr_hit[72] && reg_we && (RV_PLIC_PERMIT[72] != (RV_PLIC_PERMIT[72] & reg_be))) wr_err = 1'b1 ;
9601:     if (addr_hit[73] && reg_we && (RV_PLIC_PERMIT[73] != (RV_PLIC_PERMIT[73] & reg_be))) wr_err = 1'b1 ;
9602:     if (addr_hit[74] && reg_we && (RV_PLIC_PERMIT[74] != (RV_PLIC_PERMIT[74] & reg_be))) wr_err = 1'b1 ;
9603:     if (addr_hit[75] && reg_we && (RV_PLIC_PERMIT[75] != (RV_PLIC_PERMIT[75] & reg_be))) wr_err = 1'b1 ;
9604:     if (addr_hit[76] && reg_we && (RV_PLIC_PERMIT[76] != (RV_PLIC_PERMIT[76] & reg_be))) wr_err = 1'b1 ;
9605:     if (addr_hit[77] && reg_we && (RV_PLIC_PERMIT[77] != (RV_PLIC_PERMIT[77] & reg_be))) wr_err = 1'b1 ;
9606:     if (addr_hit[78] && reg_we && (RV_PLIC_PERMIT[78] != (RV_PLIC_PERMIT[78] & reg_be))) wr_err = 1'b1 ;
9607:     if (addr_hit[79] && reg_we && (RV_PLIC_PERMIT[79] != (RV_PLIC_PERMIT[79] & reg_be))) wr_err = 1'b1 ;
9608:     if (addr_hit[80] && reg_we && (RV_PLIC_PERMIT[80] != (RV_PLIC_PERMIT[80] & reg_be))) wr_err = 1'b1 ;
9609:     if (addr_hit[81] && reg_we && (RV_PLIC_PERMIT[81] != (RV_PLIC_PERMIT[81] & reg_be))) wr_err = 1'b1 ;
9610:     if (addr_hit[82] && reg_we && (RV_PLIC_PERMIT[82] != (RV_PLIC_PERMIT[82] & reg_be))) wr_err = 1'b1 ;
9611:     if (addr_hit[83] && reg_we && (RV_PLIC_PERMIT[83] != (RV_PLIC_PERMIT[83] & reg_be))) wr_err = 1'b1 ;
9612:     if (addr_hit[84] && reg_we && (RV_PLIC_PERMIT[84] != (RV_PLIC_PERMIT[84] & reg_be))) wr_err = 1'b1 ;
9613:     if (addr_hit[85] && reg_we && (RV_PLIC_PERMIT[85] != (RV_PLIC_PERMIT[85] & reg_be))) wr_err = 1'b1 ;
9614:     if (addr_hit[86] && reg_we && (RV_PLIC_PERMIT[86] != (RV_PLIC_PERMIT[86] & reg_be))) wr_err = 1'b1 ;
9615:     if (addr_hit[87] && reg_we && (RV_PLIC_PERMIT[87] != (RV_PLIC_PERMIT[87] & reg_be))) wr_err = 1'b1 ;
9616:     if (addr_hit[88] && reg_we && (RV_PLIC_PERMIT[88] != (RV_PLIC_PERMIT[88] & reg_be))) wr_err = 1'b1 ;
9617:     if (addr_hit[89] && reg_we && (RV_PLIC_PERMIT[89] != (RV_PLIC_PERMIT[89] & reg_be))) wr_err = 1'b1 ;
9618:     if (addr_hit[90] && reg_we && (RV_PLIC_PERMIT[90] != (RV_PLIC_PERMIT[90] & reg_be))) wr_err = 1'b1 ;
9619:     if (addr_hit[91] && reg_we && (RV_PLIC_PERMIT[91] != (RV_PLIC_PERMIT[91] & reg_be))) wr_err = 1'b1 ;
9620:     if (addr_hit[92] && reg_we && (RV_PLIC_PERMIT[92] != (RV_PLIC_PERMIT[92] & reg_be))) wr_err = 1'b1 ;
9621:   end
9622: 
9623: 
9624: 
9625: 
9626: 
9627: 
9628: 
9629: 
9630: 
9631: 
9632: 
9633: 
9634: 
9635: 
9636: 
9637: 
9638: 
9639: 
9640: 
9641: 
9642: 
9643: 
9644: 
9645: 
9646: 
9647: 
9648: 
9649: 
9650: 
9651: 
9652: 
9653: 
9654: 
9655: 
9656: 
9657: 
9658: 
9659: 
9660: 
9661: 
9662: 
9663: 
9664: 
9665: 
9666: 
9667: 
9668: 
9669: 
9670: 
9671: 
9672: 
9673: 
9674: 
9675: 
9676: 
9677: 
9678: 
9679: 
9680: 
9681: 
9682: 
9683: 
9684: 
9685: 
9686: 
9687: 
9688: 
9689: 
9690: 
9691: 
9692: 
9693: 
9694: 
9695: 
9696: 
9697: 
9698: 
9699: 
9700: 
9701: 
9702: 
9703: 
9704:   assign le0_le0_we = addr_hit[3] & reg_we & ~wr_err;
9705:   assign le0_le0_wd = reg_wdata[0];
9706: 
9707:   assign le0_le1_we = addr_hit[3] & reg_we & ~wr_err;
9708:   assign le0_le1_wd = reg_wdata[1];
9709: 
9710:   assign le0_le2_we = addr_hit[3] & reg_we & ~wr_err;
9711:   assign le0_le2_wd = reg_wdata[2];
9712: 
9713:   assign le0_le3_we = addr_hit[3] & reg_we & ~wr_err;
9714:   assign le0_le3_wd = reg_wdata[3];
9715: 
9716:   assign le0_le4_we = addr_hit[3] & reg_we & ~wr_err;
9717:   assign le0_le4_wd = reg_wdata[4];
9718: 
9719:   assign le0_le5_we = addr_hit[3] & reg_we & ~wr_err;
9720:   assign le0_le5_wd = reg_wdata[5];
9721: 
9722:   assign le0_le6_we = addr_hit[3] & reg_we & ~wr_err;
9723:   assign le0_le6_wd = reg_wdata[6];
9724: 
9725:   assign le0_le7_we = addr_hit[3] & reg_we & ~wr_err;
9726:   assign le0_le7_wd = reg_wdata[7];
9727: 
9728:   assign le0_le8_we = addr_hit[3] & reg_we & ~wr_err;
9729:   assign le0_le8_wd = reg_wdata[8];
9730: 
9731:   assign le0_le9_we = addr_hit[3] & reg_we & ~wr_err;
9732:   assign le0_le9_wd = reg_wdata[9];
9733: 
9734:   assign le0_le10_we = addr_hit[3] & reg_we & ~wr_err;
9735:   assign le0_le10_wd = reg_wdata[10];
9736: 
9737:   assign le0_le11_we = addr_hit[3] & reg_we & ~wr_err;
9738:   assign le0_le11_wd = reg_wdata[11];
9739: 
9740:   assign le0_le12_we = addr_hit[3] & reg_we & ~wr_err;
9741:   assign le0_le12_wd = reg_wdata[12];
9742: 
9743:   assign le0_le13_we = addr_hit[3] & reg_we & ~wr_err;
9744:   assign le0_le13_wd = reg_wdata[13];
9745: 
9746:   assign le0_le14_we = addr_hit[3] & reg_we & ~wr_err;
9747:   assign le0_le14_wd = reg_wdata[14];
9748: 
9749:   assign le0_le15_we = addr_hit[3] & reg_we & ~wr_err;
9750:   assign le0_le15_wd = reg_wdata[15];
9751: 
9752:   assign le0_le16_we = addr_hit[3] & reg_we & ~wr_err;
9753:   assign le0_le16_wd = reg_wdata[16];
9754: 
9755:   assign le0_le17_we = addr_hit[3] & reg_we & ~wr_err;
9756:   assign le0_le17_wd = reg_wdata[17];
9757: 
9758:   assign le0_le18_we = addr_hit[3] & reg_we & ~wr_err;
9759:   assign le0_le18_wd = reg_wdata[18];
9760: 
9761:   assign le0_le19_we = addr_hit[3] & reg_we & ~wr_err;
9762:   assign le0_le19_wd = reg_wdata[19];
9763: 
9764:   assign le0_le20_we = addr_hit[3] & reg_we & ~wr_err;
9765:   assign le0_le20_wd = reg_wdata[20];
9766: 
9767:   assign le0_le21_we = addr_hit[3] & reg_we & ~wr_err;
9768:   assign le0_le21_wd = reg_wdata[21];
9769: 
9770:   assign le0_le22_we = addr_hit[3] & reg_we & ~wr_err;
9771:   assign le0_le22_wd = reg_wdata[22];
9772: 
9773:   assign le0_le23_we = addr_hit[3] & reg_we & ~wr_err;
9774:   assign le0_le23_wd = reg_wdata[23];
9775: 
9776:   assign le0_le24_we = addr_hit[3] & reg_we & ~wr_err;
9777:   assign le0_le24_wd = reg_wdata[24];
9778: 
9779:   assign le0_le25_we = addr_hit[3] & reg_we & ~wr_err;
9780:   assign le0_le25_wd = reg_wdata[25];
9781: 
9782:   assign le0_le26_we = addr_hit[3] & reg_we & ~wr_err;
9783:   assign le0_le26_wd = reg_wdata[26];
9784: 
9785:   assign le0_le27_we = addr_hit[3] & reg_we & ~wr_err;
9786:   assign le0_le27_wd = reg_wdata[27];
9787: 
9788:   assign le0_le28_we = addr_hit[3] & reg_we & ~wr_err;
9789:   assign le0_le28_wd = reg_wdata[28];
9790: 
9791:   assign le0_le29_we = addr_hit[3] & reg_we & ~wr_err;
9792:   assign le0_le29_wd = reg_wdata[29];
9793: 
9794:   assign le0_le30_we = addr_hit[3] & reg_we & ~wr_err;
9795:   assign le0_le30_wd = reg_wdata[30];
9796: 
9797:   assign le0_le31_we = addr_hit[3] & reg_we & ~wr_err;
9798:   assign le0_le31_wd = reg_wdata[31];
9799: 
9800:   assign le1_le32_we = addr_hit[4] & reg_we & ~wr_err;
9801:   assign le1_le32_wd = reg_wdata[0];
9802: 
9803:   assign le1_le33_we = addr_hit[4] & reg_we & ~wr_err;
9804:   assign le1_le33_wd = reg_wdata[1];
9805: 
9806:   assign le1_le34_we = addr_hit[4] & reg_we & ~wr_err;
9807:   assign le1_le34_wd = reg_wdata[2];
9808: 
9809:   assign le1_le35_we = addr_hit[4] & reg_we & ~wr_err;
9810:   assign le1_le35_wd = reg_wdata[3];
9811: 
9812:   assign le1_le36_we = addr_hit[4] & reg_we & ~wr_err;
9813:   assign le1_le36_wd = reg_wdata[4];
9814: 
9815:   assign le1_le37_we = addr_hit[4] & reg_we & ~wr_err;
9816:   assign le1_le37_wd = reg_wdata[5];
9817: 
9818:   assign le1_le38_we = addr_hit[4] & reg_we & ~wr_err;
9819:   assign le1_le38_wd = reg_wdata[6];
9820: 
9821:   assign le1_le39_we = addr_hit[4] & reg_we & ~wr_err;
9822:   assign le1_le39_wd = reg_wdata[7];
9823: 
9824:   assign le1_le40_we = addr_hit[4] & reg_we & ~wr_err;
9825:   assign le1_le40_wd = reg_wdata[8];
9826: 
9827:   assign le1_le41_we = addr_hit[4] & reg_we & ~wr_err;
9828:   assign le1_le41_wd = reg_wdata[9];
9829: 
9830:   assign le1_le42_we = addr_hit[4] & reg_we & ~wr_err;
9831:   assign le1_le42_wd = reg_wdata[10];
9832: 
9833:   assign le1_le43_we = addr_hit[4] & reg_we & ~wr_err;
9834:   assign le1_le43_wd = reg_wdata[11];
9835: 
9836:   assign le1_le44_we = addr_hit[4] & reg_we & ~wr_err;
9837:   assign le1_le44_wd = reg_wdata[12];
9838: 
9839:   assign le1_le45_we = addr_hit[4] & reg_we & ~wr_err;
9840:   assign le1_le45_wd = reg_wdata[13];
9841: 
9842:   assign le1_le46_we = addr_hit[4] & reg_we & ~wr_err;
9843:   assign le1_le46_wd = reg_wdata[14];
9844: 
9845:   assign le1_le47_we = addr_hit[4] & reg_we & ~wr_err;
9846:   assign le1_le47_wd = reg_wdata[15];
9847: 
9848:   assign le1_le48_we = addr_hit[4] & reg_we & ~wr_err;
9849:   assign le1_le48_wd = reg_wdata[16];
9850: 
9851:   assign le1_le49_we = addr_hit[4] & reg_we & ~wr_err;
9852:   assign le1_le49_wd = reg_wdata[17];
9853: 
9854:   assign le1_le50_we = addr_hit[4] & reg_we & ~wr_err;
9855:   assign le1_le50_wd = reg_wdata[18];
9856: 
9857:   assign le1_le51_we = addr_hit[4] & reg_we & ~wr_err;
9858:   assign le1_le51_wd = reg_wdata[19];
9859: 
9860:   assign le1_le52_we = addr_hit[4] & reg_we & ~wr_err;
9861:   assign le1_le52_wd = reg_wdata[20];
9862: 
9863:   assign le1_le53_we = addr_hit[4] & reg_we & ~wr_err;
9864:   assign le1_le53_wd = reg_wdata[21];
9865: 
9866:   assign le1_le54_we = addr_hit[4] & reg_we & ~wr_err;
9867:   assign le1_le54_wd = reg_wdata[22];
9868: 
9869:   assign le1_le55_we = addr_hit[4] & reg_we & ~wr_err;
9870:   assign le1_le55_wd = reg_wdata[23];
9871: 
9872:   assign le1_le56_we = addr_hit[4] & reg_we & ~wr_err;
9873:   assign le1_le56_wd = reg_wdata[24];
9874: 
9875:   assign le1_le57_we = addr_hit[4] & reg_we & ~wr_err;
9876:   assign le1_le57_wd = reg_wdata[25];
9877: 
9878:   assign le1_le58_we = addr_hit[4] & reg_we & ~wr_err;
9879:   assign le1_le58_wd = reg_wdata[26];
9880: 
9881:   assign le1_le59_we = addr_hit[4] & reg_we & ~wr_err;
9882:   assign le1_le59_wd = reg_wdata[27];
9883: 
9884:   assign le1_le60_we = addr_hit[4] & reg_we & ~wr_err;
9885:   assign le1_le60_wd = reg_wdata[28];
9886: 
9887:   assign le1_le61_we = addr_hit[4] & reg_we & ~wr_err;
9888:   assign le1_le61_wd = reg_wdata[29];
9889: 
9890:   assign le1_le62_we = addr_hit[4] & reg_we & ~wr_err;
9891:   assign le1_le62_wd = reg_wdata[30];
9892: 
9893:   assign le1_le63_we = addr_hit[4] & reg_we & ~wr_err;
9894:   assign le1_le63_wd = reg_wdata[31];
9895: 
9896:   assign le2_le64_we = addr_hit[5] & reg_we & ~wr_err;
9897:   assign le2_le64_wd = reg_wdata[0];
9898: 
9899:   assign le2_le65_we = addr_hit[5] & reg_we & ~wr_err;
9900:   assign le2_le65_wd = reg_wdata[1];
9901: 
9902:   assign le2_le66_we = addr_hit[5] & reg_we & ~wr_err;
9903:   assign le2_le66_wd = reg_wdata[2];
9904: 
9905:   assign le2_le67_we = addr_hit[5] & reg_we & ~wr_err;
9906:   assign le2_le67_wd = reg_wdata[3];
9907: 
9908:   assign le2_le68_we = addr_hit[5] & reg_we & ~wr_err;
9909:   assign le2_le68_wd = reg_wdata[4];
9910: 
9911:   assign le2_le69_we = addr_hit[5] & reg_we & ~wr_err;
9912:   assign le2_le69_wd = reg_wdata[5];
9913: 
9914:   assign le2_le70_we = addr_hit[5] & reg_we & ~wr_err;
9915:   assign le2_le70_wd = reg_wdata[6];
9916: 
9917:   assign le2_le71_we = addr_hit[5] & reg_we & ~wr_err;
9918:   assign le2_le71_wd = reg_wdata[7];
9919: 
9920:   assign le2_le72_we = addr_hit[5] & reg_we & ~wr_err;
9921:   assign le2_le72_wd = reg_wdata[8];
9922: 
9923:   assign le2_le73_we = addr_hit[5] & reg_we & ~wr_err;
9924:   assign le2_le73_wd = reg_wdata[9];
9925: 
9926:   assign le2_le74_we = addr_hit[5] & reg_we & ~wr_err;
9927:   assign le2_le74_wd = reg_wdata[10];
9928: 
9929:   assign le2_le75_we = addr_hit[5] & reg_we & ~wr_err;
9930:   assign le2_le75_wd = reg_wdata[11];
9931: 
9932:   assign le2_le76_we = addr_hit[5] & reg_we & ~wr_err;
9933:   assign le2_le76_wd = reg_wdata[12];
9934: 
9935:   assign le2_le77_we = addr_hit[5] & reg_we & ~wr_err;
9936:   assign le2_le77_wd = reg_wdata[13];
9937: 
9938:   assign le2_le78_we = addr_hit[5] & reg_we & ~wr_err;
9939:   assign le2_le78_wd = reg_wdata[14];
9940: 
9941:   assign le2_le79_we = addr_hit[5] & reg_we & ~wr_err;
9942:   assign le2_le79_wd = reg_wdata[15];
9943: 
9944:   assign le2_le80_we = addr_hit[5] & reg_we & ~wr_err;
9945:   assign le2_le80_wd = reg_wdata[16];
9946: 
9947:   assign prio0_we = addr_hit[6] & reg_we & ~wr_err;
9948:   assign prio0_wd = reg_wdata[1:0];
9949: 
9950:   assign prio1_we = addr_hit[7] & reg_we & ~wr_err;
9951:   assign prio1_wd = reg_wdata[1:0];
9952: 
9953:   assign prio2_we = addr_hit[8] & reg_we & ~wr_err;
9954:   assign prio2_wd = reg_wdata[1:0];
9955: 
9956:   assign prio3_we = addr_hit[9] & reg_we & ~wr_err;
9957:   assign prio3_wd = reg_wdata[1:0];
9958: 
9959:   assign prio4_we = addr_hit[10] & reg_we & ~wr_err;
9960:   assign prio4_wd = reg_wdata[1:0];
9961: 
9962:   assign prio5_we = addr_hit[11] & reg_we & ~wr_err;
9963:   assign prio5_wd = reg_wdata[1:0];
9964: 
9965:   assign prio6_we = addr_hit[12] & reg_we & ~wr_err;
9966:   assign prio6_wd = reg_wdata[1:0];
9967: 
9968:   assign prio7_we = addr_hit[13] & reg_we & ~wr_err;
9969:   assign prio7_wd = reg_wdata[1:0];
9970: 
9971:   assign prio8_we = addr_hit[14] & reg_we & ~wr_err;
9972:   assign prio8_wd = reg_wdata[1:0];
9973: 
9974:   assign prio9_we = addr_hit[15] & reg_we & ~wr_err;
9975:   assign prio9_wd = reg_wdata[1:0];
9976: 
9977:   assign prio10_we = addr_hit[16] & reg_we & ~wr_err;
9978:   assign prio10_wd = reg_wdata[1:0];
9979: 
9980:   assign prio11_we = addr_hit[17] & reg_we & ~wr_err;
9981:   assign prio11_wd = reg_wdata[1:0];
9982: 
9983:   assign prio12_we = addr_hit[18] & reg_we & ~wr_err;
9984:   assign prio12_wd = reg_wdata[1:0];
9985: 
9986:   assign prio13_we = addr_hit[19] & reg_we & ~wr_err;
9987:   assign prio13_wd = reg_wdata[1:0];
9988: 
9989:   assign prio14_we = addr_hit[20] & reg_we & ~wr_err;
9990:   assign prio14_wd = reg_wdata[1:0];
9991: 
9992:   assign prio15_we = addr_hit[21] & reg_we & ~wr_err;
9993:   assign prio15_wd = reg_wdata[1:0];
9994: 
9995:   assign prio16_we = addr_hit[22] & reg_we & ~wr_err;
9996:   assign prio16_wd = reg_wdata[1:0];
9997: 
9998:   assign prio17_we = addr_hit[23] & reg_we & ~wr_err;
9999:   assign prio17_wd = reg_wdata[1:0];
10000: 
10001:   assign prio18_we = addr_hit[24] & reg_we & ~wr_err;
10002:   assign prio18_wd = reg_wdata[1:0];
10003: 
10004:   assign prio19_we = addr_hit[25] & reg_we & ~wr_err;
10005:   assign prio19_wd = reg_wdata[1:0];
10006: 
10007:   assign prio20_we = addr_hit[26] & reg_we & ~wr_err;
10008:   assign prio20_wd = reg_wdata[1:0];
10009: 
10010:   assign prio21_we = addr_hit[27] & reg_we & ~wr_err;
10011:   assign prio21_wd = reg_wdata[1:0];
10012: 
10013:   assign prio22_we = addr_hit[28] & reg_we & ~wr_err;
10014:   assign prio22_wd = reg_wdata[1:0];
10015: 
10016:   assign prio23_we = addr_hit[29] & reg_we & ~wr_err;
10017:   assign prio23_wd = reg_wdata[1:0];
10018: 
10019:   assign prio24_we = addr_hit[30] & reg_we & ~wr_err;
10020:   assign prio24_wd = reg_wdata[1:0];
10021: 
10022:   assign prio25_we = addr_hit[31] & reg_we & ~wr_err;
10023:   assign prio25_wd = reg_wdata[1:0];
10024: 
10025:   assign prio26_we = addr_hit[32] & reg_we & ~wr_err;
10026:   assign prio26_wd = reg_wdata[1:0];
10027: 
10028:   assign prio27_we = addr_hit[33] & reg_we & ~wr_err;
10029:   assign prio27_wd = reg_wdata[1:0];
10030: 
10031:   assign prio28_we = addr_hit[34] & reg_we & ~wr_err;
10032:   assign prio28_wd = reg_wdata[1:0];
10033: 
10034:   assign prio29_we = addr_hit[35] & reg_we & ~wr_err;
10035:   assign prio29_wd = reg_wdata[1:0];
10036: 
10037:   assign prio30_we = addr_hit[36] & reg_we & ~wr_err;
10038:   assign prio30_wd = reg_wdata[1:0];
10039: 
10040:   assign prio31_we = addr_hit[37] & reg_we & ~wr_err;
10041:   assign prio31_wd = reg_wdata[1:0];
10042: 
10043:   assign prio32_we = addr_hit[38] & reg_we & ~wr_err;
10044:   assign prio32_wd = reg_wdata[1:0];
10045: 
10046:   assign prio33_we = addr_hit[39] & reg_we & ~wr_err;
10047:   assign prio33_wd = reg_wdata[1:0];
10048: 
10049:   assign prio34_we = addr_hit[40] & reg_we & ~wr_err;
10050:   assign prio34_wd = reg_wdata[1:0];
10051: 
10052:   assign prio35_we = addr_hit[41] & reg_we & ~wr_err;
10053:   assign prio35_wd = reg_wdata[1:0];
10054: 
10055:   assign prio36_we = addr_hit[42] & reg_we & ~wr_err;
10056:   assign prio36_wd = reg_wdata[1:0];
10057: 
10058:   assign prio37_we = addr_hit[43] & reg_we & ~wr_err;
10059:   assign prio37_wd = reg_wdata[1:0];
10060: 
10061:   assign prio38_we = addr_hit[44] & reg_we & ~wr_err;
10062:   assign prio38_wd = reg_wdata[1:0];
10063: 
10064:   assign prio39_we = addr_hit[45] & reg_we & ~wr_err;
10065:   assign prio39_wd = reg_wdata[1:0];
10066: 
10067:   assign prio40_we = addr_hit[46] & reg_we & ~wr_err;
10068:   assign prio40_wd = reg_wdata[1:0];
10069: 
10070:   assign prio41_we = addr_hit[47] & reg_we & ~wr_err;
10071:   assign prio41_wd = reg_wdata[1:0];
10072: 
10073:   assign prio42_we = addr_hit[48] & reg_we & ~wr_err;
10074:   assign prio42_wd = reg_wdata[1:0];
10075: 
10076:   assign prio43_we = addr_hit[49] & reg_we & ~wr_err;
10077:   assign prio43_wd = reg_wdata[1:0];
10078: 
10079:   assign prio44_we = addr_hit[50] & reg_we & ~wr_err;
10080:   assign prio44_wd = reg_wdata[1:0];
10081: 
10082:   assign prio45_we = addr_hit[51] & reg_we & ~wr_err;
10083:   assign prio45_wd = reg_wdata[1:0];
10084: 
10085:   assign prio46_we = addr_hit[52] & reg_we & ~wr_err;
10086:   assign prio46_wd = reg_wdata[1:0];
10087: 
10088:   assign prio47_we = addr_hit[53] & reg_we & ~wr_err;
10089:   assign prio47_wd = reg_wdata[1:0];
10090: 
10091:   assign prio48_we = addr_hit[54] & reg_we & ~wr_err;
10092:   assign prio48_wd = reg_wdata[1:0];
10093: 
10094:   assign prio49_we = addr_hit[55] & reg_we & ~wr_err;
10095:   assign prio49_wd = reg_wdata[1:0];
10096: 
10097:   assign prio50_we = addr_hit[56] & reg_we & ~wr_err;
10098:   assign prio50_wd = reg_wdata[1:0];
10099: 
10100:   assign prio51_we = addr_hit[57] & reg_we & ~wr_err;
10101:   assign prio51_wd = reg_wdata[1:0];
10102: 
10103:   assign prio52_we = addr_hit[58] & reg_we & ~wr_err;
10104:   assign prio52_wd = reg_wdata[1:0];
10105: 
10106:   assign prio53_we = addr_hit[59] & reg_we & ~wr_err;
10107:   assign prio53_wd = reg_wdata[1:0];
10108: 
10109:   assign prio54_we = addr_hit[60] & reg_we & ~wr_err;
10110:   assign prio54_wd = reg_wdata[1:0];
10111: 
10112:   assign prio55_we = addr_hit[61] & reg_we & ~wr_err;
10113:   assign prio55_wd = reg_wdata[1:0];
10114: 
10115:   assign prio56_we = addr_hit[62] & reg_we & ~wr_err;
10116:   assign prio56_wd = reg_wdata[1:0];
10117: 
10118:   assign prio57_we = addr_hit[63] & reg_we & ~wr_err;
10119:   assign prio57_wd = reg_wdata[1:0];
10120: 
10121:   assign prio58_we = addr_hit[64] & reg_we & ~wr_err;
10122:   assign prio58_wd = reg_wdata[1:0];
10123: 
10124:   assign prio59_we = addr_hit[65] & reg_we & ~wr_err;
10125:   assign prio59_wd = reg_wdata[1:0];
10126: 
10127:   assign prio60_we = addr_hit[66] & reg_we & ~wr_err;
10128:   assign prio60_wd = reg_wdata[1:0];
10129: 
10130:   assign prio61_we = addr_hit[67] & reg_we & ~wr_err;
10131:   assign prio61_wd = reg_wdata[1:0];
10132: 
10133:   assign prio62_we = addr_hit[68] & reg_we & ~wr_err;
10134:   assign prio62_wd = reg_wdata[1:0];
10135: 
10136:   assign prio63_we = addr_hit[69] & reg_we & ~wr_err;
10137:   assign prio63_wd = reg_wdata[1:0];
10138: 
10139:   assign prio64_we = addr_hit[70] & reg_we & ~wr_err;
10140:   assign prio64_wd = reg_wdata[1:0];
10141: 
10142:   assign prio65_we = addr_hit[71] & reg_we & ~wr_err;
10143:   assign prio65_wd = reg_wdata[1:0];
10144: 
10145:   assign prio66_we = addr_hit[72] & reg_we & ~wr_err;
10146:   assign prio66_wd = reg_wdata[1:0];
10147: 
10148:   assign prio67_we = addr_hit[73] & reg_we & ~wr_err;
10149:   assign prio67_wd = reg_wdata[1:0];
10150: 
10151:   assign prio68_we = addr_hit[74] & reg_we & ~wr_err;
10152:   assign prio68_wd = reg_wdata[1:0];
10153: 
10154:   assign prio69_we = addr_hit[75] & reg_we & ~wr_err;
10155:   assign prio69_wd = reg_wdata[1:0];
10156: 
10157:   assign prio70_we = addr_hit[76] & reg_we & ~wr_err;
10158:   assign prio70_wd = reg_wdata[1:0];
10159: 
10160:   assign prio71_we = addr_hit[77] & reg_we & ~wr_err;
10161:   assign prio71_wd = reg_wdata[1:0];
10162: 
10163:   assign prio72_we = addr_hit[78] & reg_we & ~wr_err;
10164:   assign prio72_wd = reg_wdata[1:0];
10165: 
10166:   assign prio73_we = addr_hit[79] & reg_we & ~wr_err;
10167:   assign prio73_wd = reg_wdata[1:0];
10168: 
10169:   assign prio74_we = addr_hit[80] & reg_we & ~wr_err;
10170:   assign prio74_wd = reg_wdata[1:0];
10171: 
10172:   assign prio75_we = addr_hit[81] & reg_we & ~wr_err;
10173:   assign prio75_wd = reg_wdata[1:0];
10174: 
10175:   assign prio76_we = addr_hit[82] & reg_we & ~wr_err;
10176:   assign prio76_wd = reg_wdata[1:0];
10177: 
10178:   assign prio77_we = addr_hit[83] & reg_we & ~wr_err;
10179:   assign prio77_wd = reg_wdata[1:0];
10180: 
10181:   assign prio78_we = addr_hit[84] & reg_we & ~wr_err;
10182:   assign prio78_wd = reg_wdata[1:0];
10183: 
10184:   assign prio79_we = addr_hit[85] & reg_we & ~wr_err;
10185:   assign prio79_wd = reg_wdata[1:0];
10186: 
10187:   assign prio80_we = addr_hit[86] & reg_we & ~wr_err;
10188:   assign prio80_wd = reg_wdata[1:0];
10189: 
10190:   assign ie00_e0_we = addr_hit[87] & reg_we & ~wr_err;
10191:   assign ie00_e0_wd = reg_wdata[0];
10192: 
10193:   assign ie00_e1_we = addr_hit[87] & reg_we & ~wr_err;
10194:   assign ie00_e1_wd = reg_wdata[1];
10195: 
10196:   assign ie00_e2_we = addr_hit[87] & reg_we & ~wr_err;
10197:   assign ie00_e2_wd = reg_wdata[2];
10198: 
10199:   assign ie00_e3_we = addr_hit[87] & reg_we & ~wr_err;
10200:   assign ie00_e3_wd = reg_wdata[3];
10201: 
10202:   assign ie00_e4_we = addr_hit[87] & reg_we & ~wr_err;
10203:   assign ie00_e4_wd = reg_wdata[4];
10204: 
10205:   assign ie00_e5_we = addr_hit[87] & reg_we & ~wr_err;
10206:   assign ie00_e5_wd = reg_wdata[5];
10207: 
10208:   assign ie00_e6_we = addr_hit[87] & reg_we & ~wr_err;
10209:   assign ie00_e6_wd = reg_wdata[6];
10210: 
10211:   assign ie00_e7_we = addr_hit[87] & reg_we & ~wr_err;
10212:   assign ie00_e7_wd = reg_wdata[7];
10213: 
10214:   assign ie00_e8_we = addr_hit[87] & reg_we & ~wr_err;
10215:   assign ie00_e8_wd = reg_wdata[8];
10216: 
10217:   assign ie00_e9_we = addr_hit[87] & reg_we & ~wr_err;
10218:   assign ie00_e9_wd = reg_wdata[9];
10219: 
10220:   assign ie00_e10_we = addr_hit[87] & reg_we & ~wr_err;
10221:   assign ie00_e10_wd = reg_wdata[10];
10222: 
10223:   assign ie00_e11_we = addr_hit[87] & reg_we & ~wr_err;
10224:   assign ie00_e11_wd = reg_wdata[11];
10225: 
10226:   assign ie00_e12_we = addr_hit[87] & reg_we & ~wr_err;
10227:   assign ie00_e12_wd = reg_wdata[12];
10228: 
10229:   assign ie00_e13_we = addr_hit[87] & reg_we & ~wr_err;
10230:   assign ie00_e13_wd = reg_wdata[13];
10231: 
10232:   assign ie00_e14_we = addr_hit[87] & reg_we & ~wr_err;
10233:   assign ie00_e14_wd = reg_wdata[14];
10234: 
10235:   assign ie00_e15_we = addr_hit[87] & reg_we & ~wr_err;
10236:   assign ie00_e15_wd = reg_wdata[15];
10237: 
10238:   assign ie00_e16_we = addr_hit[87] & reg_we & ~wr_err;
10239:   assign ie00_e16_wd = reg_wdata[16];
10240: 
10241:   assign ie00_e17_we = addr_hit[87] & reg_we & ~wr_err;
10242:   assign ie00_e17_wd = reg_wdata[17];
10243: 
10244:   assign ie00_e18_we = addr_hit[87] & reg_we & ~wr_err;
10245:   assign ie00_e18_wd = reg_wdata[18];
10246: 
10247:   assign ie00_e19_we = addr_hit[87] & reg_we & ~wr_err;
10248:   assign ie00_e19_wd = reg_wdata[19];
10249: 
10250:   assign ie00_e20_we = addr_hit[87] & reg_we & ~wr_err;
10251:   assign ie00_e20_wd = reg_wdata[20];
10252: 
10253:   assign ie00_e21_we = addr_hit[87] & reg_we & ~wr_err;
10254:   assign ie00_e21_wd = reg_wdata[21];
10255: 
10256:   assign ie00_e22_we = addr_hit[87] & reg_we & ~wr_err;
10257:   assign ie00_e22_wd = reg_wdata[22];
10258: 
10259:   assign ie00_e23_we = addr_hit[87] & reg_we & ~wr_err;
10260:   assign ie00_e23_wd = reg_wdata[23];
10261: 
10262:   assign ie00_e24_we = addr_hit[87] & reg_we & ~wr_err;
10263:   assign ie00_e24_wd = reg_wdata[24];
10264: 
10265:   assign ie00_e25_we = addr_hit[87] & reg_we & ~wr_err;
10266:   assign ie00_e25_wd = reg_wdata[25];
10267: 
10268:   assign ie00_e26_we = addr_hit[87] & reg_we & ~wr_err;
10269:   assign ie00_e26_wd = reg_wdata[26];
10270: 
10271:   assign ie00_e27_we = addr_hit[87] & reg_we & ~wr_err;
10272:   assign ie00_e27_wd = reg_wdata[27];
10273: 
10274:   assign ie00_e28_we = addr_hit[87] & reg_we & ~wr_err;
10275:   assign ie00_e28_wd = reg_wdata[28];
10276: 
10277:   assign ie00_e29_we = addr_hit[87] & reg_we & ~wr_err;
10278:   assign ie00_e29_wd = reg_wdata[29];
10279: 
10280:   assign ie00_e30_we = addr_hit[87] & reg_we & ~wr_err;
10281:   assign ie00_e30_wd = reg_wdata[30];
10282: 
10283:   assign ie00_e31_we = addr_hit[87] & reg_we & ~wr_err;
10284:   assign ie00_e31_wd = reg_wdata[31];
10285: 
10286:   assign ie01_e32_we = addr_hit[88] & reg_we & ~wr_err;
10287:   assign ie01_e32_wd = reg_wdata[0];
10288: 
10289:   assign ie01_e33_we = addr_hit[88] & reg_we & ~wr_err;
10290:   assign ie01_e33_wd = reg_wdata[1];
10291: 
10292:   assign ie01_e34_we = addr_hit[88] & reg_we & ~wr_err;
10293:   assign ie01_e34_wd = reg_wdata[2];
10294: 
10295:   assign ie01_e35_we = addr_hit[88] & reg_we & ~wr_err;
10296:   assign ie01_e35_wd = reg_wdata[3];
10297: 
10298:   assign ie01_e36_we = addr_hit[88] & reg_we & ~wr_err;
10299:   assign ie01_e36_wd = reg_wdata[4];
10300: 
10301:   assign ie01_e37_we = addr_hit[88] & reg_we & ~wr_err;
10302:   assign ie01_e37_wd = reg_wdata[5];
10303: 
10304:   assign ie01_e38_we = addr_hit[88] & reg_we & ~wr_err;
10305:   assign ie01_e38_wd = reg_wdata[6];
10306: 
10307:   assign ie01_e39_we = addr_hit[88] & reg_we & ~wr_err;
10308:   assign ie01_e39_wd = reg_wdata[7];
10309: 
10310:   assign ie01_e40_we = addr_hit[88] & reg_we & ~wr_err;
10311:   assign ie01_e40_wd = reg_wdata[8];
10312: 
10313:   assign ie01_e41_we = addr_hit[88] & reg_we & ~wr_err;
10314:   assign ie01_e41_wd = reg_wdata[9];
10315: 
10316:   assign ie01_e42_we = addr_hit[88] & reg_we & ~wr_err;
10317:   assign ie01_e42_wd = reg_wdata[10];
10318: 
10319:   assign ie01_e43_we = addr_hit[88] & reg_we & ~wr_err;
10320:   assign ie01_e43_wd = reg_wdata[11];
10321: 
10322:   assign ie01_e44_we = addr_hit[88] & reg_we & ~wr_err;
10323:   assign ie01_e44_wd = reg_wdata[12];
10324: 
10325:   assign ie01_e45_we = addr_hit[88] & reg_we & ~wr_err;
10326:   assign ie01_e45_wd = reg_wdata[13];
10327: 
10328:   assign ie01_e46_we = addr_hit[88] & reg_we & ~wr_err;
10329:   assign ie01_e46_wd = reg_wdata[14];
10330: 
10331:   assign ie01_e47_we = addr_hit[88] & reg_we & ~wr_err;
10332:   assign ie01_e47_wd = reg_wdata[15];
10333: 
10334:   assign ie01_e48_we = addr_hit[88] & reg_we & ~wr_err;
10335:   assign ie01_e48_wd = reg_wdata[16];
10336: 
10337:   assign ie01_e49_we = addr_hit[88] & reg_we & ~wr_err;
10338:   assign ie01_e49_wd = reg_wdata[17];
10339: 
10340:   assign ie01_e50_we = addr_hit[88] & reg_we & ~wr_err;
10341:   assign ie01_e50_wd = reg_wdata[18];
10342: 
10343:   assign ie01_e51_we = addr_hit[88] & reg_we & ~wr_err;
10344:   assign ie01_e51_wd = reg_wdata[19];
10345: 
10346:   assign ie01_e52_we = addr_hit[88] & reg_we & ~wr_err;
10347:   assign ie01_e52_wd = reg_wdata[20];
10348: 
10349:   assign ie01_e53_we = addr_hit[88] & reg_we & ~wr_err;
10350:   assign ie01_e53_wd = reg_wdata[21];
10351: 
10352:   assign ie01_e54_we = addr_hit[88] & reg_we & ~wr_err;
10353:   assign ie01_e54_wd = reg_wdata[22];
10354: 
10355:   assign ie01_e55_we = addr_hit[88] & reg_we & ~wr_err;
10356:   assign ie01_e55_wd = reg_wdata[23];
10357: 
10358:   assign ie01_e56_we = addr_hit[88] & reg_we & ~wr_err;
10359:   assign ie01_e56_wd = reg_wdata[24];
10360: 
10361:   assign ie01_e57_we = addr_hit[88] & reg_we & ~wr_err;
10362:   assign ie01_e57_wd = reg_wdata[25];
10363: 
10364:   assign ie01_e58_we = addr_hit[88] & reg_we & ~wr_err;
10365:   assign ie01_e58_wd = reg_wdata[26];
10366: 
10367:   assign ie01_e59_we = addr_hit[88] & reg_we & ~wr_err;
10368:   assign ie01_e59_wd = reg_wdata[27];
10369: 
10370:   assign ie01_e60_we = addr_hit[88] & reg_we & ~wr_err;
10371:   assign ie01_e60_wd = reg_wdata[28];
10372: 
10373:   assign ie01_e61_we = addr_hit[88] & reg_we & ~wr_err;
10374:   assign ie01_e61_wd = reg_wdata[29];
10375: 
10376:   assign ie01_e62_we = addr_hit[88] & reg_we & ~wr_err;
10377:   assign ie01_e62_wd = reg_wdata[30];
10378: 
10379:   assign ie01_e63_we = addr_hit[88] & reg_we & ~wr_err;
10380:   assign ie01_e63_wd = reg_wdata[31];
10381: 
10382:   assign ie02_e64_we = addr_hit[89] & reg_we & ~wr_err;
10383:   assign ie02_e64_wd = reg_wdata[0];
10384: 
10385:   assign ie02_e65_we = addr_hit[89] & reg_we & ~wr_err;
10386:   assign ie02_e65_wd = reg_wdata[1];
10387: 
10388:   assign ie02_e66_we = addr_hit[89] & reg_we & ~wr_err;
10389:   assign ie02_e66_wd = reg_wdata[2];
10390: 
10391:   assign ie02_e67_we = addr_hit[89] & reg_we & ~wr_err;
10392:   assign ie02_e67_wd = reg_wdata[3];
10393: 
10394:   assign ie02_e68_we = addr_hit[89] & reg_we & ~wr_err;
10395:   assign ie02_e68_wd = reg_wdata[4];
10396: 
10397:   assign ie02_e69_we = addr_hit[89] & reg_we & ~wr_err;
10398:   assign ie02_e69_wd = reg_wdata[5];
10399: 
10400:   assign ie02_e70_we = addr_hit[89] & reg_we & ~wr_err;
10401:   assign ie02_e70_wd = reg_wdata[6];
10402: 
10403:   assign ie02_e71_we = addr_hit[89] & reg_we & ~wr_err;
10404:   assign ie02_e71_wd = reg_wdata[7];
10405: 
10406:   assign ie02_e72_we = addr_hit[89] & reg_we & ~wr_err;
10407:   assign ie02_e72_wd = reg_wdata[8];
10408: 
10409:   assign ie02_e73_we = addr_hit[89] & reg_we & ~wr_err;
10410:   assign ie02_e73_wd = reg_wdata[9];
10411: 
10412:   assign ie02_e74_we = addr_hit[89] & reg_we & ~wr_err;
10413:   assign ie02_e74_wd = reg_wdata[10];
10414: 
10415:   assign ie02_e75_we = addr_hit[89] & reg_we & ~wr_err;
10416:   assign ie02_e75_wd = reg_wdata[11];
10417: 
10418:   assign ie02_e76_we = addr_hit[89] & reg_we & ~wr_err;
10419:   assign ie02_e76_wd = reg_wdata[12];
10420: 
10421:   assign ie02_e77_we = addr_hit[89] & reg_we & ~wr_err;
10422:   assign ie02_e77_wd = reg_wdata[13];
10423: 
10424:   assign ie02_e78_we = addr_hit[89] & reg_we & ~wr_err;
10425:   assign ie02_e78_wd = reg_wdata[14];
10426: 
10427:   assign ie02_e79_we = addr_hit[89] & reg_we & ~wr_err;
10428:   assign ie02_e79_wd = reg_wdata[15];
10429: 
10430:   assign ie02_e80_we = addr_hit[89] & reg_we & ~wr_err;
10431:   assign ie02_e80_wd = reg_wdata[16];
10432: 
10433:   assign threshold0_we = addr_hit[90] & reg_we & ~wr_err;
10434:   assign threshold0_wd = reg_wdata[1:0];
10435: 
10436:   assign cc0_we = addr_hit[91] & reg_we & ~wr_err;
10437:   assign cc0_wd = reg_wdata[6:0];
10438:   assign cc0_re = addr_hit[91] && reg_re;
10439: 
10440:   assign msip0_we = addr_hit[92] & reg_we & ~wr_err;
10441:   assign msip0_wd = reg_wdata[0];
10442: 
10443:   // Read data return
10444:   always_comb begin
10445:     reg_rdata_next = '0;
10446:     unique case (1'b1)
10447:       addr_hit[0]: begin
10448:         reg_rdata_next[0] = ip0_p0_qs;
10449:         reg_rdata_next[1] = ip0_p1_qs;
10450:         reg_rdata_next[2] = ip0_p2_qs;
10451:         reg_rdata_next[3] = ip0_p3_qs;
10452:         reg_rdata_next[4] = ip0_p4_qs;
10453:         reg_rdata_next[5] = ip0_p5_qs;
10454:         reg_rdata_next[6] = ip0_p6_qs;
10455:         reg_rdata_next[7] = ip0_p7_qs;
10456:         reg_rdata_next[8] = ip0_p8_qs;
10457:         reg_rdata_next[9] = ip0_p9_qs;
10458:         reg_rdata_next[10] = ip0_p10_qs;
10459:         reg_rdata_next[11] = ip0_p11_qs;
10460:         reg_rdata_next[12] = ip0_p12_qs;
10461:         reg_rdata_next[13] = ip0_p13_qs;
10462:         reg_rdata_next[14] = ip0_p14_qs;
10463:         reg_rdata_next[15] = ip0_p15_qs;
10464:         reg_rdata_next[16] = ip0_p16_qs;
10465:         reg_rdata_next[17] = ip0_p17_qs;
10466:         reg_rdata_next[18] = ip0_p18_qs;
10467:         reg_rdata_next[19] = ip0_p19_qs;
10468:         reg_rdata_next[20] = ip0_p20_qs;
10469:         reg_rdata_next[21] = ip0_p21_qs;
10470:         reg_rdata_next[22] = ip0_p22_qs;
10471:         reg_rdata_next[23] = ip0_p23_qs;
10472:         reg_rdata_next[24] = ip0_p24_qs;
10473:         reg_rdata_next[25] = ip0_p25_qs;
10474:         reg_rdata_next[26] = ip0_p26_qs;
10475:         reg_rdata_next[27] = ip0_p27_qs;
10476:         reg_rdata_next[28] = ip0_p28_qs;
10477:         reg_rdata_next[29] = ip0_p29_qs;
10478:         reg_rdata_next[30] = ip0_p30_qs;
10479:         reg_rdata_next[31] = ip0_p31_qs;
10480:       end
10481: 
10482:       addr_hit[1]: begin
10483:         reg_rdata_next[0] = ip1_p32_qs;
10484:         reg_rdata_next[1] = ip1_p33_qs;
10485:         reg_rdata_next[2] = ip1_p34_qs;
10486:         reg_rdata_next[3] = ip1_p35_qs;
10487:         reg_rdata_next[4] = ip1_p36_qs;
10488:         reg_rdata_next[5] = ip1_p37_qs;
10489:         reg_rdata_next[6] = ip1_p38_qs;
10490:         reg_rdata_next[7] = ip1_p39_qs;
10491:         reg_rdata_next[8] = ip1_p40_qs;
10492:         reg_rdata_next[9] = ip1_p41_qs;
10493:         reg_rdata_next[10] = ip1_p42_qs;
10494:         reg_rdata_next[11] = ip1_p43_qs;
10495:         reg_rdata_next[12] = ip1_p44_qs;
10496:         reg_rdata_next[13] = ip1_p45_qs;
10497:         reg_rdata_next[14] = ip1_p46_qs;
10498:         reg_rdata_next[15] = ip1_p47_qs;
10499:         reg_rdata_next[16] = ip1_p48_qs;
10500:         reg_rdata_next[17] = ip1_p49_qs;
10501:         reg_rdata_next[18] = ip1_p50_qs;
10502:         reg_rdata_next[19] = ip1_p51_qs;
10503:         reg_rdata_next[20] = ip1_p52_qs;
10504:         reg_rdata_next[21] = ip1_p53_qs;
10505:         reg_rdata_next[22] = ip1_p54_qs;
10506:         reg_rdata_next[23] = ip1_p55_qs;
10507:         reg_rdata_next[24] = ip1_p56_qs;
10508:         reg_rdata_next[25] = ip1_p57_qs;
10509:         reg_rdata_next[26] = ip1_p58_qs;
10510:         reg_rdata_next[27] = ip1_p59_qs;
10511:         reg_rdata_next[28] = ip1_p60_qs;
10512:         reg_rdata_next[29] = ip1_p61_qs;
10513:         reg_rdata_next[30] = ip1_p62_qs;
10514:         reg_rdata_next[31] = ip1_p63_qs;
10515:       end
10516: 
10517:       addr_hit[2]: begin
10518:         reg_rdata_next[0] = ip2_p64_qs;
10519:         reg_rdata_next[1] = ip2_p65_qs;
10520:         reg_rdata_next[2] = ip2_p66_qs;
10521:         reg_rdata_next[3] = ip2_p67_qs;
10522:         reg_rdata_next[4] = ip2_p68_qs;
10523:         reg_rdata_next[5] = ip2_p69_qs;
10524:         reg_rdata_next[6] = ip2_p70_qs;
10525:         reg_rdata_next[7] = ip2_p71_qs;
10526:         reg_rdata_next[8] = ip2_p72_qs;
10527:         reg_rdata_next[9] = ip2_p73_qs;
10528:         reg_rdata_next[10] = ip2_p74_qs;
10529:         reg_rdata_next[11] = ip2_p75_qs;
10530:         reg_rdata_next[12] = ip2_p76_qs;
10531:         reg_rdata_next[13] = ip2_p77_qs;
10532:         reg_rdata_next[14] = ip2_p78_qs;
10533:         reg_rdata_next[15] = ip2_p79_qs;
10534:         reg_rdata_next[16] = ip2_p80_qs;
10535:       end
10536: 
10537:       addr_hit[3]: begin
10538:         reg_rdata_next[0] = le0_le0_qs;
10539:         reg_rdata_next[1] = le0_le1_qs;
10540:         reg_rdata_next[2] = le0_le2_qs;
10541:         reg_rdata_next[3] = le0_le3_qs;
10542:         reg_rdata_next[4] = le0_le4_qs;
10543:         reg_rdata_next[5] = le0_le5_qs;
10544:         reg_rdata_next[6] = le0_le6_qs;
10545:         reg_rdata_next[7] = le0_le7_qs;
10546:         reg_rdata_next[8] = le0_le8_qs;
10547:         reg_rdata_next[9] = le0_le9_qs;
10548:         reg_rdata_next[10] = le0_le10_qs;
10549:         reg_rdata_next[11] = le0_le11_qs;
10550:         reg_rdata_next[12] = le0_le12_qs;
10551:         reg_rdata_next[13] = le0_le13_qs;
10552:         reg_rdata_next[14] = le0_le14_qs;
10553:         reg_rdata_next[15] = le0_le15_qs;
10554:         reg_rdata_next[16] = le0_le16_qs;
10555:         reg_rdata_next[17] = le0_le17_qs;
10556:         reg_rdata_next[18] = le0_le18_qs;
10557:         reg_rdata_next[19] = le0_le19_qs;
10558:         reg_rdata_next[20] = le0_le20_qs;
10559:         reg_rdata_next[21] = le0_le21_qs;
10560:         reg_rdata_next[22] = le0_le22_qs;
10561:         reg_rdata_next[23] = le0_le23_qs;
10562:         reg_rdata_next[24] = le0_le24_qs;
10563:         reg_rdata_next[25] = le0_le25_qs;
10564:         reg_rdata_next[26] = le0_le26_qs;
10565:         reg_rdata_next[27] = le0_le27_qs;
10566:         reg_rdata_next[28] = le0_le28_qs;
10567:         reg_rdata_next[29] = le0_le29_qs;
10568:         reg_rdata_next[30] = le0_le30_qs;
10569:         reg_rdata_next[31] = le0_le31_qs;
10570:       end
10571: 
10572:       addr_hit[4]: begin
10573:         reg_rdata_next[0] = le1_le32_qs;
10574:         reg_rdata_next[1] = le1_le33_qs;
10575:         reg_rdata_next[2] = le1_le34_qs;
10576:         reg_rdata_next[3] = le1_le35_qs;
10577:         reg_rdata_next[4] = le1_le36_qs;
10578:         reg_rdata_next[5] = le1_le37_qs;
10579:         reg_rdata_next[6] = le1_le38_qs;
10580:         reg_rdata_next[7] = le1_le39_qs;
10581:         reg_rdata_next[8] = le1_le40_qs;
10582:         reg_rdata_next[9] = le1_le41_qs;
10583:         reg_rdata_next[10] = le1_le42_qs;
10584:         reg_rdata_next[11] = le1_le43_qs;
10585:         reg_rdata_next[12] = le1_le44_qs;
10586:         reg_rdata_next[13] = le1_le45_qs;
10587:         reg_rdata_next[14] = le1_le46_qs;
10588:         reg_rdata_next[15] = le1_le47_qs;
10589:         reg_rdata_next[16] = le1_le48_qs;
10590:         reg_rdata_next[17] = le1_le49_qs;
10591:         reg_rdata_next[18] = le1_le50_qs;
10592:         reg_rdata_next[19] = le1_le51_qs;
10593:         reg_rdata_next[20] = le1_le52_qs;
10594:         reg_rdata_next[21] = le1_le53_qs;
10595:         reg_rdata_next[22] = le1_le54_qs;
10596:         reg_rdata_next[23] = le1_le55_qs;
10597:         reg_rdata_next[24] = le1_le56_qs;
10598:         reg_rdata_next[25] = le1_le57_qs;
10599:         reg_rdata_next[26] = le1_le58_qs;
10600:         reg_rdata_next[27] = le1_le59_qs;
10601:         reg_rdata_next[28] = le1_le60_qs;
10602:         reg_rdata_next[29] = le1_le61_qs;
10603:         reg_rdata_next[30] = le1_le62_qs;
10604:         reg_rdata_next[31] = le1_le63_qs;
10605:       end
10606: 
10607:       addr_hit[5]: begin
10608:         reg_rdata_next[0] = le2_le64_qs;
10609:         reg_rdata_next[1] = le2_le65_qs;
10610:         reg_rdata_next[2] = le2_le66_qs;
10611:         reg_rdata_next[3] = le2_le67_qs;
10612:         reg_rdata_next[4] = le2_le68_qs;
10613:         reg_rdata_next[5] = le2_le69_qs;
10614:         reg_rdata_next[6] = le2_le70_qs;
10615:         reg_rdata_next[7] = le2_le71_qs;
10616:         reg_rdata_next[8] = le2_le72_qs;
10617:         reg_rdata_next[9] = le2_le73_qs;
10618:         reg_rdata_next[10] = le2_le74_qs;
10619:         reg_rdata_next[11] = le2_le75_qs;
10620:         reg_rdata_next[12] = le2_le76_qs;
10621:         reg_rdata_next[13] = le2_le77_qs;
10622:         reg_rdata_next[14] = le2_le78_qs;
10623:         reg_rdata_next[15] = le2_le79_qs;
10624:         reg_rdata_next[16] = le2_le80_qs;
10625:       end
10626: 
10627:       addr_hit[6]: begin
10628:         reg_rdata_next[1:0] = prio0_qs;
10629:       end
10630: 
10631:       addr_hit[7]: begin
10632:         reg_rdata_next[1:0] = prio1_qs;
10633:       end
10634: 
10635:       addr_hit[8]: begin
10636:         reg_rdata_next[1:0] = prio2_qs;
10637:       end
10638: 
10639:       addr_hit[9]: begin
10640:         reg_rdata_next[1:0] = prio3_qs;
10641:       end
10642: 
10643:       addr_hit[10]: begin
10644:         reg_rdata_next[1:0] = prio4_qs;
10645:       end
10646: 
10647:       addr_hit[11]: begin
10648:         reg_rdata_next[1:0] = prio5_qs;
10649:       end
10650: 
10651:       addr_hit[12]: begin
10652:         reg_rdata_next[1:0] = prio6_qs;
10653:       end
10654: 
10655:       addr_hit[13]: begin
10656:         reg_rdata_next[1:0] = prio7_qs;
10657:       end
10658: 
10659:       addr_hit[14]: begin
10660:         reg_rdata_next[1:0] = prio8_qs;
10661:       end
10662: 
10663:       addr_hit[15]: begin
10664:         reg_rdata_next[1:0] = prio9_qs;
10665:       end
10666: 
10667:       addr_hit[16]: begin
10668:         reg_rdata_next[1:0] = prio10_qs;
10669:       end
10670: 
10671:       addr_hit[17]: begin
10672:         reg_rdata_next[1:0] = prio11_qs;
10673:       end
10674: 
10675:       addr_hit[18]: begin
10676:         reg_rdata_next[1:0] = prio12_qs;
10677:       end
10678: 
10679:       addr_hit[19]: begin
10680:         reg_rdata_next[1:0] = prio13_qs;
10681:       end
10682: 
10683:       addr_hit[20]: begin
10684:         reg_rdata_next[1:0] = prio14_qs;
10685:       end
10686: 
10687:       addr_hit[21]: begin
10688:         reg_rdata_next[1:0] = prio15_qs;
10689:       end
10690: 
10691:       addr_hit[22]: begin
10692:         reg_rdata_next[1:0] = prio16_qs;
10693:       end
10694: 
10695:       addr_hit[23]: begin
10696:         reg_rdata_next[1:0] = prio17_qs;
10697:       end
10698: 
10699:       addr_hit[24]: begin
10700:         reg_rdata_next[1:0] = prio18_qs;
10701:       end
10702: 
10703:       addr_hit[25]: begin
10704:         reg_rdata_next[1:0] = prio19_qs;
10705:       end
10706: 
10707:       addr_hit[26]: begin
10708:         reg_rdata_next[1:0] = prio20_qs;
10709:       end
10710: 
10711:       addr_hit[27]: begin
10712:         reg_rdata_next[1:0] = prio21_qs;
10713:       end
10714: 
10715:       addr_hit[28]: begin
10716:         reg_rdata_next[1:0] = prio22_qs;
10717:       end
10718: 
10719:       addr_hit[29]: begin
10720:         reg_rdata_next[1:0] = prio23_qs;
10721:       end
10722: 
10723:       addr_hit[30]: begin
10724:         reg_rdata_next[1:0] = prio24_qs;
10725:       end
10726: 
10727:       addr_hit[31]: begin
10728:         reg_rdata_next[1:0] = prio25_qs;
10729:       end
10730: 
10731:       addr_hit[32]: begin
10732:         reg_rdata_next[1:0] = prio26_qs;
10733:       end
10734: 
10735:       addr_hit[33]: begin
10736:         reg_rdata_next[1:0] = prio27_qs;
10737:       end
10738: 
10739:       addr_hit[34]: begin
10740:         reg_rdata_next[1:0] = prio28_qs;
10741:       end
10742: 
10743:       addr_hit[35]: begin
10744:         reg_rdata_next[1:0] = prio29_qs;
10745:       end
10746: 
10747:       addr_hit[36]: begin
10748:         reg_rdata_next[1:0] = prio30_qs;
10749:       end
10750: 
10751:       addr_hit[37]: begin
10752:         reg_rdata_next[1:0] = prio31_qs;
10753:       end
10754: 
10755:       addr_hit[38]: begin
10756:         reg_rdata_next[1:0] = prio32_qs;
10757:       end
10758: 
10759:       addr_hit[39]: begin
10760:         reg_rdata_next[1:0] = prio33_qs;
10761:       end
10762: 
10763:       addr_hit[40]: begin
10764:         reg_rdata_next[1:0] = prio34_qs;
10765:       end
10766: 
10767:       addr_hit[41]: begin
10768:         reg_rdata_next[1:0] = prio35_qs;
10769:       end
10770: 
10771:       addr_hit[42]: begin
10772:         reg_rdata_next[1:0] = prio36_qs;
10773:       end
10774: 
10775:       addr_hit[43]: begin
10776:         reg_rdata_next[1:0] = prio37_qs;
10777:       end
10778: 
10779:       addr_hit[44]: begin
10780:         reg_rdata_next[1:0] = prio38_qs;
10781:       end
10782: 
10783:       addr_hit[45]: begin
10784:         reg_rdata_next[1:0] = prio39_qs;
10785:       end
10786: 
10787:       addr_hit[46]: begin
10788:         reg_rdata_next[1:0] = prio40_qs;
10789:       end
10790: 
10791:       addr_hit[47]: begin
10792:         reg_rdata_next[1:0] = prio41_qs;
10793:       end
10794: 
10795:       addr_hit[48]: begin
10796:         reg_rdata_next[1:0] = prio42_qs;
10797:       end
10798: 
10799:       addr_hit[49]: begin
10800:         reg_rdata_next[1:0] = prio43_qs;
10801:       end
10802: 
10803:       addr_hit[50]: begin
10804:         reg_rdata_next[1:0] = prio44_qs;
10805:       end
10806: 
10807:       addr_hit[51]: begin
10808:         reg_rdata_next[1:0] = prio45_qs;
10809:       end
10810: 
10811:       addr_hit[52]: begin
10812:         reg_rdata_next[1:0] = prio46_qs;
10813:       end
10814: 
10815:       addr_hit[53]: begin
10816:         reg_rdata_next[1:0] = prio47_qs;
10817:       end
10818: 
10819:       addr_hit[54]: begin
10820:         reg_rdata_next[1:0] = prio48_qs;
10821:       end
10822: 
10823:       addr_hit[55]: begin
10824:         reg_rdata_next[1:0] = prio49_qs;
10825:       end
10826: 
10827:       addr_hit[56]: begin
10828:         reg_rdata_next[1:0] = prio50_qs;
10829:       end
10830: 
10831:       addr_hit[57]: begin
10832:         reg_rdata_next[1:0] = prio51_qs;
10833:       end
10834: 
10835:       addr_hit[58]: begin
10836:         reg_rdata_next[1:0] = prio52_qs;
10837:       end
10838: 
10839:       addr_hit[59]: begin
10840:         reg_rdata_next[1:0] = prio53_qs;
10841:       end
10842: 
10843:       addr_hit[60]: begin
10844:         reg_rdata_next[1:0] = prio54_qs;
10845:       end
10846: 
10847:       addr_hit[61]: begin
10848:         reg_rdata_next[1:0] = prio55_qs;
10849:       end
10850: 
10851:       addr_hit[62]: begin
10852:         reg_rdata_next[1:0] = prio56_qs;
10853:       end
10854: 
10855:       addr_hit[63]: begin
10856:         reg_rdata_next[1:0] = prio57_qs;
10857:       end
10858: 
10859:       addr_hit[64]: begin
10860:         reg_rdata_next[1:0] = prio58_qs;
10861:       end
10862: 
10863:       addr_hit[65]: begin
10864:         reg_rdata_next[1:0] = prio59_qs;
10865:       end
10866: 
10867:       addr_hit[66]: begin
10868:         reg_rdata_next[1:0] = prio60_qs;
10869:       end
10870: 
10871:       addr_hit[67]: begin
10872:         reg_rdata_next[1:0] = prio61_qs;
10873:       end
10874: 
10875:       addr_hit[68]: begin
10876:         reg_rdata_next[1:0] = prio62_qs;
10877:       end
10878: 
10879:       addr_hit[69]: begin
10880:         reg_rdata_next[1:0] = prio63_qs;
10881:       end
10882: 
10883:       addr_hit[70]: begin
10884:         reg_rdata_next[1:0] = prio64_qs;
10885:       end
10886: 
10887:       addr_hit[71]: begin
10888:         reg_rdata_next[1:0] = prio65_qs;
10889:       end
10890: 
10891:       addr_hit[72]: begin
10892:         reg_rdata_next[1:0] = prio66_qs;
10893:       end
10894: 
10895:       addr_hit[73]: begin
10896:         reg_rdata_next[1:0] = prio67_qs;
10897:       end
10898: 
10899:       addr_hit[74]: begin
10900:         reg_rdata_next[1:0] = prio68_qs;
10901:       end
10902: 
10903:       addr_hit[75]: begin
10904:         reg_rdata_next[1:0] = prio69_qs;
10905:       end
10906: 
10907:       addr_hit[76]: begin
10908:         reg_rdata_next[1:0] = prio70_qs;
10909:       end
10910: 
10911:       addr_hit[77]: begin
10912:         reg_rdata_next[1:0] = prio71_qs;
10913:       end
10914: 
10915:       addr_hit[78]: begin
10916:         reg_rdata_next[1:0] = prio72_qs;
10917:       end
10918: 
10919:       addr_hit[79]: begin
10920:         reg_rdata_next[1:0] = prio73_qs;
10921:       end
10922: 
10923:       addr_hit[80]: begin
10924:         reg_rdata_next[1:0] = prio74_qs;
10925:       end
10926: 
10927:       addr_hit[81]: begin
10928:         reg_rdata_next[1:0] = prio75_qs;
10929:       end
10930: 
10931:       addr_hit[82]: begin
10932:         reg_rdata_next[1:0] = prio76_qs;
10933:       end
10934: 
10935:       addr_hit[83]: begin
10936:         reg_rdata_next[1:0] = prio77_qs;
10937:       end
10938: 
10939:       addr_hit[84]: begin
10940:         reg_rdata_next[1:0] = prio78_qs;
10941:       end
10942: 
10943:       addr_hit[85]: begin
10944:         reg_rdata_next[1:0] = prio79_qs;
10945:       end
10946: 
10947:       addr_hit[86]: begin
10948:         reg_rdata_next[1:0] = prio80_qs;
10949:       end
10950: 
10951:       addr_hit[87]: begin
10952:         reg_rdata_next[0] = ie00_e0_qs;
10953:         reg_rdata_next[1] = ie00_e1_qs;
10954:         reg_rdata_next[2] = ie00_e2_qs;
10955:         reg_rdata_next[3] = ie00_e3_qs;
10956:         reg_rdata_next[4] = ie00_e4_qs;
10957:         reg_rdata_next[5] = ie00_e5_qs;
10958:         reg_rdata_next[6] = ie00_e6_qs;
10959:         reg_rdata_next[7] = ie00_e7_qs;
10960:         reg_rdata_next[8] = ie00_e8_qs;
10961:         reg_rdata_next[9] = ie00_e9_qs;
10962:         reg_rdata_next[10] = ie00_e10_qs;
10963:         reg_rdata_next[11] = ie00_e11_qs;
10964:         reg_rdata_next[12] = ie00_e12_qs;
10965:         reg_rdata_next[13] = ie00_e13_qs;
10966:         reg_rdata_next[14] = ie00_e14_qs;
10967:         reg_rdata_next[15] = ie00_e15_qs;
10968:         reg_rdata_next[16] = ie00_e16_qs;
10969:         reg_rdata_next[17] = ie00_e17_qs;
10970:         reg_rdata_next[18] = ie00_e18_qs;
10971:         reg_rdata_next[19] = ie00_e19_qs;
10972:         reg_rdata_next[20] = ie00_e20_qs;
10973:         reg_rdata_next[21] = ie00_e21_qs;
10974:         reg_rdata_next[22] = ie00_e22_qs;
10975:         reg_rdata_next[23] = ie00_e23_qs;
10976:         reg_rdata_next[24] = ie00_e24_qs;
10977:         reg_rdata_next[25] = ie00_e25_qs;
10978:         reg_rdata_next[26] = ie00_e26_qs;
10979:         reg_rdata_next[27] = ie00_e27_qs;
10980:         reg_rdata_next[28] = ie00_e28_qs;
10981:         reg_rdata_next[29] = ie00_e29_qs;
10982:         reg_rdata_next[30] = ie00_e30_qs;
10983:         reg_rdata_next[31] = ie00_e31_qs;
10984:       end
10985: 
10986:       addr_hit[88]: begin
10987:         reg_rdata_next[0] = ie01_e32_qs;
10988:         reg_rdata_next[1] = ie01_e33_qs;
10989:         reg_rdata_next[2] = ie01_e34_qs;
10990:         reg_rdata_next[3] = ie01_e35_qs;
10991:         reg_rdata_next[4] = ie01_e36_qs;
10992:         reg_rdata_next[5] = ie01_e37_qs;
10993:         reg_rdata_next[6] = ie01_e38_qs;
10994:         reg_rdata_next[7] = ie01_e39_qs;
10995:         reg_rdata_next[8] = ie01_e40_qs;
10996:         reg_rdata_next[9] = ie01_e41_qs;
10997:         reg_rdata_next[10] = ie01_e42_qs;
10998:         reg_rdata_next[11] = ie01_e43_qs;
10999:         reg_rdata_next[12] = ie01_e44_qs;
11000:         reg_rdata_next[13] = ie01_e45_qs;
11001:         reg_rdata_next[14] = ie01_e46_qs;
11002:         reg_rdata_next[15] = ie01_e47_qs;
11003:         reg_rdata_next[16] = ie01_e48_qs;
11004:         reg_rdata_next[17] = ie01_e49_qs;
11005:         reg_rdata_next[18] = ie01_e50_qs;
11006:         reg_rdata_next[19] = ie01_e51_qs;
11007:         reg_rdata_next[20] = ie01_e52_qs;
11008:         reg_rdata_next[21] = ie01_e53_qs;
11009:         reg_rdata_next[22] = ie01_e54_qs;
11010:         reg_rdata_next[23] = ie01_e55_qs;
11011:         reg_rdata_next[24] = ie01_e56_qs;
11012:         reg_rdata_next[25] = ie01_e57_qs;
11013:         reg_rdata_next[26] = ie01_e58_qs;
11014:         reg_rdata_next[27] = ie01_e59_qs;
11015:         reg_rdata_next[28] = ie01_e60_qs;
11016:         reg_rdata_next[29] = ie01_e61_qs;
11017:         reg_rdata_next[30] = ie01_e62_qs;
11018:         reg_rdata_next[31] = ie01_e63_qs;
11019:       end
11020: 
11021:       addr_hit[89]: begin
11022:         reg_rdata_next[0] = ie02_e64_qs;
11023:         reg_rdata_next[1] = ie02_e65_qs;
11024:         reg_rdata_next[2] = ie02_e66_qs;
11025:         reg_rdata_next[3] = ie02_e67_qs;
11026:         reg_rdata_next[4] = ie02_e68_qs;
11027:         reg_rdata_next[5] = ie02_e69_qs;
11028:         reg_rdata_next[6] = ie02_e70_qs;
11029:         reg_rdata_next[7] = ie02_e71_qs;
11030:         reg_rdata_next[8] = ie02_e72_qs;
11031:         reg_rdata_next[9] = ie02_e73_qs;
11032:         reg_rdata_next[10] = ie02_e74_qs;
11033:         reg_rdata_next[11] = ie02_e75_qs;
11034:         reg_rdata_next[12] = ie02_e76_qs;
11035:         reg_rdata_next[13] = ie02_e77_qs;
11036:         reg_rdata_next[14] = ie02_e78_qs;
11037:         reg_rdata_next[15] = ie02_e79_qs;
11038:         reg_rdata_next[16] = ie02_e80_qs;
11039:       end
11040: 
11041:       addr_hit[90]: begin
11042:         reg_rdata_next[1:0] = threshold0_qs;
11043:       end
11044: 
11045:       addr_hit[91]: begin
11046:         reg_rdata_next[6:0] = cc0_qs;
11047:       end
11048: 
11049:       addr_hit[92]: begin
11050:         reg_rdata_next[0] = msip0_qs;
11051:       end
11052: 
11053:       default: begin
11054:         reg_rdata_next = '1;
11055:       end
11056:     endcase
11057:   end
11058: 
11059:   // Assertions for Register Interface
11060:   `ASSERT_PULSE(wePulse, reg_we)
11061:   `ASSERT_PULSE(rePulse, reg_re)
11062: 
11063:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
11064: 
11065:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
11066: 
11067:   // this is formulated as an assumption such that the FPV testbenches do disprove this
11068:   // property by mistake
11069:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
11070: 
11071: endmodule
11072: