../src/lowrisc_ip_flash_ctrl_0.1/rtl/flash_phy_rd_buffers.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Flash Phy Read Buffers
6: //
7: // This module implements the read buffers
8: // These buffers are straightforward flip flop storage.
9: // There are 3 inputs, alloc, upate and wipe.
10: //
11: // Alloc happens when a buffer is allocated, the state transitions to WIP.
12: //
13: // Update happens when a buffer has already been allocated, and is now being updated with data, the
14: // state transitions to VALID.
15: //
16: // Wipe happens when a buffer is wiped due to a program being issued to the same location, the
17: // state transitions to INVALID
18: //
19: // Basically...this is a tag ram + data ram combined into one
20: //
21:
22: module flash_phy_rd_buffers import flash_phy_pkg::*; (
23: input clk_i,
24: input rst_ni,
25: input alloc_i,
26: input update_i,
27: input wipe_i,
28: input [PrimFlashAddrW-1:0] addr_i,
29: input [DataWidth-1:0] data_i,
30: output rd_buf_t out_o
31: );
32:
33: always_ff @(posedge clk_i or negedge rst_ni) begin
34: if (!rst_ni) begin
35: out_o.data <= '0;
36: out_o.addr <= '0;
37: out_o.attr <= Invalid;
38: end else if (wipe_i) begin
39: out_o.attr <= Invalid;
40: end else if (alloc_i) begin
41: out_o.addr <= addr_i;
42: out_o.attr <= Wip;
43: end else if (update_i) begin
44: out_o.data <= data_i;
45: out_o.attr <= Valid;
46: end
47: end
48:
49: endmodule // flash_phy_rd_buffers
50: