hw/ip/tlul/rtl/tlul_socket_1n.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // TL-UL socket 1:N module
   6: //
   7: // configuration settings
   8: //   device_count: 4
   9: //
  10: // Verilog parameters
  11: //   HReqPass:      if 1 then host requests can pass through on empty fifo,
  12: //                  default 1
  13: //   HRspPass:      if 1 then host responses can pass through on empty fifo,
  14: //                  default 1
  15: //   DReqPass:      (one per device_count) if 1 then device i requests can
  16: //                  pass through on empty fifo, default 1
  17: //   DRspPass:      (one per device_count) if 1 then device i responses can
  18: //                  pass through on empty fifo, default 1
  19: //   HReqDepth:     Depth of host request FIFO, default 2
  20: //   HRspDepth:     Depth of host response FIFO, default 2
  21: //   DReqDepth:     (one per device_count) Depth of device i request FIFO,
  22: //                  default 2
  23: //   DRspDepth:     (one per device_count) Depth of device i response FIFO,
  24: //                  default 2
  25: //
  26: // Requests must stall to one slave until all responses from other slaves
  27: // have returned.  Need to keep a counter of all outstanding requests and
  28: // wait until that counter is zero before switching slaves.
  29: //
  30: // This module will return a request error if the input value of 'dev_select'
  31: // is not within the range 0..N-1. Thus the instantiator of the socket
  32: // can indicate error by any illegal value of dev_select. 4'b1111 is
  33: // recommended for visibility
  34: //
  35: // The maximum value of N is 15
  36: 
  37: module tlul_socket_1n #(
  38:   parameter int unsigned  N         = 4,
  39:   parameter bit           HReqPass  = 1'b1,
  40:   parameter bit           HRspPass  = 1'b1,
  41:   parameter bit [N-1:0]   DReqPass  = {N{1'b1}},
  42:   parameter bit [N-1:0]   DRspPass  = {N{1'b1}},
  43:   parameter bit [3:0]     HReqDepth = 4'h2,
  44:   parameter bit [3:0]     HRspDepth = 4'h2,
  45:   parameter bit [N*4-1:0] DReqDepth = {N{4'h2}},
  46:   parameter bit [N*4-1:0] DRspDepth = {N{4'h2}},
  47:   localparam int unsigned NWD       = $clog2(N+1) // derived parameter
  48: ) (
  49:   input                     clk_i,
  50:   input                     rst_ni,
  51:   input  tlul_pkg::tl_h2d_t tl_h_i,
  52:   output tlul_pkg::tl_d2h_t tl_h_o,
  53:   output tlul_pkg::tl_h2d_t tl_d_o    [N],
  54:   input  tlul_pkg::tl_d2h_t tl_d_i    [N],
  55:   input  [NWD-1:0]          dev_select
  56: );
  57: 
  58:   `ASSERT_INIT(maxN, N < 16)
  59: 
  60:   // Since our steering is done after potential FIFOing, we need to
  61:   // shove our device select bits into spare bits of reqfifo
  62: 
  63:   // instantiate the host fifo, create intermediate bus 't'
  64: 
  65:   // FIFO'd version of device select
  66:   logic [NWD-1:0] dev_select_t;
  67: 
  68:   tlul_pkg::tl_h2d_t   tl_t_o;
  69:   tlul_pkg::tl_d2h_t   tl_t_i;
  70: 
  71:   tlul_fifo_sync #(
  72:     .ReqPass(HReqPass),
  73:     .RspPass(HRspPass),
  74:     .ReqDepth(HReqDepth),
  75:     .RspDepth(HRspDepth),
  76:     .SpareReqW(NWD)
  77:   ) fifo_h (
  78:     .clk_i,
  79:     .rst_ni,
  80:     .tl_h_i,
  81:     .tl_h_o,
  82:     .tl_d_o     (tl_t_o),
  83:     .tl_d_i     (tl_t_i),
  84:     .spare_req_i (dev_select),
  85:     .spare_req_o (dev_select_t),
  86:     .spare_rsp_i (1'b0),
  87:     .spare_rsp_o ());
  88: 
  89: 
  90:   // We need to keep track of how many requests are outstanding,
  91:   // and to which device. New requests are compared to this and
  92:   // stall until that number is zero.
  93: 
  94:   logic [7:0]     num_req_outstanding;
  95:   logic [NWD-1:0] dev_select_outstanding;
  96:   logic           hold_all_requests;
  97:   logic           accept_t_req, accept_t_rsp;
  98: 
  99:   assign  accept_t_req = tl_t_o.a_valid & tl_t_i.a_ready;
 100:   assign  accept_t_rsp = tl_t_i.d_valid & tl_t_o.d_ready;
 101: 
 102:   always_ff @(posedge clk_i or negedge rst_ni) begin
 103:     if (!rst_ni) begin
 104:       num_req_outstanding <= 8'h0;
 105:       dev_select_outstanding <= '0;
 106:     end else if (accept_t_req) begin
 107:       if (!accept_t_rsp) begin
 108:         `ASSERT_I(NotOverflowed_A, num_req_outstanding != '1)
 109:         num_req_outstanding <= num_req_outstanding + 8'h1;
 110:       end
 111:       dev_select_outstanding <= dev_select_t;
 112:     end else if (accept_t_rsp) begin
 113:       num_req_outstanding <= num_req_outstanding - 8'h1;
 114:     end
 115:   end
 116: 
 117:   assign hold_all_requests =
 118:       (num_req_outstanding != 8'h0) &
 119:       (dev_select_t != dev_select_outstanding);
 120: 
 121:   // Make N copies of 't' request side with modified reqvalid, call
 122:   // them 'u[0]' .. 'u[n-1]'.
 123: 
 124:   tlul_pkg::tl_h2d_t   tl_u_o [N+1];
 125:   tlul_pkg::tl_d2h_t   tl_u_i [N+1];
 126: 
 127:   for (genvar i = 0 ; i < N ; i++) begin : gen_u_o
 128:     assign tl_u_o[i].a_valid   = tl_t_o.a_valid &
 129:                                  (dev_select_t == NWD'(i)) &
 130:                                  ~hold_all_requests;
 131:     assign tl_u_o[i].a_opcode  = tl_t_o.a_opcode;
 132:     assign tl_u_o[i].a_param   = tl_t_o.a_param;
 133:     assign tl_u_o[i].a_size    = tl_t_o.a_size;
 134:     assign tl_u_o[i].a_source  = tl_t_o.a_source;
 135:     assign tl_u_o[i].a_address = tl_t_o.a_address;
 136:     assign tl_u_o[i].a_mask    = tl_t_o.a_mask;
 137:     assign tl_u_o[i].a_data    = tl_t_o.a_data;
 138:     assign tl_u_o[i].a_user    = tl_t_o.a_user;
 139:   end
 140: 
 141:   tlul_pkg::tl_d2h_t tl_t_p ;
 142: 
 143:   // for the returning reqready, only look at the slave we're addressing
 144:   logic hfifo_reqready;
 145:   always_comb begin
 146:     hfifo_reqready = tl_u_i[N].a_ready; // default to error
 147:     for (int idx = 0 ; idx < N ; idx++) begin
 148:       //if (dev_select_outstanding == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
 149:       if (dev_select_t == NWD'(idx)) hfifo_reqready = tl_u_i[idx].a_ready;
 150:     end
 151:     if (hold_all_requests) hfifo_reqready = 1'b0;
 152:   end
 153:   // Adding a_valid as a qualifier. This prevents the a_ready from having unknown value
 154:   // when the address is unknown and the Host TL-UL FIFO is bypass mode.
 155:   assign tl_t_i.a_ready = tl_t_o.a_valid & hfifo_reqready;
 156: 
 157:   always_comb begin
 158:     tl_t_p = tl_u_i[N];
 159:     for (int idx = 0 ; idx < N ; idx++) begin
 160:       if (dev_select_outstanding == NWD'(idx)) tl_t_p = tl_u_i[idx];
 161:     end
 162:   end
 163:   assign tl_t_i.d_valid  = tl_t_p.d_valid ;
 164:   assign tl_t_i.d_opcode = tl_t_p.d_opcode;
 165:   assign tl_t_i.d_param  = tl_t_p.d_param ;
 166:   assign tl_t_i.d_size   = tl_t_p.d_size  ;
 167:   assign tl_t_i.d_source = tl_t_p.d_source;
 168:   assign tl_t_i.d_sink   = tl_t_p.d_sink  ;
 169:   assign tl_t_i.d_data   = tl_t_p.d_data  ;
 170:   assign tl_t_i.d_user   = tl_t_p.d_user  ;
 171:   assign tl_t_i.d_error  = tl_t_p.d_error ;
 172: 
 173: 
 174:   // accept responses from devices when selected if upstream is accepting
 175:   for (genvar i = 0 ; i < N+1 ; i++) begin : gen_u_o_d_ready
 176:     assign tl_u_o[i].d_ready = tl_t_o.d_ready;
 177:   end
 178: 
 179:   // finally instantiate all device FIFOs and the error responder
 180:   for (genvar i = 0 ; i < N ; i++) begin : gen_dfifo
 181:     tlul_fifo_sync #(
 182:       .ReqPass(DReqPass[i]),
 183:       .RspPass(DRspPass[i]),
 184:       .ReqDepth(DReqDepth[i*4+:4]),
 185:       .RspDepth(DRspDepth[i*4+:4])
 186:     ) fifo_d (
 187:       .clk_i,
 188:       .rst_ni,
 189:       .tl_h_i      (tl_u_o[i]),
 190:       .tl_h_o      (tl_u_i[i]),
 191:       .tl_d_o      (tl_d_o[i]),
 192:       .tl_d_i      (tl_d_i[i]),
 193:       .spare_req_i (1'b0),
 194:       .spare_req_o (),
 195:       .spare_rsp_i (1'b0),
 196:       .spare_rsp_o ());
 197:   end
 198: 
 199:   assign tl_u_o[N].a_valid     = tl_t_o.a_valid &
 200:                                  (dev_select_t == NWD'(N)) &
 201:                                  ~hold_all_requests;
 202:   assign tl_u_o[N].a_opcode    = tl_t_o.a_opcode;
 203:   assign tl_u_o[N].a_param     = tl_t_o.a_param;
 204:   assign tl_u_o[N].a_size      = tl_t_o.a_size;
 205:   assign tl_u_o[N].a_source    = tl_t_o.a_source;
 206:   assign tl_u_o[N].a_address   = tl_t_o.a_address;
 207:   assign tl_u_o[N].a_mask      = tl_t_o.a_mask;
 208:   assign tl_u_o[N].a_data      = tl_t_o.a_data;
 209:   assign tl_u_o[N].a_user      = tl_t_o.a_user;
 210:   tlul_err_resp err_resp (
 211:     .clk_i,
 212:     .rst_ni,
 213:     .tl_h_i     (tl_u_o[N]),
 214:     .tl_h_o     (tl_u_i[N]));
 215: 
 216: endmodule
 217: