hw/ip/uart/rtl/uart_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: module uart_reg_top (
8: input clk_i,
9: input rst_ni,
10:
11: // Below Regster interface can be changed
12: input tlul_pkg::tl_h2d_t tl_i,
13: output tlul_pkg::tl_d2h_t tl_o,
14: // To HW
15: output uart_reg_pkg::uart_reg2hw_t reg2hw, // Write
16: input uart_reg_pkg::uart_hw2reg_t hw2reg, // Read
17:
18: // Config
19: input devmode_i // If 1, explicit error return for unmapped register access
20: );
21:
22: import uart_reg_pkg::* ;
23:
24: localparam int AW = 6;
25: localparam int DW = 32;
26: localparam int DBW = DW/8; // Byte Width
27:
28: // register signals
29: logic reg_we;
30: logic reg_re;
31: logic [AW-1:0] reg_addr;
32: logic [DW-1:0] reg_wdata;
33: logic [DBW-1:0] reg_be;
34: logic [DW-1:0] reg_rdata;
35: logic reg_error;
36:
37: logic addrmiss, wr_err;
38:
39: logic [DW-1:0] reg_rdata_next;
40:
41: tlul_pkg::tl_h2d_t tl_reg_h2d;
42: tlul_pkg::tl_d2h_t tl_reg_d2h;
43:
44: assign tl_reg_h2d = tl_i;
45: assign tl_o = tl_reg_d2h;
46:
47: tlul_adapter_reg #(
48: .RegAw(AW),
49: .RegDw(DW)
50: ) u_reg_if (
51: .clk_i,
52: .rst_ni,
53:
54: .tl_i (tl_reg_h2d),
55: .tl_o (tl_reg_d2h),
56:
57: .we_o (reg_we),
58: .re_o (reg_re),
59: .addr_o (reg_addr),
60: .wdata_o (reg_wdata),
61: .be_o (reg_be),
62: .rdata_i (reg_rdata),
63: .error_i (reg_error)
64: );
65:
66: assign reg_rdata = reg_rdata_next ;
67: assign reg_error = (devmode_i & addrmiss) | wr_err ;
68:
69: // Define SW related signals
70: // Format: __{wd|we|qs}
71: // or _{wd|we|qs} if field == 1 or 0
72: logic intr_state_tx_watermark_qs;
73: logic intr_state_tx_watermark_wd;
74: logic intr_state_tx_watermark_we;
75: logic intr_state_rx_watermark_qs;
76: logic intr_state_rx_watermark_wd;
77: logic intr_state_rx_watermark_we;
78: logic intr_state_tx_empty_qs;
79: logic intr_state_tx_empty_wd;
80: logic intr_state_tx_empty_we;
81: logic intr_state_rx_overflow_qs;
82: logic intr_state_rx_overflow_wd;
83: logic intr_state_rx_overflow_we;
84: logic intr_state_rx_frame_err_qs;
85: logic intr_state_rx_frame_err_wd;
86: logic intr_state_rx_frame_err_we;
87: logic intr_state_rx_break_err_qs;
88: logic intr_state_rx_break_err_wd;
89: logic intr_state_rx_break_err_we;
90: logic intr_state_rx_timeout_qs;
91: logic intr_state_rx_timeout_wd;
92: logic intr_state_rx_timeout_we;
93: logic intr_state_rx_parity_err_qs;
94: logic intr_state_rx_parity_err_wd;
95: logic intr_state_rx_parity_err_we;
96: logic intr_enable_tx_watermark_qs;
97: logic intr_enable_tx_watermark_wd;
98: logic intr_enable_tx_watermark_we;
99: logic intr_enable_rx_watermark_qs;
100: logic intr_enable_rx_watermark_wd;
101: logic intr_enable_rx_watermark_we;
102: logic intr_enable_tx_empty_qs;
103: logic intr_enable_tx_empty_wd;
104: logic intr_enable_tx_empty_we;
105: logic intr_enable_rx_overflow_qs;
106: logic intr_enable_rx_overflow_wd;
107: logic intr_enable_rx_overflow_we;
108: logic intr_enable_rx_frame_err_qs;
109: logic intr_enable_rx_frame_err_wd;
110: logic intr_enable_rx_frame_err_we;
111: logic intr_enable_rx_break_err_qs;
112: logic intr_enable_rx_break_err_wd;
113: logic intr_enable_rx_break_err_we;
114: logic intr_enable_rx_timeout_qs;
115: logic intr_enable_rx_timeout_wd;
116: logic intr_enable_rx_timeout_we;
117: logic intr_enable_rx_parity_err_qs;
118: logic intr_enable_rx_parity_err_wd;
119: logic intr_enable_rx_parity_err_we;
120: logic intr_test_tx_watermark_wd;
121: logic intr_test_tx_watermark_we;
122: logic intr_test_rx_watermark_wd;
123: logic intr_test_rx_watermark_we;
124: logic intr_test_tx_empty_wd;
125: logic intr_test_tx_empty_we;
126: logic intr_test_rx_overflow_wd;
127: logic intr_test_rx_overflow_we;
128: logic intr_test_rx_frame_err_wd;
129: logic intr_test_rx_frame_err_we;
130: logic intr_test_rx_break_err_wd;
131: logic intr_test_rx_break_err_we;
132: logic intr_test_rx_timeout_wd;
133: logic intr_test_rx_timeout_we;
134: logic intr_test_rx_parity_err_wd;
135: logic intr_test_rx_parity_err_we;
136: logic ctrl_tx_qs;
137: logic ctrl_tx_wd;
138: logic ctrl_tx_we;
139: logic ctrl_rx_qs;
140: logic ctrl_rx_wd;
141: logic ctrl_rx_we;
142: logic ctrl_nf_qs;
143: logic ctrl_nf_wd;
144: logic ctrl_nf_we;
145: logic ctrl_slpbk_qs;
146: logic ctrl_slpbk_wd;
147: logic ctrl_slpbk_we;
148: logic ctrl_llpbk_qs;
149: logic ctrl_llpbk_wd;
150: logic ctrl_llpbk_we;
151: logic ctrl_parity_en_qs;
152: logic ctrl_parity_en_wd;
153: logic ctrl_parity_en_we;
154: logic ctrl_parity_odd_qs;
155: logic ctrl_parity_odd_wd;
156: logic ctrl_parity_odd_we;
157: logic [1:0] ctrl_rxblvl_qs;
158: logic [1:0] ctrl_rxblvl_wd;
159: logic ctrl_rxblvl_we;
160: logic [15:0] ctrl_nco_qs;
161: logic [15:0] ctrl_nco_wd;
162: logic ctrl_nco_we;
163: logic status_txfull_qs;
164: logic status_txfull_re;
165: logic status_rxfull_qs;
166: logic status_rxfull_re;
167: logic status_txempty_qs;
168: logic status_txempty_re;
169: logic status_txidle_qs;
170: logic status_txidle_re;
171: logic status_rxidle_qs;
172: logic status_rxidle_re;
173: logic status_rxempty_qs;
174: logic status_rxempty_re;
175: logic [7:0] rdata_qs;
176: logic rdata_re;
177: logic [7:0] wdata_wd;
178: logic wdata_we;
179: logic fifo_ctrl_rxrst_wd;
180: logic fifo_ctrl_rxrst_we;
181: logic fifo_ctrl_txrst_wd;
182: logic fifo_ctrl_txrst_we;
183: logic [2:0] fifo_ctrl_rxilvl_qs;
184: logic [2:0] fifo_ctrl_rxilvl_wd;
185: logic fifo_ctrl_rxilvl_we;
186: logic [1:0] fifo_ctrl_txilvl_qs;
187: logic [1:0] fifo_ctrl_txilvl_wd;
188: logic fifo_ctrl_txilvl_we;
189: logic [5:0] fifo_status_txlvl_qs;
190: logic fifo_status_txlvl_re;
191: logic [5:0] fifo_status_rxlvl_qs;
192: logic fifo_status_rxlvl_re;
193: logic ovrd_txen_qs;
194: logic ovrd_txen_wd;
195: logic ovrd_txen_we;
196: logic ovrd_txval_qs;
197: logic ovrd_txval_wd;
198: logic ovrd_txval_we;
199: logic [15:0] val_qs;
200: logic val_re;
201: logic [23:0] timeout_ctrl_val_qs;
202: logic [23:0] timeout_ctrl_val_wd;
203: logic timeout_ctrl_val_we;
204: logic timeout_ctrl_en_qs;
205: logic timeout_ctrl_en_wd;
206: logic timeout_ctrl_en_we;
207:
208: // Register instances
209: // R[intr_state]: V(False)
210:
211: // F[tx_watermark]: 0:0
212: prim_subreg #(
213: .DW (1),
214: .SWACCESS("W1C"),
215: .RESVAL (1'h0)
216: ) u_intr_state_tx_watermark (
217: .clk_i (clk_i ),
218: .rst_ni (rst_ni ),
219:
220: // from register interface
221: .we (intr_state_tx_watermark_we),
222: .wd (intr_state_tx_watermark_wd),
223:
224: // from internal hardware
225: .de (hw2reg.intr_state.tx_watermark.de),
226: .d (hw2reg.intr_state.tx_watermark.d ),
227:
228: // to internal hardware
229: .qe (),
230: .q (reg2hw.intr_state.tx_watermark.q ),
231:
232: // to register interface (read)
233: .qs (intr_state_tx_watermark_qs)
234: );
235:
236:
237: // F[rx_watermark]: 1:1
238: prim_subreg #(
239: .DW (1),
240: .SWACCESS("W1C"),
241: .RESVAL (1'h0)
242: ) u_intr_state_rx_watermark (
243: .clk_i (clk_i ),
244: .rst_ni (rst_ni ),
245:
246: // from register interface
247: .we (intr_state_rx_watermark_we),
248: .wd (intr_state_rx_watermark_wd),
249:
250: // from internal hardware
251: .de (hw2reg.intr_state.rx_watermark.de),
252: .d (hw2reg.intr_state.rx_watermark.d ),
253:
254: // to internal hardware
255: .qe (),
256: .q (reg2hw.intr_state.rx_watermark.q ),
257:
258: // to register interface (read)
259: .qs (intr_state_rx_watermark_qs)
260: );
261:
262:
263: // F[tx_empty]: 2:2
264: prim_subreg #(
265: .DW (1),
266: .SWACCESS("W1C"),
267: .RESVAL (1'h0)
268: ) u_intr_state_tx_empty (
269: .clk_i (clk_i ),
270: .rst_ni (rst_ni ),
271:
272: // from register interface
273: .we (intr_state_tx_empty_we),
274: .wd (intr_state_tx_empty_wd),
275:
276: // from internal hardware
277: .de (hw2reg.intr_state.tx_empty.de),
278: .d (hw2reg.intr_state.tx_empty.d ),
279:
280: // to internal hardware
281: .qe (),
282: .q (reg2hw.intr_state.tx_empty.q ),
283:
284: // to register interface (read)
285: .qs (intr_state_tx_empty_qs)
286: );
287:
288:
289: // F[rx_overflow]: 3:3
290: prim_subreg #(
291: .DW (1),
292: .SWACCESS("W1C"),
293: .RESVAL (1'h0)
294: ) u_intr_state_rx_overflow (
295: .clk_i (clk_i ),
296: .rst_ni (rst_ni ),
297:
298: // from register interface
299: .we (intr_state_rx_overflow_we),
300: .wd (intr_state_rx_overflow_wd),
301:
302: // from internal hardware
303: .de (hw2reg.intr_state.rx_overflow.de),
304: .d (hw2reg.intr_state.rx_overflow.d ),
305:
306: // to internal hardware
307: .qe (),
308: .q (reg2hw.intr_state.rx_overflow.q ),
309:
310: // to register interface (read)
311: .qs (intr_state_rx_overflow_qs)
312: );
313:
314:
315: // F[rx_frame_err]: 4:4
316: prim_subreg #(
317: .DW (1),
318: .SWACCESS("W1C"),
319: .RESVAL (1'h0)
320: ) u_intr_state_rx_frame_err (
321: .clk_i (clk_i ),
322: .rst_ni (rst_ni ),
323:
324: // from register interface
325: .we (intr_state_rx_frame_err_we),
326: .wd (intr_state_rx_frame_err_wd),
327:
328: // from internal hardware
329: .de (hw2reg.intr_state.rx_frame_err.de),
330: .d (hw2reg.intr_state.rx_frame_err.d ),
331:
332: // to internal hardware
333: .qe (),
334: .q (reg2hw.intr_state.rx_frame_err.q ),
335:
336: // to register interface (read)
337: .qs (intr_state_rx_frame_err_qs)
338: );
339:
340:
341: // F[rx_break_err]: 5:5
342: prim_subreg #(
343: .DW (1),
344: .SWACCESS("W1C"),
345: .RESVAL (1'h0)
346: ) u_intr_state_rx_break_err (
347: .clk_i (clk_i ),
348: .rst_ni (rst_ni ),
349:
350: // from register interface
351: .we (intr_state_rx_break_err_we),
352: .wd (intr_state_rx_break_err_wd),
353:
354: // from internal hardware
355: .de (hw2reg.intr_state.rx_break_err.de),
356: .d (hw2reg.intr_state.rx_break_err.d ),
357:
358: // to internal hardware
359: .qe (),
360: .q (reg2hw.intr_state.rx_break_err.q ),
361:
362: // to register interface (read)
363: .qs (intr_state_rx_break_err_qs)
364: );
365:
366:
367: // F[rx_timeout]: 6:6
368: prim_subreg #(
369: .DW (1),
370: .SWACCESS("W1C"),
371: .RESVAL (1'h0)
372: ) u_intr_state_rx_timeout (
373: .clk_i (clk_i ),
374: .rst_ni (rst_ni ),
375:
376: // from register interface
377: .we (intr_state_rx_timeout_we),
378: .wd (intr_state_rx_timeout_wd),
379:
380: // from internal hardware
381: .de (hw2reg.intr_state.rx_timeout.de),
382: .d (hw2reg.intr_state.rx_timeout.d ),
383:
384: // to internal hardware
385: .qe (),
386: .q (reg2hw.intr_state.rx_timeout.q ),
387:
388: // to register interface (read)
389: .qs (intr_state_rx_timeout_qs)
390: );
391:
392:
393: // F[rx_parity_err]: 7:7
394: prim_subreg #(
395: .DW (1),
396: .SWACCESS("W1C"),
397: .RESVAL (1'h0)
398: ) u_intr_state_rx_parity_err (
399: .clk_i (clk_i ),
400: .rst_ni (rst_ni ),
401:
402: // from register interface
403: .we (intr_state_rx_parity_err_we),
404: .wd (intr_state_rx_parity_err_wd),
405:
406: // from internal hardware
407: .de (hw2reg.intr_state.rx_parity_err.de),
408: .d (hw2reg.intr_state.rx_parity_err.d ),
409:
410: // to internal hardware
411: .qe (),
412: .q (reg2hw.intr_state.rx_parity_err.q ),
413:
414: // to register interface (read)
415: .qs (intr_state_rx_parity_err_qs)
416: );
417:
418:
419: // R[intr_enable]: V(False)
420:
421: // F[tx_watermark]: 0:0
422: prim_subreg #(
423: .DW (1),
424: .SWACCESS("RW"),
425: .RESVAL (1'h0)
426: ) u_intr_enable_tx_watermark (
427: .clk_i (clk_i ),
428: .rst_ni (rst_ni ),
429:
430: // from register interface
431: .we (intr_enable_tx_watermark_we),
432: .wd (intr_enable_tx_watermark_wd),
433:
434: // from internal hardware
435: .de (1'b0),
436: .d ('0 ),
437:
438: // to internal hardware
439: .qe (),
440: .q (reg2hw.intr_enable.tx_watermark.q ),
441:
442: // to register interface (read)
443: .qs (intr_enable_tx_watermark_qs)
444: );
445:
446:
447: // F[rx_watermark]: 1:1
448: prim_subreg #(
449: .DW (1),
450: .SWACCESS("RW"),
451: .RESVAL (1'h0)
452: ) u_intr_enable_rx_watermark (
453: .clk_i (clk_i ),
454: .rst_ni (rst_ni ),
455:
456: // from register interface
457: .we (intr_enable_rx_watermark_we),
458: .wd (intr_enable_rx_watermark_wd),
459:
460: // from internal hardware
461: .de (1'b0),
462: .d ('0 ),
463:
464: // to internal hardware
465: .qe (),
466: .q (reg2hw.intr_enable.rx_watermark.q ),
467:
468: // to register interface (read)
469: .qs (intr_enable_rx_watermark_qs)
470: );
471:
472:
473: // F[tx_empty]: 2:2
474: prim_subreg #(
475: .DW (1),
476: .SWACCESS("RW"),
477: .RESVAL (1'h0)
478: ) u_intr_enable_tx_empty (
479: .clk_i (clk_i ),
480: .rst_ni (rst_ni ),
481:
482: // from register interface
483: .we (intr_enable_tx_empty_we),
484: .wd (intr_enable_tx_empty_wd),
485:
486: // from internal hardware
487: .de (1'b0),
488: .d ('0 ),
489:
490: // to internal hardware
491: .qe (),
492: .q (reg2hw.intr_enable.tx_empty.q ),
493:
494: // to register interface (read)
495: .qs (intr_enable_tx_empty_qs)
496: );
497:
498:
499: // F[rx_overflow]: 3:3
500: prim_subreg #(
501: .DW (1),
502: .SWACCESS("RW"),
503: .RESVAL (1'h0)
504: ) u_intr_enable_rx_overflow (
505: .clk_i (clk_i ),
506: .rst_ni (rst_ni ),
507:
508: // from register interface
509: .we (intr_enable_rx_overflow_we),
510: .wd (intr_enable_rx_overflow_wd),
511:
512: // from internal hardware
513: .de (1'b0),
514: .d ('0 ),
515:
516: // to internal hardware
517: .qe (),
518: .q (reg2hw.intr_enable.rx_overflow.q ),
519:
520: // to register interface (read)
521: .qs (intr_enable_rx_overflow_qs)
522: );
523:
524:
525: // F[rx_frame_err]: 4:4
526: prim_subreg #(
527: .DW (1),
528: .SWACCESS("RW"),
529: .RESVAL (1'h0)
530: ) u_intr_enable_rx_frame_err (
531: .clk_i (clk_i ),
532: .rst_ni (rst_ni ),
533:
534: // from register interface
535: .we (intr_enable_rx_frame_err_we),
536: .wd (intr_enable_rx_frame_err_wd),
537:
538: // from internal hardware
539: .de (1'b0),
540: .d ('0 ),
541:
542: // to internal hardware
543: .qe (),
544: .q (reg2hw.intr_enable.rx_frame_err.q ),
545:
546: // to register interface (read)
547: .qs (intr_enable_rx_frame_err_qs)
548: );
549:
550:
551: // F[rx_break_err]: 5:5
552: prim_subreg #(
553: .DW (1),
554: .SWACCESS("RW"),
555: .RESVAL (1'h0)
556: ) u_intr_enable_rx_break_err (
557: .clk_i (clk_i ),
558: .rst_ni (rst_ni ),
559:
560: // from register interface
561: .we (intr_enable_rx_break_err_we),
562: .wd (intr_enable_rx_break_err_wd),
563:
564: // from internal hardware
565: .de (1'b0),
566: .d ('0 ),
567:
568: // to internal hardware
569: .qe (),
570: .q (reg2hw.intr_enable.rx_break_err.q ),
571:
572: // to register interface (read)
573: .qs (intr_enable_rx_break_err_qs)
574: );
575:
576:
577: // F[rx_timeout]: 6:6
578: prim_subreg #(
579: .DW (1),
580: .SWACCESS("RW"),
581: .RESVAL (1'h0)
582: ) u_intr_enable_rx_timeout (
583: .clk_i (clk_i ),
584: .rst_ni (rst_ni ),
585:
586: // from register interface
587: .we (intr_enable_rx_timeout_we),
588: .wd (intr_enable_rx_timeout_wd),
589:
590: // from internal hardware
591: .de (1'b0),
592: .d ('0 ),
593:
594: // to internal hardware
595: .qe (),
596: .q (reg2hw.intr_enable.rx_timeout.q ),
597:
598: // to register interface (read)
599: .qs (intr_enable_rx_timeout_qs)
600: );
601:
602:
603: // F[rx_parity_err]: 7:7
604: prim_subreg #(
605: .DW (1),
606: .SWACCESS("RW"),
607: .RESVAL (1'h0)
608: ) u_intr_enable_rx_parity_err (
609: .clk_i (clk_i ),
610: .rst_ni (rst_ni ),
611:
612: // from register interface
613: .we (intr_enable_rx_parity_err_we),
614: .wd (intr_enable_rx_parity_err_wd),
615:
616: // from internal hardware
617: .de (1'b0),
618: .d ('0 ),
619:
620: // to internal hardware
621: .qe (),
622: .q (reg2hw.intr_enable.rx_parity_err.q ),
623:
624: // to register interface (read)
625: .qs (intr_enable_rx_parity_err_qs)
626: );
627:
628:
629: // R[intr_test]: V(True)
630:
631: // F[tx_watermark]: 0:0
632: prim_subreg_ext #(
633: .DW (1)
634: ) u_intr_test_tx_watermark (
635: .re (1'b0),
636: .we (intr_test_tx_watermark_we),
637: .wd (intr_test_tx_watermark_wd),
638: .d ('0),
639: .qre (),
640: .qe (reg2hw.intr_test.tx_watermark.qe),
641: .q (reg2hw.intr_test.tx_watermark.q ),
642: .qs ()
643: );
644:
645:
646: // F[rx_watermark]: 1:1
647: prim_subreg_ext #(
648: .DW (1)
649: ) u_intr_test_rx_watermark (
650: .re (1'b0),
651: .we (intr_test_rx_watermark_we),
652: .wd (intr_test_rx_watermark_wd),
653: .d ('0),
654: .qre (),
655: .qe (reg2hw.intr_test.rx_watermark.qe),
656: .q (reg2hw.intr_test.rx_watermark.q ),
657: .qs ()
658: );
659:
660:
661: // F[tx_empty]: 2:2
662: prim_subreg_ext #(
663: .DW (1)
664: ) u_intr_test_tx_empty (
665: .re (1'b0),
666: .we (intr_test_tx_empty_we),
667: .wd (intr_test_tx_empty_wd),
668: .d ('0),
669: .qre (),
670: .qe (reg2hw.intr_test.tx_empty.qe),
671: .q (reg2hw.intr_test.tx_empty.q ),
672: .qs ()
673: );
674:
675:
676: // F[rx_overflow]: 3:3
677: prim_subreg_ext #(
678: .DW (1)
679: ) u_intr_test_rx_overflow (
680: .re (1'b0),
681: .we (intr_test_rx_overflow_we),
682: .wd (intr_test_rx_overflow_wd),
683: .d ('0),
684: .qre (),
685: .qe (reg2hw.intr_test.rx_overflow.qe),
686: .q (reg2hw.intr_test.rx_overflow.q ),
687: .qs ()
688: );
689:
690:
691: // F[rx_frame_err]: 4:4
692: prim_subreg_ext #(
693: .DW (1)
694: ) u_intr_test_rx_frame_err (
695: .re (1'b0),
696: .we (intr_test_rx_frame_err_we),
697: .wd (intr_test_rx_frame_err_wd),
698: .d ('0),
699: .qre (),
700: .qe (reg2hw.intr_test.rx_frame_err.qe),
701: .q (reg2hw.intr_test.rx_frame_err.q ),
702: .qs ()
703: );
704:
705:
706: // F[rx_break_err]: 5:5
707: prim_subreg_ext #(
708: .DW (1)
709: ) u_intr_test_rx_break_err (
710: .re (1'b0),
711: .we (intr_test_rx_break_err_we),
712: .wd (intr_test_rx_break_err_wd),
713: .d ('0),
714: .qre (),
715: .qe (reg2hw.intr_test.rx_break_err.qe),
716: .q (reg2hw.intr_test.rx_break_err.q ),
717: .qs ()
718: );
719:
720:
721: // F[rx_timeout]: 6:6
722: prim_subreg_ext #(
723: .DW (1)
724: ) u_intr_test_rx_timeout (
725: .re (1'b0),
726: .we (intr_test_rx_timeout_we),
727: .wd (intr_test_rx_timeout_wd),
728: .d ('0),
729: .qre (),
730: .qe (reg2hw.intr_test.rx_timeout.qe),
731: .q (reg2hw.intr_test.rx_timeout.q ),
732: .qs ()
733: );
734:
735:
736: // F[rx_parity_err]: 7:7
737: prim_subreg_ext #(
738: .DW (1)
739: ) u_intr_test_rx_parity_err (
740: .re (1'b0),
741: .we (intr_test_rx_parity_err_we),
742: .wd (intr_test_rx_parity_err_wd),
743: .d ('0),
744: .qre (),
745: .qe (reg2hw.intr_test.rx_parity_err.qe),
746: .q (reg2hw.intr_test.rx_parity_err.q ),
747: .qs ()
748: );
749:
750:
751: // R[ctrl]: V(False)
752:
753: // F[tx]: 0:0
754: prim_subreg #(
755: .DW (1),
756: .SWACCESS("RW"),
757: .RESVAL (1'h0)
758: ) u_ctrl_tx (
759: .clk_i (clk_i ),
760: .rst_ni (rst_ni ),
761:
762: // from register interface
763: .we (ctrl_tx_we),
764: .wd (ctrl_tx_wd),
765:
766: // from internal hardware
767: .de (1'b0),
768: .d ('0 ),
769:
770: // to internal hardware
771: .qe (),
772: .q (reg2hw.ctrl.tx.q ),
773:
774: // to register interface (read)
775: .qs (ctrl_tx_qs)
776: );
777:
778:
779: // F[rx]: 1:1
780: prim_subreg #(
781: .DW (1),
782: .SWACCESS("RW"),
783: .RESVAL (1'h0)
784: ) u_ctrl_rx (
785: .clk_i (clk_i ),
786: .rst_ni (rst_ni ),
787:
788: // from register interface
789: .we (ctrl_rx_we),
790: .wd (ctrl_rx_wd),
791:
792: // from internal hardware
793: .de (1'b0),
794: .d ('0 ),
795:
796: // to internal hardware
797: .qe (),
798: .q (reg2hw.ctrl.rx.q ),
799:
800: // to register interface (read)
801: .qs (ctrl_rx_qs)
802: );
803:
804:
805: // F[nf]: 2:2
806: prim_subreg #(
807: .DW (1),
808: .SWACCESS("RW"),
809: .RESVAL (1'h0)
810: ) u_ctrl_nf (
811: .clk_i (clk_i ),
812: .rst_ni (rst_ni ),
813:
814: // from register interface
815: .we (ctrl_nf_we),
816: .wd (ctrl_nf_wd),
817:
818: // from internal hardware
819: .de (1'b0),
820: .d ('0 ),
821:
822: // to internal hardware
823: .qe (),
824: .q (reg2hw.ctrl.nf.q ),
825:
826: // to register interface (read)
827: .qs (ctrl_nf_qs)
828: );
829:
830:
831: // F[slpbk]: 4:4
832: prim_subreg #(
833: .DW (1),
834: .SWACCESS("RW"),
835: .RESVAL (1'h0)
836: ) u_ctrl_slpbk (
837: .clk_i (clk_i ),
838: .rst_ni (rst_ni ),
839:
840: // from register interface
841: .we (ctrl_slpbk_we),
842: .wd (ctrl_slpbk_wd),
843:
844: // from internal hardware
845: .de (1'b0),
846: .d ('0 ),
847:
848: // to internal hardware
849: .qe (),
850: .q (reg2hw.ctrl.slpbk.q ),
851:
852: // to register interface (read)
853: .qs (ctrl_slpbk_qs)
854: );
855:
856:
857: // F[llpbk]: 5:5
858: prim_subreg #(
859: .DW (1),
860: .SWACCESS("RW"),
861: .RESVAL (1'h0)
862: ) u_ctrl_llpbk (
863: .clk_i (clk_i ),
864: .rst_ni (rst_ni ),
865:
866: // from register interface
867: .we (ctrl_llpbk_we),
868: .wd (ctrl_llpbk_wd),
869:
870: // from internal hardware
871: .de (1'b0),
872: .d ('0 ),
873:
874: // to internal hardware
875: .qe (),
876: .q (reg2hw.ctrl.llpbk.q ),
877:
878: // to register interface (read)
879: .qs (ctrl_llpbk_qs)
880: );
881:
882:
883: // F[parity_en]: 6:6
884: prim_subreg #(
885: .DW (1),
886: .SWACCESS("RW"),
887: .RESVAL (1'h0)
888: ) u_ctrl_parity_en (
889: .clk_i (clk_i ),
890: .rst_ni (rst_ni ),
891:
892: // from register interface
893: .we (ctrl_parity_en_we),
894: .wd (ctrl_parity_en_wd),
895:
896: // from internal hardware
897: .de (1'b0),
898: .d ('0 ),
899:
900: // to internal hardware
901: .qe (),
902: .q (reg2hw.ctrl.parity_en.q ),
903:
904: // to register interface (read)
905: .qs (ctrl_parity_en_qs)
906: );
907:
908:
909: // F[parity_odd]: 7:7
910: prim_subreg #(
911: .DW (1),
912: .SWACCESS("RW"),
913: .RESVAL (1'h0)
914: ) u_ctrl_parity_odd (
915: .clk_i (clk_i ),
916: .rst_ni (rst_ni ),
917:
918: // from register interface
919: .we (ctrl_parity_odd_we),
920: .wd (ctrl_parity_odd_wd),
921:
922: // from internal hardware
923: .de (1'b0),
924: .d ('0 ),
925:
926: // to internal hardware
927: .qe (),
928: .q (reg2hw.ctrl.parity_odd.q ),
929:
930: // to register interface (read)
931: .qs (ctrl_parity_odd_qs)
932: );
933:
934:
935: // F[rxblvl]: 9:8
936: prim_subreg #(
937: .DW (2),
938: .SWACCESS("RW"),
939: .RESVAL (2'h0)
940: ) u_ctrl_rxblvl (
941: .clk_i (clk_i ),
942: .rst_ni (rst_ni ),
943:
944: // from register interface
945: .we (ctrl_rxblvl_we),
946: .wd (ctrl_rxblvl_wd),
947:
948: // from internal hardware
949: .de (1'b0),
950: .d ('0 ),
951:
952: // to internal hardware
953: .qe (),
954: .q (reg2hw.ctrl.rxblvl.q ),
955:
956: // to register interface (read)
957: .qs (ctrl_rxblvl_qs)
958: );
959:
960:
961: // F[nco]: 31:16
962: prim_subreg #(
963: .DW (16),
964: .SWACCESS("RW"),
965: .RESVAL (16'h0)
966: ) u_ctrl_nco (
967: .clk_i (clk_i ),
968: .rst_ni (rst_ni ),
969:
970: // from register interface
971: .we (ctrl_nco_we),
972: .wd (ctrl_nco_wd),
973:
974: // from internal hardware
975: .de (1'b0),
976: .d ('0 ),
977:
978: // to internal hardware
979: .qe (),
980: .q (reg2hw.ctrl.nco.q ),
981:
982: // to register interface (read)
983: .qs (ctrl_nco_qs)
984: );
985:
986:
987: // R[status]: V(True)
988:
989: // F[txfull]: 0:0
990: prim_subreg_ext #(
991: .DW (1)
992: ) u_status_txfull (
993: .re (status_txfull_re),
994: .we (1'b0),
995: .wd ('0),
996: .d (hw2reg.status.txfull.d),
997: .qre (reg2hw.status.txfull.re),
998: .qe (),
999: .q (reg2hw.status.txfull.q ),
1000: .qs (status_txfull_qs)
1001: );
1002:
1003:
1004: // F[rxfull]: 1:1
1005: prim_subreg_ext #(
1006: .DW (1)
1007: ) u_status_rxfull (
1008: .re (status_rxfull_re),
1009: .we (1'b0),
1010: .wd ('0),
1011: .d (hw2reg.status.rxfull.d),
1012: .qre (reg2hw.status.rxfull.re),
1013: .qe (),
1014: .q (reg2hw.status.rxfull.q ),
1015: .qs (status_rxfull_qs)
1016: );
1017:
1018:
1019: // F[txempty]: 2:2
1020: prim_subreg_ext #(
1021: .DW (1)
1022: ) u_status_txempty (
1023: .re (status_txempty_re),
1024: .we (1'b0),
1025: .wd ('0),
1026: .d (hw2reg.status.txempty.d),
1027: .qre (reg2hw.status.txempty.re),
1028: .qe (),
1029: .q (reg2hw.status.txempty.q ),
1030: .qs (status_txempty_qs)
1031: );
1032:
1033:
1034: // F[txidle]: 3:3
1035: prim_subreg_ext #(
1036: .DW (1)
1037: ) u_status_txidle (
1038: .re (status_txidle_re),
1039: .we (1'b0),
1040: .wd ('0),
1041: .d (hw2reg.status.txidle.d),
1042: .qre (reg2hw.status.txidle.re),
1043: .qe (),
1044: .q (reg2hw.status.txidle.q ),
1045: .qs (status_txidle_qs)
1046: );
1047:
1048:
1049: // F[rxidle]: 4:4
1050: prim_subreg_ext #(
1051: .DW (1)
1052: ) u_status_rxidle (
1053: .re (status_rxidle_re),
1054: .we (1'b0),
1055: .wd ('0),
1056: .d (hw2reg.status.rxidle.d),
1057: .qre (reg2hw.status.rxidle.re),
1058: .qe (),
1059: .q (reg2hw.status.rxidle.q ),
1060: .qs (status_rxidle_qs)
1061: );
1062:
1063:
1064: // F[rxempty]: 5:5
1065: prim_subreg_ext #(
1066: .DW (1)
1067: ) u_status_rxempty (
1068: .re (status_rxempty_re),
1069: .we (1'b0),
1070: .wd ('0),
1071: .d (hw2reg.status.rxempty.d),
1072: .qre (reg2hw.status.rxempty.re),
1073: .qe (),
1074: .q (reg2hw.status.rxempty.q ),
1075: .qs (status_rxempty_qs)
1076: );
1077:
1078:
1079: // R[rdata]: V(True)
1080:
1081: prim_subreg_ext #(
1082: .DW (8)
1083: ) u_rdata (
1084: .re (rdata_re),
1085: .we (1'b0),
1086: .wd ('0),
1087: .d (hw2reg.rdata.d),
1088: .qre (reg2hw.rdata.re),
1089: .qe (),
1090: .q (reg2hw.rdata.q ),
1091: .qs (rdata_qs)
1092: );
1093:
1094:
1095: // R[wdata]: V(False)
1096:
1097: prim_subreg #(
1098: .DW (8),
1099: .SWACCESS("WO"),
1100: .RESVAL (8'h0)
1101: ) u_wdata (
1102: .clk_i (clk_i ),
1103: .rst_ni (rst_ni ),
1104:
1105: // from register interface
1106: .we (wdata_we),
1107: .wd (wdata_wd),
1108:
1109: // from internal hardware
1110: .de (1'b0),
1111: .d ('0 ),
1112:
1113: // to internal hardware
1114: .qe (reg2hw.wdata.qe),
1115: .q (reg2hw.wdata.q ),
1116:
1117: .qs ()
1118: );
1119:
1120:
1121: // R[fifo_ctrl]: V(False)
1122:
1123: // F[rxrst]: 0:0
1124: prim_subreg #(
1125: .DW (1),
1126: .SWACCESS("WO"),
1127: .RESVAL (1'h0)
1128: ) u_fifo_ctrl_rxrst (
1129: .clk_i (clk_i ),
1130: .rst_ni (rst_ni ),
1131:
1132: // from register interface
1133: .we (fifo_ctrl_rxrst_we),
1134: .wd (fifo_ctrl_rxrst_wd),
1135:
1136: // from internal hardware
1137: .de (1'b0),
1138: .d ('0 ),
1139:
1140: // to internal hardware
1141: .qe (reg2hw.fifo_ctrl.rxrst.qe),
1142: .q (reg2hw.fifo_ctrl.rxrst.q ),
1143:
1144: .qs ()
1145: );
1146:
1147:
1148: // F[txrst]: 1:1
1149: prim_subreg #(
1150: .DW (1),
1151: .SWACCESS("WO"),
1152: .RESVAL (1'h0)
1153: ) u_fifo_ctrl_txrst (
1154: .clk_i (clk_i ),
1155: .rst_ni (rst_ni ),
1156:
1157: // from register interface
1158: .we (fifo_ctrl_txrst_we),
1159: .wd (fifo_ctrl_txrst_wd),
1160:
1161: // from internal hardware
1162: .de (1'b0),
1163: .d ('0 ),
1164:
1165: // to internal hardware
1166: .qe (reg2hw.fifo_ctrl.txrst.qe),
1167: .q (reg2hw.fifo_ctrl.txrst.q ),
1168:
1169: .qs ()
1170: );
1171:
1172:
1173: // F[rxilvl]: 4:2
1174: prim_subreg #(
1175: .DW (3),
1176: .SWACCESS("RW"),
1177: .RESVAL (3'h0)
1178: ) u_fifo_ctrl_rxilvl (
1179: .clk_i (clk_i ),
1180: .rst_ni (rst_ni ),
1181:
1182: // from register interface
1183: .we (fifo_ctrl_rxilvl_we),
1184: .wd (fifo_ctrl_rxilvl_wd),
1185:
1186: // from internal hardware
1187: .de (hw2reg.fifo_ctrl.rxilvl.de),
1188: .d (hw2reg.fifo_ctrl.rxilvl.d ),
1189:
1190: // to internal hardware
1191: .qe (reg2hw.fifo_ctrl.rxilvl.qe),
1192: .q (reg2hw.fifo_ctrl.rxilvl.q ),
1193:
1194: // to register interface (read)
1195: .qs (fifo_ctrl_rxilvl_qs)
1196: );
1197:
1198:
1199: // F[txilvl]: 6:5
1200: prim_subreg #(
1201: .DW (2),
1202: .SWACCESS("RW"),
1203: .RESVAL (2'h0)
1204: ) u_fifo_ctrl_txilvl (
1205: .clk_i (clk_i ),
1206: .rst_ni (rst_ni ),
1207:
1208: // from register interface
1209: .we (fifo_ctrl_txilvl_we),
1210: .wd (fifo_ctrl_txilvl_wd),
1211:
1212: // from internal hardware
1213: .de (hw2reg.fifo_ctrl.txilvl.de),
1214: .d (hw2reg.fifo_ctrl.txilvl.d ),
1215:
1216: // to internal hardware
1217: .qe (reg2hw.fifo_ctrl.txilvl.qe),
1218: .q (reg2hw.fifo_ctrl.txilvl.q ),
1219:
1220: // to register interface (read)
1221: .qs (fifo_ctrl_txilvl_qs)
1222: );
1223:
1224:
1225: // R[fifo_status]: V(True)
1226:
1227: // F[txlvl]: 5:0
1228: prim_subreg_ext #(
1229: .DW (6)
1230: ) u_fifo_status_txlvl (
1231: .re (fifo_status_txlvl_re),
1232: .we (1'b0),
1233: .wd ('0),
1234: .d (hw2reg.fifo_status.txlvl.d),
1235: .qre (),
1236: .qe (),
1237: .q (),
1238: .qs (fifo_status_txlvl_qs)
1239: );
1240:
1241:
1242: // F[rxlvl]: 21:16
1243: prim_subreg_ext #(
1244: .DW (6)
1245: ) u_fifo_status_rxlvl (
1246: .re (fifo_status_rxlvl_re),
1247: .we (1'b0),
1248: .wd ('0),
1249: .d (hw2reg.fifo_status.rxlvl.d),
1250: .qre (),
1251: .qe (),
1252: .q (),
1253: .qs (fifo_status_rxlvl_qs)
1254: );
1255:
1256:
1257: // R[ovrd]: V(False)
1258:
1259: // F[txen]: 0:0
1260: prim_subreg #(
1261: .DW (1),
1262: .SWACCESS("RW"),
1263: .RESVAL (1'h0)
1264: ) u_ovrd_txen (
1265: .clk_i (clk_i ),
1266: .rst_ni (rst_ni ),
1267:
1268: // from register interface
1269: .we (ovrd_txen_we),
1270: .wd (ovrd_txen_wd),
1271:
1272: // from internal hardware
1273: .de (1'b0),
1274: .d ('0 ),
1275:
1276: // to internal hardware
1277: .qe (),
1278: .q (reg2hw.ovrd.txen.q ),
1279:
1280: // to register interface (read)
1281: .qs (ovrd_txen_qs)
1282: );
1283:
1284:
1285: // F[txval]: 1:1
1286: prim_subreg #(
1287: .DW (1),
1288: .SWACCESS("RW"),
1289: .RESVAL (1'h0)
1290: ) u_ovrd_txval (
1291: .clk_i (clk_i ),
1292: .rst_ni (rst_ni ),
1293:
1294: // from register interface
1295: .we (ovrd_txval_we),
1296: .wd (ovrd_txval_wd),
1297:
1298: // from internal hardware
1299: .de (1'b0),
1300: .d ('0 ),
1301:
1302: // to internal hardware
1303: .qe (),
1304: .q (reg2hw.ovrd.txval.q ),
1305:
1306: // to register interface (read)
1307: .qs (ovrd_txval_qs)
1308: );
1309:
1310:
1311: // R[val]: V(True)
1312:
1313: prim_subreg_ext #(
1314: .DW (16)
1315: ) u_val (
1316: .re (val_re),
1317: .we (1'b0),
1318: .wd ('0),
1319: .d (hw2reg.val.d),
1320: .qre (),
1321: .qe (),
1322: .q (),
1323: .qs (val_qs)
1324: );
1325:
1326:
1327: // R[timeout_ctrl]: V(False)
1328:
1329: // F[val]: 23:0
1330: prim_subreg #(
1331: .DW (24),
1332: .SWACCESS("RW"),
1333: .RESVAL (24'h0)
1334: ) u_timeout_ctrl_val (
1335: .clk_i (clk_i ),
1336: .rst_ni (rst_ni ),
1337:
1338: // from register interface
1339: .we (timeout_ctrl_val_we),
1340: .wd (timeout_ctrl_val_wd),
1341:
1342: // from internal hardware
1343: .de (1'b0),
1344: .d ('0 ),
1345:
1346: // to internal hardware
1347: .qe (),
1348: .q (reg2hw.timeout_ctrl.val.q ),
1349:
1350: // to register interface (read)
1351: .qs (timeout_ctrl_val_qs)
1352: );
1353:
1354:
1355: // F[en]: 31:31
1356: prim_subreg #(
1357: .DW (1),
1358: .SWACCESS("RW"),
1359: .RESVAL (1'h0)
1360: ) u_timeout_ctrl_en (
1361: .clk_i (clk_i ),
1362: .rst_ni (rst_ni ),
1363:
1364: // from register interface
1365: .we (timeout_ctrl_en_we),
1366: .wd (timeout_ctrl_en_wd),
1367:
1368: // from internal hardware
1369: .de (1'b0),
1370: .d ('0 ),
1371:
1372: // to internal hardware
1373: .qe (),
1374: .q (reg2hw.timeout_ctrl.en.q ),
1375:
1376: // to register interface (read)
1377: .qs (timeout_ctrl_en_qs)
1378: );
1379:
1380:
1381:
1382:
1383: logic [11:0] addr_hit;
1384: always_comb begin
1385: addr_hit = '0;
1386: addr_hit[ 0] = (reg_addr == UART_INTR_STATE_OFFSET);
1387: addr_hit[ 1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
1388: addr_hit[ 2] = (reg_addr == UART_INTR_TEST_OFFSET);
1389: addr_hit[ 3] = (reg_addr == UART_CTRL_OFFSET);
1390: addr_hit[ 4] = (reg_addr == UART_STATUS_OFFSET);
1391: addr_hit[ 5] = (reg_addr == UART_RDATA_OFFSET);
1392: addr_hit[ 6] = (reg_addr == UART_WDATA_OFFSET);
1393: addr_hit[ 7] = (reg_addr == UART_FIFO_CTRL_OFFSET);
1394: addr_hit[ 8] = (reg_addr == UART_FIFO_STATUS_OFFSET);
1395: addr_hit[ 9] = (reg_addr == UART_OVRD_OFFSET);
1396: addr_hit[10] = (reg_addr == UART_VAL_OFFSET);
1397: addr_hit[11] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
1398: end
1399:
1400: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
1401:
1402: // Check sub-word write is permitted
1403: always_comb begin
1404: wr_err = 1'b0;
1405: if (addr_hit[ 0] && reg_we && (UART_PERMIT[ 0] != (UART_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
1406: if (addr_hit[ 1] && reg_we && (UART_PERMIT[ 1] != (UART_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
1407: if (addr_hit[ 2] && reg_we && (UART_PERMIT[ 2] != (UART_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
1408: if (addr_hit[ 3] && reg_we && (UART_PERMIT[ 3] != (UART_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
1409: if (addr_hit[ 4] && reg_we && (UART_PERMIT[ 4] != (UART_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
1410: if (addr_hit[ 5] && reg_we && (UART_PERMIT[ 5] != (UART_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
1411: if (addr_hit[ 6] && reg_we && (UART_PERMIT[ 6] != (UART_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
1412: if (addr_hit[ 7] && reg_we && (UART_PERMIT[ 7] != (UART_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
1413: if (addr_hit[ 8] && reg_we && (UART_PERMIT[ 8] != (UART_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
1414: if (addr_hit[ 9] && reg_we && (UART_PERMIT[ 9] != (UART_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
1415: if (addr_hit[10] && reg_we && (UART_PERMIT[10] != (UART_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
1416: if (addr_hit[11] && reg_we && (UART_PERMIT[11] != (UART_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
1417: end
1418:
1419: assign intr_state_tx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
1420: assign intr_state_tx_watermark_wd = reg_wdata[0];
1421:
1422: assign intr_state_rx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
1423: assign intr_state_rx_watermark_wd = reg_wdata[1];
1424:
1425: assign intr_state_tx_empty_we = addr_hit[0] & reg_we & ~wr_err;
1426: assign intr_state_tx_empty_wd = reg_wdata[2];
1427:
1428: assign intr_state_rx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
1429: assign intr_state_rx_overflow_wd = reg_wdata[3];
1430:
1431: assign intr_state_rx_frame_err_we = addr_hit[0] & reg_we & ~wr_err;
1432: assign intr_state_rx_frame_err_wd = reg_wdata[4];
1433:
1434: assign intr_state_rx_break_err_we = addr_hit[0] & reg_we & ~wr_err;
1435: assign intr_state_rx_break_err_wd = reg_wdata[5];
1436:
1437: assign intr_state_rx_timeout_we = addr_hit[0] & reg_we & ~wr_err;
1438: assign intr_state_rx_timeout_wd = reg_wdata[6];
1439:
1440: assign intr_state_rx_parity_err_we = addr_hit[0] & reg_we & ~wr_err;
1441: assign intr_state_rx_parity_err_wd = reg_wdata[7];
1442:
1443: assign intr_enable_tx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
1444: assign intr_enable_tx_watermark_wd = reg_wdata[0];
1445:
1446: assign intr_enable_rx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
1447: assign intr_enable_rx_watermark_wd = reg_wdata[1];
1448:
1449: assign intr_enable_tx_empty_we = addr_hit[1] & reg_we & ~wr_err;
1450: assign intr_enable_tx_empty_wd = reg_wdata[2];
1451:
1452: assign intr_enable_rx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
1453: assign intr_enable_rx_overflow_wd = reg_wdata[3];
1454:
1455: assign intr_enable_rx_frame_err_we = addr_hit[1] & reg_we & ~wr_err;
1456: assign intr_enable_rx_frame_err_wd = reg_wdata[4];
1457:
1458: assign intr_enable_rx_break_err_we = addr_hit[1] & reg_we & ~wr_err;
1459: assign intr_enable_rx_break_err_wd = reg_wdata[5];
1460:
1461: assign intr_enable_rx_timeout_we = addr_hit[1] & reg_we & ~wr_err;
1462: assign intr_enable_rx_timeout_wd = reg_wdata[6];
1463:
1464: assign intr_enable_rx_parity_err_we = addr_hit[1] & reg_we & ~wr_err;
1465: assign intr_enable_rx_parity_err_wd = reg_wdata[7];
1466:
1467: assign intr_test_tx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
1468: assign intr_test_tx_watermark_wd = reg_wdata[0];
1469:
1470: assign intr_test_rx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
1471: assign intr_test_rx_watermark_wd = reg_wdata[1];
1472:
1473: assign intr_test_tx_empty_we = addr_hit[2] & reg_we & ~wr_err;
1474: assign intr_test_tx_empty_wd = reg_wdata[2];
1475:
1476: assign intr_test_rx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
1477: assign intr_test_rx_overflow_wd = reg_wdata[3];
1478:
1479: assign intr_test_rx_frame_err_we = addr_hit[2] & reg_we & ~wr_err;
1480: assign intr_test_rx_frame_err_wd = reg_wdata[4];
1481:
1482: assign intr_test_rx_break_err_we = addr_hit[2] & reg_we & ~wr_err;
1483: assign intr_test_rx_break_err_wd = reg_wdata[5];
1484:
1485: assign intr_test_rx_timeout_we = addr_hit[2] & reg_we & ~wr_err;
1486: assign intr_test_rx_timeout_wd = reg_wdata[6];
1487:
1488: assign intr_test_rx_parity_err_we = addr_hit[2] & reg_we & ~wr_err;
1489: assign intr_test_rx_parity_err_wd = reg_wdata[7];
1490:
1491: assign ctrl_tx_we = addr_hit[3] & reg_we & ~wr_err;
1492: assign ctrl_tx_wd = reg_wdata[0];
1493:
1494: assign ctrl_rx_we = addr_hit[3] & reg_we & ~wr_err;
1495: assign ctrl_rx_wd = reg_wdata[1];
1496:
1497: assign ctrl_nf_we = addr_hit[3] & reg_we & ~wr_err;
1498: assign ctrl_nf_wd = reg_wdata[2];
1499:
1500: assign ctrl_slpbk_we = addr_hit[3] & reg_we & ~wr_err;
1501: assign ctrl_slpbk_wd = reg_wdata[4];
1502:
1503: assign ctrl_llpbk_we = addr_hit[3] & reg_we & ~wr_err;
1504: assign ctrl_llpbk_wd = reg_wdata[5];
1505:
1506: assign ctrl_parity_en_we = addr_hit[3] & reg_we & ~wr_err;
1507: assign ctrl_parity_en_wd = reg_wdata[6];
1508:
1509: assign ctrl_parity_odd_we = addr_hit[3] & reg_we & ~wr_err;
1510: assign ctrl_parity_odd_wd = reg_wdata[7];
1511:
1512: assign ctrl_rxblvl_we = addr_hit[3] & reg_we & ~wr_err;
1513: assign ctrl_rxblvl_wd = reg_wdata[9:8];
1514:
1515: assign ctrl_nco_we = addr_hit[3] & reg_we & ~wr_err;
1516: assign ctrl_nco_wd = reg_wdata[31:16];
1517:
1518: assign status_txfull_re = addr_hit[4] && reg_re;
1519:
1520: assign status_rxfull_re = addr_hit[4] && reg_re;
1521:
1522: assign status_txempty_re = addr_hit[4] && reg_re;
1523:
1524: assign status_txidle_re = addr_hit[4] && reg_re;
1525:
1526: assign status_rxidle_re = addr_hit[4] && reg_re;
1527:
1528: assign status_rxempty_re = addr_hit[4] && reg_re;
1529:
1530: assign rdata_re = addr_hit[5] && reg_re;
1531:
1532: assign wdata_we = addr_hit[6] & reg_we & ~wr_err;
1533: assign wdata_wd = reg_wdata[7:0];
1534:
1535: assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & ~wr_err;
1536: assign fifo_ctrl_rxrst_wd = reg_wdata[0];
1537:
1538: assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & ~wr_err;
1539: assign fifo_ctrl_txrst_wd = reg_wdata[1];
1540:
1541: assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & ~wr_err;
1542: assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
1543:
1544: assign fifo_ctrl_txilvl_we = addr_hit[7] & reg_we & ~wr_err;
1545: assign fifo_ctrl_txilvl_wd = reg_wdata[6:5];
1546:
1547: assign fifo_status_txlvl_re = addr_hit[8] && reg_re;
1548:
1549: assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
1550:
1551: assign ovrd_txen_we = addr_hit[9] & reg_we & ~wr_err;
1552: assign ovrd_txen_wd = reg_wdata[0];
1553:
1554: assign ovrd_txval_we = addr_hit[9] & reg_we & ~wr_err;
1555: assign ovrd_txval_wd = reg_wdata[1];
1556:
1557: assign val_re = addr_hit[10] && reg_re;
1558:
1559: assign timeout_ctrl_val_we = addr_hit[11] & reg_we & ~wr_err;
1560: assign timeout_ctrl_val_wd = reg_wdata[23:0];
1561:
1562: assign timeout_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
1563: assign timeout_ctrl_en_wd = reg_wdata[31];
1564:
1565: // Read data return
1566: always_comb begin
1567: reg_rdata_next = '0;
1568: unique case (1'b1)
1569: addr_hit[0]: begin
1570: reg_rdata_next[0] = intr_state_tx_watermark_qs;
1571: reg_rdata_next[1] = intr_state_rx_watermark_qs;
1572: reg_rdata_next[2] = intr_state_tx_empty_qs;
1573: reg_rdata_next[3] = intr_state_rx_overflow_qs;
1574: reg_rdata_next[4] = intr_state_rx_frame_err_qs;
1575: reg_rdata_next[5] = intr_state_rx_break_err_qs;
1576: reg_rdata_next[6] = intr_state_rx_timeout_qs;
1577: reg_rdata_next[7] = intr_state_rx_parity_err_qs;
1578: end
1579:
1580: addr_hit[1]: begin
1581: reg_rdata_next[0] = intr_enable_tx_watermark_qs;
1582: reg_rdata_next[1] = intr_enable_rx_watermark_qs;
1583: reg_rdata_next[2] = intr_enable_tx_empty_qs;
1584: reg_rdata_next[3] = intr_enable_rx_overflow_qs;
1585: reg_rdata_next[4] = intr_enable_rx_frame_err_qs;
1586: reg_rdata_next[5] = intr_enable_rx_break_err_qs;
1587: reg_rdata_next[6] = intr_enable_rx_timeout_qs;
1588: reg_rdata_next[7] = intr_enable_rx_parity_err_qs;
1589: end
1590:
1591: addr_hit[2]: begin
1592: reg_rdata_next[0] = '0;
1593: reg_rdata_next[1] = '0;
1594: reg_rdata_next[2] = '0;
1595: reg_rdata_next[3] = '0;
1596: reg_rdata_next[4] = '0;
1597: reg_rdata_next[5] = '0;
1598: reg_rdata_next[6] = '0;
1599: reg_rdata_next[7] = '0;
1600: end
1601:
1602: addr_hit[3]: begin
1603: reg_rdata_next[0] = ctrl_tx_qs;
1604: reg_rdata_next[1] = ctrl_rx_qs;
1605: reg_rdata_next[2] = ctrl_nf_qs;
1606: reg_rdata_next[4] = ctrl_slpbk_qs;
1607: reg_rdata_next[5] = ctrl_llpbk_qs;
1608: reg_rdata_next[6] = ctrl_parity_en_qs;
1609: reg_rdata_next[7] = ctrl_parity_odd_qs;
1610: reg_rdata_next[9:8] = ctrl_rxblvl_qs;
1611: reg_rdata_next[31:16] = ctrl_nco_qs;
1612: end
1613:
1614: addr_hit[4]: begin
1615: reg_rdata_next[0] = status_txfull_qs;
1616: reg_rdata_next[1] = status_rxfull_qs;
1617: reg_rdata_next[2] = status_txempty_qs;
1618: reg_rdata_next[3] = status_txidle_qs;
1619: reg_rdata_next[4] = status_rxidle_qs;
1620: reg_rdata_next[5] = status_rxempty_qs;
1621: end
1622:
1623: addr_hit[5]: begin
1624: reg_rdata_next[7:0] = rdata_qs;
1625: end
1626:
1627: addr_hit[6]: begin
1628: reg_rdata_next[7:0] = '0;
1629: end
1630:
1631: addr_hit[7]: begin
1632: reg_rdata_next[0] = '0;
1633: reg_rdata_next[1] = '0;
1634: reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
1635: reg_rdata_next[6:5] = fifo_ctrl_txilvl_qs;
1636: end
1637:
1638: addr_hit[8]: begin
1639: reg_rdata_next[5:0] = fifo_status_txlvl_qs;
1640: reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
1641: end
1642:
1643: addr_hit[9]: begin
1644: reg_rdata_next[0] = ovrd_txen_qs;
1645: reg_rdata_next[1] = ovrd_txval_qs;
1646: end
1647:
1648: addr_hit[10]: begin
1649: reg_rdata_next[15:0] = val_qs;
1650: end
1651:
1652: addr_hit[11]: begin
1653: reg_rdata_next[23:0] = timeout_ctrl_val_qs;
1654: reg_rdata_next[31] = timeout_ctrl_en_qs;
1655: end
1656:
1657: default: begin
1658: reg_rdata_next = '1;
1659: end
1660: endcase
1661: end
1662:
1663: // Assertions for Register Interface
1664: `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
1665: `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
1666:
1667: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
1668:
1669: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
1670:
1671: // this is formulated as an assumption such that the FPV testbenches do disprove this
1672: // property by mistake
1673: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
1674:
1675: endmodule
1676: