../src/lowrisc_ip_aes_0.6/rtl/aes_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module aes_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16: // To HW
17: output aes_reg_pkg::aes_reg2hw_t reg2hw, // Write
18: input aes_reg_pkg::aes_hw2reg_t hw2reg, // Read
19:
20: // Config
21: input devmode_i // If 1, explicit error return for unmapped register access
22: );
23:
24: import aes_reg_pkg::* ;
25:
26: localparam int AW = 7;
27: localparam int DW = 32;
28: localparam int DBW = DW/8; // Byte Width
29:
30: // register signals
31: logic reg_we;
32: logic reg_re;
33: logic [AW-1:0] reg_addr;
34: logic [DW-1:0] reg_wdata;
35: logic [DBW-1:0] reg_be;
36: logic [DW-1:0] reg_rdata;
37: logic reg_error;
38:
39: logic addrmiss, wr_err;
40:
41: logic [DW-1:0] reg_rdata_next;
42:
43: tlul_pkg::tl_h2d_t tl_reg_h2d;
44: tlul_pkg::tl_d2h_t tl_reg_d2h;
45:
46: assign tl_reg_h2d = tl_i;
47: assign tl_o = tl_reg_d2h;
48:
49: tlul_adapter_reg #(
50: .RegAw(AW),
51: .RegDw(DW)
52: ) u_reg_if (
53: .clk_i,
54: .rst_ni,
55:
56: .tl_i (tl_reg_h2d),
57: .tl_o (tl_reg_d2h),
58:
59: .we_o (reg_we),
60: .re_o (reg_re),
61: .addr_o (reg_addr),
62: .wdata_o (reg_wdata),
63: .be_o (reg_be),
64: .rdata_i (reg_rdata),
65: .error_i (reg_error)
66: );
67:
68: assign reg_rdata = reg_rdata_next ;
69: assign reg_error = (devmode_i & addrmiss) | wr_err ;
70:
71: // Define SW related signals
72: // Format: __{wd|we|qs}
73: // or _{wd|we|qs} if field == 1 or 0
74: logic [31:0] key0_wd;
75: logic key0_we;
76: logic [31:0] key1_wd;
77: logic key1_we;
78: logic [31:0] key2_wd;
79: logic key2_we;
80: logic [31:0] key3_wd;
81: logic key3_we;
82: logic [31:0] key4_wd;
83: logic key4_we;
84: logic [31:0] key5_wd;
85: logic key5_we;
86: logic [31:0] key6_wd;
87: logic key6_we;
88: logic [31:0] key7_wd;
89: logic key7_we;
90: logic [31:0] iv0_wd;
91: logic iv0_we;
92: logic [31:0] iv1_wd;
93: logic iv1_we;
94: logic [31:0] iv2_wd;
95: logic iv2_we;
96: logic [31:0] iv3_wd;
97: logic iv3_we;
98: logic [31:0] data_in0_wd;
99: logic data_in0_we;
100: logic [31:0] data_in1_wd;
101: logic data_in1_we;
102: logic [31:0] data_in2_wd;
103: logic data_in2_we;
104: logic [31:0] data_in3_wd;
105: logic data_in3_we;
106: logic [31:0] data_out0_qs;
107: logic data_out0_re;
108: logic [31:0] data_out1_qs;
109: logic data_out1_re;
110: logic [31:0] data_out2_qs;
111: logic data_out2_re;
112: logic [31:0] data_out3_qs;
113: logic data_out3_re;
114: logic ctrl_operation_qs;
115: logic ctrl_operation_wd;
116: logic ctrl_operation_we;
117: logic ctrl_operation_re;
118: logic [2:0] ctrl_mode_qs;
119: logic [2:0] ctrl_mode_wd;
120: logic ctrl_mode_we;
121: logic ctrl_mode_re;
122: logic [2:0] ctrl_key_len_qs;
123: logic [2:0] ctrl_key_len_wd;
124: logic ctrl_key_len_we;
125: logic ctrl_key_len_re;
126: logic ctrl_manual_operation_qs;
127: logic ctrl_manual_operation_wd;
128: logic ctrl_manual_operation_we;
129: logic ctrl_manual_operation_re;
130: logic trigger_start_wd;
131: logic trigger_start_we;
132: logic trigger_key_clear_wd;
133: logic trigger_key_clear_we;
134: logic trigger_iv_clear_wd;
135: logic trigger_iv_clear_we;
136: logic trigger_data_in_clear_wd;
137: logic trigger_data_in_clear_we;
138: logic trigger_data_out_clear_wd;
139: logic trigger_data_out_clear_we;
140: logic trigger_prng_reseed_wd;
141: logic trigger_prng_reseed_we;
142: logic status_idle_qs;
143: logic status_stall_qs;
144: logic status_output_valid_qs;
145: logic status_input_ready_qs;
146:
147: // Register instances
148:
149: // Subregister 0 of Multireg key
150: // R[key0]: V(True)
151:
152: prim_subreg_ext #(
153: .DW (32)
154: ) u_key0 (
155: .re (1'b0),
156: .we (key0_we),
157: .wd (key0_wd),
158: .d (hw2reg.key[0].d),
159: .qre (),
160: .qe (reg2hw.key[0].qe),
161: .q (reg2hw.key[0].q ),
162: .qs ()
163: );
164:
165: // Subregister 1 of Multireg key
166: // R[key1]: V(True)
167:
168: prim_subreg_ext #(
169: .DW (32)
170: ) u_key1 (
171: .re (1'b0),
172: .we (key1_we),
173: .wd (key1_wd),
174: .d (hw2reg.key[1].d),
175: .qre (),
176: .qe (reg2hw.key[1].qe),
177: .q (reg2hw.key[1].q ),
178: .qs ()
179: );
180:
181: // Subregister 2 of Multireg key
182: // R[key2]: V(True)
183:
184: prim_subreg_ext #(
185: .DW (32)
186: ) u_key2 (
187: .re (1'b0),
188: .we (key2_we),
189: .wd (key2_wd),
190: .d (hw2reg.key[2].d),
191: .qre (),
192: .qe (reg2hw.key[2].qe),
193: .q (reg2hw.key[2].q ),
194: .qs ()
195: );
196:
197: // Subregister 3 of Multireg key
198: // R[key3]: V(True)
199:
200: prim_subreg_ext #(
201: .DW (32)
202: ) u_key3 (
203: .re (1'b0),
204: .we (key3_we),
205: .wd (key3_wd),
206: .d (hw2reg.key[3].d),
207: .qre (),
208: .qe (reg2hw.key[3].qe),
209: .q (reg2hw.key[3].q ),
210: .qs ()
211: );
212:
213: // Subregister 4 of Multireg key
214: // R[key4]: V(True)
215:
216: prim_subreg_ext #(
217: .DW (32)
218: ) u_key4 (
219: .re (1'b0),
220: .we (key4_we),
221: .wd (key4_wd),
222: .d (hw2reg.key[4].d),
223: .qre (),
224: .qe (reg2hw.key[4].qe),
225: .q (reg2hw.key[4].q ),
226: .qs ()
227: );
228:
229: // Subregister 5 of Multireg key
230: // R[key5]: V(True)
231:
232: prim_subreg_ext #(
233: .DW (32)
234: ) u_key5 (
235: .re (1'b0),
236: .we (key5_we),
237: .wd (key5_wd),
238: .d (hw2reg.key[5].d),
239: .qre (),
240: .qe (reg2hw.key[5].qe),
241: .q (reg2hw.key[5].q ),
242: .qs ()
243: );
244:
245: // Subregister 6 of Multireg key
246: // R[key6]: V(True)
247:
248: prim_subreg_ext #(
249: .DW (32)
250: ) u_key6 (
251: .re (1'b0),
252: .we (key6_we),
253: .wd (key6_wd),
254: .d (hw2reg.key[6].d),
255: .qre (),
256: .qe (reg2hw.key[6].qe),
257: .q (reg2hw.key[6].q ),
258: .qs ()
259: );
260:
261: // Subregister 7 of Multireg key
262: // R[key7]: V(True)
263:
264: prim_subreg_ext #(
265: .DW (32)
266: ) u_key7 (
267: .re (1'b0),
268: .we (key7_we),
269: .wd (key7_wd),
270: .d (hw2reg.key[7].d),
271: .qre (),
272: .qe (reg2hw.key[7].qe),
273: .q (reg2hw.key[7].q ),
274: .qs ()
275: );
276:
277:
278:
279: // Subregister 0 of Multireg iv
280: // R[iv0]: V(True)
281:
282: prim_subreg_ext #(
283: .DW (32)
284: ) u_iv0 (
285: .re (1'b0),
286: .we (iv0_we),
287: .wd (iv0_wd),
288: .d (hw2reg.iv[0].d),
289: .qre (),
290: .qe (reg2hw.iv[0].qe),
291: .q (reg2hw.iv[0].q ),
292: .qs ()
293: );
294:
295: // Subregister 1 of Multireg iv
296: // R[iv1]: V(True)
297:
298: prim_subreg_ext #(
299: .DW (32)
300: ) u_iv1 (
301: .re (1'b0),
302: .we (iv1_we),
303: .wd (iv1_wd),
304: .d (hw2reg.iv[1].d),
305: .qre (),
306: .qe (reg2hw.iv[1].qe),
307: .q (reg2hw.iv[1].q ),
308: .qs ()
309: );
310:
311: // Subregister 2 of Multireg iv
312: // R[iv2]: V(True)
313:
314: prim_subreg_ext #(
315: .DW (32)
316: ) u_iv2 (
317: .re (1'b0),
318: .we (iv2_we),
319: .wd (iv2_wd),
320: .d (hw2reg.iv[2].d),
321: .qre (),
322: .qe (reg2hw.iv[2].qe),
323: .q (reg2hw.iv[2].q ),
324: .qs ()
325: );
326:
327: // Subregister 3 of Multireg iv
328: // R[iv3]: V(True)
329:
330: prim_subreg_ext #(
331: .DW (32)
332: ) u_iv3 (
333: .re (1'b0),
334: .we (iv3_we),
335: .wd (iv3_wd),
336: .d (hw2reg.iv[3].d),
337: .qre (),
338: .qe (reg2hw.iv[3].qe),
339: .q (reg2hw.iv[3].q ),
340: .qs ()
341: );
342:
343:
344:
345: // Subregister 0 of Multireg data_in
346: // R[data_in0]: V(False)
347:
348: prim_subreg #(
349: .DW (32),
350: .SWACCESS("WO"),
351: .RESVAL (32'h0)
352: ) u_data_in0 (
353: .clk_i (clk_i ),
354: .rst_ni (rst_ni ),
355:
356: // from register interface
357: .we (data_in0_we),
358: .wd (data_in0_wd),
359:
360: // from internal hardware
361: .de (hw2reg.data_in[0].de),
362: .d (hw2reg.data_in[0].d ),
363:
364: // to internal hardware
365: .qe (reg2hw.data_in[0].qe),
366: .q (reg2hw.data_in[0].q ),
367:
368: .qs ()
369: );
370:
371: // Subregister 1 of Multireg data_in
372: // R[data_in1]: V(False)
373:
374: prim_subreg #(
375: .DW (32),
376: .SWACCESS("WO"),
377: .RESVAL (32'h0)
378: ) u_data_in1 (
379: .clk_i (clk_i ),
380: .rst_ni (rst_ni ),
381:
382: // from register interface
383: .we (data_in1_we),
384: .wd (data_in1_wd),
385:
386: // from internal hardware
387: .de (hw2reg.data_in[1].de),
388: .d (hw2reg.data_in[1].d ),
389:
390: // to internal hardware
391: .qe (reg2hw.data_in[1].qe),
392: .q (reg2hw.data_in[1].q ),
393:
394: .qs ()
395: );
396:
397: // Subregister 2 of Multireg data_in
398: // R[data_in2]: V(False)
399:
400: prim_subreg #(
401: .DW (32),
402: .SWACCESS("WO"),
403: .RESVAL (32'h0)
404: ) u_data_in2 (
405: .clk_i (clk_i ),
406: .rst_ni (rst_ni ),
407:
408: // from register interface
409: .we (data_in2_we),
410: .wd (data_in2_wd),
411:
412: // from internal hardware
413: .de (hw2reg.data_in[2].de),
414: .d (hw2reg.data_in[2].d ),
415:
416: // to internal hardware
417: .qe (reg2hw.data_in[2].qe),
418: .q (reg2hw.data_in[2].q ),
419:
420: .qs ()
421: );
422:
423: // Subregister 3 of Multireg data_in
424: // R[data_in3]: V(False)
425:
426: prim_subreg #(
427: .DW (32),
428: .SWACCESS("WO"),
429: .RESVAL (32'h0)
430: ) u_data_in3 (
431: .clk_i (clk_i ),
432: .rst_ni (rst_ni ),
433:
434: // from register interface
435: .we (data_in3_we),
436: .wd (data_in3_wd),
437:
438: // from internal hardware
439: .de (hw2reg.data_in[3].de),
440: .d (hw2reg.data_in[3].d ),
441:
442: // to internal hardware
443: .qe (reg2hw.data_in[3].qe),
444: .q (reg2hw.data_in[3].q ),
445:
446: .qs ()
447: );
448:
449:
450:
451: // Subregister 0 of Multireg data_out
452: // R[data_out0]: V(True)
453:
454: prim_subreg_ext #(
455: .DW (32)
456: ) u_data_out0 (
457: .re (data_out0_re),
458: .we (1'b0),
459: .wd ('0),
460: .d (hw2reg.data_out[0].d),
461: .qre (reg2hw.data_out[0].re),
462: .qe (),
463: .q (reg2hw.data_out[0].q ),
464: .qs (data_out0_qs)
465: );
466:
467: // Subregister 1 of Multireg data_out
468: // R[data_out1]: V(True)
469:
470: prim_subreg_ext #(
471: .DW (32)
472: ) u_data_out1 (
473: .re (data_out1_re),
474: .we (1'b0),
475: .wd ('0),
476: .d (hw2reg.data_out[1].d),
477: .qre (reg2hw.data_out[1].re),
478: .qe (),
479: .q (reg2hw.data_out[1].q ),
480: .qs (data_out1_qs)
481: );
482:
483: // Subregister 2 of Multireg data_out
484: // R[data_out2]: V(True)
485:
486: prim_subreg_ext #(
487: .DW (32)
488: ) u_data_out2 (
489: .re (data_out2_re),
490: .we (1'b0),
491: .wd ('0),
492: .d (hw2reg.data_out[2].d),
493: .qre (reg2hw.data_out[2].re),
494: .qe (),
495: .q (reg2hw.data_out[2].q ),
496: .qs (data_out2_qs)
497: );
498:
499: // Subregister 3 of Multireg data_out
500: // R[data_out3]: V(True)
501:
502: prim_subreg_ext #(
503: .DW (32)
504: ) u_data_out3 (
505: .re (data_out3_re),
506: .we (1'b0),
507: .wd ('0),
508: .d (hw2reg.data_out[3].d),
509: .qre (reg2hw.data_out[3].re),
510: .qe (),
511: .q (reg2hw.data_out[3].q ),
512: .qs (data_out3_qs)
513: );
514:
515:
516: // R[ctrl]: V(True)
517:
518: // F[operation]: 0:0
519: prim_subreg_ext #(
520: .DW (1)
521: ) u_ctrl_operation (
522: .re (ctrl_operation_re),
523: .we (ctrl_operation_we),
524: .wd (ctrl_operation_wd),
525: .d (hw2reg.ctrl.operation.d),
526: .qre (),
527: .qe (reg2hw.ctrl.operation.qe),
528: .q (reg2hw.ctrl.operation.q ),
529: .qs (ctrl_operation_qs)
530: );
531:
532:
533: // F[mode]: 3:1
534: prim_subreg_ext #(
535: .DW (3)
536: ) u_ctrl_mode (
537: .re (ctrl_mode_re),
538: .we (ctrl_mode_we),
539: .wd (ctrl_mode_wd),
540: .d (hw2reg.ctrl.mode.d),
541: .qre (),
542: .qe (reg2hw.ctrl.mode.qe),
543: .q (reg2hw.ctrl.mode.q ),
544: .qs (ctrl_mode_qs)
545: );
546:
547:
548: // F[key_len]: 6:4
549: prim_subreg_ext #(
550: .DW (3)
551: ) u_ctrl_key_len (
552: .re (ctrl_key_len_re),
553: .we (ctrl_key_len_we),
554: .wd (ctrl_key_len_wd),
555: .d (hw2reg.ctrl.key_len.d),
556: .qre (),
557: .qe (reg2hw.ctrl.key_len.qe),
558: .q (reg2hw.ctrl.key_len.q ),
559: .qs (ctrl_key_len_qs)
560: );
561:
562:
563: // F[manual_operation]: 7:7
564: prim_subreg_ext #(
565: .DW (1)
566: ) u_ctrl_manual_operation (
567: .re (ctrl_manual_operation_re),
568: .we (ctrl_manual_operation_we),
569: .wd (ctrl_manual_operation_wd),
570: .d (hw2reg.ctrl.manual_operation.d),
571: .qre (),
572: .qe (reg2hw.ctrl.manual_operation.qe),
573: .q (reg2hw.ctrl.manual_operation.q ),
574: .qs (ctrl_manual_operation_qs)
575: );
576:
577:
578: // R[trigger]: V(False)
579:
580: // F[start]: 0:0
581: prim_subreg #(
582: .DW (1),
583: .SWACCESS("WO"),
584: .RESVAL (1'h0)
585: ) u_trigger_start (
586: .clk_i (clk_i ),
587: .rst_ni (rst_ni ),
588:
589: // from register interface
590: .we (trigger_start_we),
591: .wd (trigger_start_wd),
592:
593: // from internal hardware
594: .de (hw2reg.trigger.start.de),
595: .d (hw2reg.trigger.start.d ),
596:
597: // to internal hardware
598: .qe (),
599: .q (reg2hw.trigger.start.q ),
600:
601: .qs ()
602: );
603:
604:
605: // F[key_clear]: 1:1
606: prim_subreg #(
607: .DW (1),
608: .SWACCESS("WO"),
609: .RESVAL (1'h1)
610: ) u_trigger_key_clear (
611: .clk_i (clk_i ),
612: .rst_ni (rst_ni ),
613:
614: // from register interface
615: .we (trigger_key_clear_we),
616: .wd (trigger_key_clear_wd),
617:
618: // from internal hardware
619: .de (hw2reg.trigger.key_clear.de),
620: .d (hw2reg.trigger.key_clear.d ),
621:
622: // to internal hardware
623: .qe (),
624: .q (reg2hw.trigger.key_clear.q ),
625:
626: .qs ()
627: );
628:
629:
630: // F[iv_clear]: 2:2
631: prim_subreg #(
632: .DW (1),
633: .SWACCESS("WO"),
634: .RESVAL (1'h1)
635: ) u_trigger_iv_clear (
636: .clk_i (clk_i ),
637: .rst_ni (rst_ni ),
638:
639: // from register interface
640: .we (trigger_iv_clear_we),
641: .wd (trigger_iv_clear_wd),
642:
643: // from internal hardware
644: .de (hw2reg.trigger.iv_clear.de),
645: .d (hw2reg.trigger.iv_clear.d ),
646:
647: // to internal hardware
648: .qe (),
649: .q (reg2hw.trigger.iv_clear.q ),
650:
651: .qs ()
652: );
653:
654:
655: // F[data_in_clear]: 3:3
656: prim_subreg #(
657: .DW (1),
658: .SWACCESS("WO"),
659: .RESVAL (1'h1)
660: ) u_trigger_data_in_clear (
661: .clk_i (clk_i ),
662: .rst_ni (rst_ni ),
663:
664: // from register interface
665: .we (trigger_data_in_clear_we),
666: .wd (trigger_data_in_clear_wd),
667:
668: // from internal hardware
669: .de (hw2reg.trigger.data_in_clear.de),
670: .d (hw2reg.trigger.data_in_clear.d ),
671:
672: // to internal hardware
673: .qe (),
674: .q (reg2hw.trigger.data_in_clear.q ),
675:
676: .qs ()
677: );
678:
679:
680: // F[data_out_clear]: 4:4
681: prim_subreg #(
682: .DW (1),
683: .SWACCESS("WO"),
684: .RESVAL (1'h1)
685: ) u_trigger_data_out_clear (
686: .clk_i (clk_i ),
687: .rst_ni (rst_ni ),
688:
689: // from register interface
690: .we (trigger_data_out_clear_we),
691: .wd (trigger_data_out_clear_wd),
692:
693: // from internal hardware
694: .de (hw2reg.trigger.data_out_clear.de),
695: .d (hw2reg.trigger.data_out_clear.d ),
696:
697: // to internal hardware
698: .qe (),
699: .q (reg2hw.trigger.data_out_clear.q ),
700:
701: .qs ()
702: );
703:
704:
705: // F[prng_reseed]: 5:5
706: prim_subreg #(
707: .DW (1),
708: .SWACCESS("WO"),
709: .RESVAL (1'h1)
710: ) u_trigger_prng_reseed (
711: .clk_i (clk_i ),
712: .rst_ni (rst_ni ),
713:
714: // from register interface
715: .we (trigger_prng_reseed_we),
716: .wd (trigger_prng_reseed_wd),
717:
718: // from internal hardware
719: .de (hw2reg.trigger.prng_reseed.de),
720: .d (hw2reg.trigger.prng_reseed.d ),
721:
722: // to internal hardware
723: .qe (),
724: .q (reg2hw.trigger.prng_reseed.q ),
725:
726: .qs ()
727: );
728:
729:
730: // R[status]: V(False)
731:
732: // F[idle]: 0:0
733: prim_subreg #(
734: .DW (1),
735: .SWACCESS("RO"),
736: .RESVAL (1'h1)
737: ) u_status_idle (
738: .clk_i (clk_i ),
739: .rst_ni (rst_ni ),
740:
741: .we (1'b0),
742: .wd ('0 ),
743:
744: // from internal hardware
745: .de (hw2reg.status.idle.de),
746: .d (hw2reg.status.idle.d ),
747:
748: // to internal hardware
749: .qe (),
750: .q (),
751:
752: // to register interface (read)
753: .qs (status_idle_qs)
754: );
755:
756:
757: // F[stall]: 1:1
758: prim_subreg #(
759: .DW (1),
760: .SWACCESS("RO"),
761: .RESVAL (1'h0)
762: ) u_status_stall (
763: .clk_i (clk_i ),
764: .rst_ni (rst_ni ),
765:
766: .we (1'b0),
767: .wd ('0 ),
768:
769: // from internal hardware
770: .de (hw2reg.status.stall.de),
771: .d (hw2reg.status.stall.d ),
772:
773: // to internal hardware
774: .qe (),
775: .q (),
776:
777: // to register interface (read)
778: .qs (status_stall_qs)
779: );
780:
781:
782: // F[output_valid]: 2:2
783: prim_subreg #(
784: .DW (1),
785: .SWACCESS("RO"),
786: .RESVAL (1'h0)
787: ) u_status_output_valid (
788: .clk_i (clk_i ),
789: .rst_ni (rst_ni ),
790:
791: .we (1'b0),
792: .wd ('0 ),
793:
794: // from internal hardware
795: .de (hw2reg.status.output_valid.de),
796: .d (hw2reg.status.output_valid.d ),
797:
798: // to internal hardware
799: .qe (),
800: .q (),
801:
802: // to register interface (read)
803: .qs (status_output_valid_qs)
804: );
805:
806:
807: // F[input_ready]: 3:3
808: prim_subreg #(
809: .DW (1),
810: .SWACCESS("RO"),
811: .RESVAL (1'h1)
812: ) u_status_input_ready (
813: .clk_i (clk_i ),
814: .rst_ni (rst_ni ),
815:
816: .we (1'b0),
817: .wd ('0 ),
818:
819: // from internal hardware
820: .de (hw2reg.status.input_ready.de),
821: .d (hw2reg.status.input_ready.d ),
822:
823: // to internal hardware
824: .qe (),
825: .q (),
826:
827: // to register interface (read)
828: .qs (status_input_ready_qs)
829: );
830:
831:
832:
833:
834: logic [22:0] addr_hit;
835: always_comb begin
836: addr_hit = '0;
837: addr_hit[ 0] = (reg_addr == AES_KEY0_OFFSET);
838: addr_hit[ 1] = (reg_addr == AES_KEY1_OFFSET);
839: addr_hit[ 2] = (reg_addr == AES_KEY2_OFFSET);
840: addr_hit[ 3] = (reg_addr == AES_KEY3_OFFSET);
841: addr_hit[ 4] = (reg_addr == AES_KEY4_OFFSET);
842: addr_hit[ 5] = (reg_addr == AES_KEY5_OFFSET);
843: addr_hit[ 6] = (reg_addr == AES_KEY6_OFFSET);
844: addr_hit[ 7] = (reg_addr == AES_KEY7_OFFSET);
845: addr_hit[ 8] = (reg_addr == AES_IV0_OFFSET);
846: addr_hit[ 9] = (reg_addr == AES_IV1_OFFSET);
847: addr_hit[10] = (reg_addr == AES_IV2_OFFSET);
848: addr_hit[11] = (reg_addr == AES_IV3_OFFSET);
849: addr_hit[12] = (reg_addr == AES_DATA_IN0_OFFSET);
850: addr_hit[13] = (reg_addr == AES_DATA_IN1_OFFSET);
851: addr_hit[14] = (reg_addr == AES_DATA_IN2_OFFSET);
852: addr_hit[15] = (reg_addr == AES_DATA_IN3_OFFSET);
853: addr_hit[16] = (reg_addr == AES_DATA_OUT0_OFFSET);
854: addr_hit[17] = (reg_addr == AES_DATA_OUT1_OFFSET);
855: addr_hit[18] = (reg_addr == AES_DATA_OUT2_OFFSET);
856: addr_hit[19] = (reg_addr == AES_DATA_OUT3_OFFSET);
857: addr_hit[20] = (reg_addr == AES_CTRL_OFFSET);
858: addr_hit[21] = (reg_addr == AES_TRIGGER_OFFSET);
859: addr_hit[22] = (reg_addr == AES_STATUS_OFFSET);
860: end
861:
862: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
863:
864: // Check sub-word write is permitted
865: always_comb begin
866: wr_err = 1'b0;
867: if (addr_hit[ 0] && reg_we && (AES_PERMIT[ 0] != (AES_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
868: if (addr_hit[ 1] && reg_we && (AES_PERMIT[ 1] != (AES_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
869: if (addr_hit[ 2] && reg_we && (AES_PERMIT[ 2] != (AES_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
870: if (addr_hit[ 3] && reg_we && (AES_PERMIT[ 3] != (AES_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
871: if (addr_hit[ 4] && reg_we && (AES_PERMIT[ 4] != (AES_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
872: if (addr_hit[ 5] && reg_we && (AES_PERMIT[ 5] != (AES_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
873: if (addr_hit[ 6] && reg_we && (AES_PERMIT[ 6] != (AES_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
874: if (addr_hit[ 7] && reg_we && (AES_PERMIT[ 7] != (AES_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
875: if (addr_hit[ 8] && reg_we && (AES_PERMIT[ 8] != (AES_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
876: if (addr_hit[ 9] && reg_we && (AES_PERMIT[ 9] != (AES_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
877: if (addr_hit[10] && reg_we && (AES_PERMIT[10] != (AES_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
878: if (addr_hit[11] && reg_we && (AES_PERMIT[11] != (AES_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
879: if (addr_hit[12] && reg_we && (AES_PERMIT[12] != (AES_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
880: if (addr_hit[13] && reg_we && (AES_PERMIT[13] != (AES_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
881: if (addr_hit[14] && reg_we && (AES_PERMIT[14] != (AES_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
882: if (addr_hit[15] && reg_we && (AES_PERMIT[15] != (AES_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
883: if (addr_hit[16] && reg_we && (AES_PERMIT[16] != (AES_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
884: if (addr_hit[17] && reg_we && (AES_PERMIT[17] != (AES_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
885: if (addr_hit[18] && reg_we && (AES_PERMIT[18] != (AES_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
886: if (addr_hit[19] && reg_we && (AES_PERMIT[19] != (AES_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
887: if (addr_hit[20] && reg_we && (AES_PERMIT[20] != (AES_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
888: if (addr_hit[21] && reg_we && (AES_PERMIT[21] != (AES_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
889: if (addr_hit[22] && reg_we && (AES_PERMIT[22] != (AES_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
890: end
891:
892: assign key0_we = addr_hit[0] & reg_we & ~wr_err;
893: assign key0_wd = reg_wdata[31:0];
894:
895: assign key1_we = addr_hit[1] & reg_we & ~wr_err;
896: assign key1_wd = reg_wdata[31:0];
897:
898: assign key2_we = addr_hit[2] & reg_we & ~wr_err;
899: assign key2_wd = reg_wdata[31:0];
900:
901: assign key3_we = addr_hit[3] & reg_we & ~wr_err;
902: assign key3_wd = reg_wdata[31:0];
903:
904: assign key4_we = addr_hit[4] & reg_we & ~wr_err;
905: assign key4_wd = reg_wdata[31:0];
906:
907: assign key5_we = addr_hit[5] & reg_we & ~wr_err;
908: assign key5_wd = reg_wdata[31:0];
909:
910: assign key6_we = addr_hit[6] & reg_we & ~wr_err;
911: assign key6_wd = reg_wdata[31:0];
912:
913: assign key7_we = addr_hit[7] & reg_we & ~wr_err;
914: assign key7_wd = reg_wdata[31:0];
915:
916: assign iv0_we = addr_hit[8] & reg_we & ~wr_err;
917: assign iv0_wd = reg_wdata[31:0];
918:
919: assign iv1_we = addr_hit[9] & reg_we & ~wr_err;
920: assign iv1_wd = reg_wdata[31:0];
921:
922: assign iv2_we = addr_hit[10] & reg_we & ~wr_err;
923: assign iv2_wd = reg_wdata[31:0];
924:
925: assign iv3_we = addr_hit[11] & reg_we & ~wr_err;
926: assign iv3_wd = reg_wdata[31:0];
927:
928: assign data_in0_we = addr_hit[12] & reg_we & ~wr_err;
929: assign data_in0_wd = reg_wdata[31:0];
930:
931: assign data_in1_we = addr_hit[13] & reg_we & ~wr_err;
932: assign data_in1_wd = reg_wdata[31:0];
933:
934: assign data_in2_we = addr_hit[14] & reg_we & ~wr_err;
935: assign data_in2_wd = reg_wdata[31:0];
936:
937: assign data_in3_we = addr_hit[15] & reg_we & ~wr_err;
938: assign data_in3_wd = reg_wdata[31:0];
939:
940: assign data_out0_re = addr_hit[16] && reg_re;
941:
942: assign data_out1_re = addr_hit[17] && reg_re;
943:
944: assign data_out2_re = addr_hit[18] && reg_re;
945:
946: assign data_out3_re = addr_hit[19] && reg_re;
947:
948: assign ctrl_operation_we = addr_hit[20] & reg_we & ~wr_err;
949: assign ctrl_operation_wd = reg_wdata[0];
950: assign ctrl_operation_re = addr_hit[20] && reg_re;
951:
952: assign ctrl_mode_we = addr_hit[20] & reg_we & ~wr_err;
953: assign ctrl_mode_wd = reg_wdata[3:1];
954: assign ctrl_mode_re = addr_hit[20] && reg_re;
955:
956: assign ctrl_key_len_we = addr_hit[20] & reg_we & ~wr_err;
957: assign ctrl_key_len_wd = reg_wdata[6:4];
958: assign ctrl_key_len_re = addr_hit[20] && reg_re;
959:
960: assign ctrl_manual_operation_we = addr_hit[20] & reg_we & ~wr_err;
961: assign ctrl_manual_operation_wd = reg_wdata[7];
962: assign ctrl_manual_operation_re = addr_hit[20] && reg_re;
963:
964: assign trigger_start_we = addr_hit[21] & reg_we & ~wr_err;
965: assign trigger_start_wd = reg_wdata[0];
966:
967: assign trigger_key_clear_we = addr_hit[21] & reg_we & ~wr_err;
968: assign trigger_key_clear_wd = reg_wdata[1];
969:
970: assign trigger_iv_clear_we = addr_hit[21] & reg_we & ~wr_err;
971: assign trigger_iv_clear_wd = reg_wdata[2];
972:
973: assign trigger_data_in_clear_we = addr_hit[21] & reg_we & ~wr_err;
974: assign trigger_data_in_clear_wd = reg_wdata[3];
975:
976: assign trigger_data_out_clear_we = addr_hit[21] & reg_we & ~wr_err;
977: assign trigger_data_out_clear_wd = reg_wdata[4];
978:
979: assign trigger_prng_reseed_we = addr_hit[21] & reg_we & ~wr_err;
980: assign trigger_prng_reseed_wd = reg_wdata[5];
981:
982:
983:
984:
985:
986: // Read data return
987: always_comb begin
988: reg_rdata_next = '0;
989: unique case (1'b1)
990: addr_hit[0]: begin
991: reg_rdata_next[31:0] = '0;
992: end
993:
994: addr_hit[1]: begin
995: reg_rdata_next[31:0] = '0;
996: end
997:
998: addr_hit[2]: begin
999: reg_rdata_next[31:0] = '0;
1000: end
1001:
1002: addr_hit[3]: begin
1003: reg_rdata_next[31:0] = '0;
1004: end
1005:
1006: addr_hit[4]: begin
1007: reg_rdata_next[31:0] = '0;
1008: end
1009:
1010: addr_hit[5]: begin
1011: reg_rdata_next[31:0] = '0;
1012: end
1013:
1014: addr_hit[6]: begin
1015: reg_rdata_next[31:0] = '0;
1016: end
1017:
1018: addr_hit[7]: begin
1019: reg_rdata_next[31:0] = '0;
1020: end
1021:
1022: addr_hit[8]: begin
1023: reg_rdata_next[31:0] = '0;
1024: end
1025:
1026: addr_hit[9]: begin
1027: reg_rdata_next[31:0] = '0;
1028: end
1029:
1030: addr_hit[10]: begin
1031: reg_rdata_next[31:0] = '0;
1032: end
1033:
1034: addr_hit[11]: begin
1035: reg_rdata_next[31:0] = '0;
1036: end
1037:
1038: addr_hit[12]: begin
1039: reg_rdata_next[31:0] = '0;
1040: end
1041:
1042: addr_hit[13]: begin
1043: reg_rdata_next[31:0] = '0;
1044: end
1045:
1046: addr_hit[14]: begin
1047: reg_rdata_next[31:0] = '0;
1048: end
1049:
1050: addr_hit[15]: begin
1051: reg_rdata_next[31:0] = '0;
1052: end
1053:
1054: addr_hit[16]: begin
1055: reg_rdata_next[31:0] = data_out0_qs;
1056: end
1057:
1058: addr_hit[17]: begin
1059: reg_rdata_next[31:0] = data_out1_qs;
1060: end
1061:
1062: addr_hit[18]: begin
1063: reg_rdata_next[31:0] = data_out2_qs;
1064: end
1065:
1066: addr_hit[19]: begin
1067: reg_rdata_next[31:0] = data_out3_qs;
1068: end
1069:
1070: addr_hit[20]: begin
1071: reg_rdata_next[0] = ctrl_operation_qs;
1072: reg_rdata_next[3:1] = ctrl_mode_qs;
1073: reg_rdata_next[6:4] = ctrl_key_len_qs;
1074: reg_rdata_next[7] = ctrl_manual_operation_qs;
1075: end
1076:
1077: addr_hit[21]: begin
1078: reg_rdata_next[0] = '0;
1079: reg_rdata_next[1] = '0;
1080: reg_rdata_next[2] = '0;
1081: reg_rdata_next[3] = '0;
1082: reg_rdata_next[4] = '0;
1083: reg_rdata_next[5] = '0;
1084: end
1085:
1086: addr_hit[22]: begin
1087: reg_rdata_next[0] = status_idle_qs;
1088: reg_rdata_next[1] = status_stall_qs;
1089: reg_rdata_next[2] = status_output_valid_qs;
1090: reg_rdata_next[3] = status_input_ready_qs;
1091: end
1092:
1093: default: begin
1094: reg_rdata_next = '1;
1095: end
1096: endcase
1097: end
1098:
1099: // Assertions for Register Interface
1100: `ASSERT_PULSE(wePulse, reg_we)
1101: `ASSERT_PULSE(rePulse, reg_re)
1102:
1103: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
1104:
1105: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
1106:
1107: // this is formulated as an assumption such that the FPV testbenches do disprove this
1108: // property by mistake
1109: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
1110:
1111: endmodule
1112: