hw/ip/prim_generic/rtl/prim_generic_rom.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4:
5: module prim_generic_rom #(
6: parameter int Width = 32,
7: parameter int Depth = 2048, // 8kB default
8: parameter int Aw = $clog2(Depth)
9: ) (
10: input clk_i,
11: input rst_ni,
12: input [Aw-1:0] addr_i,
13: input cs_i,
14: output logic [Width-1:0] dout_o,
15: output logic dvalid_o
16: );
17:
18: logic [Width-1:0] mem [Depth];
19:
20: always_ff @(posedge clk_i) begin
21: if (cs_i) begin
22: dout_o <= mem[addr_i];
23: end
24: end
25:
26: always_ff @(posedge clk_i or negedge rst_ni) begin
27: if (!rst_ni) begin
28: dvalid_o <= 1'b0;
29: end else begin
30: dvalid_o <= cs_i;
31: end
32: end
33:
34: ////////////////
35: // ASSERTIONS //
36: ////////////////
37:
38: // Control Signals should never be X
39: `ASSERT(noXOnCsI, !$isunknown(cs_i), clk_i, '0)
40:
41: `ifdef VERILATOR
42: // Task for loading 'mem' with SystemVerilog system task $readmemh()
43: export "DPI-C" task simutil_verilator_memload;
44: // Function for setting a specific 32 bit element in |mem|
45: // Returns 1 (true) for success, 0 (false) for errors.
46: export "DPI-C" function simutil_verilator_set_mem;
47:
48: task simutil_verilator_memload;
49: input string file;
50: $readmemh(file, mem);
51: endtask
52:
53: // TODO: Allow 'val' to have other widths than 32 bit
54: function int simutil_verilator_set_mem(input int index,
55: input logic[31:0] val);
56: if (index >= Depth) begin
57: return 0;
58: end
59:
60: mem[index] = val;
61: return 1;
62: endfunction
63: `endif
64:
65: `ifdef ROM_INIT_FILE
66: localparam MEM_FILE = `"`ROM_INIT_FILE`";
67: initial begin
68: $display("Initializing ROM from %s", MEM_FILE);
69: $readmemh(MEM_FILE, mem);
70: end
71: `endif
72: endmodule
73: