hw/ip/prim_xilinx/rtl/prim_xilinx_clock_gating.sv Cov: 62.5%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: module prim_xilinx_clock_gating (
   6:   input        clk_i,
   7:   input        en_i,
   8:   input        test_en_i,
   9:   output logic clk_o
  10: );
  11: 
  12:   BUFGCE u_bufgce (
  13:     .I  (clk_i),
  14:     .CE (en_i | test_en_i),
  15:     .O  (clk_o)
  16:   );
  17: 
  18: endmodule
  19: