../src/lowrisc_top_earlgrey_clkmgr_0.1/rtl/autogen/clkmgr_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: `include "prim_assert.sv"
   8: 
   9: module clkmgr_reg_top (
  10:   input clk_i,
  11:   input rst_ni,
  12: 
  13:   // Below Regster interface can be changed
  14:   input  tlul_pkg::tl_h2d_t tl_i,
  15:   output tlul_pkg::tl_d2h_t tl_o,
  16:   // To HW
  17:   output clkmgr_reg_pkg::clkmgr_reg2hw_t reg2hw, // Write
  18:   input  clkmgr_reg_pkg::clkmgr_hw2reg_t hw2reg, // Read
  19: 
  20:   // Config
  21:   input devmode_i // If 1, explicit error return for unmapped register access
  22: );
  23: 
  24:   import clkmgr_reg_pkg::* ;
  25: 
  26:   localparam int AW = 4;
  27:   localparam int DW = 32;
  28:   localparam int DBW = DW/8;                    // Byte Width
  29: 
  30:   // register signals
  31:   logic           reg_we;
  32:   logic           reg_re;
  33:   logic [AW-1:0]  reg_addr;
  34:   logic [DW-1:0]  reg_wdata;
  35:   logic [DBW-1:0] reg_be;
  36:   logic [DW-1:0]  reg_rdata;
  37:   logic           reg_error;
  38: 
  39:   logic          addrmiss, wr_err;
  40: 
  41:   logic [DW-1:0] reg_rdata_next;
  42: 
  43:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  44:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  45: 
  46:   assign tl_reg_h2d = tl_i;
  47:   assign tl_o       = tl_reg_d2h;
  48: 
  49:   tlul_adapter_reg #(
  50:     .RegAw(AW),
  51:     .RegDw(DW)
  52:   ) u_reg_if (
  53:     .clk_i,
  54:     .rst_ni,
  55: 
  56:     .tl_i (tl_reg_h2d),
  57:     .tl_o (tl_reg_d2h),
  58: 
  59:     .we_o    (reg_we),
  60:     .re_o    (reg_re),
  61:     .addr_o  (reg_addr),
  62:     .wdata_o (reg_wdata),
  63:     .be_o    (reg_be),
  64:     .rdata_i (reg_rdata),
  65:     .error_i (reg_error)
  66:   );
  67: 
  68:   assign reg_rdata = reg_rdata_next ;
  69:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  70: 
  71:   // Define SW related signals
  72:   // Format: __{wd|we|qs}
  73:   //        or _{wd|we|qs} if field == 1 or 0
  74:   logic clk_enables_clk_io_peri_en_qs;
  75:   logic clk_enables_clk_io_peri_en_wd;
  76:   logic clk_enables_clk_io_peri_en_we;
  77:   logic clk_enables_clk_usb_peri_en_qs;
  78:   logic clk_enables_clk_usb_peri_en_wd;
  79:   logic clk_enables_clk_usb_peri_en_we;
  80:   logic clk_hints_clk_main_aes_hint_qs;
  81:   logic clk_hints_clk_main_aes_hint_wd;
  82:   logic clk_hints_clk_main_aes_hint_we;
  83:   logic clk_hints_clk_main_hmac_hint_qs;
  84:   logic clk_hints_clk_main_hmac_hint_wd;
  85:   logic clk_hints_clk_main_hmac_hint_we;
  86:   logic clk_hints_status_clk_main_aes_val_qs;
  87:   logic clk_hints_status_clk_main_hmac_val_qs;
  88: 
  89:   // Register instances
  90:   // R[clk_enables]: V(False)
  91: 
  92:   //   F[clk_io_peri_en]: 0:0
  93:   prim_subreg #(
  94:     .DW      (1),
  95:     .SWACCESS("RW"),
  96:     .RESVAL  (1'h1)
  97:   ) u_clk_enables_clk_io_peri_en (
  98:     .clk_i   (clk_i    ),
  99:     .rst_ni  (rst_ni  ),
 100: 
 101:     // from register interface
 102:     .we     (clk_enables_clk_io_peri_en_we),
 103:     .wd     (clk_enables_clk_io_peri_en_wd),
 104: 
 105:     // from internal hardware
 106:     .de     (1'b0),
 107:     .d      ('0  ),
 108: 
 109:     // to internal hardware
 110:     .qe     (),
 111:     .q      (reg2hw.clk_enables.clk_io_peri_en.q ),
 112: 
 113:     // to register interface (read)
 114:     .qs     (clk_enables_clk_io_peri_en_qs)
 115:   );
 116: 
 117: 
 118:   //   F[clk_usb_peri_en]: 1:1
 119:   prim_subreg #(
 120:     .DW      (1),
 121:     .SWACCESS("RW"),
 122:     .RESVAL  (1'h1)
 123:   ) u_clk_enables_clk_usb_peri_en (
 124:     .clk_i   (clk_i    ),
 125:     .rst_ni  (rst_ni  ),
 126: 
 127:     // from register interface
 128:     .we     (clk_enables_clk_usb_peri_en_we),
 129:     .wd     (clk_enables_clk_usb_peri_en_wd),
 130: 
 131:     // from internal hardware
 132:     .de     (1'b0),
 133:     .d      ('0  ),
 134: 
 135:     // to internal hardware
 136:     .qe     (),
 137:     .q      (reg2hw.clk_enables.clk_usb_peri_en.q ),
 138: 
 139:     // to register interface (read)
 140:     .qs     (clk_enables_clk_usb_peri_en_qs)
 141:   );
 142: 
 143: 
 144:   // R[clk_hints]: V(False)
 145: 
 146:   //   F[clk_main_aes_hint]: 0:0
 147:   prim_subreg #(
 148:     .DW      (1),
 149:     .SWACCESS("RW"),
 150:     .RESVAL  (1'h1)
 151:   ) u_clk_hints_clk_main_aes_hint (
 152:     .clk_i   (clk_i    ),
 153:     .rst_ni  (rst_ni  ),
 154: 
 155:     // from register interface
 156:     .we     (clk_hints_clk_main_aes_hint_we),
 157:     .wd     (clk_hints_clk_main_aes_hint_wd),
 158: 
 159:     // from internal hardware
 160:     .de     (1'b0),
 161:     .d      ('0  ),
 162: 
 163:     // to internal hardware
 164:     .qe     (),
 165:     .q      (reg2hw.clk_hints.clk_main_aes_hint.q ),
 166: 
 167:     // to register interface (read)
 168:     .qs     (clk_hints_clk_main_aes_hint_qs)
 169:   );
 170: 
 171: 
 172:   //   F[clk_main_hmac_hint]: 1:1
 173:   prim_subreg #(
 174:     .DW      (1),
 175:     .SWACCESS("RW"),
 176:     .RESVAL  (1'h1)
 177:   ) u_clk_hints_clk_main_hmac_hint (
 178:     .clk_i   (clk_i    ),
 179:     .rst_ni  (rst_ni  ),
 180: 
 181:     // from register interface
 182:     .we     (clk_hints_clk_main_hmac_hint_we),
 183:     .wd     (clk_hints_clk_main_hmac_hint_wd),
 184: 
 185:     // from internal hardware
 186:     .de     (1'b0),
 187:     .d      ('0  ),
 188: 
 189:     // to internal hardware
 190:     .qe     (),
 191:     .q      (reg2hw.clk_hints.clk_main_hmac_hint.q ),
 192: 
 193:     // to register interface (read)
 194:     .qs     (clk_hints_clk_main_hmac_hint_qs)
 195:   );
 196: 
 197: 
 198:   // R[clk_hints_status]: V(False)
 199: 
 200:   //   F[clk_main_aes_val]: 0:0
 201:   prim_subreg #(
 202:     .DW      (1),
 203:     .SWACCESS("RO"),
 204:     .RESVAL  (1'h1)
 205:   ) u_clk_hints_status_clk_main_aes_val (
 206:     .clk_i   (clk_i    ),
 207:     .rst_ni  (rst_ni  ),
 208: 
 209:     .we     (1'b0),
 210:     .wd     ('0  ),
 211: 
 212:     // from internal hardware
 213:     .de     (hw2reg.clk_hints_status.clk_main_aes_val.de),
 214:     .d      (hw2reg.clk_hints_status.clk_main_aes_val.d ),
 215: 
 216:     // to internal hardware
 217:     .qe     (),
 218:     .q      (),
 219: 
 220:     // to register interface (read)
 221:     .qs     (clk_hints_status_clk_main_aes_val_qs)
 222:   );
 223: 
 224: 
 225:   //   F[clk_main_hmac_val]: 1:1
 226:   prim_subreg #(
 227:     .DW      (1),
 228:     .SWACCESS("RO"),
 229:     .RESVAL  (1'h1)
 230:   ) u_clk_hints_status_clk_main_hmac_val (
 231:     .clk_i   (clk_i    ),
 232:     .rst_ni  (rst_ni  ),
 233: 
 234:     .we     (1'b0),
 235:     .wd     ('0  ),
 236: 
 237:     // from internal hardware
 238:     .de     (hw2reg.clk_hints_status.clk_main_hmac_val.de),
 239:     .d      (hw2reg.clk_hints_status.clk_main_hmac_val.d ),
 240: 
 241:     // to internal hardware
 242:     .qe     (),
 243:     .q      (),
 244: 
 245:     // to register interface (read)
 246:     .qs     (clk_hints_status_clk_main_hmac_val_qs)
 247:   );
 248: 
 249: 
 250: 
 251: 
 252:   logic [2:0] addr_hit;
 253:   always_comb begin
 254:     addr_hit = '0;
 255:     addr_hit[0] = (reg_addr == CLKMGR_CLK_ENABLES_OFFSET);
 256:     addr_hit[1] = (reg_addr == CLKMGR_CLK_HINTS_OFFSET);
 257:     addr_hit[2] = (reg_addr == CLKMGR_CLK_HINTS_STATUS_OFFSET);
 258:   end
 259: 
 260:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
 261: 
 262:   // Check sub-word write is permitted
 263:   always_comb begin
 264:     wr_err = 1'b0;
 265:     if (addr_hit[0] && reg_we && (CLKMGR_PERMIT[0] != (CLKMGR_PERMIT[0] & reg_be))) wr_err = 1'b1 ;
 266:     if (addr_hit[1] && reg_we && (CLKMGR_PERMIT[1] != (CLKMGR_PERMIT[1] & reg_be))) wr_err = 1'b1 ;
 267:     if (addr_hit[2] && reg_we && (CLKMGR_PERMIT[2] != (CLKMGR_PERMIT[2] & reg_be))) wr_err = 1'b1 ;
 268:   end
 269: 
 270:   assign clk_enables_clk_io_peri_en_we = addr_hit[0] & reg_we & ~wr_err;
 271:   assign clk_enables_clk_io_peri_en_wd = reg_wdata[0];
 272: 
 273:   assign clk_enables_clk_usb_peri_en_we = addr_hit[0] & reg_we & ~wr_err;
 274:   assign clk_enables_clk_usb_peri_en_wd = reg_wdata[1];
 275: 
 276:   assign clk_hints_clk_main_aes_hint_we = addr_hit[1] & reg_we & ~wr_err;
 277:   assign clk_hints_clk_main_aes_hint_wd = reg_wdata[0];
 278: 
 279:   assign clk_hints_clk_main_hmac_hint_we = addr_hit[1] & reg_we & ~wr_err;
 280:   assign clk_hints_clk_main_hmac_hint_wd = reg_wdata[1];
 281: 
 282: 
 283: 
 284:   // Read data return
 285:   always_comb begin
 286:     reg_rdata_next = '0;
 287:     unique case (1'b1)
 288:       addr_hit[0]: begin
 289:         reg_rdata_next[0] = clk_enables_clk_io_peri_en_qs;
 290:         reg_rdata_next[1] = clk_enables_clk_usb_peri_en_qs;
 291:       end
 292: 
 293:       addr_hit[1]: begin
 294:         reg_rdata_next[0] = clk_hints_clk_main_aes_hint_qs;
 295:         reg_rdata_next[1] = clk_hints_clk_main_hmac_hint_qs;
 296:       end
 297: 
 298:       addr_hit[2]: begin
 299:         reg_rdata_next[0] = clk_hints_status_clk_main_aes_val_qs;
 300:         reg_rdata_next[1] = clk_hints_status_clk_main_hmac_val_qs;
 301:       end
 302: 
 303:       default: begin
 304:         reg_rdata_next = '1;
 305:       end
 306:     endcase
 307:   end
 308: 
 309:   // Assertions for Register Interface
 310:   `ASSERT_PULSE(wePulse, reg_we)
 311:   `ASSERT_PULSE(rePulse, reg_re)
 312: 
 313:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
 314: 
 315:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
 316: 
 317:   // this is formulated as an assumption such that the FPV testbenches do disprove this
 318:   // property by mistake
 319:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
 320: 
 321: endmodule
 322: