hw/ip/hmac/rtl/hmac_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: module hmac_reg_top (
8: input clk_i,
9: input rst_ni,
10:
11: // Below Regster interface can be changed
12: input tlul_pkg::tl_h2d_t tl_i,
13: output tlul_pkg::tl_d2h_t tl_o,
14:
15: // Output port for window
16: output tlul_pkg::tl_h2d_t tl_win_o [1],
17: input tlul_pkg::tl_d2h_t tl_win_i [1],
18:
19: // To HW
20: output hmac_reg_pkg::hmac_reg2hw_t reg2hw, // Write
21: input hmac_reg_pkg::hmac_hw2reg_t hw2reg, // Read
22:
23: // Config
24: input devmode_i // If 1, explicit error return for unmapped register access
25: );
26:
27: import hmac_reg_pkg::* ;
28:
29: localparam int AW = 12;
30: localparam int DW = 32;
31: localparam int DBW = DW/8; // Byte Width
32:
33: // register signals
34: logic reg_we;
35: logic reg_re;
36: logic [AW-1:0] reg_addr;
37: logic [DW-1:0] reg_wdata;
38: logic [DBW-1:0] reg_be;
39: logic [DW-1:0] reg_rdata;
40: logic reg_error;
41:
42: logic addrmiss, wr_err;
43:
44: logic [DW-1:0] reg_rdata_next;
45:
46: tlul_pkg::tl_h2d_t tl_reg_h2d;
47: tlul_pkg::tl_d2h_t tl_reg_d2h;
48:
49: tlul_pkg::tl_h2d_t tl_socket_h2d [2];
50: tlul_pkg::tl_d2h_t tl_socket_d2h [2];
51:
52: logic [1:0] reg_steer;
53:
54: // socket_1n connection
55: assign tl_reg_h2d = tl_socket_h2d[1];
56: assign tl_socket_d2h[1] = tl_reg_d2h;
57:
58: assign tl_win_o[0] = tl_socket_h2d[0];
59: assign tl_socket_d2h[0] = tl_win_i[0];
60:
61: // Create Socket_1n
62: tlul_socket_1n #(
63: .N (2),
64: .HReqPass (1'b1),
65: .HRspPass (1'b1),
66: .DReqPass ({2{1'b1}}),
67: .DRspPass ({2{1'b1}}),
68: .HReqDepth (4'h0),
69: .HRspDepth (4'h0),
70: .DReqDepth ({2{4'h0}}),
71: .DRspDepth ({2{4'h0}})
72: ) u_socket (
73: .clk_i,
74: .rst_ni,
75: .tl_h_i (tl_i),
76: .tl_h_o (tl_o),
77: .tl_d_o (tl_socket_h2d),
78: .tl_d_i (tl_socket_d2h),
79: .dev_select (reg_steer)
80: );
81:
82: // Create steering logic
83: always_comb begin
84: reg_steer = 1; // Default set to register
85:
86: // TODO: Can below codes be unique case () inside ?
87: if (tl_i.a_address[AW-1:0] >= 2048) begin
88: // Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
89: reg_steer = 0;
90: end
91: end
92:
93: tlul_adapter_reg #(
94: .RegAw(AW),
95: .RegDw(DW)
96: ) u_reg_if (
97: .clk_i,
98: .rst_ni,
99:
100: .tl_i (tl_reg_h2d),
101: .tl_o (tl_reg_d2h),
102:
103: .we_o (reg_we),
104: .re_o (reg_re),
105: .addr_o (reg_addr),
106: .wdata_o (reg_wdata),
107: .be_o (reg_be),
108: .rdata_i (reg_rdata),
109: .error_i (reg_error)
110: );
111:
112: assign reg_rdata = reg_rdata_next ;
113: assign reg_error = (devmode_i & addrmiss) | wr_err ;
114:
115: // Define SW related signals
116: // Format: __{wd|we|qs}
117: // or _{wd|we|qs} if field == 1 or 0
118: logic intr_state_hmac_done_qs;
119: logic intr_state_hmac_done_wd;
120: logic intr_state_hmac_done_we;
121: logic intr_state_fifo_full_qs;
122: logic intr_state_fifo_full_wd;
123: logic intr_state_fifo_full_we;
124: logic intr_state_hmac_err_qs;
125: logic intr_state_hmac_err_wd;
126: logic intr_state_hmac_err_we;
127: logic intr_enable_hmac_done_qs;
128: logic intr_enable_hmac_done_wd;
129: logic intr_enable_hmac_done_we;
130: logic intr_enable_fifo_full_qs;
131: logic intr_enable_fifo_full_wd;
132: logic intr_enable_fifo_full_we;
133: logic intr_enable_hmac_err_qs;
134: logic intr_enable_hmac_err_wd;
135: logic intr_enable_hmac_err_we;
136: logic intr_test_hmac_done_wd;
137: logic intr_test_hmac_done_we;
138: logic intr_test_fifo_full_wd;
139: logic intr_test_fifo_full_we;
140: logic intr_test_hmac_err_wd;
141: logic intr_test_hmac_err_we;
142: logic cfg_hmac_en_qs;
143: logic cfg_hmac_en_wd;
144: logic cfg_hmac_en_we;
145: logic cfg_hmac_en_re;
146: logic cfg_sha_en_qs;
147: logic cfg_sha_en_wd;
148: logic cfg_sha_en_we;
149: logic cfg_sha_en_re;
150: logic cfg_endian_swap_qs;
151: logic cfg_endian_swap_wd;
152: logic cfg_endian_swap_we;
153: logic cfg_endian_swap_re;
154: logic cfg_digest_swap_qs;
155: logic cfg_digest_swap_wd;
156: logic cfg_digest_swap_we;
157: logic cfg_digest_swap_re;
158: logic cmd_hash_start_wd;
159: logic cmd_hash_start_we;
160: logic cmd_hash_process_wd;
161: logic cmd_hash_process_we;
162: logic status_fifo_empty_qs;
163: logic status_fifo_empty_re;
164: logic status_fifo_full_qs;
165: logic status_fifo_full_re;
166: logic [4:0] status_fifo_depth_qs;
167: logic status_fifo_depth_re;
168: logic [31:0] err_code_qs;
169: logic [31:0] wipe_secret_wd;
170: logic wipe_secret_we;
171: logic [31:0] key0_wd;
172: logic key0_we;
173: logic [31:0] key1_wd;
174: logic key1_we;
175: logic [31:0] key2_wd;
176: logic key2_we;
177: logic [31:0] key3_wd;
178: logic key3_we;
179: logic [31:0] key4_wd;
180: logic key4_we;
181: logic [31:0] key5_wd;
182: logic key5_we;
183: logic [31:0] key6_wd;
184: logic key6_we;
185: logic [31:0] key7_wd;
186: logic key7_we;
187: logic [31:0] digest0_qs;
188: logic digest0_re;
189: logic [31:0] digest1_qs;
190: logic digest1_re;
191: logic [31:0] digest2_qs;
192: logic digest2_re;
193: logic [31:0] digest3_qs;
194: logic digest3_re;
195: logic [31:0] digest4_qs;
196: logic digest4_re;
197: logic [31:0] digest5_qs;
198: logic digest5_re;
199: logic [31:0] digest6_qs;
200: logic digest6_re;
201: logic [31:0] digest7_qs;
202: logic digest7_re;
203: logic [31:0] msg_length_lower_qs;
204: logic [31:0] msg_length_upper_qs;
205:
206: // Register instances
207: // R[intr_state]: V(False)
208:
209: // F[hmac_done]: 0:0
210: prim_subreg #(
211: .DW (1),
212: .SWACCESS("W1C"),
213: .RESVAL (1'h0)
214: ) u_intr_state_hmac_done (
215: .clk_i (clk_i ),
216: .rst_ni (rst_ni ),
217:
218: // from register interface
219: .we (intr_state_hmac_done_we),
220: .wd (intr_state_hmac_done_wd),
221:
222: // from internal hardware
223: .de (hw2reg.intr_state.hmac_done.de),
224: .d (hw2reg.intr_state.hmac_done.d ),
225:
226: // to internal hardware
227: .qe (),
228: .q (reg2hw.intr_state.hmac_done.q ),
229:
230: // to register interface (read)
231: .qs (intr_state_hmac_done_qs)
232: );
233:
234:
235: // F[fifo_full]: 1:1
236: prim_subreg #(
237: .DW (1),
238: .SWACCESS("W1C"),
239: .RESVAL (1'h0)
240: ) u_intr_state_fifo_full (
241: .clk_i (clk_i ),
242: .rst_ni (rst_ni ),
243:
244: // from register interface
245: .we (intr_state_fifo_full_we),
246: .wd (intr_state_fifo_full_wd),
247:
248: // from internal hardware
249: .de (hw2reg.intr_state.fifo_full.de),
250: .d (hw2reg.intr_state.fifo_full.d ),
251:
252: // to internal hardware
253: .qe (),
254: .q (reg2hw.intr_state.fifo_full.q ),
255:
256: // to register interface (read)
257: .qs (intr_state_fifo_full_qs)
258: );
259:
260:
261: // F[hmac_err]: 2:2
262: prim_subreg #(
263: .DW (1),
264: .SWACCESS("W1C"),
265: .RESVAL (1'h0)
266: ) u_intr_state_hmac_err (
267: .clk_i (clk_i ),
268: .rst_ni (rst_ni ),
269:
270: // from register interface
271: .we (intr_state_hmac_err_we),
272: .wd (intr_state_hmac_err_wd),
273:
274: // from internal hardware
275: .de (hw2reg.intr_state.hmac_err.de),
276: .d (hw2reg.intr_state.hmac_err.d ),
277:
278: // to internal hardware
279: .qe (),
280: .q (reg2hw.intr_state.hmac_err.q ),
281:
282: // to register interface (read)
283: .qs (intr_state_hmac_err_qs)
284: );
285:
286:
287: // R[intr_enable]: V(False)
288:
289: // F[hmac_done]: 0:0
290: prim_subreg #(
291: .DW (1),
292: .SWACCESS("RW"),
293: .RESVAL (1'h0)
294: ) u_intr_enable_hmac_done (
295: .clk_i (clk_i ),
296: .rst_ni (rst_ni ),
297:
298: // from register interface
299: .we (intr_enable_hmac_done_we),
300: .wd (intr_enable_hmac_done_wd),
301:
302: // from internal hardware
303: .de (1'b0),
304: .d ('0 ),
305:
306: // to internal hardware
307: .qe (),
308: .q (reg2hw.intr_enable.hmac_done.q ),
309:
310: // to register interface (read)
311: .qs (intr_enable_hmac_done_qs)
312: );
313:
314:
315: // F[fifo_full]: 1:1
316: prim_subreg #(
317: .DW (1),
318: .SWACCESS("RW"),
319: .RESVAL (1'h0)
320: ) u_intr_enable_fifo_full (
321: .clk_i (clk_i ),
322: .rst_ni (rst_ni ),
323:
324: // from register interface
325: .we (intr_enable_fifo_full_we),
326: .wd (intr_enable_fifo_full_wd),
327:
328: // from internal hardware
329: .de (1'b0),
330: .d ('0 ),
331:
332: // to internal hardware
333: .qe (),
334: .q (reg2hw.intr_enable.fifo_full.q ),
335:
336: // to register interface (read)
337: .qs (intr_enable_fifo_full_qs)
338: );
339:
340:
341: // F[hmac_err]: 2:2
342: prim_subreg #(
343: .DW (1),
344: .SWACCESS("RW"),
345: .RESVAL (1'h0)
346: ) u_intr_enable_hmac_err (
347: .clk_i (clk_i ),
348: .rst_ni (rst_ni ),
349:
350: // from register interface
351: .we (intr_enable_hmac_err_we),
352: .wd (intr_enable_hmac_err_wd),
353:
354: // from internal hardware
355: .de (1'b0),
356: .d ('0 ),
357:
358: // to internal hardware
359: .qe (),
360: .q (reg2hw.intr_enable.hmac_err.q ),
361:
362: // to register interface (read)
363: .qs (intr_enable_hmac_err_qs)
364: );
365:
366:
367: // R[intr_test]: V(True)
368:
369: // F[hmac_done]: 0:0
370: prim_subreg_ext #(
371: .DW (1)
372: ) u_intr_test_hmac_done (
373: .re (1'b0),
374: .we (intr_test_hmac_done_we),
375: .wd (intr_test_hmac_done_wd),
376: .d ('0),
377: .qre (),
378: .qe (reg2hw.intr_test.hmac_done.qe),
379: .q (reg2hw.intr_test.hmac_done.q ),
380: .qs ()
381: );
382:
383:
384: // F[fifo_full]: 1:1
385: prim_subreg_ext #(
386: .DW (1)
387: ) u_intr_test_fifo_full (
388: .re (1'b0),
389: .we (intr_test_fifo_full_we),
390: .wd (intr_test_fifo_full_wd),
391: .d ('0),
392: .qre (),
393: .qe (reg2hw.intr_test.fifo_full.qe),
394: .q (reg2hw.intr_test.fifo_full.q ),
395: .qs ()
396: );
397:
398:
399: // F[hmac_err]: 2:2
400: prim_subreg_ext #(
401: .DW (1)
402: ) u_intr_test_hmac_err (
403: .re (1'b0),
404: .we (intr_test_hmac_err_we),
405: .wd (intr_test_hmac_err_wd),
406: .d ('0),
407: .qre (),
408: .qe (reg2hw.intr_test.hmac_err.qe),
409: .q (reg2hw.intr_test.hmac_err.q ),
410: .qs ()
411: );
412:
413:
414: // R[cfg]: V(True)
415:
416: // F[hmac_en]: 0:0
417: prim_subreg_ext #(
418: .DW (1)
419: ) u_cfg_hmac_en (
420: .re (cfg_hmac_en_re),
421: .we (cfg_hmac_en_we),
422: .wd (cfg_hmac_en_wd),
423: .d (hw2reg.cfg.hmac_en.d),
424: .qre (),
425: .qe (reg2hw.cfg.hmac_en.qe),
426: .q (reg2hw.cfg.hmac_en.q ),
427: .qs (cfg_hmac_en_qs)
428: );
429:
430:
431: // F[sha_en]: 1:1
432: prim_subreg_ext #(
433: .DW (1)
434: ) u_cfg_sha_en (
435: .re (cfg_sha_en_re),
436: .we (cfg_sha_en_we),
437: .wd (cfg_sha_en_wd),
438: .d (hw2reg.cfg.sha_en.d),
439: .qre (),
440: .qe (reg2hw.cfg.sha_en.qe),
441: .q (reg2hw.cfg.sha_en.q ),
442: .qs (cfg_sha_en_qs)
443: );
444:
445:
446: // F[endian_swap]: 2:2
447: prim_subreg_ext #(
448: .DW (1)
449: ) u_cfg_endian_swap (
450: .re (cfg_endian_swap_re),
451: .we (cfg_endian_swap_we),
452: .wd (cfg_endian_swap_wd),
453: .d (hw2reg.cfg.endian_swap.d),
454: .qre (),
455: .qe (reg2hw.cfg.endian_swap.qe),
456: .q (reg2hw.cfg.endian_swap.q ),
457: .qs (cfg_endian_swap_qs)
458: );
459:
460:
461: // F[digest_swap]: 3:3
462: prim_subreg_ext #(
463: .DW (1)
464: ) u_cfg_digest_swap (
465: .re (cfg_digest_swap_re),
466: .we (cfg_digest_swap_we),
467: .wd (cfg_digest_swap_wd),
468: .d (hw2reg.cfg.digest_swap.d),
469: .qre (),
470: .qe (reg2hw.cfg.digest_swap.qe),
471: .q (reg2hw.cfg.digest_swap.q ),
472: .qs (cfg_digest_swap_qs)
473: );
474:
475:
476: // R[cmd]: V(True)
477:
478: // F[hash_start]: 0:0
479: prim_subreg_ext #(
480: .DW (1)
481: ) u_cmd_hash_start (
482: .re (1'b0),
483: .we (cmd_hash_start_we),
484: .wd (cmd_hash_start_wd),
485: .d ('0),
486: .qre (),
487: .qe (reg2hw.cmd.hash_start.qe),
488: .q (reg2hw.cmd.hash_start.q ),
489: .qs ()
490: );
491:
492:
493: // F[hash_process]: 1:1
494: prim_subreg_ext #(
495: .DW (1)
496: ) u_cmd_hash_process (
497: .re (1'b0),
498: .we (cmd_hash_process_we),
499: .wd (cmd_hash_process_wd),
500: .d ('0),
501: .qre (),
502: .qe (reg2hw.cmd.hash_process.qe),
503: .q (reg2hw.cmd.hash_process.q ),
504: .qs ()
505: );
506:
507:
508: // R[status]: V(True)
509:
510: // F[fifo_empty]: 0:0
511: prim_subreg_ext #(
512: .DW (1)
513: ) u_status_fifo_empty (
514: .re (status_fifo_empty_re),
515: .we (1'b0),
516: .wd ('0),
517: .d (hw2reg.status.fifo_empty.d),
518: .qre (),
519: .qe (),
520: .q (),
521: .qs (status_fifo_empty_qs)
522: );
523:
524:
525: // F[fifo_full]: 1:1
526: prim_subreg_ext #(
527: .DW (1)
528: ) u_status_fifo_full (
529: .re (status_fifo_full_re),
530: .we (1'b0),
531: .wd ('0),
532: .d (hw2reg.status.fifo_full.d),
533: .qre (),
534: .qe (),
535: .q (),
536: .qs (status_fifo_full_qs)
537: );
538:
539:
540: // F[fifo_depth]: 8:4
541: prim_subreg_ext #(
542: .DW (5)
543: ) u_status_fifo_depth (
544: .re (status_fifo_depth_re),
545: .we (1'b0),
546: .wd ('0),
547: .d (hw2reg.status.fifo_depth.d),
548: .qre (),
549: .qe (),
550: .q (),
551: .qs (status_fifo_depth_qs)
552: );
553:
554:
555: // R[err_code]: V(False)
556:
557: prim_subreg #(
558: .DW (32),
559: .SWACCESS("RO"),
560: .RESVAL (32'h0)
561: ) u_err_code (
562: .clk_i (clk_i ),
563: .rst_ni (rst_ni ),
564:
565: .we (1'b0),
566: .wd ('0 ),
567:
568: // from internal hardware
569: .de (hw2reg.err_code.de),
570: .d (hw2reg.err_code.d ),
571:
572: // to internal hardware
573: .qe (),
574: .q (),
575:
576: // to register interface (read)
577: .qs (err_code_qs)
578: );
579:
580:
581: // R[wipe_secret]: V(True)
582:
583: prim_subreg_ext #(
584: .DW (32)
585: ) u_wipe_secret (
586: .re (1'b0),
587: .we (wipe_secret_we),
588: .wd (wipe_secret_wd),
589: .d ('0),
590: .qre (),
591: .qe (reg2hw.wipe_secret.qe),
592: .q (reg2hw.wipe_secret.q ),
593: .qs ()
594: );
595:
596:
597:
598: // Subregister 0 of Multireg key
599: // R[key0]: V(True)
600:
601: prim_subreg_ext #(
602: .DW (32)
603: ) u_key0 (
604: .re (1'b0),
605: .we (key0_we),
606: .wd (key0_wd),
607: .d (hw2reg.key[0].d),
608: .qre (),
609: .qe (reg2hw.key[0].qe),
610: .q (reg2hw.key[0].q ),
611: .qs ()
612: );
613:
614: // Subregister 1 of Multireg key
615: // R[key1]: V(True)
616:
617: prim_subreg_ext #(
618: .DW (32)
619: ) u_key1 (
620: .re (1'b0),
621: .we (key1_we),
622: .wd (key1_wd),
623: .d (hw2reg.key[1].d),
624: .qre (),
625: .qe (reg2hw.key[1].qe),
626: .q (reg2hw.key[1].q ),
627: .qs ()
628: );
629:
630: // Subregister 2 of Multireg key
631: // R[key2]: V(True)
632:
633: prim_subreg_ext #(
634: .DW (32)
635: ) u_key2 (
636: .re (1'b0),
637: .we (key2_we),
638: .wd (key2_wd),
639: .d (hw2reg.key[2].d),
640: .qre (),
641: .qe (reg2hw.key[2].qe),
642: .q (reg2hw.key[2].q ),
643: .qs ()
644: );
645:
646: // Subregister 3 of Multireg key
647: // R[key3]: V(True)
648:
649: prim_subreg_ext #(
650: .DW (32)
651: ) u_key3 (
652: .re (1'b0),
653: .we (key3_we),
654: .wd (key3_wd),
655: .d (hw2reg.key[3].d),
656: .qre (),
657: .qe (reg2hw.key[3].qe),
658: .q (reg2hw.key[3].q ),
659: .qs ()
660: );
661:
662: // Subregister 4 of Multireg key
663: // R[key4]: V(True)
664:
665: prim_subreg_ext #(
666: .DW (32)
667: ) u_key4 (
668: .re (1'b0),
669: .we (key4_we),
670: .wd (key4_wd),
671: .d (hw2reg.key[4].d),
672: .qre (),
673: .qe (reg2hw.key[4].qe),
674: .q (reg2hw.key[4].q ),
675: .qs ()
676: );
677:
678: // Subregister 5 of Multireg key
679: // R[key5]: V(True)
680:
681: prim_subreg_ext #(
682: .DW (32)
683: ) u_key5 (
684: .re (1'b0),
685: .we (key5_we),
686: .wd (key5_wd),
687: .d (hw2reg.key[5].d),
688: .qre (),
689: .qe (reg2hw.key[5].qe),
690: .q (reg2hw.key[5].q ),
691: .qs ()
692: );
693:
694: // Subregister 6 of Multireg key
695: // R[key6]: V(True)
696:
697: prim_subreg_ext #(
698: .DW (32)
699: ) u_key6 (
700: .re (1'b0),
701: .we (key6_we),
702: .wd (key6_wd),
703: .d (hw2reg.key[6].d),
704: .qre (),
705: .qe (reg2hw.key[6].qe),
706: .q (reg2hw.key[6].q ),
707: .qs ()
708: );
709:
710: // Subregister 7 of Multireg key
711: // R[key7]: V(True)
712:
713: prim_subreg_ext #(
714: .DW (32)
715: ) u_key7 (
716: .re (1'b0),
717: .we (key7_we),
718: .wd (key7_wd),
719: .d (hw2reg.key[7].d),
720: .qre (),
721: .qe (reg2hw.key[7].qe),
722: .q (reg2hw.key[7].q ),
723: .qs ()
724: );
725:
726:
727:
728: // Subregister 0 of Multireg digest
729: // R[digest0]: V(True)
730:
731: prim_subreg_ext #(
732: .DW (32)
733: ) u_digest0 (
734: .re (digest0_re),
735: .we (1'b0),
736: .wd ('0),
737: .d (hw2reg.digest[0].d),
738: .qre (),
739: .qe (),
740: .q (),
741: .qs (digest0_qs)
742: );
743:
744: // Subregister 1 of Multireg digest
745: // R[digest1]: V(True)
746:
747: prim_subreg_ext #(
748: .DW (32)
749: ) u_digest1 (
750: .re (digest1_re),
751: .we (1'b0),
752: .wd ('0),
753: .d (hw2reg.digest[1].d),
754: .qre (),
755: .qe (),
756: .q (),
757: .qs (digest1_qs)
758: );
759:
760: // Subregister 2 of Multireg digest
761: // R[digest2]: V(True)
762:
763: prim_subreg_ext #(
764: .DW (32)
765: ) u_digest2 (
766: .re (digest2_re),
767: .we (1'b0),
768: .wd ('0),
769: .d (hw2reg.digest[2].d),
770: .qre (),
771: .qe (),
772: .q (),
773: .qs (digest2_qs)
774: );
775:
776: // Subregister 3 of Multireg digest
777: // R[digest3]: V(True)
778:
779: prim_subreg_ext #(
780: .DW (32)
781: ) u_digest3 (
782: .re (digest3_re),
783: .we (1'b0),
784: .wd ('0),
785: .d (hw2reg.digest[3].d),
786: .qre (),
787: .qe (),
788: .q (),
789: .qs (digest3_qs)
790: );
791:
792: // Subregister 4 of Multireg digest
793: // R[digest4]: V(True)
794:
795: prim_subreg_ext #(
796: .DW (32)
797: ) u_digest4 (
798: .re (digest4_re),
799: .we (1'b0),
800: .wd ('0),
801: .d (hw2reg.digest[4].d),
802: .qre (),
803: .qe (),
804: .q (),
805: .qs (digest4_qs)
806: );
807:
808: // Subregister 5 of Multireg digest
809: // R[digest5]: V(True)
810:
811: prim_subreg_ext #(
812: .DW (32)
813: ) u_digest5 (
814: .re (digest5_re),
815: .we (1'b0),
816: .wd ('0),
817: .d (hw2reg.digest[5].d),
818: .qre (),
819: .qe (),
820: .q (),
821: .qs (digest5_qs)
822: );
823:
824: // Subregister 6 of Multireg digest
825: // R[digest6]: V(True)
826:
827: prim_subreg_ext #(
828: .DW (32)
829: ) u_digest6 (
830: .re (digest6_re),
831: .we (1'b0),
832: .wd ('0),
833: .d (hw2reg.digest[6].d),
834: .qre (),
835: .qe (),
836: .q (),
837: .qs (digest6_qs)
838: );
839:
840: // Subregister 7 of Multireg digest
841: // R[digest7]: V(True)
842:
843: prim_subreg_ext #(
844: .DW (32)
845: ) u_digest7 (
846: .re (digest7_re),
847: .we (1'b0),
848: .wd ('0),
849: .d (hw2reg.digest[7].d),
850: .qre (),
851: .qe (),
852: .q (),
853: .qs (digest7_qs)
854: );
855:
856:
857: // R[msg_length_lower]: V(False)
858:
859: prim_subreg #(
860: .DW (32),
861: .SWACCESS("RO"),
862: .RESVAL (32'h0)
863: ) u_msg_length_lower (
864: .clk_i (clk_i ),
865: .rst_ni (rst_ni ),
866:
867: .we (1'b0),
868: .wd ('0 ),
869:
870: // from internal hardware
871: .de (hw2reg.msg_length_lower.de),
872: .d (hw2reg.msg_length_lower.d ),
873:
874: // to internal hardware
875: .qe (),
876: .q (),
877:
878: // to register interface (read)
879: .qs (msg_length_lower_qs)
880: );
881:
882:
883: // R[msg_length_upper]: V(False)
884:
885: prim_subreg #(
886: .DW (32),
887: .SWACCESS("RO"),
888: .RESVAL (32'h0)
889: ) u_msg_length_upper (
890: .clk_i (clk_i ),
891: .rst_ni (rst_ni ),
892:
893: .we (1'b0),
894: .wd ('0 ),
895:
896: // from internal hardware
897: .de (hw2reg.msg_length_upper.de),
898: .d (hw2reg.msg_length_upper.d ),
899:
900: // to internal hardware
901: .qe (),
902: .q (),
903:
904: // to register interface (read)
905: .qs (msg_length_upper_qs)
906: );
907:
908:
909:
910:
911: logic [25:0] addr_hit;
912: always_comb begin
913: addr_hit = '0;
914: addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
915: addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
916: addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
917: addr_hit[ 3] = (reg_addr == HMAC_CFG_OFFSET);
918: addr_hit[ 4] = (reg_addr == HMAC_CMD_OFFSET);
919: addr_hit[ 5] = (reg_addr == HMAC_STATUS_OFFSET);
920: addr_hit[ 6] = (reg_addr == HMAC_ERR_CODE_OFFSET);
921: addr_hit[ 7] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
922: addr_hit[ 8] = (reg_addr == HMAC_KEY0_OFFSET);
923: addr_hit[ 9] = (reg_addr == HMAC_KEY1_OFFSET);
924: addr_hit[10] = (reg_addr == HMAC_KEY2_OFFSET);
925: addr_hit[11] = (reg_addr == HMAC_KEY3_OFFSET);
926: addr_hit[12] = (reg_addr == HMAC_KEY4_OFFSET);
927: addr_hit[13] = (reg_addr == HMAC_KEY5_OFFSET);
928: addr_hit[14] = (reg_addr == HMAC_KEY6_OFFSET);
929: addr_hit[15] = (reg_addr == HMAC_KEY7_OFFSET);
930: addr_hit[16] = (reg_addr == HMAC_DIGEST0_OFFSET);
931: addr_hit[17] = (reg_addr == HMAC_DIGEST1_OFFSET);
932: addr_hit[18] = (reg_addr == HMAC_DIGEST2_OFFSET);
933: addr_hit[19] = (reg_addr == HMAC_DIGEST3_OFFSET);
934: addr_hit[20] = (reg_addr == HMAC_DIGEST4_OFFSET);
935: addr_hit[21] = (reg_addr == HMAC_DIGEST5_OFFSET);
936: addr_hit[22] = (reg_addr == HMAC_DIGEST6_OFFSET);
937: addr_hit[23] = (reg_addr == HMAC_DIGEST7_OFFSET);
938: addr_hit[24] = (reg_addr == HMAC_MSG_LENGTH_LOWER_OFFSET);
939: addr_hit[25] = (reg_addr == HMAC_MSG_LENGTH_UPPER_OFFSET);
940: end
941:
942: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
943:
944: // Check sub-word write is permitted
945: always_comb begin
946: wr_err = 1'b0;
947: if (addr_hit[ 0] && reg_we && (HMAC_PERMIT[ 0] != (HMAC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
948: if (addr_hit[ 1] && reg_we && (HMAC_PERMIT[ 1] != (HMAC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
949: if (addr_hit[ 2] && reg_we && (HMAC_PERMIT[ 2] != (HMAC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
950: if (addr_hit[ 3] && reg_we && (HMAC_PERMIT[ 3] != (HMAC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
951: if (addr_hit[ 4] && reg_we && (HMAC_PERMIT[ 4] != (HMAC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
952: if (addr_hit[ 5] && reg_we && (HMAC_PERMIT[ 5] != (HMAC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
953: if (addr_hit[ 6] && reg_we && (HMAC_PERMIT[ 6] != (HMAC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
954: if (addr_hit[ 7] && reg_we && (HMAC_PERMIT[ 7] != (HMAC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
955: if (addr_hit[ 8] && reg_we && (HMAC_PERMIT[ 8] != (HMAC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
956: if (addr_hit[ 9] && reg_we && (HMAC_PERMIT[ 9] != (HMAC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
957: if (addr_hit[10] && reg_we && (HMAC_PERMIT[10] != (HMAC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
958: if (addr_hit[11] && reg_we && (HMAC_PERMIT[11] != (HMAC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
959: if (addr_hit[12] && reg_we && (HMAC_PERMIT[12] != (HMAC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
960: if (addr_hit[13] && reg_we && (HMAC_PERMIT[13] != (HMAC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
961: if (addr_hit[14] && reg_we && (HMAC_PERMIT[14] != (HMAC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
962: if (addr_hit[15] && reg_we && (HMAC_PERMIT[15] != (HMAC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
963: if (addr_hit[16] && reg_we && (HMAC_PERMIT[16] != (HMAC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
964: if (addr_hit[17] && reg_we && (HMAC_PERMIT[17] != (HMAC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
965: if (addr_hit[18] && reg_we && (HMAC_PERMIT[18] != (HMAC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
966: if (addr_hit[19] && reg_we && (HMAC_PERMIT[19] != (HMAC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
967: if (addr_hit[20] && reg_we && (HMAC_PERMIT[20] != (HMAC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
968: if (addr_hit[21] && reg_we && (HMAC_PERMIT[21] != (HMAC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
969: if (addr_hit[22] && reg_we && (HMAC_PERMIT[22] != (HMAC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
970: if (addr_hit[23] && reg_we && (HMAC_PERMIT[23] != (HMAC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
971: if (addr_hit[24] && reg_we && (HMAC_PERMIT[24] != (HMAC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
972: if (addr_hit[25] && reg_we && (HMAC_PERMIT[25] != (HMAC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
973: end
974:
975: assign intr_state_hmac_done_we = addr_hit[0] & reg_we & ~wr_err;
976: assign intr_state_hmac_done_wd = reg_wdata[0];
977:
978: assign intr_state_fifo_full_we = addr_hit[0] & reg_we & ~wr_err;
979: assign intr_state_fifo_full_wd = reg_wdata[1];
980:
981: assign intr_state_hmac_err_we = addr_hit[0] & reg_we & ~wr_err;
982: assign intr_state_hmac_err_wd = reg_wdata[2];
983:
984: assign intr_enable_hmac_done_we = addr_hit[1] & reg_we & ~wr_err;
985: assign intr_enable_hmac_done_wd = reg_wdata[0];
986:
987: assign intr_enable_fifo_full_we = addr_hit[1] & reg_we & ~wr_err;
988: assign intr_enable_fifo_full_wd = reg_wdata[1];
989:
990: assign intr_enable_hmac_err_we = addr_hit[1] & reg_we & ~wr_err;
991: assign intr_enable_hmac_err_wd = reg_wdata[2];
992:
993: assign intr_test_hmac_done_we = addr_hit[2] & reg_we & ~wr_err;
994: assign intr_test_hmac_done_wd = reg_wdata[0];
995:
996: assign intr_test_fifo_full_we = addr_hit[2] & reg_we & ~wr_err;
997: assign intr_test_fifo_full_wd = reg_wdata[1];
998:
999: assign intr_test_hmac_err_we = addr_hit[2] & reg_we & ~wr_err;
1000: assign intr_test_hmac_err_wd = reg_wdata[2];
1001:
1002: assign cfg_hmac_en_we = addr_hit[3] & reg_we & ~wr_err;
1003: assign cfg_hmac_en_wd = reg_wdata[0];
1004: assign cfg_hmac_en_re = addr_hit[3] && reg_re;
1005:
1006: assign cfg_sha_en_we = addr_hit[3] & reg_we & ~wr_err;
1007: assign cfg_sha_en_wd = reg_wdata[1];
1008: assign cfg_sha_en_re = addr_hit[3] && reg_re;
1009:
1010: assign cfg_endian_swap_we = addr_hit[3] & reg_we & ~wr_err;
1011: assign cfg_endian_swap_wd = reg_wdata[2];
1012: assign cfg_endian_swap_re = addr_hit[3] && reg_re;
1013:
1014: assign cfg_digest_swap_we = addr_hit[3] & reg_we & ~wr_err;
1015: assign cfg_digest_swap_wd = reg_wdata[3];
1016: assign cfg_digest_swap_re = addr_hit[3] && reg_re;
1017:
1018: assign cmd_hash_start_we = addr_hit[4] & reg_we & ~wr_err;
1019: assign cmd_hash_start_wd = reg_wdata[0];
1020:
1021: assign cmd_hash_process_we = addr_hit[4] & reg_we & ~wr_err;
1022: assign cmd_hash_process_wd = reg_wdata[1];
1023:
1024: assign status_fifo_empty_re = addr_hit[5] && reg_re;
1025:
1026: assign status_fifo_full_re = addr_hit[5] && reg_re;
1027:
1028: assign status_fifo_depth_re = addr_hit[5] && reg_re;
1029:
1030:
1031: assign wipe_secret_we = addr_hit[7] & reg_we & ~wr_err;
1032: assign wipe_secret_wd = reg_wdata[31:0];
1033:
1034: assign key0_we = addr_hit[8] & reg_we & ~wr_err;
1035: assign key0_wd = reg_wdata[31:0];
1036:
1037: assign key1_we = addr_hit[9] & reg_we & ~wr_err;
1038: assign key1_wd = reg_wdata[31:0];
1039:
1040: assign key2_we = addr_hit[10] & reg_we & ~wr_err;
1041: assign key2_wd = reg_wdata[31:0];
1042:
1043: assign key3_we = addr_hit[11] & reg_we & ~wr_err;
1044: assign key3_wd = reg_wdata[31:0];
1045:
1046: assign key4_we = addr_hit[12] & reg_we & ~wr_err;
1047: assign key4_wd = reg_wdata[31:0];
1048:
1049: assign key5_we = addr_hit[13] & reg_we & ~wr_err;
1050: assign key5_wd = reg_wdata[31:0];
1051:
1052: assign key6_we = addr_hit[14] & reg_we & ~wr_err;
1053: assign key6_wd = reg_wdata[31:0];
1054:
1055: assign key7_we = addr_hit[15] & reg_we & ~wr_err;
1056: assign key7_wd = reg_wdata[31:0];
1057:
1058: assign digest0_re = addr_hit[16] && reg_re;
1059:
1060: assign digest1_re = addr_hit[17] && reg_re;
1061:
1062: assign digest2_re = addr_hit[18] && reg_re;
1063:
1064: assign digest3_re = addr_hit[19] && reg_re;
1065:
1066: assign digest4_re = addr_hit[20] && reg_re;
1067:
1068: assign digest5_re = addr_hit[21] && reg_re;
1069:
1070: assign digest6_re = addr_hit[22] && reg_re;
1071:
1072: assign digest7_re = addr_hit[23] && reg_re;
1073:
1074:
1075:
1076: // Read data return
1077: always_comb begin
1078: reg_rdata_next = '0;
1079: unique case (1'b1)
1080: addr_hit[0]: begin
1081: reg_rdata_next[0] = intr_state_hmac_done_qs;
1082: reg_rdata_next[1] = intr_state_fifo_full_qs;
1083: reg_rdata_next[2] = intr_state_hmac_err_qs;
1084: end
1085:
1086: addr_hit[1]: begin
1087: reg_rdata_next[0] = intr_enable_hmac_done_qs;
1088: reg_rdata_next[1] = intr_enable_fifo_full_qs;
1089: reg_rdata_next[2] = intr_enable_hmac_err_qs;
1090: end
1091:
1092: addr_hit[2]: begin
1093: reg_rdata_next[0] = '0;
1094: reg_rdata_next[1] = '0;
1095: reg_rdata_next[2] = '0;
1096: end
1097:
1098: addr_hit[3]: begin
1099: reg_rdata_next[0] = cfg_hmac_en_qs;
1100: reg_rdata_next[1] = cfg_sha_en_qs;
1101: reg_rdata_next[2] = cfg_endian_swap_qs;
1102: reg_rdata_next[3] = cfg_digest_swap_qs;
1103: end
1104:
1105: addr_hit[4]: begin
1106: reg_rdata_next[0] = '0;
1107: reg_rdata_next[1] = '0;
1108: end
1109:
1110: addr_hit[5]: begin
1111: reg_rdata_next[0] = status_fifo_empty_qs;
1112: reg_rdata_next[1] = status_fifo_full_qs;
1113: reg_rdata_next[8:4] = status_fifo_depth_qs;
1114: end
1115:
1116: addr_hit[6]: begin
1117: reg_rdata_next[31:0] = err_code_qs;
1118: end
1119:
1120: addr_hit[7]: begin
1121: reg_rdata_next[31:0] = '0;
1122: end
1123:
1124: addr_hit[8]: begin
1125: reg_rdata_next[31:0] = '0;
1126: end
1127:
1128: addr_hit[9]: begin
1129: reg_rdata_next[31:0] = '0;
1130: end
1131:
1132: addr_hit[10]: begin
1133: reg_rdata_next[31:0] = '0;
1134: end
1135:
1136: addr_hit[11]: begin
1137: reg_rdata_next[31:0] = '0;
1138: end
1139:
1140: addr_hit[12]: begin
1141: reg_rdata_next[31:0] = '0;
1142: end
1143:
1144: addr_hit[13]: begin
1145: reg_rdata_next[31:0] = '0;
1146: end
1147:
1148: addr_hit[14]: begin
1149: reg_rdata_next[31:0] = '0;
1150: end
1151:
1152: addr_hit[15]: begin
1153: reg_rdata_next[31:0] = '0;
1154: end
1155:
1156: addr_hit[16]: begin
1157: reg_rdata_next[31:0] = digest0_qs;
1158: end
1159:
1160: addr_hit[17]: begin
1161: reg_rdata_next[31:0] = digest1_qs;
1162: end
1163:
1164: addr_hit[18]: begin
1165: reg_rdata_next[31:0] = digest2_qs;
1166: end
1167:
1168: addr_hit[19]: begin
1169: reg_rdata_next[31:0] = digest3_qs;
1170: end
1171:
1172: addr_hit[20]: begin
1173: reg_rdata_next[31:0] = digest4_qs;
1174: end
1175:
1176: addr_hit[21]: begin
1177: reg_rdata_next[31:0] = digest5_qs;
1178: end
1179:
1180: addr_hit[22]: begin
1181: reg_rdata_next[31:0] = digest6_qs;
1182: end
1183:
1184: addr_hit[23]: begin
1185: reg_rdata_next[31:0] = digest7_qs;
1186: end
1187:
1188: addr_hit[24]: begin
1189: reg_rdata_next[31:0] = msg_length_lower_qs;
1190: end
1191:
1192: addr_hit[25]: begin
1193: reg_rdata_next[31:0] = msg_length_upper_qs;
1194: end
1195:
1196: default: begin
1197: reg_rdata_next = '1;
1198: end
1199: endcase
1200: end
1201:
1202: // Assertions for Register Interface
1203: `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
1204: `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
1205:
1206: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
1207:
1208: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
1209:
1210: // this is formulated as an assumption such that the FPV testbenches do disprove this
1211: // property by mistake
1212: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
1213:
1214: endmodule
1215: