hw/ip/gpio/rtl/gpio_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: module gpio_reg_top (
8: input clk_i,
9: input rst_ni,
10:
11: // Below Regster interface can be changed
12: input tlul_pkg::tl_h2d_t tl_i,
13: output tlul_pkg::tl_d2h_t tl_o,
14: // To HW
15: output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write
16: input gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read
17:
18: // Config
19: input devmode_i // If 1, explicit error return for unmapped register access
20: );
21:
22: import gpio_reg_pkg::* ;
23:
24: localparam int AW = 6;
25: localparam int DW = 32;
26: localparam int DBW = DW/8; // Byte Width
27:
28: // register signals
29: logic reg_we;
30: logic reg_re;
31: logic [AW-1:0] reg_addr;
32: logic [DW-1:0] reg_wdata;
33: logic [DBW-1:0] reg_be;
34: logic [DW-1:0] reg_rdata;
35: logic reg_error;
36:
37: logic addrmiss, wr_err;
38:
39: logic [DW-1:0] reg_rdata_next;
40:
41: tlul_pkg::tl_h2d_t tl_reg_h2d;
42: tlul_pkg::tl_d2h_t tl_reg_d2h;
43:
44: assign tl_reg_h2d = tl_i;
45: assign tl_o = tl_reg_d2h;
46:
47: tlul_adapter_reg #(
48: .RegAw(AW),
49: .RegDw(DW)
50: ) u_reg_if (
51: .clk_i,
52: .rst_ni,
53:
54: .tl_i (tl_reg_h2d),
55: .tl_o (tl_reg_d2h),
56:
57: .we_o (reg_we),
58: .re_o (reg_re),
59: .addr_o (reg_addr),
60: .wdata_o (reg_wdata),
61: .be_o (reg_be),
62: .rdata_i (reg_rdata),
63: .error_i (reg_error)
64: );
65:
66: assign reg_rdata = reg_rdata_next ;
67: assign reg_error = (devmode_i & addrmiss) | wr_err ;
68:
69: // Define SW related signals
70: // Format: __{wd|we|qs}
71: // or _{wd|we|qs} if field == 1 or 0
72: logic [31:0] intr_state_qs;
73: logic [31:0] intr_state_wd;
74: logic intr_state_we;
75: logic [31:0] intr_enable_qs;
76: logic [31:0] intr_enable_wd;
77: logic intr_enable_we;
78: logic [31:0] intr_test_wd;
79: logic intr_test_we;
80: logic [31:0] data_in_qs;
81: logic [31:0] direct_out_qs;
82: logic [31:0] direct_out_wd;
83: logic direct_out_we;
84: logic direct_out_re;
85: logic [15:0] masked_out_lower_data_qs;
86: logic [15:0] masked_out_lower_data_wd;
87: logic masked_out_lower_data_we;
88: logic masked_out_lower_data_re;
89: logic [15:0] masked_out_lower_mask_wd;
90: logic masked_out_lower_mask_we;
91: logic [15:0] masked_out_upper_data_qs;
92: logic [15:0] masked_out_upper_data_wd;
93: logic masked_out_upper_data_we;
94: logic masked_out_upper_data_re;
95: logic [15:0] masked_out_upper_mask_wd;
96: logic masked_out_upper_mask_we;
97: logic [31:0] direct_oe_qs;
98: logic [31:0] direct_oe_wd;
99: logic direct_oe_we;
100: logic direct_oe_re;
101: logic [15:0] masked_oe_lower_data_qs;
102: logic [15:0] masked_oe_lower_data_wd;
103: logic masked_oe_lower_data_we;
104: logic masked_oe_lower_data_re;
105: logic [15:0] masked_oe_lower_mask_qs;
106: logic [15:0] masked_oe_lower_mask_wd;
107: logic masked_oe_lower_mask_we;
108: logic masked_oe_lower_mask_re;
109: logic [15:0] masked_oe_upper_data_qs;
110: logic [15:0] masked_oe_upper_data_wd;
111: logic masked_oe_upper_data_we;
112: logic masked_oe_upper_data_re;
113: logic [15:0] masked_oe_upper_mask_qs;
114: logic [15:0] masked_oe_upper_mask_wd;
115: logic masked_oe_upper_mask_we;
116: logic masked_oe_upper_mask_re;
117: logic [31:0] intr_ctrl_en_rising_qs;
118: logic [31:0] intr_ctrl_en_rising_wd;
119: logic intr_ctrl_en_rising_we;
120: logic [31:0] intr_ctrl_en_falling_qs;
121: logic [31:0] intr_ctrl_en_falling_wd;
122: logic intr_ctrl_en_falling_we;
123: logic [31:0] intr_ctrl_en_lvlhigh_qs;
124: logic [31:0] intr_ctrl_en_lvlhigh_wd;
125: logic intr_ctrl_en_lvlhigh_we;
126: logic [31:0] intr_ctrl_en_lvllow_qs;
127: logic [31:0] intr_ctrl_en_lvllow_wd;
128: logic intr_ctrl_en_lvllow_we;
129: logic [31:0] ctrl_en_input_filter_qs;
130: logic [31:0] ctrl_en_input_filter_wd;
131: logic ctrl_en_input_filter_we;
132:
133: // Register instances
134: // R[intr_state]: V(False)
135:
136: prim_subreg #(
137: .DW (32),
138: .SWACCESS("W1C"),
139: .RESVAL (32'h0)
140: ) u_intr_state (
141: .clk_i (clk_i ),
142: .rst_ni (rst_ni ),
143:
144: // from register interface
145: .we (intr_state_we),
146: .wd (intr_state_wd),
147:
148: // from internal hardware
149: .de (hw2reg.intr_state.de),
150: .d (hw2reg.intr_state.d ),
151:
152: // to internal hardware
153: .qe (),
154: .q (reg2hw.intr_state.q ),
155:
156: // to register interface (read)
157: .qs (intr_state_qs)
158: );
159:
160:
161: // R[intr_enable]: V(False)
162:
163: prim_subreg #(
164: .DW (32),
165: .SWACCESS("RW"),
166: .RESVAL (32'h0)
167: ) u_intr_enable (
168: .clk_i (clk_i ),
169: .rst_ni (rst_ni ),
170:
171: // from register interface
172: .we (intr_enable_we),
173: .wd (intr_enable_wd),
174:
175: // from internal hardware
176: .de (1'b0),
177: .d ('0 ),
178:
179: // to internal hardware
180: .qe (),
181: .q (reg2hw.intr_enable.q ),
182:
183: // to register interface (read)
184: .qs (intr_enable_qs)
185: );
186:
187:
188: // R[intr_test]: V(True)
189:
190: prim_subreg_ext #(
191: .DW (32)
192: ) u_intr_test (
193: .re (1'b0),
194: .we (intr_test_we),
195: .wd (intr_test_wd),
196: .d ('0),
197: .qre (),
198: .qe (reg2hw.intr_test.qe),
199: .q (reg2hw.intr_test.q ),
200: .qs ()
201: );
202:
203:
204: // R[data_in]: V(False)
205:
206: prim_subreg #(
207: .DW (32),
208: .SWACCESS("RO"),
209: .RESVAL (32'h0)
210: ) u_data_in (
211: .clk_i (clk_i ),
212: .rst_ni (rst_ni ),
213:
214: .we (1'b0),
215: .wd ('0 ),
216:
217: // from internal hardware
218: .de (hw2reg.data_in.de),
219: .d (hw2reg.data_in.d ),
220:
221: // to internal hardware
222: .qe (),
223: .q (),
224:
225: // to register interface (read)
226: .qs (data_in_qs)
227: );
228:
229:
230: // R[direct_out]: V(True)
231:
232: prim_subreg_ext #(
233: .DW (32)
234: ) u_direct_out (
235: .re (direct_out_re),
236: .we (direct_out_we),
237: .wd (direct_out_wd),
238: .d (hw2reg.direct_out.d),
239: .qre (),
240: .qe (reg2hw.direct_out.qe),
241: .q (reg2hw.direct_out.q ),
242: .qs (direct_out_qs)
243: );
244:
245:
246: // R[masked_out_lower]: V(True)
247:
248: // F[data]: 15:0
249: prim_subreg_ext #(
250: .DW (16)
251: ) u_masked_out_lower_data (
252: .re (masked_out_lower_data_re),
253: .we (masked_out_lower_data_we),
254: .wd (masked_out_lower_data_wd),
255: .d (hw2reg.masked_out_lower.data.d),
256: .qre (),
257: .qe (reg2hw.masked_out_lower.data.qe),
258: .q (reg2hw.masked_out_lower.data.q ),
259: .qs (masked_out_lower_data_qs)
260: );
261:
262:
263: // F[mask]: 31:16
264: prim_subreg_ext #(
265: .DW (16)
266: ) u_masked_out_lower_mask (
267: .re (1'b0),
268: .we (masked_out_lower_mask_we),
269: .wd (masked_out_lower_mask_wd),
270: .d (hw2reg.masked_out_lower.mask.d),
271: .qre (),
272: .qe (reg2hw.masked_out_lower.mask.qe),
273: .q (reg2hw.masked_out_lower.mask.q ),
274: .qs ()
275: );
276:
277:
278: // R[masked_out_upper]: V(True)
279:
280: // F[data]: 15:0
281: prim_subreg_ext #(
282: .DW (16)
283: ) u_masked_out_upper_data (
284: .re (masked_out_upper_data_re),
285: .we (masked_out_upper_data_we),
286: .wd (masked_out_upper_data_wd),
287: .d (hw2reg.masked_out_upper.data.d),
288: .qre (),
289: .qe (reg2hw.masked_out_upper.data.qe),
290: .q (reg2hw.masked_out_upper.data.q ),
291: .qs (masked_out_upper_data_qs)
292: );
293:
294:
295: // F[mask]: 31:16
296: prim_subreg_ext #(
297: .DW (16)
298: ) u_masked_out_upper_mask (
299: .re (1'b0),
300: .we (masked_out_upper_mask_we),
301: .wd (masked_out_upper_mask_wd),
302: .d (hw2reg.masked_out_upper.mask.d),
303: .qre (),
304: .qe (reg2hw.masked_out_upper.mask.qe),
305: .q (reg2hw.masked_out_upper.mask.q ),
306: .qs ()
307: );
308:
309:
310: // R[direct_oe]: V(True)
311:
312: prim_subreg_ext #(
313: .DW (32)
314: ) u_direct_oe (
315: .re (direct_oe_re),
316: .we (direct_oe_we),
317: .wd (direct_oe_wd),
318: .d (hw2reg.direct_oe.d),
319: .qre (),
320: .qe (reg2hw.direct_oe.qe),
321: .q (reg2hw.direct_oe.q ),
322: .qs (direct_oe_qs)
323: );
324:
325:
326: // R[masked_oe_lower]: V(True)
327:
328: // F[data]: 15:0
329: prim_subreg_ext #(
330: .DW (16)
331: ) u_masked_oe_lower_data (
332: .re (masked_oe_lower_data_re),
333: .we (masked_oe_lower_data_we),
334: .wd (masked_oe_lower_data_wd),
335: .d (hw2reg.masked_oe_lower.data.d),
336: .qre (),
337: .qe (reg2hw.masked_oe_lower.data.qe),
338: .q (reg2hw.masked_oe_lower.data.q ),
339: .qs (masked_oe_lower_data_qs)
340: );
341:
342:
343: // F[mask]: 31:16
344: prim_subreg_ext #(
345: .DW (16)
346: ) u_masked_oe_lower_mask (
347: .re (masked_oe_lower_mask_re),
348: .we (masked_oe_lower_mask_we),
349: .wd (masked_oe_lower_mask_wd),
350: .d (hw2reg.masked_oe_lower.mask.d),
351: .qre (),
352: .qe (reg2hw.masked_oe_lower.mask.qe),
353: .q (reg2hw.masked_oe_lower.mask.q ),
354: .qs (masked_oe_lower_mask_qs)
355: );
356:
357:
358: // R[masked_oe_upper]: V(True)
359:
360: // F[data]: 15:0
361: prim_subreg_ext #(
362: .DW (16)
363: ) u_masked_oe_upper_data (
364: .re (masked_oe_upper_data_re),
365: .we (masked_oe_upper_data_we),
366: .wd (masked_oe_upper_data_wd),
367: .d (hw2reg.masked_oe_upper.data.d),
368: .qre (),
369: .qe (reg2hw.masked_oe_upper.data.qe),
370: .q (reg2hw.masked_oe_upper.data.q ),
371: .qs (masked_oe_upper_data_qs)
372: );
373:
374:
375: // F[mask]: 31:16
376: prim_subreg_ext #(
377: .DW (16)
378: ) u_masked_oe_upper_mask (
379: .re (masked_oe_upper_mask_re),
380: .we (masked_oe_upper_mask_we),
381: .wd (masked_oe_upper_mask_wd),
382: .d (hw2reg.masked_oe_upper.mask.d),
383: .qre (),
384: .qe (reg2hw.masked_oe_upper.mask.qe),
385: .q (reg2hw.masked_oe_upper.mask.q ),
386: .qs (masked_oe_upper_mask_qs)
387: );
388:
389:
390: // R[intr_ctrl_en_rising]: V(False)
391:
392: prim_subreg #(
393: .DW (32),
394: .SWACCESS("RW"),
395: .RESVAL (32'h0)
396: ) u_intr_ctrl_en_rising (
397: .clk_i (clk_i ),
398: .rst_ni (rst_ni ),
399:
400: // from register interface
401: .we (intr_ctrl_en_rising_we),
402: .wd (intr_ctrl_en_rising_wd),
403:
404: // from internal hardware
405: .de (1'b0),
406: .d ('0 ),
407:
408: // to internal hardware
409: .qe (),
410: .q (reg2hw.intr_ctrl_en_rising.q ),
411:
412: // to register interface (read)
413: .qs (intr_ctrl_en_rising_qs)
414: );
415:
416:
417: // R[intr_ctrl_en_falling]: V(False)
418:
419: prim_subreg #(
420: .DW (32),
421: .SWACCESS("RW"),
422: .RESVAL (32'h0)
423: ) u_intr_ctrl_en_falling (
424: .clk_i (clk_i ),
425: .rst_ni (rst_ni ),
426:
427: // from register interface
428: .we (intr_ctrl_en_falling_we),
429: .wd (intr_ctrl_en_falling_wd),
430:
431: // from internal hardware
432: .de (1'b0),
433: .d ('0 ),
434:
435: // to internal hardware
436: .qe (),
437: .q (reg2hw.intr_ctrl_en_falling.q ),
438:
439: // to register interface (read)
440: .qs (intr_ctrl_en_falling_qs)
441: );
442:
443:
444: // R[intr_ctrl_en_lvlhigh]: V(False)
445:
446: prim_subreg #(
447: .DW (32),
448: .SWACCESS("RW"),
449: .RESVAL (32'h0)
450: ) u_intr_ctrl_en_lvlhigh (
451: .clk_i (clk_i ),
452: .rst_ni (rst_ni ),
453:
454: // from register interface
455: .we (intr_ctrl_en_lvlhigh_we),
456: .wd (intr_ctrl_en_lvlhigh_wd),
457:
458: // from internal hardware
459: .de (1'b0),
460: .d ('0 ),
461:
462: // to internal hardware
463: .qe (),
464: .q (reg2hw.intr_ctrl_en_lvlhigh.q ),
465:
466: // to register interface (read)
467: .qs (intr_ctrl_en_lvlhigh_qs)
468: );
469:
470:
471: // R[intr_ctrl_en_lvllow]: V(False)
472:
473: prim_subreg #(
474: .DW (32),
475: .SWACCESS("RW"),
476: .RESVAL (32'h0)
477: ) u_intr_ctrl_en_lvllow (
478: .clk_i (clk_i ),
479: .rst_ni (rst_ni ),
480:
481: // from register interface
482: .we (intr_ctrl_en_lvllow_we),
483: .wd (intr_ctrl_en_lvllow_wd),
484:
485: // from internal hardware
486: .de (1'b0),
487: .d ('0 ),
488:
489: // to internal hardware
490: .qe (),
491: .q (reg2hw.intr_ctrl_en_lvllow.q ),
492:
493: // to register interface (read)
494: .qs (intr_ctrl_en_lvllow_qs)
495: );
496:
497:
498: // R[ctrl_en_input_filter]: V(False)
499:
500: prim_subreg #(
501: .DW (32),
502: .SWACCESS("RW"),
503: .RESVAL (32'h0)
504: ) u_ctrl_en_input_filter (
505: .clk_i (clk_i ),
506: .rst_ni (rst_ni ),
507:
508: // from register interface
509: .we (ctrl_en_input_filter_we),
510: .wd (ctrl_en_input_filter_wd),
511:
512: // from internal hardware
513: .de (1'b0),
514: .d ('0 ),
515:
516: // to internal hardware
517: .qe (),
518: .q (reg2hw.ctrl_en_input_filter.q ),
519:
520: // to register interface (read)
521: .qs (ctrl_en_input_filter_qs)
522: );
523:
524:
525:
526:
527: logic [14:0] addr_hit;
528: always_comb begin
529: addr_hit = '0;
530: addr_hit[ 0] = (reg_addr == GPIO_INTR_STATE_OFFSET);
531: addr_hit[ 1] = (reg_addr == GPIO_INTR_ENABLE_OFFSET);
532: addr_hit[ 2] = (reg_addr == GPIO_INTR_TEST_OFFSET);
533: addr_hit[ 3] = (reg_addr == GPIO_DATA_IN_OFFSET);
534: addr_hit[ 4] = (reg_addr == GPIO_DIRECT_OUT_OFFSET);
535: addr_hit[ 5] = (reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET);
536: addr_hit[ 6] = (reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET);
537: addr_hit[ 7] = (reg_addr == GPIO_DIRECT_OE_OFFSET);
538: addr_hit[ 8] = (reg_addr == GPIO_MASKED_OE_LOWER_OFFSET);
539: addr_hit[ 9] = (reg_addr == GPIO_MASKED_OE_UPPER_OFFSET);
540: addr_hit[10] = (reg_addr == GPIO_INTR_CTRL_EN_RISING_OFFSET);
541: addr_hit[11] = (reg_addr == GPIO_INTR_CTRL_EN_FALLING_OFFSET);
542: addr_hit[12] = (reg_addr == GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET);
543: addr_hit[13] = (reg_addr == GPIO_INTR_CTRL_EN_LVLLOW_OFFSET);
544: addr_hit[14] = (reg_addr == GPIO_CTRL_EN_INPUT_FILTER_OFFSET);
545: end
546:
547: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
548:
549: // Check sub-word write is permitted
550: always_comb begin
551: wr_err = 1'b0;
552: if (addr_hit[ 0] && reg_we && (GPIO_PERMIT[ 0] != (GPIO_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
553: if (addr_hit[ 1] && reg_we && (GPIO_PERMIT[ 1] != (GPIO_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
554: if (addr_hit[ 2] && reg_we && (GPIO_PERMIT[ 2] != (GPIO_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
555: if (addr_hit[ 3] && reg_we && (GPIO_PERMIT[ 3] != (GPIO_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
556: if (addr_hit[ 4] && reg_we && (GPIO_PERMIT[ 4] != (GPIO_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
557: if (addr_hit[ 5] && reg_we && (GPIO_PERMIT[ 5] != (GPIO_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
558: if (addr_hit[ 6] && reg_we && (GPIO_PERMIT[ 6] != (GPIO_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
559: if (addr_hit[ 7] && reg_we && (GPIO_PERMIT[ 7] != (GPIO_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
560: if (addr_hit[ 8] && reg_we && (GPIO_PERMIT[ 8] != (GPIO_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
561: if (addr_hit[ 9] && reg_we && (GPIO_PERMIT[ 9] != (GPIO_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
562: if (addr_hit[10] && reg_we && (GPIO_PERMIT[10] != (GPIO_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
563: if (addr_hit[11] && reg_we && (GPIO_PERMIT[11] != (GPIO_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
564: if (addr_hit[12] && reg_we && (GPIO_PERMIT[12] != (GPIO_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
565: if (addr_hit[13] && reg_we && (GPIO_PERMIT[13] != (GPIO_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
566: if (addr_hit[14] && reg_we && (GPIO_PERMIT[14] != (GPIO_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
567: end
568:
569: assign intr_state_we = addr_hit[0] & reg_we & ~wr_err;
570: assign intr_state_wd = reg_wdata[31:0];
571:
572: assign intr_enable_we = addr_hit[1] & reg_we & ~wr_err;
573: assign intr_enable_wd = reg_wdata[31:0];
574:
575: assign intr_test_we = addr_hit[2] & reg_we & ~wr_err;
576: assign intr_test_wd = reg_wdata[31:0];
577:
578:
579: assign direct_out_we = addr_hit[4] & reg_we & ~wr_err;
580: assign direct_out_wd = reg_wdata[31:0];
581: assign direct_out_re = addr_hit[4] && reg_re;
582:
583: assign masked_out_lower_data_we = addr_hit[5] & reg_we & ~wr_err;
584: assign masked_out_lower_data_wd = reg_wdata[15:0];
585: assign masked_out_lower_data_re = addr_hit[5] && reg_re;
586:
587: assign masked_out_lower_mask_we = addr_hit[5] & reg_we & ~wr_err;
588: assign masked_out_lower_mask_wd = reg_wdata[31:16];
589:
590: assign masked_out_upper_data_we = addr_hit[6] & reg_we & ~wr_err;
591: assign masked_out_upper_data_wd = reg_wdata[15:0];
592: assign masked_out_upper_data_re = addr_hit[6] && reg_re;
593:
594: assign masked_out_upper_mask_we = addr_hit[6] & reg_we & ~wr_err;
595: assign masked_out_upper_mask_wd = reg_wdata[31:16];
596:
597: assign direct_oe_we = addr_hit[7] & reg_we & ~wr_err;
598: assign direct_oe_wd = reg_wdata[31:0];
599: assign direct_oe_re = addr_hit[7] && reg_re;
600:
601: assign masked_oe_lower_data_we = addr_hit[8] & reg_we & ~wr_err;
602: assign masked_oe_lower_data_wd = reg_wdata[15:0];
603: assign masked_oe_lower_data_re = addr_hit[8] && reg_re;
604:
605: assign masked_oe_lower_mask_we = addr_hit[8] & reg_we & ~wr_err;
606: assign masked_oe_lower_mask_wd = reg_wdata[31:16];
607: assign masked_oe_lower_mask_re = addr_hit[8] && reg_re;
608:
609: assign masked_oe_upper_data_we = addr_hit[9] & reg_we & ~wr_err;
610: assign masked_oe_upper_data_wd = reg_wdata[15:0];
611: assign masked_oe_upper_data_re = addr_hit[9] && reg_re;
612:
613: assign masked_oe_upper_mask_we = addr_hit[9] & reg_we & ~wr_err;
614: assign masked_oe_upper_mask_wd = reg_wdata[31:16];
615: assign masked_oe_upper_mask_re = addr_hit[9] && reg_re;
616:
617: assign intr_ctrl_en_rising_we = addr_hit[10] & reg_we & ~wr_err;
618: assign intr_ctrl_en_rising_wd = reg_wdata[31:0];
619:
620: assign intr_ctrl_en_falling_we = addr_hit[11] & reg_we & ~wr_err;
621: assign intr_ctrl_en_falling_wd = reg_wdata[31:0];
622:
623: assign intr_ctrl_en_lvlhigh_we = addr_hit[12] & reg_we & ~wr_err;
624: assign intr_ctrl_en_lvlhigh_wd = reg_wdata[31:0];
625:
626: assign intr_ctrl_en_lvllow_we = addr_hit[13] & reg_we & ~wr_err;
627: assign intr_ctrl_en_lvllow_wd = reg_wdata[31:0];
628:
629: assign ctrl_en_input_filter_we = addr_hit[14] & reg_we & ~wr_err;
630: assign ctrl_en_input_filter_wd = reg_wdata[31:0];
631:
632: // Read data return
633: always_comb begin
634: reg_rdata_next = '0;
635: unique case (1'b1)
636: addr_hit[0]: begin
637: reg_rdata_next[31:0] = intr_state_qs;
638: end
639:
640: addr_hit[1]: begin
641: reg_rdata_next[31:0] = intr_enable_qs;
642: end
643:
644: addr_hit[2]: begin
645: reg_rdata_next[31:0] = '0;
646: end
647:
648: addr_hit[3]: begin
649: reg_rdata_next[31:0] = data_in_qs;
650: end
651:
652: addr_hit[4]: begin
653: reg_rdata_next[31:0] = direct_out_qs;
654: end
655:
656: addr_hit[5]: begin
657: reg_rdata_next[15:0] = masked_out_lower_data_qs;
658: reg_rdata_next[31:16] = '0;
659: end
660:
661: addr_hit[6]: begin
662: reg_rdata_next[15:0] = masked_out_upper_data_qs;
663: reg_rdata_next[31:16] = '0;
664: end
665:
666: addr_hit[7]: begin
667: reg_rdata_next[31:0] = direct_oe_qs;
668: end
669:
670: addr_hit[8]: begin
671: reg_rdata_next[15:0] = masked_oe_lower_data_qs;
672: reg_rdata_next[31:16] = masked_oe_lower_mask_qs;
673: end
674:
675: addr_hit[9]: begin
676: reg_rdata_next[15:0] = masked_oe_upper_data_qs;
677: reg_rdata_next[31:16] = masked_oe_upper_mask_qs;
678: end
679:
680: addr_hit[10]: begin
681: reg_rdata_next[31:0] = intr_ctrl_en_rising_qs;
682: end
683:
684: addr_hit[11]: begin
685: reg_rdata_next[31:0] = intr_ctrl_en_falling_qs;
686: end
687:
688: addr_hit[12]: begin
689: reg_rdata_next[31:0] = intr_ctrl_en_lvlhigh_qs;
690: end
691:
692: addr_hit[13]: begin
693: reg_rdata_next[31:0] = intr_ctrl_en_lvllow_qs;
694: end
695:
696: addr_hit[14]: begin
697: reg_rdata_next[31:0] = ctrl_en_input_filter_qs;
698: end
699:
700: default: begin
701: reg_rdata_next = '1;
702: end
703: endcase
704: end
705:
706: // Assertions for Register Interface
707: `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
708: `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
709:
710: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
711:
712: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
713:
714: // this is formulated as an assumption such that the FPV testbenches do disprove this
715: // property by mistake
716: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
717:
718: endmodule
719: