hw/top_earlgrey/ip/pinmux/rtl/autogen/pinmux_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: module pinmux_reg_top (
   8:   input clk_i,
   9:   input rst_ni,
  10: 
  11:   // Below Regster interface can be changed
  12:   input  tlul_pkg::tl_h2d_t tl_i,
  13:   output tlul_pkg::tl_d2h_t tl_o,
  14:   // To HW
  15:   output pinmux_reg_pkg::pinmux_reg2hw_t reg2hw, // Write
  16: 
  17:   // Config
  18:   input devmode_i // If 1, explicit error return for unmapped register access
  19: );
  20: 
  21:   import pinmux_reg_pkg::* ;
  22: 
  23:   localparam AW = 6;
  24:   localparam DW = 32;
  25:   localparam DBW = DW/8;                    // Byte Width
  26: 
  27:   // register signals
  28:   logic           reg_we;
  29:   logic           reg_re;
  30:   logic [AW-1:0]  reg_addr;
  31:   logic [DW-1:0]  reg_wdata;
  32:   logic [DBW-1:0] reg_be;
  33:   logic [DW-1:0]  reg_rdata;
  34:   logic           reg_error;
  35: 
  36:   logic          addrmiss, wr_err;
  37: 
  38:   logic [DW-1:0] reg_rdata_next;
  39: 
  40:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  41:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  42: 
  43:   assign tl_reg_h2d = tl_i;
  44:   assign tl_o       = tl_reg_d2h;
  45: 
  46:   tlul_adapter_reg #(
  47:     .RegAw(AW),
  48:     .RegDw(DW)
  49:   ) u_reg_if (
  50:     .clk_i,
  51:     .rst_ni,
  52: 
  53:     .tl_i (tl_reg_h2d),
  54:     .tl_o (tl_reg_d2h),
  55: 
  56:     .we_o    (reg_we),
  57:     .re_o    (reg_re),
  58:     .addr_o  (reg_addr),
  59:     .wdata_o (reg_wdata),
  60:     .be_o    (reg_be),
  61:     .rdata_i (reg_rdata),
  62:     .error_i (reg_error)
  63:   );
  64: 
  65:   assign reg_rdata = reg_rdata_next ;
  66:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  67: 
  68:   // Define SW related signals
  69:   // Format: __{wd|we|qs}
  70:   //        or _{wd|we|qs} if field == 1 or 0
  71:   logic regen_qs;
  72:   logic regen_wd;
  73:   logic regen_we;
  74:   logic [5:0] periph_insel0_in0_qs;
  75:   logic [5:0] periph_insel0_in0_wd;
  76:   logic periph_insel0_in0_we;
  77:   logic [5:0] periph_insel0_in1_qs;
  78:   logic [5:0] periph_insel0_in1_wd;
  79:   logic periph_insel0_in1_we;
  80:   logic [5:0] periph_insel0_in2_qs;
  81:   logic [5:0] periph_insel0_in2_wd;
  82:   logic periph_insel0_in2_we;
  83:   logic [5:0] periph_insel0_in3_qs;
  84:   logic [5:0] periph_insel0_in3_wd;
  85:   logic periph_insel0_in3_we;
  86:   logic [5:0] periph_insel0_in4_qs;
  87:   logic [5:0] periph_insel0_in4_wd;
  88:   logic periph_insel0_in4_we;
  89:   logic [5:0] periph_insel1_in5_qs;
  90:   logic [5:0] periph_insel1_in5_wd;
  91:   logic periph_insel1_in5_we;
  92:   logic [5:0] periph_insel1_in6_qs;
  93:   logic [5:0] periph_insel1_in6_wd;
  94:   logic periph_insel1_in6_we;
  95:   logic [5:0] periph_insel1_in7_qs;
  96:   logic [5:0] periph_insel1_in7_wd;
  97:   logic periph_insel1_in7_we;
  98:   logic [5:0] periph_insel1_in8_qs;
  99:   logic [5:0] periph_insel1_in8_wd;
 100:   logic periph_insel1_in8_we;
 101:   logic [5:0] periph_insel1_in9_qs;
 102:   logic [5:0] periph_insel1_in9_wd;
 103:   logic periph_insel1_in9_we;
 104:   logic [5:0] periph_insel2_in10_qs;
 105:   logic [5:0] periph_insel2_in10_wd;
 106:   logic periph_insel2_in10_we;
 107:   logic [5:0] periph_insel2_in11_qs;
 108:   logic [5:0] periph_insel2_in11_wd;
 109:   logic periph_insel2_in11_we;
 110:   logic [5:0] periph_insel2_in12_qs;
 111:   logic [5:0] periph_insel2_in12_wd;
 112:   logic periph_insel2_in12_we;
 113:   logic [5:0] periph_insel2_in13_qs;
 114:   logic [5:0] periph_insel2_in13_wd;
 115:   logic periph_insel2_in13_we;
 116:   logic [5:0] periph_insel2_in14_qs;
 117:   logic [5:0] periph_insel2_in14_wd;
 118:   logic periph_insel2_in14_we;
 119:   logic [5:0] periph_insel3_in15_qs;
 120:   logic [5:0] periph_insel3_in15_wd;
 121:   logic periph_insel3_in15_we;
 122:   logic [5:0] periph_insel3_in16_qs;
 123:   logic [5:0] periph_insel3_in16_wd;
 124:   logic periph_insel3_in16_we;
 125:   logic [5:0] periph_insel3_in17_qs;
 126:   logic [5:0] periph_insel3_in17_wd;
 127:   logic periph_insel3_in17_we;
 128:   logic [5:0] periph_insel3_in18_qs;
 129:   logic [5:0] periph_insel3_in18_wd;
 130:   logic periph_insel3_in18_we;
 131:   logic [5:0] periph_insel3_in19_qs;
 132:   logic [5:0] periph_insel3_in19_wd;
 133:   logic periph_insel3_in19_we;
 134:   logic [5:0] periph_insel4_in20_qs;
 135:   logic [5:0] periph_insel4_in20_wd;
 136:   logic periph_insel4_in20_we;
 137:   logic [5:0] periph_insel4_in21_qs;
 138:   logic [5:0] periph_insel4_in21_wd;
 139:   logic periph_insel4_in21_we;
 140:   logic [5:0] periph_insel4_in22_qs;
 141:   logic [5:0] periph_insel4_in22_wd;
 142:   logic periph_insel4_in22_we;
 143:   logic [5:0] periph_insel4_in23_qs;
 144:   logic [5:0] periph_insel4_in23_wd;
 145:   logic periph_insel4_in23_we;
 146:   logic [5:0] periph_insel4_in24_qs;
 147:   logic [5:0] periph_insel4_in24_wd;
 148:   logic periph_insel4_in24_we;
 149:   logic [5:0] periph_insel5_in25_qs;
 150:   logic [5:0] periph_insel5_in25_wd;
 151:   logic periph_insel5_in25_we;
 152:   logic [5:0] periph_insel5_in26_qs;
 153:   logic [5:0] periph_insel5_in26_wd;
 154:   logic periph_insel5_in26_we;
 155:   logic [5:0] periph_insel5_in27_qs;
 156:   logic [5:0] periph_insel5_in27_wd;
 157:   logic periph_insel5_in27_we;
 158:   logic [5:0] periph_insel5_in28_qs;
 159:   logic [5:0] periph_insel5_in28_wd;
 160:   logic periph_insel5_in28_we;
 161:   logic [5:0] periph_insel5_in29_qs;
 162:   logic [5:0] periph_insel5_in29_wd;
 163:   logic periph_insel5_in29_we;
 164:   logic [5:0] periph_insel6_in30_qs;
 165:   logic [5:0] periph_insel6_in30_wd;
 166:   logic periph_insel6_in30_we;
 167:   logic [5:0] periph_insel6_in31_qs;
 168:   logic [5:0] periph_insel6_in31_wd;
 169:   logic periph_insel6_in31_we;
 170:   logic [5:0] mio_outsel0_out0_qs;
 171:   logic [5:0] mio_outsel0_out0_wd;
 172:   logic mio_outsel0_out0_we;
 173:   logic [5:0] mio_outsel0_out1_qs;
 174:   logic [5:0] mio_outsel0_out1_wd;
 175:   logic mio_outsel0_out1_we;
 176:   logic [5:0] mio_outsel0_out2_qs;
 177:   logic [5:0] mio_outsel0_out2_wd;
 178:   logic mio_outsel0_out2_we;
 179:   logic [5:0] mio_outsel0_out3_qs;
 180:   logic [5:0] mio_outsel0_out3_wd;
 181:   logic mio_outsel0_out3_we;
 182:   logic [5:0] mio_outsel0_out4_qs;
 183:   logic [5:0] mio_outsel0_out4_wd;
 184:   logic mio_outsel0_out4_we;
 185:   logic [5:0] mio_outsel1_out5_qs;
 186:   logic [5:0] mio_outsel1_out5_wd;
 187:   logic mio_outsel1_out5_we;
 188:   logic [5:0] mio_outsel1_out6_qs;
 189:   logic [5:0] mio_outsel1_out6_wd;
 190:   logic mio_outsel1_out6_we;
 191:   logic [5:0] mio_outsel1_out7_qs;
 192:   logic [5:0] mio_outsel1_out7_wd;
 193:   logic mio_outsel1_out7_we;
 194:   logic [5:0] mio_outsel1_out8_qs;
 195:   logic [5:0] mio_outsel1_out8_wd;
 196:   logic mio_outsel1_out8_we;
 197:   logic [5:0] mio_outsel1_out9_qs;
 198:   logic [5:0] mio_outsel1_out9_wd;
 199:   logic mio_outsel1_out9_we;
 200:   logic [5:0] mio_outsel2_out10_qs;
 201:   logic [5:0] mio_outsel2_out10_wd;
 202:   logic mio_outsel2_out10_we;
 203:   logic [5:0] mio_outsel2_out11_qs;
 204:   logic [5:0] mio_outsel2_out11_wd;
 205:   logic mio_outsel2_out11_we;
 206:   logic [5:0] mio_outsel2_out12_qs;
 207:   logic [5:0] mio_outsel2_out12_wd;
 208:   logic mio_outsel2_out12_we;
 209:   logic [5:0] mio_outsel2_out13_qs;
 210:   logic [5:0] mio_outsel2_out13_wd;
 211:   logic mio_outsel2_out13_we;
 212:   logic [5:0] mio_outsel2_out14_qs;
 213:   logic [5:0] mio_outsel2_out14_wd;
 214:   logic mio_outsel2_out14_we;
 215:   logic [5:0] mio_outsel3_out15_qs;
 216:   logic [5:0] mio_outsel3_out15_wd;
 217:   logic mio_outsel3_out15_we;
 218:   logic [5:0] mio_outsel3_out16_qs;
 219:   logic [5:0] mio_outsel3_out16_wd;
 220:   logic mio_outsel3_out16_we;
 221:   logic [5:0] mio_outsel3_out17_qs;
 222:   logic [5:0] mio_outsel3_out17_wd;
 223:   logic mio_outsel3_out17_we;
 224:   logic [5:0] mio_outsel3_out18_qs;
 225:   logic [5:0] mio_outsel3_out18_wd;
 226:   logic mio_outsel3_out18_we;
 227:   logic [5:0] mio_outsel3_out19_qs;
 228:   logic [5:0] mio_outsel3_out19_wd;
 229:   logic mio_outsel3_out19_we;
 230:   logic [5:0] mio_outsel4_out20_qs;
 231:   logic [5:0] mio_outsel4_out20_wd;
 232:   logic mio_outsel4_out20_we;
 233:   logic [5:0] mio_outsel4_out21_qs;
 234:   logic [5:0] mio_outsel4_out21_wd;
 235:   logic mio_outsel4_out21_we;
 236:   logic [5:0] mio_outsel4_out22_qs;
 237:   logic [5:0] mio_outsel4_out22_wd;
 238:   logic mio_outsel4_out22_we;
 239:   logic [5:0] mio_outsel4_out23_qs;
 240:   logic [5:0] mio_outsel4_out23_wd;
 241:   logic mio_outsel4_out23_we;
 242:   logic [5:0] mio_outsel4_out24_qs;
 243:   logic [5:0] mio_outsel4_out24_wd;
 244:   logic mio_outsel4_out24_we;
 245:   logic [5:0] mio_outsel5_out25_qs;
 246:   logic [5:0] mio_outsel5_out25_wd;
 247:   logic mio_outsel5_out25_we;
 248:   logic [5:0] mio_outsel5_out26_qs;
 249:   logic [5:0] mio_outsel5_out26_wd;
 250:   logic mio_outsel5_out26_we;
 251:   logic [5:0] mio_outsel5_out27_qs;
 252:   logic [5:0] mio_outsel5_out27_wd;
 253:   logic mio_outsel5_out27_we;
 254:   logic [5:0] mio_outsel5_out28_qs;
 255:   logic [5:0] mio_outsel5_out28_wd;
 256:   logic mio_outsel5_out28_we;
 257:   logic [5:0] mio_outsel5_out29_qs;
 258:   logic [5:0] mio_outsel5_out29_wd;
 259:   logic mio_outsel5_out29_we;
 260:   logic [5:0] mio_outsel6_out30_qs;
 261:   logic [5:0] mio_outsel6_out30_wd;
 262:   logic mio_outsel6_out30_we;
 263:   logic [5:0] mio_outsel6_out31_qs;
 264:   logic [5:0] mio_outsel6_out31_wd;
 265:   logic mio_outsel6_out31_we;
 266: 
 267:   // Register instances
 268:   // R[regen]: V(False)
 269: 
 270:   prim_subreg #(
 271:     .DW      (1),
 272:     .SWACCESS("W0C"),
 273:     .RESVAL  (1'h1)
 274:   ) u_regen (
 275:     .clk_i   (clk_i    ),
 276:     .rst_ni  (rst_ni  ),
 277: 
 278:     // from register interface
 279:     .we     (regen_we),
 280:     .wd     (regen_wd),
 281: 
 282:     // from internal hardware
 283:     .de     (1'b0),
 284:     .d      ('0  ),
 285: 
 286:     // to internal hardware
 287:     .qe     (),
 288:     .q      (),
 289: 
 290:     // to register interface (read)
 291:     .qs     (regen_qs)
 292:   );
 293: 
 294: 
 295: 
 296:   // Subregister 0 of Multireg periph_insel
 297:   // R[periph_insel0]: V(False)
 298: 
 299:   // F[in0]: 5:0
 300:   prim_subreg #(
 301:     .DW      (6),
 302:     .SWACCESS("RW"),
 303:     .RESVAL  (6'h0)
 304:   ) u_periph_insel0_in0 (
 305:     .clk_i   (clk_i    ),
 306:     .rst_ni  (rst_ni  ),
 307: 
 308:     // from register interface (qualified with register enable)
 309:     .we     (periph_insel0_in0_we & regen_qs),
 310:     .wd     (periph_insel0_in0_wd),
 311: 
 312:     // from internal hardware
 313:     .de     (1'b0),
 314:     .d      ('0  ),
 315: 
 316:     // to internal hardware
 317:     .qe     (),
 318:     .q      (reg2hw.periph_insel[0].q ),
 319: 
 320:     // to register interface (read)
 321:     .qs     (periph_insel0_in0_qs)
 322:   );
 323: 
 324: 
 325:   // F[in1]: 11:6
 326:   prim_subreg #(
 327:     .DW      (6),
 328:     .SWACCESS("RW"),
 329:     .RESVAL  (6'h0)
 330:   ) u_periph_insel0_in1 (
 331:     .clk_i   (clk_i    ),
 332:     .rst_ni  (rst_ni  ),
 333: 
 334:     // from register interface (qualified with register enable)
 335:     .we     (periph_insel0_in1_we & regen_qs),
 336:     .wd     (periph_insel0_in1_wd),
 337: 
 338:     // from internal hardware
 339:     .de     (1'b0),
 340:     .d      ('0  ),
 341: 
 342:     // to internal hardware
 343:     .qe     (),
 344:     .q      (reg2hw.periph_insel[1].q ),
 345: 
 346:     // to register interface (read)
 347:     .qs     (periph_insel0_in1_qs)
 348:   );
 349: 
 350: 
 351:   // F[in2]: 17:12
 352:   prim_subreg #(
 353:     .DW      (6),
 354:     .SWACCESS("RW"),
 355:     .RESVAL  (6'h0)
 356:   ) u_periph_insel0_in2 (
 357:     .clk_i   (clk_i    ),
 358:     .rst_ni  (rst_ni  ),
 359: 
 360:     // from register interface (qualified with register enable)
 361:     .we     (periph_insel0_in2_we & regen_qs),
 362:     .wd     (periph_insel0_in2_wd),
 363: 
 364:     // from internal hardware
 365:     .de     (1'b0),
 366:     .d      ('0  ),
 367: 
 368:     // to internal hardware
 369:     .qe     (),
 370:     .q      (reg2hw.periph_insel[2].q ),
 371: 
 372:     // to register interface (read)
 373:     .qs     (periph_insel0_in2_qs)
 374:   );
 375: 
 376: 
 377:   // F[in3]: 23:18
 378:   prim_subreg #(
 379:     .DW      (6),
 380:     .SWACCESS("RW"),
 381:     .RESVAL  (6'h0)
 382:   ) u_periph_insel0_in3 (
 383:     .clk_i   (clk_i    ),
 384:     .rst_ni  (rst_ni  ),
 385: 
 386:     // from register interface (qualified with register enable)
 387:     .we     (periph_insel0_in3_we & regen_qs),
 388:     .wd     (periph_insel0_in3_wd),
 389: 
 390:     // from internal hardware
 391:     .de     (1'b0),
 392:     .d      ('0  ),
 393: 
 394:     // to internal hardware
 395:     .qe     (),
 396:     .q      (reg2hw.periph_insel[3].q ),
 397: 
 398:     // to register interface (read)
 399:     .qs     (periph_insel0_in3_qs)
 400:   );
 401: 
 402: 
 403:   // F[in4]: 29:24
 404:   prim_subreg #(
 405:     .DW      (6),
 406:     .SWACCESS("RW"),
 407:     .RESVAL  (6'h0)
 408:   ) u_periph_insel0_in4 (
 409:     .clk_i   (clk_i    ),
 410:     .rst_ni  (rst_ni  ),
 411: 
 412:     // from register interface (qualified with register enable)
 413:     .we     (periph_insel0_in4_we & regen_qs),
 414:     .wd     (periph_insel0_in4_wd),
 415: 
 416:     // from internal hardware
 417:     .de     (1'b0),
 418:     .d      ('0  ),
 419: 
 420:     // to internal hardware
 421:     .qe     (),
 422:     .q      (reg2hw.periph_insel[4].q ),
 423: 
 424:     // to register interface (read)
 425:     .qs     (periph_insel0_in4_qs)
 426:   );
 427: 
 428: 
 429:   // Subregister 5 of Multireg periph_insel
 430:   // R[periph_insel1]: V(False)
 431: 
 432:   // F[in5]: 5:0
 433:   prim_subreg #(
 434:     .DW      (6),
 435:     .SWACCESS("RW"),
 436:     .RESVAL  (6'h0)
 437:   ) u_periph_insel1_in5 (
 438:     .clk_i   (clk_i    ),
 439:     .rst_ni  (rst_ni  ),
 440: 
 441:     // from register interface (qualified with register enable)
 442:     .we     (periph_insel1_in5_we & regen_qs),
 443:     .wd     (periph_insel1_in5_wd),
 444: 
 445:     // from internal hardware
 446:     .de     (1'b0),
 447:     .d      ('0  ),
 448: 
 449:     // to internal hardware
 450:     .qe     (),
 451:     .q      (reg2hw.periph_insel[5].q ),
 452: 
 453:     // to register interface (read)
 454:     .qs     (periph_insel1_in5_qs)
 455:   );
 456: 
 457: 
 458:   // F[in6]: 11:6
 459:   prim_subreg #(
 460:     .DW      (6),
 461:     .SWACCESS("RW"),
 462:     .RESVAL  (6'h0)
 463:   ) u_periph_insel1_in6 (
 464:     .clk_i   (clk_i    ),
 465:     .rst_ni  (rst_ni  ),
 466: 
 467:     // from register interface (qualified with register enable)
 468:     .we     (periph_insel1_in6_we & regen_qs),
 469:     .wd     (periph_insel1_in6_wd),
 470: 
 471:     // from internal hardware
 472:     .de     (1'b0),
 473:     .d      ('0  ),
 474: 
 475:     // to internal hardware
 476:     .qe     (),
 477:     .q      (reg2hw.periph_insel[6].q ),
 478: 
 479:     // to register interface (read)
 480:     .qs     (periph_insel1_in6_qs)
 481:   );
 482: 
 483: 
 484:   // F[in7]: 17:12
 485:   prim_subreg #(
 486:     .DW      (6),
 487:     .SWACCESS("RW"),
 488:     .RESVAL  (6'h0)
 489:   ) u_periph_insel1_in7 (
 490:     .clk_i   (clk_i    ),
 491:     .rst_ni  (rst_ni  ),
 492: 
 493:     // from register interface (qualified with register enable)
 494:     .we     (periph_insel1_in7_we & regen_qs),
 495:     .wd     (periph_insel1_in7_wd),
 496: 
 497:     // from internal hardware
 498:     .de     (1'b0),
 499:     .d      ('0  ),
 500: 
 501:     // to internal hardware
 502:     .qe     (),
 503:     .q      (reg2hw.periph_insel[7].q ),
 504: 
 505:     // to register interface (read)
 506:     .qs     (periph_insel1_in7_qs)
 507:   );
 508: 
 509: 
 510:   // F[in8]: 23:18
 511:   prim_subreg #(
 512:     .DW      (6),
 513:     .SWACCESS("RW"),
 514:     .RESVAL  (6'h0)
 515:   ) u_periph_insel1_in8 (
 516:     .clk_i   (clk_i    ),
 517:     .rst_ni  (rst_ni  ),
 518: 
 519:     // from register interface (qualified with register enable)
 520:     .we     (periph_insel1_in8_we & regen_qs),
 521:     .wd     (periph_insel1_in8_wd),
 522: 
 523:     // from internal hardware
 524:     .de     (1'b0),
 525:     .d      ('0  ),
 526: 
 527:     // to internal hardware
 528:     .qe     (),
 529:     .q      (reg2hw.periph_insel[8].q ),
 530: 
 531:     // to register interface (read)
 532:     .qs     (periph_insel1_in8_qs)
 533:   );
 534: 
 535: 
 536:   // F[in9]: 29:24
 537:   prim_subreg #(
 538:     .DW      (6),
 539:     .SWACCESS("RW"),
 540:     .RESVAL  (6'h0)
 541:   ) u_periph_insel1_in9 (
 542:     .clk_i   (clk_i    ),
 543:     .rst_ni  (rst_ni  ),
 544: 
 545:     // from register interface (qualified with register enable)
 546:     .we     (periph_insel1_in9_we & regen_qs),
 547:     .wd     (periph_insel1_in9_wd),
 548: 
 549:     // from internal hardware
 550:     .de     (1'b0),
 551:     .d      ('0  ),
 552: 
 553:     // to internal hardware
 554:     .qe     (),
 555:     .q      (reg2hw.periph_insel[9].q ),
 556: 
 557:     // to register interface (read)
 558:     .qs     (periph_insel1_in9_qs)
 559:   );
 560: 
 561: 
 562:   // Subregister 10 of Multireg periph_insel
 563:   // R[periph_insel2]: V(False)
 564: 
 565:   // F[in10]: 5:0
 566:   prim_subreg #(
 567:     .DW      (6),
 568:     .SWACCESS("RW"),
 569:     .RESVAL  (6'h0)
 570:   ) u_periph_insel2_in10 (
 571:     .clk_i   (clk_i    ),
 572:     .rst_ni  (rst_ni  ),
 573: 
 574:     // from register interface (qualified with register enable)
 575:     .we     (periph_insel2_in10_we & regen_qs),
 576:     .wd     (periph_insel2_in10_wd),
 577: 
 578:     // from internal hardware
 579:     .de     (1'b0),
 580:     .d      ('0  ),
 581: 
 582:     // to internal hardware
 583:     .qe     (),
 584:     .q      (reg2hw.periph_insel[10].q ),
 585: 
 586:     // to register interface (read)
 587:     .qs     (periph_insel2_in10_qs)
 588:   );
 589: 
 590: 
 591:   // F[in11]: 11:6
 592:   prim_subreg #(
 593:     .DW      (6),
 594:     .SWACCESS("RW"),
 595:     .RESVAL  (6'h0)
 596:   ) u_periph_insel2_in11 (
 597:     .clk_i   (clk_i    ),
 598:     .rst_ni  (rst_ni  ),
 599: 
 600:     // from register interface (qualified with register enable)
 601:     .we     (periph_insel2_in11_we & regen_qs),
 602:     .wd     (periph_insel2_in11_wd),
 603: 
 604:     // from internal hardware
 605:     .de     (1'b0),
 606:     .d      ('0  ),
 607: 
 608:     // to internal hardware
 609:     .qe     (),
 610:     .q      (reg2hw.periph_insel[11].q ),
 611: 
 612:     // to register interface (read)
 613:     .qs     (periph_insel2_in11_qs)
 614:   );
 615: 
 616: 
 617:   // F[in12]: 17:12
 618:   prim_subreg #(
 619:     .DW      (6),
 620:     .SWACCESS("RW"),
 621:     .RESVAL  (6'h0)
 622:   ) u_periph_insel2_in12 (
 623:     .clk_i   (clk_i    ),
 624:     .rst_ni  (rst_ni  ),
 625: 
 626:     // from register interface (qualified with register enable)
 627:     .we     (periph_insel2_in12_we & regen_qs),
 628:     .wd     (periph_insel2_in12_wd),
 629: 
 630:     // from internal hardware
 631:     .de     (1'b0),
 632:     .d      ('0  ),
 633: 
 634:     // to internal hardware
 635:     .qe     (),
 636:     .q      (reg2hw.periph_insel[12].q ),
 637: 
 638:     // to register interface (read)
 639:     .qs     (periph_insel2_in12_qs)
 640:   );
 641: 
 642: 
 643:   // F[in13]: 23:18
 644:   prim_subreg #(
 645:     .DW      (6),
 646:     .SWACCESS("RW"),
 647:     .RESVAL  (6'h0)
 648:   ) u_periph_insel2_in13 (
 649:     .clk_i   (clk_i    ),
 650:     .rst_ni  (rst_ni  ),
 651: 
 652:     // from register interface (qualified with register enable)
 653:     .we     (periph_insel2_in13_we & regen_qs),
 654:     .wd     (periph_insel2_in13_wd),
 655: 
 656:     // from internal hardware
 657:     .de     (1'b0),
 658:     .d      ('0  ),
 659: 
 660:     // to internal hardware
 661:     .qe     (),
 662:     .q      (reg2hw.periph_insel[13].q ),
 663: 
 664:     // to register interface (read)
 665:     .qs     (periph_insel2_in13_qs)
 666:   );
 667: 
 668: 
 669:   // F[in14]: 29:24
 670:   prim_subreg #(
 671:     .DW      (6),
 672:     .SWACCESS("RW"),
 673:     .RESVAL  (6'h0)
 674:   ) u_periph_insel2_in14 (
 675:     .clk_i   (clk_i    ),
 676:     .rst_ni  (rst_ni  ),
 677: 
 678:     // from register interface (qualified with register enable)
 679:     .we     (periph_insel2_in14_we & regen_qs),
 680:     .wd     (periph_insel2_in14_wd),
 681: 
 682:     // from internal hardware
 683:     .de     (1'b0),
 684:     .d      ('0  ),
 685: 
 686:     // to internal hardware
 687:     .qe     (),
 688:     .q      (reg2hw.periph_insel[14].q ),
 689: 
 690:     // to register interface (read)
 691:     .qs     (periph_insel2_in14_qs)
 692:   );
 693: 
 694: 
 695:   // Subregister 15 of Multireg periph_insel
 696:   // R[periph_insel3]: V(False)
 697: 
 698:   // F[in15]: 5:0
 699:   prim_subreg #(
 700:     .DW      (6),
 701:     .SWACCESS("RW"),
 702:     .RESVAL  (6'h0)
 703:   ) u_periph_insel3_in15 (
 704:     .clk_i   (clk_i    ),
 705:     .rst_ni  (rst_ni  ),
 706: 
 707:     // from register interface (qualified with register enable)
 708:     .we     (periph_insel3_in15_we & regen_qs),
 709:     .wd     (periph_insel3_in15_wd),
 710: 
 711:     // from internal hardware
 712:     .de     (1'b0),
 713:     .d      ('0  ),
 714: 
 715:     // to internal hardware
 716:     .qe     (),
 717:     .q      (reg2hw.periph_insel[15].q ),
 718: 
 719:     // to register interface (read)
 720:     .qs     (periph_insel3_in15_qs)
 721:   );
 722: 
 723: 
 724:   // F[in16]: 11:6
 725:   prim_subreg #(
 726:     .DW      (6),
 727:     .SWACCESS("RW"),
 728:     .RESVAL  (6'h0)
 729:   ) u_periph_insel3_in16 (
 730:     .clk_i   (clk_i    ),
 731:     .rst_ni  (rst_ni  ),
 732: 
 733:     // from register interface (qualified with register enable)
 734:     .we     (periph_insel3_in16_we & regen_qs),
 735:     .wd     (periph_insel3_in16_wd),
 736: 
 737:     // from internal hardware
 738:     .de     (1'b0),
 739:     .d      ('0  ),
 740: 
 741:     // to internal hardware
 742:     .qe     (),
 743:     .q      (reg2hw.periph_insel[16].q ),
 744: 
 745:     // to register interface (read)
 746:     .qs     (periph_insel3_in16_qs)
 747:   );
 748: 
 749: 
 750:   // F[in17]: 17:12
 751:   prim_subreg #(
 752:     .DW      (6),
 753:     .SWACCESS("RW"),
 754:     .RESVAL  (6'h0)
 755:   ) u_periph_insel3_in17 (
 756:     .clk_i   (clk_i    ),
 757:     .rst_ni  (rst_ni  ),
 758: 
 759:     // from register interface (qualified with register enable)
 760:     .we     (periph_insel3_in17_we & regen_qs),
 761:     .wd     (periph_insel3_in17_wd),
 762: 
 763:     // from internal hardware
 764:     .de     (1'b0),
 765:     .d      ('0  ),
 766: 
 767:     // to internal hardware
 768:     .qe     (),
 769:     .q      (reg2hw.periph_insel[17].q ),
 770: 
 771:     // to register interface (read)
 772:     .qs     (periph_insel3_in17_qs)
 773:   );
 774: 
 775: 
 776:   // F[in18]: 23:18
 777:   prim_subreg #(
 778:     .DW      (6),
 779:     .SWACCESS("RW"),
 780:     .RESVAL  (6'h0)
 781:   ) u_periph_insel3_in18 (
 782:     .clk_i   (clk_i    ),
 783:     .rst_ni  (rst_ni  ),
 784: 
 785:     // from register interface (qualified with register enable)
 786:     .we     (periph_insel3_in18_we & regen_qs),
 787:     .wd     (periph_insel3_in18_wd),
 788: 
 789:     // from internal hardware
 790:     .de     (1'b0),
 791:     .d      ('0  ),
 792: 
 793:     // to internal hardware
 794:     .qe     (),
 795:     .q      (reg2hw.periph_insel[18].q ),
 796: 
 797:     // to register interface (read)
 798:     .qs     (periph_insel3_in18_qs)
 799:   );
 800: 
 801: 
 802:   // F[in19]: 29:24
 803:   prim_subreg #(
 804:     .DW      (6),
 805:     .SWACCESS("RW"),
 806:     .RESVAL  (6'h0)
 807:   ) u_periph_insel3_in19 (
 808:     .clk_i   (clk_i    ),
 809:     .rst_ni  (rst_ni  ),
 810: 
 811:     // from register interface (qualified with register enable)
 812:     .we     (periph_insel3_in19_we & regen_qs),
 813:     .wd     (periph_insel3_in19_wd),
 814: 
 815:     // from internal hardware
 816:     .de     (1'b0),
 817:     .d      ('0  ),
 818: 
 819:     // to internal hardware
 820:     .qe     (),
 821:     .q      (reg2hw.periph_insel[19].q ),
 822: 
 823:     // to register interface (read)
 824:     .qs     (periph_insel3_in19_qs)
 825:   );
 826: 
 827: 
 828:   // Subregister 20 of Multireg periph_insel
 829:   // R[periph_insel4]: V(False)
 830: 
 831:   // F[in20]: 5:0
 832:   prim_subreg #(
 833:     .DW      (6),
 834:     .SWACCESS("RW"),
 835:     .RESVAL  (6'h0)
 836:   ) u_periph_insel4_in20 (
 837:     .clk_i   (clk_i    ),
 838:     .rst_ni  (rst_ni  ),
 839: 
 840:     // from register interface (qualified with register enable)
 841:     .we     (periph_insel4_in20_we & regen_qs),
 842:     .wd     (periph_insel4_in20_wd),
 843: 
 844:     // from internal hardware
 845:     .de     (1'b0),
 846:     .d      ('0  ),
 847: 
 848:     // to internal hardware
 849:     .qe     (),
 850:     .q      (reg2hw.periph_insel[20].q ),
 851: 
 852:     // to register interface (read)
 853:     .qs     (periph_insel4_in20_qs)
 854:   );
 855: 
 856: 
 857:   // F[in21]: 11:6
 858:   prim_subreg #(
 859:     .DW      (6),
 860:     .SWACCESS("RW"),
 861:     .RESVAL  (6'h0)
 862:   ) u_periph_insel4_in21 (
 863:     .clk_i   (clk_i    ),
 864:     .rst_ni  (rst_ni  ),
 865: 
 866:     // from register interface (qualified with register enable)
 867:     .we     (periph_insel4_in21_we & regen_qs),
 868:     .wd     (periph_insel4_in21_wd),
 869: 
 870:     // from internal hardware
 871:     .de     (1'b0),
 872:     .d      ('0  ),
 873: 
 874:     // to internal hardware
 875:     .qe     (),
 876:     .q      (reg2hw.periph_insel[21].q ),
 877: 
 878:     // to register interface (read)
 879:     .qs     (periph_insel4_in21_qs)
 880:   );
 881: 
 882: 
 883:   // F[in22]: 17:12
 884:   prim_subreg #(
 885:     .DW      (6),
 886:     .SWACCESS("RW"),
 887:     .RESVAL  (6'h0)
 888:   ) u_periph_insel4_in22 (
 889:     .clk_i   (clk_i    ),
 890:     .rst_ni  (rst_ni  ),
 891: 
 892:     // from register interface (qualified with register enable)
 893:     .we     (periph_insel4_in22_we & regen_qs),
 894:     .wd     (periph_insel4_in22_wd),
 895: 
 896:     // from internal hardware
 897:     .de     (1'b0),
 898:     .d      ('0  ),
 899: 
 900:     // to internal hardware
 901:     .qe     (),
 902:     .q      (reg2hw.periph_insel[22].q ),
 903: 
 904:     // to register interface (read)
 905:     .qs     (periph_insel4_in22_qs)
 906:   );
 907: 
 908: 
 909:   // F[in23]: 23:18
 910:   prim_subreg #(
 911:     .DW      (6),
 912:     .SWACCESS("RW"),
 913:     .RESVAL  (6'h0)
 914:   ) u_periph_insel4_in23 (
 915:     .clk_i   (clk_i    ),
 916:     .rst_ni  (rst_ni  ),
 917: 
 918:     // from register interface (qualified with register enable)
 919:     .we     (periph_insel4_in23_we & regen_qs),
 920:     .wd     (periph_insel4_in23_wd),
 921: 
 922:     // from internal hardware
 923:     .de     (1'b0),
 924:     .d      ('0  ),
 925: 
 926:     // to internal hardware
 927:     .qe     (),
 928:     .q      (reg2hw.periph_insel[23].q ),
 929: 
 930:     // to register interface (read)
 931:     .qs     (periph_insel4_in23_qs)
 932:   );
 933: 
 934: 
 935:   // F[in24]: 29:24
 936:   prim_subreg #(
 937:     .DW      (6),
 938:     .SWACCESS("RW"),
 939:     .RESVAL  (6'h0)
 940:   ) u_periph_insel4_in24 (
 941:     .clk_i   (clk_i    ),
 942:     .rst_ni  (rst_ni  ),
 943: 
 944:     // from register interface (qualified with register enable)
 945:     .we     (periph_insel4_in24_we & regen_qs),
 946:     .wd     (periph_insel4_in24_wd),
 947: 
 948:     // from internal hardware
 949:     .de     (1'b0),
 950:     .d      ('0  ),
 951: 
 952:     // to internal hardware
 953:     .qe     (),
 954:     .q      (reg2hw.periph_insel[24].q ),
 955: 
 956:     // to register interface (read)
 957:     .qs     (periph_insel4_in24_qs)
 958:   );
 959: 
 960: 
 961:   // Subregister 25 of Multireg periph_insel
 962:   // R[periph_insel5]: V(False)
 963: 
 964:   // F[in25]: 5:0
 965:   prim_subreg #(
 966:     .DW      (6),
 967:     .SWACCESS("RW"),
 968:     .RESVAL  (6'h0)
 969:   ) u_periph_insel5_in25 (
 970:     .clk_i   (clk_i    ),
 971:     .rst_ni  (rst_ni  ),
 972: 
 973:     // from register interface (qualified with register enable)
 974:     .we     (periph_insel5_in25_we & regen_qs),
 975:     .wd     (periph_insel5_in25_wd),
 976: 
 977:     // from internal hardware
 978:     .de     (1'b0),
 979:     .d      ('0  ),
 980: 
 981:     // to internal hardware
 982:     .qe     (),
 983:     .q      (reg2hw.periph_insel[25].q ),
 984: 
 985:     // to register interface (read)
 986:     .qs     (periph_insel5_in25_qs)
 987:   );
 988: 
 989: 
 990:   // F[in26]: 11:6
 991:   prim_subreg #(
 992:     .DW      (6),
 993:     .SWACCESS("RW"),
 994:     .RESVAL  (6'h0)
 995:   ) u_periph_insel5_in26 (
 996:     .clk_i   (clk_i    ),
 997:     .rst_ni  (rst_ni  ),
 998: 
 999:     // from register interface (qualified with register enable)
1000:     .we     (periph_insel5_in26_we & regen_qs),
1001:     .wd     (periph_insel5_in26_wd),
1002: 
1003:     // from internal hardware
1004:     .de     (1'b0),
1005:     .d      ('0  ),
1006: 
1007:     // to internal hardware
1008:     .qe     (),
1009:     .q      (reg2hw.periph_insel[26].q ),
1010: 
1011:     // to register interface (read)
1012:     .qs     (periph_insel5_in26_qs)
1013:   );
1014: 
1015: 
1016:   // F[in27]: 17:12
1017:   prim_subreg #(
1018:     .DW      (6),
1019:     .SWACCESS("RW"),
1020:     .RESVAL  (6'h0)
1021:   ) u_periph_insel5_in27 (
1022:     .clk_i   (clk_i    ),
1023:     .rst_ni  (rst_ni  ),
1024: 
1025:     // from register interface (qualified with register enable)
1026:     .we     (periph_insel5_in27_we & regen_qs),
1027:     .wd     (periph_insel5_in27_wd),
1028: 
1029:     // from internal hardware
1030:     .de     (1'b0),
1031:     .d      ('0  ),
1032: 
1033:     // to internal hardware
1034:     .qe     (),
1035:     .q      (reg2hw.periph_insel[27].q ),
1036: 
1037:     // to register interface (read)
1038:     .qs     (periph_insel5_in27_qs)
1039:   );
1040: 
1041: 
1042:   // F[in28]: 23:18
1043:   prim_subreg #(
1044:     .DW      (6),
1045:     .SWACCESS("RW"),
1046:     .RESVAL  (6'h0)
1047:   ) u_periph_insel5_in28 (
1048:     .clk_i   (clk_i    ),
1049:     .rst_ni  (rst_ni  ),
1050: 
1051:     // from register interface (qualified with register enable)
1052:     .we     (periph_insel5_in28_we & regen_qs),
1053:     .wd     (periph_insel5_in28_wd),
1054: 
1055:     // from internal hardware
1056:     .de     (1'b0),
1057:     .d      ('0  ),
1058: 
1059:     // to internal hardware
1060:     .qe     (),
1061:     .q      (reg2hw.periph_insel[28].q ),
1062: 
1063:     // to register interface (read)
1064:     .qs     (periph_insel5_in28_qs)
1065:   );
1066: 
1067: 
1068:   // F[in29]: 29:24
1069:   prim_subreg #(
1070:     .DW      (6),
1071:     .SWACCESS("RW"),
1072:     .RESVAL  (6'h0)
1073:   ) u_periph_insel5_in29 (
1074:     .clk_i   (clk_i    ),
1075:     .rst_ni  (rst_ni  ),
1076: 
1077:     // from register interface (qualified with register enable)
1078:     .we     (periph_insel5_in29_we & regen_qs),
1079:     .wd     (periph_insel5_in29_wd),
1080: 
1081:     // from internal hardware
1082:     .de     (1'b0),
1083:     .d      ('0  ),
1084: 
1085:     // to internal hardware
1086:     .qe     (),
1087:     .q      (reg2hw.periph_insel[29].q ),
1088: 
1089:     // to register interface (read)
1090:     .qs     (periph_insel5_in29_qs)
1091:   );
1092: 
1093: 
1094:   // Subregister 30 of Multireg periph_insel
1095:   // R[periph_insel6]: V(False)
1096: 
1097:   // F[in30]: 5:0
1098:   prim_subreg #(
1099:     .DW      (6),
1100:     .SWACCESS("RW"),
1101:     .RESVAL  (6'h0)
1102:   ) u_periph_insel6_in30 (
1103:     .clk_i   (clk_i    ),
1104:     .rst_ni  (rst_ni  ),
1105: 
1106:     // from register interface (qualified with register enable)
1107:     .we     (periph_insel6_in30_we & regen_qs),
1108:     .wd     (periph_insel6_in30_wd),
1109: 
1110:     // from internal hardware
1111:     .de     (1'b0),
1112:     .d      ('0  ),
1113: 
1114:     // to internal hardware
1115:     .qe     (),
1116:     .q      (reg2hw.periph_insel[30].q ),
1117: 
1118:     // to register interface (read)
1119:     .qs     (periph_insel6_in30_qs)
1120:   );
1121: 
1122: 
1123:   // F[in31]: 11:6
1124:   prim_subreg #(
1125:     .DW      (6),
1126:     .SWACCESS("RW"),
1127:     .RESVAL  (6'h0)
1128:   ) u_periph_insel6_in31 (
1129:     .clk_i   (clk_i    ),
1130:     .rst_ni  (rst_ni  ),
1131: 
1132:     // from register interface (qualified with register enable)
1133:     .we     (periph_insel6_in31_we & regen_qs),
1134:     .wd     (periph_insel6_in31_wd),
1135: 
1136:     // from internal hardware
1137:     .de     (1'b0),
1138:     .d      ('0  ),
1139: 
1140:     // to internal hardware
1141:     .qe     (),
1142:     .q      (reg2hw.periph_insel[31].q ),
1143: 
1144:     // to register interface (read)
1145:     .qs     (periph_insel6_in31_qs)
1146:   );
1147: 
1148: 
1149: 
1150: 
1151:   // Subregister 0 of Multireg mio_outsel
1152:   // R[mio_outsel0]: V(False)
1153: 
1154:   // F[out0]: 5:0
1155:   prim_subreg #(
1156:     .DW      (6),
1157:     .SWACCESS("RW"),
1158:     .RESVAL  (6'h2)
1159:   ) u_mio_outsel0_out0 (
1160:     .clk_i   (clk_i    ),
1161:     .rst_ni  (rst_ni  ),
1162: 
1163:     // from register interface (qualified with register enable)
1164:     .we     (mio_outsel0_out0_we & regen_qs),
1165:     .wd     (mio_outsel0_out0_wd),
1166: 
1167:     // from internal hardware
1168:     .de     (1'b0),
1169:     .d      ('0  ),
1170: 
1171:     // to internal hardware
1172:     .qe     (),
1173:     .q      (reg2hw.mio_outsel[0].q ),
1174: 
1175:     // to register interface (read)
1176:     .qs     (mio_outsel0_out0_qs)
1177:   );
1178: 
1179: 
1180:   // F[out1]: 11:6
1181:   prim_subreg #(
1182:     .DW      (6),
1183:     .SWACCESS("RW"),
1184:     .RESVAL  (6'h2)
1185:   ) u_mio_outsel0_out1 (
1186:     .clk_i   (clk_i    ),
1187:     .rst_ni  (rst_ni  ),
1188: 
1189:     // from register interface (qualified with register enable)
1190:     .we     (mio_outsel0_out1_we & regen_qs),
1191:     .wd     (mio_outsel0_out1_wd),
1192: 
1193:     // from internal hardware
1194:     .de     (1'b0),
1195:     .d      ('0  ),
1196: 
1197:     // to internal hardware
1198:     .qe     (),
1199:     .q      (reg2hw.mio_outsel[1].q ),
1200: 
1201:     // to register interface (read)
1202:     .qs     (mio_outsel0_out1_qs)
1203:   );
1204: 
1205: 
1206:   // F[out2]: 17:12
1207:   prim_subreg #(
1208:     .DW      (6),
1209:     .SWACCESS("RW"),
1210:     .RESVAL  (6'h2)
1211:   ) u_mio_outsel0_out2 (
1212:     .clk_i   (clk_i    ),
1213:     .rst_ni  (rst_ni  ),
1214: 
1215:     // from register interface (qualified with register enable)
1216:     .we     (mio_outsel0_out2_we & regen_qs),
1217:     .wd     (mio_outsel0_out2_wd),
1218: 
1219:     // from internal hardware
1220:     .de     (1'b0),
1221:     .d      ('0  ),
1222: 
1223:     // to internal hardware
1224:     .qe     (),
1225:     .q      (reg2hw.mio_outsel[2].q ),
1226: 
1227:     // to register interface (read)
1228:     .qs     (mio_outsel0_out2_qs)
1229:   );
1230: 
1231: 
1232:   // F[out3]: 23:18
1233:   prim_subreg #(
1234:     .DW      (6),
1235:     .SWACCESS("RW"),
1236:     .RESVAL  (6'h2)
1237:   ) u_mio_outsel0_out3 (
1238:     .clk_i   (clk_i    ),
1239:     .rst_ni  (rst_ni  ),
1240: 
1241:     // from register interface (qualified with register enable)
1242:     .we     (mio_outsel0_out3_we & regen_qs),
1243:     .wd     (mio_outsel0_out3_wd),
1244: 
1245:     // from internal hardware
1246:     .de     (1'b0),
1247:     .d      ('0  ),
1248: 
1249:     // to internal hardware
1250:     .qe     (),
1251:     .q      (reg2hw.mio_outsel[3].q ),
1252: 
1253:     // to register interface (read)
1254:     .qs     (mio_outsel0_out3_qs)
1255:   );
1256: 
1257: 
1258:   // F[out4]: 29:24
1259:   prim_subreg #(
1260:     .DW      (6),
1261:     .SWACCESS("RW"),
1262:     .RESVAL  (6'h2)
1263:   ) u_mio_outsel0_out4 (
1264:     .clk_i   (clk_i    ),
1265:     .rst_ni  (rst_ni  ),
1266: 
1267:     // from register interface (qualified with register enable)
1268:     .we     (mio_outsel0_out4_we & regen_qs),
1269:     .wd     (mio_outsel0_out4_wd),
1270: 
1271:     // from internal hardware
1272:     .de     (1'b0),
1273:     .d      ('0  ),
1274: 
1275:     // to internal hardware
1276:     .qe     (),
1277:     .q      (reg2hw.mio_outsel[4].q ),
1278: 
1279:     // to register interface (read)
1280:     .qs     (mio_outsel0_out4_qs)
1281:   );
1282: 
1283: 
1284:   // Subregister 5 of Multireg mio_outsel
1285:   // R[mio_outsel1]: V(False)
1286: 
1287:   // F[out5]: 5:0
1288:   prim_subreg #(
1289:     .DW      (6),
1290:     .SWACCESS("RW"),
1291:     .RESVAL  (6'h2)
1292:   ) u_mio_outsel1_out5 (
1293:     .clk_i   (clk_i    ),
1294:     .rst_ni  (rst_ni  ),
1295: 
1296:     // from register interface (qualified with register enable)
1297:     .we     (mio_outsel1_out5_we & regen_qs),
1298:     .wd     (mio_outsel1_out5_wd),
1299: 
1300:     // from internal hardware
1301:     .de     (1'b0),
1302:     .d      ('0  ),
1303: 
1304:     // to internal hardware
1305:     .qe     (),
1306:     .q      (reg2hw.mio_outsel[5].q ),
1307: 
1308:     // to register interface (read)
1309:     .qs     (mio_outsel1_out5_qs)
1310:   );
1311: 
1312: 
1313:   // F[out6]: 11:6
1314:   prim_subreg #(
1315:     .DW      (6),
1316:     .SWACCESS("RW"),
1317:     .RESVAL  (6'h2)
1318:   ) u_mio_outsel1_out6 (
1319:     .clk_i   (clk_i    ),
1320:     .rst_ni  (rst_ni  ),
1321: 
1322:     // from register interface (qualified with register enable)
1323:     .we     (mio_outsel1_out6_we & regen_qs),
1324:     .wd     (mio_outsel1_out6_wd),
1325: 
1326:     // from internal hardware
1327:     .de     (1'b0),
1328:     .d      ('0  ),
1329: 
1330:     // to internal hardware
1331:     .qe     (),
1332:     .q      (reg2hw.mio_outsel[6].q ),
1333: 
1334:     // to register interface (read)
1335:     .qs     (mio_outsel1_out6_qs)
1336:   );
1337: 
1338: 
1339:   // F[out7]: 17:12
1340:   prim_subreg #(
1341:     .DW      (6),
1342:     .SWACCESS("RW"),
1343:     .RESVAL  (6'h2)
1344:   ) u_mio_outsel1_out7 (
1345:     .clk_i   (clk_i    ),
1346:     .rst_ni  (rst_ni  ),
1347: 
1348:     // from register interface (qualified with register enable)
1349:     .we     (mio_outsel1_out7_we & regen_qs),
1350:     .wd     (mio_outsel1_out7_wd),
1351: 
1352:     // from internal hardware
1353:     .de     (1'b0),
1354:     .d      ('0  ),
1355: 
1356:     // to internal hardware
1357:     .qe     (),
1358:     .q      (reg2hw.mio_outsel[7].q ),
1359: 
1360:     // to register interface (read)
1361:     .qs     (mio_outsel1_out7_qs)
1362:   );
1363: 
1364: 
1365:   // F[out8]: 23:18
1366:   prim_subreg #(
1367:     .DW      (6),
1368:     .SWACCESS("RW"),
1369:     .RESVAL  (6'h2)
1370:   ) u_mio_outsel1_out8 (
1371:     .clk_i   (clk_i    ),
1372:     .rst_ni  (rst_ni  ),
1373: 
1374:     // from register interface (qualified with register enable)
1375:     .we     (mio_outsel1_out8_we & regen_qs),
1376:     .wd     (mio_outsel1_out8_wd),
1377: 
1378:     // from internal hardware
1379:     .de     (1'b0),
1380:     .d      ('0  ),
1381: 
1382:     // to internal hardware
1383:     .qe     (),
1384:     .q      (reg2hw.mio_outsel[8].q ),
1385: 
1386:     // to register interface (read)
1387:     .qs     (mio_outsel1_out8_qs)
1388:   );
1389: 
1390: 
1391:   // F[out9]: 29:24
1392:   prim_subreg #(
1393:     .DW      (6),
1394:     .SWACCESS("RW"),
1395:     .RESVAL  (6'h2)
1396:   ) u_mio_outsel1_out9 (
1397:     .clk_i   (clk_i    ),
1398:     .rst_ni  (rst_ni  ),
1399: 
1400:     // from register interface (qualified with register enable)
1401:     .we     (mio_outsel1_out9_we & regen_qs),
1402:     .wd     (mio_outsel1_out9_wd),
1403: 
1404:     // from internal hardware
1405:     .de     (1'b0),
1406:     .d      ('0  ),
1407: 
1408:     // to internal hardware
1409:     .qe     (),
1410:     .q      (reg2hw.mio_outsel[9].q ),
1411: 
1412:     // to register interface (read)
1413:     .qs     (mio_outsel1_out9_qs)
1414:   );
1415: 
1416: 
1417:   // Subregister 10 of Multireg mio_outsel
1418:   // R[mio_outsel2]: V(False)
1419: 
1420:   // F[out10]: 5:0
1421:   prim_subreg #(
1422:     .DW      (6),
1423:     .SWACCESS("RW"),
1424:     .RESVAL  (6'h2)
1425:   ) u_mio_outsel2_out10 (
1426:     .clk_i   (clk_i    ),
1427:     .rst_ni  (rst_ni  ),
1428: 
1429:     // from register interface (qualified with register enable)
1430:     .we     (mio_outsel2_out10_we & regen_qs),
1431:     .wd     (mio_outsel2_out10_wd),
1432: 
1433:     // from internal hardware
1434:     .de     (1'b0),
1435:     .d      ('0  ),
1436: 
1437:     // to internal hardware
1438:     .qe     (),
1439:     .q      (reg2hw.mio_outsel[10].q ),
1440: 
1441:     // to register interface (read)
1442:     .qs     (mio_outsel2_out10_qs)
1443:   );
1444: 
1445: 
1446:   // F[out11]: 11:6
1447:   prim_subreg #(
1448:     .DW      (6),
1449:     .SWACCESS("RW"),
1450:     .RESVAL  (6'h2)
1451:   ) u_mio_outsel2_out11 (
1452:     .clk_i   (clk_i    ),
1453:     .rst_ni  (rst_ni  ),
1454: 
1455:     // from register interface (qualified with register enable)
1456:     .we     (mio_outsel2_out11_we & regen_qs),
1457:     .wd     (mio_outsel2_out11_wd),
1458: 
1459:     // from internal hardware
1460:     .de     (1'b0),
1461:     .d      ('0  ),
1462: 
1463:     // to internal hardware
1464:     .qe     (),
1465:     .q      (reg2hw.mio_outsel[11].q ),
1466: 
1467:     // to register interface (read)
1468:     .qs     (mio_outsel2_out11_qs)
1469:   );
1470: 
1471: 
1472:   // F[out12]: 17:12
1473:   prim_subreg #(
1474:     .DW      (6),
1475:     .SWACCESS("RW"),
1476:     .RESVAL  (6'h2)
1477:   ) u_mio_outsel2_out12 (
1478:     .clk_i   (clk_i    ),
1479:     .rst_ni  (rst_ni  ),
1480: 
1481:     // from register interface (qualified with register enable)
1482:     .we     (mio_outsel2_out12_we & regen_qs),
1483:     .wd     (mio_outsel2_out12_wd),
1484: 
1485:     // from internal hardware
1486:     .de     (1'b0),
1487:     .d      ('0  ),
1488: 
1489:     // to internal hardware
1490:     .qe     (),
1491:     .q      (reg2hw.mio_outsel[12].q ),
1492: 
1493:     // to register interface (read)
1494:     .qs     (mio_outsel2_out12_qs)
1495:   );
1496: 
1497: 
1498:   // F[out13]: 23:18
1499:   prim_subreg #(
1500:     .DW      (6),
1501:     .SWACCESS("RW"),
1502:     .RESVAL  (6'h2)
1503:   ) u_mio_outsel2_out13 (
1504:     .clk_i   (clk_i    ),
1505:     .rst_ni  (rst_ni  ),
1506: 
1507:     // from register interface (qualified with register enable)
1508:     .we     (mio_outsel2_out13_we & regen_qs),
1509:     .wd     (mio_outsel2_out13_wd),
1510: 
1511:     // from internal hardware
1512:     .de     (1'b0),
1513:     .d      ('0  ),
1514: 
1515:     // to internal hardware
1516:     .qe     (),
1517:     .q      (reg2hw.mio_outsel[13].q ),
1518: 
1519:     // to register interface (read)
1520:     .qs     (mio_outsel2_out13_qs)
1521:   );
1522: 
1523: 
1524:   // F[out14]: 29:24
1525:   prim_subreg #(
1526:     .DW      (6),
1527:     .SWACCESS("RW"),
1528:     .RESVAL  (6'h2)
1529:   ) u_mio_outsel2_out14 (
1530:     .clk_i   (clk_i    ),
1531:     .rst_ni  (rst_ni  ),
1532: 
1533:     // from register interface (qualified with register enable)
1534:     .we     (mio_outsel2_out14_we & regen_qs),
1535:     .wd     (mio_outsel2_out14_wd),
1536: 
1537:     // from internal hardware
1538:     .de     (1'b0),
1539:     .d      ('0  ),
1540: 
1541:     // to internal hardware
1542:     .qe     (),
1543:     .q      (reg2hw.mio_outsel[14].q ),
1544: 
1545:     // to register interface (read)
1546:     .qs     (mio_outsel2_out14_qs)
1547:   );
1548: 
1549: 
1550:   // Subregister 15 of Multireg mio_outsel
1551:   // R[mio_outsel3]: V(False)
1552: 
1553:   // F[out15]: 5:0
1554:   prim_subreg #(
1555:     .DW      (6),
1556:     .SWACCESS("RW"),
1557:     .RESVAL  (6'h2)
1558:   ) u_mio_outsel3_out15 (
1559:     .clk_i   (clk_i    ),
1560:     .rst_ni  (rst_ni  ),
1561: 
1562:     // from register interface (qualified with register enable)
1563:     .we     (mio_outsel3_out15_we & regen_qs),
1564:     .wd     (mio_outsel3_out15_wd),
1565: 
1566:     // from internal hardware
1567:     .de     (1'b0),
1568:     .d      ('0  ),
1569: 
1570:     // to internal hardware
1571:     .qe     (),
1572:     .q      (reg2hw.mio_outsel[15].q ),
1573: 
1574:     // to register interface (read)
1575:     .qs     (mio_outsel3_out15_qs)
1576:   );
1577: 
1578: 
1579:   // F[out16]: 11:6
1580:   prim_subreg #(
1581:     .DW      (6),
1582:     .SWACCESS("RW"),
1583:     .RESVAL  (6'h2)
1584:   ) u_mio_outsel3_out16 (
1585:     .clk_i   (clk_i    ),
1586:     .rst_ni  (rst_ni  ),
1587: 
1588:     // from register interface (qualified with register enable)
1589:     .we     (mio_outsel3_out16_we & regen_qs),
1590:     .wd     (mio_outsel3_out16_wd),
1591: 
1592:     // from internal hardware
1593:     .de     (1'b0),
1594:     .d      ('0  ),
1595: 
1596:     // to internal hardware
1597:     .qe     (),
1598:     .q      (reg2hw.mio_outsel[16].q ),
1599: 
1600:     // to register interface (read)
1601:     .qs     (mio_outsel3_out16_qs)
1602:   );
1603: 
1604: 
1605:   // F[out17]: 17:12
1606:   prim_subreg #(
1607:     .DW      (6),
1608:     .SWACCESS("RW"),
1609:     .RESVAL  (6'h2)
1610:   ) u_mio_outsel3_out17 (
1611:     .clk_i   (clk_i    ),
1612:     .rst_ni  (rst_ni  ),
1613: 
1614:     // from register interface (qualified with register enable)
1615:     .we     (mio_outsel3_out17_we & regen_qs),
1616:     .wd     (mio_outsel3_out17_wd),
1617: 
1618:     // from internal hardware
1619:     .de     (1'b0),
1620:     .d      ('0  ),
1621: 
1622:     // to internal hardware
1623:     .qe     (),
1624:     .q      (reg2hw.mio_outsel[17].q ),
1625: 
1626:     // to register interface (read)
1627:     .qs     (mio_outsel3_out17_qs)
1628:   );
1629: 
1630: 
1631:   // F[out18]: 23:18
1632:   prim_subreg #(
1633:     .DW      (6),
1634:     .SWACCESS("RW"),
1635:     .RESVAL  (6'h2)
1636:   ) u_mio_outsel3_out18 (
1637:     .clk_i   (clk_i    ),
1638:     .rst_ni  (rst_ni  ),
1639: 
1640:     // from register interface (qualified with register enable)
1641:     .we     (mio_outsel3_out18_we & regen_qs),
1642:     .wd     (mio_outsel3_out18_wd),
1643: 
1644:     // from internal hardware
1645:     .de     (1'b0),
1646:     .d      ('0  ),
1647: 
1648:     // to internal hardware
1649:     .qe     (),
1650:     .q      (reg2hw.mio_outsel[18].q ),
1651: 
1652:     // to register interface (read)
1653:     .qs     (mio_outsel3_out18_qs)
1654:   );
1655: 
1656: 
1657:   // F[out19]: 29:24
1658:   prim_subreg #(
1659:     .DW      (6),
1660:     .SWACCESS("RW"),
1661:     .RESVAL  (6'h2)
1662:   ) u_mio_outsel3_out19 (
1663:     .clk_i   (clk_i    ),
1664:     .rst_ni  (rst_ni  ),
1665: 
1666:     // from register interface (qualified with register enable)
1667:     .we     (mio_outsel3_out19_we & regen_qs),
1668:     .wd     (mio_outsel3_out19_wd),
1669: 
1670:     // from internal hardware
1671:     .de     (1'b0),
1672:     .d      ('0  ),
1673: 
1674:     // to internal hardware
1675:     .qe     (),
1676:     .q      (reg2hw.mio_outsel[19].q ),
1677: 
1678:     // to register interface (read)
1679:     .qs     (mio_outsel3_out19_qs)
1680:   );
1681: 
1682: 
1683:   // Subregister 20 of Multireg mio_outsel
1684:   // R[mio_outsel4]: V(False)
1685: 
1686:   // F[out20]: 5:0
1687:   prim_subreg #(
1688:     .DW      (6),
1689:     .SWACCESS("RW"),
1690:     .RESVAL  (6'h2)
1691:   ) u_mio_outsel4_out20 (
1692:     .clk_i   (clk_i    ),
1693:     .rst_ni  (rst_ni  ),
1694: 
1695:     // from register interface (qualified with register enable)
1696:     .we     (mio_outsel4_out20_we & regen_qs),
1697:     .wd     (mio_outsel4_out20_wd),
1698: 
1699:     // from internal hardware
1700:     .de     (1'b0),
1701:     .d      ('0  ),
1702: 
1703:     // to internal hardware
1704:     .qe     (),
1705:     .q      (reg2hw.mio_outsel[20].q ),
1706: 
1707:     // to register interface (read)
1708:     .qs     (mio_outsel4_out20_qs)
1709:   );
1710: 
1711: 
1712:   // F[out21]: 11:6
1713:   prim_subreg #(
1714:     .DW      (6),
1715:     .SWACCESS("RW"),
1716:     .RESVAL  (6'h2)
1717:   ) u_mio_outsel4_out21 (
1718:     .clk_i   (clk_i    ),
1719:     .rst_ni  (rst_ni  ),
1720: 
1721:     // from register interface (qualified with register enable)
1722:     .we     (mio_outsel4_out21_we & regen_qs),
1723:     .wd     (mio_outsel4_out21_wd),
1724: 
1725:     // from internal hardware
1726:     .de     (1'b0),
1727:     .d      ('0  ),
1728: 
1729:     // to internal hardware
1730:     .qe     (),
1731:     .q      (reg2hw.mio_outsel[21].q ),
1732: 
1733:     // to register interface (read)
1734:     .qs     (mio_outsel4_out21_qs)
1735:   );
1736: 
1737: 
1738:   // F[out22]: 17:12
1739:   prim_subreg #(
1740:     .DW      (6),
1741:     .SWACCESS("RW"),
1742:     .RESVAL  (6'h2)
1743:   ) u_mio_outsel4_out22 (
1744:     .clk_i   (clk_i    ),
1745:     .rst_ni  (rst_ni  ),
1746: 
1747:     // from register interface (qualified with register enable)
1748:     .we     (mio_outsel4_out22_we & regen_qs),
1749:     .wd     (mio_outsel4_out22_wd),
1750: 
1751:     // from internal hardware
1752:     .de     (1'b0),
1753:     .d      ('0  ),
1754: 
1755:     // to internal hardware
1756:     .qe     (),
1757:     .q      (reg2hw.mio_outsel[22].q ),
1758: 
1759:     // to register interface (read)
1760:     .qs     (mio_outsel4_out22_qs)
1761:   );
1762: 
1763: 
1764:   // F[out23]: 23:18
1765:   prim_subreg #(
1766:     .DW      (6),
1767:     .SWACCESS("RW"),
1768:     .RESVAL  (6'h2)
1769:   ) u_mio_outsel4_out23 (
1770:     .clk_i   (clk_i    ),
1771:     .rst_ni  (rst_ni  ),
1772: 
1773:     // from register interface (qualified with register enable)
1774:     .we     (mio_outsel4_out23_we & regen_qs),
1775:     .wd     (mio_outsel4_out23_wd),
1776: 
1777:     // from internal hardware
1778:     .de     (1'b0),
1779:     .d      ('0  ),
1780: 
1781:     // to internal hardware
1782:     .qe     (),
1783:     .q      (reg2hw.mio_outsel[23].q ),
1784: 
1785:     // to register interface (read)
1786:     .qs     (mio_outsel4_out23_qs)
1787:   );
1788: 
1789: 
1790:   // F[out24]: 29:24
1791:   prim_subreg #(
1792:     .DW      (6),
1793:     .SWACCESS("RW"),
1794:     .RESVAL  (6'h2)
1795:   ) u_mio_outsel4_out24 (
1796:     .clk_i   (clk_i    ),
1797:     .rst_ni  (rst_ni  ),
1798: 
1799:     // from register interface (qualified with register enable)
1800:     .we     (mio_outsel4_out24_we & regen_qs),
1801:     .wd     (mio_outsel4_out24_wd),
1802: 
1803:     // from internal hardware
1804:     .de     (1'b0),
1805:     .d      ('0  ),
1806: 
1807:     // to internal hardware
1808:     .qe     (),
1809:     .q      (reg2hw.mio_outsel[24].q ),
1810: 
1811:     // to register interface (read)
1812:     .qs     (mio_outsel4_out24_qs)
1813:   );
1814: 
1815: 
1816:   // Subregister 25 of Multireg mio_outsel
1817:   // R[mio_outsel5]: V(False)
1818: 
1819:   // F[out25]: 5:0
1820:   prim_subreg #(
1821:     .DW      (6),
1822:     .SWACCESS("RW"),
1823:     .RESVAL  (6'h2)
1824:   ) u_mio_outsel5_out25 (
1825:     .clk_i   (clk_i    ),
1826:     .rst_ni  (rst_ni  ),
1827: 
1828:     // from register interface (qualified with register enable)
1829:     .we     (mio_outsel5_out25_we & regen_qs),
1830:     .wd     (mio_outsel5_out25_wd),
1831: 
1832:     // from internal hardware
1833:     .de     (1'b0),
1834:     .d      ('0  ),
1835: 
1836:     // to internal hardware
1837:     .qe     (),
1838:     .q      (reg2hw.mio_outsel[25].q ),
1839: 
1840:     // to register interface (read)
1841:     .qs     (mio_outsel5_out25_qs)
1842:   );
1843: 
1844: 
1845:   // F[out26]: 11:6
1846:   prim_subreg #(
1847:     .DW      (6),
1848:     .SWACCESS("RW"),
1849:     .RESVAL  (6'h2)
1850:   ) u_mio_outsel5_out26 (
1851:     .clk_i   (clk_i    ),
1852:     .rst_ni  (rst_ni  ),
1853: 
1854:     // from register interface (qualified with register enable)
1855:     .we     (mio_outsel5_out26_we & regen_qs),
1856:     .wd     (mio_outsel5_out26_wd),
1857: 
1858:     // from internal hardware
1859:     .de     (1'b0),
1860:     .d      ('0  ),
1861: 
1862:     // to internal hardware
1863:     .qe     (),
1864:     .q      (reg2hw.mio_outsel[26].q ),
1865: 
1866:     // to register interface (read)
1867:     .qs     (mio_outsel5_out26_qs)
1868:   );
1869: 
1870: 
1871:   // F[out27]: 17:12
1872:   prim_subreg #(
1873:     .DW      (6),
1874:     .SWACCESS("RW"),
1875:     .RESVAL  (6'h2)
1876:   ) u_mio_outsel5_out27 (
1877:     .clk_i   (clk_i    ),
1878:     .rst_ni  (rst_ni  ),
1879: 
1880:     // from register interface (qualified with register enable)
1881:     .we     (mio_outsel5_out27_we & regen_qs),
1882:     .wd     (mio_outsel5_out27_wd),
1883: 
1884:     // from internal hardware
1885:     .de     (1'b0),
1886:     .d      ('0  ),
1887: 
1888:     // to internal hardware
1889:     .qe     (),
1890:     .q      (reg2hw.mio_outsel[27].q ),
1891: 
1892:     // to register interface (read)
1893:     .qs     (mio_outsel5_out27_qs)
1894:   );
1895: 
1896: 
1897:   // F[out28]: 23:18
1898:   prim_subreg #(
1899:     .DW      (6),
1900:     .SWACCESS("RW"),
1901:     .RESVAL  (6'h2)
1902:   ) u_mio_outsel5_out28 (
1903:     .clk_i   (clk_i    ),
1904:     .rst_ni  (rst_ni  ),
1905: 
1906:     // from register interface (qualified with register enable)
1907:     .we     (mio_outsel5_out28_we & regen_qs),
1908:     .wd     (mio_outsel5_out28_wd),
1909: 
1910:     // from internal hardware
1911:     .de     (1'b0),
1912:     .d      ('0  ),
1913: 
1914:     // to internal hardware
1915:     .qe     (),
1916:     .q      (reg2hw.mio_outsel[28].q ),
1917: 
1918:     // to register interface (read)
1919:     .qs     (mio_outsel5_out28_qs)
1920:   );
1921: 
1922: 
1923:   // F[out29]: 29:24
1924:   prim_subreg #(
1925:     .DW      (6),
1926:     .SWACCESS("RW"),
1927:     .RESVAL  (6'h2)
1928:   ) u_mio_outsel5_out29 (
1929:     .clk_i   (clk_i    ),
1930:     .rst_ni  (rst_ni  ),
1931: 
1932:     // from register interface (qualified with register enable)
1933:     .we     (mio_outsel5_out29_we & regen_qs),
1934:     .wd     (mio_outsel5_out29_wd),
1935: 
1936:     // from internal hardware
1937:     .de     (1'b0),
1938:     .d      ('0  ),
1939: 
1940:     // to internal hardware
1941:     .qe     (),
1942:     .q      (reg2hw.mio_outsel[29].q ),
1943: 
1944:     // to register interface (read)
1945:     .qs     (mio_outsel5_out29_qs)
1946:   );
1947: 
1948: 
1949:   // Subregister 30 of Multireg mio_outsel
1950:   // R[mio_outsel6]: V(False)
1951: 
1952:   // F[out30]: 5:0
1953:   prim_subreg #(
1954:     .DW      (6),
1955:     .SWACCESS("RW"),
1956:     .RESVAL  (6'h2)
1957:   ) u_mio_outsel6_out30 (
1958:     .clk_i   (clk_i    ),
1959:     .rst_ni  (rst_ni  ),
1960: 
1961:     // from register interface (qualified with register enable)
1962:     .we     (mio_outsel6_out30_we & regen_qs),
1963:     .wd     (mio_outsel6_out30_wd),
1964: 
1965:     // from internal hardware
1966:     .de     (1'b0),
1967:     .d      ('0  ),
1968: 
1969:     // to internal hardware
1970:     .qe     (),
1971:     .q      (reg2hw.mio_outsel[30].q ),
1972: 
1973:     // to register interface (read)
1974:     .qs     (mio_outsel6_out30_qs)
1975:   );
1976: 
1977: 
1978:   // F[out31]: 11:6
1979:   prim_subreg #(
1980:     .DW      (6),
1981:     .SWACCESS("RW"),
1982:     .RESVAL  (6'h2)
1983:   ) u_mio_outsel6_out31 (
1984:     .clk_i   (clk_i    ),
1985:     .rst_ni  (rst_ni  ),
1986: 
1987:     // from register interface (qualified with register enable)
1988:     .we     (mio_outsel6_out31_we & regen_qs),
1989:     .wd     (mio_outsel6_out31_wd),
1990: 
1991:     // from internal hardware
1992:     .de     (1'b0),
1993:     .d      ('0  ),
1994: 
1995:     // to internal hardware
1996:     .qe     (),
1997:     .q      (reg2hw.mio_outsel[31].q ),
1998: 
1999:     // to register interface (read)
2000:     .qs     (mio_outsel6_out31_qs)
2001:   );
2002: 
2003: 
2004: 
2005: 
2006: 
2007:   logic [14:0] addr_hit;
2008:   always_comb begin
2009:     addr_hit = '0;
2010:     addr_hit[ 0] = (reg_addr == PINMUX_REGEN_OFFSET);
2011:     addr_hit[ 1] = (reg_addr == PINMUX_PERIPH_INSEL0_OFFSET);
2012:     addr_hit[ 2] = (reg_addr == PINMUX_PERIPH_INSEL1_OFFSET);
2013:     addr_hit[ 3] = (reg_addr == PINMUX_PERIPH_INSEL2_OFFSET);
2014:     addr_hit[ 4] = (reg_addr == PINMUX_PERIPH_INSEL3_OFFSET);
2015:     addr_hit[ 5] = (reg_addr == PINMUX_PERIPH_INSEL4_OFFSET);
2016:     addr_hit[ 6] = (reg_addr == PINMUX_PERIPH_INSEL5_OFFSET);
2017:     addr_hit[ 7] = (reg_addr == PINMUX_PERIPH_INSEL6_OFFSET);
2018:     addr_hit[ 8] = (reg_addr == PINMUX_MIO_OUTSEL0_OFFSET);
2019:     addr_hit[ 9] = (reg_addr == PINMUX_MIO_OUTSEL1_OFFSET);
2020:     addr_hit[10] = (reg_addr == PINMUX_MIO_OUTSEL2_OFFSET);
2021:     addr_hit[11] = (reg_addr == PINMUX_MIO_OUTSEL3_OFFSET);
2022:     addr_hit[12] = (reg_addr == PINMUX_MIO_OUTSEL4_OFFSET);
2023:     addr_hit[13] = (reg_addr == PINMUX_MIO_OUTSEL5_OFFSET);
2024:     addr_hit[14] = (reg_addr == PINMUX_MIO_OUTSEL6_OFFSET);
2025:   end
2026: 
2027:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
2028: 
2029:   // Check sub-word write is permitted
2030:   always_comb begin
2031:     wr_err = 1'b0;
2032:     if (addr_hit[ 0] && reg_we && (PINMUX_PERMIT[ 0] != (PINMUX_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
2033:     if (addr_hit[ 1] && reg_we && (PINMUX_PERMIT[ 1] != (PINMUX_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
2034:     if (addr_hit[ 2] && reg_we && (PINMUX_PERMIT[ 2] != (PINMUX_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
2035:     if (addr_hit[ 3] && reg_we && (PINMUX_PERMIT[ 3] != (PINMUX_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
2036:     if (addr_hit[ 4] && reg_we && (PINMUX_PERMIT[ 4] != (PINMUX_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
2037:     if (addr_hit[ 5] && reg_we && (PINMUX_PERMIT[ 5] != (PINMUX_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
2038:     if (addr_hit[ 6] && reg_we && (PINMUX_PERMIT[ 6] != (PINMUX_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
2039:     if (addr_hit[ 7] && reg_we && (PINMUX_PERMIT[ 7] != (PINMUX_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
2040:     if (addr_hit[ 8] && reg_we && (PINMUX_PERMIT[ 8] != (PINMUX_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
2041:     if (addr_hit[ 9] && reg_we && (PINMUX_PERMIT[ 9] != (PINMUX_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
2042:     if (addr_hit[10] && reg_we && (PINMUX_PERMIT[10] != (PINMUX_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
2043:     if (addr_hit[11] && reg_we && (PINMUX_PERMIT[11] != (PINMUX_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
2044:     if (addr_hit[12] && reg_we && (PINMUX_PERMIT[12] != (PINMUX_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
2045:     if (addr_hit[13] && reg_we && (PINMUX_PERMIT[13] != (PINMUX_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
2046:     if (addr_hit[14] && reg_we && (PINMUX_PERMIT[14] != (PINMUX_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
2047:   end
2048: 
2049:   assign regen_we = addr_hit[0] & reg_we & ~wr_err;
2050:   assign regen_wd = reg_wdata[0];
2051: 
2052:   assign periph_insel0_in0_we = addr_hit[1] & reg_we & ~wr_err;
2053:   assign periph_insel0_in0_wd = reg_wdata[5:0];
2054: 
2055:   assign periph_insel0_in1_we = addr_hit[1] & reg_we & ~wr_err;
2056:   assign periph_insel0_in1_wd = reg_wdata[11:6];
2057: 
2058:   assign periph_insel0_in2_we = addr_hit[1] & reg_we & ~wr_err;
2059:   assign periph_insel0_in2_wd = reg_wdata[17:12];
2060: 
2061:   assign periph_insel0_in3_we = addr_hit[1] & reg_we & ~wr_err;
2062:   assign periph_insel0_in3_wd = reg_wdata[23:18];
2063: 
2064:   assign periph_insel0_in4_we = addr_hit[1] & reg_we & ~wr_err;
2065:   assign periph_insel0_in4_wd = reg_wdata[29:24];
2066: 
2067:   assign periph_insel1_in5_we = addr_hit[2] & reg_we & ~wr_err;
2068:   assign periph_insel1_in5_wd = reg_wdata[5:0];
2069: 
2070:   assign periph_insel1_in6_we = addr_hit[2] & reg_we & ~wr_err;
2071:   assign periph_insel1_in6_wd = reg_wdata[11:6];
2072: 
2073:   assign periph_insel1_in7_we = addr_hit[2] & reg_we & ~wr_err;
2074:   assign periph_insel1_in7_wd = reg_wdata[17:12];
2075: 
2076:   assign periph_insel1_in8_we = addr_hit[2] & reg_we & ~wr_err;
2077:   assign periph_insel1_in8_wd = reg_wdata[23:18];
2078: 
2079:   assign periph_insel1_in9_we = addr_hit[2] & reg_we & ~wr_err;
2080:   assign periph_insel1_in9_wd = reg_wdata[29:24];
2081: 
2082:   assign periph_insel2_in10_we = addr_hit[3] & reg_we & ~wr_err;
2083:   assign periph_insel2_in10_wd = reg_wdata[5:0];
2084: 
2085:   assign periph_insel2_in11_we = addr_hit[3] & reg_we & ~wr_err;
2086:   assign periph_insel2_in11_wd = reg_wdata[11:6];
2087: 
2088:   assign periph_insel2_in12_we = addr_hit[3] & reg_we & ~wr_err;
2089:   assign periph_insel2_in12_wd = reg_wdata[17:12];
2090: 
2091:   assign periph_insel2_in13_we = addr_hit[3] & reg_we & ~wr_err;
2092:   assign periph_insel2_in13_wd = reg_wdata[23:18];
2093: 
2094:   assign periph_insel2_in14_we = addr_hit[3] & reg_we & ~wr_err;
2095:   assign periph_insel2_in14_wd = reg_wdata[29:24];
2096: 
2097:   assign periph_insel3_in15_we = addr_hit[4] & reg_we & ~wr_err;
2098:   assign periph_insel3_in15_wd = reg_wdata[5:0];
2099: 
2100:   assign periph_insel3_in16_we = addr_hit[4] & reg_we & ~wr_err;
2101:   assign periph_insel3_in16_wd = reg_wdata[11:6];
2102: 
2103:   assign periph_insel3_in17_we = addr_hit[4] & reg_we & ~wr_err;
2104:   assign periph_insel3_in17_wd = reg_wdata[17:12];
2105: 
2106:   assign periph_insel3_in18_we = addr_hit[4] & reg_we & ~wr_err;
2107:   assign periph_insel3_in18_wd = reg_wdata[23:18];
2108: 
2109:   assign periph_insel3_in19_we = addr_hit[4] & reg_we & ~wr_err;
2110:   assign periph_insel3_in19_wd = reg_wdata[29:24];
2111: 
2112:   assign periph_insel4_in20_we = addr_hit[5] & reg_we & ~wr_err;
2113:   assign periph_insel4_in20_wd = reg_wdata[5:0];
2114: 
2115:   assign periph_insel4_in21_we = addr_hit[5] & reg_we & ~wr_err;
2116:   assign periph_insel4_in21_wd = reg_wdata[11:6];
2117: 
2118:   assign periph_insel4_in22_we = addr_hit[5] & reg_we & ~wr_err;
2119:   assign periph_insel4_in22_wd = reg_wdata[17:12];
2120: 
2121:   assign periph_insel4_in23_we = addr_hit[5] & reg_we & ~wr_err;
2122:   assign periph_insel4_in23_wd = reg_wdata[23:18];
2123: 
2124:   assign periph_insel4_in24_we = addr_hit[5] & reg_we & ~wr_err;
2125:   assign periph_insel4_in24_wd = reg_wdata[29:24];
2126: 
2127:   assign periph_insel5_in25_we = addr_hit[6] & reg_we & ~wr_err;
2128:   assign periph_insel5_in25_wd = reg_wdata[5:0];
2129: 
2130:   assign periph_insel5_in26_we = addr_hit[6] & reg_we & ~wr_err;
2131:   assign periph_insel5_in26_wd = reg_wdata[11:6];
2132: 
2133:   assign periph_insel5_in27_we = addr_hit[6] & reg_we & ~wr_err;
2134:   assign periph_insel5_in27_wd = reg_wdata[17:12];
2135: 
2136:   assign periph_insel5_in28_we = addr_hit[6] & reg_we & ~wr_err;
2137:   assign periph_insel5_in28_wd = reg_wdata[23:18];
2138: 
2139:   assign periph_insel5_in29_we = addr_hit[6] & reg_we & ~wr_err;
2140:   assign periph_insel5_in29_wd = reg_wdata[29:24];
2141: 
2142:   assign periph_insel6_in30_we = addr_hit[7] & reg_we & ~wr_err;
2143:   assign periph_insel6_in30_wd = reg_wdata[5:0];
2144: 
2145:   assign periph_insel6_in31_we = addr_hit[7] & reg_we & ~wr_err;
2146:   assign periph_insel6_in31_wd = reg_wdata[11:6];
2147: 
2148:   assign mio_outsel0_out0_we = addr_hit[8] & reg_we & ~wr_err;
2149:   assign mio_outsel0_out0_wd = reg_wdata[5:0];
2150: 
2151:   assign mio_outsel0_out1_we = addr_hit[8] & reg_we & ~wr_err;
2152:   assign mio_outsel0_out1_wd = reg_wdata[11:6];
2153: 
2154:   assign mio_outsel0_out2_we = addr_hit[8] & reg_we & ~wr_err;
2155:   assign mio_outsel0_out2_wd = reg_wdata[17:12];
2156: 
2157:   assign mio_outsel0_out3_we = addr_hit[8] & reg_we & ~wr_err;
2158:   assign mio_outsel0_out3_wd = reg_wdata[23:18];
2159: 
2160:   assign mio_outsel0_out4_we = addr_hit[8] & reg_we & ~wr_err;
2161:   assign mio_outsel0_out4_wd = reg_wdata[29:24];
2162: 
2163:   assign mio_outsel1_out5_we = addr_hit[9] & reg_we & ~wr_err;
2164:   assign mio_outsel1_out5_wd = reg_wdata[5:0];
2165: 
2166:   assign mio_outsel1_out6_we = addr_hit[9] & reg_we & ~wr_err;
2167:   assign mio_outsel1_out6_wd = reg_wdata[11:6];
2168: 
2169:   assign mio_outsel1_out7_we = addr_hit[9] & reg_we & ~wr_err;
2170:   assign mio_outsel1_out7_wd = reg_wdata[17:12];
2171: 
2172:   assign mio_outsel1_out8_we = addr_hit[9] & reg_we & ~wr_err;
2173:   assign mio_outsel1_out8_wd = reg_wdata[23:18];
2174: 
2175:   assign mio_outsel1_out9_we = addr_hit[9] & reg_we & ~wr_err;
2176:   assign mio_outsel1_out9_wd = reg_wdata[29:24];
2177: 
2178:   assign mio_outsel2_out10_we = addr_hit[10] & reg_we & ~wr_err;
2179:   assign mio_outsel2_out10_wd = reg_wdata[5:0];
2180: 
2181:   assign mio_outsel2_out11_we = addr_hit[10] & reg_we & ~wr_err;
2182:   assign mio_outsel2_out11_wd = reg_wdata[11:6];
2183: 
2184:   assign mio_outsel2_out12_we = addr_hit[10] & reg_we & ~wr_err;
2185:   assign mio_outsel2_out12_wd = reg_wdata[17:12];
2186: 
2187:   assign mio_outsel2_out13_we = addr_hit[10] & reg_we & ~wr_err;
2188:   assign mio_outsel2_out13_wd = reg_wdata[23:18];
2189: 
2190:   assign mio_outsel2_out14_we = addr_hit[10] & reg_we & ~wr_err;
2191:   assign mio_outsel2_out14_wd = reg_wdata[29:24];
2192: 
2193:   assign mio_outsel3_out15_we = addr_hit[11] & reg_we & ~wr_err;
2194:   assign mio_outsel3_out15_wd = reg_wdata[5:0];
2195: 
2196:   assign mio_outsel3_out16_we = addr_hit[11] & reg_we & ~wr_err;
2197:   assign mio_outsel3_out16_wd = reg_wdata[11:6];
2198: 
2199:   assign mio_outsel3_out17_we = addr_hit[11] & reg_we & ~wr_err;
2200:   assign mio_outsel3_out17_wd = reg_wdata[17:12];
2201: 
2202:   assign mio_outsel3_out18_we = addr_hit[11] & reg_we & ~wr_err;
2203:   assign mio_outsel3_out18_wd = reg_wdata[23:18];
2204: 
2205:   assign mio_outsel3_out19_we = addr_hit[11] & reg_we & ~wr_err;
2206:   assign mio_outsel3_out19_wd = reg_wdata[29:24];
2207: 
2208:   assign mio_outsel4_out20_we = addr_hit[12] & reg_we & ~wr_err;
2209:   assign mio_outsel4_out20_wd = reg_wdata[5:0];
2210: 
2211:   assign mio_outsel4_out21_we = addr_hit[12] & reg_we & ~wr_err;
2212:   assign mio_outsel4_out21_wd = reg_wdata[11:6];
2213: 
2214:   assign mio_outsel4_out22_we = addr_hit[12] & reg_we & ~wr_err;
2215:   assign mio_outsel4_out22_wd = reg_wdata[17:12];
2216: 
2217:   assign mio_outsel4_out23_we = addr_hit[12] & reg_we & ~wr_err;
2218:   assign mio_outsel4_out23_wd = reg_wdata[23:18];
2219: 
2220:   assign mio_outsel4_out24_we = addr_hit[12] & reg_we & ~wr_err;
2221:   assign mio_outsel4_out24_wd = reg_wdata[29:24];
2222: 
2223:   assign mio_outsel5_out25_we = addr_hit[13] & reg_we & ~wr_err;
2224:   assign mio_outsel5_out25_wd = reg_wdata[5:0];
2225: 
2226:   assign mio_outsel5_out26_we = addr_hit[13] & reg_we & ~wr_err;
2227:   assign mio_outsel5_out26_wd = reg_wdata[11:6];
2228: 
2229:   assign mio_outsel5_out27_we = addr_hit[13] & reg_we & ~wr_err;
2230:   assign mio_outsel5_out27_wd = reg_wdata[17:12];
2231: 
2232:   assign mio_outsel5_out28_we = addr_hit[13] & reg_we & ~wr_err;
2233:   assign mio_outsel5_out28_wd = reg_wdata[23:18];
2234: 
2235:   assign mio_outsel5_out29_we = addr_hit[13] & reg_we & ~wr_err;
2236:   assign mio_outsel5_out29_wd = reg_wdata[29:24];
2237: 
2238:   assign mio_outsel6_out30_we = addr_hit[14] & reg_we & ~wr_err;
2239:   assign mio_outsel6_out30_wd = reg_wdata[5:0];
2240: 
2241:   assign mio_outsel6_out31_we = addr_hit[14] & reg_we & ~wr_err;
2242:   assign mio_outsel6_out31_wd = reg_wdata[11:6];
2243: 
2244:   // Read data return
2245:   always_comb begin
2246:     reg_rdata_next = '0;
2247:     unique case (1'b1)
2248:       addr_hit[0]: begin
2249:         reg_rdata_next[0] = regen_qs;
2250:       end
2251: 
2252:       addr_hit[1]: begin
2253:         reg_rdata_next[5:0] = periph_insel0_in0_qs;
2254:         reg_rdata_next[11:6] = periph_insel0_in1_qs;
2255:         reg_rdata_next[17:12] = periph_insel0_in2_qs;
2256:         reg_rdata_next[23:18] = periph_insel0_in3_qs;
2257:         reg_rdata_next[29:24] = periph_insel0_in4_qs;
2258:       end
2259: 
2260:       addr_hit[2]: begin
2261:         reg_rdata_next[5:0] = periph_insel1_in5_qs;
2262:         reg_rdata_next[11:6] = periph_insel1_in6_qs;
2263:         reg_rdata_next[17:12] = periph_insel1_in7_qs;
2264:         reg_rdata_next[23:18] = periph_insel1_in8_qs;
2265:         reg_rdata_next[29:24] = periph_insel1_in9_qs;
2266:       end
2267: 
2268:       addr_hit[3]: begin
2269:         reg_rdata_next[5:0] = periph_insel2_in10_qs;
2270:         reg_rdata_next[11:6] = periph_insel2_in11_qs;
2271:         reg_rdata_next[17:12] = periph_insel2_in12_qs;
2272:         reg_rdata_next[23:18] = periph_insel2_in13_qs;
2273:         reg_rdata_next[29:24] = periph_insel2_in14_qs;
2274:       end
2275: 
2276:       addr_hit[4]: begin
2277:         reg_rdata_next[5:0] = periph_insel3_in15_qs;
2278:         reg_rdata_next[11:6] = periph_insel3_in16_qs;
2279:         reg_rdata_next[17:12] = periph_insel3_in17_qs;
2280:         reg_rdata_next[23:18] = periph_insel3_in18_qs;
2281:         reg_rdata_next[29:24] = periph_insel3_in19_qs;
2282:       end
2283: 
2284:       addr_hit[5]: begin
2285:         reg_rdata_next[5:0] = periph_insel4_in20_qs;
2286:         reg_rdata_next[11:6] = periph_insel4_in21_qs;
2287:         reg_rdata_next[17:12] = periph_insel4_in22_qs;
2288:         reg_rdata_next[23:18] = periph_insel4_in23_qs;
2289:         reg_rdata_next[29:24] = periph_insel4_in24_qs;
2290:       end
2291: 
2292:       addr_hit[6]: begin
2293:         reg_rdata_next[5:0] = periph_insel5_in25_qs;
2294:         reg_rdata_next[11:6] = periph_insel5_in26_qs;
2295:         reg_rdata_next[17:12] = periph_insel5_in27_qs;
2296:         reg_rdata_next[23:18] = periph_insel5_in28_qs;
2297:         reg_rdata_next[29:24] = periph_insel5_in29_qs;
2298:       end
2299: 
2300:       addr_hit[7]: begin
2301:         reg_rdata_next[5:0] = periph_insel6_in30_qs;
2302:         reg_rdata_next[11:6] = periph_insel6_in31_qs;
2303:       end
2304: 
2305:       addr_hit[8]: begin
2306:         reg_rdata_next[5:0] = mio_outsel0_out0_qs;
2307:         reg_rdata_next[11:6] = mio_outsel0_out1_qs;
2308:         reg_rdata_next[17:12] = mio_outsel0_out2_qs;
2309:         reg_rdata_next[23:18] = mio_outsel0_out3_qs;
2310:         reg_rdata_next[29:24] = mio_outsel0_out4_qs;
2311:       end
2312: 
2313:       addr_hit[9]: begin
2314:         reg_rdata_next[5:0] = mio_outsel1_out5_qs;
2315:         reg_rdata_next[11:6] = mio_outsel1_out6_qs;
2316:         reg_rdata_next[17:12] = mio_outsel1_out7_qs;
2317:         reg_rdata_next[23:18] = mio_outsel1_out8_qs;
2318:         reg_rdata_next[29:24] = mio_outsel1_out9_qs;
2319:       end
2320: 
2321:       addr_hit[10]: begin
2322:         reg_rdata_next[5:0] = mio_outsel2_out10_qs;
2323:         reg_rdata_next[11:6] = mio_outsel2_out11_qs;
2324:         reg_rdata_next[17:12] = mio_outsel2_out12_qs;
2325:         reg_rdata_next[23:18] = mio_outsel2_out13_qs;
2326:         reg_rdata_next[29:24] = mio_outsel2_out14_qs;
2327:       end
2328: 
2329:       addr_hit[11]: begin
2330:         reg_rdata_next[5:0] = mio_outsel3_out15_qs;
2331:         reg_rdata_next[11:6] = mio_outsel3_out16_qs;
2332:         reg_rdata_next[17:12] = mio_outsel3_out17_qs;
2333:         reg_rdata_next[23:18] = mio_outsel3_out18_qs;
2334:         reg_rdata_next[29:24] = mio_outsel3_out19_qs;
2335:       end
2336: 
2337:       addr_hit[12]: begin
2338:         reg_rdata_next[5:0] = mio_outsel4_out20_qs;
2339:         reg_rdata_next[11:6] = mio_outsel4_out21_qs;
2340:         reg_rdata_next[17:12] = mio_outsel4_out22_qs;
2341:         reg_rdata_next[23:18] = mio_outsel4_out23_qs;
2342:         reg_rdata_next[29:24] = mio_outsel4_out24_qs;
2343:       end
2344: 
2345:       addr_hit[13]: begin
2346:         reg_rdata_next[5:0] = mio_outsel5_out25_qs;
2347:         reg_rdata_next[11:6] = mio_outsel5_out26_qs;
2348:         reg_rdata_next[17:12] = mio_outsel5_out27_qs;
2349:         reg_rdata_next[23:18] = mio_outsel5_out28_qs;
2350:         reg_rdata_next[29:24] = mio_outsel5_out29_qs;
2351:       end
2352: 
2353:       addr_hit[14]: begin
2354:         reg_rdata_next[5:0] = mio_outsel6_out30_qs;
2355:         reg_rdata_next[11:6] = mio_outsel6_out31_qs;
2356:       end
2357: 
2358:       default: begin
2359:         reg_rdata_next = '1;
2360:       end
2361:     endcase
2362:   end
2363: 
2364:   // Assertions for Register Interface
2365:   `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
2366:   `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
2367: 
2368:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
2369: 
2370:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
2371: 
2372:   // this is formulated as an assumption such that the FPV testbenches do disprove this
2373:   // property by mistake
2374:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
2375: 
2376: endmodule
2377: