hw/ip/spi_device/rtl/spi_device_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: module spi_device_reg_top (
   8:   input clk_i,
   9:   input rst_ni,
  10: 
  11:   // Below Regster interface can be changed
  12:   input  tlul_pkg::tl_h2d_t tl_i,
  13:   output tlul_pkg::tl_d2h_t tl_o,
  14: 
  15:   // Output port for window
  16:   output tlul_pkg::tl_h2d_t tl_win_o  [1],
  17:   input  tlul_pkg::tl_d2h_t tl_win_i  [1],
  18: 
  19:   // To HW
  20:   output spi_device_reg_pkg::spi_device_reg2hw_t reg2hw, // Write
  21:   input  spi_device_reg_pkg::spi_device_hw2reg_t hw2reg, // Read
  22: 
  23:   // Config
  24:   input devmode_i // If 1, explicit error return for unmapped register access
  25: );
  26: 
  27:   import spi_device_reg_pkg::* ;
  28: 
  29:   localparam int AW = 12;
  30:   localparam int DW = 32;
  31:   localparam int DBW = DW/8;                    // Byte Width
  32: 
  33:   // register signals
  34:   logic           reg_we;
  35:   logic           reg_re;
  36:   logic [AW-1:0]  reg_addr;
  37:   logic [DW-1:0]  reg_wdata;
  38:   logic [DBW-1:0] reg_be;
  39:   logic [DW-1:0]  reg_rdata;
  40:   logic           reg_error;
  41: 
  42:   logic          addrmiss, wr_err;
  43: 
  44:   logic [DW-1:0] reg_rdata_next;
  45: 
  46:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  47:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  48: 
  49:   tlul_pkg::tl_h2d_t tl_socket_h2d [2];
  50:   tlul_pkg::tl_d2h_t tl_socket_d2h [2];
  51: 
  52:   logic [1:0] reg_steer;
  53: 
  54:   // socket_1n connection
  55:   assign tl_reg_h2d = tl_socket_h2d[1];
  56:   assign tl_socket_d2h[1] = tl_reg_d2h;
  57: 
  58:   assign tl_win_o[0] = tl_socket_h2d[0];
  59:   assign tl_socket_d2h[0] = tl_win_i[0];
  60: 
  61:   // Create Socket_1n
  62:   tlul_socket_1n #(
  63:     .N          (2),
  64:     .HReqPass   (1'b1),
  65:     .HRspPass   (1'b1),
  66:     .DReqPass   ({2{1'b1}}),
  67:     .DRspPass   ({2{1'b1}}),
  68:     .HReqDepth  (4'h0),
  69:     .HRspDepth  (4'h0),
  70:     .DReqDepth  ({2{4'h0}}),
  71:     .DRspDepth  ({2{4'h0}})
  72:   ) u_socket (
  73:     .clk_i,
  74:     .rst_ni,
  75:     .tl_h_i (tl_i),
  76:     .tl_h_o (tl_o),
  77:     .tl_d_o (tl_socket_h2d),
  78:     .tl_d_i (tl_socket_d2h),
  79:     .dev_select (reg_steer)
  80:   );
  81: 
  82:   // Create steering logic
  83:   always_comb begin
  84:     reg_steer = 1;       // Default set to register
  85: 
  86:     // TODO: Can below codes be unique case () inside ?
  87:     if (tl_i.a_address[AW-1:0] >= 2048) begin
  88:       // Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
  89:       reg_steer = 0;
  90:     end
  91:   end
  92: 
  93:   tlul_adapter_reg #(
  94:     .RegAw(AW),
  95:     .RegDw(DW)
  96:   ) u_reg_if (
  97:     .clk_i,
  98:     .rst_ni,
  99: 
 100:     .tl_i (tl_reg_h2d),
 101:     .tl_o (tl_reg_d2h),
 102: 
 103:     .we_o    (reg_we),
 104:     .re_o    (reg_re),
 105:     .addr_o  (reg_addr),
 106:     .wdata_o (reg_wdata),
 107:     .be_o    (reg_be),
 108:     .rdata_i (reg_rdata),
 109:     .error_i (reg_error)
 110:   );
 111: 
 112:   assign reg_rdata = reg_rdata_next ;
 113:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
 114: 
 115:   // Define SW related signals
 116:   // Format: __{wd|we|qs}
 117:   //        or _{wd|we|qs} if field == 1 or 0
 118:   logic intr_state_rxf_qs;
 119:   logic intr_state_rxf_wd;
 120:   logic intr_state_rxf_we;
 121:   logic intr_state_rxlvl_qs;
 122:   logic intr_state_rxlvl_wd;
 123:   logic intr_state_rxlvl_we;
 124:   logic intr_state_txlvl_qs;
 125:   logic intr_state_txlvl_wd;
 126:   logic intr_state_txlvl_we;
 127:   logic intr_state_rxerr_qs;
 128:   logic intr_state_rxerr_wd;
 129:   logic intr_state_rxerr_we;
 130:   logic intr_state_rxoverflow_qs;
 131:   logic intr_state_rxoverflow_wd;
 132:   logic intr_state_rxoverflow_we;
 133:   logic intr_state_txunderflow_qs;
 134:   logic intr_state_txunderflow_wd;
 135:   logic intr_state_txunderflow_we;
 136:   logic intr_enable_rxf_qs;
 137:   logic intr_enable_rxf_wd;
 138:   logic intr_enable_rxf_we;
 139:   logic intr_enable_rxlvl_qs;
 140:   logic intr_enable_rxlvl_wd;
 141:   logic intr_enable_rxlvl_we;
 142:   logic intr_enable_txlvl_qs;
 143:   logic intr_enable_txlvl_wd;
 144:   logic intr_enable_txlvl_we;
 145:   logic intr_enable_rxerr_qs;
 146:   logic intr_enable_rxerr_wd;
 147:   logic intr_enable_rxerr_we;
 148:   logic intr_enable_rxoverflow_qs;
 149:   logic intr_enable_rxoverflow_wd;
 150:   logic intr_enable_rxoverflow_we;
 151:   logic intr_enable_txunderflow_qs;
 152:   logic intr_enable_txunderflow_wd;
 153:   logic intr_enable_txunderflow_we;
 154:   logic intr_test_rxf_wd;
 155:   logic intr_test_rxf_we;
 156:   logic intr_test_rxlvl_wd;
 157:   logic intr_test_rxlvl_we;
 158:   logic intr_test_txlvl_wd;
 159:   logic intr_test_txlvl_we;
 160:   logic intr_test_rxerr_wd;
 161:   logic intr_test_rxerr_we;
 162:   logic intr_test_rxoverflow_wd;
 163:   logic intr_test_rxoverflow_we;
 164:   logic intr_test_txunderflow_wd;
 165:   logic intr_test_txunderflow_we;
 166:   logic control_abort_qs;
 167:   logic control_abort_wd;
 168:   logic control_abort_we;
 169:   logic [1:0] control_mode_qs;
 170:   logic [1:0] control_mode_wd;
 171:   logic control_mode_we;
 172:   logic control_rst_txfifo_qs;
 173:   logic control_rst_txfifo_wd;
 174:   logic control_rst_txfifo_we;
 175:   logic control_rst_rxfifo_qs;
 176:   logic control_rst_rxfifo_wd;
 177:   logic control_rst_rxfifo_we;
 178:   logic cfg_cpol_qs;
 179:   logic cfg_cpol_wd;
 180:   logic cfg_cpol_we;
 181:   logic cfg_cpha_qs;
 182:   logic cfg_cpha_wd;
 183:   logic cfg_cpha_we;
 184:   logic cfg_tx_order_qs;
 185:   logic cfg_tx_order_wd;
 186:   logic cfg_tx_order_we;
 187:   logic cfg_rx_order_qs;
 188:   logic cfg_rx_order_wd;
 189:   logic cfg_rx_order_we;
 190:   logic [7:0] cfg_timer_v_qs;
 191:   logic [7:0] cfg_timer_v_wd;
 192:   logic cfg_timer_v_we;
 193:   logic [15:0] fifo_level_rxlvl_qs;
 194:   logic [15:0] fifo_level_rxlvl_wd;
 195:   logic fifo_level_rxlvl_we;
 196:   logic [15:0] fifo_level_txlvl_qs;
 197:   logic [15:0] fifo_level_txlvl_wd;
 198:   logic fifo_level_txlvl_we;
 199:   logic [7:0] async_fifo_level_rxlvl_qs;
 200:   logic async_fifo_level_rxlvl_re;
 201:   logic [7:0] async_fifo_level_txlvl_qs;
 202:   logic async_fifo_level_txlvl_re;
 203:   logic status_rxf_full_qs;
 204:   logic status_rxf_full_re;
 205:   logic status_rxf_empty_qs;
 206:   logic status_rxf_empty_re;
 207:   logic status_txf_full_qs;
 208:   logic status_txf_full_re;
 209:   logic status_txf_empty_qs;
 210:   logic status_txf_empty_re;
 211:   logic status_abort_done_qs;
 212:   logic status_abort_done_re;
 213:   logic status_csb_qs;
 214:   logic status_csb_re;
 215:   logic [15:0] rxf_ptr_rptr_qs;
 216:   logic [15:0] rxf_ptr_rptr_wd;
 217:   logic rxf_ptr_rptr_we;
 218:   logic [15:0] rxf_ptr_wptr_qs;
 219:   logic [15:0] txf_ptr_rptr_qs;
 220:   logic [15:0] txf_ptr_wptr_qs;
 221:   logic [15:0] txf_ptr_wptr_wd;
 222:   logic txf_ptr_wptr_we;
 223:   logic [15:0] rxf_addr_base_qs;
 224:   logic [15:0] rxf_addr_base_wd;
 225:   logic rxf_addr_base_we;
 226:   logic [15:0] rxf_addr_limit_qs;
 227:   logic [15:0] rxf_addr_limit_wd;
 228:   logic rxf_addr_limit_we;
 229:   logic [15:0] txf_addr_base_qs;
 230:   logic [15:0] txf_addr_base_wd;
 231:   logic txf_addr_base_we;
 232:   logic [15:0] txf_addr_limit_qs;
 233:   logic [15:0] txf_addr_limit_wd;
 234:   logic txf_addr_limit_we;
 235: 
 236:   // Register instances
 237:   // R[intr_state]: V(False)
 238: 
 239:   //   F[rxf]: 0:0
 240:   prim_subreg #(
 241:     .DW      (1),
 242:     .SWACCESS("W1C"),
 243:     .RESVAL  (1'h0)
 244:   ) u_intr_state_rxf (
 245:     .clk_i   (clk_i    ),
 246:     .rst_ni  (rst_ni  ),
 247: 
 248:     // from register interface
 249:     .we     (intr_state_rxf_we),
 250:     .wd     (intr_state_rxf_wd),
 251: 
 252:     // from internal hardware
 253:     .de     (hw2reg.intr_state.rxf.de),
 254:     .d      (hw2reg.intr_state.rxf.d ),
 255: 
 256:     // to internal hardware
 257:     .qe     (),
 258:     .q      (reg2hw.intr_state.rxf.q ),
 259: 
 260:     // to register interface (read)
 261:     .qs     (intr_state_rxf_qs)
 262:   );
 263: 
 264: 
 265:   //   F[rxlvl]: 1:1
 266:   prim_subreg #(
 267:     .DW      (1),
 268:     .SWACCESS("W1C"),
 269:     .RESVAL  (1'h0)
 270:   ) u_intr_state_rxlvl (
 271:     .clk_i   (clk_i    ),
 272:     .rst_ni  (rst_ni  ),
 273: 
 274:     // from register interface
 275:     .we     (intr_state_rxlvl_we),
 276:     .wd     (intr_state_rxlvl_wd),
 277: 
 278:     // from internal hardware
 279:     .de     (hw2reg.intr_state.rxlvl.de),
 280:     .d      (hw2reg.intr_state.rxlvl.d ),
 281: 
 282:     // to internal hardware
 283:     .qe     (),
 284:     .q      (reg2hw.intr_state.rxlvl.q ),
 285: 
 286:     // to register interface (read)
 287:     .qs     (intr_state_rxlvl_qs)
 288:   );
 289: 
 290: 
 291:   //   F[txlvl]: 2:2
 292:   prim_subreg #(
 293:     .DW      (1),
 294:     .SWACCESS("W1C"),
 295:     .RESVAL  (1'h0)
 296:   ) u_intr_state_txlvl (
 297:     .clk_i   (clk_i    ),
 298:     .rst_ni  (rst_ni  ),
 299: 
 300:     // from register interface
 301:     .we     (intr_state_txlvl_we),
 302:     .wd     (intr_state_txlvl_wd),
 303: 
 304:     // from internal hardware
 305:     .de     (hw2reg.intr_state.txlvl.de),
 306:     .d      (hw2reg.intr_state.txlvl.d ),
 307: 
 308:     // to internal hardware
 309:     .qe     (),
 310:     .q      (reg2hw.intr_state.txlvl.q ),
 311: 
 312:     // to register interface (read)
 313:     .qs     (intr_state_txlvl_qs)
 314:   );
 315: 
 316: 
 317:   //   F[rxerr]: 3:3
 318:   prim_subreg #(
 319:     .DW      (1),
 320:     .SWACCESS("W1C"),
 321:     .RESVAL  (1'h0)
 322:   ) u_intr_state_rxerr (
 323:     .clk_i   (clk_i    ),
 324:     .rst_ni  (rst_ni  ),
 325: 
 326:     // from register interface
 327:     .we     (intr_state_rxerr_we),
 328:     .wd     (intr_state_rxerr_wd),
 329: 
 330:     // from internal hardware
 331:     .de     (hw2reg.intr_state.rxerr.de),
 332:     .d      (hw2reg.intr_state.rxerr.d ),
 333: 
 334:     // to internal hardware
 335:     .qe     (),
 336:     .q      (reg2hw.intr_state.rxerr.q ),
 337: 
 338:     // to register interface (read)
 339:     .qs     (intr_state_rxerr_qs)
 340:   );
 341: 
 342: 
 343:   //   F[rxoverflow]: 4:4
 344:   prim_subreg #(
 345:     .DW      (1),
 346:     .SWACCESS("W1C"),
 347:     .RESVAL  (1'h0)
 348:   ) u_intr_state_rxoverflow (
 349:     .clk_i   (clk_i    ),
 350:     .rst_ni  (rst_ni  ),
 351: 
 352:     // from register interface
 353:     .we     (intr_state_rxoverflow_we),
 354:     .wd     (intr_state_rxoverflow_wd),
 355: 
 356:     // from internal hardware
 357:     .de     (hw2reg.intr_state.rxoverflow.de),
 358:     .d      (hw2reg.intr_state.rxoverflow.d ),
 359: 
 360:     // to internal hardware
 361:     .qe     (),
 362:     .q      (reg2hw.intr_state.rxoverflow.q ),
 363: 
 364:     // to register interface (read)
 365:     .qs     (intr_state_rxoverflow_qs)
 366:   );
 367: 
 368: 
 369:   //   F[txunderflow]: 5:5
 370:   prim_subreg #(
 371:     .DW      (1),
 372:     .SWACCESS("W1C"),
 373:     .RESVAL  (1'h0)
 374:   ) u_intr_state_txunderflow (
 375:     .clk_i   (clk_i    ),
 376:     .rst_ni  (rst_ni  ),
 377: 
 378:     // from register interface
 379:     .we     (intr_state_txunderflow_we),
 380:     .wd     (intr_state_txunderflow_wd),
 381: 
 382:     // from internal hardware
 383:     .de     (hw2reg.intr_state.txunderflow.de),
 384:     .d      (hw2reg.intr_state.txunderflow.d ),
 385: 
 386:     // to internal hardware
 387:     .qe     (),
 388:     .q      (reg2hw.intr_state.txunderflow.q ),
 389: 
 390:     // to register interface (read)
 391:     .qs     (intr_state_txunderflow_qs)
 392:   );
 393: 
 394: 
 395:   // R[intr_enable]: V(False)
 396: 
 397:   //   F[rxf]: 0:0
 398:   prim_subreg #(
 399:     .DW      (1),
 400:     .SWACCESS("RW"),
 401:     .RESVAL  (1'h0)
 402:   ) u_intr_enable_rxf (
 403:     .clk_i   (clk_i    ),
 404:     .rst_ni  (rst_ni  ),
 405: 
 406:     // from register interface
 407:     .we     (intr_enable_rxf_we),
 408:     .wd     (intr_enable_rxf_wd),
 409: 
 410:     // from internal hardware
 411:     .de     (1'b0),
 412:     .d      ('0  ),
 413: 
 414:     // to internal hardware
 415:     .qe     (),
 416:     .q      (reg2hw.intr_enable.rxf.q ),
 417: 
 418:     // to register interface (read)
 419:     .qs     (intr_enable_rxf_qs)
 420:   );
 421: 
 422: 
 423:   //   F[rxlvl]: 1:1
 424:   prim_subreg #(
 425:     .DW      (1),
 426:     .SWACCESS("RW"),
 427:     .RESVAL  (1'h0)
 428:   ) u_intr_enable_rxlvl (
 429:     .clk_i   (clk_i    ),
 430:     .rst_ni  (rst_ni  ),
 431: 
 432:     // from register interface
 433:     .we     (intr_enable_rxlvl_we),
 434:     .wd     (intr_enable_rxlvl_wd),
 435: 
 436:     // from internal hardware
 437:     .de     (1'b0),
 438:     .d      ('0  ),
 439: 
 440:     // to internal hardware
 441:     .qe     (),
 442:     .q      (reg2hw.intr_enable.rxlvl.q ),
 443: 
 444:     // to register interface (read)
 445:     .qs     (intr_enable_rxlvl_qs)
 446:   );
 447: 
 448: 
 449:   //   F[txlvl]: 2:2
 450:   prim_subreg #(
 451:     .DW      (1),
 452:     .SWACCESS("RW"),
 453:     .RESVAL  (1'h0)
 454:   ) u_intr_enable_txlvl (
 455:     .clk_i   (clk_i    ),
 456:     .rst_ni  (rst_ni  ),
 457: 
 458:     // from register interface
 459:     .we     (intr_enable_txlvl_we),
 460:     .wd     (intr_enable_txlvl_wd),
 461: 
 462:     // from internal hardware
 463:     .de     (1'b0),
 464:     .d      ('0  ),
 465: 
 466:     // to internal hardware
 467:     .qe     (),
 468:     .q      (reg2hw.intr_enable.txlvl.q ),
 469: 
 470:     // to register interface (read)
 471:     .qs     (intr_enable_txlvl_qs)
 472:   );
 473: 
 474: 
 475:   //   F[rxerr]: 3:3
 476:   prim_subreg #(
 477:     .DW      (1),
 478:     .SWACCESS("RW"),
 479:     .RESVAL  (1'h0)
 480:   ) u_intr_enable_rxerr (
 481:     .clk_i   (clk_i    ),
 482:     .rst_ni  (rst_ni  ),
 483: 
 484:     // from register interface
 485:     .we     (intr_enable_rxerr_we),
 486:     .wd     (intr_enable_rxerr_wd),
 487: 
 488:     // from internal hardware
 489:     .de     (1'b0),
 490:     .d      ('0  ),
 491: 
 492:     // to internal hardware
 493:     .qe     (),
 494:     .q      (reg2hw.intr_enable.rxerr.q ),
 495: 
 496:     // to register interface (read)
 497:     .qs     (intr_enable_rxerr_qs)
 498:   );
 499: 
 500: 
 501:   //   F[rxoverflow]: 4:4
 502:   prim_subreg #(
 503:     .DW      (1),
 504:     .SWACCESS("RW"),
 505:     .RESVAL  (1'h0)
 506:   ) u_intr_enable_rxoverflow (
 507:     .clk_i   (clk_i    ),
 508:     .rst_ni  (rst_ni  ),
 509: 
 510:     // from register interface
 511:     .we     (intr_enable_rxoverflow_we),
 512:     .wd     (intr_enable_rxoverflow_wd),
 513: 
 514:     // from internal hardware
 515:     .de     (1'b0),
 516:     .d      ('0  ),
 517: 
 518:     // to internal hardware
 519:     .qe     (),
 520:     .q      (reg2hw.intr_enable.rxoverflow.q ),
 521: 
 522:     // to register interface (read)
 523:     .qs     (intr_enable_rxoverflow_qs)
 524:   );
 525: 
 526: 
 527:   //   F[txunderflow]: 5:5
 528:   prim_subreg #(
 529:     .DW      (1),
 530:     .SWACCESS("RW"),
 531:     .RESVAL  (1'h0)
 532:   ) u_intr_enable_txunderflow (
 533:     .clk_i   (clk_i    ),
 534:     .rst_ni  (rst_ni  ),
 535: 
 536:     // from register interface
 537:     .we     (intr_enable_txunderflow_we),
 538:     .wd     (intr_enable_txunderflow_wd),
 539: 
 540:     // from internal hardware
 541:     .de     (1'b0),
 542:     .d      ('0  ),
 543: 
 544:     // to internal hardware
 545:     .qe     (),
 546:     .q      (reg2hw.intr_enable.txunderflow.q ),
 547: 
 548:     // to register interface (read)
 549:     .qs     (intr_enable_txunderflow_qs)
 550:   );
 551: 
 552: 
 553:   // R[intr_test]: V(True)
 554: 
 555:   //   F[rxf]: 0:0
 556:   prim_subreg_ext #(
 557:     .DW    (1)
 558:   ) u_intr_test_rxf (
 559:     .re     (1'b0),
 560:     .we     (intr_test_rxf_we),
 561:     .wd     (intr_test_rxf_wd),
 562:     .d      ('0),
 563:     .qre    (),
 564:     .qe     (reg2hw.intr_test.rxf.qe),
 565:     .q      (reg2hw.intr_test.rxf.q ),
 566:     .qs     ()
 567:   );
 568: 
 569: 
 570:   //   F[rxlvl]: 1:1
 571:   prim_subreg_ext #(
 572:     .DW    (1)
 573:   ) u_intr_test_rxlvl (
 574:     .re     (1'b0),
 575:     .we     (intr_test_rxlvl_we),
 576:     .wd     (intr_test_rxlvl_wd),
 577:     .d      ('0),
 578:     .qre    (),
 579:     .qe     (reg2hw.intr_test.rxlvl.qe),
 580:     .q      (reg2hw.intr_test.rxlvl.q ),
 581:     .qs     ()
 582:   );
 583: 
 584: 
 585:   //   F[txlvl]: 2:2
 586:   prim_subreg_ext #(
 587:     .DW    (1)
 588:   ) u_intr_test_txlvl (
 589:     .re     (1'b0),
 590:     .we     (intr_test_txlvl_we),
 591:     .wd     (intr_test_txlvl_wd),
 592:     .d      ('0),
 593:     .qre    (),
 594:     .qe     (reg2hw.intr_test.txlvl.qe),
 595:     .q      (reg2hw.intr_test.txlvl.q ),
 596:     .qs     ()
 597:   );
 598: 
 599: 
 600:   //   F[rxerr]: 3:3
 601:   prim_subreg_ext #(
 602:     .DW    (1)
 603:   ) u_intr_test_rxerr (
 604:     .re     (1'b0),
 605:     .we     (intr_test_rxerr_we),
 606:     .wd     (intr_test_rxerr_wd),
 607:     .d      ('0),
 608:     .qre    (),
 609:     .qe     (reg2hw.intr_test.rxerr.qe),
 610:     .q      (reg2hw.intr_test.rxerr.q ),
 611:     .qs     ()
 612:   );
 613: 
 614: 
 615:   //   F[rxoverflow]: 4:4
 616:   prim_subreg_ext #(
 617:     .DW    (1)
 618:   ) u_intr_test_rxoverflow (
 619:     .re     (1'b0),
 620:     .we     (intr_test_rxoverflow_we),
 621:     .wd     (intr_test_rxoverflow_wd),
 622:     .d      ('0),
 623:     .qre    (),
 624:     .qe     (reg2hw.intr_test.rxoverflow.qe),
 625:     .q      (reg2hw.intr_test.rxoverflow.q ),
 626:     .qs     ()
 627:   );
 628: 
 629: 
 630:   //   F[txunderflow]: 5:5
 631:   prim_subreg_ext #(
 632:     .DW    (1)
 633:   ) u_intr_test_txunderflow (
 634:     .re     (1'b0),
 635:     .we     (intr_test_txunderflow_we),
 636:     .wd     (intr_test_txunderflow_wd),
 637:     .d      ('0),
 638:     .qre    (),
 639:     .qe     (reg2hw.intr_test.txunderflow.qe),
 640:     .q      (reg2hw.intr_test.txunderflow.q ),
 641:     .qs     ()
 642:   );
 643: 
 644: 
 645:   // R[control]: V(False)
 646: 
 647:   //   F[abort]: 0:0
 648:   prim_subreg #(
 649:     .DW      (1),
 650:     .SWACCESS("RW"),
 651:     .RESVAL  (1'h0)
 652:   ) u_control_abort (
 653:     .clk_i   (clk_i    ),
 654:     .rst_ni  (rst_ni  ),
 655: 
 656:     // from register interface
 657:     .we     (control_abort_we),
 658:     .wd     (control_abort_wd),
 659: 
 660:     // from internal hardware
 661:     .de     (1'b0),
 662:     .d      ('0  ),
 663: 
 664:     // to internal hardware
 665:     .qe     (),
 666:     .q      (reg2hw.control.abort.q ),
 667: 
 668:     // to register interface (read)
 669:     .qs     (control_abort_qs)
 670:   );
 671: 
 672: 
 673:   //   F[mode]: 5:4
 674:   prim_subreg #(
 675:     .DW      (2),
 676:     .SWACCESS("RW"),
 677:     .RESVAL  (2'h0)
 678:   ) u_control_mode (
 679:     .clk_i   (clk_i    ),
 680:     .rst_ni  (rst_ni  ),
 681: 
 682:     // from register interface
 683:     .we     (control_mode_we),
 684:     .wd     (control_mode_wd),
 685: 
 686:     // from internal hardware
 687:     .de     (1'b0),
 688:     .d      ('0  ),
 689: 
 690:     // to internal hardware
 691:     .qe     (),
 692:     .q      (reg2hw.control.mode.q ),
 693: 
 694:     // to register interface (read)
 695:     .qs     (control_mode_qs)
 696:   );
 697: 
 698: 
 699:   //   F[rst_txfifo]: 16:16
 700:   prim_subreg #(
 701:     .DW      (1),
 702:     .SWACCESS("RW"),
 703:     .RESVAL  (1'h0)
 704:   ) u_control_rst_txfifo (
 705:     .clk_i   (clk_i    ),
 706:     .rst_ni  (rst_ni  ),
 707: 
 708:     // from register interface
 709:     .we     (control_rst_txfifo_we),
 710:     .wd     (control_rst_txfifo_wd),
 711: 
 712:     // from internal hardware
 713:     .de     (1'b0),
 714:     .d      ('0  ),
 715: 
 716:     // to internal hardware
 717:     .qe     (),
 718:     .q      (reg2hw.control.rst_txfifo.q ),
 719: 
 720:     // to register interface (read)
 721:     .qs     (control_rst_txfifo_qs)
 722:   );
 723: 
 724: 
 725:   //   F[rst_rxfifo]: 17:17
 726:   prim_subreg #(
 727:     .DW      (1),
 728:     .SWACCESS("RW"),
 729:     .RESVAL  (1'h0)
 730:   ) u_control_rst_rxfifo (
 731:     .clk_i   (clk_i    ),
 732:     .rst_ni  (rst_ni  ),
 733: 
 734:     // from register interface
 735:     .we     (control_rst_rxfifo_we),
 736:     .wd     (control_rst_rxfifo_wd),
 737: 
 738:     // from internal hardware
 739:     .de     (1'b0),
 740:     .d      ('0  ),
 741: 
 742:     // to internal hardware
 743:     .qe     (),
 744:     .q      (reg2hw.control.rst_rxfifo.q ),
 745: 
 746:     // to register interface (read)
 747:     .qs     (control_rst_rxfifo_qs)
 748:   );
 749: 
 750: 
 751:   // R[cfg]: V(False)
 752: 
 753:   //   F[cpol]: 0:0
 754:   prim_subreg #(
 755:     .DW      (1),
 756:     .SWACCESS("RW"),
 757:     .RESVAL  (1'h0)
 758:   ) u_cfg_cpol (
 759:     .clk_i   (clk_i    ),
 760:     .rst_ni  (rst_ni  ),
 761: 
 762:     // from register interface
 763:     .we     (cfg_cpol_we),
 764:     .wd     (cfg_cpol_wd),
 765: 
 766:     // from internal hardware
 767:     .de     (1'b0),
 768:     .d      ('0  ),
 769: 
 770:     // to internal hardware
 771:     .qe     (),
 772:     .q      (reg2hw.cfg.cpol.q ),
 773: 
 774:     // to register interface (read)
 775:     .qs     (cfg_cpol_qs)
 776:   );
 777: 
 778: 
 779:   //   F[cpha]: 1:1
 780:   prim_subreg #(
 781:     .DW      (1),
 782:     .SWACCESS("RW"),
 783:     .RESVAL  (1'h0)
 784:   ) u_cfg_cpha (
 785:     .clk_i   (clk_i    ),
 786:     .rst_ni  (rst_ni  ),
 787: 
 788:     // from register interface
 789:     .we     (cfg_cpha_we),
 790:     .wd     (cfg_cpha_wd),
 791: 
 792:     // from internal hardware
 793:     .de     (1'b0),
 794:     .d      ('0  ),
 795: 
 796:     // to internal hardware
 797:     .qe     (),
 798:     .q      (reg2hw.cfg.cpha.q ),
 799: 
 800:     // to register interface (read)
 801:     .qs     (cfg_cpha_qs)
 802:   );
 803: 
 804: 
 805:   //   F[tx_order]: 2:2
 806:   prim_subreg #(
 807:     .DW      (1),
 808:     .SWACCESS("RW"),
 809:     .RESVAL  (1'h0)
 810:   ) u_cfg_tx_order (
 811:     .clk_i   (clk_i    ),
 812:     .rst_ni  (rst_ni  ),
 813: 
 814:     // from register interface
 815:     .we     (cfg_tx_order_we),
 816:     .wd     (cfg_tx_order_wd),
 817: 
 818:     // from internal hardware
 819:     .de     (1'b0),
 820:     .d      ('0  ),
 821: 
 822:     // to internal hardware
 823:     .qe     (),
 824:     .q      (reg2hw.cfg.tx_order.q ),
 825: 
 826:     // to register interface (read)
 827:     .qs     (cfg_tx_order_qs)
 828:   );
 829: 
 830: 
 831:   //   F[rx_order]: 3:3
 832:   prim_subreg #(
 833:     .DW      (1),
 834:     .SWACCESS("RW"),
 835:     .RESVAL  (1'h0)
 836:   ) u_cfg_rx_order (
 837:     .clk_i   (clk_i    ),
 838:     .rst_ni  (rst_ni  ),
 839: 
 840:     // from register interface
 841:     .we     (cfg_rx_order_we),
 842:     .wd     (cfg_rx_order_wd),
 843: 
 844:     // from internal hardware
 845:     .de     (1'b0),
 846:     .d      ('0  ),
 847: 
 848:     // to internal hardware
 849:     .qe     (),
 850:     .q      (reg2hw.cfg.rx_order.q ),
 851: 
 852:     // to register interface (read)
 853:     .qs     (cfg_rx_order_qs)
 854:   );
 855: 
 856: 
 857:   //   F[timer_v]: 15:8
 858:   prim_subreg #(
 859:     .DW      (8),
 860:     .SWACCESS("RW"),
 861:     .RESVAL  (8'h7f)
 862:   ) u_cfg_timer_v (
 863:     .clk_i   (clk_i    ),
 864:     .rst_ni  (rst_ni  ),
 865: 
 866:     // from register interface
 867:     .we     (cfg_timer_v_we),
 868:     .wd     (cfg_timer_v_wd),
 869: 
 870:     // from internal hardware
 871:     .de     (1'b0),
 872:     .d      ('0  ),
 873: 
 874:     // to internal hardware
 875:     .qe     (),
 876:     .q      (reg2hw.cfg.timer_v.q ),
 877: 
 878:     // to register interface (read)
 879:     .qs     (cfg_timer_v_qs)
 880:   );
 881: 
 882: 
 883:   // R[fifo_level]: V(False)
 884: 
 885:   //   F[rxlvl]: 15:0
 886:   prim_subreg #(
 887:     .DW      (16),
 888:     .SWACCESS("RW"),
 889:     .RESVAL  (16'h80)
 890:   ) u_fifo_level_rxlvl (
 891:     .clk_i   (clk_i    ),
 892:     .rst_ni  (rst_ni  ),
 893: 
 894:     // from register interface
 895:     .we     (fifo_level_rxlvl_we),
 896:     .wd     (fifo_level_rxlvl_wd),
 897: 
 898:     // from internal hardware
 899:     .de     (1'b0),
 900:     .d      ('0  ),
 901: 
 902:     // to internal hardware
 903:     .qe     (),
 904:     .q      (reg2hw.fifo_level.rxlvl.q ),
 905: 
 906:     // to register interface (read)
 907:     .qs     (fifo_level_rxlvl_qs)
 908:   );
 909: 
 910: 
 911:   //   F[txlvl]: 31:16
 912:   prim_subreg #(
 913:     .DW      (16),
 914:     .SWACCESS("RW"),
 915:     .RESVAL  (16'h0)
 916:   ) u_fifo_level_txlvl (
 917:     .clk_i   (clk_i    ),
 918:     .rst_ni  (rst_ni  ),
 919: 
 920:     // from register interface
 921:     .we     (fifo_level_txlvl_we),
 922:     .wd     (fifo_level_txlvl_wd),
 923: 
 924:     // from internal hardware
 925:     .de     (1'b0),
 926:     .d      ('0  ),
 927: 
 928:     // to internal hardware
 929:     .qe     (),
 930:     .q      (reg2hw.fifo_level.txlvl.q ),
 931: 
 932:     // to register interface (read)
 933:     .qs     (fifo_level_txlvl_qs)
 934:   );
 935: 
 936: 
 937:   // R[async_fifo_level]: V(True)
 938: 
 939:   //   F[rxlvl]: 7:0
 940:   prim_subreg_ext #(
 941:     .DW    (8)
 942:   ) u_async_fifo_level_rxlvl (
 943:     .re     (async_fifo_level_rxlvl_re),
 944:     .we     (1'b0),
 945:     .wd     ('0),
 946:     .d      (hw2reg.async_fifo_level.rxlvl.d),
 947:     .qre    (),
 948:     .qe     (),
 949:     .q      (),
 950:     .qs     (async_fifo_level_rxlvl_qs)
 951:   );
 952: 
 953: 
 954:   //   F[txlvl]: 23:16
 955:   prim_subreg_ext #(
 956:     .DW    (8)
 957:   ) u_async_fifo_level_txlvl (
 958:     .re     (async_fifo_level_txlvl_re),
 959:     .we     (1'b0),
 960:     .wd     ('0),
 961:     .d      (hw2reg.async_fifo_level.txlvl.d),
 962:     .qre    (),
 963:     .qe     (),
 964:     .q      (),
 965:     .qs     (async_fifo_level_txlvl_qs)
 966:   );
 967: 
 968: 
 969:   // R[status]: V(True)
 970: 
 971:   //   F[rxf_full]: 0:0
 972:   prim_subreg_ext #(
 973:     .DW    (1)
 974:   ) u_status_rxf_full (
 975:     .re     (status_rxf_full_re),
 976:     .we     (1'b0),
 977:     .wd     ('0),
 978:     .d      (hw2reg.status.rxf_full.d),
 979:     .qre    (),
 980:     .qe     (),
 981:     .q      (),
 982:     .qs     (status_rxf_full_qs)
 983:   );
 984: 
 985: 
 986:   //   F[rxf_empty]: 1:1
 987:   prim_subreg_ext #(
 988:     .DW    (1)
 989:   ) u_status_rxf_empty (
 990:     .re     (status_rxf_empty_re),
 991:     .we     (1'b0),
 992:     .wd     ('0),
 993:     .d      (hw2reg.status.rxf_empty.d),
 994:     .qre    (),
 995:     .qe     (),
 996:     .q      (),
 997:     .qs     (status_rxf_empty_qs)
 998:   );
 999: 
1000: 
1001:   //   F[txf_full]: 2:2
1002:   prim_subreg_ext #(
1003:     .DW    (1)
1004:   ) u_status_txf_full (
1005:     .re     (status_txf_full_re),
1006:     .we     (1'b0),
1007:     .wd     ('0),
1008:     .d      (hw2reg.status.txf_full.d),
1009:     .qre    (),
1010:     .qe     (),
1011:     .q      (),
1012:     .qs     (status_txf_full_qs)
1013:   );
1014: 
1015: 
1016:   //   F[txf_empty]: 3:3
1017:   prim_subreg_ext #(
1018:     .DW    (1)
1019:   ) u_status_txf_empty (
1020:     .re     (status_txf_empty_re),
1021:     .we     (1'b0),
1022:     .wd     ('0),
1023:     .d      (hw2reg.status.txf_empty.d),
1024:     .qre    (),
1025:     .qe     (),
1026:     .q      (),
1027:     .qs     (status_txf_empty_qs)
1028:   );
1029: 
1030: 
1031:   //   F[abort_done]: 4:4
1032:   prim_subreg_ext #(
1033:     .DW    (1)
1034:   ) u_status_abort_done (
1035:     .re     (status_abort_done_re),
1036:     .we     (1'b0),
1037:     .wd     ('0),
1038:     .d      (hw2reg.status.abort_done.d),
1039:     .qre    (),
1040:     .qe     (),
1041:     .q      (),
1042:     .qs     (status_abort_done_qs)
1043:   );
1044: 
1045: 
1046:   //   F[csb]: 5:5
1047:   prim_subreg_ext #(
1048:     .DW    (1)
1049:   ) u_status_csb (
1050:     .re     (status_csb_re),
1051:     .we     (1'b0),
1052:     .wd     ('0),
1053:     .d      (hw2reg.status.csb.d),
1054:     .qre    (),
1055:     .qe     (),
1056:     .q      (),
1057:     .qs     (status_csb_qs)
1058:   );
1059: 
1060: 
1061:   // R[rxf_ptr]: V(False)
1062: 
1063:   //   F[rptr]: 15:0
1064:   prim_subreg #(
1065:     .DW      (16),
1066:     .SWACCESS("RW"),
1067:     .RESVAL  (16'h0)
1068:   ) u_rxf_ptr_rptr (
1069:     .clk_i   (clk_i    ),
1070:     .rst_ni  (rst_ni  ),
1071: 
1072:     // from register interface
1073:     .we     (rxf_ptr_rptr_we),
1074:     .wd     (rxf_ptr_rptr_wd),
1075: 
1076:     // from internal hardware
1077:     .de     (1'b0),
1078:     .d      ('0  ),
1079: 
1080:     // to internal hardware
1081:     .qe     (),
1082:     .q      (reg2hw.rxf_ptr.rptr.q ),
1083: 
1084:     // to register interface (read)
1085:     .qs     (rxf_ptr_rptr_qs)
1086:   );
1087: 
1088: 
1089:   //   F[wptr]: 31:16
1090:   prim_subreg #(
1091:     .DW      (16),
1092:     .SWACCESS("RO"),
1093:     .RESVAL  (16'h0)
1094:   ) u_rxf_ptr_wptr (
1095:     .clk_i   (clk_i    ),
1096:     .rst_ni  (rst_ni  ),
1097: 
1098:     .we     (1'b0),
1099:     .wd     ('0  ),
1100: 
1101:     // from internal hardware
1102:     .de     (hw2reg.rxf_ptr.wptr.de),
1103:     .d      (hw2reg.rxf_ptr.wptr.d ),
1104: 
1105:     // to internal hardware
1106:     .qe     (),
1107:     .q      (),
1108: 
1109:     // to register interface (read)
1110:     .qs     (rxf_ptr_wptr_qs)
1111:   );
1112: 
1113: 
1114:   // R[txf_ptr]: V(False)
1115: 
1116:   //   F[rptr]: 15:0
1117:   prim_subreg #(
1118:     .DW      (16),
1119:     .SWACCESS("RO"),
1120:     .RESVAL  (16'h0)
1121:   ) u_txf_ptr_rptr (
1122:     .clk_i   (clk_i    ),
1123:     .rst_ni  (rst_ni  ),
1124: 
1125:     .we     (1'b0),
1126:     .wd     ('0  ),
1127: 
1128:     // from internal hardware
1129:     .de     (hw2reg.txf_ptr.rptr.de),
1130:     .d      (hw2reg.txf_ptr.rptr.d ),
1131: 
1132:     // to internal hardware
1133:     .qe     (),
1134:     .q      (),
1135: 
1136:     // to register interface (read)
1137:     .qs     (txf_ptr_rptr_qs)
1138:   );
1139: 
1140: 
1141:   //   F[wptr]: 31:16
1142:   prim_subreg #(
1143:     .DW      (16),
1144:     .SWACCESS("RW"),
1145:     .RESVAL  (16'h0)
1146:   ) u_txf_ptr_wptr (
1147:     .clk_i   (clk_i    ),
1148:     .rst_ni  (rst_ni  ),
1149: 
1150:     // from register interface
1151:     .we     (txf_ptr_wptr_we),
1152:     .wd     (txf_ptr_wptr_wd),
1153: 
1154:     // from internal hardware
1155:     .de     (1'b0),
1156:     .d      ('0  ),
1157: 
1158:     // to internal hardware
1159:     .qe     (),
1160:     .q      (reg2hw.txf_ptr.wptr.q ),
1161: 
1162:     // to register interface (read)
1163:     .qs     (txf_ptr_wptr_qs)
1164:   );
1165: 
1166: 
1167:   // R[rxf_addr]: V(False)
1168: 
1169:   //   F[base]: 15:0
1170:   prim_subreg #(
1171:     .DW      (16),
1172:     .SWACCESS("RW"),
1173:     .RESVAL  (16'h0)
1174:   ) u_rxf_addr_base (
1175:     .clk_i   (clk_i    ),
1176:     .rst_ni  (rst_ni  ),
1177: 
1178:     // from register interface
1179:     .we     (rxf_addr_base_we),
1180:     .wd     (rxf_addr_base_wd),
1181: 
1182:     // from internal hardware
1183:     .de     (1'b0),
1184:     .d      ('0  ),
1185: 
1186:     // to internal hardware
1187:     .qe     (),
1188:     .q      (reg2hw.rxf_addr.base.q ),
1189: 
1190:     // to register interface (read)
1191:     .qs     (rxf_addr_base_qs)
1192:   );
1193: 
1194: 
1195:   //   F[limit]: 31:16
1196:   prim_subreg #(
1197:     .DW      (16),
1198:     .SWACCESS("RW"),
1199:     .RESVAL  (16'h1fc)
1200:   ) u_rxf_addr_limit (
1201:     .clk_i   (clk_i    ),
1202:     .rst_ni  (rst_ni  ),
1203: 
1204:     // from register interface
1205:     .we     (rxf_addr_limit_we),
1206:     .wd     (rxf_addr_limit_wd),
1207: 
1208:     // from internal hardware
1209:     .de     (1'b0),
1210:     .d      ('0  ),
1211: 
1212:     // to internal hardware
1213:     .qe     (),
1214:     .q      (reg2hw.rxf_addr.limit.q ),
1215: 
1216:     // to register interface (read)
1217:     .qs     (rxf_addr_limit_qs)
1218:   );
1219: 
1220: 
1221:   // R[txf_addr]: V(False)
1222: 
1223:   //   F[base]: 15:0
1224:   prim_subreg #(
1225:     .DW      (16),
1226:     .SWACCESS("RW"),
1227:     .RESVAL  (16'h200)
1228:   ) u_txf_addr_base (
1229:     .clk_i   (clk_i    ),
1230:     .rst_ni  (rst_ni  ),
1231: 
1232:     // from register interface
1233:     .we     (txf_addr_base_we),
1234:     .wd     (txf_addr_base_wd),
1235: 
1236:     // from internal hardware
1237:     .de     (1'b0),
1238:     .d      ('0  ),
1239: 
1240:     // to internal hardware
1241:     .qe     (),
1242:     .q      (reg2hw.txf_addr.base.q ),
1243: 
1244:     // to register interface (read)
1245:     .qs     (txf_addr_base_qs)
1246:   );
1247: 
1248: 
1249:   //   F[limit]: 31:16
1250:   prim_subreg #(
1251:     .DW      (16),
1252:     .SWACCESS("RW"),
1253:     .RESVAL  (16'h3fc)
1254:   ) u_txf_addr_limit (
1255:     .clk_i   (clk_i    ),
1256:     .rst_ni  (rst_ni  ),
1257: 
1258:     // from register interface
1259:     .we     (txf_addr_limit_we),
1260:     .wd     (txf_addr_limit_wd),
1261: 
1262:     // from internal hardware
1263:     .de     (1'b0),
1264:     .d      ('0  ),
1265: 
1266:     // to internal hardware
1267:     .qe     (),
1268:     .q      (reg2hw.txf_addr.limit.q ),
1269: 
1270:     // to register interface (read)
1271:     .qs     (txf_addr_limit_qs)
1272:   );
1273: 
1274: 
1275: 
1276: 
1277:   logic [11:0] addr_hit;
1278:   always_comb begin
1279:     addr_hit = '0;
1280:     addr_hit[ 0] = (reg_addr == SPI_DEVICE_INTR_STATE_OFFSET);
1281:     addr_hit[ 1] = (reg_addr == SPI_DEVICE_INTR_ENABLE_OFFSET);
1282:     addr_hit[ 2] = (reg_addr == SPI_DEVICE_INTR_TEST_OFFSET);
1283:     addr_hit[ 3] = (reg_addr == SPI_DEVICE_CONTROL_OFFSET);
1284:     addr_hit[ 4] = (reg_addr == SPI_DEVICE_CFG_OFFSET);
1285:     addr_hit[ 5] = (reg_addr == SPI_DEVICE_FIFO_LEVEL_OFFSET);
1286:     addr_hit[ 6] = (reg_addr == SPI_DEVICE_ASYNC_FIFO_LEVEL_OFFSET);
1287:     addr_hit[ 7] = (reg_addr == SPI_DEVICE_STATUS_OFFSET);
1288:     addr_hit[ 8] = (reg_addr == SPI_DEVICE_RXF_PTR_OFFSET);
1289:     addr_hit[ 9] = (reg_addr == SPI_DEVICE_TXF_PTR_OFFSET);
1290:     addr_hit[10] = (reg_addr == SPI_DEVICE_RXF_ADDR_OFFSET);
1291:     addr_hit[11] = (reg_addr == SPI_DEVICE_TXF_ADDR_OFFSET);
1292:   end
1293: 
1294:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
1295: 
1296:   // Check sub-word write is permitted
1297:   always_comb begin
1298:     wr_err = 1'b0;
1299:     if (addr_hit[ 0] && reg_we && (SPI_DEVICE_PERMIT[ 0] != (SPI_DEVICE_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
1300:     if (addr_hit[ 1] && reg_we && (SPI_DEVICE_PERMIT[ 1] != (SPI_DEVICE_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
1301:     if (addr_hit[ 2] && reg_we && (SPI_DEVICE_PERMIT[ 2] != (SPI_DEVICE_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
1302:     if (addr_hit[ 3] && reg_we && (SPI_DEVICE_PERMIT[ 3] != (SPI_DEVICE_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
1303:     if (addr_hit[ 4] && reg_we && (SPI_DEVICE_PERMIT[ 4] != (SPI_DEVICE_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
1304:     if (addr_hit[ 5] && reg_we && (SPI_DEVICE_PERMIT[ 5] != (SPI_DEVICE_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
1305:     if (addr_hit[ 6] && reg_we && (SPI_DEVICE_PERMIT[ 6] != (SPI_DEVICE_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
1306:     if (addr_hit[ 7] && reg_we && (SPI_DEVICE_PERMIT[ 7] != (SPI_DEVICE_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
1307:     if (addr_hit[ 8] && reg_we && (SPI_DEVICE_PERMIT[ 8] != (SPI_DEVICE_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
1308:     if (addr_hit[ 9] && reg_we && (SPI_DEVICE_PERMIT[ 9] != (SPI_DEVICE_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
1309:     if (addr_hit[10] && reg_we && (SPI_DEVICE_PERMIT[10] != (SPI_DEVICE_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
1310:     if (addr_hit[11] && reg_we && (SPI_DEVICE_PERMIT[11] != (SPI_DEVICE_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
1311:   end
1312: 
1313:   assign intr_state_rxf_we = addr_hit[0] & reg_we & ~wr_err;
1314:   assign intr_state_rxf_wd = reg_wdata[0];
1315: 
1316:   assign intr_state_rxlvl_we = addr_hit[0] & reg_we & ~wr_err;
1317:   assign intr_state_rxlvl_wd = reg_wdata[1];
1318: 
1319:   assign intr_state_txlvl_we = addr_hit[0] & reg_we & ~wr_err;
1320:   assign intr_state_txlvl_wd = reg_wdata[2];
1321: 
1322:   assign intr_state_rxerr_we = addr_hit[0] & reg_we & ~wr_err;
1323:   assign intr_state_rxerr_wd = reg_wdata[3];
1324: 
1325:   assign intr_state_rxoverflow_we = addr_hit[0] & reg_we & ~wr_err;
1326:   assign intr_state_rxoverflow_wd = reg_wdata[4];
1327: 
1328:   assign intr_state_txunderflow_we = addr_hit[0] & reg_we & ~wr_err;
1329:   assign intr_state_txunderflow_wd = reg_wdata[5];
1330: 
1331:   assign intr_enable_rxf_we = addr_hit[1] & reg_we & ~wr_err;
1332:   assign intr_enable_rxf_wd = reg_wdata[0];
1333: 
1334:   assign intr_enable_rxlvl_we = addr_hit[1] & reg_we & ~wr_err;
1335:   assign intr_enable_rxlvl_wd = reg_wdata[1];
1336: 
1337:   assign intr_enable_txlvl_we = addr_hit[1] & reg_we & ~wr_err;
1338:   assign intr_enable_txlvl_wd = reg_wdata[2];
1339: 
1340:   assign intr_enable_rxerr_we = addr_hit[1] & reg_we & ~wr_err;
1341:   assign intr_enable_rxerr_wd = reg_wdata[3];
1342: 
1343:   assign intr_enable_rxoverflow_we = addr_hit[1] & reg_we & ~wr_err;
1344:   assign intr_enable_rxoverflow_wd = reg_wdata[4];
1345: 
1346:   assign intr_enable_txunderflow_we = addr_hit[1] & reg_we & ~wr_err;
1347:   assign intr_enable_txunderflow_wd = reg_wdata[5];
1348: 
1349:   assign intr_test_rxf_we = addr_hit[2] & reg_we & ~wr_err;
1350:   assign intr_test_rxf_wd = reg_wdata[0];
1351: 
1352:   assign intr_test_rxlvl_we = addr_hit[2] & reg_we & ~wr_err;
1353:   assign intr_test_rxlvl_wd = reg_wdata[1];
1354: 
1355:   assign intr_test_txlvl_we = addr_hit[2] & reg_we & ~wr_err;
1356:   assign intr_test_txlvl_wd = reg_wdata[2];
1357: 
1358:   assign intr_test_rxerr_we = addr_hit[2] & reg_we & ~wr_err;
1359:   assign intr_test_rxerr_wd = reg_wdata[3];
1360: 
1361:   assign intr_test_rxoverflow_we = addr_hit[2] & reg_we & ~wr_err;
1362:   assign intr_test_rxoverflow_wd = reg_wdata[4];
1363: 
1364:   assign intr_test_txunderflow_we = addr_hit[2] & reg_we & ~wr_err;
1365:   assign intr_test_txunderflow_wd = reg_wdata[5];
1366: 
1367:   assign control_abort_we = addr_hit[3] & reg_we & ~wr_err;
1368:   assign control_abort_wd = reg_wdata[0];
1369: 
1370:   assign control_mode_we = addr_hit[3] & reg_we & ~wr_err;
1371:   assign control_mode_wd = reg_wdata[5:4];
1372: 
1373:   assign control_rst_txfifo_we = addr_hit[3] & reg_we & ~wr_err;
1374:   assign control_rst_txfifo_wd = reg_wdata[16];
1375: 
1376:   assign control_rst_rxfifo_we = addr_hit[3] & reg_we & ~wr_err;
1377:   assign control_rst_rxfifo_wd = reg_wdata[17];
1378: 
1379:   assign cfg_cpol_we = addr_hit[4] & reg_we & ~wr_err;
1380:   assign cfg_cpol_wd = reg_wdata[0];
1381: 
1382:   assign cfg_cpha_we = addr_hit[4] & reg_we & ~wr_err;
1383:   assign cfg_cpha_wd = reg_wdata[1];
1384: 
1385:   assign cfg_tx_order_we = addr_hit[4] & reg_we & ~wr_err;
1386:   assign cfg_tx_order_wd = reg_wdata[2];
1387: 
1388:   assign cfg_rx_order_we = addr_hit[4] & reg_we & ~wr_err;
1389:   assign cfg_rx_order_wd = reg_wdata[3];
1390: 
1391:   assign cfg_timer_v_we = addr_hit[4] & reg_we & ~wr_err;
1392:   assign cfg_timer_v_wd = reg_wdata[15:8];
1393: 
1394:   assign fifo_level_rxlvl_we = addr_hit[5] & reg_we & ~wr_err;
1395:   assign fifo_level_rxlvl_wd = reg_wdata[15:0];
1396: 
1397:   assign fifo_level_txlvl_we = addr_hit[5] & reg_we & ~wr_err;
1398:   assign fifo_level_txlvl_wd = reg_wdata[31:16];
1399: 
1400:   assign async_fifo_level_rxlvl_re = addr_hit[6] && reg_re;
1401: 
1402:   assign async_fifo_level_txlvl_re = addr_hit[6] && reg_re;
1403: 
1404:   assign status_rxf_full_re = addr_hit[7] && reg_re;
1405: 
1406:   assign status_rxf_empty_re = addr_hit[7] && reg_re;
1407: 
1408:   assign status_txf_full_re = addr_hit[7] && reg_re;
1409: 
1410:   assign status_txf_empty_re = addr_hit[7] && reg_re;
1411: 
1412:   assign status_abort_done_re = addr_hit[7] && reg_re;
1413: 
1414:   assign status_csb_re = addr_hit[7] && reg_re;
1415: 
1416:   assign rxf_ptr_rptr_we = addr_hit[8] & reg_we & ~wr_err;
1417:   assign rxf_ptr_rptr_wd = reg_wdata[15:0];
1418: 
1419: 
1420: 
1421:   assign txf_ptr_wptr_we = addr_hit[9] & reg_we & ~wr_err;
1422:   assign txf_ptr_wptr_wd = reg_wdata[31:16];
1423: 
1424:   assign rxf_addr_base_we = addr_hit[10] & reg_we & ~wr_err;
1425:   assign rxf_addr_base_wd = reg_wdata[15:0];
1426: 
1427:   assign rxf_addr_limit_we = addr_hit[10] & reg_we & ~wr_err;
1428:   assign rxf_addr_limit_wd = reg_wdata[31:16];
1429: 
1430:   assign txf_addr_base_we = addr_hit[11] & reg_we & ~wr_err;
1431:   assign txf_addr_base_wd = reg_wdata[15:0];
1432: 
1433:   assign txf_addr_limit_we = addr_hit[11] & reg_we & ~wr_err;
1434:   assign txf_addr_limit_wd = reg_wdata[31:16];
1435: 
1436:   // Read data return
1437:   always_comb begin
1438:     reg_rdata_next = '0;
1439:     unique case (1'b1)
1440:       addr_hit[0]: begin
1441:         reg_rdata_next[0] = intr_state_rxf_qs;
1442:         reg_rdata_next[1] = intr_state_rxlvl_qs;
1443:         reg_rdata_next[2] = intr_state_txlvl_qs;
1444:         reg_rdata_next[3] = intr_state_rxerr_qs;
1445:         reg_rdata_next[4] = intr_state_rxoverflow_qs;
1446:         reg_rdata_next[5] = intr_state_txunderflow_qs;
1447:       end
1448: 
1449:       addr_hit[1]: begin
1450:         reg_rdata_next[0] = intr_enable_rxf_qs;
1451:         reg_rdata_next[1] = intr_enable_rxlvl_qs;
1452:         reg_rdata_next[2] = intr_enable_txlvl_qs;
1453:         reg_rdata_next[3] = intr_enable_rxerr_qs;
1454:         reg_rdata_next[4] = intr_enable_rxoverflow_qs;
1455:         reg_rdata_next[5] = intr_enable_txunderflow_qs;
1456:       end
1457: 
1458:       addr_hit[2]: begin
1459:         reg_rdata_next[0] = '0;
1460:         reg_rdata_next[1] = '0;
1461:         reg_rdata_next[2] = '0;
1462:         reg_rdata_next[3] = '0;
1463:         reg_rdata_next[4] = '0;
1464:         reg_rdata_next[5] = '0;
1465:       end
1466: 
1467:       addr_hit[3]: begin
1468:         reg_rdata_next[0] = control_abort_qs;
1469:         reg_rdata_next[5:4] = control_mode_qs;
1470:         reg_rdata_next[16] = control_rst_txfifo_qs;
1471:         reg_rdata_next[17] = control_rst_rxfifo_qs;
1472:       end
1473: 
1474:       addr_hit[4]: begin
1475:         reg_rdata_next[0] = cfg_cpol_qs;
1476:         reg_rdata_next[1] = cfg_cpha_qs;
1477:         reg_rdata_next[2] = cfg_tx_order_qs;
1478:         reg_rdata_next[3] = cfg_rx_order_qs;
1479:         reg_rdata_next[15:8] = cfg_timer_v_qs;
1480:       end
1481: 
1482:       addr_hit[5]: begin
1483:         reg_rdata_next[15:0] = fifo_level_rxlvl_qs;
1484:         reg_rdata_next[31:16] = fifo_level_txlvl_qs;
1485:       end
1486: 
1487:       addr_hit[6]: begin
1488:         reg_rdata_next[7:0] = async_fifo_level_rxlvl_qs;
1489:         reg_rdata_next[23:16] = async_fifo_level_txlvl_qs;
1490:       end
1491: 
1492:       addr_hit[7]: begin
1493:         reg_rdata_next[0] = status_rxf_full_qs;
1494:         reg_rdata_next[1] = status_rxf_empty_qs;
1495:         reg_rdata_next[2] = status_txf_full_qs;
1496:         reg_rdata_next[3] = status_txf_empty_qs;
1497:         reg_rdata_next[4] = status_abort_done_qs;
1498:         reg_rdata_next[5] = status_csb_qs;
1499:       end
1500: 
1501:       addr_hit[8]: begin
1502:         reg_rdata_next[15:0] = rxf_ptr_rptr_qs;
1503:         reg_rdata_next[31:16] = rxf_ptr_wptr_qs;
1504:       end
1505: 
1506:       addr_hit[9]: begin
1507:         reg_rdata_next[15:0] = txf_ptr_rptr_qs;
1508:         reg_rdata_next[31:16] = txf_ptr_wptr_qs;
1509:       end
1510: 
1511:       addr_hit[10]: begin
1512:         reg_rdata_next[15:0] = rxf_addr_base_qs;
1513:         reg_rdata_next[31:16] = rxf_addr_limit_qs;
1514:       end
1515: 
1516:       addr_hit[11]: begin
1517:         reg_rdata_next[15:0] = txf_addr_base_qs;
1518:         reg_rdata_next[31:16] = txf_addr_limit_qs;
1519:       end
1520: 
1521:       default: begin
1522:         reg_rdata_next = '1;
1523:       end
1524:     endcase
1525:   end
1526: 
1527:   // Assertions for Register Interface
1528:   `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
1529:   `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
1530: 
1531:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
1532: 
1533:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
1534: 
1535:   // this is formulated as an assumption such that the FPV testbenches do disprove this
1536:   // property by mistake
1537:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
1538: 
1539: endmodule
1540: