../src/lowrisc_top_earlgrey_xbar_peri_0.1/xbar_peri.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // xbar_peri module generated by `tlgen.py` tool
   6: // all reset signals should be generated from one reset signal to not make any deadlock
   7: //
   8: // Interconnect
   9: // main
  10: //   -> s1n_9
  11: //     -> uart
  12: //     -> gpio
  13: //     -> spi_device
  14: //     -> rv_timer
  15: //     -> usbdev
  16: //     -> pwrmgr
  17: //     -> rstmgr
  18: //     -> clkmgr
  19: 
  20: module xbar_peri (
  21:   input clk_peri_i,
  22:   input rst_peri_ni,
  23: 
  24:   // Host interfaces
  25:   input  tlul_pkg::tl_h2d_t tl_main_i,
  26:   output tlul_pkg::tl_d2h_t tl_main_o,
  27: 
  28:   // Device interfaces
  29:   output tlul_pkg::tl_h2d_t tl_uart_o,
  30:   input  tlul_pkg::tl_d2h_t tl_uart_i,
  31:   output tlul_pkg::tl_h2d_t tl_gpio_o,
  32:   input  tlul_pkg::tl_d2h_t tl_gpio_i,
  33:   output tlul_pkg::tl_h2d_t tl_spi_device_o,
  34:   input  tlul_pkg::tl_d2h_t tl_spi_device_i,
  35:   output tlul_pkg::tl_h2d_t tl_rv_timer_o,
  36:   input  tlul_pkg::tl_d2h_t tl_rv_timer_i,
  37:   output tlul_pkg::tl_h2d_t tl_usbdev_o,
  38:   input  tlul_pkg::tl_d2h_t tl_usbdev_i,
  39:   output tlul_pkg::tl_h2d_t tl_pwrmgr_o,
  40:   input  tlul_pkg::tl_d2h_t tl_pwrmgr_i,
  41:   output tlul_pkg::tl_h2d_t tl_rstmgr_o,
  42:   input  tlul_pkg::tl_d2h_t tl_rstmgr_i,
  43:   output tlul_pkg::tl_h2d_t tl_clkmgr_o,
  44:   input  tlul_pkg::tl_d2h_t tl_clkmgr_i,
  45: 
  46:   input scanmode_i
  47: );
  48: 
  49:   import tlul_pkg::*;
  50:   import tl_peri_pkg::*;
  51: 
  52:   // scanmode_i is currently not used, but provisioned for future use
  53:   // this assignment prevents lint warnings
  54:   logic unused_scanmode;
  55:   assign unused_scanmode = scanmode_i;
  56: 
  57:   tl_h2d_t tl_s1n_9_us_h2d ;
  58:   tl_d2h_t tl_s1n_9_us_d2h ;
  59: 
  60: 
  61:   tl_h2d_t tl_s1n_9_ds_h2d [8];
  62:   tl_d2h_t tl_s1n_9_ds_d2h [8];
  63: 
  64:   // Create steering signal
  65:   logic [3:0] dev_sel_s1n_9;
  66: 
  67: 
  68: 
  69:   assign tl_uart_o = tl_s1n_9_ds_h2d[0];
  70:   assign tl_s1n_9_ds_d2h[0] = tl_uart_i;
  71: 
  72:   assign tl_gpio_o = tl_s1n_9_ds_h2d[1];
  73:   assign tl_s1n_9_ds_d2h[1] = tl_gpio_i;
  74: 
  75:   assign tl_spi_device_o = tl_s1n_9_ds_h2d[2];
  76:   assign tl_s1n_9_ds_d2h[2] = tl_spi_device_i;
  77: 
  78:   assign tl_rv_timer_o = tl_s1n_9_ds_h2d[3];
  79:   assign tl_s1n_9_ds_d2h[3] = tl_rv_timer_i;
  80: 
  81:   assign tl_usbdev_o = tl_s1n_9_ds_h2d[4];
  82:   assign tl_s1n_9_ds_d2h[4] = tl_usbdev_i;
  83: 
  84:   assign tl_pwrmgr_o = tl_s1n_9_ds_h2d[5];
  85:   assign tl_s1n_9_ds_d2h[5] = tl_pwrmgr_i;
  86: 
  87:   assign tl_rstmgr_o = tl_s1n_9_ds_h2d[6];
  88:   assign tl_s1n_9_ds_d2h[6] = tl_rstmgr_i;
  89: 
  90:   assign tl_clkmgr_o = tl_s1n_9_ds_h2d[7];
  91:   assign tl_s1n_9_ds_d2h[7] = tl_clkmgr_i;
  92: 
  93:   assign tl_s1n_9_us_h2d = tl_main_i;
  94:   assign tl_main_o = tl_s1n_9_us_d2h;
  95: 
  96:   always_comb begin
  97:     // default steering to generate error response if address is not within the range
  98:     dev_sel_s1n_9 = 4'd8;
  99:     if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
 100:       dev_sel_s1n_9 = 4'd0;
 101: 
 102:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
 103:       dev_sel_s1n_9 = 4'd1;
 104: 
 105:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
 106:       dev_sel_s1n_9 = 4'd2;
 107: 
 108:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
 109:       dev_sel_s1n_9 = 4'd3;
 110: 
 111:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_USBDEV)) == ADDR_SPACE_USBDEV) begin
 112:       dev_sel_s1n_9 = 4'd4;
 113: 
 114:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_PWRMGR)) == ADDR_SPACE_PWRMGR) begin
 115:       dev_sel_s1n_9 = 4'd5;
 116: 
 117:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_RSTMGR)) == ADDR_SPACE_RSTMGR) begin
 118:       dev_sel_s1n_9 = 4'd6;
 119: 
 120:     end else if ((tl_s1n_9_us_h2d.a_address & ~(ADDR_MASK_CLKMGR)) == ADDR_SPACE_CLKMGR) begin
 121:       dev_sel_s1n_9 = 4'd7;
 122: end
 123:   end
 124: 
 125: 
 126:   // Instantiation phase
 127:   tlul_socket_1n #(
 128:     .HReqDepth (4'h0),
 129:     .HRspDepth (4'h0),
 130:     .DReqDepth ({8{4'h0}}),
 131:     .DRspDepth ({8{4'h0}}),
 132:     .N         (8)
 133:   ) u_s1n_9 (
 134:     .clk_i        (clk_peri_i),
 135:     .rst_ni       (rst_peri_ni),
 136:     .tl_h_i       (tl_s1n_9_us_h2d),
 137:     .tl_h_o       (tl_s1n_9_us_d2h),
 138:     .tl_d_o       (tl_s1n_9_ds_h2d),
 139:     .tl_d_i       (tl_s1n_9_ds_d2h),
 140:     .dev_select   (dev_sel_s1n_9)
 141:   );
 142: 
 143: endmodule
 144: