../src/lowrisc_ip_pwrmgr_pkg_0.1/rtl/pwrmgr_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Power Manager Package
6: //
7:
8: package pwrmgr_pkg;
9:
10: // global constant
11: parameter ALWAYS_ON_DOMAIN = 0;
12:
13: // variables referenced by other modules / packages
14: parameter HwRstReqs = 2; // this needs to be a topgen populated number, or from topcfg?
15: parameter PowerDomains = 2; // this maybe needs to be a topgen populated number, or from topcfg?
16:
17: // variables referenced only by pwrmgr
18: localparam WakeUpPeris = 16; // this needs to be a topgen populated number, or from topcfg?
19: localparam TotalWakeWidth = WakeUpPeris + 2; // Abort and fall through are added
20:
21:
22: // pwrmgr to ast
23: typedef struct packed {
24: logic main_pd_n;
25: logic pwr_clamp;
26: logic slow_clk_en;
27: logic core_clk_en;
28: logic io_clk_en;
29: } pwr_ast_req_t;
30:
31: typedef struct packed {
32: logic [1:0] slow_clk_val;
33: logic [1:0] core_clk_val;
34: logic [1:0] io_clk_val;
35: logic main_pok;
36: } pwr_ast_rsp_t;
37:
38: // default value of pwr_ast_rsp (for dangling ports)
39: parameter pwr_ast_rsp_t PWR_AST_RSP_DEFAULT = '{
40: slow_clk_val: 2'b10,
41: core_clk_val: 2'b10,
42: io_clk_val: 2'b10,
43: main_pok: 1'b1
44: };
45:
46: parameter pwr_ast_rsp_t PWR_AST_RSP_SYNC_DEFAULT = '{
47: slow_clk_val: 2'b01,
48: core_clk_val: 2'b01,
49: io_clk_val: 2'b10,
50: main_pok: 1'b0
51: };
52:
53: // reasons for pwrmgr reset reset
54: typedef enum logic [1:0] {
55: ResetNone = 0, // there is no reset
56: LowPwrEntry = 1, // reset is caused by low power entry
57: HwReq = 2, // reset is caused by peripheral reset requests
58: ResetUndefined = 3 // this should never happen outside of POR
59: } reset_cause_e;
60:
61: // pwrmgr to rstmgr
62: typedef struct packed {
63: logic [PowerDomains-1:0] rst_lc_req;
64: logic [PowerDomains-1:0] rst_sys_req;
65: reset_cause_e reset_cause;
66: } pwr_rst_req_t;
67:
68: // rstmgr to pwrmgr
69: typedef struct packed {
70: logic [PowerDomains-1:0] rst_lc_src_n;
71: logic [PowerDomains-1:0] rst_sys_src_n;
72: } pwr_rst_rsp_t;
73:
74: // default value (for dangling ports)
75: parameter pwr_rst_rsp_t PWR_RST_RSP_DEFAULT = '{
76: rst_lc_src_n: {PowerDomains{1'b1}},
77: rst_sys_src_n: {PowerDomains{1'b1}}
78: };
79:
80: // pwrmgr to clkmgr
81: typedef struct packed {
82: logic ip_clk_en;
83: } pwr_clk_req_t;
84:
85: // clkmgr to powrmgr
86: typedef struct packed {
87: logic roots_en;
88: } pwr_clk_rsp_t;
89:
90: // pwrmgr to otp
91: typedef struct packed {
92: logic otp_init;
93: } pwr_otp_req_t;
94:
95: // otp to pwrmgr
96: typedef struct packed {
97: logic otp_done;
98: logic otp_idle;
99: } pwr_otp_rsp_t;
100:
101: // default value (for dangling ports)
102: parameter pwr_otp_rsp_t PWR_OTP_RSP_DEFAULT = '{
103: otp_done: 1'b1,
104: otp_idle: 1'b1
105: };
106:
107: // pwrmgr to lifecycle
108: typedef struct packed {
109: logic lc_init;
110: } pwr_lc_req_t;
111:
112: // lifecycle to pwrmgr
113: typedef struct packed {
114: logic lc_done;
115: logic lc_idle;
116: } pwr_lc_rsp_t;
117:
118: // default value (for dangling ports)
119: parameter pwr_lc_rsp_t PWR_LC_RSP_DEFAULT = '{
120: lc_done: 1'b1,
121: lc_idle: 1'b1
122: };
123:
124: // flash to pwrmgr
125: typedef struct packed {
126: logic flash_idle;
127: } pwr_flash_t;
128:
129: // default value (for dangling ports)
130: parameter pwr_flash_t PWR_FLASH_DEFAULT = '{
131: flash_idle: 1'b1
132: };
133:
134: // processor to pwrmgr
135: typedef struct packed {
136: logic core_sleeping;
137: } pwr_cpu_t;
138:
139: // default value (for dangling ports)
140: parameter pwr_cpu_t PWR_CPU_DEFAULT = '{
141: core_sleeping: 1'b0
142: };
143:
144: // peripherals to pwrmgr
145: // TODO, switch this to two logic arrays once the option to support
146: // logic during intermodule.py is in.
147: // Structs are used for now since these happen to support dangling port
148: // defaults.
149: typedef struct packed {
150: logic [WakeUpPeris-1:0] wakeups;
151: logic [HwRstReqs-1:0] rstreqs;
152: } pwr_peri_t;
153:
154: // default value (for dangling ports)
155: parameter pwr_peri_t PWR_PERI_DEFAULT = '{
156: wakeups: WakeUpPeris'(1'b1),
157: rstreqs: '0
158: };
159:
160: // power-up causes
161: typedef enum logic [1:0] {
162: Por = 2'h0,
163: Wake = 2'h1,
164: Reset = 2'h2
165: } pwrup_cause_e;
166:
167: // low power hints
168: typedef enum logic {
169: None = 1'b0,
170: LowPower = 1'b1
171: } low_power_hint_e;
172:
173:
174: endpackage // pwrmgr_pkg
175: