../src/lowrisc_top_earlgrey_xbar_main_0.1/xbar_main.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // xbar_main module generated by `tlgen.py` tool
   6: // all reset signals should be generated from one reset signal to not make any deadlock
   7: //
   8: // Interconnect
   9: // corei
  10: //   -> s1n_16
  11: //     -> sm1_17
  12: //       -> rom
  13: //     -> sm1_18
  14: //       -> debug_mem
  15: //     -> sm1_19
  16: //       -> ram_main
  17: //     -> sm1_20
  18: //       -> eflash
  19: // cored
  20: //   -> s1n_21
  21: //     -> sm1_17
  22: //       -> rom
  23: //     -> sm1_18
  24: //       -> debug_mem
  25: //     -> sm1_19
  26: //       -> ram_main
  27: //     -> sm1_20
  28: //       -> eflash
  29: //     -> sm1_23
  30: //       -> asf_22
  31: //         -> peri
  32: //     -> sm1_24
  33: //       -> flash_ctrl
  34: //     -> sm1_25
  35: //       -> aes
  36: //     -> sm1_26
  37: //       -> hmac
  38: //     -> sm1_27
  39: //       -> rv_plic
  40: //     -> sm1_28
  41: //       -> pinmux
  42: //     -> sm1_29
  43: //       -> padctrl
  44: //     -> sm1_30
  45: //       -> alert_handler
  46: //     -> sm1_31
  47: //       -> nmi_gen
  48: // dm_sba
  49: //   -> s1n_32
  50: //     -> sm1_17
  51: //       -> rom
  52: //     -> sm1_19
  53: //       -> ram_main
  54: //     -> sm1_20
  55: //       -> eflash
  56: //     -> sm1_23
  57: //       -> asf_22
  58: //         -> peri
  59: //     -> sm1_24
  60: //       -> flash_ctrl
  61: //     -> sm1_25
  62: //       -> aes
  63: //     -> sm1_26
  64: //       -> hmac
  65: //     -> sm1_27
  66: //       -> rv_plic
  67: //     -> sm1_28
  68: //       -> pinmux
  69: //     -> sm1_29
  70: //       -> padctrl
  71: //     -> sm1_30
  72: //       -> alert_handler
  73: //     -> sm1_31
  74: //       -> nmi_gen
  75: 
  76: module xbar_main (
  77:   input clk_main_i,
  78:   input clk_fixed_i,
  79:   input rst_main_ni,
  80:   input rst_fixed_ni,
  81: 
  82:   // Host interfaces
  83:   input  tlul_pkg::tl_h2d_t tl_corei_i,
  84:   output tlul_pkg::tl_d2h_t tl_corei_o,
  85:   input  tlul_pkg::tl_h2d_t tl_cored_i,
  86:   output tlul_pkg::tl_d2h_t tl_cored_o,
  87:   input  tlul_pkg::tl_h2d_t tl_dm_sba_i,
  88:   output tlul_pkg::tl_d2h_t tl_dm_sba_o,
  89: 
  90:   // Device interfaces
  91:   output tlul_pkg::tl_h2d_t tl_rom_o,
  92:   input  tlul_pkg::tl_d2h_t tl_rom_i,
  93:   output tlul_pkg::tl_h2d_t tl_debug_mem_o,
  94:   input  tlul_pkg::tl_d2h_t tl_debug_mem_i,
  95:   output tlul_pkg::tl_h2d_t tl_ram_main_o,
  96:   input  tlul_pkg::tl_d2h_t tl_ram_main_i,
  97:   output tlul_pkg::tl_h2d_t tl_eflash_o,
  98:   input  tlul_pkg::tl_d2h_t tl_eflash_i,
  99:   output tlul_pkg::tl_h2d_t tl_peri_o,
 100:   input  tlul_pkg::tl_d2h_t tl_peri_i,
 101:   output tlul_pkg::tl_h2d_t tl_flash_ctrl_o,
 102:   input  tlul_pkg::tl_d2h_t tl_flash_ctrl_i,
 103:   output tlul_pkg::tl_h2d_t tl_hmac_o,
 104:   input  tlul_pkg::tl_d2h_t tl_hmac_i,
 105:   output tlul_pkg::tl_h2d_t tl_aes_o,
 106:   input  tlul_pkg::tl_d2h_t tl_aes_i,
 107:   output tlul_pkg::tl_h2d_t tl_rv_plic_o,
 108:   input  tlul_pkg::tl_d2h_t tl_rv_plic_i,
 109:   output tlul_pkg::tl_h2d_t tl_pinmux_o,
 110:   input  tlul_pkg::tl_d2h_t tl_pinmux_i,
 111:   output tlul_pkg::tl_h2d_t tl_padctrl_o,
 112:   input  tlul_pkg::tl_d2h_t tl_padctrl_i,
 113:   output tlul_pkg::tl_h2d_t tl_alert_handler_o,
 114:   input  tlul_pkg::tl_d2h_t tl_alert_handler_i,
 115:   output tlul_pkg::tl_h2d_t tl_nmi_gen_o,
 116:   input  tlul_pkg::tl_d2h_t tl_nmi_gen_i,
 117: 
 118:   input scanmode_i
 119: );
 120: 
 121:   import tlul_pkg::*;
 122:   import tl_main_pkg::*;
 123: 
 124:   // scanmode_i is currently not used, but provisioned for future use
 125:   // this assignment prevents lint warnings
 126:   logic unused_scanmode;
 127:   assign unused_scanmode = scanmode_i;
 128: 
 129:   tl_h2d_t tl_s1n_16_us_h2d ;
 130:   tl_d2h_t tl_s1n_16_us_d2h ;
 131: 
 132: 
 133:   tl_h2d_t tl_s1n_16_ds_h2d [4];
 134:   tl_d2h_t tl_s1n_16_ds_d2h [4];
 135: 
 136:   // Create steering signal
 137:   logic [2:0] dev_sel_s1n_16;
 138: 
 139: 
 140:   tl_h2d_t tl_sm1_17_us_h2d [3];
 141:   tl_d2h_t tl_sm1_17_us_d2h [3];
 142: 
 143:   tl_h2d_t tl_sm1_17_ds_h2d ;
 144:   tl_d2h_t tl_sm1_17_ds_d2h ;
 145: 
 146: 
 147:   tl_h2d_t tl_sm1_18_us_h2d [2];
 148:   tl_d2h_t tl_sm1_18_us_d2h [2];
 149: 
 150:   tl_h2d_t tl_sm1_18_ds_h2d ;
 151:   tl_d2h_t tl_sm1_18_ds_d2h ;
 152: 
 153: 
 154:   tl_h2d_t tl_sm1_19_us_h2d [3];
 155:   tl_d2h_t tl_sm1_19_us_d2h [3];
 156: 
 157:   tl_h2d_t tl_sm1_19_ds_h2d ;
 158:   tl_d2h_t tl_sm1_19_ds_d2h ;
 159: 
 160: 
 161:   tl_h2d_t tl_sm1_20_us_h2d [3];
 162:   tl_d2h_t tl_sm1_20_us_d2h [3];
 163: 
 164:   tl_h2d_t tl_sm1_20_ds_h2d ;
 165:   tl_d2h_t tl_sm1_20_ds_d2h ;
 166: 
 167:   tl_h2d_t tl_s1n_21_us_h2d ;
 168:   tl_d2h_t tl_s1n_21_us_d2h ;
 169: 
 170: 
 171:   tl_h2d_t tl_s1n_21_ds_h2d [13];
 172:   tl_d2h_t tl_s1n_21_ds_d2h [13];
 173: 
 174:   // Create steering signal
 175:   logic [3:0] dev_sel_s1n_21;
 176: 
 177:   tl_h2d_t tl_asf_22_us_h2d ;
 178:   tl_d2h_t tl_asf_22_us_d2h ;
 179:   tl_h2d_t tl_asf_22_ds_h2d ;
 180:   tl_d2h_t tl_asf_22_ds_d2h ;
 181: 
 182: 
 183:   tl_h2d_t tl_sm1_23_us_h2d [2];
 184:   tl_d2h_t tl_sm1_23_us_d2h [2];
 185: 
 186:   tl_h2d_t tl_sm1_23_ds_h2d ;
 187:   tl_d2h_t tl_sm1_23_ds_d2h ;
 188: 
 189: 
 190:   tl_h2d_t tl_sm1_24_us_h2d [2];
 191:   tl_d2h_t tl_sm1_24_us_d2h [2];
 192: 
 193:   tl_h2d_t tl_sm1_24_ds_h2d ;
 194:   tl_d2h_t tl_sm1_24_ds_d2h ;
 195: 
 196: 
 197:   tl_h2d_t tl_sm1_25_us_h2d [2];
 198:   tl_d2h_t tl_sm1_25_us_d2h [2];
 199: 
 200:   tl_h2d_t tl_sm1_25_ds_h2d ;
 201:   tl_d2h_t tl_sm1_25_ds_d2h ;
 202: 
 203: 
 204:   tl_h2d_t tl_sm1_26_us_h2d [2];
 205:   tl_d2h_t tl_sm1_26_us_d2h [2];
 206: 
 207:   tl_h2d_t tl_sm1_26_ds_h2d ;
 208:   tl_d2h_t tl_sm1_26_ds_d2h ;
 209: 
 210: 
 211:   tl_h2d_t tl_sm1_27_us_h2d [2];
 212:   tl_d2h_t tl_sm1_27_us_d2h [2];
 213: 
 214:   tl_h2d_t tl_sm1_27_ds_h2d ;
 215:   tl_d2h_t tl_sm1_27_ds_d2h ;
 216: 
 217: 
 218:   tl_h2d_t tl_sm1_28_us_h2d [2];
 219:   tl_d2h_t tl_sm1_28_us_d2h [2];
 220: 
 221:   tl_h2d_t tl_sm1_28_ds_h2d ;
 222:   tl_d2h_t tl_sm1_28_ds_d2h ;
 223: 
 224: 
 225:   tl_h2d_t tl_sm1_29_us_h2d [2];
 226:   tl_d2h_t tl_sm1_29_us_d2h [2];
 227: 
 228:   tl_h2d_t tl_sm1_29_ds_h2d ;
 229:   tl_d2h_t tl_sm1_29_ds_d2h ;
 230: 
 231: 
 232:   tl_h2d_t tl_sm1_30_us_h2d [2];
 233:   tl_d2h_t tl_sm1_30_us_d2h [2];
 234: 
 235:   tl_h2d_t tl_sm1_30_ds_h2d ;
 236:   tl_d2h_t tl_sm1_30_ds_d2h ;
 237: 
 238: 
 239:   tl_h2d_t tl_sm1_31_us_h2d [2];
 240:   tl_d2h_t tl_sm1_31_us_d2h [2];
 241: 
 242:   tl_h2d_t tl_sm1_31_ds_h2d ;
 243:   tl_d2h_t tl_sm1_31_ds_d2h ;
 244: 
 245:   tl_h2d_t tl_s1n_32_us_h2d ;
 246:   tl_d2h_t tl_s1n_32_us_d2h ;
 247: 
 248: 
 249:   tl_h2d_t tl_s1n_32_ds_h2d [12];
 250:   tl_d2h_t tl_s1n_32_ds_d2h [12];
 251: 
 252:   // Create steering signal
 253:   logic [3:0] dev_sel_s1n_32;
 254: 
 255: 
 256: 
 257:   assign tl_sm1_17_us_h2d[0] = tl_s1n_16_ds_h2d[0];
 258:   assign tl_s1n_16_ds_d2h[0] = tl_sm1_17_us_d2h[0];
 259: 
 260:   assign tl_sm1_18_us_h2d[0] = tl_s1n_16_ds_h2d[1];
 261:   assign tl_s1n_16_ds_d2h[1] = tl_sm1_18_us_d2h[0];
 262: 
 263:   assign tl_sm1_19_us_h2d[0] = tl_s1n_16_ds_h2d[2];
 264:   assign tl_s1n_16_ds_d2h[2] = tl_sm1_19_us_d2h[0];
 265: 
 266:   assign tl_sm1_20_us_h2d[0] = tl_s1n_16_ds_h2d[3];
 267:   assign tl_s1n_16_ds_d2h[3] = tl_sm1_20_us_d2h[0];
 268: 
 269:   assign tl_sm1_17_us_h2d[1] = tl_s1n_21_ds_h2d[0];
 270:   assign tl_s1n_21_ds_d2h[0] = tl_sm1_17_us_d2h[1];
 271: 
 272:   assign tl_sm1_18_us_h2d[1] = tl_s1n_21_ds_h2d[1];
 273:   assign tl_s1n_21_ds_d2h[1] = tl_sm1_18_us_d2h[1];
 274: 
 275:   assign tl_sm1_19_us_h2d[1] = tl_s1n_21_ds_h2d[2];
 276:   assign tl_s1n_21_ds_d2h[2] = tl_sm1_19_us_d2h[1];
 277: 
 278:   assign tl_sm1_20_us_h2d[1] = tl_s1n_21_ds_h2d[3];
 279:   assign tl_s1n_21_ds_d2h[3] = tl_sm1_20_us_d2h[1];
 280: 
 281:   assign tl_sm1_23_us_h2d[0] = tl_s1n_21_ds_h2d[4];
 282:   assign tl_s1n_21_ds_d2h[4] = tl_sm1_23_us_d2h[0];
 283: 
 284:   assign tl_sm1_24_us_h2d[0] = tl_s1n_21_ds_h2d[5];
 285:   assign tl_s1n_21_ds_d2h[5] = tl_sm1_24_us_d2h[0];
 286: 
 287:   assign tl_sm1_25_us_h2d[0] = tl_s1n_21_ds_h2d[6];
 288:   assign tl_s1n_21_ds_d2h[6] = tl_sm1_25_us_d2h[0];
 289: 
 290:   assign tl_sm1_26_us_h2d[0] = tl_s1n_21_ds_h2d[7];
 291:   assign tl_s1n_21_ds_d2h[7] = tl_sm1_26_us_d2h[0];
 292: 
 293:   assign tl_sm1_27_us_h2d[0] = tl_s1n_21_ds_h2d[8];
 294:   assign tl_s1n_21_ds_d2h[8] = tl_sm1_27_us_d2h[0];
 295: 
 296:   assign tl_sm1_28_us_h2d[0] = tl_s1n_21_ds_h2d[9];
 297:   assign tl_s1n_21_ds_d2h[9] = tl_sm1_28_us_d2h[0];
 298: 
 299:   assign tl_sm1_29_us_h2d[0] = tl_s1n_21_ds_h2d[10];
 300:   assign tl_s1n_21_ds_d2h[10] = tl_sm1_29_us_d2h[0];
 301: 
 302:   assign tl_sm1_30_us_h2d[0] = tl_s1n_21_ds_h2d[11];
 303:   assign tl_s1n_21_ds_d2h[11] = tl_sm1_30_us_d2h[0];
 304: 
 305:   assign tl_sm1_31_us_h2d[0] = tl_s1n_21_ds_h2d[12];
 306:   assign tl_s1n_21_ds_d2h[12] = tl_sm1_31_us_d2h[0];
 307: 
 308:   assign tl_sm1_17_us_h2d[2] = tl_s1n_32_ds_h2d[0];
 309:   assign tl_s1n_32_ds_d2h[0] = tl_sm1_17_us_d2h[2];
 310: 
 311:   assign tl_sm1_19_us_h2d[2] = tl_s1n_32_ds_h2d[1];
 312:   assign tl_s1n_32_ds_d2h[1] = tl_sm1_19_us_d2h[2];
 313: 
 314:   assign tl_sm1_20_us_h2d[2] = tl_s1n_32_ds_h2d[2];
 315:   assign tl_s1n_32_ds_d2h[2] = tl_sm1_20_us_d2h[2];
 316: 
 317:   assign tl_sm1_23_us_h2d[1] = tl_s1n_32_ds_h2d[3];
 318:   assign tl_s1n_32_ds_d2h[3] = tl_sm1_23_us_d2h[1];
 319: 
 320:   assign tl_sm1_24_us_h2d[1] = tl_s1n_32_ds_h2d[4];
 321:   assign tl_s1n_32_ds_d2h[4] = tl_sm1_24_us_d2h[1];
 322: 
 323:   assign tl_sm1_25_us_h2d[1] = tl_s1n_32_ds_h2d[5];
 324:   assign tl_s1n_32_ds_d2h[5] = tl_sm1_25_us_d2h[1];
 325: 
 326:   assign tl_sm1_26_us_h2d[1] = tl_s1n_32_ds_h2d[6];
 327:   assign tl_s1n_32_ds_d2h[6] = tl_sm1_26_us_d2h[1];
 328: 
 329:   assign tl_sm1_27_us_h2d[1] = tl_s1n_32_ds_h2d[7];
 330:   assign tl_s1n_32_ds_d2h[7] = tl_sm1_27_us_d2h[1];
 331: 
 332:   assign tl_sm1_28_us_h2d[1] = tl_s1n_32_ds_h2d[8];
 333:   assign tl_s1n_32_ds_d2h[8] = tl_sm1_28_us_d2h[1];
 334: 
 335:   assign tl_sm1_29_us_h2d[1] = tl_s1n_32_ds_h2d[9];
 336:   assign tl_s1n_32_ds_d2h[9] = tl_sm1_29_us_d2h[1];
 337: 
 338:   assign tl_sm1_30_us_h2d[1] = tl_s1n_32_ds_h2d[10];
 339:   assign tl_s1n_32_ds_d2h[10] = tl_sm1_30_us_d2h[1];
 340: 
 341:   assign tl_sm1_31_us_h2d[1] = tl_s1n_32_ds_h2d[11];
 342:   assign tl_s1n_32_ds_d2h[11] = tl_sm1_31_us_d2h[1];
 343: 
 344:   assign tl_s1n_16_us_h2d = tl_corei_i;
 345:   assign tl_corei_o = tl_s1n_16_us_d2h;
 346: 
 347:   assign tl_rom_o = tl_sm1_17_ds_h2d;
 348:   assign tl_sm1_17_ds_d2h = tl_rom_i;
 349: 
 350:   assign tl_debug_mem_o = tl_sm1_18_ds_h2d;
 351:   assign tl_sm1_18_ds_d2h = tl_debug_mem_i;
 352: 
 353:   assign tl_ram_main_o = tl_sm1_19_ds_h2d;
 354:   assign tl_sm1_19_ds_d2h = tl_ram_main_i;
 355: 
 356:   assign tl_eflash_o = tl_sm1_20_ds_h2d;
 357:   assign tl_sm1_20_ds_d2h = tl_eflash_i;
 358: 
 359:   assign tl_s1n_21_us_h2d = tl_cored_i;
 360:   assign tl_cored_o = tl_s1n_21_us_d2h;
 361: 
 362:   assign tl_peri_o = tl_asf_22_ds_h2d;
 363:   assign tl_asf_22_ds_d2h = tl_peri_i;
 364: 
 365:   assign tl_asf_22_us_h2d = tl_sm1_23_ds_h2d;
 366:   assign tl_sm1_23_ds_d2h = tl_asf_22_us_d2h;
 367: 
 368:   assign tl_flash_ctrl_o = tl_sm1_24_ds_h2d;
 369:   assign tl_sm1_24_ds_d2h = tl_flash_ctrl_i;
 370: 
 371:   assign tl_aes_o = tl_sm1_25_ds_h2d;
 372:   assign tl_sm1_25_ds_d2h = tl_aes_i;
 373: 
 374:   assign tl_hmac_o = tl_sm1_26_ds_h2d;
 375:   assign tl_sm1_26_ds_d2h = tl_hmac_i;
 376: 
 377:   assign tl_rv_plic_o = tl_sm1_27_ds_h2d;
 378:   assign tl_sm1_27_ds_d2h = tl_rv_plic_i;
 379: 
 380:   assign tl_pinmux_o = tl_sm1_28_ds_h2d;
 381:   assign tl_sm1_28_ds_d2h = tl_pinmux_i;
 382: 
 383:   assign tl_padctrl_o = tl_sm1_29_ds_h2d;
 384:   assign tl_sm1_29_ds_d2h = tl_padctrl_i;
 385: 
 386:   assign tl_alert_handler_o = tl_sm1_30_ds_h2d;
 387:   assign tl_sm1_30_ds_d2h = tl_alert_handler_i;
 388: 
 389:   assign tl_nmi_gen_o = tl_sm1_31_ds_h2d;
 390:   assign tl_sm1_31_ds_d2h = tl_nmi_gen_i;
 391: 
 392:   assign tl_s1n_32_us_h2d = tl_dm_sba_i;
 393:   assign tl_dm_sba_o = tl_s1n_32_us_d2h;
 394: 
 395:   always_comb begin
 396:     // default steering to generate error response if address is not within the range
 397:     dev_sel_s1n_16 = 3'd4;
 398:     if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
 399:       dev_sel_s1n_16 = 3'd0;
 400: 
 401:     end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
 402:       dev_sel_s1n_16 = 3'd1;
 403: 
 404:     end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
 405:       dev_sel_s1n_16 = 3'd2;
 406: 
 407:     end else if ((tl_s1n_16_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
 408:       dev_sel_s1n_16 = 3'd3;
 409: end
 410:   end
 411: 
 412:   always_comb begin
 413:     // default steering to generate error response if address is not within the range
 414:     dev_sel_s1n_21 = 4'd13;
 415:     if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
 416:       dev_sel_s1n_21 = 4'd0;
 417: 
 418:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
 419:       dev_sel_s1n_21 = 4'd1;
 420: 
 421:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
 422:       dev_sel_s1n_21 = 4'd2;
 423: 
 424:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
 425:       dev_sel_s1n_21 = 4'd3;
 426: 
 427:     end else if (
 428:       ((tl_s1n_21_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
 429:        (tl_s1n_21_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
 430:       ((tl_s1n_21_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
 431:        (tl_s1n_21_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
 432:       ((tl_s1n_21_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
 433:        (tl_s1n_21_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
 434:       ((tl_s1n_21_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
 435:        (tl_s1n_21_us_h2d.a_address >= ADDR_SPACE_PERI[3]))
 436:     ) begin
 437:       dev_sel_s1n_21 = 4'd4;
 438: 
 439:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
 440:       dev_sel_s1n_21 = 4'd5;
 441: 
 442:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
 443:       dev_sel_s1n_21 = 4'd6;
 444: 
 445:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
 446:       dev_sel_s1n_21 = 4'd7;
 447: 
 448:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
 449:       dev_sel_s1n_21 = 4'd8;
 450: 
 451:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
 452:       dev_sel_s1n_21 = 4'd9;
 453: 
 454:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
 455:       dev_sel_s1n_21 = 4'd10;
 456: 
 457:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
 458:       dev_sel_s1n_21 = 4'd11;
 459: 
 460:     end else if ((tl_s1n_21_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
 461:       dev_sel_s1n_21 = 4'd12;
 462: end
 463:   end
 464: 
 465:   always_comb begin
 466:     // default steering to generate error response if address is not within the range
 467:     dev_sel_s1n_32 = 4'd12;
 468:     if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
 469:       dev_sel_s1n_32 = 4'd0;
 470: 
 471:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
 472:       dev_sel_s1n_32 = 4'd1;
 473: 
 474:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
 475:       dev_sel_s1n_32 = 4'd2;
 476: 
 477:     end else if (
 478:       ((tl_s1n_32_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
 479:        (tl_s1n_32_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
 480:       ((tl_s1n_32_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
 481:        (tl_s1n_32_us_h2d.a_address >= ADDR_SPACE_PERI[1])) ||
 482:       ((tl_s1n_32_us_h2d.a_address <= (ADDR_MASK_PERI[2] + ADDR_SPACE_PERI[2])) &&
 483:        (tl_s1n_32_us_h2d.a_address >= ADDR_SPACE_PERI[2])) ||
 484:       ((tl_s1n_32_us_h2d.a_address <= (ADDR_MASK_PERI[3] + ADDR_SPACE_PERI[3])) &&
 485:        (tl_s1n_32_us_h2d.a_address >= ADDR_SPACE_PERI[3]))
 486:     ) begin
 487:       dev_sel_s1n_32 = 4'd3;
 488: 
 489:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
 490:       dev_sel_s1n_32 = 4'd4;
 491: 
 492:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
 493:       dev_sel_s1n_32 = 4'd5;
 494: 
 495:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
 496:       dev_sel_s1n_32 = 4'd6;
 497: 
 498:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
 499:       dev_sel_s1n_32 = 4'd7;
 500: 
 501:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
 502:       dev_sel_s1n_32 = 4'd8;
 503: 
 504:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_PADCTRL)) == ADDR_SPACE_PADCTRL) begin
 505:       dev_sel_s1n_32 = 4'd9;
 506: 
 507:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
 508:       dev_sel_s1n_32 = 4'd10;
 509: 
 510:     end else if ((tl_s1n_32_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
 511:       dev_sel_s1n_32 = 4'd11;
 512: end
 513:   end
 514: 
 515: 
 516:   // Instantiation phase
 517:   tlul_socket_1n #(
 518:     .HReqDepth (4'h0),
 519:     .HRspDepth (4'h0),
 520:     .DReqDepth ({4{4'h0}}),
 521:     .DRspDepth ({4{4'h0}}),
 522:     .N         (4)
 523:   ) u_s1n_16 (
 524:     .clk_i        (clk_main_i),
 525:     .rst_ni       (rst_main_ni),
 526:     .tl_h_i       (tl_s1n_16_us_h2d),
 527:     .tl_h_o       (tl_s1n_16_us_d2h),
 528:     .tl_d_o       (tl_s1n_16_ds_h2d),
 529:     .tl_d_i       (tl_s1n_16_ds_d2h),
 530:     .dev_select   (dev_sel_s1n_16)
 531:   );
 532:   tlul_socket_m1 #(
 533:     .HReqDepth ({3{4'h0}}),
 534:     .HRspDepth ({3{4'h0}}),
 535:     .DReqDepth (4'h0),
 536:     .DRspDepth (4'h0),
 537:     .M         (3)
 538:   ) u_sm1_17 (
 539:     .clk_i        (clk_main_i),
 540:     .rst_ni       (rst_main_ni),
 541:     .tl_h_i       (tl_sm1_17_us_h2d),
 542:     .tl_h_o       (tl_sm1_17_us_d2h),
 543:     .tl_d_o       (tl_sm1_17_ds_h2d),
 544:     .tl_d_i       (tl_sm1_17_ds_d2h)
 545:   );
 546:   tlul_socket_m1 #(
 547:     .HReqPass  (2'h0),
 548:     .HRspPass  (2'h0),
 549:     .DReqPass  (1'b0),
 550:     .DRspPass  (1'b0),
 551:     .M         (2)
 552:   ) u_sm1_18 (
 553:     .clk_i        (clk_main_i),
 554:     .rst_ni       (rst_main_ni),
 555:     .tl_h_i       (tl_sm1_18_us_h2d),
 556:     .tl_h_o       (tl_sm1_18_us_d2h),
 557:     .tl_d_o       (tl_sm1_18_ds_h2d),
 558:     .tl_d_i       (tl_sm1_18_ds_d2h)
 559:   );
 560:   tlul_socket_m1 #(
 561:     .HReqDepth ({3{4'h0}}),
 562:     .HRspDepth ({3{4'h0}}),
 563:     .DReqDepth (4'h0),
 564:     .DRspDepth (4'h0),
 565:     .M         (3)
 566:   ) u_sm1_19 (
 567:     .clk_i        (clk_main_i),
 568:     .rst_ni       (rst_main_ni),
 569:     .tl_h_i       (tl_sm1_19_us_h2d),
 570:     .tl_h_o       (tl_sm1_19_us_d2h),
 571:     .tl_d_o       (tl_sm1_19_ds_h2d),
 572:     .tl_d_i       (tl_sm1_19_ds_d2h)
 573:   );
 574:   tlul_socket_m1 #(
 575:     .HReqDepth ({3{4'h0}}),
 576:     .HRspDepth ({3{4'h0}}),
 577:     .DReqDepth (4'h0),
 578:     .DRspDepth (4'h0),
 579:     .M         (3)
 580:   ) u_sm1_20 (
 581:     .clk_i        (clk_main_i),
 582:     .rst_ni       (rst_main_ni),
 583:     .tl_h_i       (tl_sm1_20_us_h2d),
 584:     .tl_h_o       (tl_sm1_20_us_d2h),
 585:     .tl_d_o       (tl_sm1_20_ds_h2d),
 586:     .tl_d_i       (tl_sm1_20_ds_d2h)
 587:   );
 588:   tlul_socket_1n #(
 589:     .HReqDepth (4'h0),
 590:     .HRspDepth (4'h0),
 591:     .DReqDepth ({13{4'h0}}),
 592:     .DRspDepth ({13{4'h0}}),
 593:     .N         (13)
 594:   ) u_s1n_21 (
 595:     .clk_i        (clk_main_i),
 596:     .rst_ni       (rst_main_ni),
 597:     .tl_h_i       (tl_s1n_21_us_h2d),
 598:     .tl_h_o       (tl_s1n_21_us_d2h),
 599:     .tl_d_o       (tl_s1n_21_ds_h2d),
 600:     .tl_d_i       (tl_s1n_21_ds_d2h),
 601:     .dev_select   (dev_sel_s1n_21)
 602:   );
 603:   tlul_fifo_async #(
 604:     .ReqDepth        (3),// At least 3 to make async work
 605:     .RspDepth        (3) // At least 3 to make async work
 606:   ) u_asf_22 (
 607:     .clk_h_i      (clk_main_i),
 608:     .rst_h_ni     (rst_main_ni),
 609:     .clk_d_i      (clk_fixed_i),
 610:     .rst_d_ni     (rst_fixed_ni),
 611:     .tl_h_i       (tl_asf_22_us_h2d),
 612:     .tl_h_o       (tl_asf_22_us_d2h),
 613:     .tl_d_o       (tl_asf_22_ds_h2d),
 614:     .tl_d_i       (tl_asf_22_ds_d2h)
 615:   );
 616:   tlul_socket_m1 #(
 617:     .M         (2)
 618:   ) u_sm1_23 (
 619:     .clk_i        (clk_main_i),
 620:     .rst_ni       (rst_main_ni),
 621:     .tl_h_i       (tl_sm1_23_us_h2d),
 622:     .tl_h_o       (tl_sm1_23_us_d2h),
 623:     .tl_d_o       (tl_sm1_23_ds_h2d),
 624:     .tl_d_i       (tl_sm1_23_ds_d2h)
 625:   );
 626:   tlul_socket_m1 #(
 627:     .HReqPass  (2'h0),
 628:     .HRspPass  (2'h0),
 629:     .DReqPass  (1'b0),
 630:     .DRspPass  (1'b0),
 631:     .M         (2)
 632:   ) u_sm1_24 (
 633:     .clk_i        (clk_main_i),
 634:     .rst_ni       (rst_main_ni),
 635:     .tl_h_i       (tl_sm1_24_us_h2d),
 636:     .tl_h_o       (tl_sm1_24_us_d2h),
 637:     .tl_d_o       (tl_sm1_24_ds_h2d),
 638:     .tl_d_i       (tl_sm1_24_ds_d2h)
 639:   );
 640:   tlul_socket_m1 #(
 641:     .HReqPass  (2'h0),
 642:     .HRspPass  (2'h0),
 643:     .DReqPass  (1'b0),
 644:     .DRspPass  (1'b0),
 645:     .M         (2)
 646:   ) u_sm1_25 (
 647:     .clk_i        (clk_main_i),
 648:     .rst_ni       (rst_main_ni),
 649:     .tl_h_i       (tl_sm1_25_us_h2d),
 650:     .tl_h_o       (tl_sm1_25_us_d2h),
 651:     .tl_d_o       (tl_sm1_25_ds_h2d),
 652:     .tl_d_i       (tl_sm1_25_ds_d2h)
 653:   );
 654:   tlul_socket_m1 #(
 655:     .HReqPass  (2'h0),
 656:     .HRspPass  (2'h0),
 657:     .DReqPass  (1'b0),
 658:     .DRspPass  (1'b0),
 659:     .M         (2)
 660:   ) u_sm1_26 (
 661:     .clk_i        (clk_main_i),
 662:     .rst_ni       (rst_main_ni),
 663:     .tl_h_i       (tl_sm1_26_us_h2d),
 664:     .tl_h_o       (tl_sm1_26_us_d2h),
 665:     .tl_d_o       (tl_sm1_26_ds_h2d),
 666:     .tl_d_i       (tl_sm1_26_ds_d2h)
 667:   );
 668:   tlul_socket_m1 #(
 669:     .HReqPass  (2'h0),
 670:     .HRspPass  (2'h0),
 671:     .DReqPass  (1'b0),
 672:     .DRspPass  (1'b0),
 673:     .M         (2)
 674:   ) u_sm1_27 (
 675:     .clk_i        (clk_main_i),
 676:     .rst_ni       (rst_main_ni),
 677:     .tl_h_i       (tl_sm1_27_us_h2d),
 678:     .tl_h_o       (tl_sm1_27_us_d2h),
 679:     .tl_d_o       (tl_sm1_27_ds_h2d),
 680:     .tl_d_i       (tl_sm1_27_ds_d2h)
 681:   );
 682:   tlul_socket_m1 #(
 683:     .HReqPass  (2'h0),
 684:     .HRspPass  (2'h0),
 685:     .DReqPass  (1'b0),
 686:     .DRspPass  (1'b0),
 687:     .M         (2)
 688:   ) u_sm1_28 (
 689:     .clk_i        (clk_main_i),
 690:     .rst_ni       (rst_main_ni),
 691:     .tl_h_i       (tl_sm1_28_us_h2d),
 692:     .tl_h_o       (tl_sm1_28_us_d2h),
 693:     .tl_d_o       (tl_sm1_28_ds_h2d),
 694:     .tl_d_i       (tl_sm1_28_ds_d2h)
 695:   );
 696:   tlul_socket_m1 #(
 697:     .HReqPass  (2'h0),
 698:     .HRspPass  (2'h0),
 699:     .DReqPass  (1'b0),
 700:     .DRspPass  (1'b0),
 701:     .M         (2)
 702:   ) u_sm1_29 (
 703:     .clk_i        (clk_main_i),
 704:     .rst_ni       (rst_main_ni),
 705:     .tl_h_i       (tl_sm1_29_us_h2d),
 706:     .tl_h_o       (tl_sm1_29_us_d2h),
 707:     .tl_d_o       (tl_sm1_29_ds_h2d),
 708:     .tl_d_i       (tl_sm1_29_ds_d2h)
 709:   );
 710:   tlul_socket_m1 #(
 711:     .HReqPass  (2'h0),
 712:     .HRspPass  (2'h0),
 713:     .DReqPass  (1'b0),
 714:     .DRspPass  (1'b0),
 715:     .M         (2)
 716:   ) u_sm1_30 (
 717:     .clk_i        (clk_main_i),
 718:     .rst_ni       (rst_main_ni),
 719:     .tl_h_i       (tl_sm1_30_us_h2d),
 720:     .tl_h_o       (tl_sm1_30_us_d2h),
 721:     .tl_d_o       (tl_sm1_30_ds_h2d),
 722:     .tl_d_i       (tl_sm1_30_ds_d2h)
 723:   );
 724:   tlul_socket_m1 #(
 725:     .HReqPass  (2'h0),
 726:     .HRspPass  (2'h0),
 727:     .DReqPass  (1'b0),
 728:     .DRspPass  (1'b0),
 729:     .M         (2)
 730:   ) u_sm1_31 (
 731:     .clk_i        (clk_main_i),
 732:     .rst_ni       (rst_main_ni),
 733:     .tl_h_i       (tl_sm1_31_us_h2d),
 734:     .tl_h_o       (tl_sm1_31_us_d2h),
 735:     .tl_d_o       (tl_sm1_31_ds_h2d),
 736:     .tl_d_i       (tl_sm1_31_ds_d2h)
 737:   );
 738:   tlul_socket_1n #(
 739:     .HReqPass  (1'b0),
 740:     .HRspPass  (1'b0),
 741:     .DReqPass  (12'h0),
 742:     .DRspPass  (12'h0),
 743:     .N         (12)
 744:   ) u_s1n_32 (
 745:     .clk_i        (clk_main_i),
 746:     .rst_ni       (rst_main_ni),
 747:     .tl_h_i       (tl_s1n_32_us_h2d),
 748:     .tl_h_o       (tl_s1n_32_us_d2h),
 749:     .tl_d_o       (tl_s1n_32_ds_h2d),
 750:     .tl_d_i       (tl_s1n_32_ds_d2h),
 751:     .dev_select   (dev_sel_s1n_32)
 752:   );
 753: 
 754: endmodule
 755: