hw/top_earlgrey/rtl/autogen/top_earlgrey.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4:
5: module top_earlgrey #(
6: parameter bit IbexPipeLine = 0
7: ) (
8: // Clock and Reset
9: input clk_i,
10: input rst_ni,
11:
12: // JTAG interface
13: input jtag_tck_i,
14: input jtag_tms_i,
15: input jtag_trst_ni,
16: input jtag_td_i,
17: output jtag_td_o,
18:
19: // Multiplexed I/O
20: input [31:0] mio_in_i,
21: output logic [31:0] mio_out_o,
22: output logic [31:0] mio_oe_o,
23:
24: // Dedicated I/O
25: input dio_spi_device_sck_i,
26: input dio_spi_device_csb_i,
27: input dio_spi_device_mosi_i,
28: output logic dio_spi_device_miso_o,
29: output logic dio_spi_device_miso_en_o,
30: input dio_uart_rx_i,
31: output logic dio_uart_tx_o,
32: output logic dio_uart_tx_en_o,
33:
34: input scanmode_i // 1 for Scan
35: );
36:
37: // JTAG IDCODE for development versions of this code.
38: // Manufacturers of OpenTitan chips must replace this code with one of their
39: // own IDs.
40: // Field structure as defined in the IEEE 1149.1 (JTAG) specification,
41: // section 12.1.1.
42: localparam JTAG_IDCODE = {
43: 4'h0, // Version
44: 16'h4F54, // Part Number: "OT"
45: 11'h426, // Manufacturer Identity: Google
46: 1'b1 // (fixed)
47: };
48:
49: import tlul_pkg::*;
50: import top_pkg::*;
51: import tl_main_pkg::*;
52: import flash_ctrl_pkg::*;
53:
54: tl_h2d_t tl_corei_h_h2d;
55: tl_d2h_t tl_corei_h_d2h;
56:
57: tl_h2d_t tl_cored_h_h2d;
58: tl_d2h_t tl_cored_h_d2h;
59:
60: tl_h2d_t tl_dm_sba_h_h2d;
61: tl_d2h_t tl_dm_sba_h_d2h;
62:
63: tl_h2d_t tl_debug_mem_d_h2d;
64: tl_d2h_t tl_debug_mem_d_d2h;
65:
66: tl_h2d_t tl_uart_d_h2d;
67: tl_d2h_t tl_uart_d_d2h;
68: tl_h2d_t tl_gpio_d_h2d;
69: tl_d2h_t tl_gpio_d_d2h;
70: tl_h2d_t tl_spi_device_d_h2d;
71: tl_d2h_t tl_spi_device_d_d2h;
72: tl_h2d_t tl_flash_ctrl_d_h2d;
73: tl_d2h_t tl_flash_ctrl_d_d2h;
74: tl_h2d_t tl_rv_timer_d_h2d;
75: tl_d2h_t tl_rv_timer_d_d2h;
76: tl_h2d_t tl_aes_d_h2d;
77: tl_d2h_t tl_aes_d_d2h;
78: tl_h2d_t tl_hmac_d_h2d;
79: tl_d2h_t tl_hmac_d_d2h;
80: tl_h2d_t tl_rv_plic_d_h2d;
81: tl_d2h_t tl_rv_plic_d_d2h;
82: tl_h2d_t tl_pinmux_d_h2d;
83: tl_d2h_t tl_pinmux_d_d2h;
84: tl_h2d_t tl_alert_handler_d_h2d;
85: tl_d2h_t tl_alert_handler_d_d2h;
86: tl_h2d_t tl_nmi_gen_d_h2d;
87: tl_d2h_t tl_nmi_gen_d_d2h;
88:
89: tl_h2d_t tl_rom_d_h2d;
90: tl_d2h_t tl_rom_d_d2h;
91: tl_h2d_t tl_ram_main_d_h2d;
92: tl_d2h_t tl_ram_main_d_d2h;
93: tl_h2d_t tl_eflash_d_h2d;
94: tl_d2h_t tl_eflash_d_d2h;
95:
96: tl_h2d_t tl_main_h_h2d;
97: tl_d2h_t tl_main_h_d2h;
98: tl_h2d_t tl_peri_d_h2d;
99: tl_d2h_t tl_peri_d_d2h;
100:
101: assign tl_main_h_h2d = tl_peri_d_h2d;
102: assign tl_peri_d_d2h = tl_main_h_d2h;
103:
104: //reset wires declaration
105: logic lc_rst_n;
106: logic sys_rst_n;
107: logic sys_fixed_rst_n;
108: logic spi_device_rst_n;
109:
110: //clock wires declaration
111: logic main_clk;
112: logic fixed_clk;
113:
114: // Signals
115: logic [31:0] m2p;
116: logic [31:0] p2m;
117: logic [31:0] p2m_en;
118: // uart
119: logic cio_uart_rx_p2d;
120: logic cio_uart_tx_d2p;
121: logic cio_uart_tx_en_d2p;
122: // gpio
123: logic [31:0] cio_gpio_gpio_p2d;
124: logic [31:0] cio_gpio_gpio_d2p;
125: logic [31:0] cio_gpio_gpio_en_d2p;
126: // spi_device
127: logic cio_spi_device_sck_p2d;
128: logic cio_spi_device_csb_p2d;
129: logic cio_spi_device_mosi_p2d;
130: logic cio_spi_device_miso_d2p;
131: logic cio_spi_device_miso_en_d2p;
132: // flash_ctrl
133: // rv_timer
134: // aes
135: // hmac
136: // rv_plic
137: // pinmux
138: // alert_handler
139: // nmi_gen
140:
141:
142: logic [62:0] intr_vector;
143: // Interrupt source list
144: logic intr_uart_tx_watermark;
145: logic intr_uart_rx_watermark;
146: logic intr_uart_tx_empty;
147: logic intr_uart_rx_overflow;
148: logic intr_uart_rx_frame_err;
149: logic intr_uart_rx_break_err;
150: logic intr_uart_rx_timeout;
151: logic intr_uart_rx_parity_err;
152: logic [31:0] intr_gpio_gpio;
153: logic intr_spi_device_rxf;
154: logic intr_spi_device_rxlvl;
155: logic intr_spi_device_txlvl;
156: logic intr_spi_device_rxerr;
157: logic intr_spi_device_rxoverflow;
158: logic intr_spi_device_txunderflow;
159: logic intr_flash_ctrl_prog_empty;
160: logic intr_flash_ctrl_prog_lvl;
161: logic intr_flash_ctrl_rd_full;
162: logic intr_flash_ctrl_rd_lvl;
163: logic intr_flash_ctrl_op_done;
164: logic intr_flash_ctrl_op_error;
165: logic intr_rv_timer_timer_expired_0_0;
166: logic intr_hmac_hmac_done;
167: logic intr_hmac_fifo_full;
168: logic intr_hmac_hmac_err;
169: logic intr_alert_handler_classa;
170: logic intr_alert_handler_classb;
171: logic intr_alert_handler_classc;
172: logic intr_alert_handler_classd;
173: logic intr_nmi_gen_esc0;
174: logic intr_nmi_gen_esc1;
175: logic intr_nmi_gen_esc2;
176: logic intr_nmi_gen_esc3;
177:
178:
179:
180: logic [0:0] irq_plic;
181: logic [0:0] msip;
182: logic [5:0] irq_id[1];
183: logic [5:0] unused_irq_id[1];
184:
185: // this avoids lint errors
186: assign unused_irq_id = irq_id;
187:
188: // Alert list
189: prim_pkg::alert_tx_t [alert_pkg::NAlerts-1:0] alert_tx;
190: prim_pkg::alert_rx_t [alert_pkg::NAlerts-1:0] alert_rx;
191: // Escalation outputs
192: prim_pkg::esc_tx_t [alert_pkg::N_ESC_SEV-1:0] esc_tx;
193: prim_pkg::esc_rx_t [alert_pkg::N_ESC_SEV-1:0] esc_rx;
194:
195:
196: // clock assignments
197: assign main_clk = clk_i;
198: assign fixed_clk = clk_i;
199:
200: // Non-debug module reset == reset for everything except for the debug module
201: logic ndmreset_req;
202:
203: // root resets
204: // TODO: lc_rst_n is not the true root reset. It will be differentiated once the
205: // the reset controller logic is present
206: assign lc_rst_n = rst_ni;
207: assign sys_rst_n = (scanmode_i) ? lc_rst_n : ~ndmreset_req & lc_rst_n;
208:
209: //non-root reset assignments
210: assign sys_fixed_rst_n = sys_rst_n;
211: assign spi_device_rst_n = sys_rst_n;
212:
213: // debug request from rv_dm to core
214: logic debug_req;
215:
216: // processor core
217: rv_core_ibex #(
218: .PMPEnable (0),
219: .PMPGranularity (0),
220: .PMPNumRegions (4),
221: .MHPMCounterNum (8),
222: .MHPMCounterWidth (40),
223: .RV32E (0),
224: .RV32M (1),
225: .DmHaltAddr (ADDR_SPACE_DEBUG_MEM + dm::HaltAddress),
226: .DmExceptionAddr (ADDR_SPACE_DEBUG_MEM + dm::ExceptionAddress),
227: .PipeLine (IbexPipeLine)
228: ) core (
229: // clock and reset
230: .clk_i (main_clk),
231: .rst_ni (sys_rst_n),
232: .test_en_i (1'b0),
233: // static pinning
234: .hart_id_i (32'b0),
235: .boot_addr_i (ADDR_SPACE_ROM),
236: // TL-UL buses
237: .tl_i_o (tl_corei_h_h2d),
238: .tl_i_i (tl_corei_h_d2h),
239: .tl_d_o (tl_cored_h_h2d),
240: .tl_d_i (tl_cored_h_d2h),
241: // interrupts
242: .irq_software_i (msip),
243: .irq_timer_i (intr_rv_timer_timer_expired_0_0),
244: .irq_external_i (irq_plic),
245: .irq_fast_i (15'b0),// PLIC handles all peripheral interrupts
246: .irq_nm_i (1'b0),// TODO - add and connect alert responder
247: // debug interface
248: .debug_req_i (debug_req),
249: // CPU control signals
250: .fetch_enable_i (1'b1),
251: .core_sleep_o ()
252: );
253:
254: // Debug Module (RISC-V Debug Spec 0.13)
255: //
256:
257: rv_dm #(
258: .NrHarts (1),
259: .IdcodeValue (JTAG_IDCODE)
260: ) u_dm_top (
261: .clk_i (main_clk),
262: .rst_ni (lc_rst_n),
263: .testmode_i (1'b0),
264: .ndmreset_o (ndmreset_req),
265: .dmactive_o (),
266: .debug_req_o (debug_req),
267: .unavailable_i (1'b0),
268:
269: // bus device with debug memory (for execution-based debug)
270: .tl_d_i (tl_debug_mem_d_h2d),
271: .tl_d_o (tl_debug_mem_d_d2h),
272:
273: // bus host (for system bus accesses, SBA)
274: .tl_h_o (tl_dm_sba_h_h2d),
275: .tl_h_i (tl_dm_sba_h_d2h),
276:
277: //JTAG
278: .tck_i (jtag_tck_i),
279: .tms_i (jtag_tms_i),
280: .trst_ni (jtag_trst_ni),
281: .td_i (jtag_td_i),
282: .td_o (jtag_td_o),
283: .tdo_oe_o ( )
284: );
285:
286: // ROM device
287: logic rom_req;
288: logic [10:0] rom_addr;
289: logic [31:0] rom_rdata;
290: logic rom_rvalid;
291:
292: tlul_adapter_sram #(
293: .SramAw(11),
294: .SramDw(32),
295: .Outstanding(1),
296: .ErrOnWrite(1)
297: ) tl_adapter_rom (
298: .clk_i (main_clk),
299: .rst_ni (sys_rst_n),
300:
301: .tl_i (tl_rom_d_h2d),
302: .tl_o (tl_rom_d_d2h),
303:
304: .req_o (rom_req),
305: .gnt_i (1'b1), // Always grant as only one requester exists
306: .we_o (),
307: .addr_o (rom_addr),
308: .wdata_o (),
309: .wmask_o (),
310: .rdata_i (rom_rdata),
311: .rvalid_i (rom_rvalid),
312: .rerror_i (2'b00)
313: );
314:
315: prim_rom #(
316: .Width(32),
317: .Depth(2048)
318: ) u_rom_rom (
319: .clk_i (main_clk),
320: .rst_ni (sys_rst_n),
321: .cs_i (rom_req),
322: .addr_i (rom_addr),
323: .dout_o (rom_rdata),
324: .dvalid_o (rom_rvalid)
325: );
326:
327: // sram device
328: logic ram_main_req;
329: logic ram_main_we;
330: logic [13:0] ram_main_addr;
331: logic [31:0] ram_main_wdata;
332: logic [31:0] ram_main_wmask;
333: logic [31:0] ram_main_rdata;
334: logic ram_main_rvalid;
335:
336: tlul_adapter_sram #(
337: .SramAw(14),
338: .SramDw(32),
339: .Outstanding(1)
340: ) tl_adapter_ram_main (
341: .clk_i (main_clk),
342: .rst_ni (sys_rst_n),
343: .tl_i (tl_ram_main_d_h2d),
344: .tl_o (tl_ram_main_d_d2h),
345:
346: .req_o (ram_main_req),
347: .gnt_i (1'b1), // Always grant as only one requester exists
348: .we_o (ram_main_we),
349: .addr_o (ram_main_addr),
350: .wdata_o (ram_main_wdata),
351: .wmask_o (ram_main_wmask),
352: .rdata_i (ram_main_rdata),
353: .rvalid_i (ram_main_rvalid),
354: .rerror_i (2'b00)
355: );
356:
357: prim_ram_1p #(
358: .Width(32),
359: .Depth(16384),
360: .DataBitsPerMask(8)
361: ) u_ram1p_ram_main (
362: .clk_i (main_clk),
363: .rst_ni (sys_rst_n),
364:
365: .req_i (ram_main_req),
366: .write_i (ram_main_we),
367: .addr_i (ram_main_addr),
368: .wdata_i (ram_main_wdata),
369: .wmask_i (ram_main_wmask),
370: .rvalid_o (ram_main_rvalid),
371: .rdata_o (ram_main_rdata)
372: );
373:
374: // flash controller to eflash communication
375: flash_c2m_t flash_c2m;
376: flash_m2c_t flash_m2c;
377:
378: // host to flash communication
379: logic flash_host_req;
380: logic flash_host_req_rdy;
381: logic flash_host_req_done;
382: logic [FLASH_DW-1:0] flash_host_rdata;
383: logic [FLASH_AW-1:0] flash_host_addr;
384:
385: tlul_adapter_sram #(
386: .SramAw(FLASH_AW),
387: .SramDw(FLASH_DW),
388: .Outstanding(1),
389: .ByteAccess(0),
390: .ErrOnWrite(1)
391: ) tl_adapter_eflash (
392: .clk_i (main_clk),
393: .rst_ni (lc_rst_n),
394:
395: .tl_i (tl_eflash_d_h2d),
396: .tl_o (tl_eflash_d_d2h),
397:
398: .req_o (flash_host_req),
399: .gnt_i (flash_host_req_rdy),
400: .we_o (),
401: .addr_o (flash_host_addr),
402: .wdata_o (),
403: .wmask_o (),
404: .rdata_i (flash_host_rdata),
405: .rvalid_i (flash_host_req_done),
406: .rerror_i (2'b00)
407: );
408:
409: flash_phy #(
410: .NumBanks(FLASH_BANKS),
411: .PagesPerBank(FLASH_PAGES_PER_BANK),
412: .WordsPerPage(FLASH_WORDS_PER_PAGE),
413: .DataWidth(32)
414: ) u_flash_eflash (
415: .clk_i (main_clk),
416: .rst_ni (lc_rst_n),
417: .host_req_i (flash_host_req),
418: .host_addr_i (flash_host_addr),
419: .host_req_rdy_o (flash_host_req_rdy),
420: .host_req_done_o (flash_host_req_done),
421: .host_rdata_o (flash_host_rdata),
422: .flash_ctrl_i (flash_c2m),
423: .flash_ctrl_o (flash_m2c)
424: );
425:
426:
427:
428: uart uart (
429: .tl_i (tl_uart_d_h2d),
430: .tl_o (tl_uart_d_d2h),
431:
432: // Input
433: .cio_rx_i (cio_uart_rx_p2d),
434:
435: // Output
436: .cio_tx_o (cio_uart_tx_d2p),
437: .cio_tx_en_o (cio_uart_tx_en_d2p),
438:
439: // Interrupt
440: .intr_tx_watermark_o (intr_uart_tx_watermark),
441: .intr_rx_watermark_o (intr_uart_rx_watermark),
442: .intr_tx_empty_o (intr_uart_tx_empty),
443: .intr_rx_overflow_o (intr_uart_rx_overflow),
444: .intr_rx_frame_err_o (intr_uart_rx_frame_err),
445: .intr_rx_break_err_o (intr_uart_rx_break_err),
446: .intr_rx_timeout_o (intr_uart_rx_timeout),
447: .intr_rx_parity_err_o (intr_uart_rx_parity_err),
448:
449: .clk_i (fixed_clk),
450: .rst_ni (sys_fixed_rst_n)
451: );
452:
453: gpio gpio (
454: .tl_i (tl_gpio_d_h2d),
455: .tl_o (tl_gpio_d_d2h),
456:
457: // Input
458: .cio_gpio_i (cio_gpio_gpio_p2d),
459:
460: // Output
461: .cio_gpio_o (cio_gpio_gpio_d2p),
462: .cio_gpio_en_o (cio_gpio_gpio_en_d2p),
463:
464: // Interrupt
465: .intr_gpio_o (intr_gpio_gpio),
466:
467: .clk_i (fixed_clk),
468: .rst_ni (sys_fixed_rst_n)
469: );
470:
471: spi_device spi_device (
472: .tl_i (tl_spi_device_d_h2d),
473: .tl_o (tl_spi_device_d_d2h),
474:
475: // Input
476: .cio_sck_i (cio_spi_device_sck_p2d),
477: .cio_csb_i (cio_spi_device_csb_p2d),
478: .cio_mosi_i (cio_spi_device_mosi_p2d),
479:
480: // Output
481: .cio_miso_o (cio_spi_device_miso_d2p),
482: .cio_miso_en_o (cio_spi_device_miso_en_d2p),
483:
484: // Interrupt
485: .intr_rxf_o (intr_spi_device_rxf),
486: .intr_rxlvl_o (intr_spi_device_rxlvl),
487: .intr_txlvl_o (intr_spi_device_txlvl),
488: .intr_rxerr_o (intr_spi_device_rxerr),
489: .intr_rxoverflow_o (intr_spi_device_rxoverflow),
490: .intr_txunderflow_o (intr_spi_device_txunderflow),
491: .scanmode_i (scanmode_i),
492:
493: .clk_i (fixed_clk),
494: .rst_ni (spi_device_rst_n)
495: );
496:
497: flash_ctrl flash_ctrl (
498: .tl_i (tl_flash_ctrl_d_h2d),
499: .tl_o (tl_flash_ctrl_d_d2h),
500:
501: // Interrupt
502: .intr_prog_empty_o (intr_flash_ctrl_prog_empty),
503: .intr_prog_lvl_o (intr_flash_ctrl_prog_lvl),
504: .intr_rd_full_o (intr_flash_ctrl_rd_full),
505: .intr_rd_lvl_o (intr_flash_ctrl_rd_lvl),
506: .intr_op_done_o (intr_flash_ctrl_op_done),
507: .intr_op_error_o (intr_flash_ctrl_op_error),
508:
509: .flash_o(flash_c2m),
510: .flash_i(flash_m2c),
511:
512: .clk_i (main_clk),
513: .rst_ni (lc_rst_n)
514: );
515:
516: rv_timer rv_timer (
517: .tl_i (tl_rv_timer_d_h2d),
518: .tl_o (tl_rv_timer_d_d2h),
519:
520: // Interrupt
521: .intr_timer_expired_0_0_o (intr_rv_timer_timer_expired_0_0),
522:
523: .clk_i (fixed_clk),
524: .rst_ni (sys_fixed_rst_n)
525: );
526:
527: aes aes (
528: .tl_i (tl_aes_d_h2d),
529: .tl_o (tl_aes_d_d2h),
530:
531: .clk_i (main_clk),
532: .rst_ni (sys_rst_n)
533: );
534:
535: hmac hmac (
536: .tl_i (tl_hmac_d_h2d),
537: .tl_o (tl_hmac_d_d2h),
538:
539: // Interrupt
540: .intr_hmac_done_o (intr_hmac_hmac_done),
541: .intr_fifo_full_o (intr_hmac_fifo_full),
542: .intr_hmac_err_o (intr_hmac_hmac_err),
543:
544: // [0]: msg_push_sha_disabled
545: .alert_tx_o ( alert_tx[0:0] ),
546: .alert_rx_i ( alert_rx[0:0] ),
547:
548: .clk_i (main_clk),
549: .rst_ni (sys_rst_n)
550: );
551:
552: rv_plic rv_plic (
553: .tl_i (tl_rv_plic_d_h2d),
554: .tl_o (tl_rv_plic_d_d2h),
555:
556: .intr_src_i (intr_vector),
557: .irq_o (irq_plic),
558: .irq_id_o (irq_id),
559: .msip_o (msip),
560:
561: .clk_i (main_clk),
562: .rst_ni (sys_rst_n)
563: );
564:
565: pinmux pinmux (
566: .tl_i (tl_pinmux_d_h2d),
567: .tl_o (tl_pinmux_d_d2h),
568:
569: .periph_to_mio_i (p2m ),
570: .periph_to_mio_oe_i (p2m_en ),
571: .mio_to_periph_o (m2p ),
572:
573: .mio_out_o (mio_out_o),
574: .mio_oe_o (mio_oe_o ),
575: .mio_in_i (mio_in_i ),
576:
577: .clk_i (main_clk),
578: .rst_ni (sys_rst_n)
579: );
580:
581: alert_handler alert_handler (
582: .tl_i (tl_alert_handler_d_h2d),
583: .tl_o (tl_alert_handler_d_d2h),
584:
585: // Interrupt
586: .intr_classa_o (intr_alert_handler_classa),
587: .intr_classb_o (intr_alert_handler_classb),
588: .intr_classc_o (intr_alert_handler_classc),
589: .intr_classd_o (intr_alert_handler_classd),
590: // TODO: wire this to hardware debug circuit
591: .crashdump_o ( ),
592: // TODO: wire this to TRNG
593: .entropy_i ( 1'b0 ),
594: // alert signals
595: .alert_rx_o ( alert_rx ),
596: .alert_tx_i ( alert_tx ),
597: // escalation outputs
598: .esc_rx_i ( esc_rx ),
599: .esc_tx_o ( esc_tx ),
600:
601: .clk_i (main_clk),
602: .rst_ni (sys_rst_n)
603: );
604:
605: nmi_gen nmi_gen (
606: .tl_i (tl_nmi_gen_d_h2d),
607: .tl_o (tl_nmi_gen_d_d2h),
608:
609: // Interrupt
610: .intr_esc0_o (intr_nmi_gen_esc0),
611: .intr_esc1_o (intr_nmi_gen_esc1),
612: .intr_esc2_o (intr_nmi_gen_esc2),
613: .intr_esc3_o (intr_nmi_gen_esc3),
614: // escalation signal inputs
615: .esc_rx_o ( esc_rx ),
616: .esc_tx_i ( esc_tx ),
617:
618: .clk_i (main_clk),
619: .rst_ni (sys_rst_n)
620: );
621:
622: // interrupt assignments
623: assign intr_vector = {
624: intr_nmi_gen_esc3,
625: intr_nmi_gen_esc2,
626: intr_nmi_gen_esc1,
627: intr_nmi_gen_esc0,
628: intr_alert_handler_classd,
629: intr_alert_handler_classc,
630: intr_alert_handler_classb,
631: intr_alert_handler_classa,
632: intr_hmac_hmac_err,
633: intr_hmac_fifo_full,
634: intr_hmac_hmac_done,
635: intr_flash_ctrl_op_error,
636: intr_flash_ctrl_op_done,
637: intr_flash_ctrl_rd_lvl,
638: intr_flash_ctrl_rd_full,
639: intr_flash_ctrl_prog_lvl,
640: intr_flash_ctrl_prog_empty,
641: intr_spi_device_txunderflow,
642: intr_spi_device_rxoverflow,
643: intr_spi_device_rxerr,
644: intr_spi_device_txlvl,
645: intr_spi_device_rxlvl,
646: intr_spi_device_rxf,
647: intr_uart_rx_parity_err,
648: intr_uart_rx_timeout,
649: intr_uart_rx_break_err,
650: intr_uart_rx_frame_err,
651: intr_uart_rx_overflow,
652: intr_uart_tx_empty,
653: intr_uart_rx_watermark,
654: intr_uart_tx_watermark,
655: intr_gpio_gpio
656: };
657:
658: // TL-UL Crossbar
659: xbar_main u_xbar_main (
660: .clk_main_i (main_clk),
661: .clk_fixed_i (fixed_clk),
662: .rst_main_ni (sys_rst_n),
663: .rst_fixed_ni (sys_fixed_rst_n),
664: .tl_corei_i (tl_corei_h_h2d),
665: .tl_corei_o (tl_corei_h_d2h),
666: .tl_cored_i (tl_cored_h_h2d),
667: .tl_cored_o (tl_cored_h_d2h),
668: .tl_dm_sba_i (tl_dm_sba_h_h2d),
669: .tl_dm_sba_o (tl_dm_sba_h_d2h),
670: .tl_rom_o (tl_rom_d_h2d),
671: .tl_rom_i (tl_rom_d_d2h),
672: .tl_debug_mem_o (tl_debug_mem_d_h2d),
673: .tl_debug_mem_i (tl_debug_mem_d_d2h),
674: .tl_ram_main_o (tl_ram_main_d_h2d),
675: .tl_ram_main_i (tl_ram_main_d_d2h),
676: .tl_eflash_o (tl_eflash_d_h2d),
677: .tl_eflash_i (tl_eflash_d_d2h),
678: .tl_peri_o (tl_peri_d_h2d),
679: .tl_peri_i (tl_peri_d_d2h),
680: .tl_flash_ctrl_o (tl_flash_ctrl_d_h2d),
681: .tl_flash_ctrl_i (tl_flash_ctrl_d_d2h),
682: .tl_hmac_o (tl_hmac_d_h2d),
683: .tl_hmac_i (tl_hmac_d_d2h),
684: .tl_aes_o (tl_aes_d_h2d),
685: .tl_aes_i (tl_aes_d_d2h),
686: .tl_rv_plic_o (tl_rv_plic_d_h2d),
687: .tl_rv_plic_i (tl_rv_plic_d_d2h),
688: .tl_pinmux_o (tl_pinmux_d_h2d),
689: .tl_pinmux_i (tl_pinmux_d_d2h),
690: .tl_alert_handler_o (tl_alert_handler_d_h2d),
691: .tl_alert_handler_i (tl_alert_handler_d_d2h),
692: .tl_nmi_gen_o (tl_nmi_gen_d_h2d),
693: .tl_nmi_gen_i (tl_nmi_gen_d_d2h),
694:
695: .scanmode_i
696: );
697: xbar_peri u_xbar_peri (
698: .clk_peri_i (fixed_clk),
699: .rst_peri_ni (sys_fixed_rst_n),
700: .tl_main_i (tl_main_h_h2d),
701: .tl_main_o (tl_main_h_d2h),
702: .tl_uart_o (tl_uart_d_h2d),
703: .tl_uart_i (tl_uart_d_d2h),
704: .tl_gpio_o (tl_gpio_d_h2d),
705: .tl_gpio_i (tl_gpio_d_d2h),
706: .tl_spi_device_o (tl_spi_device_d_h2d),
707: .tl_spi_device_i (tl_spi_device_d_d2h),
708: .tl_rv_timer_o (tl_rv_timer_d_h2d),
709: .tl_rv_timer_i (tl_rv_timer_d_d2h),
710:
711: .scanmode_i
712: );
713:
714: // Pinmux connections
715: assign p2m = {
716: cio_gpio_gpio_d2p
717: };
718: assign p2m_en = {
719: cio_gpio_gpio_en_d2p
720: };
721: assign {
722: cio_gpio_gpio_p2d
723: } = m2p;
724:
725: assign cio_spi_device_sck_p2d = dio_spi_device_sck_i;
726: assign cio_spi_device_csb_p2d = dio_spi_device_csb_i;
727: assign cio_spi_device_mosi_p2d = dio_spi_device_mosi_i;
728: assign dio_spi_device_miso_o = cio_spi_device_miso_d2p;
729: assign dio_spi_device_miso_en_o = cio_spi_device_miso_en_d2p;
730: assign cio_uart_rx_p2d = dio_uart_rx_i;
731: assign dio_uart_tx_o = cio_uart_tx_d2p;
732: assign dio_uart_tx_en_o = cio_uart_tx_en_d2p;
733:
734: // make sure scanmode_i is never X (including during reset)
735: `ASSERT_KNOWN(scanmodeKnown, scanmode_i, clk_i, 0)
736:
737: endmodule
738: