hw/ip/tlul/rtl/tlul_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5:
6: package tlul_pkg;
7:
8: // this can be either PPC or BINTREE
9: // there is no functional difference, but timing and area behavior is different
10: // between the two instances. PPC can result in smaller implementations when timing
11: // is not critical, whereas BINTREE is favorable when timing pressure is high (but this
12: // may also result in a larger implementation). on FPGA targets, BINTREE is favorable
13: // both in terms of area and timing.
14: parameter ArbiterImpl = "BINTREE";
15:
16: typedef enum logic [2:0] {
17: PutFullData = 3'h 0,
18: PutPartialData = 3'h 1,
19: Get = 3'h 4
20: } tl_a_op_e;
21: typedef enum logic [2:0] {
22: AccessAck = 3'h 0,
23: AccessAckData = 3'h 1
24: } tl_d_op_e;
25:
26: typedef struct packed {
27: logic [6:0] rsvd1; // Reserved for future use
28: logic parity_en;
29: logic [7:0] parity; // Use only lower TL_DBW bit
30: } tl_a_user_t;
31:
32: typedef struct packed {
33: logic a_valid;
34: tl_a_op_e a_opcode;
35: logic [2:0] a_param;
36: logic [top_pkg::TL_SZW-1:0] a_size;
37: logic [top_pkg::TL_AIW-1:0] a_source;
38: logic [top_pkg::TL_AW-1:0] a_address;
39: logic [top_pkg::TL_DBW-1:0] a_mask;
40: logic [top_pkg::TL_DW-1:0] a_data;
41: tl_a_user_t a_user;
42:
43: logic d_ready;
44: } tl_h2d_t;
45:
46: typedef struct packed {
47: logic d_valid;
48: tl_d_op_e d_opcode;
49: logic [2:0] d_param;
50: logic [top_pkg::TL_SZW-1:0] d_size; // Bouncing back a_size
51: logic [top_pkg::TL_AIW-1:0] d_source;
52: logic [top_pkg::TL_DIW-1:0] d_sink;
53: logic [top_pkg::TL_DW-1:0] d_data;
54: logic [top_pkg::TL_DUW-1:0] d_user;
55: logic d_error;
56:
57: logic a_ready;
58: } tl_d2h_t;
59:
60: endpackage
61: