hw/top_earlgrey/ip/xbar_peri/rtl/autogen/xbar_peri.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // xbar_peri module generated by `tlgen.py` tool
   6: // all reset signals should be generated from one reset signal to not make any deadlock
   7: //
   8: // Interconnect
   9: // main
  10: //   -> s1n_5
  11: //     -> uart
  12: //     -> gpio
  13: //     -> spi_device
  14: //     -> rv_timer
  15: 
  16: module xbar_peri (
  17:   input clk_peri_i,
  18:   input rst_peri_ni,
  19: 
  20:   // Host interfaces
  21:   input  tlul_pkg::tl_h2d_t tl_main_i,
  22:   output tlul_pkg::tl_d2h_t tl_main_o,
  23: 
  24:   // Device interfaces
  25:   output tlul_pkg::tl_h2d_t tl_uart_o,
  26:   input  tlul_pkg::tl_d2h_t tl_uart_i,
  27:   output tlul_pkg::tl_h2d_t tl_gpio_o,
  28:   input  tlul_pkg::tl_d2h_t tl_gpio_i,
  29:   output tlul_pkg::tl_h2d_t tl_spi_device_o,
  30:   input  tlul_pkg::tl_d2h_t tl_spi_device_i,
  31:   output tlul_pkg::tl_h2d_t tl_rv_timer_o,
  32:   input  tlul_pkg::tl_d2h_t tl_rv_timer_i,
  33: 
  34:   input scanmode_i
  35: );
  36: 
  37:   import tlul_pkg::*;
  38:   import tl_peri_pkg::*;
  39: 
  40:   // scanmode_i is currently not used, but provisioned for future use
  41:   // this assignment prevents lint warnings
  42:   logic unused_scanmode;
  43:   assign unused_scanmode = scanmode_i;
  44: 
  45:   tl_h2d_t tl_s1n_5_us_h2d ;
  46:   tl_d2h_t tl_s1n_5_us_d2h ;
  47: 
  48: 
  49:   tl_h2d_t tl_s1n_5_ds_h2d [4];
  50:   tl_d2h_t tl_s1n_5_ds_d2h [4];
  51: 
  52:   // Create steering signal
  53:   logic [2:0] dev_sel_s1n_5;
  54: 
  55: 
  56: 
  57:   assign tl_uart_o = tl_s1n_5_ds_h2d[0];
  58:   assign tl_s1n_5_ds_d2h[0] = tl_uart_i;
  59: 
  60:   assign tl_gpio_o = tl_s1n_5_ds_h2d[1];
  61:   assign tl_s1n_5_ds_d2h[1] = tl_gpio_i;
  62: 
  63:   assign tl_spi_device_o = tl_s1n_5_ds_h2d[2];
  64:   assign tl_s1n_5_ds_d2h[2] = tl_spi_device_i;
  65: 
  66:   assign tl_rv_timer_o = tl_s1n_5_ds_h2d[3];
  67:   assign tl_s1n_5_ds_d2h[3] = tl_rv_timer_i;
  68: 
  69:   assign tl_s1n_5_us_h2d = tl_main_i;
  70:   assign tl_main_o = tl_s1n_5_us_d2h;
  71: 
  72:   always_comb begin
  73:     // default steering to generate error response if address is not within the range
  74:     dev_sel_s1n_5 = 3'd4;
  75:     if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_UART)) == ADDR_SPACE_UART) begin
  76:       dev_sel_s1n_5 = 3'd0;
  77:     
  78:     end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_GPIO)) == ADDR_SPACE_GPIO) begin
  79:       dev_sel_s1n_5 = 3'd1;
  80:     
  81:     end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_SPI_DEVICE)) == ADDR_SPACE_SPI_DEVICE) begin
  82:       dev_sel_s1n_5 = 3'd2;
  83:     
  84:     end else if ((tl_s1n_5_us_h2d.a_address & ~(ADDR_MASK_RV_TIMER)) == ADDR_SPACE_RV_TIMER) begin
  85:       dev_sel_s1n_5 = 3'd3;
  86:     end
  87:   end
  88: 
  89: 
  90:   // Instantiation phase
  91:   tlul_socket_1n #(
  92:     .HReqDepth (4'h0),
  93:     .HRspDepth (4'h0),
  94:     .DReqDepth ({4{4'h0}}),
  95:     .DRspDepth ({4{4'h0}}),
  96:     .N         (4)
  97:   ) u_s1n_5 (
  98:     .clk_i        (clk_peri_i),
  99:     .rst_ni       (rst_peri_ni),
 100:     .tl_h_i       (tl_s1n_5_us_h2d),
 101:     .tl_h_o       (tl_s1n_5_us_d2h),
 102:     .tl_d_o       (tl_s1n_5_ds_h2d),
 103:     .tl_d_i       (tl_s1n_5_ds_d2h),
 104:     .dev_select   (dev_sel_s1n_5)
 105:   );
 106: 
 107: endmodule
 108: