../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/debug_rom/debug_rom.sv Cov: 100%

   1: /* Copyright 2018 ETH Zurich and University of Bologna.
   2:  * Copyright and related rights are licensed under the Solderpad Hardware
   3:  * License, Version 0.51 (the "License"); you may not use this file except in
   4:  * compliance with the License.  You may obtain a copy of the License at
   5:  * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
   6:  * or agreed to in writing, software, hardware and materials distributed under
   7:  * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
   8:  * CONDITIONS OF ANY KIND, either express or implied. See the License for the
   9:  * specific language governing permissions and limitations under the License.
  10:  *
  11:  * File: $filename.v
  12:  *
  13:  * Description: Auto-generated bootrom
  14:  */
  15: 
  16: // Auto-generated code
  17: module debug_rom (
  18:   input  logic         clk_i,
  19:   input  logic         req_i,
  20:   input  logic [63:0]  addr_i,
  21:   output logic [63:0]  rdata_o
  22: );
  23: 
  24:   localparam int unsigned RomSize = 19;
  25: 
  26:   const logic [RomSize-1:0][63:0] mem = {
  27:     64'h00000000_7b200073,
  28:     64'h7b302573_7b202473,
  29:     64'h10852423_f1402473,
  30:     64'ha85ff06f_7b302573,
  31:     64'h7b202473_10052223,
  32:     64'h00100073_7b302573,
  33:     64'h7b202473_10052623,
  34:     64'h00c51513_00c55513,
  35:     64'h00000517_fd5ff06f,
  36:     64'hfa041ce3_00247413,
  37:     64'h40044403_00a40433,
  38:     64'hf1402473_02041c63,
  39:     64'h00147413_40044403,
  40:     64'h00a40433_10852023,
  41:     64'hf1402473_00c51513,
  42:     64'h00c55513_00000517,
  43:     64'h7b351073_7b241073,
  44:     64'h0ff0000f_04c0006f,
  45:     64'h07c0006f_00c0006f
  46:   };
  47: 
  48:   logic [$clog2(RomSize)-1:0] addr_q;
  49: 
  50:   always_ff @(posedge clk_i) begin
  51:     if (req_i) begin
  52:       addr_q <= addr_i[$clog2(RomSize)-1+3:3];
  53:     end
  54:   end
  55: 
  56:   // this prevents spurious Xes from propagating into
  57:   // the speculative fetch stage of the core
  58:   always_comb begin : p_outmux
  59:     rdata_o = '0;
  60:     if (addr_q < $clog2(RomSize)'(RomSize)) begin
  61:         rdata_o = mem[addr_q];
  62:     end
  63:   end
  64: 
  65: endmodule
  66: