../src/lowrisc_prim_generic_clock_mux2_0/rtl/prim_generic_clock_mux2.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4:
5: `include "prim_assert.sv"
6:
7: module prim_generic_clock_mux2 (
8: input clk0_i,
9: input clk1_i,
10: input sel_i,
11: output logic clk_o
12: );
13:
14: assign clk_o = (sel_i) ? clk1_i : clk0_i;
15:
16: // make sure sel is never X (including during reset)
17: // need to use ##1 as this could break with inverted clocks that
18: // start with a rising edge at the beginning of the simulation.
19: `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0)
20: `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0)
21:
22: endmodule : prim_generic_clock_mux2
23: