hw/ip/tlul/rtl/tlul_err.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: 
   6: module tlul_err import tlul_pkg::*; (
   7:   input clk_i,
   8:   input rst_ni,
   9: 
  10:   input tl_h2d_t tl_i,
  11: 
  12:   output logic err_o
  13: );
  14: 
  15:   localparam int IW  = $bits(tl_i.a_source);
  16:   localparam int SZW = $bits(tl_i.a_size);
  17:   localparam int DW  = $bits(tl_i.a_data);
  18:   localparam int MW  = $bits(tl_i.a_mask);
  19:   localparam int SubAW = $clog2(DW/8);
  20: 
  21:   logic opcode_allowed, a_config_allowed;
  22: 
  23:   logic op_full, op_partial, op_get;
  24:   assign op_full    = (tl_i.a_opcode == PutFullData);
  25:   assign op_partial = (tl_i.a_opcode == PutPartialData);
  26:   assign op_get     = (tl_i.a_opcode == Get);
  27: 
  28:   // Anything that doesn't fall into the permitted category, it raises an error
  29:   assign err_o = ~(opcode_allowed & a_config_allowed);
  30: 
  31:   // opcode check
  32:   assign opcode_allowed = (tl_i.a_opcode == PutFullData)
  33:                         | (tl_i.a_opcode == PutPartialData)
  34:                         | (tl_i.a_opcode == Get);
  35: 
  36:   // a channel configuration check
  37:   logic addr_sz_chk;    // address and size alignment check
  38:   logic mask_chk;       // inactive lane a_mask check
  39:   logic fulldata_chk;   // PutFullData should have size match to mask
  40: 
  41:   logic [MW-1:0] mask;
  42: 
  43:   assign mask = (1 << tl_i.a_address[SubAW-1:0]);
  44: 
  45:   always_comb begin
  46:     addr_sz_chk  = 1'b0;
  47:     mask_chk     = 1'b0;
  48:     fulldata_chk = 1'b0; // Only valid when opcode is PutFullData
  49: 
  50:     if (tl_i.a_valid) begin
  51:       unique case (tl_i.a_size)
  52:         'h0: begin // 1 Byte
  53:           addr_sz_chk  = 1'b1;
  54:           mask_chk     = ~|(tl_i.a_mask & ~mask);
  55:           fulldata_chk = |(tl_i.a_mask & mask);
  56:         end
  57: 
  58:         'h1: begin // 2 Byte
  59:           addr_sz_chk  = ~tl_i.a_address[0];
  60:           // check inactive lanes if lower 2B, check a_mask[3:2], if uppwer 2B, a_mask[1:0]
  61:           mask_chk     = (tl_i.a_address[1]) ? ~|(tl_i.a_mask & 4'b0011)
  62:                        : ~|(tl_i.a_mask & 4'b1100);
  63:           fulldata_chk = (tl_i.a_address[1]) ? &tl_i.a_mask[3:2] : &tl_i.a_mask[1:0] ;
  64:         end
  65: 
  66:         'h2: begin // 4 Byte
  67:           addr_sz_chk  = ~|tl_i.a_address[SubAW-1:0];
  68:           mask_chk     = 1'b1;
  69:           fulldata_chk = &tl_i.a_mask[3:0];
  70:         end
  71: 
  72:         default: begin // else
  73:           addr_sz_chk  = 1'b0;
  74:           mask_chk     = 1'b0;
  75:           fulldata_chk = 1'b0;
  76:         end
  77:       endcase
  78:     end else begin
  79:       addr_sz_chk  = 1'b0;
  80:       mask_chk     = 1'b0;
  81:       fulldata_chk = 1'b0;
  82:     end
  83:   end
  84: 
  85:   assign a_config_allowed = addr_sz_chk
  86:                           & mask_chk
  87:                           & (op_get | op_partial | fulldata_chk) ;
  88: 
  89:   // Only 32 bit data width for current tlul_err
  90:   `ASSERT_INIT(dataWidthOnly32_A, DW == 32)
  91: 
  92: endmodule
  93: 
  94: