hw/ip/flash_ctrl/rtl/flash_ctrl_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: module flash_ctrl_reg_top (
   8:   input clk_i,
   9:   input rst_ni,
  10: 
  11:   // Below Regster interface can be changed
  12:   input  tlul_pkg::tl_h2d_t tl_i,
  13:   output tlul_pkg::tl_d2h_t tl_o,
  14: 
  15:   // Output port for window
  16:   output tlul_pkg::tl_h2d_t tl_win_o  [2],
  17:   input  tlul_pkg::tl_d2h_t tl_win_i  [2],
  18: 
  19:   // To HW
  20:   output flash_ctrl_reg_pkg::flash_ctrl_reg2hw_t reg2hw, // Write
  21:   input  flash_ctrl_reg_pkg::flash_ctrl_hw2reg_t hw2reg, // Read
  22: 
  23:   // Config
  24:   input devmode_i // If 1, explicit error return for unmapped register access
  25: );
  26: 
  27:   import flash_ctrl_reg_pkg::* ;
  28: 
  29:   localparam int AW = 7;
  30:   localparam int DW = 32;
  31:   localparam int DBW = DW/8;                    // Byte Width
  32: 
  33:   // register signals
  34:   logic           reg_we;
  35:   logic           reg_re;
  36:   logic [AW-1:0]  reg_addr;
  37:   logic [DW-1:0]  reg_wdata;
  38:   logic [DBW-1:0] reg_be;
  39:   logic [DW-1:0]  reg_rdata;
  40:   logic           reg_error;
  41: 
  42:   logic          addrmiss, wr_err;
  43: 
  44:   logic [DW-1:0] reg_rdata_next;
  45: 
  46:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  47:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  48: 
  49:   tlul_pkg::tl_h2d_t tl_socket_h2d [3];
  50:   tlul_pkg::tl_d2h_t tl_socket_d2h [3];
  51: 
  52:   logic [1:0] reg_steer;
  53: 
  54:   // socket_1n connection
  55:   assign tl_reg_h2d = tl_socket_h2d[2];
  56:   assign tl_socket_d2h[2] = tl_reg_d2h;
  57: 
  58:   assign tl_win_o[0] = tl_socket_h2d[0];
  59:   assign tl_socket_d2h[0] = tl_win_i[0];
  60:   assign tl_win_o[1] = tl_socket_h2d[1];
  61:   assign tl_socket_d2h[1] = tl_win_i[1];
  62: 
  63:   // Create Socket_1n
  64:   tlul_socket_1n #(
  65:     .N          (3),
  66:     .HReqPass   (1'b1),
  67:     .HRspPass   (1'b1),
  68:     .DReqPass   ({3{1'b1}}),
  69:     .DRspPass   ({3{1'b1}}),
  70:     .HReqDepth  (4'h0),
  71:     .HRspDepth  (4'h0),
  72:     .DReqDepth  ({3{4'h0}}),
  73:     .DRspDepth  ({3{4'h0}})
  74:   ) u_socket (
  75:     .clk_i,
  76:     .rst_ni,
  77:     .tl_h_i (tl_i),
  78:     .tl_h_o (tl_o),
  79:     .tl_d_o (tl_socket_h2d),
  80:     .tl_d_i (tl_socket_d2h),
  81:     .dev_select (reg_steer)
  82:   );
  83: 
  84:   // Create steering logic
  85:   always_comb begin
  86:     reg_steer = 2;       // Default set to register
  87: 
  88:     // TODO: Can below codes be unique case () inside ?
  89:     if (tl_i.a_address[AW-1:0] >= 84 && tl_i.a_address[AW-1:0] < 88) begin
  90:       reg_steer = 0;
  91:     end
  92:     if (tl_i.a_address[AW-1:0] >= 88 && tl_i.a_address[AW-1:0] < 92) begin
  93:       reg_steer = 1;
  94:     end
  95:   end
  96: 
  97:   tlul_adapter_reg #(
  98:     .RegAw(AW),
  99:     .RegDw(DW)
 100:   ) u_reg_if (
 101:     .clk_i,
 102:     .rst_ni,
 103: 
 104:     .tl_i (tl_reg_h2d),
 105:     .tl_o (tl_reg_d2h),
 106: 
 107:     .we_o    (reg_we),
 108:     .re_o    (reg_re),
 109:     .addr_o  (reg_addr),
 110:     .wdata_o (reg_wdata),
 111:     .be_o    (reg_be),
 112:     .rdata_i (reg_rdata),
 113:     .error_i (reg_error)
 114:   );
 115: 
 116:   assign reg_rdata = reg_rdata_next ;
 117:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
 118: 
 119:   // Define SW related signals
 120:   // Format: __{wd|we|qs}
 121:   //        or _{wd|we|qs} if field == 1 or 0
 122:   logic intr_state_prog_empty_qs;
 123:   logic intr_state_prog_empty_wd;
 124:   logic intr_state_prog_empty_we;
 125:   logic intr_state_prog_lvl_qs;
 126:   logic intr_state_prog_lvl_wd;
 127:   logic intr_state_prog_lvl_we;
 128:   logic intr_state_rd_full_qs;
 129:   logic intr_state_rd_full_wd;
 130:   logic intr_state_rd_full_we;
 131:   logic intr_state_rd_lvl_qs;
 132:   logic intr_state_rd_lvl_wd;
 133:   logic intr_state_rd_lvl_we;
 134:   logic intr_state_op_done_qs;
 135:   logic intr_state_op_done_wd;
 136:   logic intr_state_op_done_we;
 137:   logic intr_state_op_error_qs;
 138:   logic intr_state_op_error_wd;
 139:   logic intr_state_op_error_we;
 140:   logic intr_enable_prog_empty_qs;
 141:   logic intr_enable_prog_empty_wd;
 142:   logic intr_enable_prog_empty_we;
 143:   logic intr_enable_prog_lvl_qs;
 144:   logic intr_enable_prog_lvl_wd;
 145:   logic intr_enable_prog_lvl_we;
 146:   logic intr_enable_rd_full_qs;
 147:   logic intr_enable_rd_full_wd;
 148:   logic intr_enable_rd_full_we;
 149:   logic intr_enable_rd_lvl_qs;
 150:   logic intr_enable_rd_lvl_wd;
 151:   logic intr_enable_rd_lvl_we;
 152:   logic intr_enable_op_done_qs;
 153:   logic intr_enable_op_done_wd;
 154:   logic intr_enable_op_done_we;
 155:   logic intr_enable_op_error_qs;
 156:   logic intr_enable_op_error_wd;
 157:   logic intr_enable_op_error_we;
 158:   logic intr_test_prog_empty_wd;
 159:   logic intr_test_prog_empty_we;
 160:   logic intr_test_prog_lvl_wd;
 161:   logic intr_test_prog_lvl_we;
 162:   logic intr_test_rd_full_wd;
 163:   logic intr_test_rd_full_we;
 164:   logic intr_test_rd_lvl_wd;
 165:   logic intr_test_rd_lvl_we;
 166:   logic intr_test_op_done_wd;
 167:   logic intr_test_op_done_we;
 168:   logic intr_test_op_error_wd;
 169:   logic intr_test_op_error_we;
 170:   logic control_start_qs;
 171:   logic control_start_wd;
 172:   logic control_start_we;
 173:   logic [1:0] control_op_qs;
 174:   logic [1:0] control_op_wd;
 175:   logic control_op_we;
 176:   logic control_erase_sel_qs;
 177:   logic control_erase_sel_wd;
 178:   logic control_erase_sel_we;
 179:   logic control_fifo_rst_qs;
 180:   logic control_fifo_rst_wd;
 181:   logic control_fifo_rst_we;
 182:   logic [11:0] control_num_qs;
 183:   logic [11:0] control_num_wd;
 184:   logic control_num_we;
 185:   logic [31:0] addr_qs;
 186:   logic [31:0] addr_wd;
 187:   logic addr_we;
 188:   logic region_cfg_regwen_qs;
 189:   logic region_cfg_regwen_wd;
 190:   logic region_cfg_regwen_we;
 191:   logic mp_region_cfg0_en0_qs;
 192:   logic mp_region_cfg0_en0_wd;
 193:   logic mp_region_cfg0_en0_we;
 194:   logic mp_region_cfg0_rd_en0_qs;
 195:   logic mp_region_cfg0_rd_en0_wd;
 196:   logic mp_region_cfg0_rd_en0_we;
 197:   logic mp_region_cfg0_prog_en0_qs;
 198:   logic mp_region_cfg0_prog_en0_wd;
 199:   logic mp_region_cfg0_prog_en0_we;
 200:   logic mp_region_cfg0_erase_en0_qs;
 201:   logic mp_region_cfg0_erase_en0_wd;
 202:   logic mp_region_cfg0_erase_en0_we;
 203:   logic [8:0] mp_region_cfg0_base0_qs;
 204:   logic [8:0] mp_region_cfg0_base0_wd;
 205:   logic mp_region_cfg0_base0_we;
 206:   logic [8:0] mp_region_cfg0_size0_qs;
 207:   logic [8:0] mp_region_cfg0_size0_wd;
 208:   logic mp_region_cfg0_size0_we;
 209:   logic mp_region_cfg1_en1_qs;
 210:   logic mp_region_cfg1_en1_wd;
 211:   logic mp_region_cfg1_en1_we;
 212:   logic mp_region_cfg1_rd_en1_qs;
 213:   logic mp_region_cfg1_rd_en1_wd;
 214:   logic mp_region_cfg1_rd_en1_we;
 215:   logic mp_region_cfg1_prog_en1_qs;
 216:   logic mp_region_cfg1_prog_en1_wd;
 217:   logic mp_region_cfg1_prog_en1_we;
 218:   logic mp_region_cfg1_erase_en1_qs;
 219:   logic mp_region_cfg1_erase_en1_wd;
 220:   logic mp_region_cfg1_erase_en1_we;
 221:   logic [8:0] mp_region_cfg1_base1_qs;
 222:   logic [8:0] mp_region_cfg1_base1_wd;
 223:   logic mp_region_cfg1_base1_we;
 224:   logic [8:0] mp_region_cfg1_size1_qs;
 225:   logic [8:0] mp_region_cfg1_size1_wd;
 226:   logic mp_region_cfg1_size1_we;
 227:   logic mp_region_cfg2_en2_qs;
 228:   logic mp_region_cfg2_en2_wd;
 229:   logic mp_region_cfg2_en2_we;
 230:   logic mp_region_cfg2_rd_en2_qs;
 231:   logic mp_region_cfg2_rd_en2_wd;
 232:   logic mp_region_cfg2_rd_en2_we;
 233:   logic mp_region_cfg2_prog_en2_qs;
 234:   logic mp_region_cfg2_prog_en2_wd;
 235:   logic mp_region_cfg2_prog_en2_we;
 236:   logic mp_region_cfg2_erase_en2_qs;
 237:   logic mp_region_cfg2_erase_en2_wd;
 238:   logic mp_region_cfg2_erase_en2_we;
 239:   logic [8:0] mp_region_cfg2_base2_qs;
 240:   logic [8:0] mp_region_cfg2_base2_wd;
 241:   logic mp_region_cfg2_base2_we;
 242:   logic [8:0] mp_region_cfg2_size2_qs;
 243:   logic [8:0] mp_region_cfg2_size2_wd;
 244:   logic mp_region_cfg2_size2_we;
 245:   logic mp_region_cfg3_en3_qs;
 246:   logic mp_region_cfg3_en3_wd;
 247:   logic mp_region_cfg3_en3_we;
 248:   logic mp_region_cfg3_rd_en3_qs;
 249:   logic mp_region_cfg3_rd_en3_wd;
 250:   logic mp_region_cfg3_rd_en3_we;
 251:   logic mp_region_cfg3_prog_en3_qs;
 252:   logic mp_region_cfg3_prog_en3_wd;
 253:   logic mp_region_cfg3_prog_en3_we;
 254:   logic mp_region_cfg3_erase_en3_qs;
 255:   logic mp_region_cfg3_erase_en3_wd;
 256:   logic mp_region_cfg3_erase_en3_we;
 257:   logic [8:0] mp_region_cfg3_base3_qs;
 258:   logic [8:0] mp_region_cfg3_base3_wd;
 259:   logic mp_region_cfg3_base3_we;
 260:   logic [8:0] mp_region_cfg3_size3_qs;
 261:   logic [8:0] mp_region_cfg3_size3_wd;
 262:   logic mp_region_cfg3_size3_we;
 263:   logic mp_region_cfg4_en4_qs;
 264:   logic mp_region_cfg4_en4_wd;
 265:   logic mp_region_cfg4_en4_we;
 266:   logic mp_region_cfg4_rd_en4_qs;
 267:   logic mp_region_cfg4_rd_en4_wd;
 268:   logic mp_region_cfg4_rd_en4_we;
 269:   logic mp_region_cfg4_prog_en4_qs;
 270:   logic mp_region_cfg4_prog_en4_wd;
 271:   logic mp_region_cfg4_prog_en4_we;
 272:   logic mp_region_cfg4_erase_en4_qs;
 273:   logic mp_region_cfg4_erase_en4_wd;
 274:   logic mp_region_cfg4_erase_en4_we;
 275:   logic [8:0] mp_region_cfg4_base4_qs;
 276:   logic [8:0] mp_region_cfg4_base4_wd;
 277:   logic mp_region_cfg4_base4_we;
 278:   logic [8:0] mp_region_cfg4_size4_qs;
 279:   logic [8:0] mp_region_cfg4_size4_wd;
 280:   logic mp_region_cfg4_size4_we;
 281:   logic mp_region_cfg5_en5_qs;
 282:   logic mp_region_cfg5_en5_wd;
 283:   logic mp_region_cfg5_en5_we;
 284:   logic mp_region_cfg5_rd_en5_qs;
 285:   logic mp_region_cfg5_rd_en5_wd;
 286:   logic mp_region_cfg5_rd_en5_we;
 287:   logic mp_region_cfg5_prog_en5_qs;
 288:   logic mp_region_cfg5_prog_en5_wd;
 289:   logic mp_region_cfg5_prog_en5_we;
 290:   logic mp_region_cfg5_erase_en5_qs;
 291:   logic mp_region_cfg5_erase_en5_wd;
 292:   logic mp_region_cfg5_erase_en5_we;
 293:   logic [8:0] mp_region_cfg5_base5_qs;
 294:   logic [8:0] mp_region_cfg5_base5_wd;
 295:   logic mp_region_cfg5_base5_we;
 296:   logic [8:0] mp_region_cfg5_size5_qs;
 297:   logic [8:0] mp_region_cfg5_size5_wd;
 298:   logic mp_region_cfg5_size5_we;
 299:   logic mp_region_cfg6_en6_qs;
 300:   logic mp_region_cfg6_en6_wd;
 301:   logic mp_region_cfg6_en6_we;
 302:   logic mp_region_cfg6_rd_en6_qs;
 303:   logic mp_region_cfg6_rd_en6_wd;
 304:   logic mp_region_cfg6_rd_en6_we;
 305:   logic mp_region_cfg6_prog_en6_qs;
 306:   logic mp_region_cfg6_prog_en6_wd;
 307:   logic mp_region_cfg6_prog_en6_we;
 308:   logic mp_region_cfg6_erase_en6_qs;
 309:   logic mp_region_cfg6_erase_en6_wd;
 310:   logic mp_region_cfg6_erase_en6_we;
 311:   logic [8:0] mp_region_cfg6_base6_qs;
 312:   logic [8:0] mp_region_cfg6_base6_wd;
 313:   logic mp_region_cfg6_base6_we;
 314:   logic [8:0] mp_region_cfg6_size6_qs;
 315:   logic [8:0] mp_region_cfg6_size6_wd;
 316:   logic mp_region_cfg6_size6_we;
 317:   logic mp_region_cfg7_en7_qs;
 318:   logic mp_region_cfg7_en7_wd;
 319:   logic mp_region_cfg7_en7_we;
 320:   logic mp_region_cfg7_rd_en7_qs;
 321:   logic mp_region_cfg7_rd_en7_wd;
 322:   logic mp_region_cfg7_rd_en7_we;
 323:   logic mp_region_cfg7_prog_en7_qs;
 324:   logic mp_region_cfg7_prog_en7_wd;
 325:   logic mp_region_cfg7_prog_en7_we;
 326:   logic mp_region_cfg7_erase_en7_qs;
 327:   logic mp_region_cfg7_erase_en7_wd;
 328:   logic mp_region_cfg7_erase_en7_we;
 329:   logic [8:0] mp_region_cfg7_base7_qs;
 330:   logic [8:0] mp_region_cfg7_base7_wd;
 331:   logic mp_region_cfg7_base7_we;
 332:   logic [8:0] mp_region_cfg7_size7_qs;
 333:   logic [8:0] mp_region_cfg7_size7_wd;
 334:   logic mp_region_cfg7_size7_we;
 335:   logic default_region_rd_en_qs;
 336:   logic default_region_rd_en_wd;
 337:   logic default_region_rd_en_we;
 338:   logic default_region_prog_en_qs;
 339:   logic default_region_prog_en_wd;
 340:   logic default_region_prog_en_we;
 341:   logic default_region_erase_en_qs;
 342:   logic default_region_erase_en_wd;
 343:   logic default_region_erase_en_we;
 344:   logic bank_cfg_regwen_qs;
 345:   logic bank_cfg_regwen_wd;
 346:   logic bank_cfg_regwen_we;
 347:   logic mp_bank_cfg_erase_en0_qs;
 348:   logic mp_bank_cfg_erase_en0_wd;
 349:   logic mp_bank_cfg_erase_en0_we;
 350:   logic mp_bank_cfg_erase_en1_qs;
 351:   logic mp_bank_cfg_erase_en1_wd;
 352:   logic mp_bank_cfg_erase_en1_we;
 353:   logic op_status_done_qs;
 354:   logic op_status_done_wd;
 355:   logic op_status_done_we;
 356:   logic op_status_err_qs;
 357:   logic op_status_err_wd;
 358:   logic op_status_err_we;
 359:   logic status_rd_full_qs;
 360:   logic status_rd_full_re;
 361:   logic status_rd_empty_qs;
 362:   logic status_rd_empty_re;
 363:   logic status_prog_full_qs;
 364:   logic status_prog_full_re;
 365:   logic status_prog_empty_qs;
 366:   logic status_prog_empty_re;
 367:   logic status_init_wip_qs;
 368:   logic status_init_wip_re;
 369:   logic [8:0] status_error_page_qs;
 370:   logic status_error_page_re;
 371:   logic status_error_bank_qs;
 372:   logic status_error_bank_re;
 373:   logic [31:0] scratch_qs;
 374:   logic [31:0] scratch_wd;
 375:   logic scratch_we;
 376:   logic [4:0] fifo_lvl_prog_qs;
 377:   logic [4:0] fifo_lvl_prog_wd;
 378:   logic fifo_lvl_prog_we;
 379:   logic [4:0] fifo_lvl_rd_qs;
 380:   logic [4:0] fifo_lvl_rd_wd;
 381:   logic fifo_lvl_rd_we;
 382: 
 383:   // Register instances
 384:   // R[intr_state]: V(False)
 385: 
 386:   //   F[prog_empty]: 0:0
 387:   prim_subreg #(
 388:     .DW      (1),
 389:     .SWACCESS("W1C"),
 390:     .RESVAL  (1'h0)
 391:   ) u_intr_state_prog_empty (
 392:     .clk_i   (clk_i    ),
 393:     .rst_ni  (rst_ni  ),
 394: 
 395:     // from register interface
 396:     .we     (intr_state_prog_empty_we),
 397:     .wd     (intr_state_prog_empty_wd),
 398: 
 399:     // from internal hardware
 400:     .de     (hw2reg.intr_state.prog_empty.de),
 401:     .d      (hw2reg.intr_state.prog_empty.d ),
 402: 
 403:     // to internal hardware
 404:     .qe     (),
 405:     .q      (reg2hw.intr_state.prog_empty.q ),
 406: 
 407:     // to register interface (read)
 408:     .qs     (intr_state_prog_empty_qs)
 409:   );
 410: 
 411: 
 412:   //   F[prog_lvl]: 1:1
 413:   prim_subreg #(
 414:     .DW      (1),
 415:     .SWACCESS("W1C"),
 416:     .RESVAL  (1'h0)
 417:   ) u_intr_state_prog_lvl (
 418:     .clk_i   (clk_i    ),
 419:     .rst_ni  (rst_ni  ),
 420: 
 421:     // from register interface
 422:     .we     (intr_state_prog_lvl_we),
 423:     .wd     (intr_state_prog_lvl_wd),
 424: 
 425:     // from internal hardware
 426:     .de     (hw2reg.intr_state.prog_lvl.de),
 427:     .d      (hw2reg.intr_state.prog_lvl.d ),
 428: 
 429:     // to internal hardware
 430:     .qe     (),
 431:     .q      (reg2hw.intr_state.prog_lvl.q ),
 432: 
 433:     // to register interface (read)
 434:     .qs     (intr_state_prog_lvl_qs)
 435:   );
 436: 
 437: 
 438:   //   F[rd_full]: 2:2
 439:   prim_subreg #(
 440:     .DW      (1),
 441:     .SWACCESS("W1C"),
 442:     .RESVAL  (1'h0)
 443:   ) u_intr_state_rd_full (
 444:     .clk_i   (clk_i    ),
 445:     .rst_ni  (rst_ni  ),
 446: 
 447:     // from register interface
 448:     .we     (intr_state_rd_full_we),
 449:     .wd     (intr_state_rd_full_wd),
 450: 
 451:     // from internal hardware
 452:     .de     (hw2reg.intr_state.rd_full.de),
 453:     .d      (hw2reg.intr_state.rd_full.d ),
 454: 
 455:     // to internal hardware
 456:     .qe     (),
 457:     .q      (reg2hw.intr_state.rd_full.q ),
 458: 
 459:     // to register interface (read)
 460:     .qs     (intr_state_rd_full_qs)
 461:   );
 462: 
 463: 
 464:   //   F[rd_lvl]: 3:3
 465:   prim_subreg #(
 466:     .DW      (1),
 467:     .SWACCESS("W1C"),
 468:     .RESVAL  (1'h0)
 469:   ) u_intr_state_rd_lvl (
 470:     .clk_i   (clk_i    ),
 471:     .rst_ni  (rst_ni  ),
 472: 
 473:     // from register interface
 474:     .we     (intr_state_rd_lvl_we),
 475:     .wd     (intr_state_rd_lvl_wd),
 476: 
 477:     // from internal hardware
 478:     .de     (hw2reg.intr_state.rd_lvl.de),
 479:     .d      (hw2reg.intr_state.rd_lvl.d ),
 480: 
 481:     // to internal hardware
 482:     .qe     (),
 483:     .q      (reg2hw.intr_state.rd_lvl.q ),
 484: 
 485:     // to register interface (read)
 486:     .qs     (intr_state_rd_lvl_qs)
 487:   );
 488: 
 489: 
 490:   //   F[op_done]: 4:4
 491:   prim_subreg #(
 492:     .DW      (1),
 493:     .SWACCESS("W1C"),
 494:     .RESVAL  (1'h0)
 495:   ) u_intr_state_op_done (
 496:     .clk_i   (clk_i    ),
 497:     .rst_ni  (rst_ni  ),
 498: 
 499:     // from register interface
 500:     .we     (intr_state_op_done_we),
 501:     .wd     (intr_state_op_done_wd),
 502: 
 503:     // from internal hardware
 504:     .de     (hw2reg.intr_state.op_done.de),
 505:     .d      (hw2reg.intr_state.op_done.d ),
 506: 
 507:     // to internal hardware
 508:     .qe     (),
 509:     .q      (reg2hw.intr_state.op_done.q ),
 510: 
 511:     // to register interface (read)
 512:     .qs     (intr_state_op_done_qs)
 513:   );
 514: 
 515: 
 516:   //   F[op_error]: 5:5
 517:   prim_subreg #(
 518:     .DW      (1),
 519:     .SWACCESS("W1C"),
 520:     .RESVAL  (1'h0)
 521:   ) u_intr_state_op_error (
 522:     .clk_i   (clk_i    ),
 523:     .rst_ni  (rst_ni  ),
 524: 
 525:     // from register interface
 526:     .we     (intr_state_op_error_we),
 527:     .wd     (intr_state_op_error_wd),
 528: 
 529:     // from internal hardware
 530:     .de     (hw2reg.intr_state.op_error.de),
 531:     .d      (hw2reg.intr_state.op_error.d ),
 532: 
 533:     // to internal hardware
 534:     .qe     (),
 535:     .q      (reg2hw.intr_state.op_error.q ),
 536: 
 537:     // to register interface (read)
 538:     .qs     (intr_state_op_error_qs)
 539:   );
 540: 
 541: 
 542:   // R[intr_enable]: V(False)
 543: 
 544:   //   F[prog_empty]: 0:0
 545:   prim_subreg #(
 546:     .DW      (1),
 547:     .SWACCESS("RW"),
 548:     .RESVAL  (1'h0)
 549:   ) u_intr_enable_prog_empty (
 550:     .clk_i   (clk_i    ),
 551:     .rst_ni  (rst_ni  ),
 552: 
 553:     // from register interface
 554:     .we     (intr_enable_prog_empty_we),
 555:     .wd     (intr_enable_prog_empty_wd),
 556: 
 557:     // from internal hardware
 558:     .de     (1'b0),
 559:     .d      ('0  ),
 560: 
 561:     // to internal hardware
 562:     .qe     (),
 563:     .q      (reg2hw.intr_enable.prog_empty.q ),
 564: 
 565:     // to register interface (read)
 566:     .qs     (intr_enable_prog_empty_qs)
 567:   );
 568: 
 569: 
 570:   //   F[prog_lvl]: 1:1
 571:   prim_subreg #(
 572:     .DW      (1),
 573:     .SWACCESS("RW"),
 574:     .RESVAL  (1'h0)
 575:   ) u_intr_enable_prog_lvl (
 576:     .clk_i   (clk_i    ),
 577:     .rst_ni  (rst_ni  ),
 578: 
 579:     // from register interface
 580:     .we     (intr_enable_prog_lvl_we),
 581:     .wd     (intr_enable_prog_lvl_wd),
 582: 
 583:     // from internal hardware
 584:     .de     (1'b0),
 585:     .d      ('0  ),
 586: 
 587:     // to internal hardware
 588:     .qe     (),
 589:     .q      (reg2hw.intr_enable.prog_lvl.q ),
 590: 
 591:     // to register interface (read)
 592:     .qs     (intr_enable_prog_lvl_qs)
 593:   );
 594: 
 595: 
 596:   //   F[rd_full]: 2:2
 597:   prim_subreg #(
 598:     .DW      (1),
 599:     .SWACCESS("RW"),
 600:     .RESVAL  (1'h0)
 601:   ) u_intr_enable_rd_full (
 602:     .clk_i   (clk_i    ),
 603:     .rst_ni  (rst_ni  ),
 604: 
 605:     // from register interface
 606:     .we     (intr_enable_rd_full_we),
 607:     .wd     (intr_enable_rd_full_wd),
 608: 
 609:     // from internal hardware
 610:     .de     (1'b0),
 611:     .d      ('0  ),
 612: 
 613:     // to internal hardware
 614:     .qe     (),
 615:     .q      (reg2hw.intr_enable.rd_full.q ),
 616: 
 617:     // to register interface (read)
 618:     .qs     (intr_enable_rd_full_qs)
 619:   );
 620: 
 621: 
 622:   //   F[rd_lvl]: 3:3
 623:   prim_subreg #(
 624:     .DW      (1),
 625:     .SWACCESS("RW"),
 626:     .RESVAL  (1'h0)
 627:   ) u_intr_enable_rd_lvl (
 628:     .clk_i   (clk_i    ),
 629:     .rst_ni  (rst_ni  ),
 630: 
 631:     // from register interface
 632:     .we     (intr_enable_rd_lvl_we),
 633:     .wd     (intr_enable_rd_lvl_wd),
 634: 
 635:     // from internal hardware
 636:     .de     (1'b0),
 637:     .d      ('0  ),
 638: 
 639:     // to internal hardware
 640:     .qe     (),
 641:     .q      (reg2hw.intr_enable.rd_lvl.q ),
 642: 
 643:     // to register interface (read)
 644:     .qs     (intr_enable_rd_lvl_qs)
 645:   );
 646: 
 647: 
 648:   //   F[op_done]: 4:4
 649:   prim_subreg #(
 650:     .DW      (1),
 651:     .SWACCESS("RW"),
 652:     .RESVAL  (1'h0)
 653:   ) u_intr_enable_op_done (
 654:     .clk_i   (clk_i    ),
 655:     .rst_ni  (rst_ni  ),
 656: 
 657:     // from register interface
 658:     .we     (intr_enable_op_done_we),
 659:     .wd     (intr_enable_op_done_wd),
 660: 
 661:     // from internal hardware
 662:     .de     (1'b0),
 663:     .d      ('0  ),
 664: 
 665:     // to internal hardware
 666:     .qe     (),
 667:     .q      (reg2hw.intr_enable.op_done.q ),
 668: 
 669:     // to register interface (read)
 670:     .qs     (intr_enable_op_done_qs)
 671:   );
 672: 
 673: 
 674:   //   F[op_error]: 5:5
 675:   prim_subreg #(
 676:     .DW      (1),
 677:     .SWACCESS("RW"),
 678:     .RESVAL  (1'h0)
 679:   ) u_intr_enable_op_error (
 680:     .clk_i   (clk_i    ),
 681:     .rst_ni  (rst_ni  ),
 682: 
 683:     // from register interface
 684:     .we     (intr_enable_op_error_we),
 685:     .wd     (intr_enable_op_error_wd),
 686: 
 687:     // from internal hardware
 688:     .de     (1'b0),
 689:     .d      ('0  ),
 690: 
 691:     // to internal hardware
 692:     .qe     (),
 693:     .q      (reg2hw.intr_enable.op_error.q ),
 694: 
 695:     // to register interface (read)
 696:     .qs     (intr_enable_op_error_qs)
 697:   );
 698: 
 699: 
 700:   // R[intr_test]: V(True)
 701: 
 702:   //   F[prog_empty]: 0:0
 703:   prim_subreg_ext #(
 704:     .DW    (1)
 705:   ) u_intr_test_prog_empty (
 706:     .re     (1'b0),
 707:     .we     (intr_test_prog_empty_we),
 708:     .wd     (intr_test_prog_empty_wd),
 709:     .d      ('0),
 710:     .qre    (),
 711:     .qe     (reg2hw.intr_test.prog_empty.qe),
 712:     .q      (reg2hw.intr_test.prog_empty.q ),
 713:     .qs     ()
 714:   );
 715: 
 716: 
 717:   //   F[prog_lvl]: 1:1
 718:   prim_subreg_ext #(
 719:     .DW    (1)
 720:   ) u_intr_test_prog_lvl (
 721:     .re     (1'b0),
 722:     .we     (intr_test_prog_lvl_we),
 723:     .wd     (intr_test_prog_lvl_wd),
 724:     .d      ('0),
 725:     .qre    (),
 726:     .qe     (reg2hw.intr_test.prog_lvl.qe),
 727:     .q      (reg2hw.intr_test.prog_lvl.q ),
 728:     .qs     ()
 729:   );
 730: 
 731: 
 732:   //   F[rd_full]: 2:2
 733:   prim_subreg_ext #(
 734:     .DW    (1)
 735:   ) u_intr_test_rd_full (
 736:     .re     (1'b0),
 737:     .we     (intr_test_rd_full_we),
 738:     .wd     (intr_test_rd_full_wd),
 739:     .d      ('0),
 740:     .qre    (),
 741:     .qe     (reg2hw.intr_test.rd_full.qe),
 742:     .q      (reg2hw.intr_test.rd_full.q ),
 743:     .qs     ()
 744:   );
 745: 
 746: 
 747:   //   F[rd_lvl]: 3:3
 748:   prim_subreg_ext #(
 749:     .DW    (1)
 750:   ) u_intr_test_rd_lvl (
 751:     .re     (1'b0),
 752:     .we     (intr_test_rd_lvl_we),
 753:     .wd     (intr_test_rd_lvl_wd),
 754:     .d      ('0),
 755:     .qre    (),
 756:     .qe     (reg2hw.intr_test.rd_lvl.qe),
 757:     .q      (reg2hw.intr_test.rd_lvl.q ),
 758:     .qs     ()
 759:   );
 760: 
 761: 
 762:   //   F[op_done]: 4:4
 763:   prim_subreg_ext #(
 764:     .DW    (1)
 765:   ) u_intr_test_op_done (
 766:     .re     (1'b0),
 767:     .we     (intr_test_op_done_we),
 768:     .wd     (intr_test_op_done_wd),
 769:     .d      ('0),
 770:     .qre    (),
 771:     .qe     (reg2hw.intr_test.op_done.qe),
 772:     .q      (reg2hw.intr_test.op_done.q ),
 773:     .qs     ()
 774:   );
 775: 
 776: 
 777:   //   F[op_error]: 5:5
 778:   prim_subreg_ext #(
 779:     .DW    (1)
 780:   ) u_intr_test_op_error (
 781:     .re     (1'b0),
 782:     .we     (intr_test_op_error_we),
 783:     .wd     (intr_test_op_error_wd),
 784:     .d      ('0),
 785:     .qre    (),
 786:     .qe     (reg2hw.intr_test.op_error.qe),
 787:     .q      (reg2hw.intr_test.op_error.q ),
 788:     .qs     ()
 789:   );
 790: 
 791: 
 792:   // R[control]: V(False)
 793: 
 794:   //   F[start]: 0:0
 795:   prim_subreg #(
 796:     .DW      (1),
 797:     .SWACCESS("RW"),
 798:     .RESVAL  (1'h0)
 799:   ) u_control_start (
 800:     .clk_i   (clk_i    ),
 801:     .rst_ni  (rst_ni  ),
 802: 
 803:     // from register interface
 804:     .we     (control_start_we),
 805:     .wd     (control_start_wd),
 806: 
 807:     // from internal hardware
 808:     .de     (hw2reg.control.start.de),
 809:     .d      (hw2reg.control.start.d ),
 810: 
 811:     // to internal hardware
 812:     .qe     (),
 813:     .q      (reg2hw.control.start.q ),
 814: 
 815:     // to register interface (read)
 816:     .qs     (control_start_qs)
 817:   );
 818: 
 819: 
 820:   //   F[op]: 5:4
 821:   prim_subreg #(
 822:     .DW      (2),
 823:     .SWACCESS("RW"),
 824:     .RESVAL  (2'h0)
 825:   ) u_control_op (
 826:     .clk_i   (clk_i    ),
 827:     .rst_ni  (rst_ni  ),
 828: 
 829:     // from register interface
 830:     .we     (control_op_we),
 831:     .wd     (control_op_wd),
 832: 
 833:     // from internal hardware
 834:     .de     (1'b0),
 835:     .d      ('0  ),
 836: 
 837:     // to internal hardware
 838:     .qe     (),
 839:     .q      (reg2hw.control.op.q ),
 840: 
 841:     // to register interface (read)
 842:     .qs     (control_op_qs)
 843:   );
 844: 
 845: 
 846:   //   F[erase_sel]: 6:6
 847:   prim_subreg #(
 848:     .DW      (1),
 849:     .SWACCESS("RW"),
 850:     .RESVAL  (1'h0)
 851:   ) u_control_erase_sel (
 852:     .clk_i   (clk_i    ),
 853:     .rst_ni  (rst_ni  ),
 854: 
 855:     // from register interface
 856:     .we     (control_erase_sel_we),
 857:     .wd     (control_erase_sel_wd),
 858: 
 859:     // from internal hardware
 860:     .de     (1'b0),
 861:     .d      ('0  ),
 862: 
 863:     // to internal hardware
 864:     .qe     (),
 865:     .q      (reg2hw.control.erase_sel.q ),
 866: 
 867:     // to register interface (read)
 868:     .qs     (control_erase_sel_qs)
 869:   );
 870: 
 871: 
 872:   //   F[fifo_rst]: 7:7
 873:   prim_subreg #(
 874:     .DW      (1),
 875:     .SWACCESS("RW"),
 876:     .RESVAL  (1'h0)
 877:   ) u_control_fifo_rst (
 878:     .clk_i   (clk_i    ),
 879:     .rst_ni  (rst_ni  ),
 880: 
 881:     // from register interface
 882:     .we     (control_fifo_rst_we),
 883:     .wd     (control_fifo_rst_wd),
 884: 
 885:     // from internal hardware
 886:     .de     (1'b0),
 887:     .d      ('0  ),
 888: 
 889:     // to internal hardware
 890:     .qe     (),
 891:     .q      (reg2hw.control.fifo_rst.q ),
 892: 
 893:     // to register interface (read)
 894:     .qs     (control_fifo_rst_qs)
 895:   );
 896: 
 897: 
 898:   //   F[num]: 27:16
 899:   prim_subreg #(
 900:     .DW      (12),
 901:     .SWACCESS("RW"),
 902:     .RESVAL  (12'h0)
 903:   ) u_control_num (
 904:     .clk_i   (clk_i    ),
 905:     .rst_ni  (rst_ni  ),
 906: 
 907:     // from register interface
 908:     .we     (control_num_we),
 909:     .wd     (control_num_wd),
 910: 
 911:     // from internal hardware
 912:     .de     (1'b0),
 913:     .d      ('0  ),
 914: 
 915:     // to internal hardware
 916:     .qe     (),
 917:     .q      (reg2hw.control.num.q ),
 918: 
 919:     // to register interface (read)
 920:     .qs     (control_num_qs)
 921:   );
 922: 
 923: 
 924:   // R[addr]: V(False)
 925: 
 926:   prim_subreg #(
 927:     .DW      (32),
 928:     .SWACCESS("RW"),
 929:     .RESVAL  (32'h0)
 930:   ) u_addr (
 931:     .clk_i   (clk_i    ),
 932:     .rst_ni  (rst_ni  ),
 933: 
 934:     // from register interface
 935:     .we     (addr_we),
 936:     .wd     (addr_wd),
 937: 
 938:     // from internal hardware
 939:     .de     (1'b0),
 940:     .d      ('0  ),
 941: 
 942:     // to internal hardware
 943:     .qe     (),
 944:     .q      (reg2hw.addr.q ),
 945: 
 946:     // to register interface (read)
 947:     .qs     (addr_qs)
 948:   );
 949: 
 950: 
 951:   // R[region_cfg_regwen]: V(False)
 952: 
 953:   prim_subreg #(
 954:     .DW      (1),
 955:     .SWACCESS("W0C"),
 956:     .RESVAL  (1'h1)
 957:   ) u_region_cfg_regwen (
 958:     .clk_i   (clk_i    ),
 959:     .rst_ni  (rst_ni  ),
 960: 
 961:     // from register interface
 962:     .we     (region_cfg_regwen_we),
 963:     .wd     (region_cfg_regwen_wd),
 964: 
 965:     // from internal hardware
 966:     .de     (1'b0),
 967:     .d      ('0  ),
 968: 
 969:     // to internal hardware
 970:     .qe     (),
 971:     .q      (),
 972: 
 973:     // to register interface (read)
 974:     .qs     (region_cfg_regwen_qs)
 975:   );
 976: 
 977: 
 978: 
 979:   // Subregister 0 of Multireg mp_region_cfg
 980:   // R[mp_region_cfg0]: V(False)
 981: 
 982:   // F[en0]: 0:0
 983:   prim_subreg #(
 984:     .DW      (1),
 985:     .SWACCESS("RW"),
 986:     .RESVAL  (1'h0)
 987:   ) u_mp_region_cfg0_en0 (
 988:     .clk_i   (clk_i    ),
 989:     .rst_ni  (rst_ni  ),
 990: 
 991:     // from register interface (qualified with register enable)
 992:     .we     (mp_region_cfg0_en0_we & region_cfg_regwen_qs),
 993:     .wd     (mp_region_cfg0_en0_wd),
 994: 
 995:     // from internal hardware
 996:     .de     (1'b0),
 997:     .d      ('0  ),
 998: 
 999:     // to internal hardware
1000:     .qe     (),
1001:     .q      (reg2hw.mp_region_cfg[0].en.q ),
1002: 
1003:     // to register interface (read)
1004:     .qs     (mp_region_cfg0_en0_qs)
1005:   );
1006: 
1007: 
1008:   // F[rd_en0]: 1:1
1009:   prim_subreg #(
1010:     .DW      (1),
1011:     .SWACCESS("RW"),
1012:     .RESVAL  (1'h0)
1013:   ) u_mp_region_cfg0_rd_en0 (
1014:     .clk_i   (clk_i    ),
1015:     .rst_ni  (rst_ni  ),
1016: 
1017:     // from register interface (qualified with register enable)
1018:     .we     (mp_region_cfg0_rd_en0_we & region_cfg_regwen_qs),
1019:     .wd     (mp_region_cfg0_rd_en0_wd),
1020: 
1021:     // from internal hardware
1022:     .de     (1'b0),
1023:     .d      ('0  ),
1024: 
1025:     // to internal hardware
1026:     .qe     (),
1027:     .q      (reg2hw.mp_region_cfg[0].rd_en.q ),
1028: 
1029:     // to register interface (read)
1030:     .qs     (mp_region_cfg0_rd_en0_qs)
1031:   );
1032: 
1033: 
1034:   // F[prog_en0]: 2:2
1035:   prim_subreg #(
1036:     .DW      (1),
1037:     .SWACCESS("RW"),
1038:     .RESVAL  (1'h0)
1039:   ) u_mp_region_cfg0_prog_en0 (
1040:     .clk_i   (clk_i    ),
1041:     .rst_ni  (rst_ni  ),
1042: 
1043:     // from register interface (qualified with register enable)
1044:     .we     (mp_region_cfg0_prog_en0_we & region_cfg_regwen_qs),
1045:     .wd     (mp_region_cfg0_prog_en0_wd),
1046: 
1047:     // from internal hardware
1048:     .de     (1'b0),
1049:     .d      ('0  ),
1050: 
1051:     // to internal hardware
1052:     .qe     (),
1053:     .q      (reg2hw.mp_region_cfg[0].prog_en.q ),
1054: 
1055:     // to register interface (read)
1056:     .qs     (mp_region_cfg0_prog_en0_qs)
1057:   );
1058: 
1059: 
1060:   // F[erase_en0]: 3:3
1061:   prim_subreg #(
1062:     .DW      (1),
1063:     .SWACCESS("RW"),
1064:     .RESVAL  (1'h0)
1065:   ) u_mp_region_cfg0_erase_en0 (
1066:     .clk_i   (clk_i    ),
1067:     .rst_ni  (rst_ni  ),
1068: 
1069:     // from register interface (qualified with register enable)
1070:     .we     (mp_region_cfg0_erase_en0_we & region_cfg_regwen_qs),
1071:     .wd     (mp_region_cfg0_erase_en0_wd),
1072: 
1073:     // from internal hardware
1074:     .de     (1'b0),
1075:     .d      ('0  ),
1076: 
1077:     // to internal hardware
1078:     .qe     (),
1079:     .q      (reg2hw.mp_region_cfg[0].erase_en.q ),
1080: 
1081:     // to register interface (read)
1082:     .qs     (mp_region_cfg0_erase_en0_qs)
1083:   );
1084: 
1085: 
1086:   // F[base0]: 12:4
1087:   prim_subreg #(
1088:     .DW      (9),
1089:     .SWACCESS("RW"),
1090:     .RESVAL  (9'h0)
1091:   ) u_mp_region_cfg0_base0 (
1092:     .clk_i   (clk_i    ),
1093:     .rst_ni  (rst_ni  ),
1094: 
1095:     // from register interface (qualified with register enable)
1096:     .we     (mp_region_cfg0_base0_we & region_cfg_regwen_qs),
1097:     .wd     (mp_region_cfg0_base0_wd),
1098: 
1099:     // from internal hardware
1100:     .de     (1'b0),
1101:     .d      ('0  ),
1102: 
1103:     // to internal hardware
1104:     .qe     (),
1105:     .q      (reg2hw.mp_region_cfg[0].base.q ),
1106: 
1107:     // to register interface (read)
1108:     .qs     (mp_region_cfg0_base0_qs)
1109:   );
1110: 
1111: 
1112:   // F[size0]: 24:16
1113:   prim_subreg #(
1114:     .DW      (9),
1115:     .SWACCESS("RW"),
1116:     .RESVAL  (9'h0)
1117:   ) u_mp_region_cfg0_size0 (
1118:     .clk_i   (clk_i    ),
1119:     .rst_ni  (rst_ni  ),
1120: 
1121:     // from register interface (qualified with register enable)
1122:     .we     (mp_region_cfg0_size0_we & region_cfg_regwen_qs),
1123:     .wd     (mp_region_cfg0_size0_wd),
1124: 
1125:     // from internal hardware
1126:     .de     (1'b0),
1127:     .d      ('0  ),
1128: 
1129:     // to internal hardware
1130:     .qe     (),
1131:     .q      (reg2hw.mp_region_cfg[0].size.q ),
1132: 
1133:     // to register interface (read)
1134:     .qs     (mp_region_cfg0_size0_qs)
1135:   );
1136: 
1137: 
1138:   // Subregister 1 of Multireg mp_region_cfg
1139:   // R[mp_region_cfg1]: V(False)
1140: 
1141:   // F[en1]: 0:0
1142:   prim_subreg #(
1143:     .DW      (1),
1144:     .SWACCESS("RW"),
1145:     .RESVAL  (1'h0)
1146:   ) u_mp_region_cfg1_en1 (
1147:     .clk_i   (clk_i    ),
1148:     .rst_ni  (rst_ni  ),
1149: 
1150:     // from register interface (qualified with register enable)
1151:     .we     (mp_region_cfg1_en1_we & region_cfg_regwen_qs),
1152:     .wd     (mp_region_cfg1_en1_wd),
1153: 
1154:     // from internal hardware
1155:     .de     (1'b0),
1156:     .d      ('0  ),
1157: 
1158:     // to internal hardware
1159:     .qe     (),
1160:     .q      (reg2hw.mp_region_cfg[1].en.q ),
1161: 
1162:     // to register interface (read)
1163:     .qs     (mp_region_cfg1_en1_qs)
1164:   );
1165: 
1166: 
1167:   // F[rd_en1]: 1:1
1168:   prim_subreg #(
1169:     .DW      (1),
1170:     .SWACCESS("RW"),
1171:     .RESVAL  (1'h0)
1172:   ) u_mp_region_cfg1_rd_en1 (
1173:     .clk_i   (clk_i    ),
1174:     .rst_ni  (rst_ni  ),
1175: 
1176:     // from register interface (qualified with register enable)
1177:     .we     (mp_region_cfg1_rd_en1_we & region_cfg_regwen_qs),
1178:     .wd     (mp_region_cfg1_rd_en1_wd),
1179: 
1180:     // from internal hardware
1181:     .de     (1'b0),
1182:     .d      ('0  ),
1183: 
1184:     // to internal hardware
1185:     .qe     (),
1186:     .q      (reg2hw.mp_region_cfg[1].rd_en.q ),
1187: 
1188:     // to register interface (read)
1189:     .qs     (mp_region_cfg1_rd_en1_qs)
1190:   );
1191: 
1192: 
1193:   // F[prog_en1]: 2:2
1194:   prim_subreg #(
1195:     .DW      (1),
1196:     .SWACCESS("RW"),
1197:     .RESVAL  (1'h0)
1198:   ) u_mp_region_cfg1_prog_en1 (
1199:     .clk_i   (clk_i    ),
1200:     .rst_ni  (rst_ni  ),
1201: 
1202:     // from register interface (qualified with register enable)
1203:     .we     (mp_region_cfg1_prog_en1_we & region_cfg_regwen_qs),
1204:     .wd     (mp_region_cfg1_prog_en1_wd),
1205: 
1206:     // from internal hardware
1207:     .de     (1'b0),
1208:     .d      ('0  ),
1209: 
1210:     // to internal hardware
1211:     .qe     (),
1212:     .q      (reg2hw.mp_region_cfg[1].prog_en.q ),
1213: 
1214:     // to register interface (read)
1215:     .qs     (mp_region_cfg1_prog_en1_qs)
1216:   );
1217: 
1218: 
1219:   // F[erase_en1]: 3:3
1220:   prim_subreg #(
1221:     .DW      (1),
1222:     .SWACCESS("RW"),
1223:     .RESVAL  (1'h0)
1224:   ) u_mp_region_cfg1_erase_en1 (
1225:     .clk_i   (clk_i    ),
1226:     .rst_ni  (rst_ni  ),
1227: 
1228:     // from register interface (qualified with register enable)
1229:     .we     (mp_region_cfg1_erase_en1_we & region_cfg_regwen_qs),
1230:     .wd     (mp_region_cfg1_erase_en1_wd),
1231: 
1232:     // from internal hardware
1233:     .de     (1'b0),
1234:     .d      ('0  ),
1235: 
1236:     // to internal hardware
1237:     .qe     (),
1238:     .q      (reg2hw.mp_region_cfg[1].erase_en.q ),
1239: 
1240:     // to register interface (read)
1241:     .qs     (mp_region_cfg1_erase_en1_qs)
1242:   );
1243: 
1244: 
1245:   // F[base1]: 12:4
1246:   prim_subreg #(
1247:     .DW      (9),
1248:     .SWACCESS("RW"),
1249:     .RESVAL  (9'h0)
1250:   ) u_mp_region_cfg1_base1 (
1251:     .clk_i   (clk_i    ),
1252:     .rst_ni  (rst_ni  ),
1253: 
1254:     // from register interface (qualified with register enable)
1255:     .we     (mp_region_cfg1_base1_we & region_cfg_regwen_qs),
1256:     .wd     (mp_region_cfg1_base1_wd),
1257: 
1258:     // from internal hardware
1259:     .de     (1'b0),
1260:     .d      ('0  ),
1261: 
1262:     // to internal hardware
1263:     .qe     (),
1264:     .q      (reg2hw.mp_region_cfg[1].base.q ),
1265: 
1266:     // to register interface (read)
1267:     .qs     (mp_region_cfg1_base1_qs)
1268:   );
1269: 
1270: 
1271:   // F[size1]: 24:16
1272:   prim_subreg #(
1273:     .DW      (9),
1274:     .SWACCESS("RW"),
1275:     .RESVAL  (9'h0)
1276:   ) u_mp_region_cfg1_size1 (
1277:     .clk_i   (clk_i    ),
1278:     .rst_ni  (rst_ni  ),
1279: 
1280:     // from register interface (qualified with register enable)
1281:     .we     (mp_region_cfg1_size1_we & region_cfg_regwen_qs),
1282:     .wd     (mp_region_cfg1_size1_wd),
1283: 
1284:     // from internal hardware
1285:     .de     (1'b0),
1286:     .d      ('0  ),
1287: 
1288:     // to internal hardware
1289:     .qe     (),
1290:     .q      (reg2hw.mp_region_cfg[1].size.q ),
1291: 
1292:     // to register interface (read)
1293:     .qs     (mp_region_cfg1_size1_qs)
1294:   );
1295: 
1296: 
1297:   // Subregister 2 of Multireg mp_region_cfg
1298:   // R[mp_region_cfg2]: V(False)
1299: 
1300:   // F[en2]: 0:0
1301:   prim_subreg #(
1302:     .DW      (1),
1303:     .SWACCESS("RW"),
1304:     .RESVAL  (1'h0)
1305:   ) u_mp_region_cfg2_en2 (
1306:     .clk_i   (clk_i    ),
1307:     .rst_ni  (rst_ni  ),
1308: 
1309:     // from register interface (qualified with register enable)
1310:     .we     (mp_region_cfg2_en2_we & region_cfg_regwen_qs),
1311:     .wd     (mp_region_cfg2_en2_wd),
1312: 
1313:     // from internal hardware
1314:     .de     (1'b0),
1315:     .d      ('0  ),
1316: 
1317:     // to internal hardware
1318:     .qe     (),
1319:     .q      (reg2hw.mp_region_cfg[2].en.q ),
1320: 
1321:     // to register interface (read)
1322:     .qs     (mp_region_cfg2_en2_qs)
1323:   );
1324: 
1325: 
1326:   // F[rd_en2]: 1:1
1327:   prim_subreg #(
1328:     .DW      (1),
1329:     .SWACCESS("RW"),
1330:     .RESVAL  (1'h0)
1331:   ) u_mp_region_cfg2_rd_en2 (
1332:     .clk_i   (clk_i    ),
1333:     .rst_ni  (rst_ni  ),
1334: 
1335:     // from register interface (qualified with register enable)
1336:     .we     (mp_region_cfg2_rd_en2_we & region_cfg_regwen_qs),
1337:     .wd     (mp_region_cfg2_rd_en2_wd),
1338: 
1339:     // from internal hardware
1340:     .de     (1'b0),
1341:     .d      ('0  ),
1342: 
1343:     // to internal hardware
1344:     .qe     (),
1345:     .q      (reg2hw.mp_region_cfg[2].rd_en.q ),
1346: 
1347:     // to register interface (read)
1348:     .qs     (mp_region_cfg2_rd_en2_qs)
1349:   );
1350: 
1351: 
1352:   // F[prog_en2]: 2:2
1353:   prim_subreg #(
1354:     .DW      (1),
1355:     .SWACCESS("RW"),
1356:     .RESVAL  (1'h0)
1357:   ) u_mp_region_cfg2_prog_en2 (
1358:     .clk_i   (clk_i    ),
1359:     .rst_ni  (rst_ni  ),
1360: 
1361:     // from register interface (qualified with register enable)
1362:     .we     (mp_region_cfg2_prog_en2_we & region_cfg_regwen_qs),
1363:     .wd     (mp_region_cfg2_prog_en2_wd),
1364: 
1365:     // from internal hardware
1366:     .de     (1'b0),
1367:     .d      ('0  ),
1368: 
1369:     // to internal hardware
1370:     .qe     (),
1371:     .q      (reg2hw.mp_region_cfg[2].prog_en.q ),
1372: 
1373:     // to register interface (read)
1374:     .qs     (mp_region_cfg2_prog_en2_qs)
1375:   );
1376: 
1377: 
1378:   // F[erase_en2]: 3:3
1379:   prim_subreg #(
1380:     .DW      (1),
1381:     .SWACCESS("RW"),
1382:     .RESVAL  (1'h0)
1383:   ) u_mp_region_cfg2_erase_en2 (
1384:     .clk_i   (clk_i    ),
1385:     .rst_ni  (rst_ni  ),
1386: 
1387:     // from register interface (qualified with register enable)
1388:     .we     (mp_region_cfg2_erase_en2_we & region_cfg_regwen_qs),
1389:     .wd     (mp_region_cfg2_erase_en2_wd),
1390: 
1391:     // from internal hardware
1392:     .de     (1'b0),
1393:     .d      ('0  ),
1394: 
1395:     // to internal hardware
1396:     .qe     (),
1397:     .q      (reg2hw.mp_region_cfg[2].erase_en.q ),
1398: 
1399:     // to register interface (read)
1400:     .qs     (mp_region_cfg2_erase_en2_qs)
1401:   );
1402: 
1403: 
1404:   // F[base2]: 12:4
1405:   prim_subreg #(
1406:     .DW      (9),
1407:     .SWACCESS("RW"),
1408:     .RESVAL  (9'h0)
1409:   ) u_mp_region_cfg2_base2 (
1410:     .clk_i   (clk_i    ),
1411:     .rst_ni  (rst_ni  ),
1412: 
1413:     // from register interface (qualified with register enable)
1414:     .we     (mp_region_cfg2_base2_we & region_cfg_regwen_qs),
1415:     .wd     (mp_region_cfg2_base2_wd),
1416: 
1417:     // from internal hardware
1418:     .de     (1'b0),
1419:     .d      ('0  ),
1420: 
1421:     // to internal hardware
1422:     .qe     (),
1423:     .q      (reg2hw.mp_region_cfg[2].base.q ),
1424: 
1425:     // to register interface (read)
1426:     .qs     (mp_region_cfg2_base2_qs)
1427:   );
1428: 
1429: 
1430:   // F[size2]: 24:16
1431:   prim_subreg #(
1432:     .DW      (9),
1433:     .SWACCESS("RW"),
1434:     .RESVAL  (9'h0)
1435:   ) u_mp_region_cfg2_size2 (
1436:     .clk_i   (clk_i    ),
1437:     .rst_ni  (rst_ni  ),
1438: 
1439:     // from register interface (qualified with register enable)
1440:     .we     (mp_region_cfg2_size2_we & region_cfg_regwen_qs),
1441:     .wd     (mp_region_cfg2_size2_wd),
1442: 
1443:     // from internal hardware
1444:     .de     (1'b0),
1445:     .d      ('0  ),
1446: 
1447:     // to internal hardware
1448:     .qe     (),
1449:     .q      (reg2hw.mp_region_cfg[2].size.q ),
1450: 
1451:     // to register interface (read)
1452:     .qs     (mp_region_cfg2_size2_qs)
1453:   );
1454: 
1455: 
1456:   // Subregister 3 of Multireg mp_region_cfg
1457:   // R[mp_region_cfg3]: V(False)
1458: 
1459:   // F[en3]: 0:0
1460:   prim_subreg #(
1461:     .DW      (1),
1462:     .SWACCESS("RW"),
1463:     .RESVAL  (1'h0)
1464:   ) u_mp_region_cfg3_en3 (
1465:     .clk_i   (clk_i    ),
1466:     .rst_ni  (rst_ni  ),
1467: 
1468:     // from register interface (qualified with register enable)
1469:     .we     (mp_region_cfg3_en3_we & region_cfg_regwen_qs),
1470:     .wd     (mp_region_cfg3_en3_wd),
1471: 
1472:     // from internal hardware
1473:     .de     (1'b0),
1474:     .d      ('0  ),
1475: 
1476:     // to internal hardware
1477:     .qe     (),
1478:     .q      (reg2hw.mp_region_cfg[3].en.q ),
1479: 
1480:     // to register interface (read)
1481:     .qs     (mp_region_cfg3_en3_qs)
1482:   );
1483: 
1484: 
1485:   // F[rd_en3]: 1:1
1486:   prim_subreg #(
1487:     .DW      (1),
1488:     .SWACCESS("RW"),
1489:     .RESVAL  (1'h0)
1490:   ) u_mp_region_cfg3_rd_en3 (
1491:     .clk_i   (clk_i    ),
1492:     .rst_ni  (rst_ni  ),
1493: 
1494:     // from register interface (qualified with register enable)
1495:     .we     (mp_region_cfg3_rd_en3_we & region_cfg_regwen_qs),
1496:     .wd     (mp_region_cfg3_rd_en3_wd),
1497: 
1498:     // from internal hardware
1499:     .de     (1'b0),
1500:     .d      ('0  ),
1501: 
1502:     // to internal hardware
1503:     .qe     (),
1504:     .q      (reg2hw.mp_region_cfg[3].rd_en.q ),
1505: 
1506:     // to register interface (read)
1507:     .qs     (mp_region_cfg3_rd_en3_qs)
1508:   );
1509: 
1510: 
1511:   // F[prog_en3]: 2:2
1512:   prim_subreg #(
1513:     .DW      (1),
1514:     .SWACCESS("RW"),
1515:     .RESVAL  (1'h0)
1516:   ) u_mp_region_cfg3_prog_en3 (
1517:     .clk_i   (clk_i    ),
1518:     .rst_ni  (rst_ni  ),
1519: 
1520:     // from register interface (qualified with register enable)
1521:     .we     (mp_region_cfg3_prog_en3_we & region_cfg_regwen_qs),
1522:     .wd     (mp_region_cfg3_prog_en3_wd),
1523: 
1524:     // from internal hardware
1525:     .de     (1'b0),
1526:     .d      ('0  ),
1527: 
1528:     // to internal hardware
1529:     .qe     (),
1530:     .q      (reg2hw.mp_region_cfg[3].prog_en.q ),
1531: 
1532:     // to register interface (read)
1533:     .qs     (mp_region_cfg3_prog_en3_qs)
1534:   );
1535: 
1536: 
1537:   // F[erase_en3]: 3:3
1538:   prim_subreg #(
1539:     .DW      (1),
1540:     .SWACCESS("RW"),
1541:     .RESVAL  (1'h0)
1542:   ) u_mp_region_cfg3_erase_en3 (
1543:     .clk_i   (clk_i    ),
1544:     .rst_ni  (rst_ni  ),
1545: 
1546:     // from register interface (qualified with register enable)
1547:     .we     (mp_region_cfg3_erase_en3_we & region_cfg_regwen_qs),
1548:     .wd     (mp_region_cfg3_erase_en3_wd),
1549: 
1550:     // from internal hardware
1551:     .de     (1'b0),
1552:     .d      ('0  ),
1553: 
1554:     // to internal hardware
1555:     .qe     (),
1556:     .q      (reg2hw.mp_region_cfg[3].erase_en.q ),
1557: 
1558:     // to register interface (read)
1559:     .qs     (mp_region_cfg3_erase_en3_qs)
1560:   );
1561: 
1562: 
1563:   // F[base3]: 12:4
1564:   prim_subreg #(
1565:     .DW      (9),
1566:     .SWACCESS("RW"),
1567:     .RESVAL  (9'h0)
1568:   ) u_mp_region_cfg3_base3 (
1569:     .clk_i   (clk_i    ),
1570:     .rst_ni  (rst_ni  ),
1571: 
1572:     // from register interface (qualified with register enable)
1573:     .we     (mp_region_cfg3_base3_we & region_cfg_regwen_qs),
1574:     .wd     (mp_region_cfg3_base3_wd),
1575: 
1576:     // from internal hardware
1577:     .de     (1'b0),
1578:     .d      ('0  ),
1579: 
1580:     // to internal hardware
1581:     .qe     (),
1582:     .q      (reg2hw.mp_region_cfg[3].base.q ),
1583: 
1584:     // to register interface (read)
1585:     .qs     (mp_region_cfg3_base3_qs)
1586:   );
1587: 
1588: 
1589:   // F[size3]: 24:16
1590:   prim_subreg #(
1591:     .DW      (9),
1592:     .SWACCESS("RW"),
1593:     .RESVAL  (9'h0)
1594:   ) u_mp_region_cfg3_size3 (
1595:     .clk_i   (clk_i    ),
1596:     .rst_ni  (rst_ni  ),
1597: 
1598:     // from register interface (qualified with register enable)
1599:     .we     (mp_region_cfg3_size3_we & region_cfg_regwen_qs),
1600:     .wd     (mp_region_cfg3_size3_wd),
1601: 
1602:     // from internal hardware
1603:     .de     (1'b0),
1604:     .d      ('0  ),
1605: 
1606:     // to internal hardware
1607:     .qe     (),
1608:     .q      (reg2hw.mp_region_cfg[3].size.q ),
1609: 
1610:     // to register interface (read)
1611:     .qs     (mp_region_cfg3_size3_qs)
1612:   );
1613: 
1614: 
1615:   // Subregister 4 of Multireg mp_region_cfg
1616:   // R[mp_region_cfg4]: V(False)
1617: 
1618:   // F[en4]: 0:0
1619:   prim_subreg #(
1620:     .DW      (1),
1621:     .SWACCESS("RW"),
1622:     .RESVAL  (1'h0)
1623:   ) u_mp_region_cfg4_en4 (
1624:     .clk_i   (clk_i    ),
1625:     .rst_ni  (rst_ni  ),
1626: 
1627:     // from register interface (qualified with register enable)
1628:     .we     (mp_region_cfg4_en4_we & region_cfg_regwen_qs),
1629:     .wd     (mp_region_cfg4_en4_wd),
1630: 
1631:     // from internal hardware
1632:     .de     (1'b0),
1633:     .d      ('0  ),
1634: 
1635:     // to internal hardware
1636:     .qe     (),
1637:     .q      (reg2hw.mp_region_cfg[4].en.q ),
1638: 
1639:     // to register interface (read)
1640:     .qs     (mp_region_cfg4_en4_qs)
1641:   );
1642: 
1643: 
1644:   // F[rd_en4]: 1:1
1645:   prim_subreg #(
1646:     .DW      (1),
1647:     .SWACCESS("RW"),
1648:     .RESVAL  (1'h0)
1649:   ) u_mp_region_cfg4_rd_en4 (
1650:     .clk_i   (clk_i    ),
1651:     .rst_ni  (rst_ni  ),
1652: 
1653:     // from register interface (qualified with register enable)
1654:     .we     (mp_region_cfg4_rd_en4_we & region_cfg_regwen_qs),
1655:     .wd     (mp_region_cfg4_rd_en4_wd),
1656: 
1657:     // from internal hardware
1658:     .de     (1'b0),
1659:     .d      ('0  ),
1660: 
1661:     // to internal hardware
1662:     .qe     (),
1663:     .q      (reg2hw.mp_region_cfg[4].rd_en.q ),
1664: 
1665:     // to register interface (read)
1666:     .qs     (mp_region_cfg4_rd_en4_qs)
1667:   );
1668: 
1669: 
1670:   // F[prog_en4]: 2:2
1671:   prim_subreg #(
1672:     .DW      (1),
1673:     .SWACCESS("RW"),
1674:     .RESVAL  (1'h0)
1675:   ) u_mp_region_cfg4_prog_en4 (
1676:     .clk_i   (clk_i    ),
1677:     .rst_ni  (rst_ni  ),
1678: 
1679:     // from register interface (qualified with register enable)
1680:     .we     (mp_region_cfg4_prog_en4_we & region_cfg_regwen_qs),
1681:     .wd     (mp_region_cfg4_prog_en4_wd),
1682: 
1683:     // from internal hardware
1684:     .de     (1'b0),
1685:     .d      ('0  ),
1686: 
1687:     // to internal hardware
1688:     .qe     (),
1689:     .q      (reg2hw.mp_region_cfg[4].prog_en.q ),
1690: 
1691:     // to register interface (read)
1692:     .qs     (mp_region_cfg4_prog_en4_qs)
1693:   );
1694: 
1695: 
1696:   // F[erase_en4]: 3:3
1697:   prim_subreg #(
1698:     .DW      (1),
1699:     .SWACCESS("RW"),
1700:     .RESVAL  (1'h0)
1701:   ) u_mp_region_cfg4_erase_en4 (
1702:     .clk_i   (clk_i    ),
1703:     .rst_ni  (rst_ni  ),
1704: 
1705:     // from register interface (qualified with register enable)
1706:     .we     (mp_region_cfg4_erase_en4_we & region_cfg_regwen_qs),
1707:     .wd     (mp_region_cfg4_erase_en4_wd),
1708: 
1709:     // from internal hardware
1710:     .de     (1'b0),
1711:     .d      ('0  ),
1712: 
1713:     // to internal hardware
1714:     .qe     (),
1715:     .q      (reg2hw.mp_region_cfg[4].erase_en.q ),
1716: 
1717:     // to register interface (read)
1718:     .qs     (mp_region_cfg4_erase_en4_qs)
1719:   );
1720: 
1721: 
1722:   // F[base4]: 12:4
1723:   prim_subreg #(
1724:     .DW      (9),
1725:     .SWACCESS("RW"),
1726:     .RESVAL  (9'h0)
1727:   ) u_mp_region_cfg4_base4 (
1728:     .clk_i   (clk_i    ),
1729:     .rst_ni  (rst_ni  ),
1730: 
1731:     // from register interface (qualified with register enable)
1732:     .we     (mp_region_cfg4_base4_we & region_cfg_regwen_qs),
1733:     .wd     (mp_region_cfg4_base4_wd),
1734: 
1735:     // from internal hardware
1736:     .de     (1'b0),
1737:     .d      ('0  ),
1738: 
1739:     // to internal hardware
1740:     .qe     (),
1741:     .q      (reg2hw.mp_region_cfg[4].base.q ),
1742: 
1743:     // to register interface (read)
1744:     .qs     (mp_region_cfg4_base4_qs)
1745:   );
1746: 
1747: 
1748:   // F[size4]: 24:16
1749:   prim_subreg #(
1750:     .DW      (9),
1751:     .SWACCESS("RW"),
1752:     .RESVAL  (9'h0)
1753:   ) u_mp_region_cfg4_size4 (
1754:     .clk_i   (clk_i    ),
1755:     .rst_ni  (rst_ni  ),
1756: 
1757:     // from register interface (qualified with register enable)
1758:     .we     (mp_region_cfg4_size4_we & region_cfg_regwen_qs),
1759:     .wd     (mp_region_cfg4_size4_wd),
1760: 
1761:     // from internal hardware
1762:     .de     (1'b0),
1763:     .d      ('0  ),
1764: 
1765:     // to internal hardware
1766:     .qe     (),
1767:     .q      (reg2hw.mp_region_cfg[4].size.q ),
1768: 
1769:     // to register interface (read)
1770:     .qs     (mp_region_cfg4_size4_qs)
1771:   );
1772: 
1773: 
1774:   // Subregister 5 of Multireg mp_region_cfg
1775:   // R[mp_region_cfg5]: V(False)
1776: 
1777:   // F[en5]: 0:0
1778:   prim_subreg #(
1779:     .DW      (1),
1780:     .SWACCESS("RW"),
1781:     .RESVAL  (1'h0)
1782:   ) u_mp_region_cfg5_en5 (
1783:     .clk_i   (clk_i    ),
1784:     .rst_ni  (rst_ni  ),
1785: 
1786:     // from register interface (qualified with register enable)
1787:     .we     (mp_region_cfg5_en5_we & region_cfg_regwen_qs),
1788:     .wd     (mp_region_cfg5_en5_wd),
1789: 
1790:     // from internal hardware
1791:     .de     (1'b0),
1792:     .d      ('0  ),
1793: 
1794:     // to internal hardware
1795:     .qe     (),
1796:     .q      (reg2hw.mp_region_cfg[5].en.q ),
1797: 
1798:     // to register interface (read)
1799:     .qs     (mp_region_cfg5_en5_qs)
1800:   );
1801: 
1802: 
1803:   // F[rd_en5]: 1:1
1804:   prim_subreg #(
1805:     .DW      (1),
1806:     .SWACCESS("RW"),
1807:     .RESVAL  (1'h0)
1808:   ) u_mp_region_cfg5_rd_en5 (
1809:     .clk_i   (clk_i    ),
1810:     .rst_ni  (rst_ni  ),
1811: 
1812:     // from register interface (qualified with register enable)
1813:     .we     (mp_region_cfg5_rd_en5_we & region_cfg_regwen_qs),
1814:     .wd     (mp_region_cfg5_rd_en5_wd),
1815: 
1816:     // from internal hardware
1817:     .de     (1'b0),
1818:     .d      ('0  ),
1819: 
1820:     // to internal hardware
1821:     .qe     (),
1822:     .q      (reg2hw.mp_region_cfg[5].rd_en.q ),
1823: 
1824:     // to register interface (read)
1825:     .qs     (mp_region_cfg5_rd_en5_qs)
1826:   );
1827: 
1828: 
1829:   // F[prog_en5]: 2:2
1830:   prim_subreg #(
1831:     .DW      (1),
1832:     .SWACCESS("RW"),
1833:     .RESVAL  (1'h0)
1834:   ) u_mp_region_cfg5_prog_en5 (
1835:     .clk_i   (clk_i    ),
1836:     .rst_ni  (rst_ni  ),
1837: 
1838:     // from register interface (qualified with register enable)
1839:     .we     (mp_region_cfg5_prog_en5_we & region_cfg_regwen_qs),
1840:     .wd     (mp_region_cfg5_prog_en5_wd),
1841: 
1842:     // from internal hardware
1843:     .de     (1'b0),
1844:     .d      ('0  ),
1845: 
1846:     // to internal hardware
1847:     .qe     (),
1848:     .q      (reg2hw.mp_region_cfg[5].prog_en.q ),
1849: 
1850:     // to register interface (read)
1851:     .qs     (mp_region_cfg5_prog_en5_qs)
1852:   );
1853: 
1854: 
1855:   // F[erase_en5]: 3:3
1856:   prim_subreg #(
1857:     .DW      (1),
1858:     .SWACCESS("RW"),
1859:     .RESVAL  (1'h0)
1860:   ) u_mp_region_cfg5_erase_en5 (
1861:     .clk_i   (clk_i    ),
1862:     .rst_ni  (rst_ni  ),
1863: 
1864:     // from register interface (qualified with register enable)
1865:     .we     (mp_region_cfg5_erase_en5_we & region_cfg_regwen_qs),
1866:     .wd     (mp_region_cfg5_erase_en5_wd),
1867: 
1868:     // from internal hardware
1869:     .de     (1'b0),
1870:     .d      ('0  ),
1871: 
1872:     // to internal hardware
1873:     .qe     (),
1874:     .q      (reg2hw.mp_region_cfg[5].erase_en.q ),
1875: 
1876:     // to register interface (read)
1877:     .qs     (mp_region_cfg5_erase_en5_qs)
1878:   );
1879: 
1880: 
1881:   // F[base5]: 12:4
1882:   prim_subreg #(
1883:     .DW      (9),
1884:     .SWACCESS("RW"),
1885:     .RESVAL  (9'h0)
1886:   ) u_mp_region_cfg5_base5 (
1887:     .clk_i   (clk_i    ),
1888:     .rst_ni  (rst_ni  ),
1889: 
1890:     // from register interface (qualified with register enable)
1891:     .we     (mp_region_cfg5_base5_we & region_cfg_regwen_qs),
1892:     .wd     (mp_region_cfg5_base5_wd),
1893: 
1894:     // from internal hardware
1895:     .de     (1'b0),
1896:     .d      ('0  ),
1897: 
1898:     // to internal hardware
1899:     .qe     (),
1900:     .q      (reg2hw.mp_region_cfg[5].base.q ),
1901: 
1902:     // to register interface (read)
1903:     .qs     (mp_region_cfg5_base5_qs)
1904:   );
1905: 
1906: 
1907:   // F[size5]: 24:16
1908:   prim_subreg #(
1909:     .DW      (9),
1910:     .SWACCESS("RW"),
1911:     .RESVAL  (9'h0)
1912:   ) u_mp_region_cfg5_size5 (
1913:     .clk_i   (clk_i    ),
1914:     .rst_ni  (rst_ni  ),
1915: 
1916:     // from register interface (qualified with register enable)
1917:     .we     (mp_region_cfg5_size5_we & region_cfg_regwen_qs),
1918:     .wd     (mp_region_cfg5_size5_wd),
1919: 
1920:     // from internal hardware
1921:     .de     (1'b0),
1922:     .d      ('0  ),
1923: 
1924:     // to internal hardware
1925:     .qe     (),
1926:     .q      (reg2hw.mp_region_cfg[5].size.q ),
1927: 
1928:     // to register interface (read)
1929:     .qs     (mp_region_cfg5_size5_qs)
1930:   );
1931: 
1932: 
1933:   // Subregister 6 of Multireg mp_region_cfg
1934:   // R[mp_region_cfg6]: V(False)
1935: 
1936:   // F[en6]: 0:0
1937:   prim_subreg #(
1938:     .DW      (1),
1939:     .SWACCESS("RW"),
1940:     .RESVAL  (1'h0)
1941:   ) u_mp_region_cfg6_en6 (
1942:     .clk_i   (clk_i    ),
1943:     .rst_ni  (rst_ni  ),
1944: 
1945:     // from register interface (qualified with register enable)
1946:     .we     (mp_region_cfg6_en6_we & region_cfg_regwen_qs),
1947:     .wd     (mp_region_cfg6_en6_wd),
1948: 
1949:     // from internal hardware
1950:     .de     (1'b0),
1951:     .d      ('0  ),
1952: 
1953:     // to internal hardware
1954:     .qe     (),
1955:     .q      (reg2hw.mp_region_cfg[6].en.q ),
1956: 
1957:     // to register interface (read)
1958:     .qs     (mp_region_cfg6_en6_qs)
1959:   );
1960: 
1961: 
1962:   // F[rd_en6]: 1:1
1963:   prim_subreg #(
1964:     .DW      (1),
1965:     .SWACCESS("RW"),
1966:     .RESVAL  (1'h0)
1967:   ) u_mp_region_cfg6_rd_en6 (
1968:     .clk_i   (clk_i    ),
1969:     .rst_ni  (rst_ni  ),
1970: 
1971:     // from register interface (qualified with register enable)
1972:     .we     (mp_region_cfg6_rd_en6_we & region_cfg_regwen_qs),
1973:     .wd     (mp_region_cfg6_rd_en6_wd),
1974: 
1975:     // from internal hardware
1976:     .de     (1'b0),
1977:     .d      ('0  ),
1978: 
1979:     // to internal hardware
1980:     .qe     (),
1981:     .q      (reg2hw.mp_region_cfg[6].rd_en.q ),
1982: 
1983:     // to register interface (read)
1984:     .qs     (mp_region_cfg6_rd_en6_qs)
1985:   );
1986: 
1987: 
1988:   // F[prog_en6]: 2:2
1989:   prim_subreg #(
1990:     .DW      (1),
1991:     .SWACCESS("RW"),
1992:     .RESVAL  (1'h0)
1993:   ) u_mp_region_cfg6_prog_en6 (
1994:     .clk_i   (clk_i    ),
1995:     .rst_ni  (rst_ni  ),
1996: 
1997:     // from register interface (qualified with register enable)
1998:     .we     (mp_region_cfg6_prog_en6_we & region_cfg_regwen_qs),
1999:     .wd     (mp_region_cfg6_prog_en6_wd),
2000: 
2001:     // from internal hardware
2002:     .de     (1'b0),
2003:     .d      ('0  ),
2004: 
2005:     // to internal hardware
2006:     .qe     (),
2007:     .q      (reg2hw.mp_region_cfg[6].prog_en.q ),
2008: 
2009:     // to register interface (read)
2010:     .qs     (mp_region_cfg6_prog_en6_qs)
2011:   );
2012: 
2013: 
2014:   // F[erase_en6]: 3:3
2015:   prim_subreg #(
2016:     .DW      (1),
2017:     .SWACCESS("RW"),
2018:     .RESVAL  (1'h0)
2019:   ) u_mp_region_cfg6_erase_en6 (
2020:     .clk_i   (clk_i    ),
2021:     .rst_ni  (rst_ni  ),
2022: 
2023:     // from register interface (qualified with register enable)
2024:     .we     (mp_region_cfg6_erase_en6_we & region_cfg_regwen_qs),
2025:     .wd     (mp_region_cfg6_erase_en6_wd),
2026: 
2027:     // from internal hardware
2028:     .de     (1'b0),
2029:     .d      ('0  ),
2030: 
2031:     // to internal hardware
2032:     .qe     (),
2033:     .q      (reg2hw.mp_region_cfg[6].erase_en.q ),
2034: 
2035:     // to register interface (read)
2036:     .qs     (mp_region_cfg6_erase_en6_qs)
2037:   );
2038: 
2039: 
2040:   // F[base6]: 12:4
2041:   prim_subreg #(
2042:     .DW      (9),
2043:     .SWACCESS("RW"),
2044:     .RESVAL  (9'h0)
2045:   ) u_mp_region_cfg6_base6 (
2046:     .clk_i   (clk_i    ),
2047:     .rst_ni  (rst_ni  ),
2048: 
2049:     // from register interface (qualified with register enable)
2050:     .we     (mp_region_cfg6_base6_we & region_cfg_regwen_qs),
2051:     .wd     (mp_region_cfg6_base6_wd),
2052: 
2053:     // from internal hardware
2054:     .de     (1'b0),
2055:     .d      ('0  ),
2056: 
2057:     // to internal hardware
2058:     .qe     (),
2059:     .q      (reg2hw.mp_region_cfg[6].base.q ),
2060: 
2061:     // to register interface (read)
2062:     .qs     (mp_region_cfg6_base6_qs)
2063:   );
2064: 
2065: 
2066:   // F[size6]: 24:16
2067:   prim_subreg #(
2068:     .DW      (9),
2069:     .SWACCESS("RW"),
2070:     .RESVAL  (9'h0)
2071:   ) u_mp_region_cfg6_size6 (
2072:     .clk_i   (clk_i    ),
2073:     .rst_ni  (rst_ni  ),
2074: 
2075:     // from register interface (qualified with register enable)
2076:     .we     (mp_region_cfg6_size6_we & region_cfg_regwen_qs),
2077:     .wd     (mp_region_cfg6_size6_wd),
2078: 
2079:     // from internal hardware
2080:     .de     (1'b0),
2081:     .d      ('0  ),
2082: 
2083:     // to internal hardware
2084:     .qe     (),
2085:     .q      (reg2hw.mp_region_cfg[6].size.q ),
2086: 
2087:     // to register interface (read)
2088:     .qs     (mp_region_cfg6_size6_qs)
2089:   );
2090: 
2091: 
2092:   // Subregister 7 of Multireg mp_region_cfg
2093:   // R[mp_region_cfg7]: V(False)
2094: 
2095:   // F[en7]: 0:0
2096:   prim_subreg #(
2097:     .DW      (1),
2098:     .SWACCESS("RW"),
2099:     .RESVAL  (1'h0)
2100:   ) u_mp_region_cfg7_en7 (
2101:     .clk_i   (clk_i    ),
2102:     .rst_ni  (rst_ni  ),
2103: 
2104:     // from register interface (qualified with register enable)
2105:     .we     (mp_region_cfg7_en7_we & region_cfg_regwen_qs),
2106:     .wd     (mp_region_cfg7_en7_wd),
2107: 
2108:     // from internal hardware
2109:     .de     (1'b0),
2110:     .d      ('0  ),
2111: 
2112:     // to internal hardware
2113:     .qe     (),
2114:     .q      (reg2hw.mp_region_cfg[7].en.q ),
2115: 
2116:     // to register interface (read)
2117:     .qs     (mp_region_cfg7_en7_qs)
2118:   );
2119: 
2120: 
2121:   // F[rd_en7]: 1:1
2122:   prim_subreg #(
2123:     .DW      (1),
2124:     .SWACCESS("RW"),
2125:     .RESVAL  (1'h0)
2126:   ) u_mp_region_cfg7_rd_en7 (
2127:     .clk_i   (clk_i    ),
2128:     .rst_ni  (rst_ni  ),
2129: 
2130:     // from register interface (qualified with register enable)
2131:     .we     (mp_region_cfg7_rd_en7_we & region_cfg_regwen_qs),
2132:     .wd     (mp_region_cfg7_rd_en7_wd),
2133: 
2134:     // from internal hardware
2135:     .de     (1'b0),
2136:     .d      ('0  ),
2137: 
2138:     // to internal hardware
2139:     .qe     (),
2140:     .q      (reg2hw.mp_region_cfg[7].rd_en.q ),
2141: 
2142:     // to register interface (read)
2143:     .qs     (mp_region_cfg7_rd_en7_qs)
2144:   );
2145: 
2146: 
2147:   // F[prog_en7]: 2:2
2148:   prim_subreg #(
2149:     .DW      (1),
2150:     .SWACCESS("RW"),
2151:     .RESVAL  (1'h0)
2152:   ) u_mp_region_cfg7_prog_en7 (
2153:     .clk_i   (clk_i    ),
2154:     .rst_ni  (rst_ni  ),
2155: 
2156:     // from register interface (qualified with register enable)
2157:     .we     (mp_region_cfg7_prog_en7_we & region_cfg_regwen_qs),
2158:     .wd     (mp_region_cfg7_prog_en7_wd),
2159: 
2160:     // from internal hardware
2161:     .de     (1'b0),
2162:     .d      ('0  ),
2163: 
2164:     // to internal hardware
2165:     .qe     (),
2166:     .q      (reg2hw.mp_region_cfg[7].prog_en.q ),
2167: 
2168:     // to register interface (read)
2169:     .qs     (mp_region_cfg7_prog_en7_qs)
2170:   );
2171: 
2172: 
2173:   // F[erase_en7]: 3:3
2174:   prim_subreg #(
2175:     .DW      (1),
2176:     .SWACCESS("RW"),
2177:     .RESVAL  (1'h0)
2178:   ) u_mp_region_cfg7_erase_en7 (
2179:     .clk_i   (clk_i    ),
2180:     .rst_ni  (rst_ni  ),
2181: 
2182:     // from register interface (qualified with register enable)
2183:     .we     (mp_region_cfg7_erase_en7_we & region_cfg_regwen_qs),
2184:     .wd     (mp_region_cfg7_erase_en7_wd),
2185: 
2186:     // from internal hardware
2187:     .de     (1'b0),
2188:     .d      ('0  ),
2189: 
2190:     // to internal hardware
2191:     .qe     (),
2192:     .q      (reg2hw.mp_region_cfg[7].erase_en.q ),
2193: 
2194:     // to register interface (read)
2195:     .qs     (mp_region_cfg7_erase_en7_qs)
2196:   );
2197: 
2198: 
2199:   // F[base7]: 12:4
2200:   prim_subreg #(
2201:     .DW      (9),
2202:     .SWACCESS("RW"),
2203:     .RESVAL  (9'h0)
2204:   ) u_mp_region_cfg7_base7 (
2205:     .clk_i   (clk_i    ),
2206:     .rst_ni  (rst_ni  ),
2207: 
2208:     // from register interface (qualified with register enable)
2209:     .we     (mp_region_cfg7_base7_we & region_cfg_regwen_qs),
2210:     .wd     (mp_region_cfg7_base7_wd),
2211: 
2212:     // from internal hardware
2213:     .de     (1'b0),
2214:     .d      ('0  ),
2215: 
2216:     // to internal hardware
2217:     .qe     (),
2218:     .q      (reg2hw.mp_region_cfg[7].base.q ),
2219: 
2220:     // to register interface (read)
2221:     .qs     (mp_region_cfg7_base7_qs)
2222:   );
2223: 
2224: 
2225:   // F[size7]: 24:16
2226:   prim_subreg #(
2227:     .DW      (9),
2228:     .SWACCESS("RW"),
2229:     .RESVAL  (9'h0)
2230:   ) u_mp_region_cfg7_size7 (
2231:     .clk_i   (clk_i    ),
2232:     .rst_ni  (rst_ni  ),
2233: 
2234:     // from register interface (qualified with register enable)
2235:     .we     (mp_region_cfg7_size7_we & region_cfg_regwen_qs),
2236:     .wd     (mp_region_cfg7_size7_wd),
2237: 
2238:     // from internal hardware
2239:     .de     (1'b0),
2240:     .d      ('0  ),
2241: 
2242:     // to internal hardware
2243:     .qe     (),
2244:     .q      (reg2hw.mp_region_cfg[7].size.q ),
2245: 
2246:     // to register interface (read)
2247:     .qs     (mp_region_cfg7_size7_qs)
2248:   );
2249: 
2250: 
2251: 
2252:   // R[default_region]: V(False)
2253: 
2254:   //   F[rd_en]: 0:0
2255:   prim_subreg #(
2256:     .DW      (1),
2257:     .SWACCESS("RW"),
2258:     .RESVAL  (1'h0)
2259:   ) u_default_region_rd_en (
2260:     .clk_i   (clk_i    ),
2261:     .rst_ni  (rst_ni  ),
2262: 
2263:     // from register interface
2264:     .we     (default_region_rd_en_we),
2265:     .wd     (default_region_rd_en_wd),
2266: 
2267:     // from internal hardware
2268:     .de     (1'b0),
2269:     .d      ('0  ),
2270: 
2271:     // to internal hardware
2272:     .qe     (),
2273:     .q      (reg2hw.default_region.rd_en.q ),
2274: 
2275:     // to register interface (read)
2276:     .qs     (default_region_rd_en_qs)
2277:   );
2278: 
2279: 
2280:   //   F[prog_en]: 1:1
2281:   prim_subreg #(
2282:     .DW      (1),
2283:     .SWACCESS("RW"),
2284:     .RESVAL  (1'h0)
2285:   ) u_default_region_prog_en (
2286:     .clk_i   (clk_i    ),
2287:     .rst_ni  (rst_ni  ),
2288: 
2289:     // from register interface
2290:     .we     (default_region_prog_en_we),
2291:     .wd     (default_region_prog_en_wd),
2292: 
2293:     // from internal hardware
2294:     .de     (1'b0),
2295:     .d      ('0  ),
2296: 
2297:     // to internal hardware
2298:     .qe     (),
2299:     .q      (reg2hw.default_region.prog_en.q ),
2300: 
2301:     // to register interface (read)
2302:     .qs     (default_region_prog_en_qs)
2303:   );
2304: 
2305: 
2306:   //   F[erase_en]: 2:2
2307:   prim_subreg #(
2308:     .DW      (1),
2309:     .SWACCESS("RW"),
2310:     .RESVAL  (1'h0)
2311:   ) u_default_region_erase_en (
2312:     .clk_i   (clk_i    ),
2313:     .rst_ni  (rst_ni  ),
2314: 
2315:     // from register interface
2316:     .we     (default_region_erase_en_we),
2317:     .wd     (default_region_erase_en_wd),
2318: 
2319:     // from internal hardware
2320:     .de     (1'b0),
2321:     .d      ('0  ),
2322: 
2323:     // to internal hardware
2324:     .qe     (),
2325:     .q      (reg2hw.default_region.erase_en.q ),
2326: 
2327:     // to register interface (read)
2328:     .qs     (default_region_erase_en_qs)
2329:   );
2330: 
2331: 
2332:   // R[bank_cfg_regwen]: V(False)
2333: 
2334:   prim_subreg #(
2335:     .DW      (1),
2336:     .SWACCESS("W0C"),
2337:     .RESVAL  (1'h1)
2338:   ) u_bank_cfg_regwen (
2339:     .clk_i   (clk_i    ),
2340:     .rst_ni  (rst_ni  ),
2341: 
2342:     // from register interface
2343:     .we     (bank_cfg_regwen_we),
2344:     .wd     (bank_cfg_regwen_wd),
2345: 
2346:     // from internal hardware
2347:     .de     (1'b0),
2348:     .d      ('0  ),
2349: 
2350:     // to internal hardware
2351:     .qe     (),
2352:     .q      (),
2353: 
2354:     // to register interface (read)
2355:     .qs     (bank_cfg_regwen_qs)
2356:   );
2357: 
2358: 
2359: 
2360:   // Subregister 0 of Multireg mp_bank_cfg
2361:   // R[mp_bank_cfg]: V(False)
2362: 
2363:   // F[erase_en0]: 0:0
2364:   prim_subreg #(
2365:     .DW      (1),
2366:     .SWACCESS("RW"),
2367:     .RESVAL  (1'h0)
2368:   ) u_mp_bank_cfg_erase_en0 (
2369:     .clk_i   (clk_i    ),
2370:     .rst_ni  (rst_ni  ),
2371: 
2372:     // from register interface (qualified with register enable)
2373:     .we     (mp_bank_cfg_erase_en0_we & bank_cfg_regwen_qs),
2374:     .wd     (mp_bank_cfg_erase_en0_wd),
2375: 
2376:     // from internal hardware
2377:     .de     (1'b0),
2378:     .d      ('0  ),
2379: 
2380:     // to internal hardware
2381:     .qe     (),
2382:     .q      (reg2hw.mp_bank_cfg[0].q ),
2383: 
2384:     // to register interface (read)
2385:     .qs     (mp_bank_cfg_erase_en0_qs)
2386:   );
2387: 
2388: 
2389:   // F[erase_en1]: 1:1
2390:   prim_subreg #(
2391:     .DW      (1),
2392:     .SWACCESS("RW"),
2393:     .RESVAL  (1'h0)
2394:   ) u_mp_bank_cfg_erase_en1 (
2395:     .clk_i   (clk_i    ),
2396:     .rst_ni  (rst_ni  ),
2397: 
2398:     // from register interface (qualified with register enable)
2399:     .we     (mp_bank_cfg_erase_en1_we & bank_cfg_regwen_qs),
2400:     .wd     (mp_bank_cfg_erase_en1_wd),
2401: 
2402:     // from internal hardware
2403:     .de     (1'b0),
2404:     .d      ('0  ),
2405: 
2406:     // to internal hardware
2407:     .qe     (),
2408:     .q      (reg2hw.mp_bank_cfg[1].q ),
2409: 
2410:     // to register interface (read)
2411:     .qs     (mp_bank_cfg_erase_en1_qs)
2412:   );
2413: 
2414: 
2415: 
2416:   // R[op_status]: V(False)
2417: 
2418:   //   F[done]: 0:0
2419:   prim_subreg #(
2420:     .DW      (1),
2421:     .SWACCESS("RW"),
2422:     .RESVAL  (1'h0)
2423:   ) u_op_status_done (
2424:     .clk_i   (clk_i    ),
2425:     .rst_ni  (rst_ni  ),
2426: 
2427:     // from register interface
2428:     .we     (op_status_done_we),
2429:     .wd     (op_status_done_wd),
2430: 
2431:     // from internal hardware
2432:     .de     (hw2reg.op_status.done.de),
2433:     .d      (hw2reg.op_status.done.d ),
2434: 
2435:     // to internal hardware
2436:     .qe     (),
2437:     .q      (),
2438: 
2439:     // to register interface (read)
2440:     .qs     (op_status_done_qs)
2441:   );
2442: 
2443: 
2444:   //   F[err]: 1:1
2445:   prim_subreg #(
2446:     .DW      (1),
2447:     .SWACCESS("RW"),
2448:     .RESVAL  (1'h0)
2449:   ) u_op_status_err (
2450:     .clk_i   (clk_i    ),
2451:     .rst_ni  (rst_ni  ),
2452: 
2453:     // from register interface
2454:     .we     (op_status_err_we),
2455:     .wd     (op_status_err_wd),
2456: 
2457:     // from internal hardware
2458:     .de     (hw2reg.op_status.err.de),
2459:     .d      (hw2reg.op_status.err.d ),
2460: 
2461:     // to internal hardware
2462:     .qe     (),
2463:     .q      (),
2464: 
2465:     // to register interface (read)
2466:     .qs     (op_status_err_qs)
2467:   );
2468: 
2469: 
2470:   // R[status]: V(True)
2471: 
2472:   //   F[rd_full]: 0:0
2473:   prim_subreg_ext #(
2474:     .DW    (1)
2475:   ) u_status_rd_full (
2476:     .re     (status_rd_full_re),
2477:     .we     (1'b0),
2478:     .wd     ('0),
2479:     .d      (hw2reg.status.rd_full.d),
2480:     .qre    (),
2481:     .qe     (),
2482:     .q      (),
2483:     .qs     (status_rd_full_qs)
2484:   );
2485: 
2486: 
2487:   //   F[rd_empty]: 1:1
2488:   prim_subreg_ext #(
2489:     .DW    (1)
2490:   ) u_status_rd_empty (
2491:     .re     (status_rd_empty_re),
2492:     .we     (1'b0),
2493:     .wd     ('0),
2494:     .d      (hw2reg.status.rd_empty.d),
2495:     .qre    (),
2496:     .qe     (),
2497:     .q      (),
2498:     .qs     (status_rd_empty_qs)
2499:   );
2500: 
2501: 
2502:   //   F[prog_full]: 2:2
2503:   prim_subreg_ext #(
2504:     .DW    (1)
2505:   ) u_status_prog_full (
2506:     .re     (status_prog_full_re),
2507:     .we     (1'b0),
2508:     .wd     ('0),
2509:     .d      (hw2reg.status.prog_full.d),
2510:     .qre    (),
2511:     .qe     (),
2512:     .q      (),
2513:     .qs     (status_prog_full_qs)
2514:   );
2515: 
2516: 
2517:   //   F[prog_empty]: 3:3
2518:   prim_subreg_ext #(
2519:     .DW    (1)
2520:   ) u_status_prog_empty (
2521:     .re     (status_prog_empty_re),
2522:     .we     (1'b0),
2523:     .wd     ('0),
2524:     .d      (hw2reg.status.prog_empty.d),
2525:     .qre    (),
2526:     .qe     (),
2527:     .q      (),
2528:     .qs     (status_prog_empty_qs)
2529:   );
2530: 
2531: 
2532:   //   F[init_wip]: 4:4
2533:   prim_subreg_ext #(
2534:     .DW    (1)
2535:   ) u_status_init_wip (
2536:     .re     (status_init_wip_re),
2537:     .we     (1'b0),
2538:     .wd     ('0),
2539:     .d      (hw2reg.status.init_wip.d),
2540:     .qre    (),
2541:     .qe     (),
2542:     .q      (),
2543:     .qs     (status_init_wip_qs)
2544:   );
2545: 
2546: 
2547:   //   F[error_page]: 16:8
2548:   prim_subreg_ext #(
2549:     .DW    (9)
2550:   ) u_status_error_page (
2551:     .re     (status_error_page_re),
2552:     .we     (1'b0),
2553:     .wd     ('0),
2554:     .d      (hw2reg.status.error_page.d),
2555:     .qre    (),
2556:     .qe     (),
2557:     .q      (),
2558:     .qs     (status_error_page_qs)
2559:   );
2560: 
2561: 
2562:   //   F[error_bank]: 17:17
2563:   prim_subreg_ext #(
2564:     .DW    (1)
2565:   ) u_status_error_bank (
2566:     .re     (status_error_bank_re),
2567:     .we     (1'b0),
2568:     .wd     ('0),
2569:     .d      (hw2reg.status.error_bank.d),
2570:     .qre    (),
2571:     .qe     (),
2572:     .q      (),
2573:     .qs     (status_error_bank_qs)
2574:   );
2575: 
2576: 
2577:   // R[scratch]: V(False)
2578: 
2579:   prim_subreg #(
2580:     .DW      (32),
2581:     .SWACCESS("RW"),
2582:     .RESVAL  (32'h0)
2583:   ) u_scratch (
2584:     .clk_i   (clk_i    ),
2585:     .rst_ni  (rst_ni  ),
2586: 
2587:     // from register interface
2588:     .we     (scratch_we),
2589:     .wd     (scratch_wd),
2590: 
2591:     // from internal hardware
2592:     .de     (1'b0),
2593:     .d      ('0  ),
2594: 
2595:     // to internal hardware
2596:     .qe     (),
2597:     .q      (reg2hw.scratch.q ),
2598: 
2599:     // to register interface (read)
2600:     .qs     (scratch_qs)
2601:   );
2602: 
2603: 
2604:   // R[fifo_lvl]: V(False)
2605: 
2606:   //   F[prog]: 4:0
2607:   prim_subreg #(
2608:     .DW      (5),
2609:     .SWACCESS("RW"),
2610:     .RESVAL  (5'hf)
2611:   ) u_fifo_lvl_prog (
2612:     .clk_i   (clk_i    ),
2613:     .rst_ni  (rst_ni  ),
2614: 
2615:     // from register interface
2616:     .we     (fifo_lvl_prog_we),
2617:     .wd     (fifo_lvl_prog_wd),
2618: 
2619:     // from internal hardware
2620:     .de     (1'b0),
2621:     .d      ('0  ),
2622: 
2623:     // to internal hardware
2624:     .qe     (),
2625:     .q      (reg2hw.fifo_lvl.prog.q ),
2626: 
2627:     // to register interface (read)
2628:     .qs     (fifo_lvl_prog_qs)
2629:   );
2630: 
2631: 
2632:   //   F[rd]: 12:8
2633:   prim_subreg #(
2634:     .DW      (5),
2635:     .SWACCESS("RW"),
2636:     .RESVAL  (5'hf)
2637:   ) u_fifo_lvl_rd (
2638:     .clk_i   (clk_i    ),
2639:     .rst_ni  (rst_ni  ),
2640: 
2641:     // from register interface
2642:     .we     (fifo_lvl_rd_we),
2643:     .wd     (fifo_lvl_rd_wd),
2644: 
2645:     // from internal hardware
2646:     .de     (1'b0),
2647:     .d      ('0  ),
2648: 
2649:     // to internal hardware
2650:     .qe     (),
2651:     .q      (reg2hw.fifo_lvl.rd.q ),
2652: 
2653:     // to register interface (read)
2654:     .qs     (fifo_lvl_rd_qs)
2655:   );
2656: 
2657: 
2658: 
2659: 
2660:   logic [20:0] addr_hit;
2661:   always_comb begin
2662:     addr_hit = '0;
2663:     addr_hit[ 0] = (reg_addr == FLASH_CTRL_INTR_STATE_OFFSET);
2664:     addr_hit[ 1] = (reg_addr == FLASH_CTRL_INTR_ENABLE_OFFSET);
2665:     addr_hit[ 2] = (reg_addr == FLASH_CTRL_INTR_TEST_OFFSET);
2666:     addr_hit[ 3] = (reg_addr == FLASH_CTRL_CONTROL_OFFSET);
2667:     addr_hit[ 4] = (reg_addr == FLASH_CTRL_ADDR_OFFSET);
2668:     addr_hit[ 5] = (reg_addr == FLASH_CTRL_REGION_CFG_REGWEN_OFFSET);
2669:     addr_hit[ 6] = (reg_addr == FLASH_CTRL_MP_REGION_CFG0_OFFSET);
2670:     addr_hit[ 7] = (reg_addr == FLASH_CTRL_MP_REGION_CFG1_OFFSET);
2671:     addr_hit[ 8] = (reg_addr == FLASH_CTRL_MP_REGION_CFG2_OFFSET);
2672:     addr_hit[ 9] = (reg_addr == FLASH_CTRL_MP_REGION_CFG3_OFFSET);
2673:     addr_hit[10] = (reg_addr == FLASH_CTRL_MP_REGION_CFG4_OFFSET);
2674:     addr_hit[11] = (reg_addr == FLASH_CTRL_MP_REGION_CFG5_OFFSET);
2675:     addr_hit[12] = (reg_addr == FLASH_CTRL_MP_REGION_CFG6_OFFSET);
2676:     addr_hit[13] = (reg_addr == FLASH_CTRL_MP_REGION_CFG7_OFFSET);
2677:     addr_hit[14] = (reg_addr == FLASH_CTRL_DEFAULT_REGION_OFFSET);
2678:     addr_hit[15] = (reg_addr == FLASH_CTRL_BANK_CFG_REGWEN_OFFSET);
2679:     addr_hit[16] = (reg_addr == FLASH_CTRL_MP_BANK_CFG_OFFSET);
2680:     addr_hit[17] = (reg_addr == FLASH_CTRL_OP_STATUS_OFFSET);
2681:     addr_hit[18] = (reg_addr == FLASH_CTRL_STATUS_OFFSET);
2682:     addr_hit[19] = (reg_addr == FLASH_CTRL_SCRATCH_OFFSET);
2683:     addr_hit[20] = (reg_addr == FLASH_CTRL_FIFO_LVL_OFFSET);
2684:   end
2685: 
2686:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
2687: 
2688:   // Check sub-word write is permitted
2689:   always_comb begin
2690:     wr_err = 1'b0;
2691:     if (addr_hit[ 0] && reg_we && (FLASH_CTRL_PERMIT[ 0] != (FLASH_CTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
2692:     if (addr_hit[ 1] && reg_we && (FLASH_CTRL_PERMIT[ 1] != (FLASH_CTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
2693:     if (addr_hit[ 2] && reg_we && (FLASH_CTRL_PERMIT[ 2] != (FLASH_CTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
2694:     if (addr_hit[ 3] && reg_we && (FLASH_CTRL_PERMIT[ 3] != (FLASH_CTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
2695:     if (addr_hit[ 4] && reg_we && (FLASH_CTRL_PERMIT[ 4] != (FLASH_CTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
2696:     if (addr_hit[ 5] && reg_we && (FLASH_CTRL_PERMIT[ 5] != (FLASH_CTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
2697:     if (addr_hit[ 6] && reg_we && (FLASH_CTRL_PERMIT[ 6] != (FLASH_CTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
2698:     if (addr_hit[ 7] && reg_we && (FLASH_CTRL_PERMIT[ 7] != (FLASH_CTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
2699:     if (addr_hit[ 8] && reg_we && (FLASH_CTRL_PERMIT[ 8] != (FLASH_CTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
2700:     if (addr_hit[ 9] && reg_we && (FLASH_CTRL_PERMIT[ 9] != (FLASH_CTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
2701:     if (addr_hit[10] && reg_we && (FLASH_CTRL_PERMIT[10] != (FLASH_CTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
2702:     if (addr_hit[11] && reg_we && (FLASH_CTRL_PERMIT[11] != (FLASH_CTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
2703:     if (addr_hit[12] && reg_we && (FLASH_CTRL_PERMIT[12] != (FLASH_CTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
2704:     if (addr_hit[13] && reg_we && (FLASH_CTRL_PERMIT[13] != (FLASH_CTRL_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
2705:     if (addr_hit[14] && reg_we && (FLASH_CTRL_PERMIT[14] != (FLASH_CTRL_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
2706:     if (addr_hit[15] && reg_we && (FLASH_CTRL_PERMIT[15] != (FLASH_CTRL_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
2707:     if (addr_hit[16] && reg_we && (FLASH_CTRL_PERMIT[16] != (FLASH_CTRL_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
2708:     if (addr_hit[17] && reg_we && (FLASH_CTRL_PERMIT[17] != (FLASH_CTRL_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
2709:     if (addr_hit[18] && reg_we && (FLASH_CTRL_PERMIT[18] != (FLASH_CTRL_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
2710:     if (addr_hit[19] && reg_we && (FLASH_CTRL_PERMIT[19] != (FLASH_CTRL_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
2711:     if (addr_hit[20] && reg_we && (FLASH_CTRL_PERMIT[20] != (FLASH_CTRL_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
2712:   end
2713: 
2714:   assign intr_state_prog_empty_we = addr_hit[0] & reg_we & ~wr_err;
2715:   assign intr_state_prog_empty_wd = reg_wdata[0];
2716: 
2717:   assign intr_state_prog_lvl_we = addr_hit[0] & reg_we & ~wr_err;
2718:   assign intr_state_prog_lvl_wd = reg_wdata[1];
2719: 
2720:   assign intr_state_rd_full_we = addr_hit[0] & reg_we & ~wr_err;
2721:   assign intr_state_rd_full_wd = reg_wdata[2];
2722: 
2723:   assign intr_state_rd_lvl_we = addr_hit[0] & reg_we & ~wr_err;
2724:   assign intr_state_rd_lvl_wd = reg_wdata[3];
2725: 
2726:   assign intr_state_op_done_we = addr_hit[0] & reg_we & ~wr_err;
2727:   assign intr_state_op_done_wd = reg_wdata[4];
2728: 
2729:   assign intr_state_op_error_we = addr_hit[0] & reg_we & ~wr_err;
2730:   assign intr_state_op_error_wd = reg_wdata[5];
2731: 
2732:   assign intr_enable_prog_empty_we = addr_hit[1] & reg_we & ~wr_err;
2733:   assign intr_enable_prog_empty_wd = reg_wdata[0];
2734: 
2735:   assign intr_enable_prog_lvl_we = addr_hit[1] & reg_we & ~wr_err;
2736:   assign intr_enable_prog_lvl_wd = reg_wdata[1];
2737: 
2738:   assign intr_enable_rd_full_we = addr_hit[1] & reg_we & ~wr_err;
2739:   assign intr_enable_rd_full_wd = reg_wdata[2];
2740: 
2741:   assign intr_enable_rd_lvl_we = addr_hit[1] & reg_we & ~wr_err;
2742:   assign intr_enable_rd_lvl_wd = reg_wdata[3];
2743: 
2744:   assign intr_enable_op_done_we = addr_hit[1] & reg_we & ~wr_err;
2745:   assign intr_enable_op_done_wd = reg_wdata[4];
2746: 
2747:   assign intr_enable_op_error_we = addr_hit[1] & reg_we & ~wr_err;
2748:   assign intr_enable_op_error_wd = reg_wdata[5];
2749: 
2750:   assign intr_test_prog_empty_we = addr_hit[2] & reg_we & ~wr_err;
2751:   assign intr_test_prog_empty_wd = reg_wdata[0];
2752: 
2753:   assign intr_test_prog_lvl_we = addr_hit[2] & reg_we & ~wr_err;
2754:   assign intr_test_prog_lvl_wd = reg_wdata[1];
2755: 
2756:   assign intr_test_rd_full_we = addr_hit[2] & reg_we & ~wr_err;
2757:   assign intr_test_rd_full_wd = reg_wdata[2];
2758: 
2759:   assign intr_test_rd_lvl_we = addr_hit[2] & reg_we & ~wr_err;
2760:   assign intr_test_rd_lvl_wd = reg_wdata[3];
2761: 
2762:   assign intr_test_op_done_we = addr_hit[2] & reg_we & ~wr_err;
2763:   assign intr_test_op_done_wd = reg_wdata[4];
2764: 
2765:   assign intr_test_op_error_we = addr_hit[2] & reg_we & ~wr_err;
2766:   assign intr_test_op_error_wd = reg_wdata[5];
2767: 
2768:   assign control_start_we = addr_hit[3] & reg_we & ~wr_err;
2769:   assign control_start_wd = reg_wdata[0];
2770: 
2771:   assign control_op_we = addr_hit[3] & reg_we & ~wr_err;
2772:   assign control_op_wd = reg_wdata[5:4];
2773: 
2774:   assign control_erase_sel_we = addr_hit[3] & reg_we & ~wr_err;
2775:   assign control_erase_sel_wd = reg_wdata[6];
2776: 
2777:   assign control_fifo_rst_we = addr_hit[3] & reg_we & ~wr_err;
2778:   assign control_fifo_rst_wd = reg_wdata[7];
2779: 
2780:   assign control_num_we = addr_hit[3] & reg_we & ~wr_err;
2781:   assign control_num_wd = reg_wdata[27:16];
2782: 
2783:   assign addr_we = addr_hit[4] & reg_we & ~wr_err;
2784:   assign addr_wd = reg_wdata[31:0];
2785: 
2786:   assign region_cfg_regwen_we = addr_hit[5] & reg_we & ~wr_err;
2787:   assign region_cfg_regwen_wd = reg_wdata[0];
2788: 
2789:   assign mp_region_cfg0_en0_we = addr_hit[6] & reg_we & ~wr_err;
2790:   assign mp_region_cfg0_en0_wd = reg_wdata[0];
2791: 
2792:   assign mp_region_cfg0_rd_en0_we = addr_hit[6] & reg_we & ~wr_err;
2793:   assign mp_region_cfg0_rd_en0_wd = reg_wdata[1];
2794: 
2795:   assign mp_region_cfg0_prog_en0_we = addr_hit[6] & reg_we & ~wr_err;
2796:   assign mp_region_cfg0_prog_en0_wd = reg_wdata[2];
2797: 
2798:   assign mp_region_cfg0_erase_en0_we = addr_hit[6] & reg_we & ~wr_err;
2799:   assign mp_region_cfg0_erase_en0_wd = reg_wdata[3];
2800: 
2801:   assign mp_region_cfg0_base0_we = addr_hit[6] & reg_we & ~wr_err;
2802:   assign mp_region_cfg0_base0_wd = reg_wdata[12:4];
2803: 
2804:   assign mp_region_cfg0_size0_we = addr_hit[6] & reg_we & ~wr_err;
2805:   assign mp_region_cfg0_size0_wd = reg_wdata[24:16];
2806: 
2807:   assign mp_region_cfg1_en1_we = addr_hit[7] & reg_we & ~wr_err;
2808:   assign mp_region_cfg1_en1_wd = reg_wdata[0];
2809: 
2810:   assign mp_region_cfg1_rd_en1_we = addr_hit[7] & reg_we & ~wr_err;
2811:   assign mp_region_cfg1_rd_en1_wd = reg_wdata[1];
2812: 
2813:   assign mp_region_cfg1_prog_en1_we = addr_hit[7] & reg_we & ~wr_err;
2814:   assign mp_region_cfg1_prog_en1_wd = reg_wdata[2];
2815: 
2816:   assign mp_region_cfg1_erase_en1_we = addr_hit[7] & reg_we & ~wr_err;
2817:   assign mp_region_cfg1_erase_en1_wd = reg_wdata[3];
2818: 
2819:   assign mp_region_cfg1_base1_we = addr_hit[7] & reg_we & ~wr_err;
2820:   assign mp_region_cfg1_base1_wd = reg_wdata[12:4];
2821: 
2822:   assign mp_region_cfg1_size1_we = addr_hit[7] & reg_we & ~wr_err;
2823:   assign mp_region_cfg1_size1_wd = reg_wdata[24:16];
2824: 
2825:   assign mp_region_cfg2_en2_we = addr_hit[8] & reg_we & ~wr_err;
2826:   assign mp_region_cfg2_en2_wd = reg_wdata[0];
2827: 
2828:   assign mp_region_cfg2_rd_en2_we = addr_hit[8] & reg_we & ~wr_err;
2829:   assign mp_region_cfg2_rd_en2_wd = reg_wdata[1];
2830: 
2831:   assign mp_region_cfg2_prog_en2_we = addr_hit[8] & reg_we & ~wr_err;
2832:   assign mp_region_cfg2_prog_en2_wd = reg_wdata[2];
2833: 
2834:   assign mp_region_cfg2_erase_en2_we = addr_hit[8] & reg_we & ~wr_err;
2835:   assign mp_region_cfg2_erase_en2_wd = reg_wdata[3];
2836: 
2837:   assign mp_region_cfg2_base2_we = addr_hit[8] & reg_we & ~wr_err;
2838:   assign mp_region_cfg2_base2_wd = reg_wdata[12:4];
2839: 
2840:   assign mp_region_cfg2_size2_we = addr_hit[8] & reg_we & ~wr_err;
2841:   assign mp_region_cfg2_size2_wd = reg_wdata[24:16];
2842: 
2843:   assign mp_region_cfg3_en3_we = addr_hit[9] & reg_we & ~wr_err;
2844:   assign mp_region_cfg3_en3_wd = reg_wdata[0];
2845: 
2846:   assign mp_region_cfg3_rd_en3_we = addr_hit[9] & reg_we & ~wr_err;
2847:   assign mp_region_cfg3_rd_en3_wd = reg_wdata[1];
2848: 
2849:   assign mp_region_cfg3_prog_en3_we = addr_hit[9] & reg_we & ~wr_err;
2850:   assign mp_region_cfg3_prog_en3_wd = reg_wdata[2];
2851: 
2852:   assign mp_region_cfg3_erase_en3_we = addr_hit[9] & reg_we & ~wr_err;
2853:   assign mp_region_cfg3_erase_en3_wd = reg_wdata[3];
2854: 
2855:   assign mp_region_cfg3_base3_we = addr_hit[9] & reg_we & ~wr_err;
2856:   assign mp_region_cfg3_base3_wd = reg_wdata[12:4];
2857: 
2858:   assign mp_region_cfg3_size3_we = addr_hit[9] & reg_we & ~wr_err;
2859:   assign mp_region_cfg3_size3_wd = reg_wdata[24:16];
2860: 
2861:   assign mp_region_cfg4_en4_we = addr_hit[10] & reg_we & ~wr_err;
2862:   assign mp_region_cfg4_en4_wd = reg_wdata[0];
2863: 
2864:   assign mp_region_cfg4_rd_en4_we = addr_hit[10] & reg_we & ~wr_err;
2865:   assign mp_region_cfg4_rd_en4_wd = reg_wdata[1];
2866: 
2867:   assign mp_region_cfg4_prog_en4_we = addr_hit[10] & reg_we & ~wr_err;
2868:   assign mp_region_cfg4_prog_en4_wd = reg_wdata[2];
2869: 
2870:   assign mp_region_cfg4_erase_en4_we = addr_hit[10] & reg_we & ~wr_err;
2871:   assign mp_region_cfg4_erase_en4_wd = reg_wdata[3];
2872: 
2873:   assign mp_region_cfg4_base4_we = addr_hit[10] & reg_we & ~wr_err;
2874:   assign mp_region_cfg4_base4_wd = reg_wdata[12:4];
2875: 
2876:   assign mp_region_cfg4_size4_we = addr_hit[10] & reg_we & ~wr_err;
2877:   assign mp_region_cfg4_size4_wd = reg_wdata[24:16];
2878: 
2879:   assign mp_region_cfg5_en5_we = addr_hit[11] & reg_we & ~wr_err;
2880:   assign mp_region_cfg5_en5_wd = reg_wdata[0];
2881: 
2882:   assign mp_region_cfg5_rd_en5_we = addr_hit[11] & reg_we & ~wr_err;
2883:   assign mp_region_cfg5_rd_en5_wd = reg_wdata[1];
2884: 
2885:   assign mp_region_cfg5_prog_en5_we = addr_hit[11] & reg_we & ~wr_err;
2886:   assign mp_region_cfg5_prog_en5_wd = reg_wdata[2];
2887: 
2888:   assign mp_region_cfg5_erase_en5_we = addr_hit[11] & reg_we & ~wr_err;
2889:   assign mp_region_cfg5_erase_en5_wd = reg_wdata[3];
2890: 
2891:   assign mp_region_cfg5_base5_we = addr_hit[11] & reg_we & ~wr_err;
2892:   assign mp_region_cfg5_base5_wd = reg_wdata[12:4];
2893: 
2894:   assign mp_region_cfg5_size5_we = addr_hit[11] & reg_we & ~wr_err;
2895:   assign mp_region_cfg5_size5_wd = reg_wdata[24:16];
2896: 
2897:   assign mp_region_cfg6_en6_we = addr_hit[12] & reg_we & ~wr_err;
2898:   assign mp_region_cfg6_en6_wd = reg_wdata[0];
2899: 
2900:   assign mp_region_cfg6_rd_en6_we = addr_hit[12] & reg_we & ~wr_err;
2901:   assign mp_region_cfg6_rd_en6_wd = reg_wdata[1];
2902: 
2903:   assign mp_region_cfg6_prog_en6_we = addr_hit[12] & reg_we & ~wr_err;
2904:   assign mp_region_cfg6_prog_en6_wd = reg_wdata[2];
2905: 
2906:   assign mp_region_cfg6_erase_en6_we = addr_hit[12] & reg_we & ~wr_err;
2907:   assign mp_region_cfg6_erase_en6_wd = reg_wdata[3];
2908: 
2909:   assign mp_region_cfg6_base6_we = addr_hit[12] & reg_we & ~wr_err;
2910:   assign mp_region_cfg6_base6_wd = reg_wdata[12:4];
2911: 
2912:   assign mp_region_cfg6_size6_we = addr_hit[12] & reg_we & ~wr_err;
2913:   assign mp_region_cfg6_size6_wd = reg_wdata[24:16];
2914: 
2915:   assign mp_region_cfg7_en7_we = addr_hit[13] & reg_we & ~wr_err;
2916:   assign mp_region_cfg7_en7_wd = reg_wdata[0];
2917: 
2918:   assign mp_region_cfg7_rd_en7_we = addr_hit[13] & reg_we & ~wr_err;
2919:   assign mp_region_cfg7_rd_en7_wd = reg_wdata[1];
2920: 
2921:   assign mp_region_cfg7_prog_en7_we = addr_hit[13] & reg_we & ~wr_err;
2922:   assign mp_region_cfg7_prog_en7_wd = reg_wdata[2];
2923: 
2924:   assign mp_region_cfg7_erase_en7_we = addr_hit[13] & reg_we & ~wr_err;
2925:   assign mp_region_cfg7_erase_en7_wd = reg_wdata[3];
2926: 
2927:   assign mp_region_cfg7_base7_we = addr_hit[13] & reg_we & ~wr_err;
2928:   assign mp_region_cfg7_base7_wd = reg_wdata[12:4];
2929: 
2930:   assign mp_region_cfg7_size7_we = addr_hit[13] & reg_we & ~wr_err;
2931:   assign mp_region_cfg7_size7_wd = reg_wdata[24:16];
2932: 
2933:   assign default_region_rd_en_we = addr_hit[14] & reg_we & ~wr_err;
2934:   assign default_region_rd_en_wd = reg_wdata[0];
2935: 
2936:   assign default_region_prog_en_we = addr_hit[14] & reg_we & ~wr_err;
2937:   assign default_region_prog_en_wd = reg_wdata[1];
2938: 
2939:   assign default_region_erase_en_we = addr_hit[14] & reg_we & ~wr_err;
2940:   assign default_region_erase_en_wd = reg_wdata[2];
2941: 
2942:   assign bank_cfg_regwen_we = addr_hit[15] & reg_we & ~wr_err;
2943:   assign bank_cfg_regwen_wd = reg_wdata[0];
2944: 
2945:   assign mp_bank_cfg_erase_en0_we = addr_hit[16] & reg_we & ~wr_err;
2946:   assign mp_bank_cfg_erase_en0_wd = reg_wdata[0];
2947: 
2948:   assign mp_bank_cfg_erase_en1_we = addr_hit[16] & reg_we & ~wr_err;
2949:   assign mp_bank_cfg_erase_en1_wd = reg_wdata[1];
2950: 
2951:   assign op_status_done_we = addr_hit[17] & reg_we & ~wr_err;
2952:   assign op_status_done_wd = reg_wdata[0];
2953: 
2954:   assign op_status_err_we = addr_hit[17] & reg_we & ~wr_err;
2955:   assign op_status_err_wd = reg_wdata[1];
2956: 
2957:   assign status_rd_full_re = addr_hit[18] && reg_re;
2958: 
2959:   assign status_rd_empty_re = addr_hit[18] && reg_re;
2960: 
2961:   assign status_prog_full_re = addr_hit[18] && reg_re;
2962: 
2963:   assign status_prog_empty_re = addr_hit[18] && reg_re;
2964: 
2965:   assign status_init_wip_re = addr_hit[18] && reg_re;
2966: 
2967:   assign status_error_page_re = addr_hit[18] && reg_re;
2968: 
2969:   assign status_error_bank_re = addr_hit[18] && reg_re;
2970: 
2971:   assign scratch_we = addr_hit[19] & reg_we & ~wr_err;
2972:   assign scratch_wd = reg_wdata[31:0];
2973: 
2974:   assign fifo_lvl_prog_we = addr_hit[20] & reg_we & ~wr_err;
2975:   assign fifo_lvl_prog_wd = reg_wdata[4:0];
2976: 
2977:   assign fifo_lvl_rd_we = addr_hit[20] & reg_we & ~wr_err;
2978:   assign fifo_lvl_rd_wd = reg_wdata[12:8];
2979: 
2980:   // Read data return
2981:   always_comb begin
2982:     reg_rdata_next = '0;
2983:     unique case (1'b1)
2984:       addr_hit[0]: begin
2985:         reg_rdata_next[0] = intr_state_prog_empty_qs;
2986:         reg_rdata_next[1] = intr_state_prog_lvl_qs;
2987:         reg_rdata_next[2] = intr_state_rd_full_qs;
2988:         reg_rdata_next[3] = intr_state_rd_lvl_qs;
2989:         reg_rdata_next[4] = intr_state_op_done_qs;
2990:         reg_rdata_next[5] = intr_state_op_error_qs;
2991:       end
2992: 
2993:       addr_hit[1]: begin
2994:         reg_rdata_next[0] = intr_enable_prog_empty_qs;
2995:         reg_rdata_next[1] = intr_enable_prog_lvl_qs;
2996:         reg_rdata_next[2] = intr_enable_rd_full_qs;
2997:         reg_rdata_next[3] = intr_enable_rd_lvl_qs;
2998:         reg_rdata_next[4] = intr_enable_op_done_qs;
2999:         reg_rdata_next[5] = intr_enable_op_error_qs;
3000:       end
3001: 
3002:       addr_hit[2]: begin
3003:         reg_rdata_next[0] = '0;
3004:         reg_rdata_next[1] = '0;
3005:         reg_rdata_next[2] = '0;
3006:         reg_rdata_next[3] = '0;
3007:         reg_rdata_next[4] = '0;
3008:         reg_rdata_next[5] = '0;
3009:       end
3010: 
3011:       addr_hit[3]: begin
3012:         reg_rdata_next[0] = control_start_qs;
3013:         reg_rdata_next[5:4] = control_op_qs;
3014:         reg_rdata_next[6] = control_erase_sel_qs;
3015:         reg_rdata_next[7] = control_fifo_rst_qs;
3016:         reg_rdata_next[27:16] = control_num_qs;
3017:       end
3018: 
3019:       addr_hit[4]: begin
3020:         reg_rdata_next[31:0] = addr_qs;
3021:       end
3022: 
3023:       addr_hit[5]: begin
3024:         reg_rdata_next[0] = region_cfg_regwen_qs;
3025:       end
3026: 
3027:       addr_hit[6]: begin
3028:         reg_rdata_next[0] = mp_region_cfg0_en0_qs;
3029:         reg_rdata_next[1] = mp_region_cfg0_rd_en0_qs;
3030:         reg_rdata_next[2] = mp_region_cfg0_prog_en0_qs;
3031:         reg_rdata_next[3] = mp_region_cfg0_erase_en0_qs;
3032:         reg_rdata_next[12:4] = mp_region_cfg0_base0_qs;
3033:         reg_rdata_next[24:16] = mp_region_cfg0_size0_qs;
3034:       end
3035: 
3036:       addr_hit[7]: begin
3037:         reg_rdata_next[0] = mp_region_cfg1_en1_qs;
3038:         reg_rdata_next[1] = mp_region_cfg1_rd_en1_qs;
3039:         reg_rdata_next[2] = mp_region_cfg1_prog_en1_qs;
3040:         reg_rdata_next[3] = mp_region_cfg1_erase_en1_qs;
3041:         reg_rdata_next[12:4] = mp_region_cfg1_base1_qs;
3042:         reg_rdata_next[24:16] = mp_region_cfg1_size1_qs;
3043:       end
3044: 
3045:       addr_hit[8]: begin
3046:         reg_rdata_next[0] = mp_region_cfg2_en2_qs;
3047:         reg_rdata_next[1] = mp_region_cfg2_rd_en2_qs;
3048:         reg_rdata_next[2] = mp_region_cfg2_prog_en2_qs;
3049:         reg_rdata_next[3] = mp_region_cfg2_erase_en2_qs;
3050:         reg_rdata_next[12:4] = mp_region_cfg2_base2_qs;
3051:         reg_rdata_next[24:16] = mp_region_cfg2_size2_qs;
3052:       end
3053: 
3054:       addr_hit[9]: begin
3055:         reg_rdata_next[0] = mp_region_cfg3_en3_qs;
3056:         reg_rdata_next[1] = mp_region_cfg3_rd_en3_qs;
3057:         reg_rdata_next[2] = mp_region_cfg3_prog_en3_qs;
3058:         reg_rdata_next[3] = mp_region_cfg3_erase_en3_qs;
3059:         reg_rdata_next[12:4] = mp_region_cfg3_base3_qs;
3060:         reg_rdata_next[24:16] = mp_region_cfg3_size3_qs;
3061:       end
3062: 
3063:       addr_hit[10]: begin
3064:         reg_rdata_next[0] = mp_region_cfg4_en4_qs;
3065:         reg_rdata_next[1] = mp_region_cfg4_rd_en4_qs;
3066:         reg_rdata_next[2] = mp_region_cfg4_prog_en4_qs;
3067:         reg_rdata_next[3] = mp_region_cfg4_erase_en4_qs;
3068:         reg_rdata_next[12:4] = mp_region_cfg4_base4_qs;
3069:         reg_rdata_next[24:16] = mp_region_cfg4_size4_qs;
3070:       end
3071: 
3072:       addr_hit[11]: begin
3073:         reg_rdata_next[0] = mp_region_cfg5_en5_qs;
3074:         reg_rdata_next[1] = mp_region_cfg5_rd_en5_qs;
3075:         reg_rdata_next[2] = mp_region_cfg5_prog_en5_qs;
3076:         reg_rdata_next[3] = mp_region_cfg5_erase_en5_qs;
3077:         reg_rdata_next[12:4] = mp_region_cfg5_base5_qs;
3078:         reg_rdata_next[24:16] = mp_region_cfg5_size5_qs;
3079:       end
3080: 
3081:       addr_hit[12]: begin
3082:         reg_rdata_next[0] = mp_region_cfg6_en6_qs;
3083:         reg_rdata_next[1] = mp_region_cfg6_rd_en6_qs;
3084:         reg_rdata_next[2] = mp_region_cfg6_prog_en6_qs;
3085:         reg_rdata_next[3] = mp_region_cfg6_erase_en6_qs;
3086:         reg_rdata_next[12:4] = mp_region_cfg6_base6_qs;
3087:         reg_rdata_next[24:16] = mp_region_cfg6_size6_qs;
3088:       end
3089: 
3090:       addr_hit[13]: begin
3091:         reg_rdata_next[0] = mp_region_cfg7_en7_qs;
3092:         reg_rdata_next[1] = mp_region_cfg7_rd_en7_qs;
3093:         reg_rdata_next[2] = mp_region_cfg7_prog_en7_qs;
3094:         reg_rdata_next[3] = mp_region_cfg7_erase_en7_qs;
3095:         reg_rdata_next[12:4] = mp_region_cfg7_base7_qs;
3096:         reg_rdata_next[24:16] = mp_region_cfg7_size7_qs;
3097:       end
3098: 
3099:       addr_hit[14]: begin
3100:         reg_rdata_next[0] = default_region_rd_en_qs;
3101:         reg_rdata_next[1] = default_region_prog_en_qs;
3102:         reg_rdata_next[2] = default_region_erase_en_qs;
3103:       end
3104: 
3105:       addr_hit[15]: begin
3106:         reg_rdata_next[0] = bank_cfg_regwen_qs;
3107:       end
3108: 
3109:       addr_hit[16]: begin
3110:         reg_rdata_next[0] = mp_bank_cfg_erase_en0_qs;
3111:         reg_rdata_next[1] = mp_bank_cfg_erase_en1_qs;
3112:       end
3113: 
3114:       addr_hit[17]: begin
3115:         reg_rdata_next[0] = op_status_done_qs;
3116:         reg_rdata_next[1] = op_status_err_qs;
3117:       end
3118: 
3119:       addr_hit[18]: begin
3120:         reg_rdata_next[0] = status_rd_full_qs;
3121:         reg_rdata_next[1] = status_rd_empty_qs;
3122:         reg_rdata_next[2] = status_prog_full_qs;
3123:         reg_rdata_next[3] = status_prog_empty_qs;
3124:         reg_rdata_next[4] = status_init_wip_qs;
3125:         reg_rdata_next[16:8] = status_error_page_qs;
3126:         reg_rdata_next[17] = status_error_bank_qs;
3127:       end
3128: 
3129:       addr_hit[19]: begin
3130:         reg_rdata_next[31:0] = scratch_qs;
3131:       end
3132: 
3133:       addr_hit[20]: begin
3134:         reg_rdata_next[4:0] = fifo_lvl_prog_qs;
3135:         reg_rdata_next[12:8] = fifo_lvl_rd_qs;
3136:       end
3137: 
3138:       default: begin
3139:         reg_rdata_next = '1;
3140:       end
3141:     endcase
3142:   end
3143: 
3144:   // Assertions for Register Interface
3145:   `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
3146:   `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
3147: 
3148:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
3149: 
3150:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
3151: 
3152:   // this is formulated as an assumption such that the FPV testbenches do disprove this
3153:   // property by mistake
3154:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
3155: 
3156: endmodule
3157: