hw/top_earlgrey/rtl/clkgen_xil7series.sv Cov: 79%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4:
5: module clkgen_xil7series (
6: input IO_CLK,
7: input IO_RST_N,
8: output clk_sys,
9: output clk_48MHz,
10: output rst_sys_n
11: );
12: logic locked_pll;
13: logic io_clk_buf;
14: logic clk_50_buf;
15: logic clk_50_unbuf;
16: logic clk_fb_buf;
17: logic clk_fb_unbuf;
18: logic clk_48_buf;
19: logic clk_48_unbuf;
20:
21: // input buffer
22: IBUF io_clk_ibuf (
23: .I (IO_CLK),
24: .O (io_clk_buf)
25: );
26:
27: PLLE2_ADV #(
28: .BANDWIDTH ("OPTIMIZED"),
29: .COMPENSATION ("ZHOLD"),
30: .STARTUP_WAIT ("FALSE"),
31: .DIVCLK_DIVIDE (1),
32: .CLKFBOUT_MULT (12),
33: .CLKFBOUT_PHASE (0.000),
34: .CLKOUT0_DIVIDE (24),
35: .CLKOUT0_PHASE (0.000),
36: .CLKOUT0_DUTY_CYCLE (0.500),
37: .CLKOUT1_DIVIDE (25),
38: .CLKOUT1_PHASE (0.000),
39: .CLKOUT1_DUTY_CYCLE (0.500),
40: .CLKIN1_PERIOD (10.000)
41: ) pll (
42: .CLKFBOUT (clk_fb_unbuf),
43: .CLKOUT0 (clk_50_unbuf),
44: .CLKOUT1 (clk_48_unbuf),
45: .CLKOUT2 (),
46: .CLKOUT3 (),
47: .CLKOUT4 (),
48: .CLKOUT5 (),
49: // Input clock control
50: .CLKFBIN (clk_fb_buf),
51: .CLKIN1 (io_clk_buf),
52: .CLKIN2 (1'b0),
53: // Tied to always select the primary input clock
54: .CLKINSEL (1'b1),
55: // Ports for dynamic reconfiguration
56: .DADDR (7'h0),
57: .DCLK (1'b0),
58: .DEN (1'b0),
59: .DI (16'h0),
60: .DO (),
61: .DRDY (),
62: .DWE (1'b0),
63: // Other control and status signals
64: .LOCKED (locked_pll),
65: .PWRDWN (1'b0),
66: // Do not reset PLL on external reset, otherwise ILA disconnects at a reset
67: .RST (1'b0));
68:
69: // output buffering
70: BUFG clk_fb_bufg (
71: .I (clk_fb_unbuf),
72: .O (clk_fb_buf)
73: );
74:
75: BUFG clk_50_bufg (
76: .I (clk_50_unbuf),
77: .O (clk_50_buf)
78: );
79:
80: BUFG clk_48_bufg (
81: .I (clk_48_unbuf),
82: .O (clk_48_buf)
83: );
84:
85: // outputs
86: // clock
87: assign clk_sys = clk_50_buf; // TODO: choose 50 MHz clock as sysclock for now
88: assign clk_48MHz = clk_48_buf;
89:
90: // reset
91: assign rst_sys_n = locked_pll & IO_RST_N;
92: endmodule
93: