../src/lowrisc_top_earlgrey_padctrl_reg_0.1/rtl/autogen/padctrl_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module padctrl_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16: // To HW
17: output padctrl_reg_pkg::padctrl_reg2hw_t reg2hw, // Write
18: input padctrl_reg_pkg::padctrl_hw2reg_t hw2reg, // Read
19:
20: // Config
21: input devmode_i // If 1, explicit error return for unmapped register access
22: );
23:
24: import padctrl_reg_pkg::* ;
25:
26: localparam int AW = 6;
27: localparam int DW = 32;
28: localparam int DBW = DW/8; // Byte Width
29:
30: // register signals
31: logic reg_we;
32: logic reg_re;
33: logic [AW-1:0] reg_addr;
34: logic [DW-1:0] reg_wdata;
35: logic [DBW-1:0] reg_be;
36: logic [DW-1:0] reg_rdata;
37: logic reg_error;
38:
39: logic addrmiss, wr_err;
40:
41: logic [DW-1:0] reg_rdata_next;
42:
43: tlul_pkg::tl_h2d_t tl_reg_h2d;
44: tlul_pkg::tl_d2h_t tl_reg_d2h;
45:
46: assign tl_reg_h2d = tl_i;
47: assign tl_o = tl_reg_d2h;
48:
49: tlul_adapter_reg #(
50: .RegAw(AW),
51: .RegDw(DW)
52: ) u_reg_if (
53: .clk_i,
54: .rst_ni,
55:
56: .tl_i (tl_reg_h2d),
57: .tl_o (tl_reg_d2h),
58:
59: .we_o (reg_we),
60: .re_o (reg_re),
61: .addr_o (reg_addr),
62: .wdata_o (reg_wdata),
63: .be_o (reg_be),
64: .rdata_i (reg_rdata),
65: .error_i (reg_error)
66: );
67:
68: assign reg_rdata = reg_rdata_next ;
69: assign reg_error = (devmode_i & addrmiss) | wr_err ;
70:
71: // Define SW related signals
72: // Format: __{wd|we|qs}
73: // or _{wd|we|qs} if field == 1 or 0
74: logic regen_qs;
75: logic regen_wd;
76: logic regen_we;
77: logic [7:0] dio_pads0_attr0_qs;
78: logic [7:0] dio_pads0_attr0_wd;
79: logic dio_pads0_attr0_we;
80: logic dio_pads0_attr0_re;
81: logic [7:0] dio_pads0_attr1_qs;
82: logic [7:0] dio_pads0_attr1_wd;
83: logic dio_pads0_attr1_we;
84: logic dio_pads0_attr1_re;
85: logic [7:0] dio_pads0_attr2_qs;
86: logic [7:0] dio_pads0_attr2_wd;
87: logic dio_pads0_attr2_we;
88: logic dio_pads0_attr2_re;
89: logic [7:0] dio_pads0_attr3_qs;
90: logic [7:0] dio_pads0_attr3_wd;
91: logic dio_pads0_attr3_we;
92: logic dio_pads0_attr3_re;
93: logic [7:0] dio_pads1_attr4_qs;
94: logic [7:0] dio_pads1_attr4_wd;
95: logic dio_pads1_attr4_we;
96: logic dio_pads1_attr4_re;
97: logic [7:0] dio_pads1_attr5_qs;
98: logic [7:0] dio_pads1_attr5_wd;
99: logic dio_pads1_attr5_we;
100: logic dio_pads1_attr5_re;
101: logic [7:0] dio_pads1_attr6_qs;
102: logic [7:0] dio_pads1_attr6_wd;
103: logic dio_pads1_attr6_we;
104: logic dio_pads1_attr6_re;
105: logic [7:0] dio_pads1_attr7_qs;
106: logic [7:0] dio_pads1_attr7_wd;
107: logic dio_pads1_attr7_we;
108: logic dio_pads1_attr7_re;
109: logic [7:0] dio_pads2_attr8_qs;
110: logic [7:0] dio_pads2_attr8_wd;
111: logic dio_pads2_attr8_we;
112: logic dio_pads2_attr8_re;
113: logic [7:0] dio_pads2_attr9_qs;
114: logic [7:0] dio_pads2_attr9_wd;
115: logic dio_pads2_attr9_we;
116: logic dio_pads2_attr9_re;
117: logic [7:0] dio_pads2_attr10_qs;
118: logic [7:0] dio_pads2_attr10_wd;
119: logic dio_pads2_attr10_we;
120: logic dio_pads2_attr10_re;
121: logic [7:0] dio_pads2_attr11_qs;
122: logic [7:0] dio_pads2_attr11_wd;
123: logic dio_pads2_attr11_we;
124: logic dio_pads2_attr11_re;
125: logic [7:0] dio_pads3_attr12_qs;
126: logic [7:0] dio_pads3_attr12_wd;
127: logic dio_pads3_attr12_we;
128: logic dio_pads3_attr12_re;
129: logic [7:0] dio_pads3_attr13_qs;
130: logic [7:0] dio_pads3_attr13_wd;
131: logic dio_pads3_attr13_we;
132: logic dio_pads3_attr13_re;
133: logic [7:0] dio_pads3_attr14_qs;
134: logic [7:0] dio_pads3_attr14_wd;
135: logic dio_pads3_attr14_we;
136: logic dio_pads3_attr14_re;
137: logic [7:0] mio_pads0_attr0_qs;
138: logic [7:0] mio_pads0_attr0_wd;
139: logic mio_pads0_attr0_we;
140: logic mio_pads0_attr0_re;
141: logic [7:0] mio_pads0_attr1_qs;
142: logic [7:0] mio_pads0_attr1_wd;
143: logic mio_pads0_attr1_we;
144: logic mio_pads0_attr1_re;
145: logic [7:0] mio_pads0_attr2_qs;
146: logic [7:0] mio_pads0_attr2_wd;
147: logic mio_pads0_attr2_we;
148: logic mio_pads0_attr2_re;
149: logic [7:0] mio_pads0_attr3_qs;
150: logic [7:0] mio_pads0_attr3_wd;
151: logic mio_pads0_attr3_we;
152: logic mio_pads0_attr3_re;
153: logic [7:0] mio_pads1_attr4_qs;
154: logic [7:0] mio_pads1_attr4_wd;
155: logic mio_pads1_attr4_we;
156: logic mio_pads1_attr4_re;
157: logic [7:0] mio_pads1_attr5_qs;
158: logic [7:0] mio_pads1_attr5_wd;
159: logic mio_pads1_attr5_we;
160: logic mio_pads1_attr5_re;
161: logic [7:0] mio_pads1_attr6_qs;
162: logic [7:0] mio_pads1_attr6_wd;
163: logic mio_pads1_attr6_we;
164: logic mio_pads1_attr6_re;
165: logic [7:0] mio_pads1_attr7_qs;
166: logic [7:0] mio_pads1_attr7_wd;
167: logic mio_pads1_attr7_we;
168: logic mio_pads1_attr7_re;
169: logic [7:0] mio_pads2_attr8_qs;
170: logic [7:0] mio_pads2_attr8_wd;
171: logic mio_pads2_attr8_we;
172: logic mio_pads2_attr8_re;
173: logic [7:0] mio_pads2_attr9_qs;
174: logic [7:0] mio_pads2_attr9_wd;
175: logic mio_pads2_attr9_we;
176: logic mio_pads2_attr9_re;
177: logic [7:0] mio_pads2_attr10_qs;
178: logic [7:0] mio_pads2_attr10_wd;
179: logic mio_pads2_attr10_we;
180: logic mio_pads2_attr10_re;
181: logic [7:0] mio_pads2_attr11_qs;
182: logic [7:0] mio_pads2_attr11_wd;
183: logic mio_pads2_attr11_we;
184: logic mio_pads2_attr11_re;
185: logic [7:0] mio_pads3_attr12_qs;
186: logic [7:0] mio_pads3_attr12_wd;
187: logic mio_pads3_attr12_we;
188: logic mio_pads3_attr12_re;
189: logic [7:0] mio_pads3_attr13_qs;
190: logic [7:0] mio_pads3_attr13_wd;
191: logic mio_pads3_attr13_we;
192: logic mio_pads3_attr13_re;
193: logic [7:0] mio_pads3_attr14_qs;
194: logic [7:0] mio_pads3_attr14_wd;
195: logic mio_pads3_attr14_we;
196: logic mio_pads3_attr14_re;
197: logic [7:0] mio_pads3_attr15_qs;
198: logic [7:0] mio_pads3_attr15_wd;
199: logic mio_pads3_attr15_we;
200: logic mio_pads3_attr15_re;
201: logic [7:0] mio_pads4_attr16_qs;
202: logic [7:0] mio_pads4_attr16_wd;
203: logic mio_pads4_attr16_we;
204: logic mio_pads4_attr16_re;
205: logic [7:0] mio_pads4_attr17_qs;
206: logic [7:0] mio_pads4_attr17_wd;
207: logic mio_pads4_attr17_we;
208: logic mio_pads4_attr17_re;
209: logic [7:0] mio_pads4_attr18_qs;
210: logic [7:0] mio_pads4_attr18_wd;
211: logic mio_pads4_attr18_we;
212: logic mio_pads4_attr18_re;
213: logic [7:0] mio_pads4_attr19_qs;
214: logic [7:0] mio_pads4_attr19_wd;
215: logic mio_pads4_attr19_we;
216: logic mio_pads4_attr19_re;
217: logic [7:0] mio_pads5_attr20_qs;
218: logic [7:0] mio_pads5_attr20_wd;
219: logic mio_pads5_attr20_we;
220: logic mio_pads5_attr20_re;
221: logic [7:0] mio_pads5_attr21_qs;
222: logic [7:0] mio_pads5_attr21_wd;
223: logic mio_pads5_attr21_we;
224: logic mio_pads5_attr21_re;
225: logic [7:0] mio_pads5_attr22_qs;
226: logic [7:0] mio_pads5_attr22_wd;
227: logic mio_pads5_attr22_we;
228: logic mio_pads5_attr22_re;
229: logic [7:0] mio_pads5_attr23_qs;
230: logic [7:0] mio_pads5_attr23_wd;
231: logic mio_pads5_attr23_we;
232: logic mio_pads5_attr23_re;
233: logic [7:0] mio_pads6_attr24_qs;
234: logic [7:0] mio_pads6_attr24_wd;
235: logic mio_pads6_attr24_we;
236: logic mio_pads6_attr24_re;
237: logic [7:0] mio_pads6_attr25_qs;
238: logic [7:0] mio_pads6_attr25_wd;
239: logic mio_pads6_attr25_we;
240: logic mio_pads6_attr25_re;
241: logic [7:0] mio_pads6_attr26_qs;
242: logic [7:0] mio_pads6_attr26_wd;
243: logic mio_pads6_attr26_we;
244: logic mio_pads6_attr26_re;
245: logic [7:0] mio_pads6_attr27_qs;
246: logic [7:0] mio_pads6_attr27_wd;
247: logic mio_pads6_attr27_we;
248: logic mio_pads6_attr27_re;
249: logic [7:0] mio_pads7_attr28_qs;
250: logic [7:0] mio_pads7_attr28_wd;
251: logic mio_pads7_attr28_we;
252: logic mio_pads7_attr28_re;
253: logic [7:0] mio_pads7_attr29_qs;
254: logic [7:0] mio_pads7_attr29_wd;
255: logic mio_pads7_attr29_we;
256: logic mio_pads7_attr29_re;
257: logic [7:0] mio_pads7_attr30_qs;
258: logic [7:0] mio_pads7_attr30_wd;
259: logic mio_pads7_attr30_we;
260: logic mio_pads7_attr30_re;
261: logic [7:0] mio_pads7_attr31_qs;
262: logic [7:0] mio_pads7_attr31_wd;
263: logic mio_pads7_attr31_we;
264: logic mio_pads7_attr31_re;
265:
266: // Register instances
267: // R[regen]: V(False)
268:
269: prim_subreg #(
270: .DW (1),
271: .SWACCESS("W0C"),
272: .RESVAL (1'h1)
273: ) u_regen (
274: .clk_i (clk_i ),
275: .rst_ni (rst_ni ),
276:
277: // from register interface
278: .we (regen_we),
279: .wd (regen_wd),
280:
281: // from internal hardware
282: .de (1'b0),
283: .d ('0 ),
284:
285: // to internal hardware
286: .qe (),
287: .q (),
288:
289: // to register interface (read)
290: .qs (regen_qs)
291: );
292:
293:
294:
295: // Subregister 0 of Multireg dio_pads
296: // R[dio_pads0]: V(True)
297:
298: // F[attr0]: 7:0
299: prim_subreg_ext #(
300: .DW (8)
301: ) u_dio_pads0_attr0 (
302: .re (dio_pads0_attr0_re),
303: // qualified with register enable
304: .we (dio_pads0_attr0_we & regen_qs),
305: .wd (dio_pads0_attr0_wd),
306: .d (hw2reg.dio_pads[0].d),
307: .qre (),
308: .qe (reg2hw.dio_pads[0].qe),
309: .q (reg2hw.dio_pads[0].q ),
310: .qs (dio_pads0_attr0_qs)
311: );
312:
313:
314: // F[attr1]: 15:8
315: prim_subreg_ext #(
316: .DW (8)
317: ) u_dio_pads0_attr1 (
318: .re (dio_pads0_attr1_re),
319: // qualified with register enable
320: .we (dio_pads0_attr1_we & regen_qs),
321: .wd (dio_pads0_attr1_wd),
322: .d (hw2reg.dio_pads[1].d),
323: .qre (),
324: .qe (reg2hw.dio_pads[1].qe),
325: .q (reg2hw.dio_pads[1].q ),
326: .qs (dio_pads0_attr1_qs)
327: );
328:
329:
330: // F[attr2]: 23:16
331: prim_subreg_ext #(
332: .DW (8)
333: ) u_dio_pads0_attr2 (
334: .re (dio_pads0_attr2_re),
335: // qualified with register enable
336: .we (dio_pads0_attr2_we & regen_qs),
337: .wd (dio_pads0_attr2_wd),
338: .d (hw2reg.dio_pads[2].d),
339: .qre (),
340: .qe (reg2hw.dio_pads[2].qe),
341: .q (reg2hw.dio_pads[2].q ),
342: .qs (dio_pads0_attr2_qs)
343: );
344:
345:
346: // F[attr3]: 31:24
347: prim_subreg_ext #(
348: .DW (8)
349: ) u_dio_pads0_attr3 (
350: .re (dio_pads0_attr3_re),
351: // qualified with register enable
352: .we (dio_pads0_attr3_we & regen_qs),
353: .wd (dio_pads0_attr3_wd),
354: .d (hw2reg.dio_pads[3].d),
355: .qre (),
356: .qe (reg2hw.dio_pads[3].qe),
357: .q (reg2hw.dio_pads[3].q ),
358: .qs (dio_pads0_attr3_qs)
359: );
360:
361:
362: // Subregister 4 of Multireg dio_pads
363: // R[dio_pads1]: V(True)
364:
365: // F[attr4]: 7:0
366: prim_subreg_ext #(
367: .DW (8)
368: ) u_dio_pads1_attr4 (
369: .re (dio_pads1_attr4_re),
370: // qualified with register enable
371: .we (dio_pads1_attr4_we & regen_qs),
372: .wd (dio_pads1_attr4_wd),
373: .d (hw2reg.dio_pads[4].d),
374: .qre (),
375: .qe (reg2hw.dio_pads[4].qe),
376: .q (reg2hw.dio_pads[4].q ),
377: .qs (dio_pads1_attr4_qs)
378: );
379:
380:
381: // F[attr5]: 15:8
382: prim_subreg_ext #(
383: .DW (8)
384: ) u_dio_pads1_attr5 (
385: .re (dio_pads1_attr5_re),
386: // qualified with register enable
387: .we (dio_pads1_attr5_we & regen_qs),
388: .wd (dio_pads1_attr5_wd),
389: .d (hw2reg.dio_pads[5].d),
390: .qre (),
391: .qe (reg2hw.dio_pads[5].qe),
392: .q (reg2hw.dio_pads[5].q ),
393: .qs (dio_pads1_attr5_qs)
394: );
395:
396:
397: // F[attr6]: 23:16
398: prim_subreg_ext #(
399: .DW (8)
400: ) u_dio_pads1_attr6 (
401: .re (dio_pads1_attr6_re),
402: // qualified with register enable
403: .we (dio_pads1_attr6_we & regen_qs),
404: .wd (dio_pads1_attr6_wd),
405: .d (hw2reg.dio_pads[6].d),
406: .qre (),
407: .qe (reg2hw.dio_pads[6].qe),
408: .q (reg2hw.dio_pads[6].q ),
409: .qs (dio_pads1_attr6_qs)
410: );
411:
412:
413: // F[attr7]: 31:24
414: prim_subreg_ext #(
415: .DW (8)
416: ) u_dio_pads1_attr7 (
417: .re (dio_pads1_attr7_re),
418: // qualified with register enable
419: .we (dio_pads1_attr7_we & regen_qs),
420: .wd (dio_pads1_attr7_wd),
421: .d (hw2reg.dio_pads[7].d),
422: .qre (),
423: .qe (reg2hw.dio_pads[7].qe),
424: .q (reg2hw.dio_pads[7].q ),
425: .qs (dio_pads1_attr7_qs)
426: );
427:
428:
429: // Subregister 8 of Multireg dio_pads
430: // R[dio_pads2]: V(True)
431:
432: // F[attr8]: 7:0
433: prim_subreg_ext #(
434: .DW (8)
435: ) u_dio_pads2_attr8 (
436: .re (dio_pads2_attr8_re),
437: // qualified with register enable
438: .we (dio_pads2_attr8_we & regen_qs),
439: .wd (dio_pads2_attr8_wd),
440: .d (hw2reg.dio_pads[8].d),
441: .qre (),
442: .qe (reg2hw.dio_pads[8].qe),
443: .q (reg2hw.dio_pads[8].q ),
444: .qs (dio_pads2_attr8_qs)
445: );
446:
447:
448: // F[attr9]: 15:8
449: prim_subreg_ext #(
450: .DW (8)
451: ) u_dio_pads2_attr9 (
452: .re (dio_pads2_attr9_re),
453: // qualified with register enable
454: .we (dio_pads2_attr9_we & regen_qs),
455: .wd (dio_pads2_attr9_wd),
456: .d (hw2reg.dio_pads[9].d),
457: .qre (),
458: .qe (reg2hw.dio_pads[9].qe),
459: .q (reg2hw.dio_pads[9].q ),
460: .qs (dio_pads2_attr9_qs)
461: );
462:
463:
464: // F[attr10]: 23:16
465: prim_subreg_ext #(
466: .DW (8)
467: ) u_dio_pads2_attr10 (
468: .re (dio_pads2_attr10_re),
469: // qualified with register enable
470: .we (dio_pads2_attr10_we & regen_qs),
471: .wd (dio_pads2_attr10_wd),
472: .d (hw2reg.dio_pads[10].d),
473: .qre (),
474: .qe (reg2hw.dio_pads[10].qe),
475: .q (reg2hw.dio_pads[10].q ),
476: .qs (dio_pads2_attr10_qs)
477: );
478:
479:
480: // F[attr11]: 31:24
481: prim_subreg_ext #(
482: .DW (8)
483: ) u_dio_pads2_attr11 (
484: .re (dio_pads2_attr11_re),
485: // qualified with register enable
486: .we (dio_pads2_attr11_we & regen_qs),
487: .wd (dio_pads2_attr11_wd),
488: .d (hw2reg.dio_pads[11].d),
489: .qre (),
490: .qe (reg2hw.dio_pads[11].qe),
491: .q (reg2hw.dio_pads[11].q ),
492: .qs (dio_pads2_attr11_qs)
493: );
494:
495:
496: // Subregister 12 of Multireg dio_pads
497: // R[dio_pads3]: V(True)
498:
499: // F[attr12]: 7:0
500: prim_subreg_ext #(
501: .DW (8)
502: ) u_dio_pads3_attr12 (
503: .re (dio_pads3_attr12_re),
504: // qualified with register enable
505: .we (dio_pads3_attr12_we & regen_qs),
506: .wd (dio_pads3_attr12_wd),
507: .d (hw2reg.dio_pads[12].d),
508: .qre (),
509: .qe (reg2hw.dio_pads[12].qe),
510: .q (reg2hw.dio_pads[12].q ),
511: .qs (dio_pads3_attr12_qs)
512: );
513:
514:
515: // F[attr13]: 15:8
516: prim_subreg_ext #(
517: .DW (8)
518: ) u_dio_pads3_attr13 (
519: .re (dio_pads3_attr13_re),
520: // qualified with register enable
521: .we (dio_pads3_attr13_we & regen_qs),
522: .wd (dio_pads3_attr13_wd),
523: .d (hw2reg.dio_pads[13].d),
524: .qre (),
525: .qe (reg2hw.dio_pads[13].qe),
526: .q (reg2hw.dio_pads[13].q ),
527: .qs (dio_pads3_attr13_qs)
528: );
529:
530:
531: // F[attr14]: 23:16
532: prim_subreg_ext #(
533: .DW (8)
534: ) u_dio_pads3_attr14 (
535: .re (dio_pads3_attr14_re),
536: // qualified with register enable
537: .we (dio_pads3_attr14_we & regen_qs),
538: .wd (dio_pads3_attr14_wd),
539: .d (hw2reg.dio_pads[14].d),
540: .qre (),
541: .qe (reg2hw.dio_pads[14].qe),
542: .q (reg2hw.dio_pads[14].q ),
543: .qs (dio_pads3_attr14_qs)
544: );
545:
546:
547:
548:
549: // Subregister 0 of Multireg mio_pads
550: // R[mio_pads0]: V(True)
551:
552: // F[attr0]: 7:0
553: prim_subreg_ext #(
554: .DW (8)
555: ) u_mio_pads0_attr0 (
556: .re (mio_pads0_attr0_re),
557: // qualified with register enable
558: .we (mio_pads0_attr0_we & regen_qs),
559: .wd (mio_pads0_attr0_wd),
560: .d (hw2reg.mio_pads[0].d),
561: .qre (),
562: .qe (reg2hw.mio_pads[0].qe),
563: .q (reg2hw.mio_pads[0].q ),
564: .qs (mio_pads0_attr0_qs)
565: );
566:
567:
568: // F[attr1]: 15:8
569: prim_subreg_ext #(
570: .DW (8)
571: ) u_mio_pads0_attr1 (
572: .re (mio_pads0_attr1_re),
573: // qualified with register enable
574: .we (mio_pads0_attr1_we & regen_qs),
575: .wd (mio_pads0_attr1_wd),
576: .d (hw2reg.mio_pads[1].d),
577: .qre (),
578: .qe (reg2hw.mio_pads[1].qe),
579: .q (reg2hw.mio_pads[1].q ),
580: .qs (mio_pads0_attr1_qs)
581: );
582:
583:
584: // F[attr2]: 23:16
585: prim_subreg_ext #(
586: .DW (8)
587: ) u_mio_pads0_attr2 (
588: .re (mio_pads0_attr2_re),
589: // qualified with register enable
590: .we (mio_pads0_attr2_we & regen_qs),
591: .wd (mio_pads0_attr2_wd),
592: .d (hw2reg.mio_pads[2].d),
593: .qre (),
594: .qe (reg2hw.mio_pads[2].qe),
595: .q (reg2hw.mio_pads[2].q ),
596: .qs (mio_pads0_attr2_qs)
597: );
598:
599:
600: // F[attr3]: 31:24
601: prim_subreg_ext #(
602: .DW (8)
603: ) u_mio_pads0_attr3 (
604: .re (mio_pads0_attr3_re),
605: // qualified with register enable
606: .we (mio_pads0_attr3_we & regen_qs),
607: .wd (mio_pads0_attr3_wd),
608: .d (hw2reg.mio_pads[3].d),
609: .qre (),
610: .qe (reg2hw.mio_pads[3].qe),
611: .q (reg2hw.mio_pads[3].q ),
612: .qs (mio_pads0_attr3_qs)
613: );
614:
615:
616: // Subregister 4 of Multireg mio_pads
617: // R[mio_pads1]: V(True)
618:
619: // F[attr4]: 7:0
620: prim_subreg_ext #(
621: .DW (8)
622: ) u_mio_pads1_attr4 (
623: .re (mio_pads1_attr4_re),
624: // qualified with register enable
625: .we (mio_pads1_attr4_we & regen_qs),
626: .wd (mio_pads1_attr4_wd),
627: .d (hw2reg.mio_pads[4].d),
628: .qre (),
629: .qe (reg2hw.mio_pads[4].qe),
630: .q (reg2hw.mio_pads[4].q ),
631: .qs (mio_pads1_attr4_qs)
632: );
633:
634:
635: // F[attr5]: 15:8
636: prim_subreg_ext #(
637: .DW (8)
638: ) u_mio_pads1_attr5 (
639: .re (mio_pads1_attr5_re),
640: // qualified with register enable
641: .we (mio_pads1_attr5_we & regen_qs),
642: .wd (mio_pads1_attr5_wd),
643: .d (hw2reg.mio_pads[5].d),
644: .qre (),
645: .qe (reg2hw.mio_pads[5].qe),
646: .q (reg2hw.mio_pads[5].q ),
647: .qs (mio_pads1_attr5_qs)
648: );
649:
650:
651: // F[attr6]: 23:16
652: prim_subreg_ext #(
653: .DW (8)
654: ) u_mio_pads1_attr6 (
655: .re (mio_pads1_attr6_re),
656: // qualified with register enable
657: .we (mio_pads1_attr6_we & regen_qs),
658: .wd (mio_pads1_attr6_wd),
659: .d (hw2reg.mio_pads[6].d),
660: .qre (),
661: .qe (reg2hw.mio_pads[6].qe),
662: .q (reg2hw.mio_pads[6].q ),
663: .qs (mio_pads1_attr6_qs)
664: );
665:
666:
667: // F[attr7]: 31:24
668: prim_subreg_ext #(
669: .DW (8)
670: ) u_mio_pads1_attr7 (
671: .re (mio_pads1_attr7_re),
672: // qualified with register enable
673: .we (mio_pads1_attr7_we & regen_qs),
674: .wd (mio_pads1_attr7_wd),
675: .d (hw2reg.mio_pads[7].d),
676: .qre (),
677: .qe (reg2hw.mio_pads[7].qe),
678: .q (reg2hw.mio_pads[7].q ),
679: .qs (mio_pads1_attr7_qs)
680: );
681:
682:
683: // Subregister 8 of Multireg mio_pads
684: // R[mio_pads2]: V(True)
685:
686: // F[attr8]: 7:0
687: prim_subreg_ext #(
688: .DW (8)
689: ) u_mio_pads2_attr8 (
690: .re (mio_pads2_attr8_re),
691: // qualified with register enable
692: .we (mio_pads2_attr8_we & regen_qs),
693: .wd (mio_pads2_attr8_wd),
694: .d (hw2reg.mio_pads[8].d),
695: .qre (),
696: .qe (reg2hw.mio_pads[8].qe),
697: .q (reg2hw.mio_pads[8].q ),
698: .qs (mio_pads2_attr8_qs)
699: );
700:
701:
702: // F[attr9]: 15:8
703: prim_subreg_ext #(
704: .DW (8)
705: ) u_mio_pads2_attr9 (
706: .re (mio_pads2_attr9_re),
707: // qualified with register enable
708: .we (mio_pads2_attr9_we & regen_qs),
709: .wd (mio_pads2_attr9_wd),
710: .d (hw2reg.mio_pads[9].d),
711: .qre (),
712: .qe (reg2hw.mio_pads[9].qe),
713: .q (reg2hw.mio_pads[9].q ),
714: .qs (mio_pads2_attr9_qs)
715: );
716:
717:
718: // F[attr10]: 23:16
719: prim_subreg_ext #(
720: .DW (8)
721: ) u_mio_pads2_attr10 (
722: .re (mio_pads2_attr10_re),
723: // qualified with register enable
724: .we (mio_pads2_attr10_we & regen_qs),
725: .wd (mio_pads2_attr10_wd),
726: .d (hw2reg.mio_pads[10].d),
727: .qre (),
728: .qe (reg2hw.mio_pads[10].qe),
729: .q (reg2hw.mio_pads[10].q ),
730: .qs (mio_pads2_attr10_qs)
731: );
732:
733:
734: // F[attr11]: 31:24
735: prim_subreg_ext #(
736: .DW (8)
737: ) u_mio_pads2_attr11 (
738: .re (mio_pads2_attr11_re),
739: // qualified with register enable
740: .we (mio_pads2_attr11_we & regen_qs),
741: .wd (mio_pads2_attr11_wd),
742: .d (hw2reg.mio_pads[11].d),
743: .qre (),
744: .qe (reg2hw.mio_pads[11].qe),
745: .q (reg2hw.mio_pads[11].q ),
746: .qs (mio_pads2_attr11_qs)
747: );
748:
749:
750: // Subregister 12 of Multireg mio_pads
751: // R[mio_pads3]: V(True)
752:
753: // F[attr12]: 7:0
754: prim_subreg_ext #(
755: .DW (8)
756: ) u_mio_pads3_attr12 (
757: .re (mio_pads3_attr12_re),
758: // qualified with register enable
759: .we (mio_pads3_attr12_we & regen_qs),
760: .wd (mio_pads3_attr12_wd),
761: .d (hw2reg.mio_pads[12].d),
762: .qre (),
763: .qe (reg2hw.mio_pads[12].qe),
764: .q (reg2hw.mio_pads[12].q ),
765: .qs (mio_pads3_attr12_qs)
766: );
767:
768:
769: // F[attr13]: 15:8
770: prim_subreg_ext #(
771: .DW (8)
772: ) u_mio_pads3_attr13 (
773: .re (mio_pads3_attr13_re),
774: // qualified with register enable
775: .we (mio_pads3_attr13_we & regen_qs),
776: .wd (mio_pads3_attr13_wd),
777: .d (hw2reg.mio_pads[13].d),
778: .qre (),
779: .qe (reg2hw.mio_pads[13].qe),
780: .q (reg2hw.mio_pads[13].q ),
781: .qs (mio_pads3_attr13_qs)
782: );
783:
784:
785: // F[attr14]: 23:16
786: prim_subreg_ext #(
787: .DW (8)
788: ) u_mio_pads3_attr14 (
789: .re (mio_pads3_attr14_re),
790: // qualified with register enable
791: .we (mio_pads3_attr14_we & regen_qs),
792: .wd (mio_pads3_attr14_wd),
793: .d (hw2reg.mio_pads[14].d),
794: .qre (),
795: .qe (reg2hw.mio_pads[14].qe),
796: .q (reg2hw.mio_pads[14].q ),
797: .qs (mio_pads3_attr14_qs)
798: );
799:
800:
801: // F[attr15]: 31:24
802: prim_subreg_ext #(
803: .DW (8)
804: ) u_mio_pads3_attr15 (
805: .re (mio_pads3_attr15_re),
806: // qualified with register enable
807: .we (mio_pads3_attr15_we & regen_qs),
808: .wd (mio_pads3_attr15_wd),
809: .d (hw2reg.mio_pads[15].d),
810: .qre (),
811: .qe (reg2hw.mio_pads[15].qe),
812: .q (reg2hw.mio_pads[15].q ),
813: .qs (mio_pads3_attr15_qs)
814: );
815:
816:
817: // Subregister 16 of Multireg mio_pads
818: // R[mio_pads4]: V(True)
819:
820: // F[attr16]: 7:0
821: prim_subreg_ext #(
822: .DW (8)
823: ) u_mio_pads4_attr16 (
824: .re (mio_pads4_attr16_re),
825: // qualified with register enable
826: .we (mio_pads4_attr16_we & regen_qs),
827: .wd (mio_pads4_attr16_wd),
828: .d (hw2reg.mio_pads[16].d),
829: .qre (),
830: .qe (reg2hw.mio_pads[16].qe),
831: .q (reg2hw.mio_pads[16].q ),
832: .qs (mio_pads4_attr16_qs)
833: );
834:
835:
836: // F[attr17]: 15:8
837: prim_subreg_ext #(
838: .DW (8)
839: ) u_mio_pads4_attr17 (
840: .re (mio_pads4_attr17_re),
841: // qualified with register enable
842: .we (mio_pads4_attr17_we & regen_qs),
843: .wd (mio_pads4_attr17_wd),
844: .d (hw2reg.mio_pads[17].d),
845: .qre (),
846: .qe (reg2hw.mio_pads[17].qe),
847: .q (reg2hw.mio_pads[17].q ),
848: .qs (mio_pads4_attr17_qs)
849: );
850:
851:
852: // F[attr18]: 23:16
853: prim_subreg_ext #(
854: .DW (8)
855: ) u_mio_pads4_attr18 (
856: .re (mio_pads4_attr18_re),
857: // qualified with register enable
858: .we (mio_pads4_attr18_we & regen_qs),
859: .wd (mio_pads4_attr18_wd),
860: .d (hw2reg.mio_pads[18].d),
861: .qre (),
862: .qe (reg2hw.mio_pads[18].qe),
863: .q (reg2hw.mio_pads[18].q ),
864: .qs (mio_pads4_attr18_qs)
865: );
866:
867:
868: // F[attr19]: 31:24
869: prim_subreg_ext #(
870: .DW (8)
871: ) u_mio_pads4_attr19 (
872: .re (mio_pads4_attr19_re),
873: // qualified with register enable
874: .we (mio_pads4_attr19_we & regen_qs),
875: .wd (mio_pads4_attr19_wd),
876: .d (hw2reg.mio_pads[19].d),
877: .qre (),
878: .qe (reg2hw.mio_pads[19].qe),
879: .q (reg2hw.mio_pads[19].q ),
880: .qs (mio_pads4_attr19_qs)
881: );
882:
883:
884: // Subregister 20 of Multireg mio_pads
885: // R[mio_pads5]: V(True)
886:
887: // F[attr20]: 7:0
888: prim_subreg_ext #(
889: .DW (8)
890: ) u_mio_pads5_attr20 (
891: .re (mio_pads5_attr20_re),
892: // qualified with register enable
893: .we (mio_pads5_attr20_we & regen_qs),
894: .wd (mio_pads5_attr20_wd),
895: .d (hw2reg.mio_pads[20].d),
896: .qre (),
897: .qe (reg2hw.mio_pads[20].qe),
898: .q (reg2hw.mio_pads[20].q ),
899: .qs (mio_pads5_attr20_qs)
900: );
901:
902:
903: // F[attr21]: 15:8
904: prim_subreg_ext #(
905: .DW (8)
906: ) u_mio_pads5_attr21 (
907: .re (mio_pads5_attr21_re),
908: // qualified with register enable
909: .we (mio_pads5_attr21_we & regen_qs),
910: .wd (mio_pads5_attr21_wd),
911: .d (hw2reg.mio_pads[21].d),
912: .qre (),
913: .qe (reg2hw.mio_pads[21].qe),
914: .q (reg2hw.mio_pads[21].q ),
915: .qs (mio_pads5_attr21_qs)
916: );
917:
918:
919: // F[attr22]: 23:16
920: prim_subreg_ext #(
921: .DW (8)
922: ) u_mio_pads5_attr22 (
923: .re (mio_pads5_attr22_re),
924: // qualified with register enable
925: .we (mio_pads5_attr22_we & regen_qs),
926: .wd (mio_pads5_attr22_wd),
927: .d (hw2reg.mio_pads[22].d),
928: .qre (),
929: .qe (reg2hw.mio_pads[22].qe),
930: .q (reg2hw.mio_pads[22].q ),
931: .qs (mio_pads5_attr22_qs)
932: );
933:
934:
935: // F[attr23]: 31:24
936: prim_subreg_ext #(
937: .DW (8)
938: ) u_mio_pads5_attr23 (
939: .re (mio_pads5_attr23_re),
940: // qualified with register enable
941: .we (mio_pads5_attr23_we & regen_qs),
942: .wd (mio_pads5_attr23_wd),
943: .d (hw2reg.mio_pads[23].d),
944: .qre (),
945: .qe (reg2hw.mio_pads[23].qe),
946: .q (reg2hw.mio_pads[23].q ),
947: .qs (mio_pads5_attr23_qs)
948: );
949:
950:
951: // Subregister 24 of Multireg mio_pads
952: // R[mio_pads6]: V(True)
953:
954: // F[attr24]: 7:0
955: prim_subreg_ext #(
956: .DW (8)
957: ) u_mio_pads6_attr24 (
958: .re (mio_pads6_attr24_re),
959: // qualified with register enable
960: .we (mio_pads6_attr24_we & regen_qs),
961: .wd (mio_pads6_attr24_wd),
962: .d (hw2reg.mio_pads[24].d),
963: .qre (),
964: .qe (reg2hw.mio_pads[24].qe),
965: .q (reg2hw.mio_pads[24].q ),
966: .qs (mio_pads6_attr24_qs)
967: );
968:
969:
970: // F[attr25]: 15:8
971: prim_subreg_ext #(
972: .DW (8)
973: ) u_mio_pads6_attr25 (
974: .re (mio_pads6_attr25_re),
975: // qualified with register enable
976: .we (mio_pads6_attr25_we & regen_qs),
977: .wd (mio_pads6_attr25_wd),
978: .d (hw2reg.mio_pads[25].d),
979: .qre (),
980: .qe (reg2hw.mio_pads[25].qe),
981: .q (reg2hw.mio_pads[25].q ),
982: .qs (mio_pads6_attr25_qs)
983: );
984:
985:
986: // F[attr26]: 23:16
987: prim_subreg_ext #(
988: .DW (8)
989: ) u_mio_pads6_attr26 (
990: .re (mio_pads6_attr26_re),
991: // qualified with register enable
992: .we (mio_pads6_attr26_we & regen_qs),
993: .wd (mio_pads6_attr26_wd),
994: .d (hw2reg.mio_pads[26].d),
995: .qre (),
996: .qe (reg2hw.mio_pads[26].qe),
997: .q (reg2hw.mio_pads[26].q ),
998: .qs (mio_pads6_attr26_qs)
999: );
1000:
1001:
1002: // F[attr27]: 31:24
1003: prim_subreg_ext #(
1004: .DW (8)
1005: ) u_mio_pads6_attr27 (
1006: .re (mio_pads6_attr27_re),
1007: // qualified with register enable
1008: .we (mio_pads6_attr27_we & regen_qs),
1009: .wd (mio_pads6_attr27_wd),
1010: .d (hw2reg.mio_pads[27].d),
1011: .qre (),
1012: .qe (reg2hw.mio_pads[27].qe),
1013: .q (reg2hw.mio_pads[27].q ),
1014: .qs (mio_pads6_attr27_qs)
1015: );
1016:
1017:
1018: // Subregister 28 of Multireg mio_pads
1019: // R[mio_pads7]: V(True)
1020:
1021: // F[attr28]: 7:0
1022: prim_subreg_ext #(
1023: .DW (8)
1024: ) u_mio_pads7_attr28 (
1025: .re (mio_pads7_attr28_re),
1026: // qualified with register enable
1027: .we (mio_pads7_attr28_we & regen_qs),
1028: .wd (mio_pads7_attr28_wd),
1029: .d (hw2reg.mio_pads[28].d),
1030: .qre (),
1031: .qe (reg2hw.mio_pads[28].qe),
1032: .q (reg2hw.mio_pads[28].q ),
1033: .qs (mio_pads7_attr28_qs)
1034: );
1035:
1036:
1037: // F[attr29]: 15:8
1038: prim_subreg_ext #(
1039: .DW (8)
1040: ) u_mio_pads7_attr29 (
1041: .re (mio_pads7_attr29_re),
1042: // qualified with register enable
1043: .we (mio_pads7_attr29_we & regen_qs),
1044: .wd (mio_pads7_attr29_wd),
1045: .d (hw2reg.mio_pads[29].d),
1046: .qre (),
1047: .qe (reg2hw.mio_pads[29].qe),
1048: .q (reg2hw.mio_pads[29].q ),
1049: .qs (mio_pads7_attr29_qs)
1050: );
1051:
1052:
1053: // F[attr30]: 23:16
1054: prim_subreg_ext #(
1055: .DW (8)
1056: ) u_mio_pads7_attr30 (
1057: .re (mio_pads7_attr30_re),
1058: // qualified with register enable
1059: .we (mio_pads7_attr30_we & regen_qs),
1060: .wd (mio_pads7_attr30_wd),
1061: .d (hw2reg.mio_pads[30].d),
1062: .qre (),
1063: .qe (reg2hw.mio_pads[30].qe),
1064: .q (reg2hw.mio_pads[30].q ),
1065: .qs (mio_pads7_attr30_qs)
1066: );
1067:
1068:
1069: // F[attr31]: 31:24
1070: prim_subreg_ext #(
1071: .DW (8)
1072: ) u_mio_pads7_attr31 (
1073: .re (mio_pads7_attr31_re),
1074: // qualified with register enable
1075: .we (mio_pads7_attr31_we & regen_qs),
1076: .wd (mio_pads7_attr31_wd),
1077: .d (hw2reg.mio_pads[31].d),
1078: .qre (),
1079: .qe (reg2hw.mio_pads[31].qe),
1080: .q (reg2hw.mio_pads[31].q ),
1081: .qs (mio_pads7_attr31_qs)
1082: );
1083:
1084:
1085:
1086:
1087:
1088: logic [12:0] addr_hit;
1089: always_comb begin
1090: addr_hit = '0;
1091: addr_hit[ 0] = (reg_addr == PADCTRL_REGEN_OFFSET);
1092: addr_hit[ 1] = (reg_addr == PADCTRL_DIO_PADS0_OFFSET);
1093: addr_hit[ 2] = (reg_addr == PADCTRL_DIO_PADS1_OFFSET);
1094: addr_hit[ 3] = (reg_addr == PADCTRL_DIO_PADS2_OFFSET);
1095: addr_hit[ 4] = (reg_addr == PADCTRL_DIO_PADS3_OFFSET);
1096: addr_hit[ 5] = (reg_addr == PADCTRL_MIO_PADS0_OFFSET);
1097: addr_hit[ 6] = (reg_addr == PADCTRL_MIO_PADS1_OFFSET);
1098: addr_hit[ 7] = (reg_addr == PADCTRL_MIO_PADS2_OFFSET);
1099: addr_hit[ 8] = (reg_addr == PADCTRL_MIO_PADS3_OFFSET);
1100: addr_hit[ 9] = (reg_addr == PADCTRL_MIO_PADS4_OFFSET);
1101: addr_hit[10] = (reg_addr == PADCTRL_MIO_PADS5_OFFSET);
1102: addr_hit[11] = (reg_addr == PADCTRL_MIO_PADS6_OFFSET);
1103: addr_hit[12] = (reg_addr == PADCTRL_MIO_PADS7_OFFSET);
1104: end
1105:
1106: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
1107:
1108: // Check sub-word write is permitted
1109: always_comb begin
1110: wr_err = 1'b0;
1111: if (addr_hit[ 0] && reg_we && (PADCTRL_PERMIT[ 0] != (PADCTRL_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
1112: if (addr_hit[ 1] && reg_we && (PADCTRL_PERMIT[ 1] != (PADCTRL_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
1113: if (addr_hit[ 2] && reg_we && (PADCTRL_PERMIT[ 2] != (PADCTRL_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
1114: if (addr_hit[ 3] && reg_we && (PADCTRL_PERMIT[ 3] != (PADCTRL_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
1115: if (addr_hit[ 4] && reg_we && (PADCTRL_PERMIT[ 4] != (PADCTRL_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
1116: if (addr_hit[ 5] && reg_we && (PADCTRL_PERMIT[ 5] != (PADCTRL_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
1117: if (addr_hit[ 6] && reg_we && (PADCTRL_PERMIT[ 6] != (PADCTRL_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
1118: if (addr_hit[ 7] && reg_we && (PADCTRL_PERMIT[ 7] != (PADCTRL_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
1119: if (addr_hit[ 8] && reg_we && (PADCTRL_PERMIT[ 8] != (PADCTRL_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
1120: if (addr_hit[ 9] && reg_we && (PADCTRL_PERMIT[ 9] != (PADCTRL_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
1121: if (addr_hit[10] && reg_we && (PADCTRL_PERMIT[10] != (PADCTRL_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
1122: if (addr_hit[11] && reg_we && (PADCTRL_PERMIT[11] != (PADCTRL_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
1123: if (addr_hit[12] && reg_we && (PADCTRL_PERMIT[12] != (PADCTRL_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
1124: end
1125:
1126: assign regen_we = addr_hit[0] & reg_we & ~wr_err;
1127: assign regen_wd = reg_wdata[0];
1128:
1129: assign dio_pads0_attr0_we = addr_hit[1] & reg_we & ~wr_err;
1130: assign dio_pads0_attr0_wd = reg_wdata[7:0];
1131: assign dio_pads0_attr0_re = addr_hit[1] && reg_re;
1132:
1133: assign dio_pads0_attr1_we = addr_hit[1] & reg_we & ~wr_err;
1134: assign dio_pads0_attr1_wd = reg_wdata[15:8];
1135: assign dio_pads0_attr1_re = addr_hit[1] && reg_re;
1136:
1137: assign dio_pads0_attr2_we = addr_hit[1] & reg_we & ~wr_err;
1138: assign dio_pads0_attr2_wd = reg_wdata[23:16];
1139: assign dio_pads0_attr2_re = addr_hit[1] && reg_re;
1140:
1141: assign dio_pads0_attr3_we = addr_hit[1] & reg_we & ~wr_err;
1142: assign dio_pads0_attr3_wd = reg_wdata[31:24];
1143: assign dio_pads0_attr3_re = addr_hit[1] && reg_re;
1144:
1145: assign dio_pads1_attr4_we = addr_hit[2] & reg_we & ~wr_err;
1146: assign dio_pads1_attr4_wd = reg_wdata[7:0];
1147: assign dio_pads1_attr4_re = addr_hit[2] && reg_re;
1148:
1149: assign dio_pads1_attr5_we = addr_hit[2] & reg_we & ~wr_err;
1150: assign dio_pads1_attr5_wd = reg_wdata[15:8];
1151: assign dio_pads1_attr5_re = addr_hit[2] && reg_re;
1152:
1153: assign dio_pads1_attr6_we = addr_hit[2] & reg_we & ~wr_err;
1154: assign dio_pads1_attr6_wd = reg_wdata[23:16];
1155: assign dio_pads1_attr6_re = addr_hit[2] && reg_re;
1156:
1157: assign dio_pads1_attr7_we = addr_hit[2] & reg_we & ~wr_err;
1158: assign dio_pads1_attr7_wd = reg_wdata[31:24];
1159: assign dio_pads1_attr7_re = addr_hit[2] && reg_re;
1160:
1161: assign dio_pads2_attr8_we = addr_hit[3] & reg_we & ~wr_err;
1162: assign dio_pads2_attr8_wd = reg_wdata[7:0];
1163: assign dio_pads2_attr8_re = addr_hit[3] && reg_re;
1164:
1165: assign dio_pads2_attr9_we = addr_hit[3] & reg_we & ~wr_err;
1166: assign dio_pads2_attr9_wd = reg_wdata[15:8];
1167: assign dio_pads2_attr9_re = addr_hit[3] && reg_re;
1168:
1169: assign dio_pads2_attr10_we = addr_hit[3] & reg_we & ~wr_err;
1170: assign dio_pads2_attr10_wd = reg_wdata[23:16];
1171: assign dio_pads2_attr10_re = addr_hit[3] && reg_re;
1172:
1173: assign dio_pads2_attr11_we = addr_hit[3] & reg_we & ~wr_err;
1174: assign dio_pads2_attr11_wd = reg_wdata[31:24];
1175: assign dio_pads2_attr11_re = addr_hit[3] && reg_re;
1176:
1177: assign dio_pads3_attr12_we = addr_hit[4] & reg_we & ~wr_err;
1178: assign dio_pads3_attr12_wd = reg_wdata[7:0];
1179: assign dio_pads3_attr12_re = addr_hit[4] && reg_re;
1180:
1181: assign dio_pads3_attr13_we = addr_hit[4] & reg_we & ~wr_err;
1182: assign dio_pads3_attr13_wd = reg_wdata[15:8];
1183: assign dio_pads3_attr13_re = addr_hit[4] && reg_re;
1184:
1185: assign dio_pads3_attr14_we = addr_hit[4] & reg_we & ~wr_err;
1186: assign dio_pads3_attr14_wd = reg_wdata[23:16];
1187: assign dio_pads3_attr14_re = addr_hit[4] && reg_re;
1188:
1189: assign mio_pads0_attr0_we = addr_hit[5] & reg_we & ~wr_err;
1190: assign mio_pads0_attr0_wd = reg_wdata[7:0];
1191: assign mio_pads0_attr0_re = addr_hit[5] && reg_re;
1192:
1193: assign mio_pads0_attr1_we = addr_hit[5] & reg_we & ~wr_err;
1194: assign mio_pads0_attr1_wd = reg_wdata[15:8];
1195: assign mio_pads0_attr1_re = addr_hit[5] && reg_re;
1196:
1197: assign mio_pads0_attr2_we = addr_hit[5] & reg_we & ~wr_err;
1198: assign mio_pads0_attr2_wd = reg_wdata[23:16];
1199: assign mio_pads0_attr2_re = addr_hit[5] && reg_re;
1200:
1201: assign mio_pads0_attr3_we = addr_hit[5] & reg_we & ~wr_err;
1202: assign mio_pads0_attr3_wd = reg_wdata[31:24];
1203: assign mio_pads0_attr3_re = addr_hit[5] && reg_re;
1204:
1205: assign mio_pads1_attr4_we = addr_hit[6] & reg_we & ~wr_err;
1206: assign mio_pads1_attr4_wd = reg_wdata[7:0];
1207: assign mio_pads1_attr4_re = addr_hit[6] && reg_re;
1208:
1209: assign mio_pads1_attr5_we = addr_hit[6] & reg_we & ~wr_err;
1210: assign mio_pads1_attr5_wd = reg_wdata[15:8];
1211: assign mio_pads1_attr5_re = addr_hit[6] && reg_re;
1212:
1213: assign mio_pads1_attr6_we = addr_hit[6] & reg_we & ~wr_err;
1214: assign mio_pads1_attr6_wd = reg_wdata[23:16];
1215: assign mio_pads1_attr6_re = addr_hit[6] && reg_re;
1216:
1217: assign mio_pads1_attr7_we = addr_hit[6] & reg_we & ~wr_err;
1218: assign mio_pads1_attr7_wd = reg_wdata[31:24];
1219: assign mio_pads1_attr7_re = addr_hit[6] && reg_re;
1220:
1221: assign mio_pads2_attr8_we = addr_hit[7] & reg_we & ~wr_err;
1222: assign mio_pads2_attr8_wd = reg_wdata[7:0];
1223: assign mio_pads2_attr8_re = addr_hit[7] && reg_re;
1224:
1225: assign mio_pads2_attr9_we = addr_hit[7] & reg_we & ~wr_err;
1226: assign mio_pads2_attr9_wd = reg_wdata[15:8];
1227: assign mio_pads2_attr9_re = addr_hit[7] && reg_re;
1228:
1229: assign mio_pads2_attr10_we = addr_hit[7] & reg_we & ~wr_err;
1230: assign mio_pads2_attr10_wd = reg_wdata[23:16];
1231: assign mio_pads2_attr10_re = addr_hit[7] && reg_re;
1232:
1233: assign mio_pads2_attr11_we = addr_hit[7] & reg_we & ~wr_err;
1234: assign mio_pads2_attr11_wd = reg_wdata[31:24];
1235: assign mio_pads2_attr11_re = addr_hit[7] && reg_re;
1236:
1237: assign mio_pads3_attr12_we = addr_hit[8] & reg_we & ~wr_err;
1238: assign mio_pads3_attr12_wd = reg_wdata[7:0];
1239: assign mio_pads3_attr12_re = addr_hit[8] && reg_re;
1240:
1241: assign mio_pads3_attr13_we = addr_hit[8] & reg_we & ~wr_err;
1242: assign mio_pads3_attr13_wd = reg_wdata[15:8];
1243: assign mio_pads3_attr13_re = addr_hit[8] && reg_re;
1244:
1245: assign mio_pads3_attr14_we = addr_hit[8] & reg_we & ~wr_err;
1246: assign mio_pads3_attr14_wd = reg_wdata[23:16];
1247: assign mio_pads3_attr14_re = addr_hit[8] && reg_re;
1248:
1249: assign mio_pads3_attr15_we = addr_hit[8] & reg_we & ~wr_err;
1250: assign mio_pads3_attr15_wd = reg_wdata[31:24];
1251: assign mio_pads3_attr15_re = addr_hit[8] && reg_re;
1252:
1253: assign mio_pads4_attr16_we = addr_hit[9] & reg_we & ~wr_err;
1254: assign mio_pads4_attr16_wd = reg_wdata[7:0];
1255: assign mio_pads4_attr16_re = addr_hit[9] && reg_re;
1256:
1257: assign mio_pads4_attr17_we = addr_hit[9] & reg_we & ~wr_err;
1258: assign mio_pads4_attr17_wd = reg_wdata[15:8];
1259: assign mio_pads4_attr17_re = addr_hit[9] && reg_re;
1260:
1261: assign mio_pads4_attr18_we = addr_hit[9] & reg_we & ~wr_err;
1262: assign mio_pads4_attr18_wd = reg_wdata[23:16];
1263: assign mio_pads4_attr18_re = addr_hit[9] && reg_re;
1264:
1265: assign mio_pads4_attr19_we = addr_hit[9] & reg_we & ~wr_err;
1266: assign mio_pads4_attr19_wd = reg_wdata[31:24];
1267: assign mio_pads4_attr19_re = addr_hit[9] && reg_re;
1268:
1269: assign mio_pads5_attr20_we = addr_hit[10] & reg_we & ~wr_err;
1270: assign mio_pads5_attr20_wd = reg_wdata[7:0];
1271: assign mio_pads5_attr20_re = addr_hit[10] && reg_re;
1272:
1273: assign mio_pads5_attr21_we = addr_hit[10] & reg_we & ~wr_err;
1274: assign mio_pads5_attr21_wd = reg_wdata[15:8];
1275: assign mio_pads5_attr21_re = addr_hit[10] && reg_re;
1276:
1277: assign mio_pads5_attr22_we = addr_hit[10] & reg_we & ~wr_err;
1278: assign mio_pads5_attr22_wd = reg_wdata[23:16];
1279: assign mio_pads5_attr22_re = addr_hit[10] && reg_re;
1280:
1281: assign mio_pads5_attr23_we = addr_hit[10] & reg_we & ~wr_err;
1282: assign mio_pads5_attr23_wd = reg_wdata[31:24];
1283: assign mio_pads5_attr23_re = addr_hit[10] && reg_re;
1284:
1285: assign mio_pads6_attr24_we = addr_hit[11] & reg_we & ~wr_err;
1286: assign mio_pads6_attr24_wd = reg_wdata[7:0];
1287: assign mio_pads6_attr24_re = addr_hit[11] && reg_re;
1288:
1289: assign mio_pads6_attr25_we = addr_hit[11] & reg_we & ~wr_err;
1290: assign mio_pads6_attr25_wd = reg_wdata[15:8];
1291: assign mio_pads6_attr25_re = addr_hit[11] && reg_re;
1292:
1293: assign mio_pads6_attr26_we = addr_hit[11] & reg_we & ~wr_err;
1294: assign mio_pads6_attr26_wd = reg_wdata[23:16];
1295: assign mio_pads6_attr26_re = addr_hit[11] && reg_re;
1296:
1297: assign mio_pads6_attr27_we = addr_hit[11] & reg_we & ~wr_err;
1298: assign mio_pads6_attr27_wd = reg_wdata[31:24];
1299: assign mio_pads6_attr27_re = addr_hit[11] && reg_re;
1300:
1301: assign mio_pads7_attr28_we = addr_hit[12] & reg_we & ~wr_err;
1302: assign mio_pads7_attr28_wd = reg_wdata[7:0];
1303: assign mio_pads7_attr28_re = addr_hit[12] && reg_re;
1304:
1305: assign mio_pads7_attr29_we = addr_hit[12] & reg_we & ~wr_err;
1306: assign mio_pads7_attr29_wd = reg_wdata[15:8];
1307: assign mio_pads7_attr29_re = addr_hit[12] && reg_re;
1308:
1309: assign mio_pads7_attr30_we = addr_hit[12] & reg_we & ~wr_err;
1310: assign mio_pads7_attr30_wd = reg_wdata[23:16];
1311: assign mio_pads7_attr30_re = addr_hit[12] && reg_re;
1312:
1313: assign mio_pads7_attr31_we = addr_hit[12] & reg_we & ~wr_err;
1314: assign mio_pads7_attr31_wd = reg_wdata[31:24];
1315: assign mio_pads7_attr31_re = addr_hit[12] && reg_re;
1316:
1317: // Read data return
1318: always_comb begin
1319: reg_rdata_next = '0;
1320: unique case (1'b1)
1321: addr_hit[0]: begin
1322: reg_rdata_next[0] = regen_qs;
1323: end
1324:
1325: addr_hit[1]: begin
1326: reg_rdata_next[7:0] = dio_pads0_attr0_qs;
1327: reg_rdata_next[15:8] = dio_pads0_attr1_qs;
1328: reg_rdata_next[23:16] = dio_pads0_attr2_qs;
1329: reg_rdata_next[31:24] = dio_pads0_attr3_qs;
1330: end
1331:
1332: addr_hit[2]: begin
1333: reg_rdata_next[7:0] = dio_pads1_attr4_qs;
1334: reg_rdata_next[15:8] = dio_pads1_attr5_qs;
1335: reg_rdata_next[23:16] = dio_pads1_attr6_qs;
1336: reg_rdata_next[31:24] = dio_pads1_attr7_qs;
1337: end
1338:
1339: addr_hit[3]: begin
1340: reg_rdata_next[7:0] = dio_pads2_attr8_qs;
1341: reg_rdata_next[15:8] = dio_pads2_attr9_qs;
1342: reg_rdata_next[23:16] = dio_pads2_attr10_qs;
1343: reg_rdata_next[31:24] = dio_pads2_attr11_qs;
1344: end
1345:
1346: addr_hit[4]: begin
1347: reg_rdata_next[7:0] = dio_pads3_attr12_qs;
1348: reg_rdata_next[15:8] = dio_pads3_attr13_qs;
1349: reg_rdata_next[23:16] = dio_pads3_attr14_qs;
1350: end
1351:
1352: addr_hit[5]: begin
1353: reg_rdata_next[7:0] = mio_pads0_attr0_qs;
1354: reg_rdata_next[15:8] = mio_pads0_attr1_qs;
1355: reg_rdata_next[23:16] = mio_pads0_attr2_qs;
1356: reg_rdata_next[31:24] = mio_pads0_attr3_qs;
1357: end
1358:
1359: addr_hit[6]: begin
1360: reg_rdata_next[7:0] = mio_pads1_attr4_qs;
1361: reg_rdata_next[15:8] = mio_pads1_attr5_qs;
1362: reg_rdata_next[23:16] = mio_pads1_attr6_qs;
1363: reg_rdata_next[31:24] = mio_pads1_attr7_qs;
1364: end
1365:
1366: addr_hit[7]: begin
1367: reg_rdata_next[7:0] = mio_pads2_attr8_qs;
1368: reg_rdata_next[15:8] = mio_pads2_attr9_qs;
1369: reg_rdata_next[23:16] = mio_pads2_attr10_qs;
1370: reg_rdata_next[31:24] = mio_pads2_attr11_qs;
1371: end
1372:
1373: addr_hit[8]: begin
1374: reg_rdata_next[7:0] = mio_pads3_attr12_qs;
1375: reg_rdata_next[15:8] = mio_pads3_attr13_qs;
1376: reg_rdata_next[23:16] = mio_pads3_attr14_qs;
1377: reg_rdata_next[31:24] = mio_pads3_attr15_qs;
1378: end
1379:
1380: addr_hit[9]: begin
1381: reg_rdata_next[7:0] = mio_pads4_attr16_qs;
1382: reg_rdata_next[15:8] = mio_pads4_attr17_qs;
1383: reg_rdata_next[23:16] = mio_pads4_attr18_qs;
1384: reg_rdata_next[31:24] = mio_pads4_attr19_qs;
1385: end
1386:
1387: addr_hit[10]: begin
1388: reg_rdata_next[7:0] = mio_pads5_attr20_qs;
1389: reg_rdata_next[15:8] = mio_pads5_attr21_qs;
1390: reg_rdata_next[23:16] = mio_pads5_attr22_qs;
1391: reg_rdata_next[31:24] = mio_pads5_attr23_qs;
1392: end
1393:
1394: addr_hit[11]: begin
1395: reg_rdata_next[7:0] = mio_pads6_attr24_qs;
1396: reg_rdata_next[15:8] = mio_pads6_attr25_qs;
1397: reg_rdata_next[23:16] = mio_pads6_attr26_qs;
1398: reg_rdata_next[31:24] = mio_pads6_attr27_qs;
1399: end
1400:
1401: addr_hit[12]: begin
1402: reg_rdata_next[7:0] = mio_pads7_attr28_qs;
1403: reg_rdata_next[15:8] = mio_pads7_attr29_qs;
1404: reg_rdata_next[23:16] = mio_pads7_attr30_qs;
1405: reg_rdata_next[31:24] = mio_pads7_attr31_qs;
1406: end
1407:
1408: default: begin
1409: reg_rdata_next = '1;
1410: end
1411: endcase
1412: end
1413:
1414: // Assertions for Register Interface
1415: `ASSERT_PULSE(wePulse, reg_we)
1416: `ASSERT_PULSE(rePulse, reg_re)
1417:
1418: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
1419:
1420: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
1421:
1422: // this is formulated as an assumption such that the FPV testbenches do disprove this
1423: // property by mistake
1424: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
1425:
1426: endmodule
1427: