hw/ip/aes/rtl/aes_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: module aes_reg_top (
   8:   input clk_i,
   9:   input rst_ni,
  10: 
  11:   // Below Regster interface can be changed
  12:   input  tlul_pkg::tl_h2d_t tl_i,
  13:   output tlul_pkg::tl_d2h_t tl_o,
  14:   // To HW
  15:   output aes_reg_pkg::aes_reg2hw_t reg2hw, // Write
  16:   input  aes_reg_pkg::aes_hw2reg_t hw2reg, // Read
  17: 
  18:   // Config
  19:   input devmode_i // If 1, explicit error return for unmapped register access
  20: );
  21: 
  22:   import aes_reg_pkg::* ;
  23: 
  24:   localparam int AW = 7;
  25:   localparam int DW = 32;
  26:   localparam int DBW = DW/8;                    // Byte Width
  27: 
  28:   // register signals
  29:   logic           reg_we;
  30:   logic           reg_re;
  31:   logic [AW-1:0]  reg_addr;
  32:   logic [DW-1:0]  reg_wdata;
  33:   logic [DBW-1:0] reg_be;
  34:   logic [DW-1:0]  reg_rdata;
  35:   logic           reg_error;
  36: 
  37:   logic          addrmiss, wr_err;
  38: 
  39:   logic [DW-1:0] reg_rdata_next;
  40: 
  41:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  42:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  43: 
  44:   assign tl_reg_h2d = tl_i;
  45:   assign tl_o       = tl_reg_d2h;
  46: 
  47:   tlul_adapter_reg #(
  48:     .RegAw(AW),
  49:     .RegDw(DW)
  50:   ) u_reg_if (
  51:     .clk_i,
  52:     .rst_ni,
  53: 
  54:     .tl_i (tl_reg_h2d),
  55:     .tl_o (tl_reg_d2h),
  56: 
  57:     .we_o    (reg_we),
  58:     .re_o    (reg_re),
  59:     .addr_o  (reg_addr),
  60:     .wdata_o (reg_wdata),
  61:     .be_o    (reg_be),
  62:     .rdata_i (reg_rdata),
  63:     .error_i (reg_error)
  64:   );
  65: 
  66:   assign reg_rdata = reg_rdata_next ;
  67:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  68: 
  69:   // Define SW related signals
  70:   // Format: __{wd|we|qs}
  71:   //        or _{wd|we|qs} if field == 1 or 0
  72:   logic [31:0] key0_wd;
  73:   logic key0_we;
  74:   logic [31:0] key1_wd;
  75:   logic key1_we;
  76:   logic [31:0] key2_wd;
  77:   logic key2_we;
  78:   logic [31:0] key3_wd;
  79:   logic key3_we;
  80:   logic [31:0] key4_wd;
  81:   logic key4_we;
  82:   logic [31:0] key5_wd;
  83:   logic key5_we;
  84:   logic [31:0] key6_wd;
  85:   logic key6_we;
  86:   logic [31:0] key7_wd;
  87:   logic key7_we;
  88:   logic [31:0] data_in0_wd;
  89:   logic data_in0_we;
  90:   logic [31:0] data_in1_wd;
  91:   logic data_in1_we;
  92:   logic [31:0] data_in2_wd;
  93:   logic data_in2_we;
  94:   logic [31:0] data_in3_wd;
  95:   logic data_in3_we;
  96:   logic [31:0] data_out0_qs;
  97:   logic data_out0_re;
  98:   logic [31:0] data_out1_qs;
  99:   logic data_out1_re;
 100:   logic [31:0] data_out2_qs;
 101:   logic data_out2_re;
 102:   logic [31:0] data_out3_qs;
 103:   logic data_out3_re;
 104:   logic ctrl_mode_qs;
 105:   logic ctrl_mode_wd;
 106:   logic ctrl_mode_we;
 107:   logic ctrl_mode_re;
 108:   logic [2:0] ctrl_key_len_qs;
 109:   logic [2:0] ctrl_key_len_wd;
 110:   logic ctrl_key_len_we;
 111:   logic ctrl_key_len_re;
 112:   logic ctrl_manual_start_trigger_qs;
 113:   logic ctrl_manual_start_trigger_wd;
 114:   logic ctrl_manual_start_trigger_we;
 115:   logic ctrl_manual_start_trigger_re;
 116:   logic ctrl_force_data_overwrite_qs;
 117:   logic ctrl_force_data_overwrite_wd;
 118:   logic ctrl_force_data_overwrite_we;
 119:   logic ctrl_force_data_overwrite_re;
 120:   logic trigger_start_wd;
 121:   logic trigger_start_we;
 122:   logic trigger_key_clear_wd;
 123:   logic trigger_key_clear_we;
 124:   logic trigger_data_in_clear_wd;
 125:   logic trigger_data_in_clear_we;
 126:   logic trigger_data_out_clear_wd;
 127:   logic trigger_data_out_clear_we;
 128:   logic status_idle_qs;
 129:   logic status_stall_qs;
 130:   logic status_output_valid_qs;
 131:   logic status_input_ready_qs;
 132: 
 133:   // Register instances
 134: 
 135:   // Subregister 0 of Multireg key
 136:   // R[key0]: V(True)
 137: 
 138:   prim_subreg_ext #(
 139:     .DW    (32)
 140:   ) u_key0 (
 141:     .re     (1'b0),
 142:     .we     (key0_we),
 143:     .wd     (key0_wd),
 144:     .d      (hw2reg.key[0].d),
 145:     .qre    (),
 146:     .qe     (reg2hw.key[0].qe),
 147:     .q      (reg2hw.key[0].q ),
 148:     .qs     ()
 149:   );
 150: 
 151:   // Subregister 1 of Multireg key
 152:   // R[key1]: V(True)
 153: 
 154:   prim_subreg_ext #(
 155:     .DW    (32)
 156:   ) u_key1 (
 157:     .re     (1'b0),
 158:     .we     (key1_we),
 159:     .wd     (key1_wd),
 160:     .d      (hw2reg.key[1].d),
 161:     .qre    (),
 162:     .qe     (reg2hw.key[1].qe),
 163:     .q      (reg2hw.key[1].q ),
 164:     .qs     ()
 165:   );
 166: 
 167:   // Subregister 2 of Multireg key
 168:   // R[key2]: V(True)
 169: 
 170:   prim_subreg_ext #(
 171:     .DW    (32)
 172:   ) u_key2 (
 173:     .re     (1'b0),
 174:     .we     (key2_we),
 175:     .wd     (key2_wd),
 176:     .d      (hw2reg.key[2].d),
 177:     .qre    (),
 178:     .qe     (reg2hw.key[2].qe),
 179:     .q      (reg2hw.key[2].q ),
 180:     .qs     ()
 181:   );
 182: 
 183:   // Subregister 3 of Multireg key
 184:   // R[key3]: V(True)
 185: 
 186:   prim_subreg_ext #(
 187:     .DW    (32)
 188:   ) u_key3 (
 189:     .re     (1'b0),
 190:     .we     (key3_we),
 191:     .wd     (key3_wd),
 192:     .d      (hw2reg.key[3].d),
 193:     .qre    (),
 194:     .qe     (reg2hw.key[3].qe),
 195:     .q      (reg2hw.key[3].q ),
 196:     .qs     ()
 197:   );
 198: 
 199:   // Subregister 4 of Multireg key
 200:   // R[key4]: V(True)
 201: 
 202:   prim_subreg_ext #(
 203:     .DW    (32)
 204:   ) u_key4 (
 205:     .re     (1'b0),
 206:     .we     (key4_we),
 207:     .wd     (key4_wd),
 208:     .d      (hw2reg.key[4].d),
 209:     .qre    (),
 210:     .qe     (reg2hw.key[4].qe),
 211:     .q      (reg2hw.key[4].q ),
 212:     .qs     ()
 213:   );
 214: 
 215:   // Subregister 5 of Multireg key
 216:   // R[key5]: V(True)
 217: 
 218:   prim_subreg_ext #(
 219:     .DW    (32)
 220:   ) u_key5 (
 221:     .re     (1'b0),
 222:     .we     (key5_we),
 223:     .wd     (key5_wd),
 224:     .d      (hw2reg.key[5].d),
 225:     .qre    (),
 226:     .qe     (reg2hw.key[5].qe),
 227:     .q      (reg2hw.key[5].q ),
 228:     .qs     ()
 229:   );
 230: 
 231:   // Subregister 6 of Multireg key
 232:   // R[key6]: V(True)
 233: 
 234:   prim_subreg_ext #(
 235:     .DW    (32)
 236:   ) u_key6 (
 237:     .re     (1'b0),
 238:     .we     (key6_we),
 239:     .wd     (key6_wd),
 240:     .d      (hw2reg.key[6].d),
 241:     .qre    (),
 242:     .qe     (reg2hw.key[6].qe),
 243:     .q      (reg2hw.key[6].q ),
 244:     .qs     ()
 245:   );
 246: 
 247:   // Subregister 7 of Multireg key
 248:   // R[key7]: V(True)
 249: 
 250:   prim_subreg_ext #(
 251:     .DW    (32)
 252:   ) u_key7 (
 253:     .re     (1'b0),
 254:     .we     (key7_we),
 255:     .wd     (key7_wd),
 256:     .d      (hw2reg.key[7].d),
 257:     .qre    (),
 258:     .qe     (reg2hw.key[7].qe),
 259:     .q      (reg2hw.key[7].q ),
 260:     .qs     ()
 261:   );
 262: 
 263: 
 264: 
 265:   // Subregister 0 of Multireg data_in
 266:   // R[data_in0]: V(False)
 267: 
 268:   prim_subreg #(
 269:     .DW      (32),
 270:     .SWACCESS("WO"),
 271:     .RESVAL  (32'h0)
 272:   ) u_data_in0 (
 273:     .clk_i   (clk_i    ),
 274:     .rst_ni  (rst_ni  ),
 275: 
 276:     // from register interface
 277:     .we     (data_in0_we),
 278:     .wd     (data_in0_wd),
 279: 
 280:     // from internal hardware
 281:     .de     (hw2reg.data_in[0].de),
 282:     .d      (hw2reg.data_in[0].d ),
 283: 
 284:     // to internal hardware
 285:     .qe     (reg2hw.data_in[0].qe),
 286:     .q      (reg2hw.data_in[0].q ),
 287: 
 288:     .qs     ()
 289:   );
 290: 
 291:   // Subregister 1 of Multireg data_in
 292:   // R[data_in1]: V(False)
 293: 
 294:   prim_subreg #(
 295:     .DW      (32),
 296:     .SWACCESS("WO"),
 297:     .RESVAL  (32'h0)
 298:   ) u_data_in1 (
 299:     .clk_i   (clk_i    ),
 300:     .rst_ni  (rst_ni  ),
 301: 
 302:     // from register interface
 303:     .we     (data_in1_we),
 304:     .wd     (data_in1_wd),
 305: 
 306:     // from internal hardware
 307:     .de     (hw2reg.data_in[1].de),
 308:     .d      (hw2reg.data_in[1].d ),
 309: 
 310:     // to internal hardware
 311:     .qe     (reg2hw.data_in[1].qe),
 312:     .q      (reg2hw.data_in[1].q ),
 313: 
 314:     .qs     ()
 315:   );
 316: 
 317:   // Subregister 2 of Multireg data_in
 318:   // R[data_in2]: V(False)
 319: 
 320:   prim_subreg #(
 321:     .DW      (32),
 322:     .SWACCESS("WO"),
 323:     .RESVAL  (32'h0)
 324:   ) u_data_in2 (
 325:     .clk_i   (clk_i    ),
 326:     .rst_ni  (rst_ni  ),
 327: 
 328:     // from register interface
 329:     .we     (data_in2_we),
 330:     .wd     (data_in2_wd),
 331: 
 332:     // from internal hardware
 333:     .de     (hw2reg.data_in[2].de),
 334:     .d      (hw2reg.data_in[2].d ),
 335: 
 336:     // to internal hardware
 337:     .qe     (reg2hw.data_in[2].qe),
 338:     .q      (reg2hw.data_in[2].q ),
 339: 
 340:     .qs     ()
 341:   );
 342: 
 343:   // Subregister 3 of Multireg data_in
 344:   // R[data_in3]: V(False)
 345: 
 346:   prim_subreg #(
 347:     .DW      (32),
 348:     .SWACCESS("WO"),
 349:     .RESVAL  (32'h0)
 350:   ) u_data_in3 (
 351:     .clk_i   (clk_i    ),
 352:     .rst_ni  (rst_ni  ),
 353: 
 354:     // from register interface
 355:     .we     (data_in3_we),
 356:     .wd     (data_in3_wd),
 357: 
 358:     // from internal hardware
 359:     .de     (hw2reg.data_in[3].de),
 360:     .d      (hw2reg.data_in[3].d ),
 361: 
 362:     // to internal hardware
 363:     .qe     (reg2hw.data_in[3].qe),
 364:     .q      (reg2hw.data_in[3].q ),
 365: 
 366:     .qs     ()
 367:   );
 368: 
 369: 
 370: 
 371:   // Subregister 0 of Multireg data_out
 372:   // R[data_out0]: V(True)
 373: 
 374:   prim_subreg_ext #(
 375:     .DW    (32)
 376:   ) u_data_out0 (
 377:     .re     (data_out0_re),
 378:     .we     (1'b0),
 379:     .wd     ('0),
 380:     .d      (hw2reg.data_out[0].d),
 381:     .qre    (reg2hw.data_out[0].re),
 382:     .qe     (),
 383:     .q      (reg2hw.data_out[0].q ),
 384:     .qs     (data_out0_qs)
 385:   );
 386: 
 387:   // Subregister 1 of Multireg data_out
 388:   // R[data_out1]: V(True)
 389: 
 390:   prim_subreg_ext #(
 391:     .DW    (32)
 392:   ) u_data_out1 (
 393:     .re     (data_out1_re),
 394:     .we     (1'b0),
 395:     .wd     ('0),
 396:     .d      (hw2reg.data_out[1].d),
 397:     .qre    (reg2hw.data_out[1].re),
 398:     .qe     (),
 399:     .q      (reg2hw.data_out[1].q ),
 400:     .qs     (data_out1_qs)
 401:   );
 402: 
 403:   // Subregister 2 of Multireg data_out
 404:   // R[data_out2]: V(True)
 405: 
 406:   prim_subreg_ext #(
 407:     .DW    (32)
 408:   ) u_data_out2 (
 409:     .re     (data_out2_re),
 410:     .we     (1'b0),
 411:     .wd     ('0),
 412:     .d      (hw2reg.data_out[2].d),
 413:     .qre    (reg2hw.data_out[2].re),
 414:     .qe     (),
 415:     .q      (reg2hw.data_out[2].q ),
 416:     .qs     (data_out2_qs)
 417:   );
 418: 
 419:   // Subregister 3 of Multireg data_out
 420:   // R[data_out3]: V(True)
 421: 
 422:   prim_subreg_ext #(
 423:     .DW    (32)
 424:   ) u_data_out3 (
 425:     .re     (data_out3_re),
 426:     .we     (1'b0),
 427:     .wd     ('0),
 428:     .d      (hw2reg.data_out[3].d),
 429:     .qre    (reg2hw.data_out[3].re),
 430:     .qe     (),
 431:     .q      (reg2hw.data_out[3].q ),
 432:     .qs     (data_out3_qs)
 433:   );
 434: 
 435: 
 436:   // R[ctrl]: V(True)
 437: 
 438:   //   F[mode]: 0:0
 439:   prim_subreg_ext #(
 440:     .DW    (1)
 441:   ) u_ctrl_mode (
 442:     .re     (ctrl_mode_re),
 443:     .we     (ctrl_mode_we),
 444:     .wd     (ctrl_mode_wd),
 445:     .d      ('0),
 446:     .qre    (),
 447:     .qe     (reg2hw.ctrl.mode.qe),
 448:     .q      (reg2hw.ctrl.mode.q ),
 449:     .qs     (ctrl_mode_qs)
 450:   );
 451: 
 452: 
 453:   //   F[key_len]: 3:1
 454:   prim_subreg_ext #(
 455:     .DW    (3)
 456:   ) u_ctrl_key_len (
 457:     .re     (ctrl_key_len_re),
 458:     .we     (ctrl_key_len_we),
 459:     .wd     (ctrl_key_len_wd),
 460:     .d      (hw2reg.ctrl.key_len.d),
 461:     .qre    (),
 462:     .qe     (reg2hw.ctrl.key_len.qe),
 463:     .q      (reg2hw.ctrl.key_len.q ),
 464:     .qs     (ctrl_key_len_qs)
 465:   );
 466: 
 467: 
 468:   //   F[manual_start_trigger]: 4:4
 469:   prim_subreg_ext #(
 470:     .DW    (1)
 471:   ) u_ctrl_manual_start_trigger (
 472:     .re     (ctrl_manual_start_trigger_re),
 473:     .we     (ctrl_manual_start_trigger_we),
 474:     .wd     (ctrl_manual_start_trigger_wd),
 475:     .d      ('0),
 476:     .qre    (),
 477:     .qe     (reg2hw.ctrl.manual_start_trigger.qe),
 478:     .q      (reg2hw.ctrl.manual_start_trigger.q ),
 479:     .qs     (ctrl_manual_start_trigger_qs)
 480:   );
 481: 
 482: 
 483:   //   F[force_data_overwrite]: 5:5
 484:   prim_subreg_ext #(
 485:     .DW    (1)
 486:   ) u_ctrl_force_data_overwrite (
 487:     .re     (ctrl_force_data_overwrite_re),
 488:     .we     (ctrl_force_data_overwrite_we),
 489:     .wd     (ctrl_force_data_overwrite_wd),
 490:     .d      ('0),
 491:     .qre    (),
 492:     .qe     (reg2hw.ctrl.force_data_overwrite.qe),
 493:     .q      (reg2hw.ctrl.force_data_overwrite.q ),
 494:     .qs     (ctrl_force_data_overwrite_qs)
 495:   );
 496: 
 497: 
 498:   // R[trigger]: V(False)
 499: 
 500:   //   F[start]: 0:0
 501:   prim_subreg #(
 502:     .DW      (1),
 503:     .SWACCESS("WO"),
 504:     .RESVAL  (1'h0)
 505:   ) u_trigger_start (
 506:     .clk_i   (clk_i    ),
 507:     .rst_ni  (rst_ni  ),
 508: 
 509:     // from register interface
 510:     .we     (trigger_start_we),
 511:     .wd     (trigger_start_wd),
 512: 
 513:     // from internal hardware
 514:     .de     (hw2reg.trigger.start.de),
 515:     .d      (hw2reg.trigger.start.d ),
 516: 
 517:     // to internal hardware
 518:     .qe     (),
 519:     .q      (reg2hw.trigger.start.q ),
 520: 
 521:     .qs     ()
 522:   );
 523: 
 524: 
 525:   //   F[key_clear]: 1:1
 526:   prim_subreg #(
 527:     .DW      (1),
 528:     .SWACCESS("WO"),
 529:     .RESVAL  (1'h0)
 530:   ) u_trigger_key_clear (
 531:     .clk_i   (clk_i    ),
 532:     .rst_ni  (rst_ni  ),
 533: 
 534:     // from register interface
 535:     .we     (trigger_key_clear_we),
 536:     .wd     (trigger_key_clear_wd),
 537: 
 538:     // from internal hardware
 539:     .de     (hw2reg.trigger.key_clear.de),
 540:     .d      (hw2reg.trigger.key_clear.d ),
 541: 
 542:     // to internal hardware
 543:     .qe     (),
 544:     .q      (reg2hw.trigger.key_clear.q ),
 545: 
 546:     .qs     ()
 547:   );
 548: 
 549: 
 550:   //   F[data_in_clear]: 2:2
 551:   prim_subreg #(
 552:     .DW      (1),
 553:     .SWACCESS("WO"),
 554:     .RESVAL  (1'h0)
 555:   ) u_trigger_data_in_clear (
 556:     .clk_i   (clk_i    ),
 557:     .rst_ni  (rst_ni  ),
 558: 
 559:     // from register interface
 560:     .we     (trigger_data_in_clear_we),
 561:     .wd     (trigger_data_in_clear_wd),
 562: 
 563:     // from internal hardware
 564:     .de     (hw2reg.trigger.data_in_clear.de),
 565:     .d      (hw2reg.trigger.data_in_clear.d ),
 566: 
 567:     // to internal hardware
 568:     .qe     (),
 569:     .q      (reg2hw.trigger.data_in_clear.q ),
 570: 
 571:     .qs     ()
 572:   );
 573: 
 574: 
 575:   //   F[data_out_clear]: 3:3
 576:   prim_subreg #(
 577:     .DW      (1),
 578:     .SWACCESS("WO"),
 579:     .RESVAL  (1'h0)
 580:   ) u_trigger_data_out_clear (
 581:     .clk_i   (clk_i    ),
 582:     .rst_ni  (rst_ni  ),
 583: 
 584:     // from register interface
 585:     .we     (trigger_data_out_clear_we),
 586:     .wd     (trigger_data_out_clear_wd),
 587: 
 588:     // from internal hardware
 589:     .de     (hw2reg.trigger.data_out_clear.de),
 590:     .d      (hw2reg.trigger.data_out_clear.d ),
 591: 
 592:     // to internal hardware
 593:     .qe     (),
 594:     .q      (reg2hw.trigger.data_out_clear.q ),
 595: 
 596:     .qs     ()
 597:   );
 598: 
 599: 
 600:   // R[status]: V(False)
 601: 
 602:   //   F[idle]: 0:0
 603:   prim_subreg #(
 604:     .DW      (1),
 605:     .SWACCESS("RO"),
 606:     .RESVAL  (1'h1)
 607:   ) u_status_idle (
 608:     .clk_i   (clk_i    ),
 609:     .rst_ni  (rst_ni  ),
 610: 
 611:     .we     (1'b0),
 612:     .wd     ('0  ),
 613: 
 614:     // from internal hardware
 615:     .de     (hw2reg.status.idle.de),
 616:     .d      (hw2reg.status.idle.d ),
 617: 
 618:     // to internal hardware
 619:     .qe     (),
 620:     .q      (),
 621: 
 622:     // to register interface (read)
 623:     .qs     (status_idle_qs)
 624:   );
 625: 
 626: 
 627:   //   F[stall]: 1:1
 628:   prim_subreg #(
 629:     .DW      (1),
 630:     .SWACCESS("RO"),
 631:     .RESVAL  (1'h0)
 632:   ) u_status_stall (
 633:     .clk_i   (clk_i    ),
 634:     .rst_ni  (rst_ni  ),
 635: 
 636:     .we     (1'b0),
 637:     .wd     ('0  ),
 638: 
 639:     // from internal hardware
 640:     .de     (hw2reg.status.stall.de),
 641:     .d      (hw2reg.status.stall.d ),
 642: 
 643:     // to internal hardware
 644:     .qe     (),
 645:     .q      (),
 646: 
 647:     // to register interface (read)
 648:     .qs     (status_stall_qs)
 649:   );
 650: 
 651: 
 652:   //   F[output_valid]: 2:2
 653:   prim_subreg #(
 654:     .DW      (1),
 655:     .SWACCESS("RO"),
 656:     .RESVAL  (1'h0)
 657:   ) u_status_output_valid (
 658:     .clk_i   (clk_i    ),
 659:     .rst_ni  (rst_ni  ),
 660: 
 661:     .we     (1'b0),
 662:     .wd     ('0  ),
 663: 
 664:     // from internal hardware
 665:     .de     (hw2reg.status.output_valid.de),
 666:     .d      (hw2reg.status.output_valid.d ),
 667: 
 668:     // to internal hardware
 669:     .qe     (),
 670:     .q      (),
 671: 
 672:     // to register interface (read)
 673:     .qs     (status_output_valid_qs)
 674:   );
 675: 
 676: 
 677:   //   F[input_ready]: 3:3
 678:   prim_subreg #(
 679:     .DW      (1),
 680:     .SWACCESS("RO"),
 681:     .RESVAL  (1'h1)
 682:   ) u_status_input_ready (
 683:     .clk_i   (clk_i    ),
 684:     .rst_ni  (rst_ni  ),
 685: 
 686:     .we     (1'b0),
 687:     .wd     ('0  ),
 688: 
 689:     // from internal hardware
 690:     .de     (hw2reg.status.input_ready.de),
 691:     .d      (hw2reg.status.input_ready.d ),
 692: 
 693:     // to internal hardware
 694:     .qe     (),
 695:     .q      (),
 696: 
 697:     // to register interface (read)
 698:     .qs     (status_input_ready_qs)
 699:   );
 700: 
 701: 
 702: 
 703: 
 704:   logic [18:0] addr_hit;
 705:   always_comb begin
 706:     addr_hit = '0;
 707:     addr_hit[ 0] = (reg_addr == AES_KEY0_OFFSET);
 708:     addr_hit[ 1] = (reg_addr == AES_KEY1_OFFSET);
 709:     addr_hit[ 2] = (reg_addr == AES_KEY2_OFFSET);
 710:     addr_hit[ 3] = (reg_addr == AES_KEY3_OFFSET);
 711:     addr_hit[ 4] = (reg_addr == AES_KEY4_OFFSET);
 712:     addr_hit[ 5] = (reg_addr == AES_KEY5_OFFSET);
 713:     addr_hit[ 6] = (reg_addr == AES_KEY6_OFFSET);
 714:     addr_hit[ 7] = (reg_addr == AES_KEY7_OFFSET);
 715:     addr_hit[ 8] = (reg_addr == AES_DATA_IN0_OFFSET);
 716:     addr_hit[ 9] = (reg_addr == AES_DATA_IN1_OFFSET);
 717:     addr_hit[10] = (reg_addr == AES_DATA_IN2_OFFSET);
 718:     addr_hit[11] = (reg_addr == AES_DATA_IN3_OFFSET);
 719:     addr_hit[12] = (reg_addr == AES_DATA_OUT0_OFFSET);
 720:     addr_hit[13] = (reg_addr == AES_DATA_OUT1_OFFSET);
 721:     addr_hit[14] = (reg_addr == AES_DATA_OUT2_OFFSET);
 722:     addr_hit[15] = (reg_addr == AES_DATA_OUT3_OFFSET);
 723:     addr_hit[16] = (reg_addr == AES_CTRL_OFFSET);
 724:     addr_hit[17] = (reg_addr == AES_TRIGGER_OFFSET);
 725:     addr_hit[18] = (reg_addr == AES_STATUS_OFFSET);
 726:   end
 727: 
 728:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
 729: 
 730:   // Check sub-word write is permitted
 731:   always_comb begin
 732:     wr_err = 1'b0;
 733:     if (addr_hit[ 0] && reg_we && (AES_PERMIT[ 0] != (AES_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
 734:     if (addr_hit[ 1] && reg_we && (AES_PERMIT[ 1] != (AES_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
 735:     if (addr_hit[ 2] && reg_we && (AES_PERMIT[ 2] != (AES_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
 736:     if (addr_hit[ 3] && reg_we && (AES_PERMIT[ 3] != (AES_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
 737:     if (addr_hit[ 4] && reg_we && (AES_PERMIT[ 4] != (AES_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
 738:     if (addr_hit[ 5] && reg_we && (AES_PERMIT[ 5] != (AES_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
 739:     if (addr_hit[ 6] && reg_we && (AES_PERMIT[ 6] != (AES_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
 740:     if (addr_hit[ 7] && reg_we && (AES_PERMIT[ 7] != (AES_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
 741:     if (addr_hit[ 8] && reg_we && (AES_PERMIT[ 8] != (AES_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
 742:     if (addr_hit[ 9] && reg_we && (AES_PERMIT[ 9] != (AES_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
 743:     if (addr_hit[10] && reg_we && (AES_PERMIT[10] != (AES_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
 744:     if (addr_hit[11] && reg_we && (AES_PERMIT[11] != (AES_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
 745:     if (addr_hit[12] && reg_we && (AES_PERMIT[12] != (AES_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
 746:     if (addr_hit[13] && reg_we && (AES_PERMIT[13] != (AES_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
 747:     if (addr_hit[14] && reg_we && (AES_PERMIT[14] != (AES_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
 748:     if (addr_hit[15] && reg_we && (AES_PERMIT[15] != (AES_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
 749:     if (addr_hit[16] && reg_we && (AES_PERMIT[16] != (AES_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
 750:     if (addr_hit[17] && reg_we && (AES_PERMIT[17] != (AES_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
 751:     if (addr_hit[18] && reg_we && (AES_PERMIT[18] != (AES_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
 752:   end
 753: 
 754:   assign key0_we = addr_hit[0] & reg_we & ~wr_err;
 755:   assign key0_wd = reg_wdata[31:0];
 756: 
 757:   assign key1_we = addr_hit[1] & reg_we & ~wr_err;
 758:   assign key1_wd = reg_wdata[31:0];
 759: 
 760:   assign key2_we = addr_hit[2] & reg_we & ~wr_err;
 761:   assign key2_wd = reg_wdata[31:0];
 762: 
 763:   assign key3_we = addr_hit[3] & reg_we & ~wr_err;
 764:   assign key3_wd = reg_wdata[31:0];
 765: 
 766:   assign key4_we = addr_hit[4] & reg_we & ~wr_err;
 767:   assign key4_wd = reg_wdata[31:0];
 768: 
 769:   assign key5_we = addr_hit[5] & reg_we & ~wr_err;
 770:   assign key5_wd = reg_wdata[31:0];
 771: 
 772:   assign key6_we = addr_hit[6] & reg_we & ~wr_err;
 773:   assign key6_wd = reg_wdata[31:0];
 774: 
 775:   assign key7_we = addr_hit[7] & reg_we & ~wr_err;
 776:   assign key7_wd = reg_wdata[31:0];
 777: 
 778:   assign data_in0_we = addr_hit[8] & reg_we & ~wr_err;
 779:   assign data_in0_wd = reg_wdata[31:0];
 780: 
 781:   assign data_in1_we = addr_hit[9] & reg_we & ~wr_err;
 782:   assign data_in1_wd = reg_wdata[31:0];
 783: 
 784:   assign data_in2_we = addr_hit[10] & reg_we & ~wr_err;
 785:   assign data_in2_wd = reg_wdata[31:0];
 786: 
 787:   assign data_in3_we = addr_hit[11] & reg_we & ~wr_err;
 788:   assign data_in3_wd = reg_wdata[31:0];
 789: 
 790:   assign data_out0_re = addr_hit[12] && reg_re;
 791: 
 792:   assign data_out1_re = addr_hit[13] && reg_re;
 793: 
 794:   assign data_out2_re = addr_hit[14] && reg_re;
 795: 
 796:   assign data_out3_re = addr_hit[15] && reg_re;
 797: 
 798:   assign ctrl_mode_we = addr_hit[16] & reg_we & ~wr_err;
 799:   assign ctrl_mode_wd = reg_wdata[0];
 800:   assign ctrl_mode_re = addr_hit[16] && reg_re;
 801: 
 802:   assign ctrl_key_len_we = addr_hit[16] & reg_we & ~wr_err;
 803:   assign ctrl_key_len_wd = reg_wdata[3:1];
 804:   assign ctrl_key_len_re = addr_hit[16] && reg_re;
 805: 
 806:   assign ctrl_manual_start_trigger_we = addr_hit[16] & reg_we & ~wr_err;
 807:   assign ctrl_manual_start_trigger_wd = reg_wdata[4];
 808:   assign ctrl_manual_start_trigger_re = addr_hit[16] && reg_re;
 809: 
 810:   assign ctrl_force_data_overwrite_we = addr_hit[16] & reg_we & ~wr_err;
 811:   assign ctrl_force_data_overwrite_wd = reg_wdata[5];
 812:   assign ctrl_force_data_overwrite_re = addr_hit[16] && reg_re;
 813: 
 814:   assign trigger_start_we = addr_hit[17] & reg_we & ~wr_err;
 815:   assign trigger_start_wd = reg_wdata[0];
 816: 
 817:   assign trigger_key_clear_we = addr_hit[17] & reg_we & ~wr_err;
 818:   assign trigger_key_clear_wd = reg_wdata[1];
 819: 
 820:   assign trigger_data_in_clear_we = addr_hit[17] & reg_we & ~wr_err;
 821:   assign trigger_data_in_clear_wd = reg_wdata[2];
 822: 
 823:   assign trigger_data_out_clear_we = addr_hit[17] & reg_we & ~wr_err;
 824:   assign trigger_data_out_clear_wd = reg_wdata[3];
 825: 
 826: 
 827: 
 828: 
 829: 
 830:   // Read data return
 831:   always_comb begin
 832:     reg_rdata_next = '0;
 833:     unique case (1'b1)
 834:       addr_hit[0]: begin
 835:         reg_rdata_next[31:0] = '0;
 836:       end
 837: 
 838:       addr_hit[1]: begin
 839:         reg_rdata_next[31:0] = '0;
 840:       end
 841: 
 842:       addr_hit[2]: begin
 843:         reg_rdata_next[31:0] = '0;
 844:       end
 845: 
 846:       addr_hit[3]: begin
 847:         reg_rdata_next[31:0] = '0;
 848:       end
 849: 
 850:       addr_hit[4]: begin
 851:         reg_rdata_next[31:0] = '0;
 852:       end
 853: 
 854:       addr_hit[5]: begin
 855:         reg_rdata_next[31:0] = '0;
 856:       end
 857: 
 858:       addr_hit[6]: begin
 859:         reg_rdata_next[31:0] = '0;
 860:       end
 861: 
 862:       addr_hit[7]: begin
 863:         reg_rdata_next[31:0] = '0;
 864:       end
 865: 
 866:       addr_hit[8]: begin
 867:         reg_rdata_next[31:0] = '0;
 868:       end
 869: 
 870:       addr_hit[9]: begin
 871:         reg_rdata_next[31:0] = '0;
 872:       end
 873: 
 874:       addr_hit[10]: begin
 875:         reg_rdata_next[31:0] = '0;
 876:       end
 877: 
 878:       addr_hit[11]: begin
 879:         reg_rdata_next[31:0] = '0;
 880:       end
 881: 
 882:       addr_hit[12]: begin
 883:         reg_rdata_next[31:0] = data_out0_qs;
 884:       end
 885: 
 886:       addr_hit[13]: begin
 887:         reg_rdata_next[31:0] = data_out1_qs;
 888:       end
 889: 
 890:       addr_hit[14]: begin
 891:         reg_rdata_next[31:0] = data_out2_qs;
 892:       end
 893: 
 894:       addr_hit[15]: begin
 895:         reg_rdata_next[31:0] = data_out3_qs;
 896:       end
 897: 
 898:       addr_hit[16]: begin
 899:         reg_rdata_next[0] = ctrl_mode_qs;
 900:         reg_rdata_next[3:1] = ctrl_key_len_qs;
 901:         reg_rdata_next[4] = ctrl_manual_start_trigger_qs;
 902:         reg_rdata_next[5] = ctrl_force_data_overwrite_qs;
 903:       end
 904: 
 905:       addr_hit[17]: begin
 906:         reg_rdata_next[0] = '0;
 907:         reg_rdata_next[1] = '0;
 908:         reg_rdata_next[2] = '0;
 909:         reg_rdata_next[3] = '0;
 910:       end
 911: 
 912:       addr_hit[18]: begin
 913:         reg_rdata_next[0] = status_idle_qs;
 914:         reg_rdata_next[1] = status_stall_qs;
 915:         reg_rdata_next[2] = status_output_valid_qs;
 916:         reg_rdata_next[3] = status_input_ready_qs;
 917:       end
 918: 
 919:       default: begin
 920:         reg_rdata_next = '1;
 921:       end
 922:     endcase
 923:   end
 924: 
 925:   // Assertions for Register Interface
 926:   `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
 927:   `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
 928: 
 929:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
 930: 
 931:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
 932: 
 933:   // this is formulated as an assumption such that the FPV testbenches do disprove this
 934:   // property by mistake
 935:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
 936: 
 937: endmodule
 938: