hw/vendor/lowrisc_ibex/rtl/ibex_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.
3: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
4: // SPDX-License-Identifier: Apache-2.0
5:
6: /**
7: * Package with constants used by Ibex
8: */
9: package ibex_pkg;
10:
11:
12: /////////////
13: // Opcodes //
14: /////////////
15:
16: typedef enum logic [6:0] {
17: OPCODE_LOAD = 7'h03,
18: OPCODE_MISC_MEM = 7'h0f,
19: OPCODE_OP_IMM = 7'h13,
20: OPCODE_AUIPC = 7'h17,
21: OPCODE_STORE = 7'h23,
22: OPCODE_OP = 7'h33,
23: OPCODE_LUI = 7'h37,
24: OPCODE_BRANCH = 7'h63,
25: OPCODE_JALR = 7'h67,
26: OPCODE_JAL = 7'h6f,
27: OPCODE_SYSTEM = 7'h73
28: } opcode_e;
29:
30:
31: ////////////////////
32: // ALU operations //
33: ////////////////////
34:
35: typedef enum logic [4:0] {
36: // Arithmetics
37: ALU_ADD,
38: ALU_SUB,
39:
40: // Logics
41: ALU_XOR,
42: ALU_OR,
43: ALU_AND,
44:
45: // Shifts
46: ALU_SRA,
47: ALU_SRL,
48: ALU_SLL,
49:
50: // Comparisons
51: ALU_LT,
52: ALU_LTU,
53: ALU_GE,
54: ALU_GEU,
55: ALU_EQ,
56: ALU_NE,
57:
58: // Set lower than
59: ALU_SLT,
60: ALU_SLTU
61: } alu_op_e;
62:
63: typedef enum logic [1:0] {
64: // Multiplier/divider
65: MD_OP_MULL,
66: MD_OP_MULH,
67: MD_OP_DIV,
68: MD_OP_REM
69: } md_op_e;
70:
71:
72: //////////////////////////////////
73: // Control and status registers //
74: //////////////////////////////////
75:
76: // CSR operations
77: typedef enum logic [1:0] {
78: CSR_OP_READ,
79: CSR_OP_WRITE,
80: CSR_OP_SET,
81: CSR_OP_CLEAR
82: } csr_op_e;
83:
84: // Privileged mode
85: typedef enum logic[1:0] {
86: PRIV_LVL_M = 2'b11,
87: PRIV_LVL_H = 2'b10,
88: PRIV_LVL_S = 2'b01,
89: PRIV_LVL_U = 2'b00
90: } priv_lvl_e;
91:
92: // Constants for the dcsr.xdebugver fields
93: typedef enum logic[3:0] {
94: XDEBUGVER_NO = 4'd0, // no external debug support
95: XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
96: XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec
97: } x_debug_ver_e;
98:
99:
100: //////////////
101: // ID stage //
102: //////////////
103:
104: // Operand a selection
105: typedef enum logic[1:0] {
106: OP_A_REG_A,
107: OP_A_FWD,
108: OP_A_CURRPC,
109: OP_A_IMM
110: } op_a_sel_e;
111:
112: // Immediate a selection
113: typedef enum logic {
114: IMM_A_Z,
115: IMM_A_ZERO
116: } imm_a_sel_e;
117:
118: // Operand b selection
119: typedef enum logic {
120: OP_B_REG_B,
121: OP_B_IMM
122: } op_b_sel_e;
123:
124: // Immediate b selection
125: typedef enum logic [2:0] {
126: IMM_B_I,
127: IMM_B_S,
128: IMM_B_B,
129: IMM_B_U,
130: IMM_B_J,
131: IMM_B_INCR_PC,
132: IMM_B_INCR_ADDR
133: } imm_b_sel_e;
134:
135: // Regfile write data selection
136: typedef enum logic [1:0] {
137: RF_WD_LSU,
138: RF_WD_EX,
139: RF_WD_CSR
140: } rf_wd_sel_e;
141:
142: //////////////
143: // IF stage //
144: //////////////
145:
146: // PC mux selection
147: typedef enum logic [2:0] {
148: PC_BOOT,
149: PC_JUMP,
150: PC_EXC,
151: PC_ERET,
152: PC_DRET
153: } pc_sel_e;
154:
155: // Exception PC mux selection
156: typedef enum logic [1:0] {
157: EXC_PC_EXC,
158: EXC_PC_IRQ,
159: EXC_PC_DBD,
160: EXC_PC_DBG_EXC // Exception while in debug mode
161: } exc_pc_sel_e;
162:
163: // Exception cause
164: typedef enum logic [5:0] {
165: EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03},
166: EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07},
167: EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11},
168: // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16},
169: // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30},
170: EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15
171: EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00},
172: EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01},
173: EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02},
174: EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03},
175: EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05},
176: EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},
177: EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08},
178: EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}
179: } exc_cause_e;
180:
181: // Debug cause
182: typedef enum logic [2:0] {
183: DBG_CAUSE_NONE = 3'h0,
184: DBG_CAUSE_EBREAK = 3'h1,
185: DBG_CAUSE_TRIGGER = 3'h2,
186: DBG_CAUSE_HALTREQ = 3'h3,
187: DBG_CAUSE_STEP = 3'h4
188: } dbg_cause_e;
189:
190: // PMP constants
191: parameter int unsigned PMP_MAX_REGIONS = 16;
192: parameter int unsigned PMP_CFG_W = 8;
193:
194: // PMP acces type
195: parameter int unsigned PMP_I = 0;
196: parameter int unsigned PMP_D = 1;
197:
198: typedef enum logic [1:0] {
199: PMP_ACC_EXEC = 2'b00,
200: PMP_ACC_WRITE = 2'b01,
201: PMP_ACC_READ = 2'b10
202: } pmp_req_e;
203:
204: // PMP cfg structures
205: typedef enum logic [1:0] {
206: PMP_MODE_OFF = 2'b00,
207: PMP_MODE_TOR = 2'b01,
208: PMP_MODE_NA4 = 2'b10,
209: PMP_MODE_NAPOT = 2'b11
210: } pmp_cfg_mode_e;
211:
212: typedef struct packed {
213: logic lock;
214: pmp_cfg_mode_e mode;
215: logic exec;
216: logic write;
217: logic read;
218: } pmp_cfg_t;
219:
220: // CSRs
221: typedef enum logic[11:0] {
222: // Machine information
223: CSR_MHARTID = 12'hF14,
224:
225: // Machine trap setup
226: CSR_MSTATUS = 12'h300,
227: CSR_MISA = 12'h301,
228: CSR_MIE = 12'h304,
229: CSR_MTVEC = 12'h305,
230:
231: // Machine trap handling
232: CSR_MSCRATCH = 12'h340,
233: CSR_MEPC = 12'h341,
234: CSR_MCAUSE = 12'h342,
235: CSR_MTVAL = 12'h343,
236: CSR_MIP = 12'h344,
237:
238: // Physical memory protection
239: CSR_PMPCFG0 = 12'h3A0,
240: CSR_PMPCFG1 = 12'h3A1,
241: CSR_PMPCFG2 = 12'h3A2,
242: CSR_PMPCFG3 = 12'h3A3,
243: CSR_PMPADDR0 = 12'h3B0,
244: CSR_PMPADDR1 = 12'h3B1,
245: CSR_PMPADDR2 = 12'h3B2,
246: CSR_PMPADDR3 = 12'h3B3,
247: CSR_PMPADDR4 = 12'h3B4,
248: CSR_PMPADDR5 = 12'h3B5,
249: CSR_PMPADDR6 = 12'h3B6,
250: CSR_PMPADDR7 = 12'h3B7,
251: CSR_PMPADDR8 = 12'h3B8,
252: CSR_PMPADDR9 = 12'h3B9,
253: CSR_PMPADDR10 = 12'h3BA,
254: CSR_PMPADDR11 = 12'h3BB,
255: CSR_PMPADDR12 = 12'h3BC,
256: CSR_PMPADDR13 = 12'h3BD,
257: CSR_PMPADDR14 = 12'h3BE,
258: CSR_PMPADDR15 = 12'h3BF,
259:
260: // Debug trigger
261: CSR_TSELECT = 12'h7A0,
262: CSR_TDATA1 = 12'h7A1,
263: CSR_TDATA2 = 12'h7A2,
264: CSR_TDATA3 = 12'h7A3,
265: CSR_MCONTEXT = 12'h7A8,
266: CSR_SCONTEXT = 12'h7AA,
267:
268: // Debug/trace
269: CSR_DCSR = 12'h7b0,
270: CSR_DPC = 12'h7b1,
271:
272: // Debug
273: CSR_DSCRATCH0 = 12'h7b2, // optional
274: CSR_DSCRATCH1 = 12'h7b3, // optional
275:
276: // Machine Counter/Timers
277: CSR_MCOUNTINHIBIT = 12'h320,
278: CSR_MHPMEVENT3 = 12'h323,
279: CSR_MHPMEVENT4 = 12'h324,
280: CSR_MHPMEVENT5 = 12'h325,
281: CSR_MHPMEVENT6 = 12'h326,
282: CSR_MHPMEVENT7 = 12'h327,
283: CSR_MHPMEVENT8 = 12'h328,
284: CSR_MHPMEVENT9 = 12'h329,
285: CSR_MHPMEVENT10 = 12'h32A,
286: CSR_MHPMEVENT11 = 12'h32B,
287: CSR_MHPMEVENT12 = 12'h32C,
288: CSR_MHPMEVENT13 = 12'h32D,
289: CSR_MHPMEVENT14 = 12'h32E,
290: CSR_MHPMEVENT15 = 12'h32F,
291: CSR_MHPMEVENT16 = 12'h330,
292: CSR_MHPMEVENT17 = 12'h331,
293: CSR_MHPMEVENT18 = 12'h332,
294: CSR_MHPMEVENT19 = 12'h333,
295: CSR_MHPMEVENT20 = 12'h334,
296: CSR_MHPMEVENT21 = 12'h335,
297: CSR_MHPMEVENT22 = 12'h336,
298: CSR_MHPMEVENT23 = 12'h337,
299: CSR_MHPMEVENT24 = 12'h338,
300: CSR_MHPMEVENT25 = 12'h339,
301: CSR_MHPMEVENT26 = 12'h33A,
302: CSR_MHPMEVENT27 = 12'h33B,
303: CSR_MHPMEVENT28 = 12'h33C,
304: CSR_MHPMEVENT29 = 12'h33D,
305: CSR_MHPMEVENT30 = 12'h33E,
306: CSR_MHPMEVENT31 = 12'h33F,
307: CSR_MCYCLE = 12'hB00,
308: CSR_MINSTRET = 12'hB02,
309: CSR_MHPMCOUNTER3 = 12'hB03,
310: CSR_MHPMCOUNTER4 = 12'hB04,
311: CSR_MHPMCOUNTER5 = 12'hB05,
312: CSR_MHPMCOUNTER6 = 12'hB06,
313: CSR_MHPMCOUNTER7 = 12'hB07,
314: CSR_MHPMCOUNTER8 = 12'hB08,
315: CSR_MHPMCOUNTER9 = 12'hB09,
316: CSR_MHPMCOUNTER10 = 12'hB0A,
317: CSR_MHPMCOUNTER11 = 12'hB0B,
318: CSR_MHPMCOUNTER12 = 12'hB0C,
319: CSR_MHPMCOUNTER13 = 12'hB0D,
320: CSR_MHPMCOUNTER14 = 12'hB0E,
321: CSR_MHPMCOUNTER15 = 12'hB0F,
322: CSR_MHPMCOUNTER16 = 12'hB10,
323: CSR_MHPMCOUNTER17 = 12'hB11,
324: CSR_MHPMCOUNTER18 = 12'hB12,
325: CSR_MHPMCOUNTER19 = 12'hB13,
326: CSR_MHPMCOUNTER20 = 12'hB14,
327: CSR_MHPMCOUNTER21 = 12'hB15,
328: CSR_MHPMCOUNTER22 = 12'hB16,
329: CSR_MHPMCOUNTER23 = 12'hB17,
330: CSR_MHPMCOUNTER24 = 12'hB18,
331: CSR_MHPMCOUNTER25 = 12'hB19,
332: CSR_MHPMCOUNTER26 = 12'hB1A,
333: CSR_MHPMCOUNTER27 = 12'hB1B,
334: CSR_MHPMCOUNTER28 = 12'hB1C,
335: CSR_MHPMCOUNTER29 = 12'hB1D,
336: CSR_MHPMCOUNTER30 = 12'hB1E,
337: CSR_MHPMCOUNTER31 = 12'hB1F,
338: CSR_MCYCLEH = 12'hB80,
339: CSR_MINSTRETH = 12'hB82,
340: CSR_MHPMCOUNTER3H = 12'hB83,
341: CSR_MHPMCOUNTER4H = 12'hB84,
342: CSR_MHPMCOUNTER5H = 12'hB85,
343: CSR_MHPMCOUNTER6H = 12'hB86,
344: CSR_MHPMCOUNTER7H = 12'hB87,
345: CSR_MHPMCOUNTER8H = 12'hB88,
346: CSR_MHPMCOUNTER9H = 12'hB89,
347: CSR_MHPMCOUNTER10H = 12'hB8A,
348: CSR_MHPMCOUNTER11H = 12'hB8B,
349: CSR_MHPMCOUNTER12H = 12'hB8C,
350: CSR_MHPMCOUNTER13H = 12'hB8D,
351: CSR_MHPMCOUNTER14H = 12'hB8E,
352: CSR_MHPMCOUNTER15H = 12'hB8F,
353: CSR_MHPMCOUNTER16H = 12'hB90,
354: CSR_MHPMCOUNTER17H = 12'hB91,
355: CSR_MHPMCOUNTER18H = 12'hB92,
356: CSR_MHPMCOUNTER19H = 12'hB93,
357: CSR_MHPMCOUNTER20H = 12'hB94,
358: CSR_MHPMCOUNTER21H = 12'hB95,
359: CSR_MHPMCOUNTER22H = 12'hB96,
360: CSR_MHPMCOUNTER23H = 12'hB97,
361: CSR_MHPMCOUNTER24H = 12'hB98,
362: CSR_MHPMCOUNTER25H = 12'hB99,
363: CSR_MHPMCOUNTER26H = 12'hB9A,
364: CSR_MHPMCOUNTER27H = 12'hB9B,
365: CSR_MHPMCOUNTER28H = 12'hB9C,
366: CSR_MHPMCOUNTER29H = 12'hB9D,
367: CSR_MHPMCOUNTER30H = 12'hB9E,
368: CSR_MHPMCOUNTER31H = 12'hB9F
369: } csr_num_e;
370:
371: // CSR pmp-related offsets
372: parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3
373: parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf
374:
375: // CSR status bits
376: parameter int unsigned CSR_MSTATUS_MIE_BIT = 3;
377: parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7;
378: parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11;
379: parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;
380: parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17;
381: parameter int unsigned CSR_MSTATUS_TW_BIT = 21;
382:
383: // CSR interrupt pending/enable bits
384: parameter int unsigned CSR_MSIX_BIT = 3;
385: parameter int unsigned CSR_MTIX_BIT = 7;
386: parameter int unsigned CSR_MEIX_BIT = 11;
387: parameter int unsigned CSR_MFIX_BIT_LOW = 16;
388: parameter int unsigned CSR_MFIX_BIT_HIGH = 30;
389:
390: endpackage
391: