../src/lowrisc_ip_aes_0.6/rtl/aes_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package aes_reg_pkg;
8:
9: // Param list
10: parameter int NumRegsKey = 8;
11: parameter int NumRegsIv = 4;
12: parameter int NumRegsData = 4;
13:
14: ////////////////////////////
15: // Typedefs for registers //
16: ////////////////////////////
17: typedef struct packed {
18: logic [31:0] q;
19: logic qe;
20: } aes_reg2hw_key_mreg_t;
21:
22: typedef struct packed {
23: logic [31:0] q;
24: logic qe;
25: } aes_reg2hw_iv_mreg_t;
26:
27: typedef struct packed {
28: logic [31:0] q;
29: logic qe;
30: } aes_reg2hw_data_in_mreg_t;
31:
32: typedef struct packed {
33: logic [31:0] q;
34: logic re;
35: } aes_reg2hw_data_out_mreg_t;
36:
37: typedef struct packed {
38: struct packed {
39: logic q;
40: logic qe;
41: } operation;
42: struct packed {
43: logic [2:0] q;
44: logic qe;
45: } mode;
46: struct packed {
47: logic [2:0] q;
48: logic qe;
49: } key_len;
50: struct packed {
51: logic q;
52: logic qe;
53: } manual_operation;
54: } aes_reg2hw_ctrl_reg_t;
55:
56: typedef struct packed {
57: struct packed {
58: logic q;
59: } start;
60: struct packed {
61: logic q;
62: } key_clear;
63: struct packed {
64: logic q;
65: } iv_clear;
66: struct packed {
67: logic q;
68: } data_in_clear;
69: struct packed {
70: logic q;
71: } data_out_clear;
72: struct packed {
73: logic q;
74: } prng_reseed;
75: } aes_reg2hw_trigger_reg_t;
76:
77:
78: typedef struct packed {
79: logic [31:0] d;
80: } aes_hw2reg_key_mreg_t;
81:
82: typedef struct packed {
83: logic [31:0] d;
84: } aes_hw2reg_iv_mreg_t;
85:
86: typedef struct packed {
87: logic [31:0] d;
88: logic de;
89: } aes_hw2reg_data_in_mreg_t;
90:
91: typedef struct packed {
92: logic [31:0] d;
93: } aes_hw2reg_data_out_mreg_t;
94:
95: typedef struct packed {
96: struct packed {
97: logic d;
98: } operation;
99: struct packed {
100: logic [2:0] d;
101: } mode;
102: struct packed {
103: logic [2:0] d;
104: } key_len;
105: struct packed {
106: logic d;
107: } manual_operation;
108: } aes_hw2reg_ctrl_reg_t;
109:
110: typedef struct packed {
111: struct packed {
112: logic d;
113: logic de;
114: } start;
115: struct packed {
116: logic d;
117: logic de;
118: } key_clear;
119: struct packed {
120: logic d;
121: logic de;
122: } iv_clear;
123: struct packed {
124: logic d;
125: logic de;
126: } data_in_clear;
127: struct packed {
128: logic d;
129: logic de;
130: } data_out_clear;
131: struct packed {
132: logic d;
133: logic de;
134: } prng_reseed;
135: } aes_hw2reg_trigger_reg_t;
136:
137: typedef struct packed {
138: struct packed {
139: logic d;
140: logic de;
141: } idle;
142: struct packed {
143: logic d;
144: logic de;
145: } stall;
146: struct packed {
147: logic d;
148: logic de;
149: } output_valid;
150: struct packed {
151: logic d;
152: logic de;
153: } input_ready;
154: } aes_hw2reg_status_reg_t;
155:
156:
157: ///////////////////////////////////////
158: // Register to internal design logic //
159: ///////////////////////////////////////
160: typedef struct packed {
161: aes_reg2hw_key_mreg_t [7:0] key; // [677:414]
162: aes_reg2hw_iv_mreg_t [3:0] iv; // [413:282]
163: aes_reg2hw_data_in_mreg_t [3:0] data_in; // [281:150]
164: aes_reg2hw_data_out_mreg_t [3:0] data_out; // [149:18]
165: aes_reg2hw_ctrl_reg_t ctrl; // [17:6]
166: aes_reg2hw_trigger_reg_t trigger; // [5:0]
167: } aes_reg2hw_t;
168:
169: ///////////////////////////////////////
170: // Internal design logic to register //
171: ///////////////////////////////////////
172: typedef struct packed {
173: aes_hw2reg_key_mreg_t [7:0] key; // [671:416]
174: aes_hw2reg_iv_mreg_t [3:0] iv; // [415:288]
175: aes_hw2reg_data_in_mreg_t [3:0] data_in; // [287:156]
176: aes_hw2reg_data_out_mreg_t [3:0] data_out; // [155:28]
177: aes_hw2reg_ctrl_reg_t ctrl; // [27:16]
178: aes_hw2reg_trigger_reg_t trigger; // [15:10]
179: aes_hw2reg_status_reg_t status; // [9:10]
180: } aes_hw2reg_t;
181:
182: // Register Address
183: parameter logic [6:0] AES_KEY0_OFFSET = 7'h 0;
184: parameter logic [6:0] AES_KEY1_OFFSET = 7'h 4;
185: parameter logic [6:0] AES_KEY2_OFFSET = 7'h 8;
186: parameter logic [6:0] AES_KEY3_OFFSET = 7'h c;
187: parameter logic [6:0] AES_KEY4_OFFSET = 7'h 10;
188: parameter logic [6:0] AES_KEY5_OFFSET = 7'h 14;
189: parameter logic [6:0] AES_KEY6_OFFSET = 7'h 18;
190: parameter logic [6:0] AES_KEY7_OFFSET = 7'h 1c;
191: parameter logic [6:0] AES_IV0_OFFSET = 7'h 20;
192: parameter logic [6:0] AES_IV1_OFFSET = 7'h 24;
193: parameter logic [6:0] AES_IV2_OFFSET = 7'h 28;
194: parameter logic [6:0] AES_IV3_OFFSET = 7'h 2c;
195: parameter logic [6:0] AES_DATA_IN0_OFFSET = 7'h 30;
196: parameter logic [6:0] AES_DATA_IN1_OFFSET = 7'h 34;
197: parameter logic [6:0] AES_DATA_IN2_OFFSET = 7'h 38;
198: parameter logic [6:0] AES_DATA_IN3_OFFSET = 7'h 3c;
199: parameter logic [6:0] AES_DATA_OUT0_OFFSET = 7'h 40;
200: parameter logic [6:0] AES_DATA_OUT1_OFFSET = 7'h 44;
201: parameter logic [6:0] AES_DATA_OUT2_OFFSET = 7'h 48;
202: parameter logic [6:0] AES_DATA_OUT3_OFFSET = 7'h 4c;
203: parameter logic [6:0] AES_CTRL_OFFSET = 7'h 50;
204: parameter logic [6:0] AES_TRIGGER_OFFSET = 7'h 54;
205: parameter logic [6:0] AES_STATUS_OFFSET = 7'h 58;
206:
207:
208: // Register Index
209: typedef enum int {
210: AES_KEY0,
211: AES_KEY1,
212: AES_KEY2,
213: AES_KEY3,
214: AES_KEY4,
215: AES_KEY5,
216: AES_KEY6,
217: AES_KEY7,
218: AES_IV0,
219: AES_IV1,
220: AES_IV2,
221: AES_IV3,
222: AES_DATA_IN0,
223: AES_DATA_IN1,
224: AES_DATA_IN2,
225: AES_DATA_IN3,
226: AES_DATA_OUT0,
227: AES_DATA_OUT1,
228: AES_DATA_OUT2,
229: AES_DATA_OUT3,
230: AES_CTRL,
231: AES_TRIGGER,
232: AES_STATUS
233: } aes_id_e;
234:
235: // Register width information to check illegal writes
236: parameter logic [3:0] AES_PERMIT [23] = '{
237: 4'b 1111, // index[ 0] AES_KEY0
238: 4'b 1111, // index[ 1] AES_KEY1
239: 4'b 1111, // index[ 2] AES_KEY2
240: 4'b 1111, // index[ 3] AES_KEY3
241: 4'b 1111, // index[ 4] AES_KEY4
242: 4'b 1111, // index[ 5] AES_KEY5
243: 4'b 1111, // index[ 6] AES_KEY6
244: 4'b 1111, // index[ 7] AES_KEY7
245: 4'b 1111, // index[ 8] AES_IV0
246: 4'b 1111, // index[ 9] AES_IV1
247: 4'b 1111, // index[10] AES_IV2
248: 4'b 1111, // index[11] AES_IV3
249: 4'b 1111, // index[12] AES_DATA_IN0
250: 4'b 1111, // index[13] AES_DATA_IN1
251: 4'b 1111, // index[14] AES_DATA_IN2
252: 4'b 1111, // index[15] AES_DATA_IN3
253: 4'b 1111, // index[16] AES_DATA_OUT0
254: 4'b 1111, // index[17] AES_DATA_OUT1
255: 4'b 1111, // index[18] AES_DATA_OUT2
256: 4'b 1111, // index[19] AES_DATA_OUT3
257: 4'b 0001, // index[20] AES_CTRL
258: 4'b 0001, // index[21] AES_TRIGGER
259: 4'b 0001 // index[22] AES_STATUS
260: };
261: endpackage
262:
263: