../src/lowrisc_ip_hmac_0.1/rtl/hmac_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: `include "prim_assert.sv"
   8: 
   9: module hmac_reg_top (
  10:   input clk_i,
  11:   input rst_ni,
  12: 
  13:   // Below Regster interface can be changed
  14:   input  tlul_pkg::tl_h2d_t tl_i,
  15:   output tlul_pkg::tl_d2h_t tl_o,
  16: 
  17:   // Output port for window
  18:   output tlul_pkg::tl_h2d_t tl_win_o  [1],
  19:   input  tlul_pkg::tl_d2h_t tl_win_i  [1],
  20: 
  21:   // To HW
  22:   output hmac_reg_pkg::hmac_reg2hw_t reg2hw, // Write
  23:   input  hmac_reg_pkg::hmac_hw2reg_t hw2reg, // Read
  24: 
  25:   // Config
  26:   input devmode_i // If 1, explicit error return for unmapped register access
  27: );
  28: 
  29:   import hmac_reg_pkg::* ;
  30: 
  31:   localparam int AW = 12;
  32:   localparam int DW = 32;
  33:   localparam int DBW = DW/8;                    // Byte Width
  34: 
  35:   // register signals
  36:   logic           reg_we;
  37:   logic           reg_re;
  38:   logic [AW-1:0]  reg_addr;
  39:   logic [DW-1:0]  reg_wdata;
  40:   logic [DBW-1:0] reg_be;
  41:   logic [DW-1:0]  reg_rdata;
  42:   logic           reg_error;
  43: 
  44:   logic          addrmiss, wr_err;
  45: 
  46:   logic [DW-1:0] reg_rdata_next;
  47: 
  48:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  49:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  50: 
  51:   tlul_pkg::tl_h2d_t tl_socket_h2d [2];
  52:   tlul_pkg::tl_d2h_t tl_socket_d2h [2];
  53: 
  54:   logic [1:0] reg_steer;
  55: 
  56:   // socket_1n connection
  57:   assign tl_reg_h2d = tl_socket_h2d[1];
  58:   assign tl_socket_d2h[1] = tl_reg_d2h;
  59: 
  60:   assign tl_win_o[0] = tl_socket_h2d[0];
  61:   assign tl_socket_d2h[0] = tl_win_i[0];
  62: 
  63:   // Create Socket_1n
  64:   tlul_socket_1n #(
  65:     .N          (2),
  66:     .HReqPass   (1'b1),
  67:     .HRspPass   (1'b1),
  68:     .DReqPass   ({2{1'b1}}),
  69:     .DRspPass   ({2{1'b1}}),
  70:     .HReqDepth  (4'h0),
  71:     .HRspDepth  (4'h0),
  72:     .DReqDepth  ({2{4'h0}}),
  73:     .DRspDepth  ({2{4'h0}})
  74:   ) u_socket (
  75:     .clk_i,
  76:     .rst_ni,
  77:     .tl_h_i (tl_i),
  78:     .tl_h_o (tl_o),
  79:     .tl_d_o (tl_socket_h2d),
  80:     .tl_d_i (tl_socket_d2h),
  81:     .dev_select (reg_steer)
  82:   );
  83: 
  84:   // Create steering logic
  85:   always_comb begin
  86:     reg_steer = 1;       // Default set to register
  87: 
  88:     // TODO: Can below codes be unique case () inside ?
  89:     if (tl_i.a_address[AW-1:0] >= 2048) begin
  90:       // Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
  91:       reg_steer = 0;
  92:     end
  93:   end
  94: 
  95:   tlul_adapter_reg #(
  96:     .RegAw(AW),
  97:     .RegDw(DW)
  98:   ) u_reg_if (
  99:     .clk_i,
 100:     .rst_ni,
 101: 
 102:     .tl_i (tl_reg_h2d),
 103:     .tl_o (tl_reg_d2h),
 104: 
 105:     .we_o    (reg_we),
 106:     .re_o    (reg_re),
 107:     .addr_o  (reg_addr),
 108:     .wdata_o (reg_wdata),
 109:     .be_o    (reg_be),
 110:     .rdata_i (reg_rdata),
 111:     .error_i (reg_error)
 112:   );
 113: 
 114:   assign reg_rdata = reg_rdata_next ;
 115:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
 116: 
 117:   // Define SW related signals
 118:   // Format: __{wd|we|qs}
 119:   //        or _{wd|we|qs} if field == 1 or 0
 120:   logic intr_state_hmac_done_qs;
 121:   logic intr_state_hmac_done_wd;
 122:   logic intr_state_hmac_done_we;
 123:   logic intr_state_fifo_empty_qs;
 124:   logic intr_state_fifo_empty_wd;
 125:   logic intr_state_fifo_empty_we;
 126:   logic intr_state_hmac_err_qs;
 127:   logic intr_state_hmac_err_wd;
 128:   logic intr_state_hmac_err_we;
 129:   logic intr_enable_hmac_done_qs;
 130:   logic intr_enable_hmac_done_wd;
 131:   logic intr_enable_hmac_done_we;
 132:   logic intr_enable_fifo_empty_qs;
 133:   logic intr_enable_fifo_empty_wd;
 134:   logic intr_enable_fifo_empty_we;
 135:   logic intr_enable_hmac_err_qs;
 136:   logic intr_enable_hmac_err_wd;
 137:   logic intr_enable_hmac_err_we;
 138:   logic intr_test_hmac_done_wd;
 139:   logic intr_test_hmac_done_we;
 140:   logic intr_test_fifo_empty_wd;
 141:   logic intr_test_fifo_empty_we;
 142:   logic intr_test_hmac_err_wd;
 143:   logic intr_test_hmac_err_we;
 144:   logic cfg_hmac_en_qs;
 145:   logic cfg_hmac_en_wd;
 146:   logic cfg_hmac_en_we;
 147:   logic cfg_hmac_en_re;
 148:   logic cfg_sha_en_qs;
 149:   logic cfg_sha_en_wd;
 150:   logic cfg_sha_en_we;
 151:   logic cfg_sha_en_re;
 152:   logic cfg_endian_swap_qs;
 153:   logic cfg_endian_swap_wd;
 154:   logic cfg_endian_swap_we;
 155:   logic cfg_endian_swap_re;
 156:   logic cfg_digest_swap_qs;
 157:   logic cfg_digest_swap_wd;
 158:   logic cfg_digest_swap_we;
 159:   logic cfg_digest_swap_re;
 160:   logic cmd_hash_start_wd;
 161:   logic cmd_hash_start_we;
 162:   logic cmd_hash_process_wd;
 163:   logic cmd_hash_process_we;
 164:   logic status_fifo_empty_qs;
 165:   logic status_fifo_empty_re;
 166:   logic status_fifo_full_qs;
 167:   logic status_fifo_full_re;
 168:   logic [4:0] status_fifo_depth_qs;
 169:   logic status_fifo_depth_re;
 170:   logic [31:0] err_code_qs;
 171:   logic [31:0] wipe_secret_wd;
 172:   logic wipe_secret_we;
 173:   logic [31:0] key0_wd;
 174:   logic key0_we;
 175:   logic [31:0] key1_wd;
 176:   logic key1_we;
 177:   logic [31:0] key2_wd;
 178:   logic key2_we;
 179:   logic [31:0] key3_wd;
 180:   logic key3_we;
 181:   logic [31:0] key4_wd;
 182:   logic key4_we;
 183:   logic [31:0] key5_wd;
 184:   logic key5_we;
 185:   logic [31:0] key6_wd;
 186:   logic key6_we;
 187:   logic [31:0] key7_wd;
 188:   logic key7_we;
 189:   logic [31:0] digest0_qs;
 190:   logic digest0_re;
 191:   logic [31:0] digest1_qs;
 192:   logic digest1_re;
 193:   logic [31:0] digest2_qs;
 194:   logic digest2_re;
 195:   logic [31:0] digest3_qs;
 196:   logic digest3_re;
 197:   logic [31:0] digest4_qs;
 198:   logic digest4_re;
 199:   logic [31:0] digest5_qs;
 200:   logic digest5_re;
 201:   logic [31:0] digest6_qs;
 202:   logic digest6_re;
 203:   logic [31:0] digest7_qs;
 204:   logic digest7_re;
 205:   logic [31:0] msg_length_lower_qs;
 206:   logic [31:0] msg_length_upper_qs;
 207: 
 208:   // Register instances
 209:   // R[intr_state]: V(False)
 210: 
 211:   //   F[hmac_done]: 0:0
 212:   prim_subreg #(
 213:     .DW      (1),
 214:     .SWACCESS("W1C"),
 215:     .RESVAL  (1'h0)
 216:   ) u_intr_state_hmac_done (
 217:     .clk_i   (clk_i    ),
 218:     .rst_ni  (rst_ni  ),
 219: 
 220:     // from register interface
 221:     .we     (intr_state_hmac_done_we),
 222:     .wd     (intr_state_hmac_done_wd),
 223: 
 224:     // from internal hardware
 225:     .de     (hw2reg.intr_state.hmac_done.de),
 226:     .d      (hw2reg.intr_state.hmac_done.d ),
 227: 
 228:     // to internal hardware
 229:     .qe     (),
 230:     .q      (reg2hw.intr_state.hmac_done.q ),
 231: 
 232:     // to register interface (read)
 233:     .qs     (intr_state_hmac_done_qs)
 234:   );
 235: 
 236: 
 237:   //   F[fifo_empty]: 1:1
 238:   prim_subreg #(
 239:     .DW      (1),
 240:     .SWACCESS("W1C"),
 241:     .RESVAL  (1'h0)
 242:   ) u_intr_state_fifo_empty (
 243:     .clk_i   (clk_i    ),
 244:     .rst_ni  (rst_ni  ),
 245: 
 246:     // from register interface
 247:     .we     (intr_state_fifo_empty_we),
 248:     .wd     (intr_state_fifo_empty_wd),
 249: 
 250:     // from internal hardware
 251:     .de     (hw2reg.intr_state.fifo_empty.de),
 252:     .d      (hw2reg.intr_state.fifo_empty.d ),
 253: 
 254:     // to internal hardware
 255:     .qe     (),
 256:     .q      (reg2hw.intr_state.fifo_empty.q ),
 257: 
 258:     // to register interface (read)
 259:     .qs     (intr_state_fifo_empty_qs)
 260:   );
 261: 
 262: 
 263:   //   F[hmac_err]: 2:2
 264:   prim_subreg #(
 265:     .DW      (1),
 266:     .SWACCESS("W1C"),
 267:     .RESVAL  (1'h0)
 268:   ) u_intr_state_hmac_err (
 269:     .clk_i   (clk_i    ),
 270:     .rst_ni  (rst_ni  ),
 271: 
 272:     // from register interface
 273:     .we     (intr_state_hmac_err_we),
 274:     .wd     (intr_state_hmac_err_wd),
 275: 
 276:     // from internal hardware
 277:     .de     (hw2reg.intr_state.hmac_err.de),
 278:     .d      (hw2reg.intr_state.hmac_err.d ),
 279: 
 280:     // to internal hardware
 281:     .qe     (),
 282:     .q      (reg2hw.intr_state.hmac_err.q ),
 283: 
 284:     // to register interface (read)
 285:     .qs     (intr_state_hmac_err_qs)
 286:   );
 287: 
 288: 
 289:   // R[intr_enable]: V(False)
 290: 
 291:   //   F[hmac_done]: 0:0
 292:   prim_subreg #(
 293:     .DW      (1),
 294:     .SWACCESS("RW"),
 295:     .RESVAL  (1'h0)
 296:   ) u_intr_enable_hmac_done (
 297:     .clk_i   (clk_i    ),
 298:     .rst_ni  (rst_ni  ),
 299: 
 300:     // from register interface
 301:     .we     (intr_enable_hmac_done_we),
 302:     .wd     (intr_enable_hmac_done_wd),
 303: 
 304:     // from internal hardware
 305:     .de     (1'b0),
 306:     .d      ('0  ),
 307: 
 308:     // to internal hardware
 309:     .qe     (),
 310:     .q      (reg2hw.intr_enable.hmac_done.q ),
 311: 
 312:     // to register interface (read)
 313:     .qs     (intr_enable_hmac_done_qs)
 314:   );
 315: 
 316: 
 317:   //   F[fifo_empty]: 1:1
 318:   prim_subreg #(
 319:     .DW      (1),
 320:     .SWACCESS("RW"),
 321:     .RESVAL  (1'h0)
 322:   ) u_intr_enable_fifo_empty (
 323:     .clk_i   (clk_i    ),
 324:     .rst_ni  (rst_ni  ),
 325: 
 326:     // from register interface
 327:     .we     (intr_enable_fifo_empty_we),
 328:     .wd     (intr_enable_fifo_empty_wd),
 329: 
 330:     // from internal hardware
 331:     .de     (1'b0),
 332:     .d      ('0  ),
 333: 
 334:     // to internal hardware
 335:     .qe     (),
 336:     .q      (reg2hw.intr_enable.fifo_empty.q ),
 337: 
 338:     // to register interface (read)
 339:     .qs     (intr_enable_fifo_empty_qs)
 340:   );
 341: 
 342: 
 343:   //   F[hmac_err]: 2:2
 344:   prim_subreg #(
 345:     .DW      (1),
 346:     .SWACCESS("RW"),
 347:     .RESVAL  (1'h0)
 348:   ) u_intr_enable_hmac_err (
 349:     .clk_i   (clk_i    ),
 350:     .rst_ni  (rst_ni  ),
 351: 
 352:     // from register interface
 353:     .we     (intr_enable_hmac_err_we),
 354:     .wd     (intr_enable_hmac_err_wd),
 355: 
 356:     // from internal hardware
 357:     .de     (1'b0),
 358:     .d      ('0  ),
 359: 
 360:     // to internal hardware
 361:     .qe     (),
 362:     .q      (reg2hw.intr_enable.hmac_err.q ),
 363: 
 364:     // to register interface (read)
 365:     .qs     (intr_enable_hmac_err_qs)
 366:   );
 367: 
 368: 
 369:   // R[intr_test]: V(True)
 370: 
 371:   //   F[hmac_done]: 0:0
 372:   prim_subreg_ext #(
 373:     .DW    (1)
 374:   ) u_intr_test_hmac_done (
 375:     .re     (1'b0),
 376:     .we     (intr_test_hmac_done_we),
 377:     .wd     (intr_test_hmac_done_wd),
 378:     .d      ('0),
 379:     .qre    (),
 380:     .qe     (reg2hw.intr_test.hmac_done.qe),
 381:     .q      (reg2hw.intr_test.hmac_done.q ),
 382:     .qs     ()
 383:   );
 384: 
 385: 
 386:   //   F[fifo_empty]: 1:1
 387:   prim_subreg_ext #(
 388:     .DW    (1)
 389:   ) u_intr_test_fifo_empty (
 390:     .re     (1'b0),
 391:     .we     (intr_test_fifo_empty_we),
 392:     .wd     (intr_test_fifo_empty_wd),
 393:     .d      ('0),
 394:     .qre    (),
 395:     .qe     (reg2hw.intr_test.fifo_empty.qe),
 396:     .q      (reg2hw.intr_test.fifo_empty.q ),
 397:     .qs     ()
 398:   );
 399: 
 400: 
 401:   //   F[hmac_err]: 2:2
 402:   prim_subreg_ext #(
 403:     .DW    (1)
 404:   ) u_intr_test_hmac_err (
 405:     .re     (1'b0),
 406:     .we     (intr_test_hmac_err_we),
 407:     .wd     (intr_test_hmac_err_wd),
 408:     .d      ('0),
 409:     .qre    (),
 410:     .qe     (reg2hw.intr_test.hmac_err.qe),
 411:     .q      (reg2hw.intr_test.hmac_err.q ),
 412:     .qs     ()
 413:   );
 414: 
 415: 
 416:   // R[cfg]: V(True)
 417: 
 418:   //   F[hmac_en]: 0:0
 419:   prim_subreg_ext #(
 420:     .DW    (1)
 421:   ) u_cfg_hmac_en (
 422:     .re     (cfg_hmac_en_re),
 423:     .we     (cfg_hmac_en_we),
 424:     .wd     (cfg_hmac_en_wd),
 425:     .d      (hw2reg.cfg.hmac_en.d),
 426:     .qre    (),
 427:     .qe     (reg2hw.cfg.hmac_en.qe),
 428:     .q      (reg2hw.cfg.hmac_en.q ),
 429:     .qs     (cfg_hmac_en_qs)
 430:   );
 431: 
 432: 
 433:   //   F[sha_en]: 1:1
 434:   prim_subreg_ext #(
 435:     .DW    (1)
 436:   ) u_cfg_sha_en (
 437:     .re     (cfg_sha_en_re),
 438:     .we     (cfg_sha_en_we),
 439:     .wd     (cfg_sha_en_wd),
 440:     .d      (hw2reg.cfg.sha_en.d),
 441:     .qre    (),
 442:     .qe     (reg2hw.cfg.sha_en.qe),
 443:     .q      (reg2hw.cfg.sha_en.q ),
 444:     .qs     (cfg_sha_en_qs)
 445:   );
 446: 
 447: 
 448:   //   F[endian_swap]: 2:2
 449:   prim_subreg_ext #(
 450:     .DW    (1)
 451:   ) u_cfg_endian_swap (
 452:     .re     (cfg_endian_swap_re),
 453:     .we     (cfg_endian_swap_we),
 454:     .wd     (cfg_endian_swap_wd),
 455:     .d      (hw2reg.cfg.endian_swap.d),
 456:     .qre    (),
 457:     .qe     (reg2hw.cfg.endian_swap.qe),
 458:     .q      (reg2hw.cfg.endian_swap.q ),
 459:     .qs     (cfg_endian_swap_qs)
 460:   );
 461: 
 462: 
 463:   //   F[digest_swap]: 3:3
 464:   prim_subreg_ext #(
 465:     .DW    (1)
 466:   ) u_cfg_digest_swap (
 467:     .re     (cfg_digest_swap_re),
 468:     .we     (cfg_digest_swap_we),
 469:     .wd     (cfg_digest_swap_wd),
 470:     .d      (hw2reg.cfg.digest_swap.d),
 471:     .qre    (),
 472:     .qe     (reg2hw.cfg.digest_swap.qe),
 473:     .q      (reg2hw.cfg.digest_swap.q ),
 474:     .qs     (cfg_digest_swap_qs)
 475:   );
 476: 
 477: 
 478:   // R[cmd]: V(True)
 479: 
 480:   //   F[hash_start]: 0:0
 481:   prim_subreg_ext #(
 482:     .DW    (1)
 483:   ) u_cmd_hash_start (
 484:     .re     (1'b0),
 485:     .we     (cmd_hash_start_we),
 486:     .wd     (cmd_hash_start_wd),
 487:     .d      ('0),
 488:     .qre    (),
 489:     .qe     (reg2hw.cmd.hash_start.qe),
 490:     .q      (reg2hw.cmd.hash_start.q ),
 491:     .qs     ()
 492:   );
 493: 
 494: 
 495:   //   F[hash_process]: 1:1
 496:   prim_subreg_ext #(
 497:     .DW    (1)
 498:   ) u_cmd_hash_process (
 499:     .re     (1'b0),
 500:     .we     (cmd_hash_process_we),
 501:     .wd     (cmd_hash_process_wd),
 502:     .d      ('0),
 503:     .qre    (),
 504:     .qe     (reg2hw.cmd.hash_process.qe),
 505:     .q      (reg2hw.cmd.hash_process.q ),
 506:     .qs     ()
 507:   );
 508: 
 509: 
 510:   // R[status]: V(True)
 511: 
 512:   //   F[fifo_empty]: 0:0
 513:   prim_subreg_ext #(
 514:     .DW    (1)
 515:   ) u_status_fifo_empty (
 516:     .re     (status_fifo_empty_re),
 517:     .we     (1'b0),
 518:     .wd     ('0),
 519:     .d      (hw2reg.status.fifo_empty.d),
 520:     .qre    (),
 521:     .qe     (),
 522:     .q      (),
 523:     .qs     (status_fifo_empty_qs)
 524:   );
 525: 
 526: 
 527:   //   F[fifo_full]: 1:1
 528:   prim_subreg_ext #(
 529:     .DW    (1)
 530:   ) u_status_fifo_full (
 531:     .re     (status_fifo_full_re),
 532:     .we     (1'b0),
 533:     .wd     ('0),
 534:     .d      (hw2reg.status.fifo_full.d),
 535:     .qre    (),
 536:     .qe     (),
 537:     .q      (),
 538:     .qs     (status_fifo_full_qs)
 539:   );
 540: 
 541: 
 542:   //   F[fifo_depth]: 8:4
 543:   prim_subreg_ext #(
 544:     .DW    (5)
 545:   ) u_status_fifo_depth (
 546:     .re     (status_fifo_depth_re),
 547:     .we     (1'b0),
 548:     .wd     ('0),
 549:     .d      (hw2reg.status.fifo_depth.d),
 550:     .qre    (),
 551:     .qe     (),
 552:     .q      (),
 553:     .qs     (status_fifo_depth_qs)
 554:   );
 555: 
 556: 
 557:   // R[err_code]: V(False)
 558: 
 559:   prim_subreg #(
 560:     .DW      (32),
 561:     .SWACCESS("RO"),
 562:     .RESVAL  (32'h0)
 563:   ) u_err_code (
 564:     .clk_i   (clk_i    ),
 565:     .rst_ni  (rst_ni  ),
 566: 
 567:     .we     (1'b0),
 568:     .wd     ('0  ),
 569: 
 570:     // from internal hardware
 571:     .de     (hw2reg.err_code.de),
 572:     .d      (hw2reg.err_code.d ),
 573: 
 574:     // to internal hardware
 575:     .qe     (),
 576:     .q      (),
 577: 
 578:     // to register interface (read)
 579:     .qs     (err_code_qs)
 580:   );
 581: 
 582: 
 583:   // R[wipe_secret]: V(True)
 584: 
 585:   prim_subreg_ext #(
 586:     .DW    (32)
 587:   ) u_wipe_secret (
 588:     .re     (1'b0),
 589:     .we     (wipe_secret_we),
 590:     .wd     (wipe_secret_wd),
 591:     .d      ('0),
 592:     .qre    (),
 593:     .qe     (reg2hw.wipe_secret.qe),
 594:     .q      (reg2hw.wipe_secret.q ),
 595:     .qs     ()
 596:   );
 597: 
 598: 
 599: 
 600:   // Subregister 0 of Multireg key
 601:   // R[key0]: V(True)
 602: 
 603:   prim_subreg_ext #(
 604:     .DW    (32)
 605:   ) u_key0 (
 606:     .re     (1'b0),
 607:     .we     (key0_we),
 608:     .wd     (key0_wd),
 609:     .d      (hw2reg.key[0].d),
 610:     .qre    (),
 611:     .qe     (reg2hw.key[0].qe),
 612:     .q      (reg2hw.key[0].q ),
 613:     .qs     ()
 614:   );
 615: 
 616:   // Subregister 1 of Multireg key
 617:   // R[key1]: V(True)
 618: 
 619:   prim_subreg_ext #(
 620:     .DW    (32)
 621:   ) u_key1 (
 622:     .re     (1'b0),
 623:     .we     (key1_we),
 624:     .wd     (key1_wd),
 625:     .d      (hw2reg.key[1].d),
 626:     .qre    (),
 627:     .qe     (reg2hw.key[1].qe),
 628:     .q      (reg2hw.key[1].q ),
 629:     .qs     ()
 630:   );
 631: 
 632:   // Subregister 2 of Multireg key
 633:   // R[key2]: V(True)
 634: 
 635:   prim_subreg_ext #(
 636:     .DW    (32)
 637:   ) u_key2 (
 638:     .re     (1'b0),
 639:     .we     (key2_we),
 640:     .wd     (key2_wd),
 641:     .d      (hw2reg.key[2].d),
 642:     .qre    (),
 643:     .qe     (reg2hw.key[2].qe),
 644:     .q      (reg2hw.key[2].q ),
 645:     .qs     ()
 646:   );
 647: 
 648:   // Subregister 3 of Multireg key
 649:   // R[key3]: V(True)
 650: 
 651:   prim_subreg_ext #(
 652:     .DW    (32)
 653:   ) u_key3 (
 654:     .re     (1'b0),
 655:     .we     (key3_we),
 656:     .wd     (key3_wd),
 657:     .d      (hw2reg.key[3].d),
 658:     .qre    (),
 659:     .qe     (reg2hw.key[3].qe),
 660:     .q      (reg2hw.key[3].q ),
 661:     .qs     ()
 662:   );
 663: 
 664:   // Subregister 4 of Multireg key
 665:   // R[key4]: V(True)
 666: 
 667:   prim_subreg_ext #(
 668:     .DW    (32)
 669:   ) u_key4 (
 670:     .re     (1'b0),
 671:     .we     (key4_we),
 672:     .wd     (key4_wd),
 673:     .d      (hw2reg.key[4].d),
 674:     .qre    (),
 675:     .qe     (reg2hw.key[4].qe),
 676:     .q      (reg2hw.key[4].q ),
 677:     .qs     ()
 678:   );
 679: 
 680:   // Subregister 5 of Multireg key
 681:   // R[key5]: V(True)
 682: 
 683:   prim_subreg_ext #(
 684:     .DW    (32)
 685:   ) u_key5 (
 686:     .re     (1'b0),
 687:     .we     (key5_we),
 688:     .wd     (key5_wd),
 689:     .d      (hw2reg.key[5].d),
 690:     .qre    (),
 691:     .qe     (reg2hw.key[5].qe),
 692:     .q      (reg2hw.key[5].q ),
 693:     .qs     ()
 694:   );
 695: 
 696:   // Subregister 6 of Multireg key
 697:   // R[key6]: V(True)
 698: 
 699:   prim_subreg_ext #(
 700:     .DW    (32)
 701:   ) u_key6 (
 702:     .re     (1'b0),
 703:     .we     (key6_we),
 704:     .wd     (key6_wd),
 705:     .d      (hw2reg.key[6].d),
 706:     .qre    (),
 707:     .qe     (reg2hw.key[6].qe),
 708:     .q      (reg2hw.key[6].q ),
 709:     .qs     ()
 710:   );
 711: 
 712:   // Subregister 7 of Multireg key
 713:   // R[key7]: V(True)
 714: 
 715:   prim_subreg_ext #(
 716:     .DW    (32)
 717:   ) u_key7 (
 718:     .re     (1'b0),
 719:     .we     (key7_we),
 720:     .wd     (key7_wd),
 721:     .d      (hw2reg.key[7].d),
 722:     .qre    (),
 723:     .qe     (reg2hw.key[7].qe),
 724:     .q      (reg2hw.key[7].q ),
 725:     .qs     ()
 726:   );
 727: 
 728: 
 729: 
 730:   // Subregister 0 of Multireg digest
 731:   // R[digest0]: V(True)
 732: 
 733:   prim_subreg_ext #(
 734:     .DW    (32)
 735:   ) u_digest0 (
 736:     .re     (digest0_re),
 737:     .we     (1'b0),
 738:     .wd     ('0),
 739:     .d      (hw2reg.digest[0].d),
 740:     .qre    (),
 741:     .qe     (),
 742:     .q      (),
 743:     .qs     (digest0_qs)
 744:   );
 745: 
 746:   // Subregister 1 of Multireg digest
 747:   // R[digest1]: V(True)
 748: 
 749:   prim_subreg_ext #(
 750:     .DW    (32)
 751:   ) u_digest1 (
 752:     .re     (digest1_re),
 753:     .we     (1'b0),
 754:     .wd     ('0),
 755:     .d      (hw2reg.digest[1].d),
 756:     .qre    (),
 757:     .qe     (),
 758:     .q      (),
 759:     .qs     (digest1_qs)
 760:   );
 761: 
 762:   // Subregister 2 of Multireg digest
 763:   // R[digest2]: V(True)
 764: 
 765:   prim_subreg_ext #(
 766:     .DW    (32)
 767:   ) u_digest2 (
 768:     .re     (digest2_re),
 769:     .we     (1'b0),
 770:     .wd     ('0),
 771:     .d      (hw2reg.digest[2].d),
 772:     .qre    (),
 773:     .qe     (),
 774:     .q      (),
 775:     .qs     (digest2_qs)
 776:   );
 777: 
 778:   // Subregister 3 of Multireg digest
 779:   // R[digest3]: V(True)
 780: 
 781:   prim_subreg_ext #(
 782:     .DW    (32)
 783:   ) u_digest3 (
 784:     .re     (digest3_re),
 785:     .we     (1'b0),
 786:     .wd     ('0),
 787:     .d      (hw2reg.digest[3].d),
 788:     .qre    (),
 789:     .qe     (),
 790:     .q      (),
 791:     .qs     (digest3_qs)
 792:   );
 793: 
 794:   // Subregister 4 of Multireg digest
 795:   // R[digest4]: V(True)
 796: 
 797:   prim_subreg_ext #(
 798:     .DW    (32)
 799:   ) u_digest4 (
 800:     .re     (digest4_re),
 801:     .we     (1'b0),
 802:     .wd     ('0),
 803:     .d      (hw2reg.digest[4].d),
 804:     .qre    (),
 805:     .qe     (),
 806:     .q      (),
 807:     .qs     (digest4_qs)
 808:   );
 809: 
 810:   // Subregister 5 of Multireg digest
 811:   // R[digest5]: V(True)
 812: 
 813:   prim_subreg_ext #(
 814:     .DW    (32)
 815:   ) u_digest5 (
 816:     .re     (digest5_re),
 817:     .we     (1'b0),
 818:     .wd     ('0),
 819:     .d      (hw2reg.digest[5].d),
 820:     .qre    (),
 821:     .qe     (),
 822:     .q      (),
 823:     .qs     (digest5_qs)
 824:   );
 825: 
 826:   // Subregister 6 of Multireg digest
 827:   // R[digest6]: V(True)
 828: 
 829:   prim_subreg_ext #(
 830:     .DW    (32)
 831:   ) u_digest6 (
 832:     .re     (digest6_re),
 833:     .we     (1'b0),
 834:     .wd     ('0),
 835:     .d      (hw2reg.digest[6].d),
 836:     .qre    (),
 837:     .qe     (),
 838:     .q      (),
 839:     .qs     (digest6_qs)
 840:   );
 841: 
 842:   // Subregister 7 of Multireg digest
 843:   // R[digest7]: V(True)
 844: 
 845:   prim_subreg_ext #(
 846:     .DW    (32)
 847:   ) u_digest7 (
 848:     .re     (digest7_re),
 849:     .we     (1'b0),
 850:     .wd     ('0),
 851:     .d      (hw2reg.digest[7].d),
 852:     .qre    (),
 853:     .qe     (),
 854:     .q      (),
 855:     .qs     (digest7_qs)
 856:   );
 857: 
 858: 
 859:   // R[msg_length_lower]: V(False)
 860: 
 861:   prim_subreg #(
 862:     .DW      (32),
 863:     .SWACCESS("RO"),
 864:     .RESVAL  (32'h0)
 865:   ) u_msg_length_lower (
 866:     .clk_i   (clk_i    ),
 867:     .rst_ni  (rst_ni  ),
 868: 
 869:     .we     (1'b0),
 870:     .wd     ('0  ),
 871: 
 872:     // from internal hardware
 873:     .de     (hw2reg.msg_length_lower.de),
 874:     .d      (hw2reg.msg_length_lower.d ),
 875: 
 876:     // to internal hardware
 877:     .qe     (),
 878:     .q      (),
 879: 
 880:     // to register interface (read)
 881:     .qs     (msg_length_lower_qs)
 882:   );
 883: 
 884: 
 885:   // R[msg_length_upper]: V(False)
 886: 
 887:   prim_subreg #(
 888:     .DW      (32),
 889:     .SWACCESS("RO"),
 890:     .RESVAL  (32'h0)
 891:   ) u_msg_length_upper (
 892:     .clk_i   (clk_i    ),
 893:     .rst_ni  (rst_ni  ),
 894: 
 895:     .we     (1'b0),
 896:     .wd     ('0  ),
 897: 
 898:     // from internal hardware
 899:     .de     (hw2reg.msg_length_upper.de),
 900:     .d      (hw2reg.msg_length_upper.d ),
 901: 
 902:     // to internal hardware
 903:     .qe     (),
 904:     .q      (),
 905: 
 906:     // to register interface (read)
 907:     .qs     (msg_length_upper_qs)
 908:   );
 909: 
 910: 
 911: 
 912: 
 913:   logic [25:0] addr_hit;
 914:   always_comb begin
 915:     addr_hit = '0;
 916:     addr_hit[ 0] = (reg_addr == HMAC_INTR_STATE_OFFSET);
 917:     addr_hit[ 1] = (reg_addr == HMAC_INTR_ENABLE_OFFSET);
 918:     addr_hit[ 2] = (reg_addr == HMAC_INTR_TEST_OFFSET);
 919:     addr_hit[ 3] = (reg_addr == HMAC_CFG_OFFSET);
 920:     addr_hit[ 4] = (reg_addr == HMAC_CMD_OFFSET);
 921:     addr_hit[ 5] = (reg_addr == HMAC_STATUS_OFFSET);
 922:     addr_hit[ 6] = (reg_addr == HMAC_ERR_CODE_OFFSET);
 923:     addr_hit[ 7] = (reg_addr == HMAC_WIPE_SECRET_OFFSET);
 924:     addr_hit[ 8] = (reg_addr == HMAC_KEY0_OFFSET);
 925:     addr_hit[ 9] = (reg_addr == HMAC_KEY1_OFFSET);
 926:     addr_hit[10] = (reg_addr == HMAC_KEY2_OFFSET);
 927:     addr_hit[11] = (reg_addr == HMAC_KEY3_OFFSET);
 928:     addr_hit[12] = (reg_addr == HMAC_KEY4_OFFSET);
 929:     addr_hit[13] = (reg_addr == HMAC_KEY5_OFFSET);
 930:     addr_hit[14] = (reg_addr == HMAC_KEY6_OFFSET);
 931:     addr_hit[15] = (reg_addr == HMAC_KEY7_OFFSET);
 932:     addr_hit[16] = (reg_addr == HMAC_DIGEST0_OFFSET);
 933:     addr_hit[17] = (reg_addr == HMAC_DIGEST1_OFFSET);
 934:     addr_hit[18] = (reg_addr == HMAC_DIGEST2_OFFSET);
 935:     addr_hit[19] = (reg_addr == HMAC_DIGEST3_OFFSET);
 936:     addr_hit[20] = (reg_addr == HMAC_DIGEST4_OFFSET);
 937:     addr_hit[21] = (reg_addr == HMAC_DIGEST5_OFFSET);
 938:     addr_hit[22] = (reg_addr == HMAC_DIGEST6_OFFSET);
 939:     addr_hit[23] = (reg_addr == HMAC_DIGEST7_OFFSET);
 940:     addr_hit[24] = (reg_addr == HMAC_MSG_LENGTH_LOWER_OFFSET);
 941:     addr_hit[25] = (reg_addr == HMAC_MSG_LENGTH_UPPER_OFFSET);
 942:   end
 943: 
 944:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
 945: 
 946:   // Check sub-word write is permitted
 947:   always_comb begin
 948:     wr_err = 1'b0;
 949:     if (addr_hit[ 0] && reg_we && (HMAC_PERMIT[ 0] != (HMAC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
 950:     if (addr_hit[ 1] && reg_we && (HMAC_PERMIT[ 1] != (HMAC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
 951:     if (addr_hit[ 2] && reg_we && (HMAC_PERMIT[ 2] != (HMAC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
 952:     if (addr_hit[ 3] && reg_we && (HMAC_PERMIT[ 3] != (HMAC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
 953:     if (addr_hit[ 4] && reg_we && (HMAC_PERMIT[ 4] != (HMAC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
 954:     if (addr_hit[ 5] && reg_we && (HMAC_PERMIT[ 5] != (HMAC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
 955:     if (addr_hit[ 6] && reg_we && (HMAC_PERMIT[ 6] != (HMAC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
 956:     if (addr_hit[ 7] && reg_we && (HMAC_PERMIT[ 7] != (HMAC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
 957:     if (addr_hit[ 8] && reg_we && (HMAC_PERMIT[ 8] != (HMAC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
 958:     if (addr_hit[ 9] && reg_we && (HMAC_PERMIT[ 9] != (HMAC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
 959:     if (addr_hit[10] && reg_we && (HMAC_PERMIT[10] != (HMAC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
 960:     if (addr_hit[11] && reg_we && (HMAC_PERMIT[11] != (HMAC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
 961:     if (addr_hit[12] && reg_we && (HMAC_PERMIT[12] != (HMAC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
 962:     if (addr_hit[13] && reg_we && (HMAC_PERMIT[13] != (HMAC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
 963:     if (addr_hit[14] && reg_we && (HMAC_PERMIT[14] != (HMAC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
 964:     if (addr_hit[15] && reg_we && (HMAC_PERMIT[15] != (HMAC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
 965:     if (addr_hit[16] && reg_we && (HMAC_PERMIT[16] != (HMAC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
 966:     if (addr_hit[17] && reg_we && (HMAC_PERMIT[17] != (HMAC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
 967:     if (addr_hit[18] && reg_we && (HMAC_PERMIT[18] != (HMAC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
 968:     if (addr_hit[19] && reg_we && (HMAC_PERMIT[19] != (HMAC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
 969:     if (addr_hit[20] && reg_we && (HMAC_PERMIT[20] != (HMAC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
 970:     if (addr_hit[21] && reg_we && (HMAC_PERMIT[21] != (HMAC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
 971:     if (addr_hit[22] && reg_we && (HMAC_PERMIT[22] != (HMAC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
 972:     if (addr_hit[23] && reg_we && (HMAC_PERMIT[23] != (HMAC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
 973:     if (addr_hit[24] && reg_we && (HMAC_PERMIT[24] != (HMAC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
 974:     if (addr_hit[25] && reg_we && (HMAC_PERMIT[25] != (HMAC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
 975:   end
 976: 
 977:   assign intr_state_hmac_done_we = addr_hit[0] & reg_we & ~wr_err;
 978:   assign intr_state_hmac_done_wd = reg_wdata[0];
 979: 
 980:   assign intr_state_fifo_empty_we = addr_hit[0] & reg_we & ~wr_err;
 981:   assign intr_state_fifo_empty_wd = reg_wdata[1];
 982: 
 983:   assign intr_state_hmac_err_we = addr_hit[0] & reg_we & ~wr_err;
 984:   assign intr_state_hmac_err_wd = reg_wdata[2];
 985: 
 986:   assign intr_enable_hmac_done_we = addr_hit[1] & reg_we & ~wr_err;
 987:   assign intr_enable_hmac_done_wd = reg_wdata[0];
 988: 
 989:   assign intr_enable_fifo_empty_we = addr_hit[1] & reg_we & ~wr_err;
 990:   assign intr_enable_fifo_empty_wd = reg_wdata[1];
 991: 
 992:   assign intr_enable_hmac_err_we = addr_hit[1] & reg_we & ~wr_err;
 993:   assign intr_enable_hmac_err_wd = reg_wdata[2];
 994: 
 995:   assign intr_test_hmac_done_we = addr_hit[2] & reg_we & ~wr_err;
 996:   assign intr_test_hmac_done_wd = reg_wdata[0];
 997: 
 998:   assign intr_test_fifo_empty_we = addr_hit[2] & reg_we & ~wr_err;
 999:   assign intr_test_fifo_empty_wd = reg_wdata[1];
1000: 
1001:   assign intr_test_hmac_err_we = addr_hit[2] & reg_we & ~wr_err;
1002:   assign intr_test_hmac_err_wd = reg_wdata[2];
1003: 
1004:   assign cfg_hmac_en_we = addr_hit[3] & reg_we & ~wr_err;
1005:   assign cfg_hmac_en_wd = reg_wdata[0];
1006:   assign cfg_hmac_en_re = addr_hit[3] && reg_re;
1007: 
1008:   assign cfg_sha_en_we = addr_hit[3] & reg_we & ~wr_err;
1009:   assign cfg_sha_en_wd = reg_wdata[1];
1010:   assign cfg_sha_en_re = addr_hit[3] && reg_re;
1011: 
1012:   assign cfg_endian_swap_we = addr_hit[3] & reg_we & ~wr_err;
1013:   assign cfg_endian_swap_wd = reg_wdata[2];
1014:   assign cfg_endian_swap_re = addr_hit[3] && reg_re;
1015: 
1016:   assign cfg_digest_swap_we = addr_hit[3] & reg_we & ~wr_err;
1017:   assign cfg_digest_swap_wd = reg_wdata[3];
1018:   assign cfg_digest_swap_re = addr_hit[3] && reg_re;
1019: 
1020:   assign cmd_hash_start_we = addr_hit[4] & reg_we & ~wr_err;
1021:   assign cmd_hash_start_wd = reg_wdata[0];
1022: 
1023:   assign cmd_hash_process_we = addr_hit[4] & reg_we & ~wr_err;
1024:   assign cmd_hash_process_wd = reg_wdata[1];
1025: 
1026:   assign status_fifo_empty_re = addr_hit[5] && reg_re;
1027: 
1028:   assign status_fifo_full_re = addr_hit[5] && reg_re;
1029: 
1030:   assign status_fifo_depth_re = addr_hit[5] && reg_re;
1031: 
1032: 
1033:   assign wipe_secret_we = addr_hit[7] & reg_we & ~wr_err;
1034:   assign wipe_secret_wd = reg_wdata[31:0];
1035: 
1036:   assign key0_we = addr_hit[8] & reg_we & ~wr_err;
1037:   assign key0_wd = reg_wdata[31:0];
1038: 
1039:   assign key1_we = addr_hit[9] & reg_we & ~wr_err;
1040:   assign key1_wd = reg_wdata[31:0];
1041: 
1042:   assign key2_we = addr_hit[10] & reg_we & ~wr_err;
1043:   assign key2_wd = reg_wdata[31:0];
1044: 
1045:   assign key3_we = addr_hit[11] & reg_we & ~wr_err;
1046:   assign key3_wd = reg_wdata[31:0];
1047: 
1048:   assign key4_we = addr_hit[12] & reg_we & ~wr_err;
1049:   assign key4_wd = reg_wdata[31:0];
1050: 
1051:   assign key5_we = addr_hit[13] & reg_we & ~wr_err;
1052:   assign key5_wd = reg_wdata[31:0];
1053: 
1054:   assign key6_we = addr_hit[14] & reg_we & ~wr_err;
1055:   assign key6_wd = reg_wdata[31:0];
1056: 
1057:   assign key7_we = addr_hit[15] & reg_we & ~wr_err;
1058:   assign key7_wd = reg_wdata[31:0];
1059: 
1060:   assign digest0_re = addr_hit[16] && reg_re;
1061: 
1062:   assign digest1_re = addr_hit[17] && reg_re;
1063: 
1064:   assign digest2_re = addr_hit[18] && reg_re;
1065: 
1066:   assign digest3_re = addr_hit[19] && reg_re;
1067: 
1068:   assign digest4_re = addr_hit[20] && reg_re;
1069: 
1070:   assign digest5_re = addr_hit[21] && reg_re;
1071: 
1072:   assign digest6_re = addr_hit[22] && reg_re;
1073: 
1074:   assign digest7_re = addr_hit[23] && reg_re;
1075: 
1076: 
1077: 
1078:   // Read data return
1079:   always_comb begin
1080:     reg_rdata_next = '0;
1081:     unique case (1'b1)
1082:       addr_hit[0]: begin
1083:         reg_rdata_next[0] = intr_state_hmac_done_qs;
1084:         reg_rdata_next[1] = intr_state_fifo_empty_qs;
1085:         reg_rdata_next[2] = intr_state_hmac_err_qs;
1086:       end
1087: 
1088:       addr_hit[1]: begin
1089:         reg_rdata_next[0] = intr_enable_hmac_done_qs;
1090:         reg_rdata_next[1] = intr_enable_fifo_empty_qs;
1091:         reg_rdata_next[2] = intr_enable_hmac_err_qs;
1092:       end
1093: 
1094:       addr_hit[2]: begin
1095:         reg_rdata_next[0] = '0;
1096:         reg_rdata_next[1] = '0;
1097:         reg_rdata_next[2] = '0;
1098:       end
1099: 
1100:       addr_hit[3]: begin
1101:         reg_rdata_next[0] = cfg_hmac_en_qs;
1102:         reg_rdata_next[1] = cfg_sha_en_qs;
1103:         reg_rdata_next[2] = cfg_endian_swap_qs;
1104:         reg_rdata_next[3] = cfg_digest_swap_qs;
1105:       end
1106: 
1107:       addr_hit[4]: begin
1108:         reg_rdata_next[0] = '0;
1109:         reg_rdata_next[1] = '0;
1110:       end
1111: 
1112:       addr_hit[5]: begin
1113:         reg_rdata_next[0] = status_fifo_empty_qs;
1114:         reg_rdata_next[1] = status_fifo_full_qs;
1115:         reg_rdata_next[8:4] = status_fifo_depth_qs;
1116:       end
1117: 
1118:       addr_hit[6]: begin
1119:         reg_rdata_next[31:0] = err_code_qs;
1120:       end
1121: 
1122:       addr_hit[7]: begin
1123:         reg_rdata_next[31:0] = '0;
1124:       end
1125: 
1126:       addr_hit[8]: begin
1127:         reg_rdata_next[31:0] = '0;
1128:       end
1129: 
1130:       addr_hit[9]: begin
1131:         reg_rdata_next[31:0] = '0;
1132:       end
1133: 
1134:       addr_hit[10]: begin
1135:         reg_rdata_next[31:0] = '0;
1136:       end
1137: 
1138:       addr_hit[11]: begin
1139:         reg_rdata_next[31:0] = '0;
1140:       end
1141: 
1142:       addr_hit[12]: begin
1143:         reg_rdata_next[31:0] = '0;
1144:       end
1145: 
1146:       addr_hit[13]: begin
1147:         reg_rdata_next[31:0] = '0;
1148:       end
1149: 
1150:       addr_hit[14]: begin
1151:         reg_rdata_next[31:0] = '0;
1152:       end
1153: 
1154:       addr_hit[15]: begin
1155:         reg_rdata_next[31:0] = '0;
1156:       end
1157: 
1158:       addr_hit[16]: begin
1159:         reg_rdata_next[31:0] = digest0_qs;
1160:       end
1161: 
1162:       addr_hit[17]: begin
1163:         reg_rdata_next[31:0] = digest1_qs;
1164:       end
1165: 
1166:       addr_hit[18]: begin
1167:         reg_rdata_next[31:0] = digest2_qs;
1168:       end
1169: 
1170:       addr_hit[19]: begin
1171:         reg_rdata_next[31:0] = digest3_qs;
1172:       end
1173: 
1174:       addr_hit[20]: begin
1175:         reg_rdata_next[31:0] = digest4_qs;
1176:       end
1177: 
1178:       addr_hit[21]: begin
1179:         reg_rdata_next[31:0] = digest5_qs;
1180:       end
1181: 
1182:       addr_hit[22]: begin
1183:         reg_rdata_next[31:0] = digest6_qs;
1184:       end
1185: 
1186:       addr_hit[23]: begin
1187:         reg_rdata_next[31:0] = digest7_qs;
1188:       end
1189: 
1190:       addr_hit[24]: begin
1191:         reg_rdata_next[31:0] = msg_length_lower_qs;
1192:       end
1193: 
1194:       addr_hit[25]: begin
1195:         reg_rdata_next[31:0] = msg_length_upper_qs;
1196:       end
1197: 
1198:       default: begin
1199:         reg_rdata_next = '1;
1200:       end
1201:     endcase
1202:   end
1203: 
1204:   // Assertions for Register Interface
1205:   `ASSERT_PULSE(wePulse, reg_we)
1206:   `ASSERT_PULSE(rePulse, reg_re)
1207: 
1208:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
1209: 
1210:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
1211: 
1212:   // this is formulated as an assumption such that the FPV testbenches do disprove this
1213:   // property by mistake
1214:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
1215: 
1216: endmodule
1217: