../src/lowrisc_ip_rv_timer_0.1/rtl/rv_timer_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package rv_timer_reg_pkg;
8:
9: // Param list
10: parameter int N_HARTS = 1;
11: parameter int N_TIMERS = 1;
12:
13: ////////////////////////////
14: // Typedefs for registers //
15: ////////////////////////////
16: typedef struct packed {
17: logic q;
18: } rv_timer_reg2hw_ctrl_mreg_t;
19:
20: typedef struct packed {
21: struct packed {
22: logic [11:0] q;
23: } prescale;
24: struct packed {
25: logic [7:0] q;
26: } step;
27: } rv_timer_reg2hw_cfg0_reg_t;
28:
29: typedef struct packed {
30: logic [31:0] q;
31: } rv_timer_reg2hw_timer_v_lower0_reg_t;
32:
33: typedef struct packed {
34: logic [31:0] q;
35: } rv_timer_reg2hw_timer_v_upper0_reg_t;
36:
37: typedef struct packed {
38: logic [31:0] q;
39: logic qe;
40: } rv_timer_reg2hw_compare_lower0_0_reg_t;
41:
42: typedef struct packed {
43: logic [31:0] q;
44: logic qe;
45: } rv_timer_reg2hw_compare_upper0_0_reg_t;
46:
47: typedef struct packed {
48: logic q;
49: } rv_timer_reg2hw_intr_enable0_mreg_t;
50:
51: typedef struct packed {
52: logic q;
53: } rv_timer_reg2hw_intr_state0_mreg_t;
54:
55: typedef struct packed {
56: logic q;
57: logic qe;
58: } rv_timer_reg2hw_intr_test0_mreg_t;
59:
60:
61: typedef struct packed {
62: logic [31:0] d;
63: logic de;
64: } rv_timer_hw2reg_timer_v_lower0_reg_t;
65:
66: typedef struct packed {
67: logic [31:0] d;
68: logic de;
69: } rv_timer_hw2reg_timer_v_upper0_reg_t;
70:
71: typedef struct packed {
72: logic d;
73: logic de;
74: } rv_timer_hw2reg_intr_state0_mreg_t;
75:
76:
77: ///////////////////////////////////////
78: // Register to internal design logic //
79: ///////////////////////////////////////
80: typedef struct packed {
81: rv_timer_reg2hw_ctrl_mreg_t [0:0] ctrl; // [154:154]
82: rv_timer_reg2hw_cfg0_reg_t cfg0; // [153:134]
83: rv_timer_reg2hw_timer_v_lower0_reg_t timer_v_lower0; // [133:102]
84: rv_timer_reg2hw_timer_v_upper0_reg_t timer_v_upper0; // [101:70]
85: rv_timer_reg2hw_compare_lower0_0_reg_t compare_lower0_0; // [69:37]
86: rv_timer_reg2hw_compare_upper0_0_reg_t compare_upper0_0; // [36:4]
87: rv_timer_reg2hw_intr_enable0_mreg_t [0:0] intr_enable0; // [3:3]
88: rv_timer_reg2hw_intr_state0_mreg_t [0:0] intr_state0; // [2:2]
89: rv_timer_reg2hw_intr_test0_mreg_t [0:0] intr_test0; // [1:0]
90: } rv_timer_reg2hw_t;
91:
92: ///////////////////////////////////////
93: // Internal design logic to register //
94: ///////////////////////////////////////
95: typedef struct packed {
96: rv_timer_hw2reg_timer_v_lower0_reg_t timer_v_lower0; // [67:36]
97: rv_timer_hw2reg_timer_v_upper0_reg_t timer_v_upper0; // [35:4]
98: rv_timer_hw2reg_intr_state0_mreg_t [0:0] intr_state0; // [3:2]
99: } rv_timer_hw2reg_t;
100:
101: // Register Address
102: parameter logic [8:0] RV_TIMER_CTRL_OFFSET = 9'h 0;
103: parameter logic [8:0] RV_TIMER_CFG0_OFFSET = 9'h 100;
104: parameter logic [8:0] RV_TIMER_TIMER_V_LOWER0_OFFSET = 9'h 104;
105: parameter logic [8:0] RV_TIMER_TIMER_V_UPPER0_OFFSET = 9'h 108;
106: parameter logic [8:0] RV_TIMER_COMPARE_LOWER0_0_OFFSET = 9'h 10c;
107: parameter logic [8:0] RV_TIMER_COMPARE_UPPER0_0_OFFSET = 9'h 110;
108: parameter logic [8:0] RV_TIMER_INTR_ENABLE0_OFFSET = 9'h 114;
109: parameter logic [8:0] RV_TIMER_INTR_STATE0_OFFSET = 9'h 118;
110: parameter logic [8:0] RV_TIMER_INTR_TEST0_OFFSET = 9'h 11c;
111:
112:
113: // Register Index
114: typedef enum int {
115: RV_TIMER_CTRL,
116: RV_TIMER_CFG0,
117: RV_TIMER_TIMER_V_LOWER0,
118: RV_TIMER_TIMER_V_UPPER0,
119: RV_TIMER_COMPARE_LOWER0_0,
120: RV_TIMER_COMPARE_UPPER0_0,
121: RV_TIMER_INTR_ENABLE0,
122: RV_TIMER_INTR_STATE0,
123: RV_TIMER_INTR_TEST0
124: } rv_timer_id_e;
125:
126: // Register width information to check illegal writes
127: parameter logic [3:0] RV_TIMER_PERMIT [9] = '{
128: 4'b 0001, // index[0] RV_TIMER_CTRL
129: 4'b 0111, // index[1] RV_TIMER_CFG0
130: 4'b 1111, // index[2] RV_TIMER_TIMER_V_LOWER0
131: 4'b 1111, // index[3] RV_TIMER_TIMER_V_UPPER0
132: 4'b 1111, // index[4] RV_TIMER_COMPARE_LOWER0_0
133: 4'b 1111, // index[5] RV_TIMER_COMPARE_UPPER0_0
134: 4'b 0001, // index[6] RV_TIMER_INTR_ENABLE0
135: 4'b 0001, // index[7] RV_TIMER_INTR_STATE0
136: 4'b 0001 // index[8] RV_TIMER_INTR_TEST0
137: };
138: endpackage
139:
140: