../src/lowrisc_ip_usbdev_0.1/rtl/usbdev_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module usbdev_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16:
17: // Output port for window
18: output tlul_pkg::tl_h2d_t tl_win_o [1],
19: input tlul_pkg::tl_d2h_t tl_win_i [1],
20:
21: // To HW
22: output usbdev_reg_pkg::usbdev_reg2hw_t reg2hw, // Write
23: input usbdev_reg_pkg::usbdev_hw2reg_t hw2reg, // Read
24:
25: // Config
26: input devmode_i // If 1, explicit error return for unmapped register access
27: );
28:
29: import usbdev_reg_pkg::* ;
30:
31: localparam int AW = 12;
32: localparam int DW = 32;
33: localparam int DBW = DW/8; // Byte Width
34:
35: // register signals
36: logic reg_we;
37: logic reg_re;
38: logic [AW-1:0] reg_addr;
39: logic [DW-1:0] reg_wdata;
40: logic [DBW-1:0] reg_be;
41: logic [DW-1:0] reg_rdata;
42: logic reg_error;
43:
44: logic addrmiss, wr_err;
45:
46: logic [DW-1:0] reg_rdata_next;
47:
48: tlul_pkg::tl_h2d_t tl_reg_h2d;
49: tlul_pkg::tl_d2h_t tl_reg_d2h;
50:
51: tlul_pkg::tl_h2d_t tl_socket_h2d [2];
52: tlul_pkg::tl_d2h_t tl_socket_d2h [2];
53:
54: logic [1:0] reg_steer;
55:
56: // socket_1n connection
57: assign tl_reg_h2d = tl_socket_h2d[1];
58: assign tl_socket_d2h[1] = tl_reg_d2h;
59:
60: assign tl_win_o[0] = tl_socket_h2d[0];
61: assign tl_socket_d2h[0] = tl_win_i[0];
62:
63: // Create Socket_1n
64: tlul_socket_1n #(
65: .N (2),
66: .HReqPass (1'b1),
67: .HRspPass (1'b1),
68: .DReqPass ({2{1'b1}}),
69: .DRspPass ({2{1'b1}}),
70: .HReqDepth (4'h0),
71: .HRspDepth (4'h0),
72: .DReqDepth ({2{4'h0}}),
73: .DRspDepth ({2{4'h0}})
74: ) u_socket (
75: .clk_i,
76: .rst_ni,
77: .tl_h_i (tl_i),
78: .tl_h_o (tl_o),
79: .tl_d_o (tl_socket_h2d),
80: .tl_d_i (tl_socket_d2h),
81: .dev_select (reg_steer)
82: );
83:
84: // Create steering logic
85: always_comb begin
86: reg_steer = 1; // Default set to register
87:
88: // TODO: Can below codes be unique case () inside ?
89: if (tl_i.a_address[AW-1:0] >= 2048) begin
90: // Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
91: reg_steer = 0;
92: end
93: end
94:
95: tlul_adapter_reg #(
96: .RegAw(AW),
97: .RegDw(DW)
98: ) u_reg_if (
99: .clk_i,
100: .rst_ni,
101:
102: .tl_i (tl_reg_h2d),
103: .tl_o (tl_reg_d2h),
104:
105: .we_o (reg_we),
106: .re_o (reg_re),
107: .addr_o (reg_addr),
108: .wdata_o (reg_wdata),
109: .be_o (reg_be),
110: .rdata_i (reg_rdata),
111: .error_i (reg_error)
112: );
113:
114: assign reg_rdata = reg_rdata_next ;
115: assign reg_error = (devmode_i & addrmiss) | wr_err ;
116:
117: // Define SW related signals
118: // Format: __{wd|we|qs}
119: // or _{wd|we|qs} if field == 1 or 0
120: logic intr_state_pkt_received_qs;
121: logic intr_state_pkt_received_wd;
122: logic intr_state_pkt_received_we;
123: logic intr_state_pkt_sent_qs;
124: logic intr_state_pkt_sent_wd;
125: logic intr_state_pkt_sent_we;
126: logic intr_state_disconnected_qs;
127: logic intr_state_disconnected_wd;
128: logic intr_state_disconnected_we;
129: logic intr_state_host_lost_qs;
130: logic intr_state_host_lost_wd;
131: logic intr_state_host_lost_we;
132: logic intr_state_link_reset_qs;
133: logic intr_state_link_reset_wd;
134: logic intr_state_link_reset_we;
135: logic intr_state_link_suspend_qs;
136: logic intr_state_link_suspend_wd;
137: logic intr_state_link_suspend_we;
138: logic intr_state_link_resume_qs;
139: logic intr_state_link_resume_wd;
140: logic intr_state_link_resume_we;
141: logic intr_state_av_empty_qs;
142: logic intr_state_av_empty_wd;
143: logic intr_state_av_empty_we;
144: logic intr_state_rx_full_qs;
145: logic intr_state_rx_full_wd;
146: logic intr_state_rx_full_we;
147: logic intr_state_av_overflow_qs;
148: logic intr_state_av_overflow_wd;
149: logic intr_state_av_overflow_we;
150: logic intr_state_link_in_err_qs;
151: logic intr_state_link_in_err_wd;
152: logic intr_state_link_in_err_we;
153: logic intr_state_rx_crc_err_qs;
154: logic intr_state_rx_crc_err_wd;
155: logic intr_state_rx_crc_err_we;
156: logic intr_state_rx_pid_err_qs;
157: logic intr_state_rx_pid_err_wd;
158: logic intr_state_rx_pid_err_we;
159: logic intr_state_rx_bitstuff_err_qs;
160: logic intr_state_rx_bitstuff_err_wd;
161: logic intr_state_rx_bitstuff_err_we;
162: logic intr_state_frame_qs;
163: logic intr_state_frame_wd;
164: logic intr_state_frame_we;
165: logic intr_state_connected_qs;
166: logic intr_state_connected_wd;
167: logic intr_state_connected_we;
168: logic intr_enable_pkt_received_qs;
169: logic intr_enable_pkt_received_wd;
170: logic intr_enable_pkt_received_we;
171: logic intr_enable_pkt_sent_qs;
172: logic intr_enable_pkt_sent_wd;
173: logic intr_enable_pkt_sent_we;
174: logic intr_enable_disconnected_qs;
175: logic intr_enable_disconnected_wd;
176: logic intr_enable_disconnected_we;
177: logic intr_enable_host_lost_qs;
178: logic intr_enable_host_lost_wd;
179: logic intr_enable_host_lost_we;
180: logic intr_enable_link_reset_qs;
181: logic intr_enable_link_reset_wd;
182: logic intr_enable_link_reset_we;
183: logic intr_enable_link_suspend_qs;
184: logic intr_enable_link_suspend_wd;
185: logic intr_enable_link_suspend_we;
186: logic intr_enable_link_resume_qs;
187: logic intr_enable_link_resume_wd;
188: logic intr_enable_link_resume_we;
189: logic intr_enable_av_empty_qs;
190: logic intr_enable_av_empty_wd;
191: logic intr_enable_av_empty_we;
192: logic intr_enable_rx_full_qs;
193: logic intr_enable_rx_full_wd;
194: logic intr_enable_rx_full_we;
195: logic intr_enable_av_overflow_qs;
196: logic intr_enable_av_overflow_wd;
197: logic intr_enable_av_overflow_we;
198: logic intr_enable_link_in_err_qs;
199: logic intr_enable_link_in_err_wd;
200: logic intr_enable_link_in_err_we;
201: logic intr_enable_rx_crc_err_qs;
202: logic intr_enable_rx_crc_err_wd;
203: logic intr_enable_rx_crc_err_we;
204: logic intr_enable_rx_pid_err_qs;
205: logic intr_enable_rx_pid_err_wd;
206: logic intr_enable_rx_pid_err_we;
207: logic intr_enable_rx_bitstuff_err_qs;
208: logic intr_enable_rx_bitstuff_err_wd;
209: logic intr_enable_rx_bitstuff_err_we;
210: logic intr_enable_frame_qs;
211: logic intr_enable_frame_wd;
212: logic intr_enable_frame_we;
213: logic intr_enable_connected_qs;
214: logic intr_enable_connected_wd;
215: logic intr_enable_connected_we;
216: logic intr_test_pkt_received_wd;
217: logic intr_test_pkt_received_we;
218: logic intr_test_pkt_sent_wd;
219: logic intr_test_pkt_sent_we;
220: logic intr_test_disconnected_wd;
221: logic intr_test_disconnected_we;
222: logic intr_test_host_lost_wd;
223: logic intr_test_host_lost_we;
224: logic intr_test_link_reset_wd;
225: logic intr_test_link_reset_we;
226: logic intr_test_link_suspend_wd;
227: logic intr_test_link_suspend_we;
228: logic intr_test_link_resume_wd;
229: logic intr_test_link_resume_we;
230: logic intr_test_av_empty_wd;
231: logic intr_test_av_empty_we;
232: logic intr_test_rx_full_wd;
233: logic intr_test_rx_full_we;
234: logic intr_test_av_overflow_wd;
235: logic intr_test_av_overflow_we;
236: logic intr_test_link_in_err_wd;
237: logic intr_test_link_in_err_we;
238: logic intr_test_rx_crc_err_wd;
239: logic intr_test_rx_crc_err_we;
240: logic intr_test_rx_pid_err_wd;
241: logic intr_test_rx_pid_err_we;
242: logic intr_test_rx_bitstuff_err_wd;
243: logic intr_test_rx_bitstuff_err_we;
244: logic intr_test_frame_wd;
245: logic intr_test_frame_we;
246: logic intr_test_connected_wd;
247: logic intr_test_connected_we;
248: logic usbctrl_enable_qs;
249: logic usbctrl_enable_wd;
250: logic usbctrl_enable_we;
251: logic [6:0] usbctrl_device_address_qs;
252: logic [6:0] usbctrl_device_address_wd;
253: logic usbctrl_device_address_we;
254: logic [10:0] usbstat_frame_qs;
255: logic usbstat_frame_re;
256: logic usbstat_host_lost_qs;
257: logic usbstat_host_lost_re;
258: logic [2:0] usbstat_link_state_qs;
259: logic usbstat_link_state_re;
260: logic usbstat_sense_qs;
261: logic usbstat_sense_re;
262: logic [2:0] usbstat_av_depth_qs;
263: logic usbstat_av_depth_re;
264: logic usbstat_av_full_qs;
265: logic usbstat_av_full_re;
266: logic [2:0] usbstat_rx_depth_qs;
267: logic usbstat_rx_depth_re;
268: logic usbstat_rx_empty_qs;
269: logic usbstat_rx_empty_re;
270: logic [4:0] avbuffer_wd;
271: logic avbuffer_we;
272: logic [4:0] rxfifo_buffer_qs;
273: logic rxfifo_buffer_re;
274: logic [6:0] rxfifo_size_qs;
275: logic rxfifo_size_re;
276: logic rxfifo_setup_qs;
277: logic rxfifo_setup_re;
278: logic [3:0] rxfifo_ep_qs;
279: logic rxfifo_ep_re;
280: logic rxenable_setup_setup0_qs;
281: logic rxenable_setup_setup0_wd;
282: logic rxenable_setup_setup0_we;
283: logic rxenable_setup_setup1_qs;
284: logic rxenable_setup_setup1_wd;
285: logic rxenable_setup_setup1_we;
286: logic rxenable_setup_setup2_qs;
287: logic rxenable_setup_setup2_wd;
288: logic rxenable_setup_setup2_we;
289: logic rxenable_setup_setup3_qs;
290: logic rxenable_setup_setup3_wd;
291: logic rxenable_setup_setup3_we;
292: logic rxenable_setup_setup4_qs;
293: logic rxenable_setup_setup4_wd;
294: logic rxenable_setup_setup4_we;
295: logic rxenable_setup_setup5_qs;
296: logic rxenable_setup_setup5_wd;
297: logic rxenable_setup_setup5_we;
298: logic rxenable_setup_setup6_qs;
299: logic rxenable_setup_setup6_wd;
300: logic rxenable_setup_setup6_we;
301: logic rxenable_setup_setup7_qs;
302: logic rxenable_setup_setup7_wd;
303: logic rxenable_setup_setup7_we;
304: logic rxenable_setup_setup8_qs;
305: logic rxenable_setup_setup8_wd;
306: logic rxenable_setup_setup8_we;
307: logic rxenable_setup_setup9_qs;
308: logic rxenable_setup_setup9_wd;
309: logic rxenable_setup_setup9_we;
310: logic rxenable_setup_setup10_qs;
311: logic rxenable_setup_setup10_wd;
312: logic rxenable_setup_setup10_we;
313: logic rxenable_setup_setup11_qs;
314: logic rxenable_setup_setup11_wd;
315: logic rxenable_setup_setup11_we;
316: logic rxenable_out_out0_qs;
317: logic rxenable_out_out0_wd;
318: logic rxenable_out_out0_we;
319: logic rxenable_out_out1_qs;
320: logic rxenable_out_out1_wd;
321: logic rxenable_out_out1_we;
322: logic rxenable_out_out2_qs;
323: logic rxenable_out_out2_wd;
324: logic rxenable_out_out2_we;
325: logic rxenable_out_out3_qs;
326: logic rxenable_out_out3_wd;
327: logic rxenable_out_out3_we;
328: logic rxenable_out_out4_qs;
329: logic rxenable_out_out4_wd;
330: logic rxenable_out_out4_we;
331: logic rxenable_out_out5_qs;
332: logic rxenable_out_out5_wd;
333: logic rxenable_out_out5_we;
334: logic rxenable_out_out6_qs;
335: logic rxenable_out_out6_wd;
336: logic rxenable_out_out6_we;
337: logic rxenable_out_out7_qs;
338: logic rxenable_out_out7_wd;
339: logic rxenable_out_out7_we;
340: logic rxenable_out_out8_qs;
341: logic rxenable_out_out8_wd;
342: logic rxenable_out_out8_we;
343: logic rxenable_out_out9_qs;
344: logic rxenable_out_out9_wd;
345: logic rxenable_out_out9_we;
346: logic rxenable_out_out10_qs;
347: logic rxenable_out_out10_wd;
348: logic rxenable_out_out10_we;
349: logic rxenable_out_out11_qs;
350: logic rxenable_out_out11_wd;
351: logic rxenable_out_out11_we;
352: logic in_sent_sent0_qs;
353: logic in_sent_sent0_wd;
354: logic in_sent_sent0_we;
355: logic in_sent_sent1_qs;
356: logic in_sent_sent1_wd;
357: logic in_sent_sent1_we;
358: logic in_sent_sent2_qs;
359: logic in_sent_sent2_wd;
360: logic in_sent_sent2_we;
361: logic in_sent_sent3_qs;
362: logic in_sent_sent3_wd;
363: logic in_sent_sent3_we;
364: logic in_sent_sent4_qs;
365: logic in_sent_sent4_wd;
366: logic in_sent_sent4_we;
367: logic in_sent_sent5_qs;
368: logic in_sent_sent5_wd;
369: logic in_sent_sent5_we;
370: logic in_sent_sent6_qs;
371: logic in_sent_sent6_wd;
372: logic in_sent_sent6_we;
373: logic in_sent_sent7_qs;
374: logic in_sent_sent7_wd;
375: logic in_sent_sent7_we;
376: logic in_sent_sent8_qs;
377: logic in_sent_sent8_wd;
378: logic in_sent_sent8_we;
379: logic in_sent_sent9_qs;
380: logic in_sent_sent9_wd;
381: logic in_sent_sent9_we;
382: logic in_sent_sent10_qs;
383: logic in_sent_sent10_wd;
384: logic in_sent_sent10_we;
385: logic in_sent_sent11_qs;
386: logic in_sent_sent11_wd;
387: logic in_sent_sent11_we;
388: logic stall_stall0_qs;
389: logic stall_stall0_wd;
390: logic stall_stall0_we;
391: logic stall_stall1_qs;
392: logic stall_stall1_wd;
393: logic stall_stall1_we;
394: logic stall_stall2_qs;
395: logic stall_stall2_wd;
396: logic stall_stall2_we;
397: logic stall_stall3_qs;
398: logic stall_stall3_wd;
399: logic stall_stall3_we;
400: logic stall_stall4_qs;
401: logic stall_stall4_wd;
402: logic stall_stall4_we;
403: logic stall_stall5_qs;
404: logic stall_stall5_wd;
405: logic stall_stall5_we;
406: logic stall_stall6_qs;
407: logic stall_stall6_wd;
408: logic stall_stall6_we;
409: logic stall_stall7_qs;
410: logic stall_stall7_wd;
411: logic stall_stall7_we;
412: logic stall_stall8_qs;
413: logic stall_stall8_wd;
414: logic stall_stall8_we;
415: logic stall_stall9_qs;
416: logic stall_stall9_wd;
417: logic stall_stall9_we;
418: logic stall_stall10_qs;
419: logic stall_stall10_wd;
420: logic stall_stall10_we;
421: logic stall_stall11_qs;
422: logic stall_stall11_wd;
423: logic stall_stall11_we;
424: logic [4:0] configin0_buffer0_qs;
425: logic [4:0] configin0_buffer0_wd;
426: logic configin0_buffer0_we;
427: logic [6:0] configin0_size0_qs;
428: logic [6:0] configin0_size0_wd;
429: logic configin0_size0_we;
430: logic configin0_pend0_qs;
431: logic configin0_pend0_wd;
432: logic configin0_pend0_we;
433: logic configin0_rdy0_qs;
434: logic configin0_rdy0_wd;
435: logic configin0_rdy0_we;
436: logic [4:0] configin1_buffer1_qs;
437: logic [4:0] configin1_buffer1_wd;
438: logic configin1_buffer1_we;
439: logic [6:0] configin1_size1_qs;
440: logic [6:0] configin1_size1_wd;
441: logic configin1_size1_we;
442: logic configin1_pend1_qs;
443: logic configin1_pend1_wd;
444: logic configin1_pend1_we;
445: logic configin1_rdy1_qs;
446: logic configin1_rdy1_wd;
447: logic configin1_rdy1_we;
448: logic [4:0] configin2_buffer2_qs;
449: logic [4:0] configin2_buffer2_wd;
450: logic configin2_buffer2_we;
451: logic [6:0] configin2_size2_qs;
452: logic [6:0] configin2_size2_wd;
453: logic configin2_size2_we;
454: logic configin2_pend2_qs;
455: logic configin2_pend2_wd;
456: logic configin2_pend2_we;
457: logic configin2_rdy2_qs;
458: logic configin2_rdy2_wd;
459: logic configin2_rdy2_we;
460: logic [4:0] configin3_buffer3_qs;
461: logic [4:0] configin3_buffer3_wd;
462: logic configin3_buffer3_we;
463: logic [6:0] configin3_size3_qs;
464: logic [6:0] configin3_size3_wd;
465: logic configin3_size3_we;
466: logic configin3_pend3_qs;
467: logic configin3_pend3_wd;
468: logic configin3_pend3_we;
469: logic configin3_rdy3_qs;
470: logic configin3_rdy3_wd;
471: logic configin3_rdy3_we;
472: logic [4:0] configin4_buffer4_qs;
473: logic [4:0] configin4_buffer4_wd;
474: logic configin4_buffer4_we;
475: logic [6:0] configin4_size4_qs;
476: logic [6:0] configin4_size4_wd;
477: logic configin4_size4_we;
478: logic configin4_pend4_qs;
479: logic configin4_pend4_wd;
480: logic configin4_pend4_we;
481: logic configin4_rdy4_qs;
482: logic configin4_rdy4_wd;
483: logic configin4_rdy4_we;
484: logic [4:0] configin5_buffer5_qs;
485: logic [4:0] configin5_buffer5_wd;
486: logic configin5_buffer5_we;
487: logic [6:0] configin5_size5_qs;
488: logic [6:0] configin5_size5_wd;
489: logic configin5_size5_we;
490: logic configin5_pend5_qs;
491: logic configin5_pend5_wd;
492: logic configin5_pend5_we;
493: logic configin5_rdy5_qs;
494: logic configin5_rdy5_wd;
495: logic configin5_rdy5_we;
496: logic [4:0] configin6_buffer6_qs;
497: logic [4:0] configin6_buffer6_wd;
498: logic configin6_buffer6_we;
499: logic [6:0] configin6_size6_qs;
500: logic [6:0] configin6_size6_wd;
501: logic configin6_size6_we;
502: logic configin6_pend6_qs;
503: logic configin6_pend6_wd;
504: logic configin6_pend6_we;
505: logic configin6_rdy6_qs;
506: logic configin6_rdy6_wd;
507: logic configin6_rdy6_we;
508: logic [4:0] configin7_buffer7_qs;
509: logic [4:0] configin7_buffer7_wd;
510: logic configin7_buffer7_we;
511: logic [6:0] configin7_size7_qs;
512: logic [6:0] configin7_size7_wd;
513: logic configin7_size7_we;
514: logic configin7_pend7_qs;
515: logic configin7_pend7_wd;
516: logic configin7_pend7_we;
517: logic configin7_rdy7_qs;
518: logic configin7_rdy7_wd;
519: logic configin7_rdy7_we;
520: logic [4:0] configin8_buffer8_qs;
521: logic [4:0] configin8_buffer8_wd;
522: logic configin8_buffer8_we;
523: logic [6:0] configin8_size8_qs;
524: logic [6:0] configin8_size8_wd;
525: logic configin8_size8_we;
526: logic configin8_pend8_qs;
527: logic configin8_pend8_wd;
528: logic configin8_pend8_we;
529: logic configin8_rdy8_qs;
530: logic configin8_rdy8_wd;
531: logic configin8_rdy8_we;
532: logic [4:0] configin9_buffer9_qs;
533: logic [4:0] configin9_buffer9_wd;
534: logic configin9_buffer9_we;
535: logic [6:0] configin9_size9_qs;
536: logic [6:0] configin9_size9_wd;
537: logic configin9_size9_we;
538: logic configin9_pend9_qs;
539: logic configin9_pend9_wd;
540: logic configin9_pend9_we;
541: logic configin9_rdy9_qs;
542: logic configin9_rdy9_wd;
543: logic configin9_rdy9_we;
544: logic [4:0] configin10_buffer10_qs;
545: logic [4:0] configin10_buffer10_wd;
546: logic configin10_buffer10_we;
547: logic [6:0] configin10_size10_qs;
548: logic [6:0] configin10_size10_wd;
549: logic configin10_size10_we;
550: logic configin10_pend10_qs;
551: logic configin10_pend10_wd;
552: logic configin10_pend10_we;
553: logic configin10_rdy10_qs;
554: logic configin10_rdy10_wd;
555: logic configin10_rdy10_we;
556: logic [4:0] configin11_buffer11_qs;
557: logic [4:0] configin11_buffer11_wd;
558: logic configin11_buffer11_we;
559: logic [6:0] configin11_size11_qs;
560: logic [6:0] configin11_size11_wd;
561: logic configin11_size11_we;
562: logic configin11_pend11_qs;
563: logic configin11_pend11_wd;
564: logic configin11_pend11_we;
565: logic configin11_rdy11_qs;
566: logic configin11_rdy11_wd;
567: logic configin11_rdy11_we;
568: logic iso_iso0_qs;
569: logic iso_iso0_wd;
570: logic iso_iso0_we;
571: logic iso_iso1_qs;
572: logic iso_iso1_wd;
573: logic iso_iso1_we;
574: logic iso_iso2_qs;
575: logic iso_iso2_wd;
576: logic iso_iso2_we;
577: logic iso_iso3_qs;
578: logic iso_iso3_wd;
579: logic iso_iso3_we;
580: logic iso_iso4_qs;
581: logic iso_iso4_wd;
582: logic iso_iso4_we;
583: logic iso_iso5_qs;
584: logic iso_iso5_wd;
585: logic iso_iso5_we;
586: logic iso_iso6_qs;
587: logic iso_iso6_wd;
588: logic iso_iso6_we;
589: logic iso_iso7_qs;
590: logic iso_iso7_wd;
591: logic iso_iso7_we;
592: logic iso_iso8_qs;
593: logic iso_iso8_wd;
594: logic iso_iso8_we;
595: logic iso_iso9_qs;
596: logic iso_iso9_wd;
597: logic iso_iso9_we;
598: logic iso_iso10_qs;
599: logic iso_iso10_wd;
600: logic iso_iso10_we;
601: logic iso_iso11_qs;
602: logic iso_iso11_wd;
603: logic iso_iso11_we;
604: logic data_toggle_clear_clear0_wd;
605: logic data_toggle_clear_clear0_we;
606: logic data_toggle_clear_clear1_wd;
607: logic data_toggle_clear_clear1_we;
608: logic data_toggle_clear_clear2_wd;
609: logic data_toggle_clear_clear2_we;
610: logic data_toggle_clear_clear3_wd;
611: logic data_toggle_clear_clear3_we;
612: logic data_toggle_clear_clear4_wd;
613: logic data_toggle_clear_clear4_we;
614: logic data_toggle_clear_clear5_wd;
615: logic data_toggle_clear_clear5_we;
616: logic data_toggle_clear_clear6_wd;
617: logic data_toggle_clear_clear6_we;
618: logic data_toggle_clear_clear7_wd;
619: logic data_toggle_clear_clear7_we;
620: logic data_toggle_clear_clear8_wd;
621: logic data_toggle_clear_clear8_we;
622: logic data_toggle_clear_clear9_wd;
623: logic data_toggle_clear_clear9_we;
624: logic data_toggle_clear_clear10_wd;
625: logic data_toggle_clear_clear10_we;
626: logic data_toggle_clear_clear11_wd;
627: logic data_toggle_clear_clear11_we;
628: logic phy_config_rx_differential_mode_qs;
629: logic phy_config_rx_differential_mode_wd;
630: logic phy_config_rx_differential_mode_we;
631: logic phy_config_tx_differential_mode_qs;
632: logic phy_config_tx_differential_mode_wd;
633: logic phy_config_tx_differential_mode_we;
634: logic phy_config_eop_single_bit_qs;
635: logic phy_config_eop_single_bit_wd;
636: logic phy_config_eop_single_bit_we;
637: logic phy_config_override_pwr_sense_en_qs;
638: logic phy_config_override_pwr_sense_en_wd;
639: logic phy_config_override_pwr_sense_en_we;
640: logic phy_config_override_pwr_sense_val_qs;
641: logic phy_config_override_pwr_sense_val_wd;
642: logic phy_config_override_pwr_sense_val_we;
643: logic phy_config_pinflip_qs;
644: logic phy_config_pinflip_wd;
645: logic phy_config_pinflip_we;
646: logic phy_config_usb_ref_disable_qs;
647: logic phy_config_usb_ref_disable_wd;
648: logic phy_config_usb_ref_disable_we;
649:
650: // Register instances
651: // R[intr_state]: V(False)
652:
653: // F[pkt_received]: 0:0
654: prim_subreg #(
655: .DW (1),
656: .SWACCESS("W1C"),
657: .RESVAL (1'h0)
658: ) u_intr_state_pkt_received (
659: .clk_i (clk_i ),
660: .rst_ni (rst_ni ),
661:
662: // from register interface
663: .we (intr_state_pkt_received_we),
664: .wd (intr_state_pkt_received_wd),
665:
666: // from internal hardware
667: .de (hw2reg.intr_state.pkt_received.de),
668: .d (hw2reg.intr_state.pkt_received.d ),
669:
670: // to internal hardware
671: .qe (),
672: .q (reg2hw.intr_state.pkt_received.q ),
673:
674: // to register interface (read)
675: .qs (intr_state_pkt_received_qs)
676: );
677:
678:
679: // F[pkt_sent]: 1:1
680: prim_subreg #(
681: .DW (1),
682: .SWACCESS("W1C"),
683: .RESVAL (1'h0)
684: ) u_intr_state_pkt_sent (
685: .clk_i (clk_i ),
686: .rst_ni (rst_ni ),
687:
688: // from register interface
689: .we (intr_state_pkt_sent_we),
690: .wd (intr_state_pkt_sent_wd),
691:
692: // from internal hardware
693: .de (hw2reg.intr_state.pkt_sent.de),
694: .d (hw2reg.intr_state.pkt_sent.d ),
695:
696: // to internal hardware
697: .qe (),
698: .q (reg2hw.intr_state.pkt_sent.q ),
699:
700: // to register interface (read)
701: .qs (intr_state_pkt_sent_qs)
702: );
703:
704:
705: // F[disconnected]: 2:2
706: prim_subreg #(
707: .DW (1),
708: .SWACCESS("W1C"),
709: .RESVAL (1'h0)
710: ) u_intr_state_disconnected (
711: .clk_i (clk_i ),
712: .rst_ni (rst_ni ),
713:
714: // from register interface
715: .we (intr_state_disconnected_we),
716: .wd (intr_state_disconnected_wd),
717:
718: // from internal hardware
719: .de (hw2reg.intr_state.disconnected.de),
720: .d (hw2reg.intr_state.disconnected.d ),
721:
722: // to internal hardware
723: .qe (),
724: .q (reg2hw.intr_state.disconnected.q ),
725:
726: // to register interface (read)
727: .qs (intr_state_disconnected_qs)
728: );
729:
730:
731: // F[host_lost]: 3:3
732: prim_subreg #(
733: .DW (1),
734: .SWACCESS("W1C"),
735: .RESVAL (1'h0)
736: ) u_intr_state_host_lost (
737: .clk_i (clk_i ),
738: .rst_ni (rst_ni ),
739:
740: // from register interface
741: .we (intr_state_host_lost_we),
742: .wd (intr_state_host_lost_wd),
743:
744: // from internal hardware
745: .de (hw2reg.intr_state.host_lost.de),
746: .d (hw2reg.intr_state.host_lost.d ),
747:
748: // to internal hardware
749: .qe (),
750: .q (reg2hw.intr_state.host_lost.q ),
751:
752: // to register interface (read)
753: .qs (intr_state_host_lost_qs)
754: );
755:
756:
757: // F[link_reset]: 4:4
758: prim_subreg #(
759: .DW (1),
760: .SWACCESS("W1C"),
761: .RESVAL (1'h0)
762: ) u_intr_state_link_reset (
763: .clk_i (clk_i ),
764: .rst_ni (rst_ni ),
765:
766: // from register interface
767: .we (intr_state_link_reset_we),
768: .wd (intr_state_link_reset_wd),
769:
770: // from internal hardware
771: .de (hw2reg.intr_state.link_reset.de),
772: .d (hw2reg.intr_state.link_reset.d ),
773:
774: // to internal hardware
775: .qe (),
776: .q (reg2hw.intr_state.link_reset.q ),
777:
778: // to register interface (read)
779: .qs (intr_state_link_reset_qs)
780: );
781:
782:
783: // F[link_suspend]: 5:5
784: prim_subreg #(
785: .DW (1),
786: .SWACCESS("W1C"),
787: .RESVAL (1'h0)
788: ) u_intr_state_link_suspend (
789: .clk_i (clk_i ),
790: .rst_ni (rst_ni ),
791:
792: // from register interface
793: .we (intr_state_link_suspend_we),
794: .wd (intr_state_link_suspend_wd),
795:
796: // from internal hardware
797: .de (hw2reg.intr_state.link_suspend.de),
798: .d (hw2reg.intr_state.link_suspend.d ),
799:
800: // to internal hardware
801: .qe (),
802: .q (reg2hw.intr_state.link_suspend.q ),
803:
804: // to register interface (read)
805: .qs (intr_state_link_suspend_qs)
806: );
807:
808:
809: // F[link_resume]: 6:6
810: prim_subreg #(
811: .DW (1),
812: .SWACCESS("W1C"),
813: .RESVAL (1'h0)
814: ) u_intr_state_link_resume (
815: .clk_i (clk_i ),
816: .rst_ni (rst_ni ),
817:
818: // from register interface
819: .we (intr_state_link_resume_we),
820: .wd (intr_state_link_resume_wd),
821:
822: // from internal hardware
823: .de (hw2reg.intr_state.link_resume.de),
824: .d (hw2reg.intr_state.link_resume.d ),
825:
826: // to internal hardware
827: .qe (),
828: .q (reg2hw.intr_state.link_resume.q ),
829:
830: // to register interface (read)
831: .qs (intr_state_link_resume_qs)
832: );
833:
834:
835: // F[av_empty]: 7:7
836: prim_subreg #(
837: .DW (1),
838: .SWACCESS("W1C"),
839: .RESVAL (1'h0)
840: ) u_intr_state_av_empty (
841: .clk_i (clk_i ),
842: .rst_ni (rst_ni ),
843:
844: // from register interface
845: .we (intr_state_av_empty_we),
846: .wd (intr_state_av_empty_wd),
847:
848: // from internal hardware
849: .de (hw2reg.intr_state.av_empty.de),
850: .d (hw2reg.intr_state.av_empty.d ),
851:
852: // to internal hardware
853: .qe (),
854: .q (reg2hw.intr_state.av_empty.q ),
855:
856: // to register interface (read)
857: .qs (intr_state_av_empty_qs)
858: );
859:
860:
861: // F[rx_full]: 8:8
862: prim_subreg #(
863: .DW (1),
864: .SWACCESS("W1C"),
865: .RESVAL (1'h0)
866: ) u_intr_state_rx_full (
867: .clk_i (clk_i ),
868: .rst_ni (rst_ni ),
869:
870: // from register interface
871: .we (intr_state_rx_full_we),
872: .wd (intr_state_rx_full_wd),
873:
874: // from internal hardware
875: .de (hw2reg.intr_state.rx_full.de),
876: .d (hw2reg.intr_state.rx_full.d ),
877:
878: // to internal hardware
879: .qe (),
880: .q (reg2hw.intr_state.rx_full.q ),
881:
882: // to register interface (read)
883: .qs (intr_state_rx_full_qs)
884: );
885:
886:
887: // F[av_overflow]: 9:9
888: prim_subreg #(
889: .DW (1),
890: .SWACCESS("W1C"),
891: .RESVAL (1'h0)
892: ) u_intr_state_av_overflow (
893: .clk_i (clk_i ),
894: .rst_ni (rst_ni ),
895:
896: // from register interface
897: .we (intr_state_av_overflow_we),
898: .wd (intr_state_av_overflow_wd),
899:
900: // from internal hardware
901: .de (hw2reg.intr_state.av_overflow.de),
902: .d (hw2reg.intr_state.av_overflow.d ),
903:
904: // to internal hardware
905: .qe (),
906: .q (reg2hw.intr_state.av_overflow.q ),
907:
908: // to register interface (read)
909: .qs (intr_state_av_overflow_qs)
910: );
911:
912:
913: // F[link_in_err]: 10:10
914: prim_subreg #(
915: .DW (1),
916: .SWACCESS("W1C"),
917: .RESVAL (1'h0)
918: ) u_intr_state_link_in_err (
919: .clk_i (clk_i ),
920: .rst_ni (rst_ni ),
921:
922: // from register interface
923: .we (intr_state_link_in_err_we),
924: .wd (intr_state_link_in_err_wd),
925:
926: // from internal hardware
927: .de (hw2reg.intr_state.link_in_err.de),
928: .d (hw2reg.intr_state.link_in_err.d ),
929:
930: // to internal hardware
931: .qe (),
932: .q (reg2hw.intr_state.link_in_err.q ),
933:
934: // to register interface (read)
935: .qs (intr_state_link_in_err_qs)
936: );
937:
938:
939: // F[rx_crc_err]: 11:11
940: prim_subreg #(
941: .DW (1),
942: .SWACCESS("W1C"),
943: .RESVAL (1'h0)
944: ) u_intr_state_rx_crc_err (
945: .clk_i (clk_i ),
946: .rst_ni (rst_ni ),
947:
948: // from register interface
949: .we (intr_state_rx_crc_err_we),
950: .wd (intr_state_rx_crc_err_wd),
951:
952: // from internal hardware
953: .de (hw2reg.intr_state.rx_crc_err.de),
954: .d (hw2reg.intr_state.rx_crc_err.d ),
955:
956: // to internal hardware
957: .qe (),
958: .q (reg2hw.intr_state.rx_crc_err.q ),
959:
960: // to register interface (read)
961: .qs (intr_state_rx_crc_err_qs)
962: );
963:
964:
965: // F[rx_pid_err]: 12:12
966: prim_subreg #(
967: .DW (1),
968: .SWACCESS("W1C"),
969: .RESVAL (1'h0)
970: ) u_intr_state_rx_pid_err (
971: .clk_i (clk_i ),
972: .rst_ni (rst_ni ),
973:
974: // from register interface
975: .we (intr_state_rx_pid_err_we),
976: .wd (intr_state_rx_pid_err_wd),
977:
978: // from internal hardware
979: .de (hw2reg.intr_state.rx_pid_err.de),
980: .d (hw2reg.intr_state.rx_pid_err.d ),
981:
982: // to internal hardware
983: .qe (),
984: .q (reg2hw.intr_state.rx_pid_err.q ),
985:
986: // to register interface (read)
987: .qs (intr_state_rx_pid_err_qs)
988: );
989:
990:
991: // F[rx_bitstuff_err]: 13:13
992: prim_subreg #(
993: .DW (1),
994: .SWACCESS("W1C"),
995: .RESVAL (1'h0)
996: ) u_intr_state_rx_bitstuff_err (
997: .clk_i (clk_i ),
998: .rst_ni (rst_ni ),
999:
1000: // from register interface
1001: .we (intr_state_rx_bitstuff_err_we),
1002: .wd (intr_state_rx_bitstuff_err_wd),
1003:
1004: // from internal hardware
1005: .de (hw2reg.intr_state.rx_bitstuff_err.de),
1006: .d (hw2reg.intr_state.rx_bitstuff_err.d ),
1007:
1008: // to internal hardware
1009: .qe (),
1010: .q (reg2hw.intr_state.rx_bitstuff_err.q ),
1011:
1012: // to register interface (read)
1013: .qs (intr_state_rx_bitstuff_err_qs)
1014: );
1015:
1016:
1017: // F[frame]: 14:14
1018: prim_subreg #(
1019: .DW (1),
1020: .SWACCESS("W1C"),
1021: .RESVAL (1'h0)
1022: ) u_intr_state_frame (
1023: .clk_i (clk_i ),
1024: .rst_ni (rst_ni ),
1025:
1026: // from register interface
1027: .we (intr_state_frame_we),
1028: .wd (intr_state_frame_wd),
1029:
1030: // from internal hardware
1031: .de (hw2reg.intr_state.frame.de),
1032: .d (hw2reg.intr_state.frame.d ),
1033:
1034: // to internal hardware
1035: .qe (),
1036: .q (reg2hw.intr_state.frame.q ),
1037:
1038: // to register interface (read)
1039: .qs (intr_state_frame_qs)
1040: );
1041:
1042:
1043: // F[connected]: 15:15
1044: prim_subreg #(
1045: .DW (1),
1046: .SWACCESS("W1C"),
1047: .RESVAL (1'h0)
1048: ) u_intr_state_connected (
1049: .clk_i (clk_i ),
1050: .rst_ni (rst_ni ),
1051:
1052: // from register interface
1053: .we (intr_state_connected_we),
1054: .wd (intr_state_connected_wd),
1055:
1056: // from internal hardware
1057: .de (hw2reg.intr_state.connected.de),
1058: .d (hw2reg.intr_state.connected.d ),
1059:
1060: // to internal hardware
1061: .qe (),
1062: .q (reg2hw.intr_state.connected.q ),
1063:
1064: // to register interface (read)
1065: .qs (intr_state_connected_qs)
1066: );
1067:
1068:
1069: // R[intr_enable]: V(False)
1070:
1071: // F[pkt_received]: 0:0
1072: prim_subreg #(
1073: .DW (1),
1074: .SWACCESS("RW"),
1075: .RESVAL (1'h0)
1076: ) u_intr_enable_pkt_received (
1077: .clk_i (clk_i ),
1078: .rst_ni (rst_ni ),
1079:
1080: // from register interface
1081: .we (intr_enable_pkt_received_we),
1082: .wd (intr_enable_pkt_received_wd),
1083:
1084: // from internal hardware
1085: .de (1'b0),
1086: .d ('0 ),
1087:
1088: // to internal hardware
1089: .qe (),
1090: .q (reg2hw.intr_enable.pkt_received.q ),
1091:
1092: // to register interface (read)
1093: .qs (intr_enable_pkt_received_qs)
1094: );
1095:
1096:
1097: // F[pkt_sent]: 1:1
1098: prim_subreg #(
1099: .DW (1),
1100: .SWACCESS("RW"),
1101: .RESVAL (1'h0)
1102: ) u_intr_enable_pkt_sent (
1103: .clk_i (clk_i ),
1104: .rst_ni (rst_ni ),
1105:
1106: // from register interface
1107: .we (intr_enable_pkt_sent_we),
1108: .wd (intr_enable_pkt_sent_wd),
1109:
1110: // from internal hardware
1111: .de (1'b0),
1112: .d ('0 ),
1113:
1114: // to internal hardware
1115: .qe (),
1116: .q (reg2hw.intr_enable.pkt_sent.q ),
1117:
1118: // to register interface (read)
1119: .qs (intr_enable_pkt_sent_qs)
1120: );
1121:
1122:
1123: // F[disconnected]: 2:2
1124: prim_subreg #(
1125: .DW (1),
1126: .SWACCESS("RW"),
1127: .RESVAL (1'h0)
1128: ) u_intr_enable_disconnected (
1129: .clk_i (clk_i ),
1130: .rst_ni (rst_ni ),
1131:
1132: // from register interface
1133: .we (intr_enable_disconnected_we),
1134: .wd (intr_enable_disconnected_wd),
1135:
1136: // from internal hardware
1137: .de (1'b0),
1138: .d ('0 ),
1139:
1140: // to internal hardware
1141: .qe (),
1142: .q (reg2hw.intr_enable.disconnected.q ),
1143:
1144: // to register interface (read)
1145: .qs (intr_enable_disconnected_qs)
1146: );
1147:
1148:
1149: // F[host_lost]: 3:3
1150: prim_subreg #(
1151: .DW (1),
1152: .SWACCESS("RW"),
1153: .RESVAL (1'h0)
1154: ) u_intr_enable_host_lost (
1155: .clk_i (clk_i ),
1156: .rst_ni (rst_ni ),
1157:
1158: // from register interface
1159: .we (intr_enable_host_lost_we),
1160: .wd (intr_enable_host_lost_wd),
1161:
1162: // from internal hardware
1163: .de (1'b0),
1164: .d ('0 ),
1165:
1166: // to internal hardware
1167: .qe (),
1168: .q (reg2hw.intr_enable.host_lost.q ),
1169:
1170: // to register interface (read)
1171: .qs (intr_enable_host_lost_qs)
1172: );
1173:
1174:
1175: // F[link_reset]: 4:4
1176: prim_subreg #(
1177: .DW (1),
1178: .SWACCESS("RW"),
1179: .RESVAL (1'h0)
1180: ) u_intr_enable_link_reset (
1181: .clk_i (clk_i ),
1182: .rst_ni (rst_ni ),
1183:
1184: // from register interface
1185: .we (intr_enable_link_reset_we),
1186: .wd (intr_enable_link_reset_wd),
1187:
1188: // from internal hardware
1189: .de (1'b0),
1190: .d ('0 ),
1191:
1192: // to internal hardware
1193: .qe (),
1194: .q (reg2hw.intr_enable.link_reset.q ),
1195:
1196: // to register interface (read)
1197: .qs (intr_enable_link_reset_qs)
1198: );
1199:
1200:
1201: // F[link_suspend]: 5:5
1202: prim_subreg #(
1203: .DW (1),
1204: .SWACCESS("RW"),
1205: .RESVAL (1'h0)
1206: ) u_intr_enable_link_suspend (
1207: .clk_i (clk_i ),
1208: .rst_ni (rst_ni ),
1209:
1210: // from register interface
1211: .we (intr_enable_link_suspend_we),
1212: .wd (intr_enable_link_suspend_wd),
1213:
1214: // from internal hardware
1215: .de (1'b0),
1216: .d ('0 ),
1217:
1218: // to internal hardware
1219: .qe (),
1220: .q (reg2hw.intr_enable.link_suspend.q ),
1221:
1222: // to register interface (read)
1223: .qs (intr_enable_link_suspend_qs)
1224: );
1225:
1226:
1227: // F[link_resume]: 6:6
1228: prim_subreg #(
1229: .DW (1),
1230: .SWACCESS("RW"),
1231: .RESVAL (1'h0)
1232: ) u_intr_enable_link_resume (
1233: .clk_i (clk_i ),
1234: .rst_ni (rst_ni ),
1235:
1236: // from register interface
1237: .we (intr_enable_link_resume_we),
1238: .wd (intr_enable_link_resume_wd),
1239:
1240: // from internal hardware
1241: .de (1'b0),
1242: .d ('0 ),
1243:
1244: // to internal hardware
1245: .qe (),
1246: .q (reg2hw.intr_enable.link_resume.q ),
1247:
1248: // to register interface (read)
1249: .qs (intr_enable_link_resume_qs)
1250: );
1251:
1252:
1253: // F[av_empty]: 7:7
1254: prim_subreg #(
1255: .DW (1),
1256: .SWACCESS("RW"),
1257: .RESVAL (1'h0)
1258: ) u_intr_enable_av_empty (
1259: .clk_i (clk_i ),
1260: .rst_ni (rst_ni ),
1261:
1262: // from register interface
1263: .we (intr_enable_av_empty_we),
1264: .wd (intr_enable_av_empty_wd),
1265:
1266: // from internal hardware
1267: .de (1'b0),
1268: .d ('0 ),
1269:
1270: // to internal hardware
1271: .qe (),
1272: .q (reg2hw.intr_enable.av_empty.q ),
1273:
1274: // to register interface (read)
1275: .qs (intr_enable_av_empty_qs)
1276: );
1277:
1278:
1279: // F[rx_full]: 8:8
1280: prim_subreg #(
1281: .DW (1),
1282: .SWACCESS("RW"),
1283: .RESVAL (1'h0)
1284: ) u_intr_enable_rx_full (
1285: .clk_i (clk_i ),
1286: .rst_ni (rst_ni ),
1287:
1288: // from register interface
1289: .we (intr_enable_rx_full_we),
1290: .wd (intr_enable_rx_full_wd),
1291:
1292: // from internal hardware
1293: .de (1'b0),
1294: .d ('0 ),
1295:
1296: // to internal hardware
1297: .qe (),
1298: .q (reg2hw.intr_enable.rx_full.q ),
1299:
1300: // to register interface (read)
1301: .qs (intr_enable_rx_full_qs)
1302: );
1303:
1304:
1305: // F[av_overflow]: 9:9
1306: prim_subreg #(
1307: .DW (1),
1308: .SWACCESS("RW"),
1309: .RESVAL (1'h0)
1310: ) u_intr_enable_av_overflow (
1311: .clk_i (clk_i ),
1312: .rst_ni (rst_ni ),
1313:
1314: // from register interface
1315: .we (intr_enable_av_overflow_we),
1316: .wd (intr_enable_av_overflow_wd),
1317:
1318: // from internal hardware
1319: .de (1'b0),
1320: .d ('0 ),
1321:
1322: // to internal hardware
1323: .qe (),
1324: .q (reg2hw.intr_enable.av_overflow.q ),
1325:
1326: // to register interface (read)
1327: .qs (intr_enable_av_overflow_qs)
1328: );
1329:
1330:
1331: // F[link_in_err]: 10:10
1332: prim_subreg #(
1333: .DW (1),
1334: .SWACCESS("RW"),
1335: .RESVAL (1'h0)
1336: ) u_intr_enable_link_in_err (
1337: .clk_i (clk_i ),
1338: .rst_ni (rst_ni ),
1339:
1340: // from register interface
1341: .we (intr_enable_link_in_err_we),
1342: .wd (intr_enable_link_in_err_wd),
1343:
1344: // from internal hardware
1345: .de (1'b0),
1346: .d ('0 ),
1347:
1348: // to internal hardware
1349: .qe (),
1350: .q (reg2hw.intr_enable.link_in_err.q ),
1351:
1352: // to register interface (read)
1353: .qs (intr_enable_link_in_err_qs)
1354: );
1355:
1356:
1357: // F[rx_crc_err]: 11:11
1358: prim_subreg #(
1359: .DW (1),
1360: .SWACCESS("RW"),
1361: .RESVAL (1'h0)
1362: ) u_intr_enable_rx_crc_err (
1363: .clk_i (clk_i ),
1364: .rst_ni (rst_ni ),
1365:
1366: // from register interface
1367: .we (intr_enable_rx_crc_err_we),
1368: .wd (intr_enable_rx_crc_err_wd),
1369:
1370: // from internal hardware
1371: .de (1'b0),
1372: .d ('0 ),
1373:
1374: // to internal hardware
1375: .qe (),
1376: .q (reg2hw.intr_enable.rx_crc_err.q ),
1377:
1378: // to register interface (read)
1379: .qs (intr_enable_rx_crc_err_qs)
1380: );
1381:
1382:
1383: // F[rx_pid_err]: 12:12
1384: prim_subreg #(
1385: .DW (1),
1386: .SWACCESS("RW"),
1387: .RESVAL (1'h0)
1388: ) u_intr_enable_rx_pid_err (
1389: .clk_i (clk_i ),
1390: .rst_ni (rst_ni ),
1391:
1392: // from register interface
1393: .we (intr_enable_rx_pid_err_we),
1394: .wd (intr_enable_rx_pid_err_wd),
1395:
1396: // from internal hardware
1397: .de (1'b0),
1398: .d ('0 ),
1399:
1400: // to internal hardware
1401: .qe (),
1402: .q (reg2hw.intr_enable.rx_pid_err.q ),
1403:
1404: // to register interface (read)
1405: .qs (intr_enable_rx_pid_err_qs)
1406: );
1407:
1408:
1409: // F[rx_bitstuff_err]: 13:13
1410: prim_subreg #(
1411: .DW (1),
1412: .SWACCESS("RW"),
1413: .RESVAL (1'h0)
1414: ) u_intr_enable_rx_bitstuff_err (
1415: .clk_i (clk_i ),
1416: .rst_ni (rst_ni ),
1417:
1418: // from register interface
1419: .we (intr_enable_rx_bitstuff_err_we),
1420: .wd (intr_enable_rx_bitstuff_err_wd),
1421:
1422: // from internal hardware
1423: .de (1'b0),
1424: .d ('0 ),
1425:
1426: // to internal hardware
1427: .qe (),
1428: .q (reg2hw.intr_enable.rx_bitstuff_err.q ),
1429:
1430: // to register interface (read)
1431: .qs (intr_enable_rx_bitstuff_err_qs)
1432: );
1433:
1434:
1435: // F[frame]: 14:14
1436: prim_subreg #(
1437: .DW (1),
1438: .SWACCESS("RW"),
1439: .RESVAL (1'h0)
1440: ) u_intr_enable_frame (
1441: .clk_i (clk_i ),
1442: .rst_ni (rst_ni ),
1443:
1444: // from register interface
1445: .we (intr_enable_frame_we),
1446: .wd (intr_enable_frame_wd),
1447:
1448: // from internal hardware
1449: .de (1'b0),
1450: .d ('0 ),
1451:
1452: // to internal hardware
1453: .qe (),
1454: .q (reg2hw.intr_enable.frame.q ),
1455:
1456: // to register interface (read)
1457: .qs (intr_enable_frame_qs)
1458: );
1459:
1460:
1461: // F[connected]: 15:15
1462: prim_subreg #(
1463: .DW (1),
1464: .SWACCESS("RW"),
1465: .RESVAL (1'h0)
1466: ) u_intr_enable_connected (
1467: .clk_i (clk_i ),
1468: .rst_ni (rst_ni ),
1469:
1470: // from register interface
1471: .we (intr_enable_connected_we),
1472: .wd (intr_enable_connected_wd),
1473:
1474: // from internal hardware
1475: .de (1'b0),
1476: .d ('0 ),
1477:
1478: // to internal hardware
1479: .qe (),
1480: .q (reg2hw.intr_enable.connected.q ),
1481:
1482: // to register interface (read)
1483: .qs (intr_enable_connected_qs)
1484: );
1485:
1486:
1487: // R[intr_test]: V(True)
1488:
1489: // F[pkt_received]: 0:0
1490: prim_subreg_ext #(
1491: .DW (1)
1492: ) u_intr_test_pkt_received (
1493: .re (1'b0),
1494: .we (intr_test_pkt_received_we),
1495: .wd (intr_test_pkt_received_wd),
1496: .d ('0),
1497: .qre (),
1498: .qe (reg2hw.intr_test.pkt_received.qe),
1499: .q (reg2hw.intr_test.pkt_received.q ),
1500: .qs ()
1501: );
1502:
1503:
1504: // F[pkt_sent]: 1:1
1505: prim_subreg_ext #(
1506: .DW (1)
1507: ) u_intr_test_pkt_sent (
1508: .re (1'b0),
1509: .we (intr_test_pkt_sent_we),
1510: .wd (intr_test_pkt_sent_wd),
1511: .d ('0),
1512: .qre (),
1513: .qe (reg2hw.intr_test.pkt_sent.qe),
1514: .q (reg2hw.intr_test.pkt_sent.q ),
1515: .qs ()
1516: );
1517:
1518:
1519: // F[disconnected]: 2:2
1520: prim_subreg_ext #(
1521: .DW (1)
1522: ) u_intr_test_disconnected (
1523: .re (1'b0),
1524: .we (intr_test_disconnected_we),
1525: .wd (intr_test_disconnected_wd),
1526: .d ('0),
1527: .qre (),
1528: .qe (reg2hw.intr_test.disconnected.qe),
1529: .q (reg2hw.intr_test.disconnected.q ),
1530: .qs ()
1531: );
1532:
1533:
1534: // F[host_lost]: 3:3
1535: prim_subreg_ext #(
1536: .DW (1)
1537: ) u_intr_test_host_lost (
1538: .re (1'b0),
1539: .we (intr_test_host_lost_we),
1540: .wd (intr_test_host_lost_wd),
1541: .d ('0),
1542: .qre (),
1543: .qe (reg2hw.intr_test.host_lost.qe),
1544: .q (reg2hw.intr_test.host_lost.q ),
1545: .qs ()
1546: );
1547:
1548:
1549: // F[link_reset]: 4:4
1550: prim_subreg_ext #(
1551: .DW (1)
1552: ) u_intr_test_link_reset (
1553: .re (1'b0),
1554: .we (intr_test_link_reset_we),
1555: .wd (intr_test_link_reset_wd),
1556: .d ('0),
1557: .qre (),
1558: .qe (reg2hw.intr_test.link_reset.qe),
1559: .q (reg2hw.intr_test.link_reset.q ),
1560: .qs ()
1561: );
1562:
1563:
1564: // F[link_suspend]: 5:5
1565: prim_subreg_ext #(
1566: .DW (1)
1567: ) u_intr_test_link_suspend (
1568: .re (1'b0),
1569: .we (intr_test_link_suspend_we),
1570: .wd (intr_test_link_suspend_wd),
1571: .d ('0),
1572: .qre (),
1573: .qe (reg2hw.intr_test.link_suspend.qe),
1574: .q (reg2hw.intr_test.link_suspend.q ),
1575: .qs ()
1576: );
1577:
1578:
1579: // F[link_resume]: 6:6
1580: prim_subreg_ext #(
1581: .DW (1)
1582: ) u_intr_test_link_resume (
1583: .re (1'b0),
1584: .we (intr_test_link_resume_we),
1585: .wd (intr_test_link_resume_wd),
1586: .d ('0),
1587: .qre (),
1588: .qe (reg2hw.intr_test.link_resume.qe),
1589: .q (reg2hw.intr_test.link_resume.q ),
1590: .qs ()
1591: );
1592:
1593:
1594: // F[av_empty]: 7:7
1595: prim_subreg_ext #(
1596: .DW (1)
1597: ) u_intr_test_av_empty (
1598: .re (1'b0),
1599: .we (intr_test_av_empty_we),
1600: .wd (intr_test_av_empty_wd),
1601: .d ('0),
1602: .qre (),
1603: .qe (reg2hw.intr_test.av_empty.qe),
1604: .q (reg2hw.intr_test.av_empty.q ),
1605: .qs ()
1606: );
1607:
1608:
1609: // F[rx_full]: 8:8
1610: prim_subreg_ext #(
1611: .DW (1)
1612: ) u_intr_test_rx_full (
1613: .re (1'b0),
1614: .we (intr_test_rx_full_we),
1615: .wd (intr_test_rx_full_wd),
1616: .d ('0),
1617: .qre (),
1618: .qe (reg2hw.intr_test.rx_full.qe),
1619: .q (reg2hw.intr_test.rx_full.q ),
1620: .qs ()
1621: );
1622:
1623:
1624: // F[av_overflow]: 9:9
1625: prim_subreg_ext #(
1626: .DW (1)
1627: ) u_intr_test_av_overflow (
1628: .re (1'b0),
1629: .we (intr_test_av_overflow_we),
1630: .wd (intr_test_av_overflow_wd),
1631: .d ('0),
1632: .qre (),
1633: .qe (reg2hw.intr_test.av_overflow.qe),
1634: .q (reg2hw.intr_test.av_overflow.q ),
1635: .qs ()
1636: );
1637:
1638:
1639: // F[link_in_err]: 10:10
1640: prim_subreg_ext #(
1641: .DW (1)
1642: ) u_intr_test_link_in_err (
1643: .re (1'b0),
1644: .we (intr_test_link_in_err_we),
1645: .wd (intr_test_link_in_err_wd),
1646: .d ('0),
1647: .qre (),
1648: .qe (reg2hw.intr_test.link_in_err.qe),
1649: .q (reg2hw.intr_test.link_in_err.q ),
1650: .qs ()
1651: );
1652:
1653:
1654: // F[rx_crc_err]: 11:11
1655: prim_subreg_ext #(
1656: .DW (1)
1657: ) u_intr_test_rx_crc_err (
1658: .re (1'b0),
1659: .we (intr_test_rx_crc_err_we),
1660: .wd (intr_test_rx_crc_err_wd),
1661: .d ('0),
1662: .qre (),
1663: .qe (reg2hw.intr_test.rx_crc_err.qe),
1664: .q (reg2hw.intr_test.rx_crc_err.q ),
1665: .qs ()
1666: );
1667:
1668:
1669: // F[rx_pid_err]: 12:12
1670: prim_subreg_ext #(
1671: .DW (1)
1672: ) u_intr_test_rx_pid_err (
1673: .re (1'b0),
1674: .we (intr_test_rx_pid_err_we),
1675: .wd (intr_test_rx_pid_err_wd),
1676: .d ('0),
1677: .qre (),
1678: .qe (reg2hw.intr_test.rx_pid_err.qe),
1679: .q (reg2hw.intr_test.rx_pid_err.q ),
1680: .qs ()
1681: );
1682:
1683:
1684: // F[rx_bitstuff_err]: 13:13
1685: prim_subreg_ext #(
1686: .DW (1)
1687: ) u_intr_test_rx_bitstuff_err (
1688: .re (1'b0),
1689: .we (intr_test_rx_bitstuff_err_we),
1690: .wd (intr_test_rx_bitstuff_err_wd),
1691: .d ('0),
1692: .qre (),
1693: .qe (reg2hw.intr_test.rx_bitstuff_err.qe),
1694: .q (reg2hw.intr_test.rx_bitstuff_err.q ),
1695: .qs ()
1696: );
1697:
1698:
1699: // F[frame]: 14:14
1700: prim_subreg_ext #(
1701: .DW (1)
1702: ) u_intr_test_frame (
1703: .re (1'b0),
1704: .we (intr_test_frame_we),
1705: .wd (intr_test_frame_wd),
1706: .d ('0),
1707: .qre (),
1708: .qe (reg2hw.intr_test.frame.qe),
1709: .q (reg2hw.intr_test.frame.q ),
1710: .qs ()
1711: );
1712:
1713:
1714: // F[connected]: 15:15
1715: prim_subreg_ext #(
1716: .DW (1)
1717: ) u_intr_test_connected (
1718: .re (1'b0),
1719: .we (intr_test_connected_we),
1720: .wd (intr_test_connected_wd),
1721: .d ('0),
1722: .qre (),
1723: .qe (reg2hw.intr_test.connected.qe),
1724: .q (reg2hw.intr_test.connected.q ),
1725: .qs ()
1726: );
1727:
1728:
1729: // R[usbctrl]: V(False)
1730:
1731: // F[enable]: 0:0
1732: prim_subreg #(
1733: .DW (1),
1734: .SWACCESS("RW"),
1735: .RESVAL (1'h0)
1736: ) u_usbctrl_enable (
1737: .clk_i (clk_i ),
1738: .rst_ni (rst_ni ),
1739:
1740: // from register interface
1741: .we (usbctrl_enable_we),
1742: .wd (usbctrl_enable_wd),
1743:
1744: // from internal hardware
1745: .de (1'b0),
1746: .d ('0 ),
1747:
1748: // to internal hardware
1749: .qe (),
1750: .q (reg2hw.usbctrl.enable.q ),
1751:
1752: // to register interface (read)
1753: .qs (usbctrl_enable_qs)
1754: );
1755:
1756:
1757: // F[device_address]: 22:16
1758: prim_subreg #(
1759: .DW (7),
1760: .SWACCESS("RW"),
1761: .RESVAL (7'h0)
1762: ) u_usbctrl_device_address (
1763: .clk_i (clk_i ),
1764: .rst_ni (rst_ni ),
1765:
1766: // from register interface
1767: .we (usbctrl_device_address_we),
1768: .wd (usbctrl_device_address_wd),
1769:
1770: // from internal hardware
1771: .de (hw2reg.usbctrl.device_address.de),
1772: .d (hw2reg.usbctrl.device_address.d ),
1773:
1774: // to internal hardware
1775: .qe (),
1776: .q (reg2hw.usbctrl.device_address.q ),
1777:
1778: // to register interface (read)
1779: .qs (usbctrl_device_address_qs)
1780: );
1781:
1782:
1783: // R[usbstat]: V(True)
1784:
1785: // F[frame]: 10:0
1786: prim_subreg_ext #(
1787: .DW (11)
1788: ) u_usbstat_frame (
1789: .re (usbstat_frame_re),
1790: .we (1'b0),
1791: .wd ('0),
1792: .d (hw2reg.usbstat.frame.d),
1793: .qre (),
1794: .qe (),
1795: .q (),
1796: .qs (usbstat_frame_qs)
1797: );
1798:
1799:
1800: // F[host_lost]: 11:11
1801: prim_subreg_ext #(
1802: .DW (1)
1803: ) u_usbstat_host_lost (
1804: .re (usbstat_host_lost_re),
1805: .we (1'b0),
1806: .wd ('0),
1807: .d (hw2reg.usbstat.host_lost.d),
1808: .qre (),
1809: .qe (),
1810: .q (),
1811: .qs (usbstat_host_lost_qs)
1812: );
1813:
1814:
1815: // F[link_state]: 14:12
1816: prim_subreg_ext #(
1817: .DW (3)
1818: ) u_usbstat_link_state (
1819: .re (usbstat_link_state_re),
1820: .we (1'b0),
1821: .wd ('0),
1822: .d (hw2reg.usbstat.link_state.d),
1823: .qre (),
1824: .qe (),
1825: .q (),
1826: .qs (usbstat_link_state_qs)
1827: );
1828:
1829:
1830: // F[sense]: 15:15
1831: prim_subreg_ext #(
1832: .DW (1)
1833: ) u_usbstat_sense (
1834: .re (usbstat_sense_re),
1835: .we (1'b0),
1836: .wd ('0),
1837: .d (hw2reg.usbstat.sense.d),
1838: .qre (),
1839: .qe (),
1840: .q (),
1841: .qs (usbstat_sense_qs)
1842: );
1843:
1844:
1845: // F[av_depth]: 18:16
1846: prim_subreg_ext #(
1847: .DW (3)
1848: ) u_usbstat_av_depth (
1849: .re (usbstat_av_depth_re),
1850: .we (1'b0),
1851: .wd ('0),
1852: .d (hw2reg.usbstat.av_depth.d),
1853: .qre (),
1854: .qe (),
1855: .q (),
1856: .qs (usbstat_av_depth_qs)
1857: );
1858:
1859:
1860: // F[av_full]: 23:23
1861: prim_subreg_ext #(
1862: .DW (1)
1863: ) u_usbstat_av_full (
1864: .re (usbstat_av_full_re),
1865: .we (1'b0),
1866: .wd ('0),
1867: .d (hw2reg.usbstat.av_full.d),
1868: .qre (),
1869: .qe (),
1870: .q (),
1871: .qs (usbstat_av_full_qs)
1872: );
1873:
1874:
1875: // F[rx_depth]: 26:24
1876: prim_subreg_ext #(
1877: .DW (3)
1878: ) u_usbstat_rx_depth (
1879: .re (usbstat_rx_depth_re),
1880: .we (1'b0),
1881: .wd ('0),
1882: .d (hw2reg.usbstat.rx_depth.d),
1883: .qre (),
1884: .qe (),
1885: .q (),
1886: .qs (usbstat_rx_depth_qs)
1887: );
1888:
1889:
1890: // F[rx_empty]: 31:31
1891: prim_subreg_ext #(
1892: .DW (1)
1893: ) u_usbstat_rx_empty (
1894: .re (usbstat_rx_empty_re),
1895: .we (1'b0),
1896: .wd ('0),
1897: .d (hw2reg.usbstat.rx_empty.d),
1898: .qre (),
1899: .qe (),
1900: .q (),
1901: .qs (usbstat_rx_empty_qs)
1902: );
1903:
1904:
1905: // R[avbuffer]: V(False)
1906:
1907: prim_subreg #(
1908: .DW (5),
1909: .SWACCESS("WO"),
1910: .RESVAL (5'h0)
1911: ) u_avbuffer (
1912: .clk_i (clk_i ),
1913: .rst_ni (rst_ni ),
1914:
1915: // from register interface
1916: .we (avbuffer_we),
1917: .wd (avbuffer_wd),
1918:
1919: // from internal hardware
1920: .de (1'b0),
1921: .d ('0 ),
1922:
1923: // to internal hardware
1924: .qe (reg2hw.avbuffer.qe),
1925: .q (reg2hw.avbuffer.q ),
1926:
1927: .qs ()
1928: );
1929:
1930:
1931: // R[rxfifo]: V(True)
1932:
1933: // F[buffer]: 4:0
1934: prim_subreg_ext #(
1935: .DW (5)
1936: ) u_rxfifo_buffer (
1937: .re (rxfifo_buffer_re),
1938: .we (1'b0),
1939: .wd ('0),
1940: .d (hw2reg.rxfifo.buffer.d),
1941: .qre (reg2hw.rxfifo.buffer.re),
1942: .qe (),
1943: .q (reg2hw.rxfifo.buffer.q ),
1944: .qs (rxfifo_buffer_qs)
1945: );
1946:
1947:
1948: // F[size]: 14:8
1949: prim_subreg_ext #(
1950: .DW (7)
1951: ) u_rxfifo_size (
1952: .re (rxfifo_size_re),
1953: .we (1'b0),
1954: .wd ('0),
1955: .d (hw2reg.rxfifo.size.d),
1956: .qre (reg2hw.rxfifo.size.re),
1957: .qe (),
1958: .q (reg2hw.rxfifo.size.q ),
1959: .qs (rxfifo_size_qs)
1960: );
1961:
1962:
1963: // F[setup]: 19:19
1964: prim_subreg_ext #(
1965: .DW (1)
1966: ) u_rxfifo_setup (
1967: .re (rxfifo_setup_re),
1968: .we (1'b0),
1969: .wd ('0),
1970: .d (hw2reg.rxfifo.setup.d),
1971: .qre (reg2hw.rxfifo.setup.re),
1972: .qe (),
1973: .q (reg2hw.rxfifo.setup.q ),
1974: .qs (rxfifo_setup_qs)
1975: );
1976:
1977:
1978: // F[ep]: 23:20
1979: prim_subreg_ext #(
1980: .DW (4)
1981: ) u_rxfifo_ep (
1982: .re (rxfifo_ep_re),
1983: .we (1'b0),
1984: .wd ('0),
1985: .d (hw2reg.rxfifo.ep.d),
1986: .qre (reg2hw.rxfifo.ep.re),
1987: .qe (),
1988: .q (reg2hw.rxfifo.ep.q ),
1989: .qs (rxfifo_ep_qs)
1990: );
1991:
1992:
1993:
1994: // Subregister 0 of Multireg rxenable_setup
1995: // R[rxenable_setup]: V(False)
1996:
1997: // F[setup0]: 0:0
1998: prim_subreg #(
1999: .DW (1),
2000: .SWACCESS("RW"),
2001: .RESVAL (1'h0)
2002: ) u_rxenable_setup_setup0 (
2003: .clk_i (clk_i ),
2004: .rst_ni (rst_ni ),
2005:
2006: // from register interface
2007: .we (rxenable_setup_setup0_we),
2008: .wd (rxenable_setup_setup0_wd),
2009:
2010: // from internal hardware
2011: .de (1'b0),
2012: .d ('0 ),
2013:
2014: // to internal hardware
2015: .qe (),
2016: .q (reg2hw.rxenable_setup[0].q ),
2017:
2018: // to register interface (read)
2019: .qs (rxenable_setup_setup0_qs)
2020: );
2021:
2022:
2023: // F[setup1]: 1:1
2024: prim_subreg #(
2025: .DW (1),
2026: .SWACCESS("RW"),
2027: .RESVAL (1'h0)
2028: ) u_rxenable_setup_setup1 (
2029: .clk_i (clk_i ),
2030: .rst_ni (rst_ni ),
2031:
2032: // from register interface
2033: .we (rxenable_setup_setup1_we),
2034: .wd (rxenable_setup_setup1_wd),
2035:
2036: // from internal hardware
2037: .de (1'b0),
2038: .d ('0 ),
2039:
2040: // to internal hardware
2041: .qe (),
2042: .q (reg2hw.rxenable_setup[1].q ),
2043:
2044: // to register interface (read)
2045: .qs (rxenable_setup_setup1_qs)
2046: );
2047:
2048:
2049: // F[setup2]: 2:2
2050: prim_subreg #(
2051: .DW (1),
2052: .SWACCESS("RW"),
2053: .RESVAL (1'h0)
2054: ) u_rxenable_setup_setup2 (
2055: .clk_i (clk_i ),
2056: .rst_ni (rst_ni ),
2057:
2058: // from register interface
2059: .we (rxenable_setup_setup2_we),
2060: .wd (rxenable_setup_setup2_wd),
2061:
2062: // from internal hardware
2063: .de (1'b0),
2064: .d ('0 ),
2065:
2066: // to internal hardware
2067: .qe (),
2068: .q (reg2hw.rxenable_setup[2].q ),
2069:
2070: // to register interface (read)
2071: .qs (rxenable_setup_setup2_qs)
2072: );
2073:
2074:
2075: // F[setup3]: 3:3
2076: prim_subreg #(
2077: .DW (1),
2078: .SWACCESS("RW"),
2079: .RESVAL (1'h0)
2080: ) u_rxenable_setup_setup3 (
2081: .clk_i (clk_i ),
2082: .rst_ni (rst_ni ),
2083:
2084: // from register interface
2085: .we (rxenable_setup_setup3_we),
2086: .wd (rxenable_setup_setup3_wd),
2087:
2088: // from internal hardware
2089: .de (1'b0),
2090: .d ('0 ),
2091:
2092: // to internal hardware
2093: .qe (),
2094: .q (reg2hw.rxenable_setup[3].q ),
2095:
2096: // to register interface (read)
2097: .qs (rxenable_setup_setup3_qs)
2098: );
2099:
2100:
2101: // F[setup4]: 4:4
2102: prim_subreg #(
2103: .DW (1),
2104: .SWACCESS("RW"),
2105: .RESVAL (1'h0)
2106: ) u_rxenable_setup_setup4 (
2107: .clk_i (clk_i ),
2108: .rst_ni (rst_ni ),
2109:
2110: // from register interface
2111: .we (rxenable_setup_setup4_we),
2112: .wd (rxenable_setup_setup4_wd),
2113:
2114: // from internal hardware
2115: .de (1'b0),
2116: .d ('0 ),
2117:
2118: // to internal hardware
2119: .qe (),
2120: .q (reg2hw.rxenable_setup[4].q ),
2121:
2122: // to register interface (read)
2123: .qs (rxenable_setup_setup4_qs)
2124: );
2125:
2126:
2127: // F[setup5]: 5:5
2128: prim_subreg #(
2129: .DW (1),
2130: .SWACCESS("RW"),
2131: .RESVAL (1'h0)
2132: ) u_rxenable_setup_setup5 (
2133: .clk_i (clk_i ),
2134: .rst_ni (rst_ni ),
2135:
2136: // from register interface
2137: .we (rxenable_setup_setup5_we),
2138: .wd (rxenable_setup_setup5_wd),
2139:
2140: // from internal hardware
2141: .de (1'b0),
2142: .d ('0 ),
2143:
2144: // to internal hardware
2145: .qe (),
2146: .q (reg2hw.rxenable_setup[5].q ),
2147:
2148: // to register interface (read)
2149: .qs (rxenable_setup_setup5_qs)
2150: );
2151:
2152:
2153: // F[setup6]: 6:6
2154: prim_subreg #(
2155: .DW (1),
2156: .SWACCESS("RW"),
2157: .RESVAL (1'h0)
2158: ) u_rxenable_setup_setup6 (
2159: .clk_i (clk_i ),
2160: .rst_ni (rst_ni ),
2161:
2162: // from register interface
2163: .we (rxenable_setup_setup6_we),
2164: .wd (rxenable_setup_setup6_wd),
2165:
2166: // from internal hardware
2167: .de (1'b0),
2168: .d ('0 ),
2169:
2170: // to internal hardware
2171: .qe (),
2172: .q (reg2hw.rxenable_setup[6].q ),
2173:
2174: // to register interface (read)
2175: .qs (rxenable_setup_setup6_qs)
2176: );
2177:
2178:
2179: // F[setup7]: 7:7
2180: prim_subreg #(
2181: .DW (1),
2182: .SWACCESS("RW"),
2183: .RESVAL (1'h0)
2184: ) u_rxenable_setup_setup7 (
2185: .clk_i (clk_i ),
2186: .rst_ni (rst_ni ),
2187:
2188: // from register interface
2189: .we (rxenable_setup_setup7_we),
2190: .wd (rxenable_setup_setup7_wd),
2191:
2192: // from internal hardware
2193: .de (1'b0),
2194: .d ('0 ),
2195:
2196: // to internal hardware
2197: .qe (),
2198: .q (reg2hw.rxenable_setup[7].q ),
2199:
2200: // to register interface (read)
2201: .qs (rxenable_setup_setup7_qs)
2202: );
2203:
2204:
2205: // F[setup8]: 8:8
2206: prim_subreg #(
2207: .DW (1),
2208: .SWACCESS("RW"),
2209: .RESVAL (1'h0)
2210: ) u_rxenable_setup_setup8 (
2211: .clk_i (clk_i ),
2212: .rst_ni (rst_ni ),
2213:
2214: // from register interface
2215: .we (rxenable_setup_setup8_we),
2216: .wd (rxenable_setup_setup8_wd),
2217:
2218: // from internal hardware
2219: .de (1'b0),
2220: .d ('0 ),
2221:
2222: // to internal hardware
2223: .qe (),
2224: .q (reg2hw.rxenable_setup[8].q ),
2225:
2226: // to register interface (read)
2227: .qs (rxenable_setup_setup8_qs)
2228: );
2229:
2230:
2231: // F[setup9]: 9:9
2232: prim_subreg #(
2233: .DW (1),
2234: .SWACCESS("RW"),
2235: .RESVAL (1'h0)
2236: ) u_rxenable_setup_setup9 (
2237: .clk_i (clk_i ),
2238: .rst_ni (rst_ni ),
2239:
2240: // from register interface
2241: .we (rxenable_setup_setup9_we),
2242: .wd (rxenable_setup_setup9_wd),
2243:
2244: // from internal hardware
2245: .de (1'b0),
2246: .d ('0 ),
2247:
2248: // to internal hardware
2249: .qe (),
2250: .q (reg2hw.rxenable_setup[9].q ),
2251:
2252: // to register interface (read)
2253: .qs (rxenable_setup_setup9_qs)
2254: );
2255:
2256:
2257: // F[setup10]: 10:10
2258: prim_subreg #(
2259: .DW (1),
2260: .SWACCESS("RW"),
2261: .RESVAL (1'h0)
2262: ) u_rxenable_setup_setup10 (
2263: .clk_i (clk_i ),
2264: .rst_ni (rst_ni ),
2265:
2266: // from register interface
2267: .we (rxenable_setup_setup10_we),
2268: .wd (rxenable_setup_setup10_wd),
2269:
2270: // from internal hardware
2271: .de (1'b0),
2272: .d ('0 ),
2273:
2274: // to internal hardware
2275: .qe (),
2276: .q (reg2hw.rxenable_setup[10].q ),
2277:
2278: // to register interface (read)
2279: .qs (rxenable_setup_setup10_qs)
2280: );
2281:
2282:
2283: // F[setup11]: 11:11
2284: prim_subreg #(
2285: .DW (1),
2286: .SWACCESS("RW"),
2287: .RESVAL (1'h0)
2288: ) u_rxenable_setup_setup11 (
2289: .clk_i (clk_i ),
2290: .rst_ni (rst_ni ),
2291:
2292: // from register interface
2293: .we (rxenable_setup_setup11_we),
2294: .wd (rxenable_setup_setup11_wd),
2295:
2296: // from internal hardware
2297: .de (1'b0),
2298: .d ('0 ),
2299:
2300: // to internal hardware
2301: .qe (),
2302: .q (reg2hw.rxenable_setup[11].q ),
2303:
2304: // to register interface (read)
2305: .qs (rxenable_setup_setup11_qs)
2306: );
2307:
2308:
2309:
2310:
2311: // Subregister 0 of Multireg rxenable_out
2312: // R[rxenable_out]: V(False)
2313:
2314: // F[out0]: 0:0
2315: prim_subreg #(
2316: .DW (1),
2317: .SWACCESS("RW"),
2318: .RESVAL (1'h0)
2319: ) u_rxenable_out_out0 (
2320: .clk_i (clk_i ),
2321: .rst_ni (rst_ni ),
2322:
2323: // from register interface
2324: .we (rxenable_out_out0_we),
2325: .wd (rxenable_out_out0_wd),
2326:
2327: // from internal hardware
2328: .de (1'b0),
2329: .d ('0 ),
2330:
2331: // to internal hardware
2332: .qe (),
2333: .q (reg2hw.rxenable_out[0].q ),
2334:
2335: // to register interface (read)
2336: .qs (rxenable_out_out0_qs)
2337: );
2338:
2339:
2340: // F[out1]: 1:1
2341: prim_subreg #(
2342: .DW (1),
2343: .SWACCESS("RW"),
2344: .RESVAL (1'h0)
2345: ) u_rxenable_out_out1 (
2346: .clk_i (clk_i ),
2347: .rst_ni (rst_ni ),
2348:
2349: // from register interface
2350: .we (rxenable_out_out1_we),
2351: .wd (rxenable_out_out1_wd),
2352:
2353: // from internal hardware
2354: .de (1'b0),
2355: .d ('0 ),
2356:
2357: // to internal hardware
2358: .qe (),
2359: .q (reg2hw.rxenable_out[1].q ),
2360:
2361: // to register interface (read)
2362: .qs (rxenable_out_out1_qs)
2363: );
2364:
2365:
2366: // F[out2]: 2:2
2367: prim_subreg #(
2368: .DW (1),
2369: .SWACCESS("RW"),
2370: .RESVAL (1'h0)
2371: ) u_rxenable_out_out2 (
2372: .clk_i (clk_i ),
2373: .rst_ni (rst_ni ),
2374:
2375: // from register interface
2376: .we (rxenable_out_out2_we),
2377: .wd (rxenable_out_out2_wd),
2378:
2379: // from internal hardware
2380: .de (1'b0),
2381: .d ('0 ),
2382:
2383: // to internal hardware
2384: .qe (),
2385: .q (reg2hw.rxenable_out[2].q ),
2386:
2387: // to register interface (read)
2388: .qs (rxenable_out_out2_qs)
2389: );
2390:
2391:
2392: // F[out3]: 3:3
2393: prim_subreg #(
2394: .DW (1),
2395: .SWACCESS("RW"),
2396: .RESVAL (1'h0)
2397: ) u_rxenable_out_out3 (
2398: .clk_i (clk_i ),
2399: .rst_ni (rst_ni ),
2400:
2401: // from register interface
2402: .we (rxenable_out_out3_we),
2403: .wd (rxenable_out_out3_wd),
2404:
2405: // from internal hardware
2406: .de (1'b0),
2407: .d ('0 ),
2408:
2409: // to internal hardware
2410: .qe (),
2411: .q (reg2hw.rxenable_out[3].q ),
2412:
2413: // to register interface (read)
2414: .qs (rxenable_out_out3_qs)
2415: );
2416:
2417:
2418: // F[out4]: 4:4
2419: prim_subreg #(
2420: .DW (1),
2421: .SWACCESS("RW"),
2422: .RESVAL (1'h0)
2423: ) u_rxenable_out_out4 (
2424: .clk_i (clk_i ),
2425: .rst_ni (rst_ni ),
2426:
2427: // from register interface
2428: .we (rxenable_out_out4_we),
2429: .wd (rxenable_out_out4_wd),
2430:
2431: // from internal hardware
2432: .de (1'b0),
2433: .d ('0 ),
2434:
2435: // to internal hardware
2436: .qe (),
2437: .q (reg2hw.rxenable_out[4].q ),
2438:
2439: // to register interface (read)
2440: .qs (rxenable_out_out4_qs)
2441: );
2442:
2443:
2444: // F[out5]: 5:5
2445: prim_subreg #(
2446: .DW (1),
2447: .SWACCESS("RW"),
2448: .RESVAL (1'h0)
2449: ) u_rxenable_out_out5 (
2450: .clk_i (clk_i ),
2451: .rst_ni (rst_ni ),
2452:
2453: // from register interface
2454: .we (rxenable_out_out5_we),
2455: .wd (rxenable_out_out5_wd),
2456:
2457: // from internal hardware
2458: .de (1'b0),
2459: .d ('0 ),
2460:
2461: // to internal hardware
2462: .qe (),
2463: .q (reg2hw.rxenable_out[5].q ),
2464:
2465: // to register interface (read)
2466: .qs (rxenable_out_out5_qs)
2467: );
2468:
2469:
2470: // F[out6]: 6:6
2471: prim_subreg #(
2472: .DW (1),
2473: .SWACCESS("RW"),
2474: .RESVAL (1'h0)
2475: ) u_rxenable_out_out6 (
2476: .clk_i (clk_i ),
2477: .rst_ni (rst_ni ),
2478:
2479: // from register interface
2480: .we (rxenable_out_out6_we),
2481: .wd (rxenable_out_out6_wd),
2482:
2483: // from internal hardware
2484: .de (1'b0),
2485: .d ('0 ),
2486:
2487: // to internal hardware
2488: .qe (),
2489: .q (reg2hw.rxenable_out[6].q ),
2490:
2491: // to register interface (read)
2492: .qs (rxenable_out_out6_qs)
2493: );
2494:
2495:
2496: // F[out7]: 7:7
2497: prim_subreg #(
2498: .DW (1),
2499: .SWACCESS("RW"),
2500: .RESVAL (1'h0)
2501: ) u_rxenable_out_out7 (
2502: .clk_i (clk_i ),
2503: .rst_ni (rst_ni ),
2504:
2505: // from register interface
2506: .we (rxenable_out_out7_we),
2507: .wd (rxenable_out_out7_wd),
2508:
2509: // from internal hardware
2510: .de (1'b0),
2511: .d ('0 ),
2512:
2513: // to internal hardware
2514: .qe (),
2515: .q (reg2hw.rxenable_out[7].q ),
2516:
2517: // to register interface (read)
2518: .qs (rxenable_out_out7_qs)
2519: );
2520:
2521:
2522: // F[out8]: 8:8
2523: prim_subreg #(
2524: .DW (1),
2525: .SWACCESS("RW"),
2526: .RESVAL (1'h0)
2527: ) u_rxenable_out_out8 (
2528: .clk_i (clk_i ),
2529: .rst_ni (rst_ni ),
2530:
2531: // from register interface
2532: .we (rxenable_out_out8_we),
2533: .wd (rxenable_out_out8_wd),
2534:
2535: // from internal hardware
2536: .de (1'b0),
2537: .d ('0 ),
2538:
2539: // to internal hardware
2540: .qe (),
2541: .q (reg2hw.rxenable_out[8].q ),
2542:
2543: // to register interface (read)
2544: .qs (rxenable_out_out8_qs)
2545: );
2546:
2547:
2548: // F[out9]: 9:9
2549: prim_subreg #(
2550: .DW (1),
2551: .SWACCESS("RW"),
2552: .RESVAL (1'h0)
2553: ) u_rxenable_out_out9 (
2554: .clk_i (clk_i ),
2555: .rst_ni (rst_ni ),
2556:
2557: // from register interface
2558: .we (rxenable_out_out9_we),
2559: .wd (rxenable_out_out9_wd),
2560:
2561: // from internal hardware
2562: .de (1'b0),
2563: .d ('0 ),
2564:
2565: // to internal hardware
2566: .qe (),
2567: .q (reg2hw.rxenable_out[9].q ),
2568:
2569: // to register interface (read)
2570: .qs (rxenable_out_out9_qs)
2571: );
2572:
2573:
2574: // F[out10]: 10:10
2575: prim_subreg #(
2576: .DW (1),
2577: .SWACCESS("RW"),
2578: .RESVAL (1'h0)
2579: ) u_rxenable_out_out10 (
2580: .clk_i (clk_i ),
2581: .rst_ni (rst_ni ),
2582:
2583: // from register interface
2584: .we (rxenable_out_out10_we),
2585: .wd (rxenable_out_out10_wd),
2586:
2587: // from internal hardware
2588: .de (1'b0),
2589: .d ('0 ),
2590:
2591: // to internal hardware
2592: .qe (),
2593: .q (reg2hw.rxenable_out[10].q ),
2594:
2595: // to register interface (read)
2596: .qs (rxenable_out_out10_qs)
2597: );
2598:
2599:
2600: // F[out11]: 11:11
2601: prim_subreg #(
2602: .DW (1),
2603: .SWACCESS("RW"),
2604: .RESVAL (1'h0)
2605: ) u_rxenable_out_out11 (
2606: .clk_i (clk_i ),
2607: .rst_ni (rst_ni ),
2608:
2609: // from register interface
2610: .we (rxenable_out_out11_we),
2611: .wd (rxenable_out_out11_wd),
2612:
2613: // from internal hardware
2614: .de (1'b0),
2615: .d ('0 ),
2616:
2617: // to internal hardware
2618: .qe (),
2619: .q (reg2hw.rxenable_out[11].q ),
2620:
2621: // to register interface (read)
2622: .qs (rxenable_out_out11_qs)
2623: );
2624:
2625:
2626:
2627:
2628: // Subregister 0 of Multireg in_sent
2629: // R[in_sent]: V(False)
2630:
2631: // F[sent0]: 0:0
2632: prim_subreg #(
2633: .DW (1),
2634: .SWACCESS("W1C"),
2635: .RESVAL (1'h0)
2636: ) u_in_sent_sent0 (
2637: .clk_i (clk_i ),
2638: .rst_ni (rst_ni ),
2639:
2640: // from register interface
2641: .we (in_sent_sent0_we),
2642: .wd (in_sent_sent0_wd),
2643:
2644: // from internal hardware
2645: .de (hw2reg.in_sent[0].de),
2646: .d (hw2reg.in_sent[0].d ),
2647:
2648: // to internal hardware
2649: .qe (),
2650: .q (),
2651:
2652: // to register interface (read)
2653: .qs (in_sent_sent0_qs)
2654: );
2655:
2656:
2657: // F[sent1]: 1:1
2658: prim_subreg #(
2659: .DW (1),
2660: .SWACCESS("W1C"),
2661: .RESVAL (1'h0)
2662: ) u_in_sent_sent1 (
2663: .clk_i (clk_i ),
2664: .rst_ni (rst_ni ),
2665:
2666: // from register interface
2667: .we (in_sent_sent1_we),
2668: .wd (in_sent_sent1_wd),
2669:
2670: // from internal hardware
2671: .de (hw2reg.in_sent[1].de),
2672: .d (hw2reg.in_sent[1].d ),
2673:
2674: // to internal hardware
2675: .qe (),
2676: .q (),
2677:
2678: // to register interface (read)
2679: .qs (in_sent_sent1_qs)
2680: );
2681:
2682:
2683: // F[sent2]: 2:2
2684: prim_subreg #(
2685: .DW (1),
2686: .SWACCESS("W1C"),
2687: .RESVAL (1'h0)
2688: ) u_in_sent_sent2 (
2689: .clk_i (clk_i ),
2690: .rst_ni (rst_ni ),
2691:
2692: // from register interface
2693: .we (in_sent_sent2_we),
2694: .wd (in_sent_sent2_wd),
2695:
2696: // from internal hardware
2697: .de (hw2reg.in_sent[2].de),
2698: .d (hw2reg.in_sent[2].d ),
2699:
2700: // to internal hardware
2701: .qe (),
2702: .q (),
2703:
2704: // to register interface (read)
2705: .qs (in_sent_sent2_qs)
2706: );
2707:
2708:
2709: // F[sent3]: 3:3
2710: prim_subreg #(
2711: .DW (1),
2712: .SWACCESS("W1C"),
2713: .RESVAL (1'h0)
2714: ) u_in_sent_sent3 (
2715: .clk_i (clk_i ),
2716: .rst_ni (rst_ni ),
2717:
2718: // from register interface
2719: .we (in_sent_sent3_we),
2720: .wd (in_sent_sent3_wd),
2721:
2722: // from internal hardware
2723: .de (hw2reg.in_sent[3].de),
2724: .d (hw2reg.in_sent[3].d ),
2725:
2726: // to internal hardware
2727: .qe (),
2728: .q (),
2729:
2730: // to register interface (read)
2731: .qs (in_sent_sent3_qs)
2732: );
2733:
2734:
2735: // F[sent4]: 4:4
2736: prim_subreg #(
2737: .DW (1),
2738: .SWACCESS("W1C"),
2739: .RESVAL (1'h0)
2740: ) u_in_sent_sent4 (
2741: .clk_i (clk_i ),
2742: .rst_ni (rst_ni ),
2743:
2744: // from register interface
2745: .we (in_sent_sent4_we),
2746: .wd (in_sent_sent4_wd),
2747:
2748: // from internal hardware
2749: .de (hw2reg.in_sent[4].de),
2750: .d (hw2reg.in_sent[4].d ),
2751:
2752: // to internal hardware
2753: .qe (),
2754: .q (),
2755:
2756: // to register interface (read)
2757: .qs (in_sent_sent4_qs)
2758: );
2759:
2760:
2761: // F[sent5]: 5:5
2762: prim_subreg #(
2763: .DW (1),
2764: .SWACCESS("W1C"),
2765: .RESVAL (1'h0)
2766: ) u_in_sent_sent5 (
2767: .clk_i (clk_i ),
2768: .rst_ni (rst_ni ),
2769:
2770: // from register interface
2771: .we (in_sent_sent5_we),
2772: .wd (in_sent_sent5_wd),
2773:
2774: // from internal hardware
2775: .de (hw2reg.in_sent[5].de),
2776: .d (hw2reg.in_sent[5].d ),
2777:
2778: // to internal hardware
2779: .qe (),
2780: .q (),
2781:
2782: // to register interface (read)
2783: .qs (in_sent_sent5_qs)
2784: );
2785:
2786:
2787: // F[sent6]: 6:6
2788: prim_subreg #(
2789: .DW (1),
2790: .SWACCESS("W1C"),
2791: .RESVAL (1'h0)
2792: ) u_in_sent_sent6 (
2793: .clk_i (clk_i ),
2794: .rst_ni (rst_ni ),
2795:
2796: // from register interface
2797: .we (in_sent_sent6_we),
2798: .wd (in_sent_sent6_wd),
2799:
2800: // from internal hardware
2801: .de (hw2reg.in_sent[6].de),
2802: .d (hw2reg.in_sent[6].d ),
2803:
2804: // to internal hardware
2805: .qe (),
2806: .q (),
2807:
2808: // to register interface (read)
2809: .qs (in_sent_sent6_qs)
2810: );
2811:
2812:
2813: // F[sent7]: 7:7
2814: prim_subreg #(
2815: .DW (1),
2816: .SWACCESS("W1C"),
2817: .RESVAL (1'h0)
2818: ) u_in_sent_sent7 (
2819: .clk_i (clk_i ),
2820: .rst_ni (rst_ni ),
2821:
2822: // from register interface
2823: .we (in_sent_sent7_we),
2824: .wd (in_sent_sent7_wd),
2825:
2826: // from internal hardware
2827: .de (hw2reg.in_sent[7].de),
2828: .d (hw2reg.in_sent[7].d ),
2829:
2830: // to internal hardware
2831: .qe (),
2832: .q (),
2833:
2834: // to register interface (read)
2835: .qs (in_sent_sent7_qs)
2836: );
2837:
2838:
2839: // F[sent8]: 8:8
2840: prim_subreg #(
2841: .DW (1),
2842: .SWACCESS("W1C"),
2843: .RESVAL (1'h0)
2844: ) u_in_sent_sent8 (
2845: .clk_i (clk_i ),
2846: .rst_ni (rst_ni ),
2847:
2848: // from register interface
2849: .we (in_sent_sent8_we),
2850: .wd (in_sent_sent8_wd),
2851:
2852: // from internal hardware
2853: .de (hw2reg.in_sent[8].de),
2854: .d (hw2reg.in_sent[8].d ),
2855:
2856: // to internal hardware
2857: .qe (),
2858: .q (),
2859:
2860: // to register interface (read)
2861: .qs (in_sent_sent8_qs)
2862: );
2863:
2864:
2865: // F[sent9]: 9:9
2866: prim_subreg #(
2867: .DW (1),
2868: .SWACCESS("W1C"),
2869: .RESVAL (1'h0)
2870: ) u_in_sent_sent9 (
2871: .clk_i (clk_i ),
2872: .rst_ni (rst_ni ),
2873:
2874: // from register interface
2875: .we (in_sent_sent9_we),
2876: .wd (in_sent_sent9_wd),
2877:
2878: // from internal hardware
2879: .de (hw2reg.in_sent[9].de),
2880: .d (hw2reg.in_sent[9].d ),
2881:
2882: // to internal hardware
2883: .qe (),
2884: .q (),
2885:
2886: // to register interface (read)
2887: .qs (in_sent_sent9_qs)
2888: );
2889:
2890:
2891: // F[sent10]: 10:10
2892: prim_subreg #(
2893: .DW (1),
2894: .SWACCESS("W1C"),
2895: .RESVAL (1'h0)
2896: ) u_in_sent_sent10 (
2897: .clk_i (clk_i ),
2898: .rst_ni (rst_ni ),
2899:
2900: // from register interface
2901: .we (in_sent_sent10_we),
2902: .wd (in_sent_sent10_wd),
2903:
2904: // from internal hardware
2905: .de (hw2reg.in_sent[10].de),
2906: .d (hw2reg.in_sent[10].d ),
2907:
2908: // to internal hardware
2909: .qe (),
2910: .q (),
2911:
2912: // to register interface (read)
2913: .qs (in_sent_sent10_qs)
2914: );
2915:
2916:
2917: // F[sent11]: 11:11
2918: prim_subreg #(
2919: .DW (1),
2920: .SWACCESS("W1C"),
2921: .RESVAL (1'h0)
2922: ) u_in_sent_sent11 (
2923: .clk_i (clk_i ),
2924: .rst_ni (rst_ni ),
2925:
2926: // from register interface
2927: .we (in_sent_sent11_we),
2928: .wd (in_sent_sent11_wd),
2929:
2930: // from internal hardware
2931: .de (hw2reg.in_sent[11].de),
2932: .d (hw2reg.in_sent[11].d ),
2933:
2934: // to internal hardware
2935: .qe (),
2936: .q (),
2937:
2938: // to register interface (read)
2939: .qs (in_sent_sent11_qs)
2940: );
2941:
2942:
2943:
2944:
2945: // Subregister 0 of Multireg stall
2946: // R[stall]: V(False)
2947:
2948: // F[stall0]: 0:0
2949: prim_subreg #(
2950: .DW (1),
2951: .SWACCESS("RW"),
2952: .RESVAL (1'h0)
2953: ) u_stall_stall0 (
2954: .clk_i (clk_i ),
2955: .rst_ni (rst_ni ),
2956:
2957: // from register interface
2958: .we (stall_stall0_we),
2959: .wd (stall_stall0_wd),
2960:
2961: // from internal hardware
2962: .de (hw2reg.stall[0].de),
2963: .d (hw2reg.stall[0].d ),
2964:
2965: // to internal hardware
2966: .qe (),
2967: .q (reg2hw.stall[0].q ),
2968:
2969: // to register interface (read)
2970: .qs (stall_stall0_qs)
2971: );
2972:
2973:
2974: // F[stall1]: 1:1
2975: prim_subreg #(
2976: .DW (1),
2977: .SWACCESS("RW"),
2978: .RESVAL (1'h0)
2979: ) u_stall_stall1 (
2980: .clk_i (clk_i ),
2981: .rst_ni (rst_ni ),
2982:
2983: // from register interface
2984: .we (stall_stall1_we),
2985: .wd (stall_stall1_wd),
2986:
2987: // from internal hardware
2988: .de (hw2reg.stall[1].de),
2989: .d (hw2reg.stall[1].d ),
2990:
2991: // to internal hardware
2992: .qe (),
2993: .q (reg2hw.stall[1].q ),
2994:
2995: // to register interface (read)
2996: .qs (stall_stall1_qs)
2997: );
2998:
2999:
3000: // F[stall2]: 2:2
3001: prim_subreg #(
3002: .DW (1),
3003: .SWACCESS("RW"),
3004: .RESVAL (1'h0)
3005: ) u_stall_stall2 (
3006: .clk_i (clk_i ),
3007: .rst_ni (rst_ni ),
3008:
3009: // from register interface
3010: .we (stall_stall2_we),
3011: .wd (stall_stall2_wd),
3012:
3013: // from internal hardware
3014: .de (hw2reg.stall[2].de),
3015: .d (hw2reg.stall[2].d ),
3016:
3017: // to internal hardware
3018: .qe (),
3019: .q (reg2hw.stall[2].q ),
3020:
3021: // to register interface (read)
3022: .qs (stall_stall2_qs)
3023: );
3024:
3025:
3026: // F[stall3]: 3:3
3027: prim_subreg #(
3028: .DW (1),
3029: .SWACCESS("RW"),
3030: .RESVAL (1'h0)
3031: ) u_stall_stall3 (
3032: .clk_i (clk_i ),
3033: .rst_ni (rst_ni ),
3034:
3035: // from register interface
3036: .we (stall_stall3_we),
3037: .wd (stall_stall3_wd),
3038:
3039: // from internal hardware
3040: .de (hw2reg.stall[3].de),
3041: .d (hw2reg.stall[3].d ),
3042:
3043: // to internal hardware
3044: .qe (),
3045: .q (reg2hw.stall[3].q ),
3046:
3047: // to register interface (read)
3048: .qs (stall_stall3_qs)
3049: );
3050:
3051:
3052: // F[stall4]: 4:4
3053: prim_subreg #(
3054: .DW (1),
3055: .SWACCESS("RW"),
3056: .RESVAL (1'h0)
3057: ) u_stall_stall4 (
3058: .clk_i (clk_i ),
3059: .rst_ni (rst_ni ),
3060:
3061: // from register interface
3062: .we (stall_stall4_we),
3063: .wd (stall_stall4_wd),
3064:
3065: // from internal hardware
3066: .de (hw2reg.stall[4].de),
3067: .d (hw2reg.stall[4].d ),
3068:
3069: // to internal hardware
3070: .qe (),
3071: .q (reg2hw.stall[4].q ),
3072:
3073: // to register interface (read)
3074: .qs (stall_stall4_qs)
3075: );
3076:
3077:
3078: // F[stall5]: 5:5
3079: prim_subreg #(
3080: .DW (1),
3081: .SWACCESS("RW"),
3082: .RESVAL (1'h0)
3083: ) u_stall_stall5 (
3084: .clk_i (clk_i ),
3085: .rst_ni (rst_ni ),
3086:
3087: // from register interface
3088: .we (stall_stall5_we),
3089: .wd (stall_stall5_wd),
3090:
3091: // from internal hardware
3092: .de (hw2reg.stall[5].de),
3093: .d (hw2reg.stall[5].d ),
3094:
3095: // to internal hardware
3096: .qe (),
3097: .q (reg2hw.stall[5].q ),
3098:
3099: // to register interface (read)
3100: .qs (stall_stall5_qs)
3101: );
3102:
3103:
3104: // F[stall6]: 6:6
3105: prim_subreg #(
3106: .DW (1),
3107: .SWACCESS("RW"),
3108: .RESVAL (1'h0)
3109: ) u_stall_stall6 (
3110: .clk_i (clk_i ),
3111: .rst_ni (rst_ni ),
3112:
3113: // from register interface
3114: .we (stall_stall6_we),
3115: .wd (stall_stall6_wd),
3116:
3117: // from internal hardware
3118: .de (hw2reg.stall[6].de),
3119: .d (hw2reg.stall[6].d ),
3120:
3121: // to internal hardware
3122: .qe (),
3123: .q (reg2hw.stall[6].q ),
3124:
3125: // to register interface (read)
3126: .qs (stall_stall6_qs)
3127: );
3128:
3129:
3130: // F[stall7]: 7:7
3131: prim_subreg #(
3132: .DW (1),
3133: .SWACCESS("RW"),
3134: .RESVAL (1'h0)
3135: ) u_stall_stall7 (
3136: .clk_i (clk_i ),
3137: .rst_ni (rst_ni ),
3138:
3139: // from register interface
3140: .we (stall_stall7_we),
3141: .wd (stall_stall7_wd),
3142:
3143: // from internal hardware
3144: .de (hw2reg.stall[7].de),
3145: .d (hw2reg.stall[7].d ),
3146:
3147: // to internal hardware
3148: .qe (),
3149: .q (reg2hw.stall[7].q ),
3150:
3151: // to register interface (read)
3152: .qs (stall_stall7_qs)
3153: );
3154:
3155:
3156: // F[stall8]: 8:8
3157: prim_subreg #(
3158: .DW (1),
3159: .SWACCESS("RW"),
3160: .RESVAL (1'h0)
3161: ) u_stall_stall8 (
3162: .clk_i (clk_i ),
3163: .rst_ni (rst_ni ),
3164:
3165: // from register interface
3166: .we (stall_stall8_we),
3167: .wd (stall_stall8_wd),
3168:
3169: // from internal hardware
3170: .de (hw2reg.stall[8].de),
3171: .d (hw2reg.stall[8].d ),
3172:
3173: // to internal hardware
3174: .qe (),
3175: .q (reg2hw.stall[8].q ),
3176:
3177: // to register interface (read)
3178: .qs (stall_stall8_qs)
3179: );
3180:
3181:
3182: // F[stall9]: 9:9
3183: prim_subreg #(
3184: .DW (1),
3185: .SWACCESS("RW"),
3186: .RESVAL (1'h0)
3187: ) u_stall_stall9 (
3188: .clk_i (clk_i ),
3189: .rst_ni (rst_ni ),
3190:
3191: // from register interface
3192: .we (stall_stall9_we),
3193: .wd (stall_stall9_wd),
3194:
3195: // from internal hardware
3196: .de (hw2reg.stall[9].de),
3197: .d (hw2reg.stall[9].d ),
3198:
3199: // to internal hardware
3200: .qe (),
3201: .q (reg2hw.stall[9].q ),
3202:
3203: // to register interface (read)
3204: .qs (stall_stall9_qs)
3205: );
3206:
3207:
3208: // F[stall10]: 10:10
3209: prim_subreg #(
3210: .DW (1),
3211: .SWACCESS("RW"),
3212: .RESVAL (1'h0)
3213: ) u_stall_stall10 (
3214: .clk_i (clk_i ),
3215: .rst_ni (rst_ni ),
3216:
3217: // from register interface
3218: .we (stall_stall10_we),
3219: .wd (stall_stall10_wd),
3220:
3221: // from internal hardware
3222: .de (hw2reg.stall[10].de),
3223: .d (hw2reg.stall[10].d ),
3224:
3225: // to internal hardware
3226: .qe (),
3227: .q (reg2hw.stall[10].q ),
3228:
3229: // to register interface (read)
3230: .qs (stall_stall10_qs)
3231: );
3232:
3233:
3234: // F[stall11]: 11:11
3235: prim_subreg #(
3236: .DW (1),
3237: .SWACCESS("RW"),
3238: .RESVAL (1'h0)
3239: ) u_stall_stall11 (
3240: .clk_i (clk_i ),
3241: .rst_ni (rst_ni ),
3242:
3243: // from register interface
3244: .we (stall_stall11_we),
3245: .wd (stall_stall11_wd),
3246:
3247: // from internal hardware
3248: .de (hw2reg.stall[11].de),
3249: .d (hw2reg.stall[11].d ),
3250:
3251: // to internal hardware
3252: .qe (),
3253: .q (reg2hw.stall[11].q ),
3254:
3255: // to register interface (read)
3256: .qs (stall_stall11_qs)
3257: );
3258:
3259:
3260:
3261:
3262: // Subregister 0 of Multireg configin
3263: // R[configin0]: V(False)
3264:
3265: // F[buffer0]: 4:0
3266: prim_subreg #(
3267: .DW (5),
3268: .SWACCESS("RW"),
3269: .RESVAL (5'h0)
3270: ) u_configin0_buffer0 (
3271: .clk_i (clk_i ),
3272: .rst_ni (rst_ni ),
3273:
3274: // from register interface
3275: .we (configin0_buffer0_we),
3276: .wd (configin0_buffer0_wd),
3277:
3278: // from internal hardware
3279: .de (1'b0),
3280: .d ('0 ),
3281:
3282: // to internal hardware
3283: .qe (),
3284: .q (reg2hw.configin[0].buffer.q ),
3285:
3286: // to register interface (read)
3287: .qs (configin0_buffer0_qs)
3288: );
3289:
3290:
3291: // F[size0]: 14:8
3292: prim_subreg #(
3293: .DW (7),
3294: .SWACCESS("RW"),
3295: .RESVAL (7'h0)
3296: ) u_configin0_size0 (
3297: .clk_i (clk_i ),
3298: .rst_ni (rst_ni ),
3299:
3300: // from register interface
3301: .we (configin0_size0_we),
3302: .wd (configin0_size0_wd),
3303:
3304: // from internal hardware
3305: .de (1'b0),
3306: .d ('0 ),
3307:
3308: // to internal hardware
3309: .qe (),
3310: .q (reg2hw.configin[0].size.q ),
3311:
3312: // to register interface (read)
3313: .qs (configin0_size0_qs)
3314: );
3315:
3316:
3317: // F[pend0]: 30:30
3318: prim_subreg #(
3319: .DW (1),
3320: .SWACCESS("W1C"),
3321: .RESVAL (1'h0)
3322: ) u_configin0_pend0 (
3323: .clk_i (clk_i ),
3324: .rst_ni (rst_ni ),
3325:
3326: // from register interface
3327: .we (configin0_pend0_we),
3328: .wd (configin0_pend0_wd),
3329:
3330: // from internal hardware
3331: .de (hw2reg.configin[0].pend.de),
3332: .d (hw2reg.configin[0].pend.d ),
3333:
3334: // to internal hardware
3335: .qe (),
3336: .q (reg2hw.configin[0].pend.q ),
3337:
3338: // to register interface (read)
3339: .qs (configin0_pend0_qs)
3340: );
3341:
3342:
3343: // F[rdy0]: 31:31
3344: prim_subreg #(
3345: .DW (1),
3346: .SWACCESS("RW"),
3347: .RESVAL (1'h0)
3348: ) u_configin0_rdy0 (
3349: .clk_i (clk_i ),
3350: .rst_ni (rst_ni ),
3351:
3352: // from register interface
3353: .we (configin0_rdy0_we),
3354: .wd (configin0_rdy0_wd),
3355:
3356: // from internal hardware
3357: .de (hw2reg.configin[0].rdy.de),
3358: .d (hw2reg.configin[0].rdy.d ),
3359:
3360: // to internal hardware
3361: .qe (),
3362: .q (reg2hw.configin[0].rdy.q ),
3363:
3364: // to register interface (read)
3365: .qs (configin0_rdy0_qs)
3366: );
3367:
3368:
3369: // Subregister 1 of Multireg configin
3370: // R[configin1]: V(False)
3371:
3372: // F[buffer1]: 4:0
3373: prim_subreg #(
3374: .DW (5),
3375: .SWACCESS("RW"),
3376: .RESVAL (5'h0)
3377: ) u_configin1_buffer1 (
3378: .clk_i (clk_i ),
3379: .rst_ni (rst_ni ),
3380:
3381: // from register interface
3382: .we (configin1_buffer1_we),
3383: .wd (configin1_buffer1_wd),
3384:
3385: // from internal hardware
3386: .de (1'b0),
3387: .d ('0 ),
3388:
3389: // to internal hardware
3390: .qe (),
3391: .q (reg2hw.configin[1].buffer.q ),
3392:
3393: // to register interface (read)
3394: .qs (configin1_buffer1_qs)
3395: );
3396:
3397:
3398: // F[size1]: 14:8
3399: prim_subreg #(
3400: .DW (7),
3401: .SWACCESS("RW"),
3402: .RESVAL (7'h0)
3403: ) u_configin1_size1 (
3404: .clk_i (clk_i ),
3405: .rst_ni (rst_ni ),
3406:
3407: // from register interface
3408: .we (configin1_size1_we),
3409: .wd (configin1_size1_wd),
3410:
3411: // from internal hardware
3412: .de (1'b0),
3413: .d ('0 ),
3414:
3415: // to internal hardware
3416: .qe (),
3417: .q (reg2hw.configin[1].size.q ),
3418:
3419: // to register interface (read)
3420: .qs (configin1_size1_qs)
3421: );
3422:
3423:
3424: // F[pend1]: 30:30
3425: prim_subreg #(
3426: .DW (1),
3427: .SWACCESS("W1C"),
3428: .RESVAL (1'h0)
3429: ) u_configin1_pend1 (
3430: .clk_i (clk_i ),
3431: .rst_ni (rst_ni ),
3432:
3433: // from register interface
3434: .we (configin1_pend1_we),
3435: .wd (configin1_pend1_wd),
3436:
3437: // from internal hardware
3438: .de (hw2reg.configin[1].pend.de),
3439: .d (hw2reg.configin[1].pend.d ),
3440:
3441: // to internal hardware
3442: .qe (),
3443: .q (reg2hw.configin[1].pend.q ),
3444:
3445: // to register interface (read)
3446: .qs (configin1_pend1_qs)
3447: );
3448:
3449:
3450: // F[rdy1]: 31:31
3451: prim_subreg #(
3452: .DW (1),
3453: .SWACCESS("RW"),
3454: .RESVAL (1'h0)
3455: ) u_configin1_rdy1 (
3456: .clk_i (clk_i ),
3457: .rst_ni (rst_ni ),
3458:
3459: // from register interface
3460: .we (configin1_rdy1_we),
3461: .wd (configin1_rdy1_wd),
3462:
3463: // from internal hardware
3464: .de (hw2reg.configin[1].rdy.de),
3465: .d (hw2reg.configin[1].rdy.d ),
3466:
3467: // to internal hardware
3468: .qe (),
3469: .q (reg2hw.configin[1].rdy.q ),
3470:
3471: // to register interface (read)
3472: .qs (configin1_rdy1_qs)
3473: );
3474:
3475:
3476: // Subregister 2 of Multireg configin
3477: // R[configin2]: V(False)
3478:
3479: // F[buffer2]: 4:0
3480: prim_subreg #(
3481: .DW (5),
3482: .SWACCESS("RW"),
3483: .RESVAL (5'h0)
3484: ) u_configin2_buffer2 (
3485: .clk_i (clk_i ),
3486: .rst_ni (rst_ni ),
3487:
3488: // from register interface
3489: .we (configin2_buffer2_we),
3490: .wd (configin2_buffer2_wd),
3491:
3492: // from internal hardware
3493: .de (1'b0),
3494: .d ('0 ),
3495:
3496: // to internal hardware
3497: .qe (),
3498: .q (reg2hw.configin[2].buffer.q ),
3499:
3500: // to register interface (read)
3501: .qs (configin2_buffer2_qs)
3502: );
3503:
3504:
3505: // F[size2]: 14:8
3506: prim_subreg #(
3507: .DW (7),
3508: .SWACCESS("RW"),
3509: .RESVAL (7'h0)
3510: ) u_configin2_size2 (
3511: .clk_i (clk_i ),
3512: .rst_ni (rst_ni ),
3513:
3514: // from register interface
3515: .we (configin2_size2_we),
3516: .wd (configin2_size2_wd),
3517:
3518: // from internal hardware
3519: .de (1'b0),
3520: .d ('0 ),
3521:
3522: // to internal hardware
3523: .qe (),
3524: .q (reg2hw.configin[2].size.q ),
3525:
3526: // to register interface (read)
3527: .qs (configin2_size2_qs)
3528: );
3529:
3530:
3531: // F[pend2]: 30:30
3532: prim_subreg #(
3533: .DW (1),
3534: .SWACCESS("W1C"),
3535: .RESVAL (1'h0)
3536: ) u_configin2_pend2 (
3537: .clk_i (clk_i ),
3538: .rst_ni (rst_ni ),
3539:
3540: // from register interface
3541: .we (configin2_pend2_we),
3542: .wd (configin2_pend2_wd),
3543:
3544: // from internal hardware
3545: .de (hw2reg.configin[2].pend.de),
3546: .d (hw2reg.configin[2].pend.d ),
3547:
3548: // to internal hardware
3549: .qe (),
3550: .q (reg2hw.configin[2].pend.q ),
3551:
3552: // to register interface (read)
3553: .qs (configin2_pend2_qs)
3554: );
3555:
3556:
3557: // F[rdy2]: 31:31
3558: prim_subreg #(
3559: .DW (1),
3560: .SWACCESS("RW"),
3561: .RESVAL (1'h0)
3562: ) u_configin2_rdy2 (
3563: .clk_i (clk_i ),
3564: .rst_ni (rst_ni ),
3565:
3566: // from register interface
3567: .we (configin2_rdy2_we),
3568: .wd (configin2_rdy2_wd),
3569:
3570: // from internal hardware
3571: .de (hw2reg.configin[2].rdy.de),
3572: .d (hw2reg.configin[2].rdy.d ),
3573:
3574: // to internal hardware
3575: .qe (),
3576: .q (reg2hw.configin[2].rdy.q ),
3577:
3578: // to register interface (read)
3579: .qs (configin2_rdy2_qs)
3580: );
3581:
3582:
3583: // Subregister 3 of Multireg configin
3584: // R[configin3]: V(False)
3585:
3586: // F[buffer3]: 4:0
3587: prim_subreg #(
3588: .DW (5),
3589: .SWACCESS("RW"),
3590: .RESVAL (5'h0)
3591: ) u_configin3_buffer3 (
3592: .clk_i (clk_i ),
3593: .rst_ni (rst_ni ),
3594:
3595: // from register interface
3596: .we (configin3_buffer3_we),
3597: .wd (configin3_buffer3_wd),
3598:
3599: // from internal hardware
3600: .de (1'b0),
3601: .d ('0 ),
3602:
3603: // to internal hardware
3604: .qe (),
3605: .q (reg2hw.configin[3].buffer.q ),
3606:
3607: // to register interface (read)
3608: .qs (configin3_buffer3_qs)
3609: );
3610:
3611:
3612: // F[size3]: 14:8
3613: prim_subreg #(
3614: .DW (7),
3615: .SWACCESS("RW"),
3616: .RESVAL (7'h0)
3617: ) u_configin3_size3 (
3618: .clk_i (clk_i ),
3619: .rst_ni (rst_ni ),
3620:
3621: // from register interface
3622: .we (configin3_size3_we),
3623: .wd (configin3_size3_wd),
3624:
3625: // from internal hardware
3626: .de (1'b0),
3627: .d ('0 ),
3628:
3629: // to internal hardware
3630: .qe (),
3631: .q (reg2hw.configin[3].size.q ),
3632:
3633: // to register interface (read)
3634: .qs (configin3_size3_qs)
3635: );
3636:
3637:
3638: // F[pend3]: 30:30
3639: prim_subreg #(
3640: .DW (1),
3641: .SWACCESS("W1C"),
3642: .RESVAL (1'h0)
3643: ) u_configin3_pend3 (
3644: .clk_i (clk_i ),
3645: .rst_ni (rst_ni ),
3646:
3647: // from register interface
3648: .we (configin3_pend3_we),
3649: .wd (configin3_pend3_wd),
3650:
3651: // from internal hardware
3652: .de (hw2reg.configin[3].pend.de),
3653: .d (hw2reg.configin[3].pend.d ),
3654:
3655: // to internal hardware
3656: .qe (),
3657: .q (reg2hw.configin[3].pend.q ),
3658:
3659: // to register interface (read)
3660: .qs (configin3_pend3_qs)
3661: );
3662:
3663:
3664: // F[rdy3]: 31:31
3665: prim_subreg #(
3666: .DW (1),
3667: .SWACCESS("RW"),
3668: .RESVAL (1'h0)
3669: ) u_configin3_rdy3 (
3670: .clk_i (clk_i ),
3671: .rst_ni (rst_ni ),
3672:
3673: // from register interface
3674: .we (configin3_rdy3_we),
3675: .wd (configin3_rdy3_wd),
3676:
3677: // from internal hardware
3678: .de (hw2reg.configin[3].rdy.de),
3679: .d (hw2reg.configin[3].rdy.d ),
3680:
3681: // to internal hardware
3682: .qe (),
3683: .q (reg2hw.configin[3].rdy.q ),
3684:
3685: // to register interface (read)
3686: .qs (configin3_rdy3_qs)
3687: );
3688:
3689:
3690: // Subregister 4 of Multireg configin
3691: // R[configin4]: V(False)
3692:
3693: // F[buffer4]: 4:0
3694: prim_subreg #(
3695: .DW (5),
3696: .SWACCESS("RW"),
3697: .RESVAL (5'h0)
3698: ) u_configin4_buffer4 (
3699: .clk_i (clk_i ),
3700: .rst_ni (rst_ni ),
3701:
3702: // from register interface
3703: .we (configin4_buffer4_we),
3704: .wd (configin4_buffer4_wd),
3705:
3706: // from internal hardware
3707: .de (1'b0),
3708: .d ('0 ),
3709:
3710: // to internal hardware
3711: .qe (),
3712: .q (reg2hw.configin[4].buffer.q ),
3713:
3714: // to register interface (read)
3715: .qs (configin4_buffer4_qs)
3716: );
3717:
3718:
3719: // F[size4]: 14:8
3720: prim_subreg #(
3721: .DW (7),
3722: .SWACCESS("RW"),
3723: .RESVAL (7'h0)
3724: ) u_configin4_size4 (
3725: .clk_i (clk_i ),
3726: .rst_ni (rst_ni ),
3727:
3728: // from register interface
3729: .we (configin4_size4_we),
3730: .wd (configin4_size4_wd),
3731:
3732: // from internal hardware
3733: .de (1'b0),
3734: .d ('0 ),
3735:
3736: // to internal hardware
3737: .qe (),
3738: .q (reg2hw.configin[4].size.q ),
3739:
3740: // to register interface (read)
3741: .qs (configin4_size4_qs)
3742: );
3743:
3744:
3745: // F[pend4]: 30:30
3746: prim_subreg #(
3747: .DW (1),
3748: .SWACCESS("W1C"),
3749: .RESVAL (1'h0)
3750: ) u_configin4_pend4 (
3751: .clk_i (clk_i ),
3752: .rst_ni (rst_ni ),
3753:
3754: // from register interface
3755: .we (configin4_pend4_we),
3756: .wd (configin4_pend4_wd),
3757:
3758: // from internal hardware
3759: .de (hw2reg.configin[4].pend.de),
3760: .d (hw2reg.configin[4].pend.d ),
3761:
3762: // to internal hardware
3763: .qe (),
3764: .q (reg2hw.configin[4].pend.q ),
3765:
3766: // to register interface (read)
3767: .qs (configin4_pend4_qs)
3768: );
3769:
3770:
3771: // F[rdy4]: 31:31
3772: prim_subreg #(
3773: .DW (1),
3774: .SWACCESS("RW"),
3775: .RESVAL (1'h0)
3776: ) u_configin4_rdy4 (
3777: .clk_i (clk_i ),
3778: .rst_ni (rst_ni ),
3779:
3780: // from register interface
3781: .we (configin4_rdy4_we),
3782: .wd (configin4_rdy4_wd),
3783:
3784: // from internal hardware
3785: .de (hw2reg.configin[4].rdy.de),
3786: .d (hw2reg.configin[4].rdy.d ),
3787:
3788: // to internal hardware
3789: .qe (),
3790: .q (reg2hw.configin[4].rdy.q ),
3791:
3792: // to register interface (read)
3793: .qs (configin4_rdy4_qs)
3794: );
3795:
3796:
3797: // Subregister 5 of Multireg configin
3798: // R[configin5]: V(False)
3799:
3800: // F[buffer5]: 4:0
3801: prim_subreg #(
3802: .DW (5),
3803: .SWACCESS("RW"),
3804: .RESVAL (5'h0)
3805: ) u_configin5_buffer5 (
3806: .clk_i (clk_i ),
3807: .rst_ni (rst_ni ),
3808:
3809: // from register interface
3810: .we (configin5_buffer5_we),
3811: .wd (configin5_buffer5_wd),
3812:
3813: // from internal hardware
3814: .de (1'b0),
3815: .d ('0 ),
3816:
3817: // to internal hardware
3818: .qe (),
3819: .q (reg2hw.configin[5].buffer.q ),
3820:
3821: // to register interface (read)
3822: .qs (configin5_buffer5_qs)
3823: );
3824:
3825:
3826: // F[size5]: 14:8
3827: prim_subreg #(
3828: .DW (7),
3829: .SWACCESS("RW"),
3830: .RESVAL (7'h0)
3831: ) u_configin5_size5 (
3832: .clk_i (clk_i ),
3833: .rst_ni (rst_ni ),
3834:
3835: // from register interface
3836: .we (configin5_size5_we),
3837: .wd (configin5_size5_wd),
3838:
3839: // from internal hardware
3840: .de (1'b0),
3841: .d ('0 ),
3842:
3843: // to internal hardware
3844: .qe (),
3845: .q (reg2hw.configin[5].size.q ),
3846:
3847: // to register interface (read)
3848: .qs (configin5_size5_qs)
3849: );
3850:
3851:
3852: // F[pend5]: 30:30
3853: prim_subreg #(
3854: .DW (1),
3855: .SWACCESS("W1C"),
3856: .RESVAL (1'h0)
3857: ) u_configin5_pend5 (
3858: .clk_i (clk_i ),
3859: .rst_ni (rst_ni ),
3860:
3861: // from register interface
3862: .we (configin5_pend5_we),
3863: .wd (configin5_pend5_wd),
3864:
3865: // from internal hardware
3866: .de (hw2reg.configin[5].pend.de),
3867: .d (hw2reg.configin[5].pend.d ),
3868:
3869: // to internal hardware
3870: .qe (),
3871: .q (reg2hw.configin[5].pend.q ),
3872:
3873: // to register interface (read)
3874: .qs (configin5_pend5_qs)
3875: );
3876:
3877:
3878: // F[rdy5]: 31:31
3879: prim_subreg #(
3880: .DW (1),
3881: .SWACCESS("RW"),
3882: .RESVAL (1'h0)
3883: ) u_configin5_rdy5 (
3884: .clk_i (clk_i ),
3885: .rst_ni (rst_ni ),
3886:
3887: // from register interface
3888: .we (configin5_rdy5_we),
3889: .wd (configin5_rdy5_wd),
3890:
3891: // from internal hardware
3892: .de (hw2reg.configin[5].rdy.de),
3893: .d (hw2reg.configin[5].rdy.d ),
3894:
3895: // to internal hardware
3896: .qe (),
3897: .q (reg2hw.configin[5].rdy.q ),
3898:
3899: // to register interface (read)
3900: .qs (configin5_rdy5_qs)
3901: );
3902:
3903:
3904: // Subregister 6 of Multireg configin
3905: // R[configin6]: V(False)
3906:
3907: // F[buffer6]: 4:0
3908: prim_subreg #(
3909: .DW (5),
3910: .SWACCESS("RW"),
3911: .RESVAL (5'h0)
3912: ) u_configin6_buffer6 (
3913: .clk_i (clk_i ),
3914: .rst_ni (rst_ni ),
3915:
3916: // from register interface
3917: .we (configin6_buffer6_we),
3918: .wd (configin6_buffer6_wd),
3919:
3920: // from internal hardware
3921: .de (1'b0),
3922: .d ('0 ),
3923:
3924: // to internal hardware
3925: .qe (),
3926: .q (reg2hw.configin[6].buffer.q ),
3927:
3928: // to register interface (read)
3929: .qs (configin6_buffer6_qs)
3930: );
3931:
3932:
3933: // F[size6]: 14:8
3934: prim_subreg #(
3935: .DW (7),
3936: .SWACCESS("RW"),
3937: .RESVAL (7'h0)
3938: ) u_configin6_size6 (
3939: .clk_i (clk_i ),
3940: .rst_ni (rst_ni ),
3941:
3942: // from register interface
3943: .we (configin6_size6_we),
3944: .wd (configin6_size6_wd),
3945:
3946: // from internal hardware
3947: .de (1'b0),
3948: .d ('0 ),
3949:
3950: // to internal hardware
3951: .qe (),
3952: .q (reg2hw.configin[6].size.q ),
3953:
3954: // to register interface (read)
3955: .qs (configin6_size6_qs)
3956: );
3957:
3958:
3959: // F[pend6]: 30:30
3960: prim_subreg #(
3961: .DW (1),
3962: .SWACCESS("W1C"),
3963: .RESVAL (1'h0)
3964: ) u_configin6_pend6 (
3965: .clk_i (clk_i ),
3966: .rst_ni (rst_ni ),
3967:
3968: // from register interface
3969: .we (configin6_pend6_we),
3970: .wd (configin6_pend6_wd),
3971:
3972: // from internal hardware
3973: .de (hw2reg.configin[6].pend.de),
3974: .d (hw2reg.configin[6].pend.d ),
3975:
3976: // to internal hardware
3977: .qe (),
3978: .q (reg2hw.configin[6].pend.q ),
3979:
3980: // to register interface (read)
3981: .qs (configin6_pend6_qs)
3982: );
3983:
3984:
3985: // F[rdy6]: 31:31
3986: prim_subreg #(
3987: .DW (1),
3988: .SWACCESS("RW"),
3989: .RESVAL (1'h0)
3990: ) u_configin6_rdy6 (
3991: .clk_i (clk_i ),
3992: .rst_ni (rst_ni ),
3993:
3994: // from register interface
3995: .we (configin6_rdy6_we),
3996: .wd (configin6_rdy6_wd),
3997:
3998: // from internal hardware
3999: .de (hw2reg.configin[6].rdy.de),
4000: .d (hw2reg.configin[6].rdy.d ),
4001:
4002: // to internal hardware
4003: .qe (),
4004: .q (reg2hw.configin[6].rdy.q ),
4005:
4006: // to register interface (read)
4007: .qs (configin6_rdy6_qs)
4008: );
4009:
4010:
4011: // Subregister 7 of Multireg configin
4012: // R[configin7]: V(False)
4013:
4014: // F[buffer7]: 4:0
4015: prim_subreg #(
4016: .DW (5),
4017: .SWACCESS("RW"),
4018: .RESVAL (5'h0)
4019: ) u_configin7_buffer7 (
4020: .clk_i (clk_i ),
4021: .rst_ni (rst_ni ),
4022:
4023: // from register interface
4024: .we (configin7_buffer7_we),
4025: .wd (configin7_buffer7_wd),
4026:
4027: // from internal hardware
4028: .de (1'b0),
4029: .d ('0 ),
4030:
4031: // to internal hardware
4032: .qe (),
4033: .q (reg2hw.configin[7].buffer.q ),
4034:
4035: // to register interface (read)
4036: .qs (configin7_buffer7_qs)
4037: );
4038:
4039:
4040: // F[size7]: 14:8
4041: prim_subreg #(
4042: .DW (7),
4043: .SWACCESS("RW"),
4044: .RESVAL (7'h0)
4045: ) u_configin7_size7 (
4046: .clk_i (clk_i ),
4047: .rst_ni (rst_ni ),
4048:
4049: // from register interface
4050: .we (configin7_size7_we),
4051: .wd (configin7_size7_wd),
4052:
4053: // from internal hardware
4054: .de (1'b0),
4055: .d ('0 ),
4056:
4057: // to internal hardware
4058: .qe (),
4059: .q (reg2hw.configin[7].size.q ),
4060:
4061: // to register interface (read)
4062: .qs (configin7_size7_qs)
4063: );
4064:
4065:
4066: // F[pend7]: 30:30
4067: prim_subreg #(
4068: .DW (1),
4069: .SWACCESS("W1C"),
4070: .RESVAL (1'h0)
4071: ) u_configin7_pend7 (
4072: .clk_i (clk_i ),
4073: .rst_ni (rst_ni ),
4074:
4075: // from register interface
4076: .we (configin7_pend7_we),
4077: .wd (configin7_pend7_wd),
4078:
4079: // from internal hardware
4080: .de (hw2reg.configin[7].pend.de),
4081: .d (hw2reg.configin[7].pend.d ),
4082:
4083: // to internal hardware
4084: .qe (),
4085: .q (reg2hw.configin[7].pend.q ),
4086:
4087: // to register interface (read)
4088: .qs (configin7_pend7_qs)
4089: );
4090:
4091:
4092: // F[rdy7]: 31:31
4093: prim_subreg #(
4094: .DW (1),
4095: .SWACCESS("RW"),
4096: .RESVAL (1'h0)
4097: ) u_configin7_rdy7 (
4098: .clk_i (clk_i ),
4099: .rst_ni (rst_ni ),
4100:
4101: // from register interface
4102: .we (configin7_rdy7_we),
4103: .wd (configin7_rdy7_wd),
4104:
4105: // from internal hardware
4106: .de (hw2reg.configin[7].rdy.de),
4107: .d (hw2reg.configin[7].rdy.d ),
4108:
4109: // to internal hardware
4110: .qe (),
4111: .q (reg2hw.configin[7].rdy.q ),
4112:
4113: // to register interface (read)
4114: .qs (configin7_rdy7_qs)
4115: );
4116:
4117:
4118: // Subregister 8 of Multireg configin
4119: // R[configin8]: V(False)
4120:
4121: // F[buffer8]: 4:0
4122: prim_subreg #(
4123: .DW (5),
4124: .SWACCESS("RW"),
4125: .RESVAL (5'h0)
4126: ) u_configin8_buffer8 (
4127: .clk_i (clk_i ),
4128: .rst_ni (rst_ni ),
4129:
4130: // from register interface
4131: .we (configin8_buffer8_we),
4132: .wd (configin8_buffer8_wd),
4133:
4134: // from internal hardware
4135: .de (1'b0),
4136: .d ('0 ),
4137:
4138: // to internal hardware
4139: .qe (),
4140: .q (reg2hw.configin[8].buffer.q ),
4141:
4142: // to register interface (read)
4143: .qs (configin8_buffer8_qs)
4144: );
4145:
4146:
4147: // F[size8]: 14:8
4148: prim_subreg #(
4149: .DW (7),
4150: .SWACCESS("RW"),
4151: .RESVAL (7'h0)
4152: ) u_configin8_size8 (
4153: .clk_i (clk_i ),
4154: .rst_ni (rst_ni ),
4155:
4156: // from register interface
4157: .we (configin8_size8_we),
4158: .wd (configin8_size8_wd),
4159:
4160: // from internal hardware
4161: .de (1'b0),
4162: .d ('0 ),
4163:
4164: // to internal hardware
4165: .qe (),
4166: .q (reg2hw.configin[8].size.q ),
4167:
4168: // to register interface (read)
4169: .qs (configin8_size8_qs)
4170: );
4171:
4172:
4173: // F[pend8]: 30:30
4174: prim_subreg #(
4175: .DW (1),
4176: .SWACCESS("W1C"),
4177: .RESVAL (1'h0)
4178: ) u_configin8_pend8 (
4179: .clk_i (clk_i ),
4180: .rst_ni (rst_ni ),
4181:
4182: // from register interface
4183: .we (configin8_pend8_we),
4184: .wd (configin8_pend8_wd),
4185:
4186: // from internal hardware
4187: .de (hw2reg.configin[8].pend.de),
4188: .d (hw2reg.configin[8].pend.d ),
4189:
4190: // to internal hardware
4191: .qe (),
4192: .q (reg2hw.configin[8].pend.q ),
4193:
4194: // to register interface (read)
4195: .qs (configin8_pend8_qs)
4196: );
4197:
4198:
4199: // F[rdy8]: 31:31
4200: prim_subreg #(
4201: .DW (1),
4202: .SWACCESS("RW"),
4203: .RESVAL (1'h0)
4204: ) u_configin8_rdy8 (
4205: .clk_i (clk_i ),
4206: .rst_ni (rst_ni ),
4207:
4208: // from register interface
4209: .we (configin8_rdy8_we),
4210: .wd (configin8_rdy8_wd),
4211:
4212: // from internal hardware
4213: .de (hw2reg.configin[8].rdy.de),
4214: .d (hw2reg.configin[8].rdy.d ),
4215:
4216: // to internal hardware
4217: .qe (),
4218: .q (reg2hw.configin[8].rdy.q ),
4219:
4220: // to register interface (read)
4221: .qs (configin8_rdy8_qs)
4222: );
4223:
4224:
4225: // Subregister 9 of Multireg configin
4226: // R[configin9]: V(False)
4227:
4228: // F[buffer9]: 4:0
4229: prim_subreg #(
4230: .DW (5),
4231: .SWACCESS("RW"),
4232: .RESVAL (5'h0)
4233: ) u_configin9_buffer9 (
4234: .clk_i (clk_i ),
4235: .rst_ni (rst_ni ),
4236:
4237: // from register interface
4238: .we (configin9_buffer9_we),
4239: .wd (configin9_buffer9_wd),
4240:
4241: // from internal hardware
4242: .de (1'b0),
4243: .d ('0 ),
4244:
4245: // to internal hardware
4246: .qe (),
4247: .q (reg2hw.configin[9].buffer.q ),
4248:
4249: // to register interface (read)
4250: .qs (configin9_buffer9_qs)
4251: );
4252:
4253:
4254: // F[size9]: 14:8
4255: prim_subreg #(
4256: .DW (7),
4257: .SWACCESS("RW"),
4258: .RESVAL (7'h0)
4259: ) u_configin9_size9 (
4260: .clk_i (clk_i ),
4261: .rst_ni (rst_ni ),
4262:
4263: // from register interface
4264: .we (configin9_size9_we),
4265: .wd (configin9_size9_wd),
4266:
4267: // from internal hardware
4268: .de (1'b0),
4269: .d ('0 ),
4270:
4271: // to internal hardware
4272: .qe (),
4273: .q (reg2hw.configin[9].size.q ),
4274:
4275: // to register interface (read)
4276: .qs (configin9_size9_qs)
4277: );
4278:
4279:
4280: // F[pend9]: 30:30
4281: prim_subreg #(
4282: .DW (1),
4283: .SWACCESS("W1C"),
4284: .RESVAL (1'h0)
4285: ) u_configin9_pend9 (
4286: .clk_i (clk_i ),
4287: .rst_ni (rst_ni ),
4288:
4289: // from register interface
4290: .we (configin9_pend9_we),
4291: .wd (configin9_pend9_wd),
4292:
4293: // from internal hardware
4294: .de (hw2reg.configin[9].pend.de),
4295: .d (hw2reg.configin[9].pend.d ),
4296:
4297: // to internal hardware
4298: .qe (),
4299: .q (reg2hw.configin[9].pend.q ),
4300:
4301: // to register interface (read)
4302: .qs (configin9_pend9_qs)
4303: );
4304:
4305:
4306: // F[rdy9]: 31:31
4307: prim_subreg #(
4308: .DW (1),
4309: .SWACCESS("RW"),
4310: .RESVAL (1'h0)
4311: ) u_configin9_rdy9 (
4312: .clk_i (clk_i ),
4313: .rst_ni (rst_ni ),
4314:
4315: // from register interface
4316: .we (configin9_rdy9_we),
4317: .wd (configin9_rdy9_wd),
4318:
4319: // from internal hardware
4320: .de (hw2reg.configin[9].rdy.de),
4321: .d (hw2reg.configin[9].rdy.d ),
4322:
4323: // to internal hardware
4324: .qe (),
4325: .q (reg2hw.configin[9].rdy.q ),
4326:
4327: // to register interface (read)
4328: .qs (configin9_rdy9_qs)
4329: );
4330:
4331:
4332: // Subregister 10 of Multireg configin
4333: // R[configin10]: V(False)
4334:
4335: // F[buffer10]: 4:0
4336: prim_subreg #(
4337: .DW (5),
4338: .SWACCESS("RW"),
4339: .RESVAL (5'h0)
4340: ) u_configin10_buffer10 (
4341: .clk_i (clk_i ),
4342: .rst_ni (rst_ni ),
4343:
4344: // from register interface
4345: .we (configin10_buffer10_we),
4346: .wd (configin10_buffer10_wd),
4347:
4348: // from internal hardware
4349: .de (1'b0),
4350: .d ('0 ),
4351:
4352: // to internal hardware
4353: .qe (),
4354: .q (reg2hw.configin[10].buffer.q ),
4355:
4356: // to register interface (read)
4357: .qs (configin10_buffer10_qs)
4358: );
4359:
4360:
4361: // F[size10]: 14:8
4362: prim_subreg #(
4363: .DW (7),
4364: .SWACCESS("RW"),
4365: .RESVAL (7'h0)
4366: ) u_configin10_size10 (
4367: .clk_i (clk_i ),
4368: .rst_ni (rst_ni ),
4369:
4370: // from register interface
4371: .we (configin10_size10_we),
4372: .wd (configin10_size10_wd),
4373:
4374: // from internal hardware
4375: .de (1'b0),
4376: .d ('0 ),
4377:
4378: // to internal hardware
4379: .qe (),
4380: .q (reg2hw.configin[10].size.q ),
4381:
4382: // to register interface (read)
4383: .qs (configin10_size10_qs)
4384: );
4385:
4386:
4387: // F[pend10]: 30:30
4388: prim_subreg #(
4389: .DW (1),
4390: .SWACCESS("W1C"),
4391: .RESVAL (1'h0)
4392: ) u_configin10_pend10 (
4393: .clk_i (clk_i ),
4394: .rst_ni (rst_ni ),
4395:
4396: // from register interface
4397: .we (configin10_pend10_we),
4398: .wd (configin10_pend10_wd),
4399:
4400: // from internal hardware
4401: .de (hw2reg.configin[10].pend.de),
4402: .d (hw2reg.configin[10].pend.d ),
4403:
4404: // to internal hardware
4405: .qe (),
4406: .q (reg2hw.configin[10].pend.q ),
4407:
4408: // to register interface (read)
4409: .qs (configin10_pend10_qs)
4410: );
4411:
4412:
4413: // F[rdy10]: 31:31
4414: prim_subreg #(
4415: .DW (1),
4416: .SWACCESS("RW"),
4417: .RESVAL (1'h0)
4418: ) u_configin10_rdy10 (
4419: .clk_i (clk_i ),
4420: .rst_ni (rst_ni ),
4421:
4422: // from register interface
4423: .we (configin10_rdy10_we),
4424: .wd (configin10_rdy10_wd),
4425:
4426: // from internal hardware
4427: .de (hw2reg.configin[10].rdy.de),
4428: .d (hw2reg.configin[10].rdy.d ),
4429:
4430: // to internal hardware
4431: .qe (),
4432: .q (reg2hw.configin[10].rdy.q ),
4433:
4434: // to register interface (read)
4435: .qs (configin10_rdy10_qs)
4436: );
4437:
4438:
4439: // Subregister 11 of Multireg configin
4440: // R[configin11]: V(False)
4441:
4442: // F[buffer11]: 4:0
4443: prim_subreg #(
4444: .DW (5),
4445: .SWACCESS("RW"),
4446: .RESVAL (5'h0)
4447: ) u_configin11_buffer11 (
4448: .clk_i (clk_i ),
4449: .rst_ni (rst_ni ),
4450:
4451: // from register interface
4452: .we (configin11_buffer11_we),
4453: .wd (configin11_buffer11_wd),
4454:
4455: // from internal hardware
4456: .de (1'b0),
4457: .d ('0 ),
4458:
4459: // to internal hardware
4460: .qe (),
4461: .q (reg2hw.configin[11].buffer.q ),
4462:
4463: // to register interface (read)
4464: .qs (configin11_buffer11_qs)
4465: );
4466:
4467:
4468: // F[size11]: 14:8
4469: prim_subreg #(
4470: .DW (7),
4471: .SWACCESS("RW"),
4472: .RESVAL (7'h0)
4473: ) u_configin11_size11 (
4474: .clk_i (clk_i ),
4475: .rst_ni (rst_ni ),
4476:
4477: // from register interface
4478: .we (configin11_size11_we),
4479: .wd (configin11_size11_wd),
4480:
4481: // from internal hardware
4482: .de (1'b0),
4483: .d ('0 ),
4484:
4485: // to internal hardware
4486: .qe (),
4487: .q (reg2hw.configin[11].size.q ),
4488:
4489: // to register interface (read)
4490: .qs (configin11_size11_qs)
4491: );
4492:
4493:
4494: // F[pend11]: 30:30
4495: prim_subreg #(
4496: .DW (1),
4497: .SWACCESS("W1C"),
4498: .RESVAL (1'h0)
4499: ) u_configin11_pend11 (
4500: .clk_i (clk_i ),
4501: .rst_ni (rst_ni ),
4502:
4503: // from register interface
4504: .we (configin11_pend11_we),
4505: .wd (configin11_pend11_wd),
4506:
4507: // from internal hardware
4508: .de (hw2reg.configin[11].pend.de),
4509: .d (hw2reg.configin[11].pend.d ),
4510:
4511: // to internal hardware
4512: .qe (),
4513: .q (reg2hw.configin[11].pend.q ),
4514:
4515: // to register interface (read)
4516: .qs (configin11_pend11_qs)
4517: );
4518:
4519:
4520: // F[rdy11]: 31:31
4521: prim_subreg #(
4522: .DW (1),
4523: .SWACCESS("RW"),
4524: .RESVAL (1'h0)
4525: ) u_configin11_rdy11 (
4526: .clk_i (clk_i ),
4527: .rst_ni (rst_ni ),
4528:
4529: // from register interface
4530: .we (configin11_rdy11_we),
4531: .wd (configin11_rdy11_wd),
4532:
4533: // from internal hardware
4534: .de (hw2reg.configin[11].rdy.de),
4535: .d (hw2reg.configin[11].rdy.d ),
4536:
4537: // to internal hardware
4538: .qe (),
4539: .q (reg2hw.configin[11].rdy.q ),
4540:
4541: // to register interface (read)
4542: .qs (configin11_rdy11_qs)
4543: );
4544:
4545:
4546:
4547:
4548: // Subregister 0 of Multireg iso
4549: // R[iso]: V(False)
4550:
4551: // F[iso0]: 0:0
4552: prim_subreg #(
4553: .DW (1),
4554: .SWACCESS("RW"),
4555: .RESVAL (1'h0)
4556: ) u_iso_iso0 (
4557: .clk_i (clk_i ),
4558: .rst_ni (rst_ni ),
4559:
4560: // from register interface
4561: .we (iso_iso0_we),
4562: .wd (iso_iso0_wd),
4563:
4564: // from internal hardware
4565: .de (1'b0),
4566: .d ('0 ),
4567:
4568: // to internal hardware
4569: .qe (),
4570: .q (reg2hw.iso[0].q ),
4571:
4572: // to register interface (read)
4573: .qs (iso_iso0_qs)
4574: );
4575:
4576:
4577: // F[iso1]: 1:1
4578: prim_subreg #(
4579: .DW (1),
4580: .SWACCESS("RW"),
4581: .RESVAL (1'h0)
4582: ) u_iso_iso1 (
4583: .clk_i (clk_i ),
4584: .rst_ni (rst_ni ),
4585:
4586: // from register interface
4587: .we (iso_iso1_we),
4588: .wd (iso_iso1_wd),
4589:
4590: // from internal hardware
4591: .de (1'b0),
4592: .d ('0 ),
4593:
4594: // to internal hardware
4595: .qe (),
4596: .q (reg2hw.iso[1].q ),
4597:
4598: // to register interface (read)
4599: .qs (iso_iso1_qs)
4600: );
4601:
4602:
4603: // F[iso2]: 2:2
4604: prim_subreg #(
4605: .DW (1),
4606: .SWACCESS("RW"),
4607: .RESVAL (1'h0)
4608: ) u_iso_iso2 (
4609: .clk_i (clk_i ),
4610: .rst_ni (rst_ni ),
4611:
4612: // from register interface
4613: .we (iso_iso2_we),
4614: .wd (iso_iso2_wd),
4615:
4616: // from internal hardware
4617: .de (1'b0),
4618: .d ('0 ),
4619:
4620: // to internal hardware
4621: .qe (),
4622: .q (reg2hw.iso[2].q ),
4623:
4624: // to register interface (read)
4625: .qs (iso_iso2_qs)
4626: );
4627:
4628:
4629: // F[iso3]: 3:3
4630: prim_subreg #(
4631: .DW (1),
4632: .SWACCESS("RW"),
4633: .RESVAL (1'h0)
4634: ) u_iso_iso3 (
4635: .clk_i (clk_i ),
4636: .rst_ni (rst_ni ),
4637:
4638: // from register interface
4639: .we (iso_iso3_we),
4640: .wd (iso_iso3_wd),
4641:
4642: // from internal hardware
4643: .de (1'b0),
4644: .d ('0 ),
4645:
4646: // to internal hardware
4647: .qe (),
4648: .q (reg2hw.iso[3].q ),
4649:
4650: // to register interface (read)
4651: .qs (iso_iso3_qs)
4652: );
4653:
4654:
4655: // F[iso4]: 4:4
4656: prim_subreg #(
4657: .DW (1),
4658: .SWACCESS("RW"),
4659: .RESVAL (1'h0)
4660: ) u_iso_iso4 (
4661: .clk_i (clk_i ),
4662: .rst_ni (rst_ni ),
4663:
4664: // from register interface
4665: .we (iso_iso4_we),
4666: .wd (iso_iso4_wd),
4667:
4668: // from internal hardware
4669: .de (1'b0),
4670: .d ('0 ),
4671:
4672: // to internal hardware
4673: .qe (),
4674: .q (reg2hw.iso[4].q ),
4675:
4676: // to register interface (read)
4677: .qs (iso_iso4_qs)
4678: );
4679:
4680:
4681: // F[iso5]: 5:5
4682: prim_subreg #(
4683: .DW (1),
4684: .SWACCESS("RW"),
4685: .RESVAL (1'h0)
4686: ) u_iso_iso5 (
4687: .clk_i (clk_i ),
4688: .rst_ni (rst_ni ),
4689:
4690: // from register interface
4691: .we (iso_iso5_we),
4692: .wd (iso_iso5_wd),
4693:
4694: // from internal hardware
4695: .de (1'b0),
4696: .d ('0 ),
4697:
4698: // to internal hardware
4699: .qe (),
4700: .q (reg2hw.iso[5].q ),
4701:
4702: // to register interface (read)
4703: .qs (iso_iso5_qs)
4704: );
4705:
4706:
4707: // F[iso6]: 6:6
4708: prim_subreg #(
4709: .DW (1),
4710: .SWACCESS("RW"),
4711: .RESVAL (1'h0)
4712: ) u_iso_iso6 (
4713: .clk_i (clk_i ),
4714: .rst_ni (rst_ni ),
4715:
4716: // from register interface
4717: .we (iso_iso6_we),
4718: .wd (iso_iso6_wd),
4719:
4720: // from internal hardware
4721: .de (1'b0),
4722: .d ('0 ),
4723:
4724: // to internal hardware
4725: .qe (),
4726: .q (reg2hw.iso[6].q ),
4727:
4728: // to register interface (read)
4729: .qs (iso_iso6_qs)
4730: );
4731:
4732:
4733: // F[iso7]: 7:7
4734: prim_subreg #(
4735: .DW (1),
4736: .SWACCESS("RW"),
4737: .RESVAL (1'h0)
4738: ) u_iso_iso7 (
4739: .clk_i (clk_i ),
4740: .rst_ni (rst_ni ),
4741:
4742: // from register interface
4743: .we (iso_iso7_we),
4744: .wd (iso_iso7_wd),
4745:
4746: // from internal hardware
4747: .de (1'b0),
4748: .d ('0 ),
4749:
4750: // to internal hardware
4751: .qe (),
4752: .q (reg2hw.iso[7].q ),
4753:
4754: // to register interface (read)
4755: .qs (iso_iso7_qs)
4756: );
4757:
4758:
4759: // F[iso8]: 8:8
4760: prim_subreg #(
4761: .DW (1),
4762: .SWACCESS("RW"),
4763: .RESVAL (1'h0)
4764: ) u_iso_iso8 (
4765: .clk_i (clk_i ),
4766: .rst_ni (rst_ni ),
4767:
4768: // from register interface
4769: .we (iso_iso8_we),
4770: .wd (iso_iso8_wd),
4771:
4772: // from internal hardware
4773: .de (1'b0),
4774: .d ('0 ),
4775:
4776: // to internal hardware
4777: .qe (),
4778: .q (reg2hw.iso[8].q ),
4779:
4780: // to register interface (read)
4781: .qs (iso_iso8_qs)
4782: );
4783:
4784:
4785: // F[iso9]: 9:9
4786: prim_subreg #(
4787: .DW (1),
4788: .SWACCESS("RW"),
4789: .RESVAL (1'h0)
4790: ) u_iso_iso9 (
4791: .clk_i (clk_i ),
4792: .rst_ni (rst_ni ),
4793:
4794: // from register interface
4795: .we (iso_iso9_we),
4796: .wd (iso_iso9_wd),
4797:
4798: // from internal hardware
4799: .de (1'b0),
4800: .d ('0 ),
4801:
4802: // to internal hardware
4803: .qe (),
4804: .q (reg2hw.iso[9].q ),
4805:
4806: // to register interface (read)
4807: .qs (iso_iso9_qs)
4808: );
4809:
4810:
4811: // F[iso10]: 10:10
4812: prim_subreg #(
4813: .DW (1),
4814: .SWACCESS("RW"),
4815: .RESVAL (1'h0)
4816: ) u_iso_iso10 (
4817: .clk_i (clk_i ),
4818: .rst_ni (rst_ni ),
4819:
4820: // from register interface
4821: .we (iso_iso10_we),
4822: .wd (iso_iso10_wd),
4823:
4824: // from internal hardware
4825: .de (1'b0),
4826: .d ('0 ),
4827:
4828: // to internal hardware
4829: .qe (),
4830: .q (reg2hw.iso[10].q ),
4831:
4832: // to register interface (read)
4833: .qs (iso_iso10_qs)
4834: );
4835:
4836:
4837: // F[iso11]: 11:11
4838: prim_subreg #(
4839: .DW (1),
4840: .SWACCESS("RW"),
4841: .RESVAL (1'h0)
4842: ) u_iso_iso11 (
4843: .clk_i (clk_i ),
4844: .rst_ni (rst_ni ),
4845:
4846: // from register interface
4847: .we (iso_iso11_we),
4848: .wd (iso_iso11_wd),
4849:
4850: // from internal hardware
4851: .de (1'b0),
4852: .d ('0 ),
4853:
4854: // to internal hardware
4855: .qe (),
4856: .q (reg2hw.iso[11].q ),
4857:
4858: // to register interface (read)
4859: .qs (iso_iso11_qs)
4860: );
4861:
4862:
4863:
4864:
4865: // Subregister 0 of Multireg data_toggle_clear
4866: // R[data_toggle_clear]: V(False)
4867:
4868: // F[clear0]: 0:0
4869: prim_subreg #(
4870: .DW (1),
4871: .SWACCESS("WO"),
4872: .RESVAL (1'h0)
4873: ) u_data_toggle_clear_clear0 (
4874: .clk_i (clk_i ),
4875: .rst_ni (rst_ni ),
4876:
4877: // from register interface
4878: .we (data_toggle_clear_clear0_we),
4879: .wd (data_toggle_clear_clear0_wd),
4880:
4881: // from internal hardware
4882: .de (1'b0),
4883: .d ('0 ),
4884:
4885: // to internal hardware
4886: .qe (reg2hw.data_toggle_clear[0].qe),
4887: .q (reg2hw.data_toggle_clear[0].q ),
4888:
4889: .qs ()
4890: );
4891:
4892:
4893: // F[clear1]: 1:1
4894: prim_subreg #(
4895: .DW (1),
4896: .SWACCESS("WO"),
4897: .RESVAL (1'h0)
4898: ) u_data_toggle_clear_clear1 (
4899: .clk_i (clk_i ),
4900: .rst_ni (rst_ni ),
4901:
4902: // from register interface
4903: .we (data_toggle_clear_clear1_we),
4904: .wd (data_toggle_clear_clear1_wd),
4905:
4906: // from internal hardware
4907: .de (1'b0),
4908: .d ('0 ),
4909:
4910: // to internal hardware
4911: .qe (reg2hw.data_toggle_clear[1].qe),
4912: .q (reg2hw.data_toggle_clear[1].q ),
4913:
4914: .qs ()
4915: );
4916:
4917:
4918: // F[clear2]: 2:2
4919: prim_subreg #(
4920: .DW (1),
4921: .SWACCESS("WO"),
4922: .RESVAL (1'h0)
4923: ) u_data_toggle_clear_clear2 (
4924: .clk_i (clk_i ),
4925: .rst_ni (rst_ni ),
4926:
4927: // from register interface
4928: .we (data_toggle_clear_clear2_we),
4929: .wd (data_toggle_clear_clear2_wd),
4930:
4931: // from internal hardware
4932: .de (1'b0),
4933: .d ('0 ),
4934:
4935: // to internal hardware
4936: .qe (reg2hw.data_toggle_clear[2].qe),
4937: .q (reg2hw.data_toggle_clear[2].q ),
4938:
4939: .qs ()
4940: );
4941:
4942:
4943: // F[clear3]: 3:3
4944: prim_subreg #(
4945: .DW (1),
4946: .SWACCESS("WO"),
4947: .RESVAL (1'h0)
4948: ) u_data_toggle_clear_clear3 (
4949: .clk_i (clk_i ),
4950: .rst_ni (rst_ni ),
4951:
4952: // from register interface
4953: .we (data_toggle_clear_clear3_we),
4954: .wd (data_toggle_clear_clear3_wd),
4955:
4956: // from internal hardware
4957: .de (1'b0),
4958: .d ('0 ),
4959:
4960: // to internal hardware
4961: .qe (reg2hw.data_toggle_clear[3].qe),
4962: .q (reg2hw.data_toggle_clear[3].q ),
4963:
4964: .qs ()
4965: );
4966:
4967:
4968: // F[clear4]: 4:4
4969: prim_subreg #(
4970: .DW (1),
4971: .SWACCESS("WO"),
4972: .RESVAL (1'h0)
4973: ) u_data_toggle_clear_clear4 (
4974: .clk_i (clk_i ),
4975: .rst_ni (rst_ni ),
4976:
4977: // from register interface
4978: .we (data_toggle_clear_clear4_we),
4979: .wd (data_toggle_clear_clear4_wd),
4980:
4981: // from internal hardware
4982: .de (1'b0),
4983: .d ('0 ),
4984:
4985: // to internal hardware
4986: .qe (reg2hw.data_toggle_clear[4].qe),
4987: .q (reg2hw.data_toggle_clear[4].q ),
4988:
4989: .qs ()
4990: );
4991:
4992:
4993: // F[clear5]: 5:5
4994: prim_subreg #(
4995: .DW (1),
4996: .SWACCESS("WO"),
4997: .RESVAL (1'h0)
4998: ) u_data_toggle_clear_clear5 (
4999: .clk_i (clk_i ),
5000: .rst_ni (rst_ni ),
5001:
5002: // from register interface
5003: .we (data_toggle_clear_clear5_we),
5004: .wd (data_toggle_clear_clear5_wd),
5005:
5006: // from internal hardware
5007: .de (1'b0),
5008: .d ('0 ),
5009:
5010: // to internal hardware
5011: .qe (reg2hw.data_toggle_clear[5].qe),
5012: .q (reg2hw.data_toggle_clear[5].q ),
5013:
5014: .qs ()
5015: );
5016:
5017:
5018: // F[clear6]: 6:6
5019: prim_subreg #(
5020: .DW (1),
5021: .SWACCESS("WO"),
5022: .RESVAL (1'h0)
5023: ) u_data_toggle_clear_clear6 (
5024: .clk_i (clk_i ),
5025: .rst_ni (rst_ni ),
5026:
5027: // from register interface
5028: .we (data_toggle_clear_clear6_we),
5029: .wd (data_toggle_clear_clear6_wd),
5030:
5031: // from internal hardware
5032: .de (1'b0),
5033: .d ('0 ),
5034:
5035: // to internal hardware
5036: .qe (reg2hw.data_toggle_clear[6].qe),
5037: .q (reg2hw.data_toggle_clear[6].q ),
5038:
5039: .qs ()
5040: );
5041:
5042:
5043: // F[clear7]: 7:7
5044: prim_subreg #(
5045: .DW (1),
5046: .SWACCESS("WO"),
5047: .RESVAL (1'h0)
5048: ) u_data_toggle_clear_clear7 (
5049: .clk_i (clk_i ),
5050: .rst_ni (rst_ni ),
5051:
5052: // from register interface
5053: .we (data_toggle_clear_clear7_we),
5054: .wd (data_toggle_clear_clear7_wd),
5055:
5056: // from internal hardware
5057: .de (1'b0),
5058: .d ('0 ),
5059:
5060: // to internal hardware
5061: .qe (reg2hw.data_toggle_clear[7].qe),
5062: .q (reg2hw.data_toggle_clear[7].q ),
5063:
5064: .qs ()
5065: );
5066:
5067:
5068: // F[clear8]: 8:8
5069: prim_subreg #(
5070: .DW (1),
5071: .SWACCESS("WO"),
5072: .RESVAL (1'h0)
5073: ) u_data_toggle_clear_clear8 (
5074: .clk_i (clk_i ),
5075: .rst_ni (rst_ni ),
5076:
5077: // from register interface
5078: .we (data_toggle_clear_clear8_we),
5079: .wd (data_toggle_clear_clear8_wd),
5080:
5081: // from internal hardware
5082: .de (1'b0),
5083: .d ('0 ),
5084:
5085: // to internal hardware
5086: .qe (reg2hw.data_toggle_clear[8].qe),
5087: .q (reg2hw.data_toggle_clear[8].q ),
5088:
5089: .qs ()
5090: );
5091:
5092:
5093: // F[clear9]: 9:9
5094: prim_subreg #(
5095: .DW (1),
5096: .SWACCESS("WO"),
5097: .RESVAL (1'h0)
5098: ) u_data_toggle_clear_clear9 (
5099: .clk_i (clk_i ),
5100: .rst_ni (rst_ni ),
5101:
5102: // from register interface
5103: .we (data_toggle_clear_clear9_we),
5104: .wd (data_toggle_clear_clear9_wd),
5105:
5106: // from internal hardware
5107: .de (1'b0),
5108: .d ('0 ),
5109:
5110: // to internal hardware
5111: .qe (reg2hw.data_toggle_clear[9].qe),
5112: .q (reg2hw.data_toggle_clear[9].q ),
5113:
5114: .qs ()
5115: );
5116:
5117:
5118: // F[clear10]: 10:10
5119: prim_subreg #(
5120: .DW (1),
5121: .SWACCESS("WO"),
5122: .RESVAL (1'h0)
5123: ) u_data_toggle_clear_clear10 (
5124: .clk_i (clk_i ),
5125: .rst_ni (rst_ni ),
5126:
5127: // from register interface
5128: .we (data_toggle_clear_clear10_we),
5129: .wd (data_toggle_clear_clear10_wd),
5130:
5131: // from internal hardware
5132: .de (1'b0),
5133: .d ('0 ),
5134:
5135: // to internal hardware
5136: .qe (reg2hw.data_toggle_clear[10].qe),
5137: .q (reg2hw.data_toggle_clear[10].q ),
5138:
5139: .qs ()
5140: );
5141:
5142:
5143: // F[clear11]: 11:11
5144: prim_subreg #(
5145: .DW (1),
5146: .SWACCESS("WO"),
5147: .RESVAL (1'h0)
5148: ) u_data_toggle_clear_clear11 (
5149: .clk_i (clk_i ),
5150: .rst_ni (rst_ni ),
5151:
5152: // from register interface
5153: .we (data_toggle_clear_clear11_we),
5154: .wd (data_toggle_clear_clear11_wd),
5155:
5156: // from internal hardware
5157: .de (1'b0),
5158: .d ('0 ),
5159:
5160: // to internal hardware
5161: .qe (reg2hw.data_toggle_clear[11].qe),
5162: .q (reg2hw.data_toggle_clear[11].q ),
5163:
5164: .qs ()
5165: );
5166:
5167:
5168:
5169: // R[phy_config]: V(False)
5170:
5171: // F[rx_differential_mode]: 0:0
5172: prim_subreg #(
5173: .DW (1),
5174: .SWACCESS("RW"),
5175: .RESVAL (1'h0)
5176: ) u_phy_config_rx_differential_mode (
5177: .clk_i (clk_i ),
5178: .rst_ni (rst_ni ),
5179:
5180: // from register interface
5181: .we (phy_config_rx_differential_mode_we),
5182: .wd (phy_config_rx_differential_mode_wd),
5183:
5184: // from internal hardware
5185: .de (1'b0),
5186: .d ('0 ),
5187:
5188: // to internal hardware
5189: .qe (),
5190: .q (reg2hw.phy_config.rx_differential_mode.q ),
5191:
5192: // to register interface (read)
5193: .qs (phy_config_rx_differential_mode_qs)
5194: );
5195:
5196:
5197: // F[tx_differential_mode]: 1:1
5198: prim_subreg #(
5199: .DW (1),
5200: .SWACCESS("RW"),
5201: .RESVAL (1'h0)
5202: ) u_phy_config_tx_differential_mode (
5203: .clk_i (clk_i ),
5204: .rst_ni (rst_ni ),
5205:
5206: // from register interface
5207: .we (phy_config_tx_differential_mode_we),
5208: .wd (phy_config_tx_differential_mode_wd),
5209:
5210: // from internal hardware
5211: .de (1'b0),
5212: .d ('0 ),
5213:
5214: // to internal hardware
5215: .qe (),
5216: .q (reg2hw.phy_config.tx_differential_mode.q ),
5217:
5218: // to register interface (read)
5219: .qs (phy_config_tx_differential_mode_qs)
5220: );
5221:
5222:
5223: // F[eop_single_bit]: 2:2
5224: prim_subreg #(
5225: .DW (1),
5226: .SWACCESS("RW"),
5227: .RESVAL (1'h1)
5228: ) u_phy_config_eop_single_bit (
5229: .clk_i (clk_i ),
5230: .rst_ni (rst_ni ),
5231:
5232: // from register interface
5233: .we (phy_config_eop_single_bit_we),
5234: .wd (phy_config_eop_single_bit_wd),
5235:
5236: // from internal hardware
5237: .de (1'b0),
5238: .d ('0 ),
5239:
5240: // to internal hardware
5241: .qe (),
5242: .q (reg2hw.phy_config.eop_single_bit.q ),
5243:
5244: // to register interface (read)
5245: .qs (phy_config_eop_single_bit_qs)
5246: );
5247:
5248:
5249: // F[override_pwr_sense_en]: 3:3
5250: prim_subreg #(
5251: .DW (1),
5252: .SWACCESS("RW"),
5253: .RESVAL (1'h0)
5254: ) u_phy_config_override_pwr_sense_en (
5255: .clk_i (clk_i ),
5256: .rst_ni (rst_ni ),
5257:
5258: // from register interface
5259: .we (phy_config_override_pwr_sense_en_we),
5260: .wd (phy_config_override_pwr_sense_en_wd),
5261:
5262: // from internal hardware
5263: .de (1'b0),
5264: .d ('0 ),
5265:
5266: // to internal hardware
5267: .qe (),
5268: .q (reg2hw.phy_config.override_pwr_sense_en.q ),
5269:
5270: // to register interface (read)
5271: .qs (phy_config_override_pwr_sense_en_qs)
5272: );
5273:
5274:
5275: // F[override_pwr_sense_val]: 4:4
5276: prim_subreg #(
5277: .DW (1),
5278: .SWACCESS("RW"),
5279: .RESVAL (1'h0)
5280: ) u_phy_config_override_pwr_sense_val (
5281: .clk_i (clk_i ),
5282: .rst_ni (rst_ni ),
5283:
5284: // from register interface
5285: .we (phy_config_override_pwr_sense_val_we),
5286: .wd (phy_config_override_pwr_sense_val_wd),
5287:
5288: // from internal hardware
5289: .de (1'b0),
5290: .d ('0 ),
5291:
5292: // to internal hardware
5293: .qe (),
5294: .q (reg2hw.phy_config.override_pwr_sense_val.q ),
5295:
5296: // to register interface (read)
5297: .qs (phy_config_override_pwr_sense_val_qs)
5298: );
5299:
5300:
5301: // F[pinflip]: 5:5
5302: prim_subreg #(
5303: .DW (1),
5304: .SWACCESS("RW"),
5305: .RESVAL (1'h0)
5306: ) u_phy_config_pinflip (
5307: .clk_i (clk_i ),
5308: .rst_ni (rst_ni ),
5309:
5310: // from register interface
5311: .we (phy_config_pinflip_we),
5312: .wd (phy_config_pinflip_wd),
5313:
5314: // from internal hardware
5315: .de (1'b0),
5316: .d ('0 ),
5317:
5318: // to internal hardware
5319: .qe (),
5320: .q (reg2hw.phy_config.pinflip.q ),
5321:
5322: // to register interface (read)
5323: .qs (phy_config_pinflip_qs)
5324: );
5325:
5326:
5327: // F[usb_ref_disable]: 6:6
5328: prim_subreg #(
5329: .DW (1),
5330: .SWACCESS("RW"),
5331: .RESVAL (1'h0)
5332: ) u_phy_config_usb_ref_disable (
5333: .clk_i (clk_i ),
5334: .rst_ni (rst_ni ),
5335:
5336: // from register interface
5337: .we (phy_config_usb_ref_disable_we),
5338: .wd (phy_config_usb_ref_disable_wd),
5339:
5340: // from internal hardware
5341: .de (1'b0),
5342: .d ('0 ),
5343:
5344: // to internal hardware
5345: .qe (),
5346: .q (reg2hw.phy_config.usb_ref_disable.q ),
5347:
5348: // to register interface (read)
5349: .qs (phy_config_usb_ref_disable_qs)
5350: );
5351:
5352:
5353:
5354:
5355: logic [25:0] addr_hit;
5356: always_comb begin
5357: addr_hit = '0;
5358: addr_hit[ 0] = (reg_addr == USBDEV_INTR_STATE_OFFSET);
5359: addr_hit[ 1] = (reg_addr == USBDEV_INTR_ENABLE_OFFSET);
5360: addr_hit[ 2] = (reg_addr == USBDEV_INTR_TEST_OFFSET);
5361: addr_hit[ 3] = (reg_addr == USBDEV_USBCTRL_OFFSET);
5362: addr_hit[ 4] = (reg_addr == USBDEV_USBSTAT_OFFSET);
5363: addr_hit[ 5] = (reg_addr == USBDEV_AVBUFFER_OFFSET);
5364: addr_hit[ 6] = (reg_addr == USBDEV_RXFIFO_OFFSET);
5365: addr_hit[ 7] = (reg_addr == USBDEV_RXENABLE_SETUP_OFFSET);
5366: addr_hit[ 8] = (reg_addr == USBDEV_RXENABLE_OUT_OFFSET);
5367: addr_hit[ 9] = (reg_addr == USBDEV_IN_SENT_OFFSET);
5368: addr_hit[10] = (reg_addr == USBDEV_STALL_OFFSET);
5369: addr_hit[11] = (reg_addr == USBDEV_CONFIGIN0_OFFSET);
5370: addr_hit[12] = (reg_addr == USBDEV_CONFIGIN1_OFFSET);
5371: addr_hit[13] = (reg_addr == USBDEV_CONFIGIN2_OFFSET);
5372: addr_hit[14] = (reg_addr == USBDEV_CONFIGIN3_OFFSET);
5373: addr_hit[15] = (reg_addr == USBDEV_CONFIGIN4_OFFSET);
5374: addr_hit[16] = (reg_addr == USBDEV_CONFIGIN5_OFFSET);
5375: addr_hit[17] = (reg_addr == USBDEV_CONFIGIN6_OFFSET);
5376: addr_hit[18] = (reg_addr == USBDEV_CONFIGIN7_OFFSET);
5377: addr_hit[19] = (reg_addr == USBDEV_CONFIGIN8_OFFSET);
5378: addr_hit[20] = (reg_addr == USBDEV_CONFIGIN9_OFFSET);
5379: addr_hit[21] = (reg_addr == USBDEV_CONFIGIN10_OFFSET);
5380: addr_hit[22] = (reg_addr == USBDEV_CONFIGIN11_OFFSET);
5381: addr_hit[23] = (reg_addr == USBDEV_ISO_OFFSET);
5382: addr_hit[24] = (reg_addr == USBDEV_DATA_TOGGLE_CLEAR_OFFSET);
5383: addr_hit[25] = (reg_addr == USBDEV_PHY_CONFIG_OFFSET);
5384: end
5385:
5386: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
5387:
5388: // Check sub-word write is permitted
5389: always_comb begin
5390: wr_err = 1'b0;
5391: if (addr_hit[ 0] && reg_we && (USBDEV_PERMIT[ 0] != (USBDEV_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
5392: if (addr_hit[ 1] && reg_we && (USBDEV_PERMIT[ 1] != (USBDEV_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
5393: if (addr_hit[ 2] && reg_we && (USBDEV_PERMIT[ 2] != (USBDEV_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
5394: if (addr_hit[ 3] && reg_we && (USBDEV_PERMIT[ 3] != (USBDEV_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
5395: if (addr_hit[ 4] && reg_we && (USBDEV_PERMIT[ 4] != (USBDEV_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
5396: if (addr_hit[ 5] && reg_we && (USBDEV_PERMIT[ 5] != (USBDEV_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
5397: if (addr_hit[ 6] && reg_we && (USBDEV_PERMIT[ 6] != (USBDEV_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
5398: if (addr_hit[ 7] && reg_we && (USBDEV_PERMIT[ 7] != (USBDEV_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
5399: if (addr_hit[ 8] && reg_we && (USBDEV_PERMIT[ 8] != (USBDEV_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
5400: if (addr_hit[ 9] && reg_we && (USBDEV_PERMIT[ 9] != (USBDEV_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
5401: if (addr_hit[10] && reg_we && (USBDEV_PERMIT[10] != (USBDEV_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
5402: if (addr_hit[11] && reg_we && (USBDEV_PERMIT[11] != (USBDEV_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
5403: if (addr_hit[12] && reg_we && (USBDEV_PERMIT[12] != (USBDEV_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
5404: if (addr_hit[13] && reg_we && (USBDEV_PERMIT[13] != (USBDEV_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
5405: if (addr_hit[14] && reg_we && (USBDEV_PERMIT[14] != (USBDEV_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
5406: if (addr_hit[15] && reg_we && (USBDEV_PERMIT[15] != (USBDEV_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
5407: if (addr_hit[16] && reg_we && (USBDEV_PERMIT[16] != (USBDEV_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
5408: if (addr_hit[17] && reg_we && (USBDEV_PERMIT[17] != (USBDEV_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
5409: if (addr_hit[18] && reg_we && (USBDEV_PERMIT[18] != (USBDEV_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
5410: if (addr_hit[19] && reg_we && (USBDEV_PERMIT[19] != (USBDEV_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
5411: if (addr_hit[20] && reg_we && (USBDEV_PERMIT[20] != (USBDEV_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
5412: if (addr_hit[21] && reg_we && (USBDEV_PERMIT[21] != (USBDEV_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
5413: if (addr_hit[22] && reg_we && (USBDEV_PERMIT[22] != (USBDEV_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
5414: if (addr_hit[23] && reg_we && (USBDEV_PERMIT[23] != (USBDEV_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
5415: if (addr_hit[24] && reg_we && (USBDEV_PERMIT[24] != (USBDEV_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
5416: if (addr_hit[25] && reg_we && (USBDEV_PERMIT[25] != (USBDEV_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
5417: end
5418:
5419: assign intr_state_pkt_received_we = addr_hit[0] & reg_we & ~wr_err;
5420: assign intr_state_pkt_received_wd = reg_wdata[0];
5421:
5422: assign intr_state_pkt_sent_we = addr_hit[0] & reg_we & ~wr_err;
5423: assign intr_state_pkt_sent_wd = reg_wdata[1];
5424:
5425: assign intr_state_disconnected_we = addr_hit[0] & reg_we & ~wr_err;
5426: assign intr_state_disconnected_wd = reg_wdata[2];
5427:
5428: assign intr_state_host_lost_we = addr_hit[0] & reg_we & ~wr_err;
5429: assign intr_state_host_lost_wd = reg_wdata[3];
5430:
5431: assign intr_state_link_reset_we = addr_hit[0] & reg_we & ~wr_err;
5432: assign intr_state_link_reset_wd = reg_wdata[4];
5433:
5434: assign intr_state_link_suspend_we = addr_hit[0] & reg_we & ~wr_err;
5435: assign intr_state_link_suspend_wd = reg_wdata[5];
5436:
5437: assign intr_state_link_resume_we = addr_hit[0] & reg_we & ~wr_err;
5438: assign intr_state_link_resume_wd = reg_wdata[6];
5439:
5440: assign intr_state_av_empty_we = addr_hit[0] & reg_we & ~wr_err;
5441: assign intr_state_av_empty_wd = reg_wdata[7];
5442:
5443: assign intr_state_rx_full_we = addr_hit[0] & reg_we & ~wr_err;
5444: assign intr_state_rx_full_wd = reg_wdata[8];
5445:
5446: assign intr_state_av_overflow_we = addr_hit[0] & reg_we & ~wr_err;
5447: assign intr_state_av_overflow_wd = reg_wdata[9];
5448:
5449: assign intr_state_link_in_err_we = addr_hit[0] & reg_we & ~wr_err;
5450: assign intr_state_link_in_err_wd = reg_wdata[10];
5451:
5452: assign intr_state_rx_crc_err_we = addr_hit[0] & reg_we & ~wr_err;
5453: assign intr_state_rx_crc_err_wd = reg_wdata[11];
5454:
5455: assign intr_state_rx_pid_err_we = addr_hit[0] & reg_we & ~wr_err;
5456: assign intr_state_rx_pid_err_wd = reg_wdata[12];
5457:
5458: assign intr_state_rx_bitstuff_err_we = addr_hit[0] & reg_we & ~wr_err;
5459: assign intr_state_rx_bitstuff_err_wd = reg_wdata[13];
5460:
5461: assign intr_state_frame_we = addr_hit[0] & reg_we & ~wr_err;
5462: assign intr_state_frame_wd = reg_wdata[14];
5463:
5464: assign intr_state_connected_we = addr_hit[0] & reg_we & ~wr_err;
5465: assign intr_state_connected_wd = reg_wdata[15];
5466:
5467: assign intr_enable_pkt_received_we = addr_hit[1] & reg_we & ~wr_err;
5468: assign intr_enable_pkt_received_wd = reg_wdata[0];
5469:
5470: assign intr_enable_pkt_sent_we = addr_hit[1] & reg_we & ~wr_err;
5471: assign intr_enable_pkt_sent_wd = reg_wdata[1];
5472:
5473: assign intr_enable_disconnected_we = addr_hit[1] & reg_we & ~wr_err;
5474: assign intr_enable_disconnected_wd = reg_wdata[2];
5475:
5476: assign intr_enable_host_lost_we = addr_hit[1] & reg_we & ~wr_err;
5477: assign intr_enable_host_lost_wd = reg_wdata[3];
5478:
5479: assign intr_enable_link_reset_we = addr_hit[1] & reg_we & ~wr_err;
5480: assign intr_enable_link_reset_wd = reg_wdata[4];
5481:
5482: assign intr_enable_link_suspend_we = addr_hit[1] & reg_we & ~wr_err;
5483: assign intr_enable_link_suspend_wd = reg_wdata[5];
5484:
5485: assign intr_enable_link_resume_we = addr_hit[1] & reg_we & ~wr_err;
5486: assign intr_enable_link_resume_wd = reg_wdata[6];
5487:
5488: assign intr_enable_av_empty_we = addr_hit[1] & reg_we & ~wr_err;
5489: assign intr_enable_av_empty_wd = reg_wdata[7];
5490:
5491: assign intr_enable_rx_full_we = addr_hit[1] & reg_we & ~wr_err;
5492: assign intr_enable_rx_full_wd = reg_wdata[8];
5493:
5494: assign intr_enable_av_overflow_we = addr_hit[1] & reg_we & ~wr_err;
5495: assign intr_enable_av_overflow_wd = reg_wdata[9];
5496:
5497: assign intr_enable_link_in_err_we = addr_hit[1] & reg_we & ~wr_err;
5498: assign intr_enable_link_in_err_wd = reg_wdata[10];
5499:
5500: assign intr_enable_rx_crc_err_we = addr_hit[1] & reg_we & ~wr_err;
5501: assign intr_enable_rx_crc_err_wd = reg_wdata[11];
5502:
5503: assign intr_enable_rx_pid_err_we = addr_hit[1] & reg_we & ~wr_err;
5504: assign intr_enable_rx_pid_err_wd = reg_wdata[12];
5505:
5506: assign intr_enable_rx_bitstuff_err_we = addr_hit[1] & reg_we & ~wr_err;
5507: assign intr_enable_rx_bitstuff_err_wd = reg_wdata[13];
5508:
5509: assign intr_enable_frame_we = addr_hit[1] & reg_we & ~wr_err;
5510: assign intr_enable_frame_wd = reg_wdata[14];
5511:
5512: assign intr_enable_connected_we = addr_hit[1] & reg_we & ~wr_err;
5513: assign intr_enable_connected_wd = reg_wdata[15];
5514:
5515: assign intr_test_pkt_received_we = addr_hit[2] & reg_we & ~wr_err;
5516: assign intr_test_pkt_received_wd = reg_wdata[0];
5517:
5518: assign intr_test_pkt_sent_we = addr_hit[2] & reg_we & ~wr_err;
5519: assign intr_test_pkt_sent_wd = reg_wdata[1];
5520:
5521: assign intr_test_disconnected_we = addr_hit[2] & reg_we & ~wr_err;
5522: assign intr_test_disconnected_wd = reg_wdata[2];
5523:
5524: assign intr_test_host_lost_we = addr_hit[2] & reg_we & ~wr_err;
5525: assign intr_test_host_lost_wd = reg_wdata[3];
5526:
5527: assign intr_test_link_reset_we = addr_hit[2] & reg_we & ~wr_err;
5528: assign intr_test_link_reset_wd = reg_wdata[4];
5529:
5530: assign intr_test_link_suspend_we = addr_hit[2] & reg_we & ~wr_err;
5531: assign intr_test_link_suspend_wd = reg_wdata[5];
5532:
5533: assign intr_test_link_resume_we = addr_hit[2] & reg_we & ~wr_err;
5534: assign intr_test_link_resume_wd = reg_wdata[6];
5535:
5536: assign intr_test_av_empty_we = addr_hit[2] & reg_we & ~wr_err;
5537: assign intr_test_av_empty_wd = reg_wdata[7];
5538:
5539: assign intr_test_rx_full_we = addr_hit[2] & reg_we & ~wr_err;
5540: assign intr_test_rx_full_wd = reg_wdata[8];
5541:
5542: assign intr_test_av_overflow_we = addr_hit[2] & reg_we & ~wr_err;
5543: assign intr_test_av_overflow_wd = reg_wdata[9];
5544:
5545: assign intr_test_link_in_err_we = addr_hit[2] & reg_we & ~wr_err;
5546: assign intr_test_link_in_err_wd = reg_wdata[10];
5547:
5548: assign intr_test_rx_crc_err_we = addr_hit[2] & reg_we & ~wr_err;
5549: assign intr_test_rx_crc_err_wd = reg_wdata[11];
5550:
5551: assign intr_test_rx_pid_err_we = addr_hit[2] & reg_we & ~wr_err;
5552: assign intr_test_rx_pid_err_wd = reg_wdata[12];
5553:
5554: assign intr_test_rx_bitstuff_err_we = addr_hit[2] & reg_we & ~wr_err;
5555: assign intr_test_rx_bitstuff_err_wd = reg_wdata[13];
5556:
5557: assign intr_test_frame_we = addr_hit[2] & reg_we & ~wr_err;
5558: assign intr_test_frame_wd = reg_wdata[14];
5559:
5560: assign intr_test_connected_we = addr_hit[2] & reg_we & ~wr_err;
5561: assign intr_test_connected_wd = reg_wdata[15];
5562:
5563: assign usbctrl_enable_we = addr_hit[3] & reg_we & ~wr_err;
5564: assign usbctrl_enable_wd = reg_wdata[0];
5565:
5566: assign usbctrl_device_address_we = addr_hit[3] & reg_we & ~wr_err;
5567: assign usbctrl_device_address_wd = reg_wdata[22:16];
5568:
5569: assign usbstat_frame_re = addr_hit[4] && reg_re;
5570:
5571: assign usbstat_host_lost_re = addr_hit[4] && reg_re;
5572:
5573: assign usbstat_link_state_re = addr_hit[4] && reg_re;
5574:
5575: assign usbstat_sense_re = addr_hit[4] && reg_re;
5576:
5577: assign usbstat_av_depth_re = addr_hit[4] && reg_re;
5578:
5579: assign usbstat_av_full_re = addr_hit[4] && reg_re;
5580:
5581: assign usbstat_rx_depth_re = addr_hit[4] && reg_re;
5582:
5583: assign usbstat_rx_empty_re = addr_hit[4] && reg_re;
5584:
5585: assign avbuffer_we = addr_hit[5] & reg_we & ~wr_err;
5586: assign avbuffer_wd = reg_wdata[4:0];
5587:
5588: assign rxfifo_buffer_re = addr_hit[6] && reg_re;
5589:
5590: assign rxfifo_size_re = addr_hit[6] && reg_re;
5591:
5592: assign rxfifo_setup_re = addr_hit[6] && reg_re;
5593:
5594: assign rxfifo_ep_re = addr_hit[6] && reg_re;
5595:
5596: assign rxenable_setup_setup0_we = addr_hit[7] & reg_we & ~wr_err;
5597: assign rxenable_setup_setup0_wd = reg_wdata[0];
5598:
5599: assign rxenable_setup_setup1_we = addr_hit[7] & reg_we & ~wr_err;
5600: assign rxenable_setup_setup1_wd = reg_wdata[1];
5601:
5602: assign rxenable_setup_setup2_we = addr_hit[7] & reg_we & ~wr_err;
5603: assign rxenable_setup_setup2_wd = reg_wdata[2];
5604:
5605: assign rxenable_setup_setup3_we = addr_hit[7] & reg_we & ~wr_err;
5606: assign rxenable_setup_setup3_wd = reg_wdata[3];
5607:
5608: assign rxenable_setup_setup4_we = addr_hit[7] & reg_we & ~wr_err;
5609: assign rxenable_setup_setup4_wd = reg_wdata[4];
5610:
5611: assign rxenable_setup_setup5_we = addr_hit[7] & reg_we & ~wr_err;
5612: assign rxenable_setup_setup5_wd = reg_wdata[5];
5613:
5614: assign rxenable_setup_setup6_we = addr_hit[7] & reg_we & ~wr_err;
5615: assign rxenable_setup_setup6_wd = reg_wdata[6];
5616:
5617: assign rxenable_setup_setup7_we = addr_hit[7] & reg_we & ~wr_err;
5618: assign rxenable_setup_setup7_wd = reg_wdata[7];
5619:
5620: assign rxenable_setup_setup8_we = addr_hit[7] & reg_we & ~wr_err;
5621: assign rxenable_setup_setup8_wd = reg_wdata[8];
5622:
5623: assign rxenable_setup_setup9_we = addr_hit[7] & reg_we & ~wr_err;
5624: assign rxenable_setup_setup9_wd = reg_wdata[9];
5625:
5626: assign rxenable_setup_setup10_we = addr_hit[7] & reg_we & ~wr_err;
5627: assign rxenable_setup_setup10_wd = reg_wdata[10];
5628:
5629: assign rxenable_setup_setup11_we = addr_hit[7] & reg_we & ~wr_err;
5630: assign rxenable_setup_setup11_wd = reg_wdata[11];
5631:
5632: assign rxenable_out_out0_we = addr_hit[8] & reg_we & ~wr_err;
5633: assign rxenable_out_out0_wd = reg_wdata[0];
5634:
5635: assign rxenable_out_out1_we = addr_hit[8] & reg_we & ~wr_err;
5636: assign rxenable_out_out1_wd = reg_wdata[1];
5637:
5638: assign rxenable_out_out2_we = addr_hit[8] & reg_we & ~wr_err;
5639: assign rxenable_out_out2_wd = reg_wdata[2];
5640:
5641: assign rxenable_out_out3_we = addr_hit[8] & reg_we & ~wr_err;
5642: assign rxenable_out_out3_wd = reg_wdata[3];
5643:
5644: assign rxenable_out_out4_we = addr_hit[8] & reg_we & ~wr_err;
5645: assign rxenable_out_out4_wd = reg_wdata[4];
5646:
5647: assign rxenable_out_out5_we = addr_hit[8] & reg_we & ~wr_err;
5648: assign rxenable_out_out5_wd = reg_wdata[5];
5649:
5650: assign rxenable_out_out6_we = addr_hit[8] & reg_we & ~wr_err;
5651: assign rxenable_out_out6_wd = reg_wdata[6];
5652:
5653: assign rxenable_out_out7_we = addr_hit[8] & reg_we & ~wr_err;
5654: assign rxenable_out_out7_wd = reg_wdata[7];
5655:
5656: assign rxenable_out_out8_we = addr_hit[8] & reg_we & ~wr_err;
5657: assign rxenable_out_out8_wd = reg_wdata[8];
5658:
5659: assign rxenable_out_out9_we = addr_hit[8] & reg_we & ~wr_err;
5660: assign rxenable_out_out9_wd = reg_wdata[9];
5661:
5662: assign rxenable_out_out10_we = addr_hit[8] & reg_we & ~wr_err;
5663: assign rxenable_out_out10_wd = reg_wdata[10];
5664:
5665: assign rxenable_out_out11_we = addr_hit[8] & reg_we & ~wr_err;
5666: assign rxenable_out_out11_wd = reg_wdata[11];
5667:
5668: assign in_sent_sent0_we = addr_hit[9] & reg_we & ~wr_err;
5669: assign in_sent_sent0_wd = reg_wdata[0];
5670:
5671: assign in_sent_sent1_we = addr_hit[9] & reg_we & ~wr_err;
5672: assign in_sent_sent1_wd = reg_wdata[1];
5673:
5674: assign in_sent_sent2_we = addr_hit[9] & reg_we & ~wr_err;
5675: assign in_sent_sent2_wd = reg_wdata[2];
5676:
5677: assign in_sent_sent3_we = addr_hit[9] & reg_we & ~wr_err;
5678: assign in_sent_sent3_wd = reg_wdata[3];
5679:
5680: assign in_sent_sent4_we = addr_hit[9] & reg_we & ~wr_err;
5681: assign in_sent_sent4_wd = reg_wdata[4];
5682:
5683: assign in_sent_sent5_we = addr_hit[9] & reg_we & ~wr_err;
5684: assign in_sent_sent5_wd = reg_wdata[5];
5685:
5686: assign in_sent_sent6_we = addr_hit[9] & reg_we & ~wr_err;
5687: assign in_sent_sent6_wd = reg_wdata[6];
5688:
5689: assign in_sent_sent7_we = addr_hit[9] & reg_we & ~wr_err;
5690: assign in_sent_sent7_wd = reg_wdata[7];
5691:
5692: assign in_sent_sent8_we = addr_hit[9] & reg_we & ~wr_err;
5693: assign in_sent_sent8_wd = reg_wdata[8];
5694:
5695: assign in_sent_sent9_we = addr_hit[9] & reg_we & ~wr_err;
5696: assign in_sent_sent9_wd = reg_wdata[9];
5697:
5698: assign in_sent_sent10_we = addr_hit[9] & reg_we & ~wr_err;
5699: assign in_sent_sent10_wd = reg_wdata[10];
5700:
5701: assign in_sent_sent11_we = addr_hit[9] & reg_we & ~wr_err;
5702: assign in_sent_sent11_wd = reg_wdata[11];
5703:
5704: assign stall_stall0_we = addr_hit[10] & reg_we & ~wr_err;
5705: assign stall_stall0_wd = reg_wdata[0];
5706:
5707: assign stall_stall1_we = addr_hit[10] & reg_we & ~wr_err;
5708: assign stall_stall1_wd = reg_wdata[1];
5709:
5710: assign stall_stall2_we = addr_hit[10] & reg_we & ~wr_err;
5711: assign stall_stall2_wd = reg_wdata[2];
5712:
5713: assign stall_stall3_we = addr_hit[10] & reg_we & ~wr_err;
5714: assign stall_stall3_wd = reg_wdata[3];
5715:
5716: assign stall_stall4_we = addr_hit[10] & reg_we & ~wr_err;
5717: assign stall_stall4_wd = reg_wdata[4];
5718:
5719: assign stall_stall5_we = addr_hit[10] & reg_we & ~wr_err;
5720: assign stall_stall5_wd = reg_wdata[5];
5721:
5722: assign stall_stall6_we = addr_hit[10] & reg_we & ~wr_err;
5723: assign stall_stall6_wd = reg_wdata[6];
5724:
5725: assign stall_stall7_we = addr_hit[10] & reg_we & ~wr_err;
5726: assign stall_stall7_wd = reg_wdata[7];
5727:
5728: assign stall_stall8_we = addr_hit[10] & reg_we & ~wr_err;
5729: assign stall_stall8_wd = reg_wdata[8];
5730:
5731: assign stall_stall9_we = addr_hit[10] & reg_we & ~wr_err;
5732: assign stall_stall9_wd = reg_wdata[9];
5733:
5734: assign stall_stall10_we = addr_hit[10] & reg_we & ~wr_err;
5735: assign stall_stall10_wd = reg_wdata[10];
5736:
5737: assign stall_stall11_we = addr_hit[10] & reg_we & ~wr_err;
5738: assign stall_stall11_wd = reg_wdata[11];
5739:
5740: assign configin0_buffer0_we = addr_hit[11] & reg_we & ~wr_err;
5741: assign configin0_buffer0_wd = reg_wdata[4:0];
5742:
5743: assign configin0_size0_we = addr_hit[11] & reg_we & ~wr_err;
5744: assign configin0_size0_wd = reg_wdata[14:8];
5745:
5746: assign configin0_pend0_we = addr_hit[11] & reg_we & ~wr_err;
5747: assign configin0_pend0_wd = reg_wdata[30];
5748:
5749: assign configin0_rdy0_we = addr_hit[11] & reg_we & ~wr_err;
5750: assign configin0_rdy0_wd = reg_wdata[31];
5751:
5752: assign configin1_buffer1_we = addr_hit[12] & reg_we & ~wr_err;
5753: assign configin1_buffer1_wd = reg_wdata[4:0];
5754:
5755: assign configin1_size1_we = addr_hit[12] & reg_we & ~wr_err;
5756: assign configin1_size1_wd = reg_wdata[14:8];
5757:
5758: assign configin1_pend1_we = addr_hit[12] & reg_we & ~wr_err;
5759: assign configin1_pend1_wd = reg_wdata[30];
5760:
5761: assign configin1_rdy1_we = addr_hit[12] & reg_we & ~wr_err;
5762: assign configin1_rdy1_wd = reg_wdata[31];
5763:
5764: assign configin2_buffer2_we = addr_hit[13] & reg_we & ~wr_err;
5765: assign configin2_buffer2_wd = reg_wdata[4:0];
5766:
5767: assign configin2_size2_we = addr_hit[13] & reg_we & ~wr_err;
5768: assign configin2_size2_wd = reg_wdata[14:8];
5769:
5770: assign configin2_pend2_we = addr_hit[13] & reg_we & ~wr_err;
5771: assign configin2_pend2_wd = reg_wdata[30];
5772:
5773: assign configin2_rdy2_we = addr_hit[13] & reg_we & ~wr_err;
5774: assign configin2_rdy2_wd = reg_wdata[31];
5775:
5776: assign configin3_buffer3_we = addr_hit[14] & reg_we & ~wr_err;
5777: assign configin3_buffer3_wd = reg_wdata[4:0];
5778:
5779: assign configin3_size3_we = addr_hit[14] & reg_we & ~wr_err;
5780: assign configin3_size3_wd = reg_wdata[14:8];
5781:
5782: assign configin3_pend3_we = addr_hit[14] & reg_we & ~wr_err;
5783: assign configin3_pend3_wd = reg_wdata[30];
5784:
5785: assign configin3_rdy3_we = addr_hit[14] & reg_we & ~wr_err;
5786: assign configin3_rdy3_wd = reg_wdata[31];
5787:
5788: assign configin4_buffer4_we = addr_hit[15] & reg_we & ~wr_err;
5789: assign configin4_buffer4_wd = reg_wdata[4:0];
5790:
5791: assign configin4_size4_we = addr_hit[15] & reg_we & ~wr_err;
5792: assign configin4_size4_wd = reg_wdata[14:8];
5793:
5794: assign configin4_pend4_we = addr_hit[15] & reg_we & ~wr_err;
5795: assign configin4_pend4_wd = reg_wdata[30];
5796:
5797: assign configin4_rdy4_we = addr_hit[15] & reg_we & ~wr_err;
5798: assign configin4_rdy4_wd = reg_wdata[31];
5799:
5800: assign configin5_buffer5_we = addr_hit[16] & reg_we & ~wr_err;
5801: assign configin5_buffer5_wd = reg_wdata[4:0];
5802:
5803: assign configin5_size5_we = addr_hit[16] & reg_we & ~wr_err;
5804: assign configin5_size5_wd = reg_wdata[14:8];
5805:
5806: assign configin5_pend5_we = addr_hit[16] & reg_we & ~wr_err;
5807: assign configin5_pend5_wd = reg_wdata[30];
5808:
5809: assign configin5_rdy5_we = addr_hit[16] & reg_we & ~wr_err;
5810: assign configin5_rdy5_wd = reg_wdata[31];
5811:
5812: assign configin6_buffer6_we = addr_hit[17] & reg_we & ~wr_err;
5813: assign configin6_buffer6_wd = reg_wdata[4:0];
5814:
5815: assign configin6_size6_we = addr_hit[17] & reg_we & ~wr_err;
5816: assign configin6_size6_wd = reg_wdata[14:8];
5817:
5818: assign configin6_pend6_we = addr_hit[17] & reg_we & ~wr_err;
5819: assign configin6_pend6_wd = reg_wdata[30];
5820:
5821: assign configin6_rdy6_we = addr_hit[17] & reg_we & ~wr_err;
5822: assign configin6_rdy6_wd = reg_wdata[31];
5823:
5824: assign configin7_buffer7_we = addr_hit[18] & reg_we & ~wr_err;
5825: assign configin7_buffer7_wd = reg_wdata[4:0];
5826:
5827: assign configin7_size7_we = addr_hit[18] & reg_we & ~wr_err;
5828: assign configin7_size7_wd = reg_wdata[14:8];
5829:
5830: assign configin7_pend7_we = addr_hit[18] & reg_we & ~wr_err;
5831: assign configin7_pend7_wd = reg_wdata[30];
5832:
5833: assign configin7_rdy7_we = addr_hit[18] & reg_we & ~wr_err;
5834: assign configin7_rdy7_wd = reg_wdata[31];
5835:
5836: assign configin8_buffer8_we = addr_hit[19] & reg_we & ~wr_err;
5837: assign configin8_buffer8_wd = reg_wdata[4:0];
5838:
5839: assign configin8_size8_we = addr_hit[19] & reg_we & ~wr_err;
5840: assign configin8_size8_wd = reg_wdata[14:8];
5841:
5842: assign configin8_pend8_we = addr_hit[19] & reg_we & ~wr_err;
5843: assign configin8_pend8_wd = reg_wdata[30];
5844:
5845: assign configin8_rdy8_we = addr_hit[19] & reg_we & ~wr_err;
5846: assign configin8_rdy8_wd = reg_wdata[31];
5847:
5848: assign configin9_buffer9_we = addr_hit[20] & reg_we & ~wr_err;
5849: assign configin9_buffer9_wd = reg_wdata[4:0];
5850:
5851: assign configin9_size9_we = addr_hit[20] & reg_we & ~wr_err;
5852: assign configin9_size9_wd = reg_wdata[14:8];
5853:
5854: assign configin9_pend9_we = addr_hit[20] & reg_we & ~wr_err;
5855: assign configin9_pend9_wd = reg_wdata[30];
5856:
5857: assign configin9_rdy9_we = addr_hit[20] & reg_we & ~wr_err;
5858: assign configin9_rdy9_wd = reg_wdata[31];
5859:
5860: assign configin10_buffer10_we = addr_hit[21] & reg_we & ~wr_err;
5861: assign configin10_buffer10_wd = reg_wdata[4:0];
5862:
5863: assign configin10_size10_we = addr_hit[21] & reg_we & ~wr_err;
5864: assign configin10_size10_wd = reg_wdata[14:8];
5865:
5866: assign configin10_pend10_we = addr_hit[21] & reg_we & ~wr_err;
5867: assign configin10_pend10_wd = reg_wdata[30];
5868:
5869: assign configin10_rdy10_we = addr_hit[21] & reg_we & ~wr_err;
5870: assign configin10_rdy10_wd = reg_wdata[31];
5871:
5872: assign configin11_buffer11_we = addr_hit[22] & reg_we & ~wr_err;
5873: assign configin11_buffer11_wd = reg_wdata[4:0];
5874:
5875: assign configin11_size11_we = addr_hit[22] & reg_we & ~wr_err;
5876: assign configin11_size11_wd = reg_wdata[14:8];
5877:
5878: assign configin11_pend11_we = addr_hit[22] & reg_we & ~wr_err;
5879: assign configin11_pend11_wd = reg_wdata[30];
5880:
5881: assign configin11_rdy11_we = addr_hit[22] & reg_we & ~wr_err;
5882: assign configin11_rdy11_wd = reg_wdata[31];
5883:
5884: assign iso_iso0_we = addr_hit[23] & reg_we & ~wr_err;
5885: assign iso_iso0_wd = reg_wdata[0];
5886:
5887: assign iso_iso1_we = addr_hit[23] & reg_we & ~wr_err;
5888: assign iso_iso1_wd = reg_wdata[1];
5889:
5890: assign iso_iso2_we = addr_hit[23] & reg_we & ~wr_err;
5891: assign iso_iso2_wd = reg_wdata[2];
5892:
5893: assign iso_iso3_we = addr_hit[23] & reg_we & ~wr_err;
5894: assign iso_iso3_wd = reg_wdata[3];
5895:
5896: assign iso_iso4_we = addr_hit[23] & reg_we & ~wr_err;
5897: assign iso_iso4_wd = reg_wdata[4];
5898:
5899: assign iso_iso5_we = addr_hit[23] & reg_we & ~wr_err;
5900: assign iso_iso5_wd = reg_wdata[5];
5901:
5902: assign iso_iso6_we = addr_hit[23] & reg_we & ~wr_err;
5903: assign iso_iso6_wd = reg_wdata[6];
5904:
5905: assign iso_iso7_we = addr_hit[23] & reg_we & ~wr_err;
5906: assign iso_iso7_wd = reg_wdata[7];
5907:
5908: assign iso_iso8_we = addr_hit[23] & reg_we & ~wr_err;
5909: assign iso_iso8_wd = reg_wdata[8];
5910:
5911: assign iso_iso9_we = addr_hit[23] & reg_we & ~wr_err;
5912: assign iso_iso9_wd = reg_wdata[9];
5913:
5914: assign iso_iso10_we = addr_hit[23] & reg_we & ~wr_err;
5915: assign iso_iso10_wd = reg_wdata[10];
5916:
5917: assign iso_iso11_we = addr_hit[23] & reg_we & ~wr_err;
5918: assign iso_iso11_wd = reg_wdata[11];
5919:
5920: assign data_toggle_clear_clear0_we = addr_hit[24] & reg_we & ~wr_err;
5921: assign data_toggle_clear_clear0_wd = reg_wdata[0];
5922:
5923: assign data_toggle_clear_clear1_we = addr_hit[24] & reg_we & ~wr_err;
5924: assign data_toggle_clear_clear1_wd = reg_wdata[1];
5925:
5926: assign data_toggle_clear_clear2_we = addr_hit[24] & reg_we & ~wr_err;
5927: assign data_toggle_clear_clear2_wd = reg_wdata[2];
5928:
5929: assign data_toggle_clear_clear3_we = addr_hit[24] & reg_we & ~wr_err;
5930: assign data_toggle_clear_clear3_wd = reg_wdata[3];
5931:
5932: assign data_toggle_clear_clear4_we = addr_hit[24] & reg_we & ~wr_err;
5933: assign data_toggle_clear_clear4_wd = reg_wdata[4];
5934:
5935: assign data_toggle_clear_clear5_we = addr_hit[24] & reg_we & ~wr_err;
5936: assign data_toggle_clear_clear5_wd = reg_wdata[5];
5937:
5938: assign data_toggle_clear_clear6_we = addr_hit[24] & reg_we & ~wr_err;
5939: assign data_toggle_clear_clear6_wd = reg_wdata[6];
5940:
5941: assign data_toggle_clear_clear7_we = addr_hit[24] & reg_we & ~wr_err;
5942: assign data_toggle_clear_clear7_wd = reg_wdata[7];
5943:
5944: assign data_toggle_clear_clear8_we = addr_hit[24] & reg_we & ~wr_err;
5945: assign data_toggle_clear_clear8_wd = reg_wdata[8];
5946:
5947: assign data_toggle_clear_clear9_we = addr_hit[24] & reg_we & ~wr_err;
5948: assign data_toggle_clear_clear9_wd = reg_wdata[9];
5949:
5950: assign data_toggle_clear_clear10_we = addr_hit[24] & reg_we & ~wr_err;
5951: assign data_toggle_clear_clear10_wd = reg_wdata[10];
5952:
5953: assign data_toggle_clear_clear11_we = addr_hit[24] & reg_we & ~wr_err;
5954: assign data_toggle_clear_clear11_wd = reg_wdata[11];
5955:
5956: assign phy_config_rx_differential_mode_we = addr_hit[25] & reg_we & ~wr_err;
5957: assign phy_config_rx_differential_mode_wd = reg_wdata[0];
5958:
5959: assign phy_config_tx_differential_mode_we = addr_hit[25] & reg_we & ~wr_err;
5960: assign phy_config_tx_differential_mode_wd = reg_wdata[1];
5961:
5962: assign phy_config_eop_single_bit_we = addr_hit[25] & reg_we & ~wr_err;
5963: assign phy_config_eop_single_bit_wd = reg_wdata[2];
5964:
5965: assign phy_config_override_pwr_sense_en_we = addr_hit[25] & reg_we & ~wr_err;
5966: assign phy_config_override_pwr_sense_en_wd = reg_wdata[3];
5967:
5968: assign phy_config_override_pwr_sense_val_we = addr_hit[25] & reg_we & ~wr_err;
5969: assign phy_config_override_pwr_sense_val_wd = reg_wdata[4];
5970:
5971: assign phy_config_pinflip_we = addr_hit[25] & reg_we & ~wr_err;
5972: assign phy_config_pinflip_wd = reg_wdata[5];
5973:
5974: assign phy_config_usb_ref_disable_we = addr_hit[25] & reg_we & ~wr_err;
5975: assign phy_config_usb_ref_disable_wd = reg_wdata[6];
5976:
5977: // Read data return
5978: always_comb begin
5979: reg_rdata_next = '0;
5980: unique case (1'b1)
5981: addr_hit[0]: begin
5982: reg_rdata_next[0] = intr_state_pkt_received_qs;
5983: reg_rdata_next[1] = intr_state_pkt_sent_qs;
5984: reg_rdata_next[2] = intr_state_disconnected_qs;
5985: reg_rdata_next[3] = intr_state_host_lost_qs;
5986: reg_rdata_next[4] = intr_state_link_reset_qs;
5987: reg_rdata_next[5] = intr_state_link_suspend_qs;
5988: reg_rdata_next[6] = intr_state_link_resume_qs;
5989: reg_rdata_next[7] = intr_state_av_empty_qs;
5990: reg_rdata_next[8] = intr_state_rx_full_qs;
5991: reg_rdata_next[9] = intr_state_av_overflow_qs;
5992: reg_rdata_next[10] = intr_state_link_in_err_qs;
5993: reg_rdata_next[11] = intr_state_rx_crc_err_qs;
5994: reg_rdata_next[12] = intr_state_rx_pid_err_qs;
5995: reg_rdata_next[13] = intr_state_rx_bitstuff_err_qs;
5996: reg_rdata_next[14] = intr_state_frame_qs;
5997: reg_rdata_next[15] = intr_state_connected_qs;
5998: end
5999:
6000: addr_hit[1]: begin
6001: reg_rdata_next[0] = intr_enable_pkt_received_qs;
6002: reg_rdata_next[1] = intr_enable_pkt_sent_qs;
6003: reg_rdata_next[2] = intr_enable_disconnected_qs;
6004: reg_rdata_next[3] = intr_enable_host_lost_qs;
6005: reg_rdata_next[4] = intr_enable_link_reset_qs;
6006: reg_rdata_next[5] = intr_enable_link_suspend_qs;
6007: reg_rdata_next[6] = intr_enable_link_resume_qs;
6008: reg_rdata_next[7] = intr_enable_av_empty_qs;
6009: reg_rdata_next[8] = intr_enable_rx_full_qs;
6010: reg_rdata_next[9] = intr_enable_av_overflow_qs;
6011: reg_rdata_next[10] = intr_enable_link_in_err_qs;
6012: reg_rdata_next[11] = intr_enable_rx_crc_err_qs;
6013: reg_rdata_next[12] = intr_enable_rx_pid_err_qs;
6014: reg_rdata_next[13] = intr_enable_rx_bitstuff_err_qs;
6015: reg_rdata_next[14] = intr_enable_frame_qs;
6016: reg_rdata_next[15] = intr_enable_connected_qs;
6017: end
6018:
6019: addr_hit[2]: begin
6020: reg_rdata_next[0] = '0;
6021: reg_rdata_next[1] = '0;
6022: reg_rdata_next[2] = '0;
6023: reg_rdata_next[3] = '0;
6024: reg_rdata_next[4] = '0;
6025: reg_rdata_next[5] = '0;
6026: reg_rdata_next[6] = '0;
6027: reg_rdata_next[7] = '0;
6028: reg_rdata_next[8] = '0;
6029: reg_rdata_next[9] = '0;
6030: reg_rdata_next[10] = '0;
6031: reg_rdata_next[11] = '0;
6032: reg_rdata_next[12] = '0;
6033: reg_rdata_next[13] = '0;
6034: reg_rdata_next[14] = '0;
6035: reg_rdata_next[15] = '0;
6036: end
6037:
6038: addr_hit[3]: begin
6039: reg_rdata_next[0] = usbctrl_enable_qs;
6040: reg_rdata_next[22:16] = usbctrl_device_address_qs;
6041: end
6042:
6043: addr_hit[4]: begin
6044: reg_rdata_next[10:0] = usbstat_frame_qs;
6045: reg_rdata_next[11] = usbstat_host_lost_qs;
6046: reg_rdata_next[14:12] = usbstat_link_state_qs;
6047: reg_rdata_next[15] = usbstat_sense_qs;
6048: reg_rdata_next[18:16] = usbstat_av_depth_qs;
6049: reg_rdata_next[23] = usbstat_av_full_qs;
6050: reg_rdata_next[26:24] = usbstat_rx_depth_qs;
6051: reg_rdata_next[31] = usbstat_rx_empty_qs;
6052: end
6053:
6054: addr_hit[5]: begin
6055: reg_rdata_next[4:0] = '0;
6056: end
6057:
6058: addr_hit[6]: begin
6059: reg_rdata_next[4:0] = rxfifo_buffer_qs;
6060: reg_rdata_next[14:8] = rxfifo_size_qs;
6061: reg_rdata_next[19] = rxfifo_setup_qs;
6062: reg_rdata_next[23:20] = rxfifo_ep_qs;
6063: end
6064:
6065: addr_hit[7]: begin
6066: reg_rdata_next[0] = rxenable_setup_setup0_qs;
6067: reg_rdata_next[1] = rxenable_setup_setup1_qs;
6068: reg_rdata_next[2] = rxenable_setup_setup2_qs;
6069: reg_rdata_next[3] = rxenable_setup_setup3_qs;
6070: reg_rdata_next[4] = rxenable_setup_setup4_qs;
6071: reg_rdata_next[5] = rxenable_setup_setup5_qs;
6072: reg_rdata_next[6] = rxenable_setup_setup6_qs;
6073: reg_rdata_next[7] = rxenable_setup_setup7_qs;
6074: reg_rdata_next[8] = rxenable_setup_setup8_qs;
6075: reg_rdata_next[9] = rxenable_setup_setup9_qs;
6076: reg_rdata_next[10] = rxenable_setup_setup10_qs;
6077: reg_rdata_next[11] = rxenable_setup_setup11_qs;
6078: end
6079:
6080: addr_hit[8]: begin
6081: reg_rdata_next[0] = rxenable_out_out0_qs;
6082: reg_rdata_next[1] = rxenable_out_out1_qs;
6083: reg_rdata_next[2] = rxenable_out_out2_qs;
6084: reg_rdata_next[3] = rxenable_out_out3_qs;
6085: reg_rdata_next[4] = rxenable_out_out4_qs;
6086: reg_rdata_next[5] = rxenable_out_out5_qs;
6087: reg_rdata_next[6] = rxenable_out_out6_qs;
6088: reg_rdata_next[7] = rxenable_out_out7_qs;
6089: reg_rdata_next[8] = rxenable_out_out8_qs;
6090: reg_rdata_next[9] = rxenable_out_out9_qs;
6091: reg_rdata_next[10] = rxenable_out_out10_qs;
6092: reg_rdata_next[11] = rxenable_out_out11_qs;
6093: end
6094:
6095: addr_hit[9]: begin
6096: reg_rdata_next[0] = in_sent_sent0_qs;
6097: reg_rdata_next[1] = in_sent_sent1_qs;
6098: reg_rdata_next[2] = in_sent_sent2_qs;
6099: reg_rdata_next[3] = in_sent_sent3_qs;
6100: reg_rdata_next[4] = in_sent_sent4_qs;
6101: reg_rdata_next[5] = in_sent_sent5_qs;
6102: reg_rdata_next[6] = in_sent_sent6_qs;
6103: reg_rdata_next[7] = in_sent_sent7_qs;
6104: reg_rdata_next[8] = in_sent_sent8_qs;
6105: reg_rdata_next[9] = in_sent_sent9_qs;
6106: reg_rdata_next[10] = in_sent_sent10_qs;
6107: reg_rdata_next[11] = in_sent_sent11_qs;
6108: end
6109:
6110: addr_hit[10]: begin
6111: reg_rdata_next[0] = stall_stall0_qs;
6112: reg_rdata_next[1] = stall_stall1_qs;
6113: reg_rdata_next[2] = stall_stall2_qs;
6114: reg_rdata_next[3] = stall_stall3_qs;
6115: reg_rdata_next[4] = stall_stall4_qs;
6116: reg_rdata_next[5] = stall_stall5_qs;
6117: reg_rdata_next[6] = stall_stall6_qs;
6118: reg_rdata_next[7] = stall_stall7_qs;
6119: reg_rdata_next[8] = stall_stall8_qs;
6120: reg_rdata_next[9] = stall_stall9_qs;
6121: reg_rdata_next[10] = stall_stall10_qs;
6122: reg_rdata_next[11] = stall_stall11_qs;
6123: end
6124:
6125: addr_hit[11]: begin
6126: reg_rdata_next[4:0] = configin0_buffer0_qs;
6127: reg_rdata_next[14:8] = configin0_size0_qs;
6128: reg_rdata_next[30] = configin0_pend0_qs;
6129: reg_rdata_next[31] = configin0_rdy0_qs;
6130: end
6131:
6132: addr_hit[12]: begin
6133: reg_rdata_next[4:0] = configin1_buffer1_qs;
6134: reg_rdata_next[14:8] = configin1_size1_qs;
6135: reg_rdata_next[30] = configin1_pend1_qs;
6136: reg_rdata_next[31] = configin1_rdy1_qs;
6137: end
6138:
6139: addr_hit[13]: begin
6140: reg_rdata_next[4:0] = configin2_buffer2_qs;
6141: reg_rdata_next[14:8] = configin2_size2_qs;
6142: reg_rdata_next[30] = configin2_pend2_qs;
6143: reg_rdata_next[31] = configin2_rdy2_qs;
6144: end
6145:
6146: addr_hit[14]: begin
6147: reg_rdata_next[4:0] = configin3_buffer3_qs;
6148: reg_rdata_next[14:8] = configin3_size3_qs;
6149: reg_rdata_next[30] = configin3_pend3_qs;
6150: reg_rdata_next[31] = configin3_rdy3_qs;
6151: end
6152:
6153: addr_hit[15]: begin
6154: reg_rdata_next[4:0] = configin4_buffer4_qs;
6155: reg_rdata_next[14:8] = configin4_size4_qs;
6156: reg_rdata_next[30] = configin4_pend4_qs;
6157: reg_rdata_next[31] = configin4_rdy4_qs;
6158: end
6159:
6160: addr_hit[16]: begin
6161: reg_rdata_next[4:0] = configin5_buffer5_qs;
6162: reg_rdata_next[14:8] = configin5_size5_qs;
6163: reg_rdata_next[30] = configin5_pend5_qs;
6164: reg_rdata_next[31] = configin5_rdy5_qs;
6165: end
6166:
6167: addr_hit[17]: begin
6168: reg_rdata_next[4:0] = configin6_buffer6_qs;
6169: reg_rdata_next[14:8] = configin6_size6_qs;
6170: reg_rdata_next[30] = configin6_pend6_qs;
6171: reg_rdata_next[31] = configin6_rdy6_qs;
6172: end
6173:
6174: addr_hit[18]: begin
6175: reg_rdata_next[4:0] = configin7_buffer7_qs;
6176: reg_rdata_next[14:8] = configin7_size7_qs;
6177: reg_rdata_next[30] = configin7_pend7_qs;
6178: reg_rdata_next[31] = configin7_rdy7_qs;
6179: end
6180:
6181: addr_hit[19]: begin
6182: reg_rdata_next[4:0] = configin8_buffer8_qs;
6183: reg_rdata_next[14:8] = configin8_size8_qs;
6184: reg_rdata_next[30] = configin8_pend8_qs;
6185: reg_rdata_next[31] = configin8_rdy8_qs;
6186: end
6187:
6188: addr_hit[20]: begin
6189: reg_rdata_next[4:0] = configin9_buffer9_qs;
6190: reg_rdata_next[14:8] = configin9_size9_qs;
6191: reg_rdata_next[30] = configin9_pend9_qs;
6192: reg_rdata_next[31] = configin9_rdy9_qs;
6193: end
6194:
6195: addr_hit[21]: begin
6196: reg_rdata_next[4:0] = configin10_buffer10_qs;
6197: reg_rdata_next[14:8] = configin10_size10_qs;
6198: reg_rdata_next[30] = configin10_pend10_qs;
6199: reg_rdata_next[31] = configin10_rdy10_qs;
6200: end
6201:
6202: addr_hit[22]: begin
6203: reg_rdata_next[4:0] = configin11_buffer11_qs;
6204: reg_rdata_next[14:8] = configin11_size11_qs;
6205: reg_rdata_next[30] = configin11_pend11_qs;
6206: reg_rdata_next[31] = configin11_rdy11_qs;
6207: end
6208:
6209: addr_hit[23]: begin
6210: reg_rdata_next[0] = iso_iso0_qs;
6211: reg_rdata_next[1] = iso_iso1_qs;
6212: reg_rdata_next[2] = iso_iso2_qs;
6213: reg_rdata_next[3] = iso_iso3_qs;
6214: reg_rdata_next[4] = iso_iso4_qs;
6215: reg_rdata_next[5] = iso_iso5_qs;
6216: reg_rdata_next[6] = iso_iso6_qs;
6217: reg_rdata_next[7] = iso_iso7_qs;
6218: reg_rdata_next[8] = iso_iso8_qs;
6219: reg_rdata_next[9] = iso_iso9_qs;
6220: reg_rdata_next[10] = iso_iso10_qs;
6221: reg_rdata_next[11] = iso_iso11_qs;
6222: end
6223:
6224: addr_hit[24]: begin
6225: reg_rdata_next[0] = '0;
6226: reg_rdata_next[1] = '0;
6227: reg_rdata_next[2] = '0;
6228: reg_rdata_next[3] = '0;
6229: reg_rdata_next[4] = '0;
6230: reg_rdata_next[5] = '0;
6231: reg_rdata_next[6] = '0;
6232: reg_rdata_next[7] = '0;
6233: reg_rdata_next[8] = '0;
6234: reg_rdata_next[9] = '0;
6235: reg_rdata_next[10] = '0;
6236: reg_rdata_next[11] = '0;
6237: end
6238:
6239: addr_hit[25]: begin
6240: reg_rdata_next[0] = phy_config_rx_differential_mode_qs;
6241: reg_rdata_next[1] = phy_config_tx_differential_mode_qs;
6242: reg_rdata_next[2] = phy_config_eop_single_bit_qs;
6243: reg_rdata_next[3] = phy_config_override_pwr_sense_en_qs;
6244: reg_rdata_next[4] = phy_config_override_pwr_sense_val_qs;
6245: reg_rdata_next[5] = phy_config_pinflip_qs;
6246: reg_rdata_next[6] = phy_config_usb_ref_disable_qs;
6247: end
6248:
6249: default: begin
6250: reg_rdata_next = '1;
6251: end
6252: endcase
6253: end
6254:
6255: // Assertions for Register Interface
6256: `ASSERT_PULSE(wePulse, reg_we)
6257: `ASSERT_PULSE(rePulse, reg_re)
6258:
6259: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
6260:
6261: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
6262:
6263: // this is formulated as an assumption such that the FPV testbenches do disprove this
6264: // property by mistake
6265: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
6266:
6267: endmodule
6268: