hw/ip/prim_generic/rtl/prim_generic_clock_gating.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Common Library: Clock Gating cell
   6: 
   7: module prim_generic_clock_gating (
   8:   input        clk_i,
   9:   input        en_i,
  10:   input        test_en_i,
  11:   output logic clk_o
  12: );
  13: 
  14:   // Assume en_i synchronized, if not put synchronizer prior to en_i
  15:   logic en_latch;
  16:   always_latch begin
  17:     if (!clk_i) begin
  18:       en_latch = en_i | test_en_i;
  19:     end
  20:   end
  21:   assign clk_o = en_latch & clk_i;
  22: 
  23: endmodule
  24: