../src/lowrisc_prim_all_0.1/rtl/prim_clock_gating_sync.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Common Library: Clock Gating cell with synchronizer
6:
7: module prim_clock_gating_sync (
8: input clk_i,
9: input rst_ni,
10: input test_en_i,
11: input async_en_i,
12: output logic en_o,
13: output logic clk_o
14: );
15:
16:
17: prim_flop_2sync #(
18: .Width(1)
19: ) i_sync (
20: .clk_i,
21: .rst_ni,
22: .d(async_en_i),
23: .q(en_o)
24: );
25:
26: prim_clock_gating i_cg (
27: .clk_i,
28: .en_i(en_o),
29: .test_en_i,
30: .clk_o
31: );
32:
33:
34: endmodule
35: