hw/ip/prim_xilinx/rtl/prim_xilinx_clock_mux2.sv Cov: 60%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: module prim_xilinx_clock_mux2 (
   6:   input        clk0_i,
   7:   input        clk1_i,
   8:   input        sel_i,
   9:   output logic clk_o
  10: );
  11: 
  12:   // for more info, refer to the Xilinx technology primitives userguide, e.g.:
  13:   // ug953-vivado-7series-libraries.pdf
  14:   // ug974-vivado-ultrascale-libraries.pdf
  15:   BUFGMUX bufgmux_i (
  16:     .S  ( sel_i  ),
  17:     .I0 ( clk0_i ),
  18:     .I1 ( clk1_i ),
  19:     .O  ( clk_o  )
  20:   );
  21: 
  22:   // make sure sel is never X (including during reset)
  23:   // need to use ##1 as this could break with inverted clocks that
  24:   // start with a rising edge at the beginning of the simulation.
  25:   `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0)
  26:   `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0)
  27: 
  28: endmodule : prim_xilinx_clock_mux2
  29: