../src/lowrisc_ip_pwrmgr_0.1/rtl/pwrmgr_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: `include "prim_assert.sv"
   8: 
   9: module pwrmgr_reg_top (
  10:   input clk_i,
  11:   input rst_ni,
  12: 
  13:   // Below Regster interface can be changed
  14:   input  tlul_pkg::tl_h2d_t tl_i,
  15:   output tlul_pkg::tl_d2h_t tl_o,
  16:   // To HW
  17:   output pwrmgr_reg_pkg::pwrmgr_reg2hw_t reg2hw, // Write
  18:   input  pwrmgr_reg_pkg::pwrmgr_hw2reg_t hw2reg, // Read
  19: 
  20:   // Config
  21:   input devmode_i // If 1, explicit error return for unmapped register access
  22: );
  23: 
  24:   import pwrmgr_reg_pkg::* ;
  25: 
  26:   localparam int AW = 6;
  27:   localparam int DW = 32;
  28:   localparam int DBW = DW/8;                    // Byte Width
  29: 
  30:   // register signals
  31:   logic           reg_we;
  32:   logic           reg_re;
  33:   logic [AW-1:0]  reg_addr;
  34:   logic [DW-1:0]  reg_wdata;
  35:   logic [DBW-1:0] reg_be;
  36:   logic [DW-1:0]  reg_rdata;
  37:   logic           reg_error;
  38: 
  39:   logic          addrmiss, wr_err;
  40: 
  41:   logic [DW-1:0] reg_rdata_next;
  42: 
  43:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  44:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  45: 
  46:   assign tl_reg_h2d = tl_i;
  47:   assign tl_o       = tl_reg_d2h;
  48: 
  49:   tlul_adapter_reg #(
  50:     .RegAw(AW),
  51:     .RegDw(DW)
  52:   ) u_reg_if (
  53:     .clk_i,
  54:     .rst_ni,
  55: 
  56:     .tl_i (tl_reg_h2d),
  57:     .tl_o (tl_reg_d2h),
  58: 
  59:     .we_o    (reg_we),
  60:     .re_o    (reg_re),
  61:     .addr_o  (reg_addr),
  62:     .wdata_o (reg_wdata),
  63:     .be_o    (reg_be),
  64:     .rdata_i (reg_rdata),
  65:     .error_i (reg_error)
  66:   );
  67: 
  68:   assign reg_rdata = reg_rdata_next ;
  69:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  70: 
  71:   // Define SW related signals
  72:   // Format: __{wd|we|qs}
  73:   //        or _{wd|we|qs} if field == 1 or 0
  74:   logic intr_state_qs;
  75:   logic intr_state_wd;
  76:   logic intr_state_we;
  77:   logic intr_enable_qs;
  78:   logic intr_enable_wd;
  79:   logic intr_enable_we;
  80:   logic intr_test_wd;
  81:   logic intr_test_we;
  82:   logic ctrl_cfg_regwen_qs;
  83:   logic ctrl_cfg_regwen_re;
  84:   logic control_low_power_hint_qs;
  85:   logic control_low_power_hint_wd;
  86:   logic control_low_power_hint_we;
  87:   logic control_core_clk_en_qs;
  88:   logic control_core_clk_en_wd;
  89:   logic control_core_clk_en_we;
  90:   logic control_io_clk_en_qs;
  91:   logic control_io_clk_en_wd;
  92:   logic control_io_clk_en_we;
  93:   logic control_main_pd_n_qs;
  94:   logic control_main_pd_n_wd;
  95:   logic control_main_pd_n_we;
  96:   logic cfg_cdc_sync_qs;
  97:   logic cfg_cdc_sync_wd;
  98:   logic cfg_cdc_sync_we;
  99:   logic wakeup_en_regwen_qs;
 100:   logic wakeup_en_regwen_wd;
 101:   logic wakeup_en_regwen_we;
 102:   logic [15:0] wakeup_en_qs;
 103:   logic [15:0] wakeup_en_wd;
 104:   logic wakeup_en_we;
 105:   logic [15:0] wake_status_qs;
 106:   logic reset_en_regwen_qs;
 107:   logic reset_en_regwen_wd;
 108:   logic reset_en_regwen_we;
 109:   logic [1:0] reset_en_qs;
 110:   logic [1:0] reset_en_wd;
 111:   logic reset_en_we;
 112:   logic [1:0] reset_status_qs;
 113:   logic wake_info_capture_dis_qs;
 114:   logic wake_info_capture_dis_wd;
 115:   logic wake_info_capture_dis_we;
 116:   logic [15:0] wake_info_reasons_qs;
 117:   logic [15:0] wake_info_reasons_wd;
 118:   logic wake_info_reasons_we;
 119:   logic wake_info_reasons_re;
 120:   logic wake_info_fall_through_qs;
 121:   logic wake_info_fall_through_wd;
 122:   logic wake_info_fall_through_we;
 123:   logic wake_info_fall_through_re;
 124:   logic wake_info_abort_qs;
 125:   logic wake_info_abort_wd;
 126:   logic wake_info_abort_we;
 127:   logic wake_info_abort_re;
 128: 
 129:   // Register instances
 130:   // R[intr_state]: V(False)
 131: 
 132:   prim_subreg #(
 133:     .DW      (1),
 134:     .SWACCESS("W1C"),
 135:     .RESVAL  (1'h0)
 136:   ) u_intr_state (
 137:     .clk_i   (clk_i    ),
 138:     .rst_ni  (rst_ni  ),
 139: 
 140:     // from register interface
 141:     .we     (intr_state_we),
 142:     .wd     (intr_state_wd),
 143: 
 144:     // from internal hardware
 145:     .de     (hw2reg.intr_state.de),
 146:     .d      (hw2reg.intr_state.d ),
 147: 
 148:     // to internal hardware
 149:     .qe     (),
 150:     .q      (reg2hw.intr_state.q ),
 151: 
 152:     // to register interface (read)
 153:     .qs     (intr_state_qs)
 154:   );
 155: 
 156: 
 157:   // R[intr_enable]: V(False)
 158: 
 159:   prim_subreg #(
 160:     .DW      (1),
 161:     .SWACCESS("RW"),
 162:     .RESVAL  (1'h0)
 163:   ) u_intr_enable (
 164:     .clk_i   (clk_i    ),
 165:     .rst_ni  (rst_ni  ),
 166: 
 167:     // from register interface
 168:     .we     (intr_enable_we),
 169:     .wd     (intr_enable_wd),
 170: 
 171:     // from internal hardware
 172:     .de     (1'b0),
 173:     .d      ('0  ),
 174: 
 175:     // to internal hardware
 176:     .qe     (),
 177:     .q      (reg2hw.intr_enable.q ),
 178: 
 179:     // to register interface (read)
 180:     .qs     (intr_enable_qs)
 181:   );
 182: 
 183: 
 184:   // R[intr_test]: V(True)
 185: 
 186:   prim_subreg_ext #(
 187:     .DW    (1)
 188:   ) u_intr_test (
 189:     .re     (1'b0),
 190:     .we     (intr_test_we),
 191:     .wd     (intr_test_wd),
 192:     .d      ('0),
 193:     .qre    (),
 194:     .qe     (reg2hw.intr_test.qe),
 195:     .q      (reg2hw.intr_test.q ),
 196:     .qs     ()
 197:   );
 198: 
 199: 
 200:   // R[ctrl_cfg_regwen]: V(True)
 201: 
 202:   prim_subreg_ext #(
 203:     .DW    (1)
 204:   ) u_ctrl_cfg_regwen (
 205:     .re     (ctrl_cfg_regwen_re),
 206:     .we     (1'b0),
 207:     .wd     ('0),
 208:     .d      (hw2reg.ctrl_cfg_regwen.d),
 209:     .qre    (),
 210:     .qe     (),
 211:     .q      (),
 212:     .qs     (ctrl_cfg_regwen_qs)
 213:   );
 214: 
 215: 
 216:   // R[control]: V(False)
 217: 
 218:   //   F[low_power_hint]: 0:0
 219:   prim_subreg #(
 220:     .DW      (1),
 221:     .SWACCESS("RW"),
 222:     .RESVAL  (1'h0)
 223:   ) u_control_low_power_hint (
 224:     .clk_i   (clk_i    ),
 225:     .rst_ni  (rst_ni  ),
 226: 
 227:     // from register interface (qualified with register enable)
 228:     .we     (control_low_power_hint_we & ctrl_cfg_regwen_qs),
 229:     .wd     (control_low_power_hint_wd),
 230: 
 231:     // from internal hardware
 232:     .de     (hw2reg.control.low_power_hint.de),
 233:     .d      (hw2reg.control.low_power_hint.d ),
 234: 
 235:     // to internal hardware
 236:     .qe     (),
 237:     .q      (reg2hw.control.low_power_hint.q ),
 238: 
 239:     // to register interface (read)
 240:     .qs     (control_low_power_hint_qs)
 241:   );
 242: 
 243: 
 244:   //   F[core_clk_en]: 4:4
 245:   prim_subreg #(
 246:     .DW      (1),
 247:     .SWACCESS("RW"),
 248:     .RESVAL  (1'h0)
 249:   ) u_control_core_clk_en (
 250:     .clk_i   (clk_i    ),
 251:     .rst_ni  (rst_ni  ),
 252: 
 253:     // from register interface (qualified with register enable)
 254:     .we     (control_core_clk_en_we & ctrl_cfg_regwen_qs),
 255:     .wd     (control_core_clk_en_wd),
 256: 
 257:     // from internal hardware
 258:     .de     (1'b0),
 259:     .d      ('0  ),
 260: 
 261:     // to internal hardware
 262:     .qe     (),
 263:     .q      (reg2hw.control.core_clk_en.q ),
 264: 
 265:     // to register interface (read)
 266:     .qs     (control_core_clk_en_qs)
 267:   );
 268: 
 269: 
 270:   //   F[io_clk_en]: 5:5
 271:   prim_subreg #(
 272:     .DW      (1),
 273:     .SWACCESS("RW"),
 274:     .RESVAL  (1'h0)
 275:   ) u_control_io_clk_en (
 276:     .clk_i   (clk_i    ),
 277:     .rst_ni  (rst_ni  ),
 278: 
 279:     // from register interface (qualified with register enable)
 280:     .we     (control_io_clk_en_we & ctrl_cfg_regwen_qs),
 281:     .wd     (control_io_clk_en_wd),
 282: 
 283:     // from internal hardware
 284:     .de     (1'b0),
 285:     .d      ('0  ),
 286: 
 287:     // to internal hardware
 288:     .qe     (),
 289:     .q      (reg2hw.control.io_clk_en.q ),
 290: 
 291:     // to register interface (read)
 292:     .qs     (control_io_clk_en_qs)
 293:   );
 294: 
 295: 
 296:   //   F[main_pd_n]: 6:6
 297:   prim_subreg #(
 298:     .DW      (1),
 299:     .SWACCESS("RW"),
 300:     .RESVAL  (1'h1)
 301:   ) u_control_main_pd_n (
 302:     .clk_i   (clk_i    ),
 303:     .rst_ni  (rst_ni  ),
 304: 
 305:     // from register interface (qualified with register enable)
 306:     .we     (control_main_pd_n_we & ctrl_cfg_regwen_qs),
 307:     .wd     (control_main_pd_n_wd),
 308: 
 309:     // from internal hardware
 310:     .de     (1'b0),
 311:     .d      ('0  ),
 312: 
 313:     // to internal hardware
 314:     .qe     (),
 315:     .q      (reg2hw.control.main_pd_n.q ),
 316: 
 317:     // to register interface (read)
 318:     .qs     (control_main_pd_n_qs)
 319:   );
 320: 
 321: 
 322:   // R[cfg_cdc_sync]: V(False)
 323: 
 324:   prim_subreg #(
 325:     .DW      (1),
 326:     .SWACCESS("RW"),
 327:     .RESVAL  (1'h0)
 328:   ) u_cfg_cdc_sync (
 329:     .clk_i   (clk_i    ),
 330:     .rst_ni  (rst_ni  ),
 331: 
 332:     // from register interface
 333:     .we     (cfg_cdc_sync_we),
 334:     .wd     (cfg_cdc_sync_wd),
 335: 
 336:     // from internal hardware
 337:     .de     (hw2reg.cfg_cdc_sync.de),
 338:     .d      (hw2reg.cfg_cdc_sync.d ),
 339: 
 340:     // to internal hardware
 341:     .qe     (reg2hw.cfg_cdc_sync.qe),
 342:     .q      (reg2hw.cfg_cdc_sync.q ),
 343: 
 344:     // to register interface (read)
 345:     .qs     (cfg_cdc_sync_qs)
 346:   );
 347: 
 348: 
 349:   // R[wakeup_en_regwen]: V(False)
 350: 
 351:   prim_subreg #(
 352:     .DW      (1),
 353:     .SWACCESS("W0C"),
 354:     .RESVAL  (1'h1)
 355:   ) u_wakeup_en_regwen (
 356:     .clk_i   (clk_i    ),
 357:     .rst_ni  (rst_ni  ),
 358: 
 359:     // from register interface
 360:     .we     (wakeup_en_regwen_we),
 361:     .wd     (wakeup_en_regwen_wd),
 362: 
 363:     // from internal hardware
 364:     .de     (1'b0),
 365:     .d      ('0  ),
 366: 
 367:     // to internal hardware
 368:     .qe     (),
 369:     .q      (),
 370: 
 371:     // to register interface (read)
 372:     .qs     (wakeup_en_regwen_qs)
 373:   );
 374: 
 375: 
 376:   // R[wakeup_en]: V(False)
 377: 
 378:   prim_subreg #(
 379:     .DW      (16),
 380:     .SWACCESS("RW"),
 381:     .RESVAL  (16'h0)
 382:   ) u_wakeup_en (
 383:     .clk_i   (clk_i    ),
 384:     .rst_ni  (rst_ni  ),
 385: 
 386:     // from register interface (qualified with register enable)
 387:     .we     (wakeup_en_we & wakeup_en_regwen_qs),
 388:     .wd     (wakeup_en_wd),
 389: 
 390:     // from internal hardware
 391:     .de     (1'b0),
 392:     .d      ('0  ),
 393: 
 394:     // to internal hardware
 395:     .qe     (),
 396:     .q      (reg2hw.wakeup_en.q ),
 397: 
 398:     // to register interface (read)
 399:     .qs     (wakeup_en_qs)
 400:   );
 401: 
 402: 
 403:   // R[wake_status]: V(False)
 404: 
 405:   // constant-only read
 406:   assign wake_status_qs = 16'h0;
 407: 
 408: 
 409:   // R[reset_en_regwen]: V(False)
 410: 
 411:   prim_subreg #(
 412:     .DW      (1),
 413:     .SWACCESS("W0C"),
 414:     .RESVAL  (1'h1)
 415:   ) u_reset_en_regwen (
 416:     .clk_i   (clk_i    ),
 417:     .rst_ni  (rst_ni  ),
 418: 
 419:     // from register interface
 420:     .we     (reset_en_regwen_we),
 421:     .wd     (reset_en_regwen_wd),
 422: 
 423:     // from internal hardware
 424:     .de     (1'b0),
 425:     .d      ('0  ),
 426: 
 427:     // to internal hardware
 428:     .qe     (),
 429:     .q      (),
 430: 
 431:     // to register interface (read)
 432:     .qs     (reset_en_regwen_qs)
 433:   );
 434: 
 435: 
 436:   // R[reset_en]: V(False)
 437: 
 438:   prim_subreg #(
 439:     .DW      (2),
 440:     .SWACCESS("RW"),
 441:     .RESVAL  (2'h0)
 442:   ) u_reset_en (
 443:     .clk_i   (clk_i    ),
 444:     .rst_ni  (rst_ni  ),
 445: 
 446:     // from register interface (qualified with register enable)
 447:     .we     (reset_en_we & reset_en_regwen_qs),
 448:     .wd     (reset_en_wd),
 449: 
 450:     // from internal hardware
 451:     .de     (1'b0),
 452:     .d      ('0  ),
 453: 
 454:     // to internal hardware
 455:     .qe     (),
 456:     .q      (reg2hw.reset_en.q ),
 457: 
 458:     // to register interface (read)
 459:     .qs     (reset_en_qs)
 460:   );
 461: 
 462: 
 463:   // R[reset_status]: V(False)
 464: 
 465:   // constant-only read
 466:   assign reset_status_qs = 2'h0;
 467: 
 468: 
 469:   // R[wake_info_capture_dis]: V(False)
 470: 
 471:   prim_subreg #(
 472:     .DW      (1),
 473:     .SWACCESS("RW"),
 474:     .RESVAL  (1'h0)
 475:   ) u_wake_info_capture_dis (
 476:     .clk_i   (clk_i    ),
 477:     .rst_ni  (rst_ni  ),
 478: 
 479:     // from register interface
 480:     .we     (wake_info_capture_dis_we),
 481:     .wd     (wake_info_capture_dis_wd),
 482: 
 483:     // from internal hardware
 484:     .de     (1'b0),
 485:     .d      ('0  ),
 486: 
 487:     // to internal hardware
 488:     .qe     (),
 489:     .q      (reg2hw.wake_info_capture_dis.q ),
 490: 
 491:     // to register interface (read)
 492:     .qs     (wake_info_capture_dis_qs)
 493:   );
 494: 
 495: 
 496:   // R[wake_info]: V(True)
 497: 
 498:   //   F[reasons]: 15:0
 499:   prim_subreg_ext #(
 500:     .DW    (16)
 501:   ) u_wake_info_reasons (
 502:     .re     (wake_info_reasons_re),
 503:     .we     (wake_info_reasons_we),
 504:     .wd     (wake_info_reasons_wd),
 505:     .d      (hw2reg.wake_info.reasons.d),
 506:     .qre    (),
 507:     .qe     (reg2hw.wake_info.reasons.qe),
 508:     .q      (reg2hw.wake_info.reasons.q ),
 509:     .qs     (wake_info_reasons_qs)
 510:   );
 511: 
 512: 
 513:   //   F[fall_through]: 16:16
 514:   prim_subreg_ext #(
 515:     .DW    (1)
 516:   ) u_wake_info_fall_through (
 517:     .re     (wake_info_fall_through_re),
 518:     .we     (wake_info_fall_through_we),
 519:     .wd     (wake_info_fall_through_wd),
 520:     .d      (hw2reg.wake_info.fall_through.d),
 521:     .qre    (),
 522:     .qe     (reg2hw.wake_info.fall_through.qe),
 523:     .q      (reg2hw.wake_info.fall_through.q ),
 524:     .qs     (wake_info_fall_through_qs)
 525:   );
 526: 
 527: 
 528:   //   F[abort]: 17:17
 529:   prim_subreg_ext #(
 530:     .DW    (1)
 531:   ) u_wake_info_abort (
 532:     .re     (wake_info_abort_re),
 533:     .we     (wake_info_abort_we),
 534:     .wd     (wake_info_abort_wd),
 535:     .d      (hw2reg.wake_info.abort.d),
 536:     .qre    (),
 537:     .qe     (reg2hw.wake_info.abort.qe),
 538:     .q      (reg2hw.wake_info.abort.q ),
 539:     .qs     (wake_info_abort_qs)
 540:   );
 541: 
 542: 
 543: 
 544: 
 545:   logic [13:0] addr_hit;
 546:   always_comb begin
 547:     addr_hit = '0;
 548:     addr_hit[ 0] = (reg_addr == PWRMGR_INTR_STATE_OFFSET);
 549:     addr_hit[ 1] = (reg_addr == PWRMGR_INTR_ENABLE_OFFSET);
 550:     addr_hit[ 2] = (reg_addr == PWRMGR_INTR_TEST_OFFSET);
 551:     addr_hit[ 3] = (reg_addr == PWRMGR_CTRL_CFG_REGWEN_OFFSET);
 552:     addr_hit[ 4] = (reg_addr == PWRMGR_CONTROL_OFFSET);
 553:     addr_hit[ 5] = (reg_addr == PWRMGR_CFG_CDC_SYNC_OFFSET);
 554:     addr_hit[ 6] = (reg_addr == PWRMGR_WAKEUP_EN_REGWEN_OFFSET);
 555:     addr_hit[ 7] = (reg_addr == PWRMGR_WAKEUP_EN_OFFSET);
 556:     addr_hit[ 8] = (reg_addr == PWRMGR_WAKE_STATUS_OFFSET);
 557:     addr_hit[ 9] = (reg_addr == PWRMGR_RESET_EN_REGWEN_OFFSET);
 558:     addr_hit[10] = (reg_addr == PWRMGR_RESET_EN_OFFSET);
 559:     addr_hit[11] = (reg_addr == PWRMGR_RESET_STATUS_OFFSET);
 560:     addr_hit[12] = (reg_addr == PWRMGR_WAKE_INFO_CAPTURE_DIS_OFFSET);
 561:     addr_hit[13] = (reg_addr == PWRMGR_WAKE_INFO_OFFSET);
 562:   end
 563: 
 564:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
 565: 
 566:   // Check sub-word write is permitted
 567:   always_comb begin
 568:     wr_err = 1'b0;
 569:     if (addr_hit[ 0] && reg_we && (PWRMGR_PERMIT[ 0] != (PWRMGR_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
 570:     if (addr_hit[ 1] && reg_we && (PWRMGR_PERMIT[ 1] != (PWRMGR_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
 571:     if (addr_hit[ 2] && reg_we && (PWRMGR_PERMIT[ 2] != (PWRMGR_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
 572:     if (addr_hit[ 3] && reg_we && (PWRMGR_PERMIT[ 3] != (PWRMGR_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
 573:     if (addr_hit[ 4] && reg_we && (PWRMGR_PERMIT[ 4] != (PWRMGR_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
 574:     if (addr_hit[ 5] && reg_we && (PWRMGR_PERMIT[ 5] != (PWRMGR_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
 575:     if (addr_hit[ 6] && reg_we && (PWRMGR_PERMIT[ 6] != (PWRMGR_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
 576:     if (addr_hit[ 7] && reg_we && (PWRMGR_PERMIT[ 7] != (PWRMGR_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
 577:     if (addr_hit[ 8] && reg_we && (PWRMGR_PERMIT[ 8] != (PWRMGR_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
 578:     if (addr_hit[ 9] && reg_we && (PWRMGR_PERMIT[ 9] != (PWRMGR_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
 579:     if (addr_hit[10] && reg_we && (PWRMGR_PERMIT[10] != (PWRMGR_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
 580:     if (addr_hit[11] && reg_we && (PWRMGR_PERMIT[11] != (PWRMGR_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
 581:     if (addr_hit[12] && reg_we && (PWRMGR_PERMIT[12] != (PWRMGR_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
 582:     if (addr_hit[13] && reg_we && (PWRMGR_PERMIT[13] != (PWRMGR_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
 583:   end
 584: 
 585:   assign intr_state_we = addr_hit[0] & reg_we & ~wr_err;
 586:   assign intr_state_wd = reg_wdata[0];
 587: 
 588:   assign intr_enable_we = addr_hit[1] & reg_we & ~wr_err;
 589:   assign intr_enable_wd = reg_wdata[0];
 590: 
 591:   assign intr_test_we = addr_hit[2] & reg_we & ~wr_err;
 592:   assign intr_test_wd = reg_wdata[0];
 593: 
 594:   assign ctrl_cfg_regwen_re = addr_hit[3] && reg_re;
 595: 
 596:   assign control_low_power_hint_we = addr_hit[4] & reg_we & ~wr_err;
 597:   assign control_low_power_hint_wd = reg_wdata[0];
 598: 
 599:   assign control_core_clk_en_we = addr_hit[4] & reg_we & ~wr_err;
 600:   assign control_core_clk_en_wd = reg_wdata[4];
 601: 
 602:   assign control_io_clk_en_we = addr_hit[4] & reg_we & ~wr_err;
 603:   assign control_io_clk_en_wd = reg_wdata[5];
 604: 
 605:   assign control_main_pd_n_we = addr_hit[4] & reg_we & ~wr_err;
 606:   assign control_main_pd_n_wd = reg_wdata[6];
 607: 
 608:   assign cfg_cdc_sync_we = addr_hit[5] & reg_we & ~wr_err;
 609:   assign cfg_cdc_sync_wd = reg_wdata[0];
 610: 
 611:   assign wakeup_en_regwen_we = addr_hit[6] & reg_we & ~wr_err;
 612:   assign wakeup_en_regwen_wd = reg_wdata[0];
 613: 
 614:   assign wakeup_en_we = addr_hit[7] & reg_we & ~wr_err;
 615:   assign wakeup_en_wd = reg_wdata[15:0];
 616: 
 617: 
 618:   assign reset_en_regwen_we = addr_hit[9] & reg_we & ~wr_err;
 619:   assign reset_en_regwen_wd = reg_wdata[0];
 620: 
 621:   assign reset_en_we = addr_hit[10] & reg_we & ~wr_err;
 622:   assign reset_en_wd = reg_wdata[1:0];
 623: 
 624: 
 625:   assign wake_info_capture_dis_we = addr_hit[12] & reg_we & ~wr_err;
 626:   assign wake_info_capture_dis_wd = reg_wdata[0];
 627: 
 628:   assign wake_info_reasons_we = addr_hit[13] & reg_we & ~wr_err;
 629:   assign wake_info_reasons_wd = reg_wdata[15:0];
 630:   assign wake_info_reasons_re = addr_hit[13] && reg_re;
 631: 
 632:   assign wake_info_fall_through_we = addr_hit[13] & reg_we & ~wr_err;
 633:   assign wake_info_fall_through_wd = reg_wdata[16];
 634:   assign wake_info_fall_through_re = addr_hit[13] && reg_re;
 635: 
 636:   assign wake_info_abort_we = addr_hit[13] & reg_we & ~wr_err;
 637:   assign wake_info_abort_wd = reg_wdata[17];
 638:   assign wake_info_abort_re = addr_hit[13] && reg_re;
 639: 
 640:   // Read data return
 641:   always_comb begin
 642:     reg_rdata_next = '0;
 643:     unique case (1'b1)
 644:       addr_hit[0]: begin
 645:         reg_rdata_next[0] = intr_state_qs;
 646:       end
 647: 
 648:       addr_hit[1]: begin
 649:         reg_rdata_next[0] = intr_enable_qs;
 650:       end
 651: 
 652:       addr_hit[2]: begin
 653:         reg_rdata_next[0] = '0;
 654:       end
 655: 
 656:       addr_hit[3]: begin
 657:         reg_rdata_next[0] = ctrl_cfg_regwen_qs;
 658:       end
 659: 
 660:       addr_hit[4]: begin
 661:         reg_rdata_next[0] = control_low_power_hint_qs;
 662:         reg_rdata_next[4] = control_core_clk_en_qs;
 663:         reg_rdata_next[5] = control_io_clk_en_qs;
 664:         reg_rdata_next[6] = control_main_pd_n_qs;
 665:       end
 666: 
 667:       addr_hit[5]: begin
 668:         reg_rdata_next[0] = cfg_cdc_sync_qs;
 669:       end
 670: 
 671:       addr_hit[6]: begin
 672:         reg_rdata_next[0] = wakeup_en_regwen_qs;
 673:       end
 674: 
 675:       addr_hit[7]: begin
 676:         reg_rdata_next[15:0] = wakeup_en_qs;
 677:       end
 678: 
 679:       addr_hit[8]: begin
 680:         reg_rdata_next[15:0] = wake_status_qs;
 681:       end
 682: 
 683:       addr_hit[9]: begin
 684:         reg_rdata_next[0] = reset_en_regwen_qs;
 685:       end
 686: 
 687:       addr_hit[10]: begin
 688:         reg_rdata_next[1:0] = reset_en_qs;
 689:       end
 690: 
 691:       addr_hit[11]: begin
 692:         reg_rdata_next[1:0] = reset_status_qs;
 693:       end
 694: 
 695:       addr_hit[12]: begin
 696:         reg_rdata_next[0] = wake_info_capture_dis_qs;
 697:       end
 698: 
 699:       addr_hit[13]: begin
 700:         reg_rdata_next[15:0] = wake_info_reasons_qs;
 701:         reg_rdata_next[16] = wake_info_fall_through_qs;
 702:         reg_rdata_next[17] = wake_info_abort_qs;
 703:       end
 704: 
 705:       default: begin
 706:         reg_rdata_next = '1;
 707:       end
 708:     endcase
 709:   end
 710: 
 711:   // Assertions for Register Interface
 712:   `ASSERT_PULSE(wePulse, reg_we)
 713:   `ASSERT_PULSE(rePulse, reg_re)
 714: 
 715:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
 716: 
 717:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
 718: 
 719:   // this is formulated as an assumption such that the FPV testbenches do disprove this
 720:   // property by mistake
 721:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
 722: 
 723: endmodule
 724: