hw/ip/prim/rtl/prim_intr_hw.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Indentifier: Apache-2.0
4: //
5: // Primitive interrupt handler. This assumes the existence of three
6: // controller registers: INTR_ENABLE, INTR_STATE, INTR_TEST.
7: // This module can be instantiated once per interrupt field, or
8: // "bussified" with all fields of the interrupt vector.
9:
10: module prim_intr_hw #(parameter int unsigned Width = 1) (
11: // event
12: input [Width-1:0] event_intr_i,
13:
14: // register interface
15: input [Width-1:0] reg2hw_intr_enable_q_i,
16: input [Width-1:0] reg2hw_intr_test_q_i,
17: input reg2hw_intr_test_qe_i,
18: input [Width-1:0] reg2hw_intr_state_q_i,
19: output hw2reg_intr_state_de_o,
20: output [Width-1:0] hw2reg_intr_state_d_o,
21:
22: // outgoing interrupt
23: output [Width-1:0] intr_o
24: );
25:
26: logic [Width-1:0] new_event;
27: assign new_event =
28: (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i);
29: assign hw2reg_intr_state_de_o = |new_event;
30: // for scalar interrupts, this resolves to '1' with new event
31: // for vector interrupts, new events are OR'd in to existing interrupt state
32: assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i;
33: assign intr_o = reg2hw_intr_state_q_i & reg2hw_intr_enable_q_i;
34:
35: endmodule
36:
37: