hw/ip/prim/rtl/prim_subreg_ext.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register slice conforming to Comportibility guide.
6:
7: module prim_subreg_ext #(
8: parameter int unsigned DW = 32
9: ) (
10: input re,
11: input we,
12: input [DW-1:0] wd,
13:
14: input [DW-1:0] d,
15:
16: // output to HW and Reg Read
17: output logic qe,
18: output logic qre,
19: output logic [DW-1:0] q,
20: output logic [DW-1:0] qs
21: );
22:
23: assign qs = d;
24: assign q = wd;
25: assign qe = we;
26: assign qre = re;
27:
28: endmodule
29: