../src/lowrisc_prim_xilinx_clock_mux2_0/rtl/prim_xilinx_clock_mux2.sv Cov: 60%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: `include "prim_assert.sv"
   6: 
   7: module prim_xilinx_clock_mux2 (
   8:   input        clk0_i,
   9:   input        clk1_i,
  10:   input        sel_i,
  11:   output logic clk_o
  12: );
  13: 
  14:   // for more info, refer to the Xilinx technology primitives userguide, e.g.:
  15:   // ug953-vivado-7series-libraries.pdf
  16:   // ug974-vivado-ultrascale-libraries.pdf
  17:   BUFGMUX bufgmux_i (
  18:     .S  ( sel_i  ),
  19:     .I0 ( clk0_i ),
  20:     .I1 ( clk1_i ),
  21:     .O  ( clk_o  )
  22:   );
  23: 
  24:   // make sure sel is never X (including during reset)
  25:   // need to use ##1 as this could break with inverted clocks that
  26:   // start with a rising edge at the beginning of the simulation.
  27:   `ASSERT(selKnown0, ##1 !$isunknown(sel_i), clk0_i, 0)
  28:   `ASSERT(selKnown1, ##1 !$isunknown(sel_i), clk1_i, 0)
  29: 
  30: endmodule : prim_xilinx_clock_mux2
  31: