../src/pulp-platform_riscv-dbg_0.1_0/pulp_riscv_dbg/src/dm_pkg.sv Cov: 100%
1: /* Copyright 2018 ETH Zurich and University of Bologna.
2: * Copyright and related rights are licensed under the Solderpad Hardware
3: * License, Version 0.51 (the “License”); you may not use this file except in
4: * compliance with the License. You may obtain a copy of the License at
5: * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
6: * or agreed to in writing, software, hardware and materials distributed under
7: * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
8: * CONDITIONS OF ANY KIND, either express or implied. See the License for the
9: * specific language governing permissions and limitations under the License.
10: *
11: * File: dm_pkg.sv
12: * Author: Florian Zaruba
13: * Date: 30.6.2018
14: *
15: * Description: Debug-module package, contains common system definitions.
16: *
17: */
18:
19: package dm;
20: localparam logic [3:0] DbgVersion013 = 4'h2;
21: // size of program buffer in junks of 32-bit words
22: localparam logic [4:0] ProgBufSize = 5'h8;
23:
24: // amount of data count registers implemented
25: localparam logic [3:0] DataCount = 4'h2;
26:
27: // address to which a hart should jump when it was requested to halt
28: localparam logic [63:0] HaltAddress = 64'h800;
29: localparam logic [63:0] ResumeAddress = HaltAddress + 4;
30: localparam logic [63:0] ExceptionAddress = HaltAddress + 8;
31:
32: // address where data0-15 is shadowed or if shadowed in a CSR
33: // address of the first CSR used for shadowing the data
34: localparam logic [11:0] DataAddr = 12'h380; // we are aligned with Rocket here
35:
36: // debug registers
37: typedef enum logic [7:0] {
38: Data0 = 8'h04,
39: Data1 = 8'h05,
40: Data2 = 8'h06,
41: Data3 = 8'h07,
42: Data4 = 8'h08,
43: Data5 = 8'h09,
44: Data6 = 8'h0A,
45: Data7 = 8'h0B,
46: Data8 = 8'h0C,
47: Data9 = 8'h0D,
48: Data10 = 8'h0E,
49: Data11 = 8'h0F,
50: DMControl = 8'h10,
51: DMStatus = 8'h11, // r/o
52: Hartinfo = 8'h12,
53: HaltSum1 = 8'h13,
54: HAWindowSel = 8'h14,
55: HAWindow = 8'h15,
56: AbstractCS = 8'h16,
57: Command = 8'h17,
58: AbstractAuto = 8'h18,
59: DevTreeAddr0 = 8'h19,
60: DevTreeAddr1 = 8'h1A,
61: DevTreeAddr2 = 8'h1B,
62: DevTreeAddr3 = 8'h1C,
63: NextDM = 8'h1D,
64: ProgBuf0 = 8'h20,
65: ProgBuf15 = 8'h2F,
66: AuthData = 8'h30,
67: HaltSum2 = 8'h34,
68: HaltSum3 = 8'h35,
69: SBAddress3 = 8'h37,
70: SBCS = 8'h38,
71: SBAddress0 = 8'h39,
72: SBAddress1 = 8'h3A,
73: SBAddress2 = 8'h3B,
74: SBData0 = 8'h3C,
75: SBData1 = 8'h3D,
76: SBData2 = 8'h3E,
77: SBData3 = 8'h3F,
78: HaltSum0 = 8'h40
79: } dm_csr_e;
80:
81: // debug causes
82: localparam logic [2:0] CauseBreakpoint = 3'h1;
83: localparam logic [2:0] CauseTrigger = 3'h2;
84: localparam logic [2:0] CauseRequest = 3'h3;
85: localparam logic [2:0] CauseSingleStep = 3'h4;
86:
87: typedef struct packed {
88: logic [31:23] zero1;
89: logic impebreak;
90: logic [21:20] zero0;
91: logic allhavereset;
92: logic anyhavereset;
93: logic allresumeack;
94: logic anyresumeack;
95: logic allnonexistent;
96: logic anynonexistent;
97: logic allunavail;
98: logic anyunavail;
99: logic allrunning;
100: logic anyrunning;
101: logic allhalted;
102: logic anyhalted;
103: logic authenticated;
104: logic authbusy;
105: logic hasresethaltreq;
106: logic devtreevalid;
107: logic [3:0] version;
108: } dmstatus_t;
109:
110: typedef struct packed {
111: logic haltreq;
112: logic resumereq;
113: logic hartreset;
114: logic ackhavereset;
115: logic zero1;
116: logic hasel;
117: logic [25:16] hartsello;
118: logic [15:6] hartselhi;
119: logic [5:4] zero0;
120: logic setresethaltreq;
121: logic clrresethaltreq;
122: logic ndmreset;
123: logic dmactive;
124: } dmcontrol_t;
125:
126: typedef struct packed {
127: logic [31:24] zero1;
128: logic [23:20] nscratch;
129: logic [19:17] zero0;
130: logic dataaccess;
131: logic [15:12] datasize;
132: logic [11:0] dataaddr;
133: } hartinfo_t;
134:
135: typedef enum logic [2:0] {
136: CmdErrNone, CmdErrBusy, CmdErrNotSupported,
137: CmdErrorException, CmdErrorHaltResume,
138: CmdErrorBus, CmdErrorOther = 7
139: } cmderr_e;
140:
141: typedef struct packed {
142: logic [31:29] zero3;
143: logic [28:24] progbufsize;
144: logic [23:13] zero2;
145: logic busy;
146: logic zero1;
147: cmderr_e cmderr;
148: logic [7:4] zero0;
149: logic [3:0] datacount;
150: } abstractcs_t;
151:
152: typedef enum logic [7:0] {
153: AccessRegister = 8'h0,
154: QuickAccess = 8'h1,
155: AccessMemory = 8'h2
156: } cmd_e;
157:
158: typedef struct packed {
159: cmd_e cmdtype;
160: logic [23:0] control;
161: } command_t;
162:
163: typedef struct packed {
164: logic [31:16] autoexecprogbuf;
165: logic [15:12] zero0;
166: logic [11:0] autoexecdata;
167: } abstractauto_t;
168:
169: typedef struct packed {
170: logic zero1;
171: logic [22:20] aarsize;
172: logic aarpostincrement;
173: logic postexec;
174: logic transfer;
175: logic write;
176: logic [15:0] regno;
177: } ac_ar_cmd_t;
178:
179: // DTM
180: typedef enum logic [1:0] {
181: DTM_NOP = 2'h0,
182: DTM_READ = 2'h1,
183: DTM_WRITE = 2'h2
184: } dtm_op_e;
185:
186: typedef struct packed {
187: logic [31:29] sbversion;
188: logic [28:23] zero0;
189: logic sbbusyerror;
190: logic sbbusy;
191: logic sbreadonaddr;
192: logic [19:17] sbaccess;
193: logic sbautoincrement;
194: logic sbreadondata;
195: logic [14:12] sberror;
196: logic [11:5] sbasize;
197: logic sbaccess128;
198: logic sbaccess64;
199: logic sbaccess32;
200: logic sbaccess16;
201: logic sbaccess8;
202: } sbcs_t;
203:
204: localparam logic[1:0] DTM_SUCCESS = 2'h0;
205:
206: typedef struct packed {
207: logic [6:0] addr;
208: dtm_op_e op;
209: logic [31:0] data;
210: } dmi_req_t;
211:
212: typedef struct packed {
213: logic [31:0] data;
214: logic [1:0] resp;
215: } dmi_resp_t;
216:
217: // privilege levels
218: typedef enum logic[1:0] {
219: PRIV_LVL_M = 2'b11,
220: PRIV_LVL_S = 2'b01,
221: PRIV_LVL_U = 2'b00
222: } priv_lvl_t;
223:
224: // debugregs in core
225: typedef struct packed {
226: logic [31:28] xdebugver;
227: logic [27:16] zero2;
228: logic ebreakm;
229: logic zero1;
230: logic ebreaks;
231: logic ebreaku;
232: logic stepie;
233: logic stopcount;
234: logic stoptime;
235: logic [8:6] cause;
236: logic zero0;
237: logic mprven;
238: logic nmip;
239: logic step;
240: priv_lvl_t prv;
241: } dcsr_t;
242:
243: // CSRs
244: typedef enum logic [11:0] {
245: // Floating-Point CSRs
246: CSR_FFLAGS = 12'h001,
247: CSR_FRM = 12'h002,
248: CSR_FCSR = 12'h003,
249: CSR_FTRAN = 12'h800,
250: // Supervisor Mode CSRs
251: CSR_SSTATUS = 12'h100,
252: CSR_SIE = 12'h104,
253: CSR_STVEC = 12'h105,
254: CSR_SCOUNTEREN = 12'h106,
255: CSR_SSCRATCH = 12'h140,
256: CSR_SEPC = 12'h141,
257: CSR_SCAUSE = 12'h142,
258: CSR_STVAL = 12'h143,
259: CSR_SIP = 12'h144,
260: CSR_SATP = 12'h180,
261: // Machine Mode CSRs
262: CSR_MSTATUS = 12'h300,
263: CSR_MISA = 12'h301,
264: CSR_MEDELEG = 12'h302,
265: CSR_MIDELEG = 12'h303,
266: CSR_MIE = 12'h304,
267: CSR_MTVEC = 12'h305,
268: CSR_MCOUNTEREN = 12'h306,
269: CSR_MSCRATCH = 12'h340,
270: CSR_MEPC = 12'h341,
271: CSR_MCAUSE = 12'h342,
272: CSR_MTVAL = 12'h343,
273: CSR_MIP = 12'h344,
274: CSR_PMPCFG0 = 12'h3A0,
275: CSR_PMPADDR0 = 12'h3B0,
276: CSR_MVENDORID = 12'hF11,
277: CSR_MARCHID = 12'hF12,
278: CSR_MIMPID = 12'hF13,
279: CSR_MHARTID = 12'hF14,
280: CSR_MCYCLE = 12'hB00,
281: CSR_MINSTRET = 12'hB02,
282: CSR_DCACHE = 12'h701,
283: CSR_ICACHE = 12'h700,
284:
285: CSR_TSELECT = 12'h7A0,
286: CSR_TDATA1 = 12'h7A1,
287: CSR_TDATA2 = 12'h7A2,
288: CSR_TDATA3 = 12'h7A3,
289: CSR_TINFO = 12'h7A4,
290:
291: // Debug CSR
292: CSR_DCSR = 12'h7b0,
293: CSR_DPC = 12'h7b1,
294: CSR_DSCRATCH0 = 12'h7b2, // optional
295: CSR_DSCRATCH1 = 12'h7b3, // optional
296:
297: // Counters and Timers
298: CSR_CYCLE = 12'hC00,
299: CSR_TIME = 12'hC01,
300: CSR_INSTRET = 12'hC02
301: } csr_reg_t;
302:
303:
304: // Instruction Generation Helpers
305: function automatic logic [31:0] jal (logic [4:0] rd,
306: logic [20:0] imm);
307: // OpCode Jal
308: return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h6f};
309: endfunction
310:
311: function automatic logic [31:0] jalr (logic [4:0] rd,
312: logic [4:0] rs1,
313: logic [11:0] offset);
314: // OpCode Jal
315: return {offset[11:0], rs1, 3'b0, rd, 7'h67};
316: endfunction
317:
318: function automatic logic [31:0] andi (logic [4:0] rd,
319: logic [4:0] rs1,
320: logic [11:0] imm);
321: // OpCode andi
322: return {imm[11:0], rs1, 3'h7, rd, 7'h13};
323: endfunction
324:
325: function automatic logic [31:0] slli (logic [4:0] rd,
326: logic [4:0] rs1,
327: logic [5:0] shamt);
328: // OpCode slli
329: return {6'b0, shamt[5:0], rs1, 3'h1, rd, 7'h13};
330: endfunction
331:
332: function automatic logic [31:0] srli (logic [4:0] rd,
333: logic [4:0] rs1,
334: logic [5:0] shamt);
335: // OpCode srli
336: return {6'b0, shamt[5:0], rs1, 3'h5, rd, 7'h13};
337: endfunction
338:
339: function automatic logic [31:0] load (logic [2:0] size,
340: logic [4:0] dest,
341: logic [4:0] base,
342: logic [11:0] offset);
343: // OpCode Load
344: return {offset[11:0], base, size, dest, 7'h03};
345: endfunction
346:
347: function automatic logic [31:0] auipc (logic [4:0] rd,
348: logic [20:0] imm);
349: // OpCode Auipc
350: return {imm[20], imm[10:1], imm[11], imm[19:12], rd, 7'h17};
351: endfunction
352:
353: function automatic logic [31:0] store (logic [2:0] size,
354: logic [4:0] src,
355: logic [4:0] base,
356: logic [11:0] offset);
357: // OpCode Store
358: return {offset[11:5], src, base, size, offset[4:0], 7'h23};
359: endfunction
360:
361: function automatic logic [31:0] float_load (logic [2:0] size,
362: logic [4:0] dest,
363: logic [4:0] base,
364: logic [11:0] offset);
365: // OpCode Load
366: return {offset[11:0], base, size, dest, 7'b00_001_11};
367: endfunction
368:
369: function automatic logic [31:0] float_store (logic [2:0] size,
370: logic [4:0] src,
371: logic [4:0] base,
372: logic [11:0] offset);
373: // OpCode Store
374: return {offset[11:5], src, base, size, offset[4:0], 7'b01_001_11};
375: endfunction
376:
377: function automatic logic [31:0] csrw (csr_reg_t csr,
378: logic [4:0] rs1);
379: // CSRRW, rd, OpCode System
380: return {csr, rs1, 3'h1, 5'h0, 7'h73};
381: endfunction
382:
383: function automatic logic [31:0] csrr (csr_reg_t csr,
384: logic [4:0] dest);
385: // rs1, CSRRS, rd, OpCode System
386: return {csr, 5'h0, 3'h2, dest, 7'h73};
387: endfunction
388:
389: function automatic logic [31:0] branch(logic [4:0] src2,
390: logic [4:0] src1,
391: logic [2:0] funct3,
392: logic [11:0] offset);
393: // OpCode Branch
394: return {offset[11], offset[9:4], src2, src1, funct3,
395: offset[3:0], offset[10], 7'b11_000_11};
396: endfunction
397:
398: function automatic logic [31:0] ebreak ();
399: return 32'h00100073;
400: endfunction
401:
402: function automatic logic [31:0] wfi ();
403: return 32'h10500073;
404: endfunction
405:
406: function automatic logic [31:0] nop ();
407: return 32'h00000013;
408: endfunction
409:
410: function automatic logic [31:0] illegal ();
411: return 32'h00000000;
412: endfunction
413:
414: endpackage : dm
415: