hw/ip/spi_device/rtl/spi_device_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Serial Peripheral Interface (SPI) Device module.
6: //
7:
8: package spi_device_pkg;
9:
10: // SPI Operation mode
11: typedef enum logic [1:0] {
12: FwMode = 'h0,
13: EepromRam = 'h1,
14: EepromFlash = 'h2,
15: PassThrough = 'h3
16: } spi_mode_e;
17:
18: // SPI Read mode. QUAD uses additional two pins to read
19: // Bit 0: Single, Bit 1: Dual Bit 2: Quad
20: typedef logic [2:0] spi_rdmode_t;
21:
22: typedef logic [7:0] spi_byte_t;
23:
24: // eSPI utilizes Alert# signal (from device to host)
25: typedef enum logic [1:0] {
26: Spi = 2'h0,
27: Espi = 2'h1,
28: Tpm = 2'h2
29: } spi_type_e;
30:
31: typedef enum logic [1:0] {
32: AddrByte = 2'h0, // 1 byte for address
33: AddrWord = 2'h1, // 2 bytes for address
34: AddrFull = 2'h2 // 3 bytes for address
35: } spi_addr_size_e;
36:
37: localparam int MEM_AW = 12; // Memory Address width (Byte based)
38:
39: // List of supported commands @ Bunker mode (SPI Manufacturing mode)
40: typedef enum logic [7:0] {
41: Nop = 8'h00,
42: WrSts = 8'h01, // Write STATUS1 followed by STATUS2 register
43: Write = 8'h02, // Write Data
44: Read = 8'h03, // Limit to a certain speed as read data starts right after addr
45: WrDi = 8'h04, // Write Disable: Clear WEL to 0
46: RdSts = 8'h05,
47: WrEn = 8'h06, // Write Enable: Set WEL to 1
48: HsRd = 8'h0B, // 8 cycle gap between addr/ rdata
49: RdSts2 = 8'h35, // Read STATUS2 register
50: DlRd = 8'h3B, // Dual Read
51: QdRd = 8'h6B // Quad Read
52: } spi_rom_cmd_e;
53:
54: endpackage : spi_device_pkg
55: