hw/top_earlgrey/ip/xbar_main/rtl/autogen/xbar_main.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // xbar_main module generated by `tlgen.py` tool
   6: // all reset signals should be generated from one reset signal to not make any deadlock
   7: //
   8: // Interconnect
   9: // corei
  10: //   -> s1n_15
  11: //     -> sm1_16
  12: //       -> rom
  13: //     -> sm1_17
  14: //       -> debug_mem
  15: //     -> sm1_18
  16: //       -> ram_main
  17: //     -> sm1_19
  18: //       -> eflash
  19: // cored
  20: //   -> s1n_20
  21: //     -> sm1_16
  22: //       -> rom
  23: //     -> sm1_17
  24: //       -> debug_mem
  25: //     -> sm1_18
  26: //       -> ram_main
  27: //     -> sm1_19
  28: //       -> eflash
  29: //     -> sm1_22
  30: //       -> asf_21
  31: //         -> peri
  32: //     -> sm1_23
  33: //       -> flash_ctrl
  34: //     -> sm1_24
  35: //       -> aes
  36: //     -> sm1_25
  37: //       -> hmac
  38: //     -> sm1_26
  39: //       -> rv_plic
  40: //     -> sm1_27
  41: //       -> pinmux
  42: //     -> sm1_28
  43: //       -> alert_handler
  44: //     -> sm1_29
  45: //       -> nmi_gen
  46: // dm_sba
  47: //   -> s1n_30
  48: //     -> sm1_16
  49: //       -> rom
  50: //     -> sm1_18
  51: //       -> ram_main
  52: //     -> sm1_19
  53: //       -> eflash
  54: //     -> sm1_22
  55: //       -> asf_21
  56: //         -> peri
  57: //     -> sm1_23
  58: //       -> flash_ctrl
  59: //     -> sm1_24
  60: //       -> aes
  61: //     -> sm1_25
  62: //       -> hmac
  63: //     -> sm1_26
  64: //       -> rv_plic
  65: //     -> sm1_27
  66: //       -> pinmux
  67: //     -> sm1_28
  68: //       -> alert_handler
  69: //     -> sm1_29
  70: //       -> nmi_gen
  71: 
  72: module xbar_main (
  73:   input clk_main_i,
  74:   input clk_fixed_i,
  75:   input rst_main_ni,
  76:   input rst_fixed_ni,
  77: 
  78:   // Host interfaces
  79:   input  tlul_pkg::tl_h2d_t tl_corei_i,
  80:   output tlul_pkg::tl_d2h_t tl_corei_o,
  81:   input  tlul_pkg::tl_h2d_t tl_cored_i,
  82:   output tlul_pkg::tl_d2h_t tl_cored_o,
  83:   input  tlul_pkg::tl_h2d_t tl_dm_sba_i,
  84:   output tlul_pkg::tl_d2h_t tl_dm_sba_o,
  85: 
  86:   // Device interfaces
  87:   output tlul_pkg::tl_h2d_t tl_rom_o,
  88:   input  tlul_pkg::tl_d2h_t tl_rom_i,
  89:   output tlul_pkg::tl_h2d_t tl_debug_mem_o,
  90:   input  tlul_pkg::tl_d2h_t tl_debug_mem_i,
  91:   output tlul_pkg::tl_h2d_t tl_ram_main_o,
  92:   input  tlul_pkg::tl_d2h_t tl_ram_main_i,
  93:   output tlul_pkg::tl_h2d_t tl_eflash_o,
  94:   input  tlul_pkg::tl_d2h_t tl_eflash_i,
  95:   output tlul_pkg::tl_h2d_t tl_peri_o,
  96:   input  tlul_pkg::tl_d2h_t tl_peri_i,
  97:   output tlul_pkg::tl_h2d_t tl_flash_ctrl_o,
  98:   input  tlul_pkg::tl_d2h_t tl_flash_ctrl_i,
  99:   output tlul_pkg::tl_h2d_t tl_hmac_o,
 100:   input  tlul_pkg::tl_d2h_t tl_hmac_i,
 101:   output tlul_pkg::tl_h2d_t tl_aes_o,
 102:   input  tlul_pkg::tl_d2h_t tl_aes_i,
 103:   output tlul_pkg::tl_h2d_t tl_rv_plic_o,
 104:   input  tlul_pkg::tl_d2h_t tl_rv_plic_i,
 105:   output tlul_pkg::tl_h2d_t tl_pinmux_o,
 106:   input  tlul_pkg::tl_d2h_t tl_pinmux_i,
 107:   output tlul_pkg::tl_h2d_t tl_alert_handler_o,
 108:   input  tlul_pkg::tl_d2h_t tl_alert_handler_i,
 109:   output tlul_pkg::tl_h2d_t tl_nmi_gen_o,
 110:   input  tlul_pkg::tl_d2h_t tl_nmi_gen_i,
 111: 
 112:   input scanmode_i
 113: );
 114: 
 115:   import tlul_pkg::*;
 116:   import tl_main_pkg::*;
 117: 
 118:   // scanmode_i is currently not used, but provisioned for future use
 119:   // this assignment prevents lint warnings
 120:   logic unused_scanmode;
 121:   assign unused_scanmode = scanmode_i;
 122: 
 123:   tl_h2d_t tl_s1n_15_us_h2d ;
 124:   tl_d2h_t tl_s1n_15_us_d2h ;
 125: 
 126: 
 127:   tl_h2d_t tl_s1n_15_ds_h2d [4];
 128:   tl_d2h_t tl_s1n_15_ds_d2h [4];
 129: 
 130:   // Create steering signal
 131:   logic [2:0] dev_sel_s1n_15;
 132: 
 133: 
 134:   tl_h2d_t tl_sm1_16_us_h2d [3];
 135:   tl_d2h_t tl_sm1_16_us_d2h [3];
 136: 
 137:   tl_h2d_t tl_sm1_16_ds_h2d ;
 138:   tl_d2h_t tl_sm1_16_ds_d2h ;
 139: 
 140: 
 141:   tl_h2d_t tl_sm1_17_us_h2d [2];
 142:   tl_d2h_t tl_sm1_17_us_d2h [2];
 143: 
 144:   tl_h2d_t tl_sm1_17_ds_h2d ;
 145:   tl_d2h_t tl_sm1_17_ds_d2h ;
 146: 
 147: 
 148:   tl_h2d_t tl_sm1_18_us_h2d [3];
 149:   tl_d2h_t tl_sm1_18_us_d2h [3];
 150: 
 151:   tl_h2d_t tl_sm1_18_ds_h2d ;
 152:   tl_d2h_t tl_sm1_18_ds_d2h ;
 153: 
 154: 
 155:   tl_h2d_t tl_sm1_19_us_h2d [3];
 156:   tl_d2h_t tl_sm1_19_us_d2h [3];
 157: 
 158:   tl_h2d_t tl_sm1_19_ds_h2d ;
 159:   tl_d2h_t tl_sm1_19_ds_d2h ;
 160: 
 161:   tl_h2d_t tl_s1n_20_us_h2d ;
 162:   tl_d2h_t tl_s1n_20_us_d2h ;
 163: 
 164: 
 165:   tl_h2d_t tl_s1n_20_ds_h2d [12];
 166:   tl_d2h_t tl_s1n_20_ds_d2h [12];
 167: 
 168:   // Create steering signal
 169:   logic [3:0] dev_sel_s1n_20;
 170: 
 171:   tl_h2d_t tl_asf_21_us_h2d ;
 172:   tl_d2h_t tl_asf_21_us_d2h ;
 173:   tl_h2d_t tl_asf_21_ds_h2d ;
 174:   tl_d2h_t tl_asf_21_ds_d2h ;
 175: 
 176: 
 177:   tl_h2d_t tl_sm1_22_us_h2d [2];
 178:   tl_d2h_t tl_sm1_22_us_d2h [2];
 179: 
 180:   tl_h2d_t tl_sm1_22_ds_h2d ;
 181:   tl_d2h_t tl_sm1_22_ds_d2h ;
 182: 
 183: 
 184:   tl_h2d_t tl_sm1_23_us_h2d [2];
 185:   tl_d2h_t tl_sm1_23_us_d2h [2];
 186: 
 187:   tl_h2d_t tl_sm1_23_ds_h2d ;
 188:   tl_d2h_t tl_sm1_23_ds_d2h ;
 189: 
 190: 
 191:   tl_h2d_t tl_sm1_24_us_h2d [2];
 192:   tl_d2h_t tl_sm1_24_us_d2h [2];
 193: 
 194:   tl_h2d_t tl_sm1_24_ds_h2d ;
 195:   tl_d2h_t tl_sm1_24_ds_d2h ;
 196: 
 197: 
 198:   tl_h2d_t tl_sm1_25_us_h2d [2];
 199:   tl_d2h_t tl_sm1_25_us_d2h [2];
 200: 
 201:   tl_h2d_t tl_sm1_25_ds_h2d ;
 202:   tl_d2h_t tl_sm1_25_ds_d2h ;
 203: 
 204: 
 205:   tl_h2d_t tl_sm1_26_us_h2d [2];
 206:   tl_d2h_t tl_sm1_26_us_d2h [2];
 207: 
 208:   tl_h2d_t tl_sm1_26_ds_h2d ;
 209:   tl_d2h_t tl_sm1_26_ds_d2h ;
 210: 
 211: 
 212:   tl_h2d_t tl_sm1_27_us_h2d [2];
 213:   tl_d2h_t tl_sm1_27_us_d2h [2];
 214: 
 215:   tl_h2d_t tl_sm1_27_ds_h2d ;
 216:   tl_d2h_t tl_sm1_27_ds_d2h ;
 217: 
 218: 
 219:   tl_h2d_t tl_sm1_28_us_h2d [2];
 220:   tl_d2h_t tl_sm1_28_us_d2h [2];
 221: 
 222:   tl_h2d_t tl_sm1_28_ds_h2d ;
 223:   tl_d2h_t tl_sm1_28_ds_d2h ;
 224: 
 225: 
 226:   tl_h2d_t tl_sm1_29_us_h2d [2];
 227:   tl_d2h_t tl_sm1_29_us_d2h [2];
 228: 
 229:   tl_h2d_t tl_sm1_29_ds_h2d ;
 230:   tl_d2h_t tl_sm1_29_ds_d2h ;
 231: 
 232:   tl_h2d_t tl_s1n_30_us_h2d ;
 233:   tl_d2h_t tl_s1n_30_us_d2h ;
 234: 
 235: 
 236:   tl_h2d_t tl_s1n_30_ds_h2d [11];
 237:   tl_d2h_t tl_s1n_30_ds_d2h [11];
 238: 
 239:   // Create steering signal
 240:   logic [3:0] dev_sel_s1n_30;
 241: 
 242: 
 243: 
 244:   assign tl_sm1_16_us_h2d[0] = tl_s1n_15_ds_h2d[0];
 245:   assign tl_s1n_15_ds_d2h[0] = tl_sm1_16_us_d2h[0];
 246: 
 247:   assign tl_sm1_17_us_h2d[0] = tl_s1n_15_ds_h2d[1];
 248:   assign tl_s1n_15_ds_d2h[1] = tl_sm1_17_us_d2h[0];
 249: 
 250:   assign tl_sm1_18_us_h2d[0] = tl_s1n_15_ds_h2d[2];
 251:   assign tl_s1n_15_ds_d2h[2] = tl_sm1_18_us_d2h[0];
 252: 
 253:   assign tl_sm1_19_us_h2d[0] = tl_s1n_15_ds_h2d[3];
 254:   assign tl_s1n_15_ds_d2h[3] = tl_sm1_19_us_d2h[0];
 255: 
 256:   assign tl_sm1_16_us_h2d[1] = tl_s1n_20_ds_h2d[0];
 257:   assign tl_s1n_20_ds_d2h[0] = tl_sm1_16_us_d2h[1];
 258: 
 259:   assign tl_sm1_17_us_h2d[1] = tl_s1n_20_ds_h2d[1];
 260:   assign tl_s1n_20_ds_d2h[1] = tl_sm1_17_us_d2h[1];
 261: 
 262:   assign tl_sm1_18_us_h2d[1] = tl_s1n_20_ds_h2d[2];
 263:   assign tl_s1n_20_ds_d2h[2] = tl_sm1_18_us_d2h[1];
 264: 
 265:   assign tl_sm1_19_us_h2d[1] = tl_s1n_20_ds_h2d[3];
 266:   assign tl_s1n_20_ds_d2h[3] = tl_sm1_19_us_d2h[1];
 267: 
 268:   assign tl_sm1_22_us_h2d[0] = tl_s1n_20_ds_h2d[4];
 269:   assign tl_s1n_20_ds_d2h[4] = tl_sm1_22_us_d2h[0];
 270: 
 271:   assign tl_sm1_23_us_h2d[0] = tl_s1n_20_ds_h2d[5];
 272:   assign tl_s1n_20_ds_d2h[5] = tl_sm1_23_us_d2h[0];
 273: 
 274:   assign tl_sm1_24_us_h2d[0] = tl_s1n_20_ds_h2d[6];
 275:   assign tl_s1n_20_ds_d2h[6] = tl_sm1_24_us_d2h[0];
 276: 
 277:   assign tl_sm1_25_us_h2d[0] = tl_s1n_20_ds_h2d[7];
 278:   assign tl_s1n_20_ds_d2h[7] = tl_sm1_25_us_d2h[0];
 279: 
 280:   assign tl_sm1_26_us_h2d[0] = tl_s1n_20_ds_h2d[8];
 281:   assign tl_s1n_20_ds_d2h[8] = tl_sm1_26_us_d2h[0];
 282: 
 283:   assign tl_sm1_27_us_h2d[0] = tl_s1n_20_ds_h2d[9];
 284:   assign tl_s1n_20_ds_d2h[9] = tl_sm1_27_us_d2h[0];
 285: 
 286:   assign tl_sm1_28_us_h2d[0] = tl_s1n_20_ds_h2d[10];
 287:   assign tl_s1n_20_ds_d2h[10] = tl_sm1_28_us_d2h[0];
 288: 
 289:   assign tl_sm1_29_us_h2d[0] = tl_s1n_20_ds_h2d[11];
 290:   assign tl_s1n_20_ds_d2h[11] = tl_sm1_29_us_d2h[0];
 291: 
 292:   assign tl_sm1_16_us_h2d[2] = tl_s1n_30_ds_h2d[0];
 293:   assign tl_s1n_30_ds_d2h[0] = tl_sm1_16_us_d2h[2];
 294: 
 295:   assign tl_sm1_18_us_h2d[2] = tl_s1n_30_ds_h2d[1];
 296:   assign tl_s1n_30_ds_d2h[1] = tl_sm1_18_us_d2h[2];
 297: 
 298:   assign tl_sm1_19_us_h2d[2] = tl_s1n_30_ds_h2d[2];
 299:   assign tl_s1n_30_ds_d2h[2] = tl_sm1_19_us_d2h[2];
 300: 
 301:   assign tl_sm1_22_us_h2d[1] = tl_s1n_30_ds_h2d[3];
 302:   assign tl_s1n_30_ds_d2h[3] = tl_sm1_22_us_d2h[1];
 303: 
 304:   assign tl_sm1_23_us_h2d[1] = tl_s1n_30_ds_h2d[4];
 305:   assign tl_s1n_30_ds_d2h[4] = tl_sm1_23_us_d2h[1];
 306: 
 307:   assign tl_sm1_24_us_h2d[1] = tl_s1n_30_ds_h2d[5];
 308:   assign tl_s1n_30_ds_d2h[5] = tl_sm1_24_us_d2h[1];
 309: 
 310:   assign tl_sm1_25_us_h2d[1] = tl_s1n_30_ds_h2d[6];
 311:   assign tl_s1n_30_ds_d2h[6] = tl_sm1_25_us_d2h[1];
 312: 
 313:   assign tl_sm1_26_us_h2d[1] = tl_s1n_30_ds_h2d[7];
 314:   assign tl_s1n_30_ds_d2h[7] = tl_sm1_26_us_d2h[1];
 315: 
 316:   assign tl_sm1_27_us_h2d[1] = tl_s1n_30_ds_h2d[8];
 317:   assign tl_s1n_30_ds_d2h[8] = tl_sm1_27_us_d2h[1];
 318: 
 319:   assign tl_sm1_28_us_h2d[1] = tl_s1n_30_ds_h2d[9];
 320:   assign tl_s1n_30_ds_d2h[9] = tl_sm1_28_us_d2h[1];
 321: 
 322:   assign tl_sm1_29_us_h2d[1] = tl_s1n_30_ds_h2d[10];
 323:   assign tl_s1n_30_ds_d2h[10] = tl_sm1_29_us_d2h[1];
 324: 
 325:   assign tl_s1n_15_us_h2d = tl_corei_i;
 326:   assign tl_corei_o = tl_s1n_15_us_d2h;
 327: 
 328:   assign tl_rom_o = tl_sm1_16_ds_h2d;
 329:   assign tl_sm1_16_ds_d2h = tl_rom_i;
 330: 
 331:   assign tl_debug_mem_o = tl_sm1_17_ds_h2d;
 332:   assign tl_sm1_17_ds_d2h = tl_debug_mem_i;
 333: 
 334:   assign tl_ram_main_o = tl_sm1_18_ds_h2d;
 335:   assign tl_sm1_18_ds_d2h = tl_ram_main_i;
 336: 
 337:   assign tl_eflash_o = tl_sm1_19_ds_h2d;
 338:   assign tl_sm1_19_ds_d2h = tl_eflash_i;
 339: 
 340:   assign tl_s1n_20_us_h2d = tl_cored_i;
 341:   assign tl_cored_o = tl_s1n_20_us_d2h;
 342: 
 343:   assign tl_peri_o = tl_asf_21_ds_h2d;
 344:   assign tl_asf_21_ds_d2h = tl_peri_i;
 345: 
 346:   assign tl_asf_21_us_h2d = tl_sm1_22_ds_h2d;
 347:   assign tl_sm1_22_ds_d2h = tl_asf_21_us_d2h;
 348: 
 349:   assign tl_flash_ctrl_o = tl_sm1_23_ds_h2d;
 350:   assign tl_sm1_23_ds_d2h = tl_flash_ctrl_i;
 351: 
 352:   assign tl_aes_o = tl_sm1_24_ds_h2d;
 353:   assign tl_sm1_24_ds_d2h = tl_aes_i;
 354: 
 355:   assign tl_hmac_o = tl_sm1_25_ds_h2d;
 356:   assign tl_sm1_25_ds_d2h = tl_hmac_i;
 357: 
 358:   assign tl_rv_plic_o = tl_sm1_26_ds_h2d;
 359:   assign tl_sm1_26_ds_d2h = tl_rv_plic_i;
 360: 
 361:   assign tl_pinmux_o = tl_sm1_27_ds_h2d;
 362:   assign tl_sm1_27_ds_d2h = tl_pinmux_i;
 363: 
 364:   assign tl_alert_handler_o = tl_sm1_28_ds_h2d;
 365:   assign tl_sm1_28_ds_d2h = tl_alert_handler_i;
 366: 
 367:   assign tl_nmi_gen_o = tl_sm1_29_ds_h2d;
 368:   assign tl_sm1_29_ds_d2h = tl_nmi_gen_i;
 369: 
 370:   assign tl_s1n_30_us_h2d = tl_dm_sba_i;
 371:   assign tl_dm_sba_o = tl_s1n_30_us_d2h;
 372: 
 373:   always_comb begin
 374:     // default steering to generate error response if address is not within the range
 375:     dev_sel_s1n_15 = 3'd4;
 376:     if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
 377:       dev_sel_s1n_15 = 3'd0;
 378:     
 379:     end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
 380:       dev_sel_s1n_15 = 3'd1;
 381:     
 382:     end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
 383:       dev_sel_s1n_15 = 3'd2;
 384:     
 385:     end else if ((tl_s1n_15_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
 386:       dev_sel_s1n_15 = 3'd3;
 387:     end
 388:   end
 389: 
 390:   always_comb begin
 391:     // default steering to generate error response if address is not within the range
 392:     dev_sel_s1n_20 = 4'd12;
 393:     if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
 394:       dev_sel_s1n_20 = 4'd0;
 395:     
 396:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_DEBUG_MEM)) == ADDR_SPACE_DEBUG_MEM) begin
 397:       dev_sel_s1n_20 = 4'd1;
 398:     
 399:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
 400:       dev_sel_s1n_20 = 4'd2;
 401:     
 402:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
 403:       dev_sel_s1n_20 = 4'd3;
 404:     
 405:     end else if (
 406:       ((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
 407:        (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
 408:       ((tl_s1n_20_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
 409:        (tl_s1n_20_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
 410:     ) begin
 411:       dev_sel_s1n_20 = 4'd4;
 412:     
 413:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
 414:       dev_sel_s1n_20 = 4'd5;
 415:     
 416:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
 417:       dev_sel_s1n_20 = 4'd6;
 418:     
 419:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
 420:       dev_sel_s1n_20 = 4'd7;
 421:     
 422:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
 423:       dev_sel_s1n_20 = 4'd8;
 424:     
 425:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
 426:       dev_sel_s1n_20 = 4'd9;
 427:     
 428:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
 429:       dev_sel_s1n_20 = 4'd10;
 430:     
 431:     end else if ((tl_s1n_20_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
 432:       dev_sel_s1n_20 = 4'd11;
 433:     end
 434:   end
 435: 
 436:   always_comb begin
 437:     // default steering to generate error response if address is not within the range
 438:     dev_sel_s1n_30 = 4'd11;
 439:     if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_ROM)) == ADDR_SPACE_ROM) begin
 440:       dev_sel_s1n_30 = 4'd0;
 441:     
 442:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_RAM_MAIN)) == ADDR_SPACE_RAM_MAIN) begin
 443:       dev_sel_s1n_30 = 4'd1;
 444:     
 445:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_EFLASH)) == ADDR_SPACE_EFLASH) begin
 446:       dev_sel_s1n_30 = 4'd2;
 447:     
 448:     end else if (
 449:       ((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[0] + ADDR_SPACE_PERI[0])) &&
 450:        (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[0])) ||
 451:       ((tl_s1n_30_us_h2d.a_address <= (ADDR_MASK_PERI[1] + ADDR_SPACE_PERI[1])) &&
 452:        (tl_s1n_30_us_h2d.a_address >= ADDR_SPACE_PERI[1]))
 453:     ) begin
 454:       dev_sel_s1n_30 = 4'd3;
 455:     
 456:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_FLASH_CTRL)) == ADDR_SPACE_FLASH_CTRL) begin
 457:       dev_sel_s1n_30 = 4'd4;
 458:     
 459:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_AES)) == ADDR_SPACE_AES) begin
 460:       dev_sel_s1n_30 = 4'd5;
 461:     
 462:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_HMAC)) == ADDR_SPACE_HMAC) begin
 463:       dev_sel_s1n_30 = 4'd6;
 464:     
 465:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_RV_PLIC)) == ADDR_SPACE_RV_PLIC) begin
 466:       dev_sel_s1n_30 = 4'd7;
 467:     
 468:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_PINMUX)) == ADDR_SPACE_PINMUX) begin
 469:       dev_sel_s1n_30 = 4'd8;
 470:     
 471:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_ALERT_HANDLER)) == ADDR_SPACE_ALERT_HANDLER) begin
 472:       dev_sel_s1n_30 = 4'd9;
 473:     
 474:     end else if ((tl_s1n_30_us_h2d.a_address & ~(ADDR_MASK_NMI_GEN)) == ADDR_SPACE_NMI_GEN) begin
 475:       dev_sel_s1n_30 = 4'd10;
 476:     end
 477:   end
 478: 
 479: 
 480:   // Instantiation phase
 481:   tlul_socket_1n #(
 482:     .HReqDepth (4'h0),
 483:     .HRspDepth (4'h0),
 484:     .DReqDepth ({4{4'h0}}),
 485:     .DRspDepth ({4{4'h0}}),
 486:     .N         (4)
 487:   ) u_s1n_15 (
 488:     .clk_i        (clk_main_i),
 489:     .rst_ni       (rst_main_ni),
 490:     .tl_h_i       (tl_s1n_15_us_h2d),
 491:     .tl_h_o       (tl_s1n_15_us_d2h),
 492:     .tl_d_o       (tl_s1n_15_ds_h2d),
 493:     .tl_d_i       (tl_s1n_15_ds_d2h),
 494:     .dev_select   (dev_sel_s1n_15)
 495:   );
 496:   tlul_socket_m1 #(
 497:     .HReqDepth ({3{4'h0}}),
 498:     .HRspDepth ({3{4'h0}}),
 499:     .DReqDepth (4'h0),
 500:     .DRspDepth (4'h0),
 501:     .M         (3)
 502:   ) u_sm1_16 (
 503:     .clk_i        (clk_main_i),
 504:     .rst_ni       (rst_main_ni),
 505:     .tl_h_i       (tl_sm1_16_us_h2d),
 506:     .tl_h_o       (tl_sm1_16_us_d2h),
 507:     .tl_d_o       (tl_sm1_16_ds_h2d),
 508:     .tl_d_i       (tl_sm1_16_ds_d2h)
 509:   );
 510:   tlul_socket_m1 #(
 511:     .HReqPass  (2'h0),
 512:     .HRspPass  (2'h0),
 513:     .DReqPass  (1'b0),
 514:     .DRspPass  (1'b0),
 515:     .M         (2)
 516:   ) u_sm1_17 (
 517:     .clk_i        (clk_main_i),
 518:     .rst_ni       (rst_main_ni),
 519:     .tl_h_i       (tl_sm1_17_us_h2d),
 520:     .tl_h_o       (tl_sm1_17_us_d2h),
 521:     .tl_d_o       (tl_sm1_17_ds_h2d),
 522:     .tl_d_i       (tl_sm1_17_ds_d2h)
 523:   );
 524:   tlul_socket_m1 #(
 525:     .HReqDepth ({3{4'h0}}),
 526:     .HRspDepth ({3{4'h0}}),
 527:     .DReqDepth (4'h0),
 528:     .DRspDepth (4'h0),
 529:     .M         (3)
 530:   ) u_sm1_18 (
 531:     .clk_i        (clk_main_i),
 532:     .rst_ni       (rst_main_ni),
 533:     .tl_h_i       (tl_sm1_18_us_h2d),
 534:     .tl_h_o       (tl_sm1_18_us_d2h),
 535:     .tl_d_o       (tl_sm1_18_ds_h2d),
 536:     .tl_d_i       (tl_sm1_18_ds_d2h)
 537:   );
 538:   tlul_socket_m1 #(
 539:     .HReqDepth ({3{4'h0}}),
 540:     .HRspDepth ({3{4'h0}}),
 541:     .DReqDepth (4'h0),
 542:     .DRspDepth (4'h0),
 543:     .M         (3)
 544:   ) u_sm1_19 (
 545:     .clk_i        (clk_main_i),
 546:     .rst_ni       (rst_main_ni),
 547:     .tl_h_i       (tl_sm1_19_us_h2d),
 548:     .tl_h_o       (tl_sm1_19_us_d2h),
 549:     .tl_d_o       (tl_sm1_19_ds_h2d),
 550:     .tl_d_i       (tl_sm1_19_ds_d2h)
 551:   );
 552:   tlul_socket_1n #(
 553:     .HReqDepth (4'h0),
 554:     .HRspDepth (4'h0),
 555:     .DReqDepth ({12{4'h0}}),
 556:     .DRspDepth ({12{4'h0}}),
 557:     .N         (12)
 558:   ) u_s1n_20 (
 559:     .clk_i        (clk_main_i),
 560:     .rst_ni       (rst_main_ni),
 561:     .tl_h_i       (tl_s1n_20_us_h2d),
 562:     .tl_h_o       (tl_s1n_20_us_d2h),
 563:     .tl_d_o       (tl_s1n_20_ds_h2d),
 564:     .tl_d_i       (tl_s1n_20_ds_d2h),
 565:     .dev_select   (dev_sel_s1n_20)
 566:   );
 567:   tlul_fifo_async #(
 568:     .ReqDepth        (3),// At least 3 to make async work
 569:     .RspDepth        (3) // At least 3 to make async work
 570:   ) u_asf_21 (
 571:     .clk_h_i      (clk_main_i),
 572:     .rst_h_ni     (rst_main_ni),
 573:     .clk_d_i      (clk_fixed_i),
 574:     .rst_d_ni     (rst_fixed_ni),
 575:     .tl_h_i       (tl_asf_21_us_h2d),
 576:     .tl_h_o       (tl_asf_21_us_d2h),
 577:     .tl_d_o       (tl_asf_21_ds_h2d),
 578:     .tl_d_i       (tl_asf_21_ds_d2h)
 579:   );
 580:   tlul_socket_m1 #(
 581:     .M         (2)
 582:   ) u_sm1_22 (
 583:     .clk_i        (clk_main_i),
 584:     .rst_ni       (rst_main_ni),
 585:     .tl_h_i       (tl_sm1_22_us_h2d),
 586:     .tl_h_o       (tl_sm1_22_us_d2h),
 587:     .tl_d_o       (tl_sm1_22_ds_h2d),
 588:     .tl_d_i       (tl_sm1_22_ds_d2h)
 589:   );
 590:   tlul_socket_m1 #(
 591:     .HReqPass  (2'h0),
 592:     .HRspPass  (2'h0),
 593:     .DReqPass  (1'b0),
 594:     .DRspPass  (1'b0),
 595:     .M         (2)
 596:   ) u_sm1_23 (
 597:     .clk_i        (clk_main_i),
 598:     .rst_ni       (rst_main_ni),
 599:     .tl_h_i       (tl_sm1_23_us_h2d),
 600:     .tl_h_o       (tl_sm1_23_us_d2h),
 601:     .tl_d_o       (tl_sm1_23_ds_h2d),
 602:     .tl_d_i       (tl_sm1_23_ds_d2h)
 603:   );
 604:   tlul_socket_m1 #(
 605:     .HReqPass  (2'h0),
 606:     .HRspPass  (2'h0),
 607:     .DReqPass  (1'b0),
 608:     .DRspPass  (1'b0),
 609:     .M         (2)
 610:   ) u_sm1_24 (
 611:     .clk_i        (clk_main_i),
 612:     .rst_ni       (rst_main_ni),
 613:     .tl_h_i       (tl_sm1_24_us_h2d),
 614:     .tl_h_o       (tl_sm1_24_us_d2h),
 615:     .tl_d_o       (tl_sm1_24_ds_h2d),
 616:     .tl_d_i       (tl_sm1_24_ds_d2h)
 617:   );
 618:   tlul_socket_m1 #(
 619:     .HReqPass  (2'h0),
 620:     .HRspPass  (2'h0),
 621:     .DReqPass  (1'b0),
 622:     .DRspPass  (1'b0),
 623:     .M         (2)
 624:   ) u_sm1_25 (
 625:     .clk_i        (clk_main_i),
 626:     .rst_ni       (rst_main_ni),
 627:     .tl_h_i       (tl_sm1_25_us_h2d),
 628:     .tl_h_o       (tl_sm1_25_us_d2h),
 629:     .tl_d_o       (tl_sm1_25_ds_h2d),
 630:     .tl_d_i       (tl_sm1_25_ds_d2h)
 631:   );
 632:   tlul_socket_m1 #(
 633:     .HReqPass  (2'h0),
 634:     .HRspPass  (2'h0),
 635:     .DReqPass  (1'b0),
 636:     .DRspPass  (1'b0),
 637:     .M         (2)
 638:   ) u_sm1_26 (
 639:     .clk_i        (clk_main_i),
 640:     .rst_ni       (rst_main_ni),
 641:     .tl_h_i       (tl_sm1_26_us_h2d),
 642:     .tl_h_o       (tl_sm1_26_us_d2h),
 643:     .tl_d_o       (tl_sm1_26_ds_h2d),
 644:     .tl_d_i       (tl_sm1_26_ds_d2h)
 645:   );
 646:   tlul_socket_m1 #(
 647:     .HReqPass  (2'h0),
 648:     .HRspPass  (2'h0),
 649:     .DReqPass  (1'b0),
 650:     .DRspPass  (1'b0),
 651:     .M         (2)
 652:   ) u_sm1_27 (
 653:     .clk_i        (clk_main_i),
 654:     .rst_ni       (rst_main_ni),
 655:     .tl_h_i       (tl_sm1_27_us_h2d),
 656:     .tl_h_o       (tl_sm1_27_us_d2h),
 657:     .tl_d_o       (tl_sm1_27_ds_h2d),
 658:     .tl_d_i       (tl_sm1_27_ds_d2h)
 659:   );
 660:   tlul_socket_m1 #(
 661:     .HReqPass  (2'h0),
 662:     .HRspPass  (2'h0),
 663:     .DReqPass  (1'b0),
 664:     .DRspPass  (1'b0),
 665:     .M         (2)
 666:   ) u_sm1_28 (
 667:     .clk_i        (clk_main_i),
 668:     .rst_ni       (rst_main_ni),
 669:     .tl_h_i       (tl_sm1_28_us_h2d),
 670:     .tl_h_o       (tl_sm1_28_us_d2h),
 671:     .tl_d_o       (tl_sm1_28_ds_h2d),
 672:     .tl_d_i       (tl_sm1_28_ds_d2h)
 673:   );
 674:   tlul_socket_m1 #(
 675:     .HReqPass  (2'h0),
 676:     .HRspPass  (2'h0),
 677:     .DReqPass  (1'b0),
 678:     .DRspPass  (1'b0),
 679:     .M         (2)
 680:   ) u_sm1_29 (
 681:     .clk_i        (clk_main_i),
 682:     .rst_ni       (rst_main_ni),
 683:     .tl_h_i       (tl_sm1_29_us_h2d),
 684:     .tl_h_o       (tl_sm1_29_us_d2h),
 685:     .tl_d_o       (tl_sm1_29_ds_h2d),
 686:     .tl_d_i       (tl_sm1_29_ds_d2h)
 687:   );
 688:   tlul_socket_1n #(
 689:     .HReqPass  (1'b0),
 690:     .HRspPass  (1'b0),
 691:     .DReqPass  (11'h0),
 692:     .DRspPass  (11'h0),
 693:     .N         (11)
 694:   ) u_s1n_30 (
 695:     .clk_i        (clk_main_i),
 696:     .rst_ni       (rst_main_ni),
 697:     .tl_h_i       (tl_s1n_30_us_h2d),
 698:     .tl_h_o       (tl_s1n_30_us_d2h),
 699:     .tl_d_o       (tl_s1n_30_ds_h2d),
 700:     .tl_d_i       (tl_s1n_30_ds_d2h),
 701:     .dev_select   (dev_sel_s1n_30)
 702:   );
 703: 
 704: endmodule
 705: