hw/ip/prim/abstract/prim_clock_gating.sv Cov: 68.4%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: // TODO: This module is a hard-coded stopgap to select an implementation of an
   6: // "abstract module". This module is to be replaced by generated code.
   7: 
   8: `ifndef PRIM_DEFAULT_IMPL
   9:   `define PRIM_DEFAULT_IMPL prim_pkg::ImplGeneric
  10: `endif
  11: 
  12: module prim_clock_gating #(
  13:   parameter prim_pkg::impl_e Impl = `PRIM_DEFAULT_IMPL
  14: ) (
  15:   input        clk_i,
  16:   input        en_i,
  17:   input        test_en_i,
  18:   output logic clk_o
  19: );
  20: 
  21:   import prim_pkg::*;
  22: 
  23:   if (Impl == ImplGeneric) begin : gen_generic
  24:     prim_generic_clock_gating u_impl_generic (
  25:       .clk_i,
  26:       .en_i,
  27:       .test_en_i,
  28:       .clk_o
  29:     );
  30:   end else if (Impl == ImplXilinx) begin : gen_xilinx
  31:     prim_xilinx_clock_gating u_impl_xilinx (
  32:       .clk_i,
  33:       .en_i,
  34:       .test_en_i,
  35:       .clk_o
  36:     );
  37:   end else begin : gen_failure
  38:     // TODO: Find code that works across tools and causes a compile failure
  39:   end
  40: 
  41: endmodule
  42: