../src/lowrisc_top_earlgrey_rv_plic_0.1/rtl/autogen/rv_plic_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package rv_plic_reg_pkg;
8:
9: // Param list
10: parameter int NumSrc = 81;
11: parameter int NumTarget = 1;
12:
13: ////////////////////////////
14: // Typedefs for registers //
15: ////////////////////////////
16: typedef struct packed {
17: logic q;
18: } rv_plic_reg2hw_le_mreg_t;
19:
20: typedef struct packed {
21: logic [1:0] q;
22: } rv_plic_reg2hw_prio0_reg_t;
23:
24: typedef struct packed {
25: logic [1:0] q;
26: } rv_plic_reg2hw_prio1_reg_t;
27:
28: typedef struct packed {
29: logic [1:0] q;
30: } rv_plic_reg2hw_prio2_reg_t;
31:
32: typedef struct packed {
33: logic [1:0] q;
34: } rv_plic_reg2hw_prio3_reg_t;
35:
36: typedef struct packed {
37: logic [1:0] q;
38: } rv_plic_reg2hw_prio4_reg_t;
39:
40: typedef struct packed {
41: logic [1:0] q;
42: } rv_plic_reg2hw_prio5_reg_t;
43:
44: typedef struct packed {
45: logic [1:0] q;
46: } rv_plic_reg2hw_prio6_reg_t;
47:
48: typedef struct packed {
49: logic [1:0] q;
50: } rv_plic_reg2hw_prio7_reg_t;
51:
52: typedef struct packed {
53: logic [1:0] q;
54: } rv_plic_reg2hw_prio8_reg_t;
55:
56: typedef struct packed {
57: logic [1:0] q;
58: } rv_plic_reg2hw_prio9_reg_t;
59:
60: typedef struct packed {
61: logic [1:0] q;
62: } rv_plic_reg2hw_prio10_reg_t;
63:
64: typedef struct packed {
65: logic [1:0] q;
66: } rv_plic_reg2hw_prio11_reg_t;
67:
68: typedef struct packed {
69: logic [1:0] q;
70: } rv_plic_reg2hw_prio12_reg_t;
71:
72: typedef struct packed {
73: logic [1:0] q;
74: } rv_plic_reg2hw_prio13_reg_t;
75:
76: typedef struct packed {
77: logic [1:0] q;
78: } rv_plic_reg2hw_prio14_reg_t;
79:
80: typedef struct packed {
81: logic [1:0] q;
82: } rv_plic_reg2hw_prio15_reg_t;
83:
84: typedef struct packed {
85: logic [1:0] q;
86: } rv_plic_reg2hw_prio16_reg_t;
87:
88: typedef struct packed {
89: logic [1:0] q;
90: } rv_plic_reg2hw_prio17_reg_t;
91:
92: typedef struct packed {
93: logic [1:0] q;
94: } rv_plic_reg2hw_prio18_reg_t;
95:
96: typedef struct packed {
97: logic [1:0] q;
98: } rv_plic_reg2hw_prio19_reg_t;
99:
100: typedef struct packed {
101: logic [1:0] q;
102: } rv_plic_reg2hw_prio20_reg_t;
103:
104: typedef struct packed {
105: logic [1:0] q;
106: } rv_plic_reg2hw_prio21_reg_t;
107:
108: typedef struct packed {
109: logic [1:0] q;
110: } rv_plic_reg2hw_prio22_reg_t;
111:
112: typedef struct packed {
113: logic [1:0] q;
114: } rv_plic_reg2hw_prio23_reg_t;
115:
116: typedef struct packed {
117: logic [1:0] q;
118: } rv_plic_reg2hw_prio24_reg_t;
119:
120: typedef struct packed {
121: logic [1:0] q;
122: } rv_plic_reg2hw_prio25_reg_t;
123:
124: typedef struct packed {
125: logic [1:0] q;
126: } rv_plic_reg2hw_prio26_reg_t;
127:
128: typedef struct packed {
129: logic [1:0] q;
130: } rv_plic_reg2hw_prio27_reg_t;
131:
132: typedef struct packed {
133: logic [1:0] q;
134: } rv_plic_reg2hw_prio28_reg_t;
135:
136: typedef struct packed {
137: logic [1:0] q;
138: } rv_plic_reg2hw_prio29_reg_t;
139:
140: typedef struct packed {
141: logic [1:0] q;
142: } rv_plic_reg2hw_prio30_reg_t;
143:
144: typedef struct packed {
145: logic [1:0] q;
146: } rv_plic_reg2hw_prio31_reg_t;
147:
148: typedef struct packed {
149: logic [1:0] q;
150: } rv_plic_reg2hw_prio32_reg_t;
151:
152: typedef struct packed {
153: logic [1:0] q;
154: } rv_plic_reg2hw_prio33_reg_t;
155:
156: typedef struct packed {
157: logic [1:0] q;
158: } rv_plic_reg2hw_prio34_reg_t;
159:
160: typedef struct packed {
161: logic [1:0] q;
162: } rv_plic_reg2hw_prio35_reg_t;
163:
164: typedef struct packed {
165: logic [1:0] q;
166: } rv_plic_reg2hw_prio36_reg_t;
167:
168: typedef struct packed {
169: logic [1:0] q;
170: } rv_plic_reg2hw_prio37_reg_t;
171:
172: typedef struct packed {
173: logic [1:0] q;
174: } rv_plic_reg2hw_prio38_reg_t;
175:
176: typedef struct packed {
177: logic [1:0] q;
178: } rv_plic_reg2hw_prio39_reg_t;
179:
180: typedef struct packed {
181: logic [1:0] q;
182: } rv_plic_reg2hw_prio40_reg_t;
183:
184: typedef struct packed {
185: logic [1:0] q;
186: } rv_plic_reg2hw_prio41_reg_t;
187:
188: typedef struct packed {
189: logic [1:0] q;
190: } rv_plic_reg2hw_prio42_reg_t;
191:
192: typedef struct packed {
193: logic [1:0] q;
194: } rv_plic_reg2hw_prio43_reg_t;
195:
196: typedef struct packed {
197: logic [1:0] q;
198: } rv_plic_reg2hw_prio44_reg_t;
199:
200: typedef struct packed {
201: logic [1:0] q;
202: } rv_plic_reg2hw_prio45_reg_t;
203:
204: typedef struct packed {
205: logic [1:0] q;
206: } rv_plic_reg2hw_prio46_reg_t;
207:
208: typedef struct packed {
209: logic [1:0] q;
210: } rv_plic_reg2hw_prio47_reg_t;
211:
212: typedef struct packed {
213: logic [1:0] q;
214: } rv_plic_reg2hw_prio48_reg_t;
215:
216: typedef struct packed {
217: logic [1:0] q;
218: } rv_plic_reg2hw_prio49_reg_t;
219:
220: typedef struct packed {
221: logic [1:0] q;
222: } rv_plic_reg2hw_prio50_reg_t;
223:
224: typedef struct packed {
225: logic [1:0] q;
226: } rv_plic_reg2hw_prio51_reg_t;
227:
228: typedef struct packed {
229: logic [1:0] q;
230: } rv_plic_reg2hw_prio52_reg_t;
231:
232: typedef struct packed {
233: logic [1:0] q;
234: } rv_plic_reg2hw_prio53_reg_t;
235:
236: typedef struct packed {
237: logic [1:0] q;
238: } rv_plic_reg2hw_prio54_reg_t;
239:
240: typedef struct packed {
241: logic [1:0] q;
242: } rv_plic_reg2hw_prio55_reg_t;
243:
244: typedef struct packed {
245: logic [1:0] q;
246: } rv_plic_reg2hw_prio56_reg_t;
247:
248: typedef struct packed {
249: logic [1:0] q;
250: } rv_plic_reg2hw_prio57_reg_t;
251:
252: typedef struct packed {
253: logic [1:0] q;
254: } rv_plic_reg2hw_prio58_reg_t;
255:
256: typedef struct packed {
257: logic [1:0] q;
258: } rv_plic_reg2hw_prio59_reg_t;
259:
260: typedef struct packed {
261: logic [1:0] q;
262: } rv_plic_reg2hw_prio60_reg_t;
263:
264: typedef struct packed {
265: logic [1:0] q;
266: } rv_plic_reg2hw_prio61_reg_t;
267:
268: typedef struct packed {
269: logic [1:0] q;
270: } rv_plic_reg2hw_prio62_reg_t;
271:
272: typedef struct packed {
273: logic [1:0] q;
274: } rv_plic_reg2hw_prio63_reg_t;
275:
276: typedef struct packed {
277: logic [1:0] q;
278: } rv_plic_reg2hw_prio64_reg_t;
279:
280: typedef struct packed {
281: logic [1:0] q;
282: } rv_plic_reg2hw_prio65_reg_t;
283:
284: typedef struct packed {
285: logic [1:0] q;
286: } rv_plic_reg2hw_prio66_reg_t;
287:
288: typedef struct packed {
289: logic [1:0] q;
290: } rv_plic_reg2hw_prio67_reg_t;
291:
292: typedef struct packed {
293: logic [1:0] q;
294: } rv_plic_reg2hw_prio68_reg_t;
295:
296: typedef struct packed {
297: logic [1:0] q;
298: } rv_plic_reg2hw_prio69_reg_t;
299:
300: typedef struct packed {
301: logic [1:0] q;
302: } rv_plic_reg2hw_prio70_reg_t;
303:
304: typedef struct packed {
305: logic [1:0] q;
306: } rv_plic_reg2hw_prio71_reg_t;
307:
308: typedef struct packed {
309: logic [1:0] q;
310: } rv_plic_reg2hw_prio72_reg_t;
311:
312: typedef struct packed {
313: logic [1:0] q;
314: } rv_plic_reg2hw_prio73_reg_t;
315:
316: typedef struct packed {
317: logic [1:0] q;
318: } rv_plic_reg2hw_prio74_reg_t;
319:
320: typedef struct packed {
321: logic [1:0] q;
322: } rv_plic_reg2hw_prio75_reg_t;
323:
324: typedef struct packed {
325: logic [1:0] q;
326: } rv_plic_reg2hw_prio76_reg_t;
327:
328: typedef struct packed {
329: logic [1:0] q;
330: } rv_plic_reg2hw_prio77_reg_t;
331:
332: typedef struct packed {
333: logic [1:0] q;
334: } rv_plic_reg2hw_prio78_reg_t;
335:
336: typedef struct packed {
337: logic [1:0] q;
338: } rv_plic_reg2hw_prio79_reg_t;
339:
340: typedef struct packed {
341: logic [1:0] q;
342: } rv_plic_reg2hw_prio80_reg_t;
343:
344: typedef struct packed {
345: logic q;
346: } rv_plic_reg2hw_ie0_mreg_t;
347:
348: typedef struct packed {
349: logic [1:0] q;
350: } rv_plic_reg2hw_threshold0_reg_t;
351:
352: typedef struct packed {
353: logic [6:0] q;
354: logic qe;
355: logic re;
356: } rv_plic_reg2hw_cc0_reg_t;
357:
358: typedef struct packed {
359: logic q;
360: } rv_plic_reg2hw_msip0_reg_t;
361:
362:
363: typedef struct packed {
364: logic d;
365: logic de;
366: } rv_plic_hw2reg_ip_mreg_t;
367:
368: typedef struct packed {
369: logic [6:0] d;
370: } rv_plic_hw2reg_cc0_reg_t;
371:
372:
373: ///////////////////////////////////////
374: // Register to internal design logic //
375: ///////////////////////////////////////
376: typedef struct packed {
377: rv_plic_reg2hw_le_mreg_t [80:0] le; // [335:255]
378: rv_plic_reg2hw_prio0_reg_t prio0; // [254:253]
379: rv_plic_reg2hw_prio1_reg_t prio1; // [252:251]
380: rv_plic_reg2hw_prio2_reg_t prio2; // [250:249]
381: rv_plic_reg2hw_prio3_reg_t prio3; // [248:247]
382: rv_plic_reg2hw_prio4_reg_t prio4; // [246:245]
383: rv_plic_reg2hw_prio5_reg_t prio5; // [244:243]
384: rv_plic_reg2hw_prio6_reg_t prio6; // [242:241]
385: rv_plic_reg2hw_prio7_reg_t prio7; // [240:239]
386: rv_plic_reg2hw_prio8_reg_t prio8; // [238:237]
387: rv_plic_reg2hw_prio9_reg_t prio9; // [236:235]
388: rv_plic_reg2hw_prio10_reg_t prio10; // [234:233]
389: rv_plic_reg2hw_prio11_reg_t prio11; // [232:231]
390: rv_plic_reg2hw_prio12_reg_t prio12; // [230:229]
391: rv_plic_reg2hw_prio13_reg_t prio13; // [228:227]
392: rv_plic_reg2hw_prio14_reg_t prio14; // [226:225]
393: rv_plic_reg2hw_prio15_reg_t prio15; // [224:223]
394: rv_plic_reg2hw_prio16_reg_t prio16; // [222:221]
395: rv_plic_reg2hw_prio17_reg_t prio17; // [220:219]
396: rv_plic_reg2hw_prio18_reg_t prio18; // [218:217]
397: rv_plic_reg2hw_prio19_reg_t prio19; // [216:215]
398: rv_plic_reg2hw_prio20_reg_t prio20; // [214:213]
399: rv_plic_reg2hw_prio21_reg_t prio21; // [212:211]
400: rv_plic_reg2hw_prio22_reg_t prio22; // [210:209]
401: rv_plic_reg2hw_prio23_reg_t prio23; // [208:207]
402: rv_plic_reg2hw_prio24_reg_t prio24; // [206:205]
403: rv_plic_reg2hw_prio25_reg_t prio25; // [204:203]
404: rv_plic_reg2hw_prio26_reg_t prio26; // [202:201]
405: rv_plic_reg2hw_prio27_reg_t prio27; // [200:199]
406: rv_plic_reg2hw_prio28_reg_t prio28; // [198:197]
407: rv_plic_reg2hw_prio29_reg_t prio29; // [196:195]
408: rv_plic_reg2hw_prio30_reg_t prio30; // [194:193]
409: rv_plic_reg2hw_prio31_reg_t prio31; // [192:191]
410: rv_plic_reg2hw_prio32_reg_t prio32; // [190:189]
411: rv_plic_reg2hw_prio33_reg_t prio33; // [188:187]
412: rv_plic_reg2hw_prio34_reg_t prio34; // [186:185]
413: rv_plic_reg2hw_prio35_reg_t prio35; // [184:183]
414: rv_plic_reg2hw_prio36_reg_t prio36; // [182:181]
415: rv_plic_reg2hw_prio37_reg_t prio37; // [180:179]
416: rv_plic_reg2hw_prio38_reg_t prio38; // [178:177]
417: rv_plic_reg2hw_prio39_reg_t prio39; // [176:175]
418: rv_plic_reg2hw_prio40_reg_t prio40; // [174:173]
419: rv_plic_reg2hw_prio41_reg_t prio41; // [172:171]
420: rv_plic_reg2hw_prio42_reg_t prio42; // [170:169]
421: rv_plic_reg2hw_prio43_reg_t prio43; // [168:167]
422: rv_plic_reg2hw_prio44_reg_t prio44; // [166:165]
423: rv_plic_reg2hw_prio45_reg_t prio45; // [164:163]
424: rv_plic_reg2hw_prio46_reg_t prio46; // [162:161]
425: rv_plic_reg2hw_prio47_reg_t prio47; // [160:159]
426: rv_plic_reg2hw_prio48_reg_t prio48; // [158:157]
427: rv_plic_reg2hw_prio49_reg_t prio49; // [156:155]
428: rv_plic_reg2hw_prio50_reg_t prio50; // [154:153]
429: rv_plic_reg2hw_prio51_reg_t prio51; // [152:151]
430: rv_plic_reg2hw_prio52_reg_t prio52; // [150:149]
431: rv_plic_reg2hw_prio53_reg_t prio53; // [148:147]
432: rv_plic_reg2hw_prio54_reg_t prio54; // [146:145]
433: rv_plic_reg2hw_prio55_reg_t prio55; // [144:143]
434: rv_plic_reg2hw_prio56_reg_t prio56; // [142:141]
435: rv_plic_reg2hw_prio57_reg_t prio57; // [140:139]
436: rv_plic_reg2hw_prio58_reg_t prio58; // [138:137]
437: rv_plic_reg2hw_prio59_reg_t prio59; // [136:135]
438: rv_plic_reg2hw_prio60_reg_t prio60; // [134:133]
439: rv_plic_reg2hw_prio61_reg_t prio61; // [132:131]
440: rv_plic_reg2hw_prio62_reg_t prio62; // [130:129]
441: rv_plic_reg2hw_prio63_reg_t prio63; // [128:127]
442: rv_plic_reg2hw_prio64_reg_t prio64; // [126:125]
443: rv_plic_reg2hw_prio65_reg_t prio65; // [124:123]
444: rv_plic_reg2hw_prio66_reg_t prio66; // [122:121]
445: rv_plic_reg2hw_prio67_reg_t prio67; // [120:119]
446: rv_plic_reg2hw_prio68_reg_t prio68; // [118:117]
447: rv_plic_reg2hw_prio69_reg_t prio69; // [116:115]
448: rv_plic_reg2hw_prio70_reg_t prio70; // [114:113]
449: rv_plic_reg2hw_prio71_reg_t prio71; // [112:111]
450: rv_plic_reg2hw_prio72_reg_t prio72; // [110:109]
451: rv_plic_reg2hw_prio73_reg_t prio73; // [108:107]
452: rv_plic_reg2hw_prio74_reg_t prio74; // [106:105]
453: rv_plic_reg2hw_prio75_reg_t prio75; // [104:103]
454: rv_plic_reg2hw_prio76_reg_t prio76; // [102:101]
455: rv_plic_reg2hw_prio77_reg_t prio77; // [100:99]
456: rv_plic_reg2hw_prio78_reg_t prio78; // [98:97]
457: rv_plic_reg2hw_prio79_reg_t prio79; // [96:95]
458: rv_plic_reg2hw_prio80_reg_t prio80; // [94:93]
459: rv_plic_reg2hw_ie0_mreg_t [80:0] ie0; // [92:12]
460: rv_plic_reg2hw_threshold0_reg_t threshold0; // [11:10]
461: rv_plic_reg2hw_cc0_reg_t cc0; // [9:1]
462: rv_plic_reg2hw_msip0_reg_t msip0; // [0:0]
463: } rv_plic_reg2hw_t;
464:
465: ///////////////////////////////////////
466: // Internal design logic to register //
467: ///////////////////////////////////////
468: typedef struct packed {
469: rv_plic_hw2reg_ip_mreg_t [80:0] ip; // [168:7]
470: rv_plic_hw2reg_cc0_reg_t cc0; // [6:-2]
471: } rv_plic_hw2reg_t;
472:
473: // Register Address
474: parameter logic [9:0] RV_PLIC_IP0_OFFSET = 10'h 0;
475: parameter logic [9:0] RV_PLIC_IP1_OFFSET = 10'h 4;
476: parameter logic [9:0] RV_PLIC_IP2_OFFSET = 10'h 8;
477: parameter logic [9:0] RV_PLIC_LE0_OFFSET = 10'h c;
478: parameter logic [9:0] RV_PLIC_LE1_OFFSET = 10'h 10;
479: parameter logic [9:0] RV_PLIC_LE2_OFFSET = 10'h 14;
480: parameter logic [9:0] RV_PLIC_PRIO0_OFFSET = 10'h 18;
481: parameter logic [9:0] RV_PLIC_PRIO1_OFFSET = 10'h 1c;
482: parameter logic [9:0] RV_PLIC_PRIO2_OFFSET = 10'h 20;
483: parameter logic [9:0] RV_PLIC_PRIO3_OFFSET = 10'h 24;
484: parameter logic [9:0] RV_PLIC_PRIO4_OFFSET = 10'h 28;
485: parameter logic [9:0] RV_PLIC_PRIO5_OFFSET = 10'h 2c;
486: parameter logic [9:0] RV_PLIC_PRIO6_OFFSET = 10'h 30;
487: parameter logic [9:0] RV_PLIC_PRIO7_OFFSET = 10'h 34;
488: parameter logic [9:0] RV_PLIC_PRIO8_OFFSET = 10'h 38;
489: parameter logic [9:0] RV_PLIC_PRIO9_OFFSET = 10'h 3c;
490: parameter logic [9:0] RV_PLIC_PRIO10_OFFSET = 10'h 40;
491: parameter logic [9:0] RV_PLIC_PRIO11_OFFSET = 10'h 44;
492: parameter logic [9:0] RV_PLIC_PRIO12_OFFSET = 10'h 48;
493: parameter logic [9:0] RV_PLIC_PRIO13_OFFSET = 10'h 4c;
494: parameter logic [9:0] RV_PLIC_PRIO14_OFFSET = 10'h 50;
495: parameter logic [9:0] RV_PLIC_PRIO15_OFFSET = 10'h 54;
496: parameter logic [9:0] RV_PLIC_PRIO16_OFFSET = 10'h 58;
497: parameter logic [9:0] RV_PLIC_PRIO17_OFFSET = 10'h 5c;
498: parameter logic [9:0] RV_PLIC_PRIO18_OFFSET = 10'h 60;
499: parameter logic [9:0] RV_PLIC_PRIO19_OFFSET = 10'h 64;
500: parameter logic [9:0] RV_PLIC_PRIO20_OFFSET = 10'h 68;
501: parameter logic [9:0] RV_PLIC_PRIO21_OFFSET = 10'h 6c;
502: parameter logic [9:0] RV_PLIC_PRIO22_OFFSET = 10'h 70;
503: parameter logic [9:0] RV_PLIC_PRIO23_OFFSET = 10'h 74;
504: parameter logic [9:0] RV_PLIC_PRIO24_OFFSET = 10'h 78;
505: parameter logic [9:0] RV_PLIC_PRIO25_OFFSET = 10'h 7c;
506: parameter logic [9:0] RV_PLIC_PRIO26_OFFSET = 10'h 80;
507: parameter logic [9:0] RV_PLIC_PRIO27_OFFSET = 10'h 84;
508: parameter logic [9:0] RV_PLIC_PRIO28_OFFSET = 10'h 88;
509: parameter logic [9:0] RV_PLIC_PRIO29_OFFSET = 10'h 8c;
510: parameter logic [9:0] RV_PLIC_PRIO30_OFFSET = 10'h 90;
511: parameter logic [9:0] RV_PLIC_PRIO31_OFFSET = 10'h 94;
512: parameter logic [9:0] RV_PLIC_PRIO32_OFFSET = 10'h 98;
513: parameter logic [9:0] RV_PLIC_PRIO33_OFFSET = 10'h 9c;
514: parameter logic [9:0] RV_PLIC_PRIO34_OFFSET = 10'h a0;
515: parameter logic [9:0] RV_PLIC_PRIO35_OFFSET = 10'h a4;
516: parameter logic [9:0] RV_PLIC_PRIO36_OFFSET = 10'h a8;
517: parameter logic [9:0] RV_PLIC_PRIO37_OFFSET = 10'h ac;
518: parameter logic [9:0] RV_PLIC_PRIO38_OFFSET = 10'h b0;
519: parameter logic [9:0] RV_PLIC_PRIO39_OFFSET = 10'h b4;
520: parameter logic [9:0] RV_PLIC_PRIO40_OFFSET = 10'h b8;
521: parameter logic [9:0] RV_PLIC_PRIO41_OFFSET = 10'h bc;
522: parameter logic [9:0] RV_PLIC_PRIO42_OFFSET = 10'h c0;
523: parameter logic [9:0] RV_PLIC_PRIO43_OFFSET = 10'h c4;
524: parameter logic [9:0] RV_PLIC_PRIO44_OFFSET = 10'h c8;
525: parameter logic [9:0] RV_PLIC_PRIO45_OFFSET = 10'h cc;
526: parameter logic [9:0] RV_PLIC_PRIO46_OFFSET = 10'h d0;
527: parameter logic [9:0] RV_PLIC_PRIO47_OFFSET = 10'h d4;
528: parameter logic [9:0] RV_PLIC_PRIO48_OFFSET = 10'h d8;
529: parameter logic [9:0] RV_PLIC_PRIO49_OFFSET = 10'h dc;
530: parameter logic [9:0] RV_PLIC_PRIO50_OFFSET = 10'h e0;
531: parameter logic [9:0] RV_PLIC_PRIO51_OFFSET = 10'h e4;
532: parameter logic [9:0] RV_PLIC_PRIO52_OFFSET = 10'h e8;
533: parameter logic [9:0] RV_PLIC_PRIO53_OFFSET = 10'h ec;
534: parameter logic [9:0] RV_PLIC_PRIO54_OFFSET = 10'h f0;
535: parameter logic [9:0] RV_PLIC_PRIO55_OFFSET = 10'h f4;
536: parameter logic [9:0] RV_PLIC_PRIO56_OFFSET = 10'h f8;
537: parameter logic [9:0] RV_PLIC_PRIO57_OFFSET = 10'h fc;
538: parameter logic [9:0] RV_PLIC_PRIO58_OFFSET = 10'h 100;
539: parameter logic [9:0] RV_PLIC_PRIO59_OFFSET = 10'h 104;
540: parameter logic [9:0] RV_PLIC_PRIO60_OFFSET = 10'h 108;
541: parameter logic [9:0] RV_PLIC_PRIO61_OFFSET = 10'h 10c;
542: parameter logic [9:0] RV_PLIC_PRIO62_OFFSET = 10'h 110;
543: parameter logic [9:0] RV_PLIC_PRIO63_OFFSET = 10'h 114;
544: parameter logic [9:0] RV_PLIC_PRIO64_OFFSET = 10'h 118;
545: parameter logic [9:0] RV_PLIC_PRIO65_OFFSET = 10'h 11c;
546: parameter logic [9:0] RV_PLIC_PRIO66_OFFSET = 10'h 120;
547: parameter logic [9:0] RV_PLIC_PRIO67_OFFSET = 10'h 124;
548: parameter logic [9:0] RV_PLIC_PRIO68_OFFSET = 10'h 128;
549: parameter logic [9:0] RV_PLIC_PRIO69_OFFSET = 10'h 12c;
550: parameter logic [9:0] RV_PLIC_PRIO70_OFFSET = 10'h 130;
551: parameter logic [9:0] RV_PLIC_PRIO71_OFFSET = 10'h 134;
552: parameter logic [9:0] RV_PLIC_PRIO72_OFFSET = 10'h 138;
553: parameter logic [9:0] RV_PLIC_PRIO73_OFFSET = 10'h 13c;
554: parameter logic [9:0] RV_PLIC_PRIO74_OFFSET = 10'h 140;
555: parameter logic [9:0] RV_PLIC_PRIO75_OFFSET = 10'h 144;
556: parameter logic [9:0] RV_PLIC_PRIO76_OFFSET = 10'h 148;
557: parameter logic [9:0] RV_PLIC_PRIO77_OFFSET = 10'h 14c;
558: parameter logic [9:0] RV_PLIC_PRIO78_OFFSET = 10'h 150;
559: parameter logic [9:0] RV_PLIC_PRIO79_OFFSET = 10'h 154;
560: parameter logic [9:0] RV_PLIC_PRIO80_OFFSET = 10'h 158;
561: parameter logic [9:0] RV_PLIC_IE00_OFFSET = 10'h 200;
562: parameter logic [9:0] RV_PLIC_IE01_OFFSET = 10'h 204;
563: parameter logic [9:0] RV_PLIC_IE02_OFFSET = 10'h 208;
564: parameter logic [9:0] RV_PLIC_THRESHOLD0_OFFSET = 10'h 20c;
565: parameter logic [9:0] RV_PLIC_CC0_OFFSET = 10'h 210;
566: parameter logic [9:0] RV_PLIC_MSIP0_OFFSET = 10'h 214;
567:
568:
569: // Register Index
570: typedef enum int {
571: RV_PLIC_IP0,
572: RV_PLIC_IP1,
573: RV_PLIC_IP2,
574: RV_PLIC_LE0,
575: RV_PLIC_LE1,
576: RV_PLIC_LE2,
577: RV_PLIC_PRIO0,
578: RV_PLIC_PRIO1,
579: RV_PLIC_PRIO2,
580: RV_PLIC_PRIO3,
581: RV_PLIC_PRIO4,
582: RV_PLIC_PRIO5,
583: RV_PLIC_PRIO6,
584: RV_PLIC_PRIO7,
585: RV_PLIC_PRIO8,
586: RV_PLIC_PRIO9,
587: RV_PLIC_PRIO10,
588: RV_PLIC_PRIO11,
589: RV_PLIC_PRIO12,
590: RV_PLIC_PRIO13,
591: RV_PLIC_PRIO14,
592: RV_PLIC_PRIO15,
593: RV_PLIC_PRIO16,
594: RV_PLIC_PRIO17,
595: RV_PLIC_PRIO18,
596: RV_PLIC_PRIO19,
597: RV_PLIC_PRIO20,
598: RV_PLIC_PRIO21,
599: RV_PLIC_PRIO22,
600: RV_PLIC_PRIO23,
601: RV_PLIC_PRIO24,
602: RV_PLIC_PRIO25,
603: RV_PLIC_PRIO26,
604: RV_PLIC_PRIO27,
605: RV_PLIC_PRIO28,
606: RV_PLIC_PRIO29,
607: RV_PLIC_PRIO30,
608: RV_PLIC_PRIO31,
609: RV_PLIC_PRIO32,
610: RV_PLIC_PRIO33,
611: RV_PLIC_PRIO34,
612: RV_PLIC_PRIO35,
613: RV_PLIC_PRIO36,
614: RV_PLIC_PRIO37,
615: RV_PLIC_PRIO38,
616: RV_PLIC_PRIO39,
617: RV_PLIC_PRIO40,
618: RV_PLIC_PRIO41,
619: RV_PLIC_PRIO42,
620: RV_PLIC_PRIO43,
621: RV_PLIC_PRIO44,
622: RV_PLIC_PRIO45,
623: RV_PLIC_PRIO46,
624: RV_PLIC_PRIO47,
625: RV_PLIC_PRIO48,
626: RV_PLIC_PRIO49,
627: RV_PLIC_PRIO50,
628: RV_PLIC_PRIO51,
629: RV_PLIC_PRIO52,
630: RV_PLIC_PRIO53,
631: RV_PLIC_PRIO54,
632: RV_PLIC_PRIO55,
633: RV_PLIC_PRIO56,
634: RV_PLIC_PRIO57,
635: RV_PLIC_PRIO58,
636: RV_PLIC_PRIO59,
637: RV_PLIC_PRIO60,
638: RV_PLIC_PRIO61,
639: RV_PLIC_PRIO62,
640: RV_PLIC_PRIO63,
641: RV_PLIC_PRIO64,
642: RV_PLIC_PRIO65,
643: RV_PLIC_PRIO66,
644: RV_PLIC_PRIO67,
645: RV_PLIC_PRIO68,
646: RV_PLIC_PRIO69,
647: RV_PLIC_PRIO70,
648: RV_PLIC_PRIO71,
649: RV_PLIC_PRIO72,
650: RV_PLIC_PRIO73,
651: RV_PLIC_PRIO74,
652: RV_PLIC_PRIO75,
653: RV_PLIC_PRIO76,
654: RV_PLIC_PRIO77,
655: RV_PLIC_PRIO78,
656: RV_PLIC_PRIO79,
657: RV_PLIC_PRIO80,
658: RV_PLIC_IE00,
659: RV_PLIC_IE01,
660: RV_PLIC_IE02,
661: RV_PLIC_THRESHOLD0,
662: RV_PLIC_CC0,
663: RV_PLIC_MSIP0
664: } rv_plic_id_e;
665:
666: // Register width information to check illegal writes
667: parameter logic [3:0] RV_PLIC_PERMIT [93] = '{
668: 4'b 1111, // index[ 0] RV_PLIC_IP0
669: 4'b 1111, // index[ 1] RV_PLIC_IP1
670: 4'b 0111, // index[ 2] RV_PLIC_IP2
671: 4'b 1111, // index[ 3] RV_PLIC_LE0
672: 4'b 1111, // index[ 4] RV_PLIC_LE1
673: 4'b 0111, // index[ 5] RV_PLIC_LE2
674: 4'b 0001, // index[ 6] RV_PLIC_PRIO0
675: 4'b 0001, // index[ 7] RV_PLIC_PRIO1
676: 4'b 0001, // index[ 8] RV_PLIC_PRIO2
677: 4'b 0001, // index[ 9] RV_PLIC_PRIO3
678: 4'b 0001, // index[10] RV_PLIC_PRIO4
679: 4'b 0001, // index[11] RV_PLIC_PRIO5
680: 4'b 0001, // index[12] RV_PLIC_PRIO6
681: 4'b 0001, // index[13] RV_PLIC_PRIO7
682: 4'b 0001, // index[14] RV_PLIC_PRIO8
683: 4'b 0001, // index[15] RV_PLIC_PRIO9
684: 4'b 0001, // index[16] RV_PLIC_PRIO10
685: 4'b 0001, // index[17] RV_PLIC_PRIO11
686: 4'b 0001, // index[18] RV_PLIC_PRIO12
687: 4'b 0001, // index[19] RV_PLIC_PRIO13
688: 4'b 0001, // index[20] RV_PLIC_PRIO14
689: 4'b 0001, // index[21] RV_PLIC_PRIO15
690: 4'b 0001, // index[22] RV_PLIC_PRIO16
691: 4'b 0001, // index[23] RV_PLIC_PRIO17
692: 4'b 0001, // index[24] RV_PLIC_PRIO18
693: 4'b 0001, // index[25] RV_PLIC_PRIO19
694: 4'b 0001, // index[26] RV_PLIC_PRIO20
695: 4'b 0001, // index[27] RV_PLIC_PRIO21
696: 4'b 0001, // index[28] RV_PLIC_PRIO22
697: 4'b 0001, // index[29] RV_PLIC_PRIO23
698: 4'b 0001, // index[30] RV_PLIC_PRIO24
699: 4'b 0001, // index[31] RV_PLIC_PRIO25
700: 4'b 0001, // index[32] RV_PLIC_PRIO26
701: 4'b 0001, // index[33] RV_PLIC_PRIO27
702: 4'b 0001, // index[34] RV_PLIC_PRIO28
703: 4'b 0001, // index[35] RV_PLIC_PRIO29
704: 4'b 0001, // index[36] RV_PLIC_PRIO30
705: 4'b 0001, // index[37] RV_PLIC_PRIO31
706: 4'b 0001, // index[38] RV_PLIC_PRIO32
707: 4'b 0001, // index[39] RV_PLIC_PRIO33
708: 4'b 0001, // index[40] RV_PLIC_PRIO34
709: 4'b 0001, // index[41] RV_PLIC_PRIO35
710: 4'b 0001, // index[42] RV_PLIC_PRIO36
711: 4'b 0001, // index[43] RV_PLIC_PRIO37
712: 4'b 0001, // index[44] RV_PLIC_PRIO38
713: 4'b 0001, // index[45] RV_PLIC_PRIO39
714: 4'b 0001, // index[46] RV_PLIC_PRIO40
715: 4'b 0001, // index[47] RV_PLIC_PRIO41
716: 4'b 0001, // index[48] RV_PLIC_PRIO42
717: 4'b 0001, // index[49] RV_PLIC_PRIO43
718: 4'b 0001, // index[50] RV_PLIC_PRIO44
719: 4'b 0001, // index[51] RV_PLIC_PRIO45
720: 4'b 0001, // index[52] RV_PLIC_PRIO46
721: 4'b 0001, // index[53] RV_PLIC_PRIO47
722: 4'b 0001, // index[54] RV_PLIC_PRIO48
723: 4'b 0001, // index[55] RV_PLIC_PRIO49
724: 4'b 0001, // index[56] RV_PLIC_PRIO50
725: 4'b 0001, // index[57] RV_PLIC_PRIO51
726: 4'b 0001, // index[58] RV_PLIC_PRIO52
727: 4'b 0001, // index[59] RV_PLIC_PRIO53
728: 4'b 0001, // index[60] RV_PLIC_PRIO54
729: 4'b 0001, // index[61] RV_PLIC_PRIO55
730: 4'b 0001, // index[62] RV_PLIC_PRIO56
731: 4'b 0001, // index[63] RV_PLIC_PRIO57
732: 4'b 0001, // index[64] RV_PLIC_PRIO58
733: 4'b 0001, // index[65] RV_PLIC_PRIO59
734: 4'b 0001, // index[66] RV_PLIC_PRIO60
735: 4'b 0001, // index[67] RV_PLIC_PRIO61
736: 4'b 0001, // index[68] RV_PLIC_PRIO62
737: 4'b 0001, // index[69] RV_PLIC_PRIO63
738: 4'b 0001, // index[70] RV_PLIC_PRIO64
739: 4'b 0001, // index[71] RV_PLIC_PRIO65
740: 4'b 0001, // index[72] RV_PLIC_PRIO66
741: 4'b 0001, // index[73] RV_PLIC_PRIO67
742: 4'b 0001, // index[74] RV_PLIC_PRIO68
743: 4'b 0001, // index[75] RV_PLIC_PRIO69
744: 4'b 0001, // index[76] RV_PLIC_PRIO70
745: 4'b 0001, // index[77] RV_PLIC_PRIO71
746: 4'b 0001, // index[78] RV_PLIC_PRIO72
747: 4'b 0001, // index[79] RV_PLIC_PRIO73
748: 4'b 0001, // index[80] RV_PLIC_PRIO74
749: 4'b 0001, // index[81] RV_PLIC_PRIO75
750: 4'b 0001, // index[82] RV_PLIC_PRIO76
751: 4'b 0001, // index[83] RV_PLIC_PRIO77
752: 4'b 0001, // index[84] RV_PLIC_PRIO78
753: 4'b 0001, // index[85] RV_PLIC_PRIO79
754: 4'b 0001, // index[86] RV_PLIC_PRIO80
755: 4'b 1111, // index[87] RV_PLIC_IE00
756: 4'b 1111, // index[88] RV_PLIC_IE01
757: 4'b 0111, // index[89] RV_PLIC_IE02
758: 4'b 0001, // index[90] RV_PLIC_THRESHOLD0
759: 4'b 0001, // index[91] RV_PLIC_CC0
760: 4'b 0001 // index[92] RV_PLIC_MSIP0
761: };
762: endpackage
763:
764: