../src/lowrisc_ip_uart_0.1/rtl/uart_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: `include "prim_assert.sv"
8:
9: module uart_reg_top (
10: input clk_i,
11: input rst_ni,
12:
13: // Below Regster interface can be changed
14: input tlul_pkg::tl_h2d_t tl_i,
15: output tlul_pkg::tl_d2h_t tl_o,
16: // To HW
17: output uart_reg_pkg::uart_reg2hw_t reg2hw, // Write
18: input uart_reg_pkg::uart_hw2reg_t hw2reg, // Read
19:
20: // Config
21: input devmode_i // If 1, explicit error return for unmapped register access
22: );
23:
24: import uart_reg_pkg::* ;
25:
26: localparam int AW = 6;
27: localparam int DW = 32;
28: localparam int DBW = DW/8; // Byte Width
29:
30: // register signals
31: logic reg_we;
32: logic reg_re;
33: logic [AW-1:0] reg_addr;
34: logic [DW-1:0] reg_wdata;
35: logic [DBW-1:0] reg_be;
36: logic [DW-1:0] reg_rdata;
37: logic reg_error;
38:
39: logic addrmiss, wr_err;
40:
41: logic [DW-1:0] reg_rdata_next;
42:
43: tlul_pkg::tl_h2d_t tl_reg_h2d;
44: tlul_pkg::tl_d2h_t tl_reg_d2h;
45:
46: assign tl_reg_h2d = tl_i;
47: assign tl_o = tl_reg_d2h;
48:
49: tlul_adapter_reg #(
50: .RegAw(AW),
51: .RegDw(DW)
52: ) u_reg_if (
53: .clk_i,
54: .rst_ni,
55:
56: .tl_i (tl_reg_h2d),
57: .tl_o (tl_reg_d2h),
58:
59: .we_o (reg_we),
60: .re_o (reg_re),
61: .addr_o (reg_addr),
62: .wdata_o (reg_wdata),
63: .be_o (reg_be),
64: .rdata_i (reg_rdata),
65: .error_i (reg_error)
66: );
67:
68: assign reg_rdata = reg_rdata_next ;
69: assign reg_error = (devmode_i & addrmiss) | wr_err ;
70:
71: // Define SW related signals
72: // Format: __{wd|we|qs}
73: // or _{wd|we|qs} if field == 1 or 0
74: logic intr_state_tx_watermark_qs;
75: logic intr_state_tx_watermark_wd;
76: logic intr_state_tx_watermark_we;
77: logic intr_state_rx_watermark_qs;
78: logic intr_state_rx_watermark_wd;
79: logic intr_state_rx_watermark_we;
80: logic intr_state_tx_empty_qs;
81: logic intr_state_tx_empty_wd;
82: logic intr_state_tx_empty_we;
83: logic intr_state_rx_overflow_qs;
84: logic intr_state_rx_overflow_wd;
85: logic intr_state_rx_overflow_we;
86: logic intr_state_rx_frame_err_qs;
87: logic intr_state_rx_frame_err_wd;
88: logic intr_state_rx_frame_err_we;
89: logic intr_state_rx_break_err_qs;
90: logic intr_state_rx_break_err_wd;
91: logic intr_state_rx_break_err_we;
92: logic intr_state_rx_timeout_qs;
93: logic intr_state_rx_timeout_wd;
94: logic intr_state_rx_timeout_we;
95: logic intr_state_rx_parity_err_qs;
96: logic intr_state_rx_parity_err_wd;
97: logic intr_state_rx_parity_err_we;
98: logic intr_enable_tx_watermark_qs;
99: logic intr_enable_tx_watermark_wd;
100: logic intr_enable_tx_watermark_we;
101: logic intr_enable_rx_watermark_qs;
102: logic intr_enable_rx_watermark_wd;
103: logic intr_enable_rx_watermark_we;
104: logic intr_enable_tx_empty_qs;
105: logic intr_enable_tx_empty_wd;
106: logic intr_enable_tx_empty_we;
107: logic intr_enable_rx_overflow_qs;
108: logic intr_enable_rx_overflow_wd;
109: logic intr_enable_rx_overflow_we;
110: logic intr_enable_rx_frame_err_qs;
111: logic intr_enable_rx_frame_err_wd;
112: logic intr_enable_rx_frame_err_we;
113: logic intr_enable_rx_break_err_qs;
114: logic intr_enable_rx_break_err_wd;
115: logic intr_enable_rx_break_err_we;
116: logic intr_enable_rx_timeout_qs;
117: logic intr_enable_rx_timeout_wd;
118: logic intr_enable_rx_timeout_we;
119: logic intr_enable_rx_parity_err_qs;
120: logic intr_enable_rx_parity_err_wd;
121: logic intr_enable_rx_parity_err_we;
122: logic intr_test_tx_watermark_wd;
123: logic intr_test_tx_watermark_we;
124: logic intr_test_rx_watermark_wd;
125: logic intr_test_rx_watermark_we;
126: logic intr_test_tx_empty_wd;
127: logic intr_test_tx_empty_we;
128: logic intr_test_rx_overflow_wd;
129: logic intr_test_rx_overflow_we;
130: logic intr_test_rx_frame_err_wd;
131: logic intr_test_rx_frame_err_we;
132: logic intr_test_rx_break_err_wd;
133: logic intr_test_rx_break_err_we;
134: logic intr_test_rx_timeout_wd;
135: logic intr_test_rx_timeout_we;
136: logic intr_test_rx_parity_err_wd;
137: logic intr_test_rx_parity_err_we;
138: logic ctrl_tx_qs;
139: logic ctrl_tx_wd;
140: logic ctrl_tx_we;
141: logic ctrl_rx_qs;
142: logic ctrl_rx_wd;
143: logic ctrl_rx_we;
144: logic ctrl_nf_qs;
145: logic ctrl_nf_wd;
146: logic ctrl_nf_we;
147: logic ctrl_slpbk_qs;
148: logic ctrl_slpbk_wd;
149: logic ctrl_slpbk_we;
150: logic ctrl_llpbk_qs;
151: logic ctrl_llpbk_wd;
152: logic ctrl_llpbk_we;
153: logic ctrl_parity_en_qs;
154: logic ctrl_parity_en_wd;
155: logic ctrl_parity_en_we;
156: logic ctrl_parity_odd_qs;
157: logic ctrl_parity_odd_wd;
158: logic ctrl_parity_odd_we;
159: logic [1:0] ctrl_rxblvl_qs;
160: logic [1:0] ctrl_rxblvl_wd;
161: logic ctrl_rxblvl_we;
162: logic [15:0] ctrl_nco_qs;
163: logic [15:0] ctrl_nco_wd;
164: logic ctrl_nco_we;
165: logic status_txfull_qs;
166: logic status_txfull_re;
167: logic status_rxfull_qs;
168: logic status_rxfull_re;
169: logic status_txempty_qs;
170: logic status_txempty_re;
171: logic status_txidle_qs;
172: logic status_txidle_re;
173: logic status_rxidle_qs;
174: logic status_rxidle_re;
175: logic status_rxempty_qs;
176: logic status_rxempty_re;
177: logic [7:0] rdata_qs;
178: logic rdata_re;
179: logic [7:0] wdata_wd;
180: logic wdata_we;
181: logic fifo_ctrl_rxrst_wd;
182: logic fifo_ctrl_rxrst_we;
183: logic fifo_ctrl_txrst_wd;
184: logic fifo_ctrl_txrst_we;
185: logic [2:0] fifo_ctrl_rxilvl_qs;
186: logic [2:0] fifo_ctrl_rxilvl_wd;
187: logic fifo_ctrl_rxilvl_we;
188: logic [1:0] fifo_ctrl_txilvl_qs;
189: logic [1:0] fifo_ctrl_txilvl_wd;
190: logic fifo_ctrl_txilvl_we;
191: logic [5:0] fifo_status_txlvl_qs;
192: logic fifo_status_txlvl_re;
193: logic [5:0] fifo_status_rxlvl_qs;
194: logic fifo_status_rxlvl_re;
195: logic ovrd_txen_qs;
196: logic ovrd_txen_wd;
197: logic ovrd_txen_we;
198: logic ovrd_txval_qs;
199: logic ovrd_txval_wd;
200: logic ovrd_txval_we;
201: logic [15:0] val_qs;
202: logic val_re;
203: logic [23:0] timeout_ctrl_val_qs;
204: logic [23:0] timeout_ctrl_val_wd;
205: logic timeout_ctrl_val_we;
206: logic timeout_ctrl_en_qs;
207: logic timeout_ctrl_en_wd;
208: logic timeout_ctrl_en_we;
209:
210: // Register instances
211: // R[intr_state]: V(False)
212:
213: // F[tx_watermark]: 0:0
214: prim_subreg #(
215: .DW (1),
216: .SWACCESS("W1C"),
217: .RESVAL (1'h0)
218: ) u_intr_state_tx_watermark (
219: .clk_i (clk_i ),
220: .rst_ni (rst_ni ),
221:
222: // from register interface
223: .we (intr_state_tx_watermark_we),
224: .wd (intr_state_tx_watermark_wd),
225:
226: // from internal hardware
227: .de (hw2reg.intr_state.tx_watermark.de),
228: .d (hw2reg.intr_state.tx_watermark.d ),
229:
230: // to internal hardware
231: .qe (),
232: .q (reg2hw.intr_state.tx_watermark.q ),
233:
234: // to register interface (read)
235: .qs (intr_state_tx_watermark_qs)
236: );
237:
238:
239: // F[rx_watermark]: 1:1
240: prim_subreg #(
241: .DW (1),
242: .SWACCESS("W1C"),
243: .RESVAL (1'h0)
244: ) u_intr_state_rx_watermark (
245: .clk_i (clk_i ),
246: .rst_ni (rst_ni ),
247:
248: // from register interface
249: .we (intr_state_rx_watermark_we),
250: .wd (intr_state_rx_watermark_wd),
251:
252: // from internal hardware
253: .de (hw2reg.intr_state.rx_watermark.de),
254: .d (hw2reg.intr_state.rx_watermark.d ),
255:
256: // to internal hardware
257: .qe (),
258: .q (reg2hw.intr_state.rx_watermark.q ),
259:
260: // to register interface (read)
261: .qs (intr_state_rx_watermark_qs)
262: );
263:
264:
265: // F[tx_empty]: 2:2
266: prim_subreg #(
267: .DW (1),
268: .SWACCESS("W1C"),
269: .RESVAL (1'h0)
270: ) u_intr_state_tx_empty (
271: .clk_i (clk_i ),
272: .rst_ni (rst_ni ),
273:
274: // from register interface
275: .we (intr_state_tx_empty_we),
276: .wd (intr_state_tx_empty_wd),
277:
278: // from internal hardware
279: .de (hw2reg.intr_state.tx_empty.de),
280: .d (hw2reg.intr_state.tx_empty.d ),
281:
282: // to internal hardware
283: .qe (),
284: .q (reg2hw.intr_state.tx_empty.q ),
285:
286: // to register interface (read)
287: .qs (intr_state_tx_empty_qs)
288: );
289:
290:
291: // F[rx_overflow]: 3:3
292: prim_subreg #(
293: .DW (1),
294: .SWACCESS("W1C"),
295: .RESVAL (1'h0)
296: ) u_intr_state_rx_overflow (
297: .clk_i (clk_i ),
298: .rst_ni (rst_ni ),
299:
300: // from register interface
301: .we (intr_state_rx_overflow_we),
302: .wd (intr_state_rx_overflow_wd),
303:
304: // from internal hardware
305: .de (hw2reg.intr_state.rx_overflow.de),
306: .d (hw2reg.intr_state.rx_overflow.d ),
307:
308: // to internal hardware
309: .qe (),
310: .q (reg2hw.intr_state.rx_overflow.q ),
311:
312: // to register interface (read)
313: .qs (intr_state_rx_overflow_qs)
314: );
315:
316:
317: // F[rx_frame_err]: 4:4
318: prim_subreg #(
319: .DW (1),
320: .SWACCESS("W1C"),
321: .RESVAL (1'h0)
322: ) u_intr_state_rx_frame_err (
323: .clk_i (clk_i ),
324: .rst_ni (rst_ni ),
325:
326: // from register interface
327: .we (intr_state_rx_frame_err_we),
328: .wd (intr_state_rx_frame_err_wd),
329:
330: // from internal hardware
331: .de (hw2reg.intr_state.rx_frame_err.de),
332: .d (hw2reg.intr_state.rx_frame_err.d ),
333:
334: // to internal hardware
335: .qe (),
336: .q (reg2hw.intr_state.rx_frame_err.q ),
337:
338: // to register interface (read)
339: .qs (intr_state_rx_frame_err_qs)
340: );
341:
342:
343: // F[rx_break_err]: 5:5
344: prim_subreg #(
345: .DW (1),
346: .SWACCESS("W1C"),
347: .RESVAL (1'h0)
348: ) u_intr_state_rx_break_err (
349: .clk_i (clk_i ),
350: .rst_ni (rst_ni ),
351:
352: // from register interface
353: .we (intr_state_rx_break_err_we),
354: .wd (intr_state_rx_break_err_wd),
355:
356: // from internal hardware
357: .de (hw2reg.intr_state.rx_break_err.de),
358: .d (hw2reg.intr_state.rx_break_err.d ),
359:
360: // to internal hardware
361: .qe (),
362: .q (reg2hw.intr_state.rx_break_err.q ),
363:
364: // to register interface (read)
365: .qs (intr_state_rx_break_err_qs)
366: );
367:
368:
369: // F[rx_timeout]: 6:6
370: prim_subreg #(
371: .DW (1),
372: .SWACCESS("W1C"),
373: .RESVAL (1'h0)
374: ) u_intr_state_rx_timeout (
375: .clk_i (clk_i ),
376: .rst_ni (rst_ni ),
377:
378: // from register interface
379: .we (intr_state_rx_timeout_we),
380: .wd (intr_state_rx_timeout_wd),
381:
382: // from internal hardware
383: .de (hw2reg.intr_state.rx_timeout.de),
384: .d (hw2reg.intr_state.rx_timeout.d ),
385:
386: // to internal hardware
387: .qe (),
388: .q (reg2hw.intr_state.rx_timeout.q ),
389:
390: // to register interface (read)
391: .qs (intr_state_rx_timeout_qs)
392: );
393:
394:
395: // F[rx_parity_err]: 7:7
396: prim_subreg #(
397: .DW (1),
398: .SWACCESS("W1C"),
399: .RESVAL (1'h0)
400: ) u_intr_state_rx_parity_err (
401: .clk_i (clk_i ),
402: .rst_ni (rst_ni ),
403:
404: // from register interface
405: .we (intr_state_rx_parity_err_we),
406: .wd (intr_state_rx_parity_err_wd),
407:
408: // from internal hardware
409: .de (hw2reg.intr_state.rx_parity_err.de),
410: .d (hw2reg.intr_state.rx_parity_err.d ),
411:
412: // to internal hardware
413: .qe (),
414: .q (reg2hw.intr_state.rx_parity_err.q ),
415:
416: // to register interface (read)
417: .qs (intr_state_rx_parity_err_qs)
418: );
419:
420:
421: // R[intr_enable]: V(False)
422:
423: // F[tx_watermark]: 0:0
424: prim_subreg #(
425: .DW (1),
426: .SWACCESS("RW"),
427: .RESVAL (1'h0)
428: ) u_intr_enable_tx_watermark (
429: .clk_i (clk_i ),
430: .rst_ni (rst_ni ),
431:
432: // from register interface
433: .we (intr_enable_tx_watermark_we),
434: .wd (intr_enable_tx_watermark_wd),
435:
436: // from internal hardware
437: .de (1'b0),
438: .d ('0 ),
439:
440: // to internal hardware
441: .qe (),
442: .q (reg2hw.intr_enable.tx_watermark.q ),
443:
444: // to register interface (read)
445: .qs (intr_enable_tx_watermark_qs)
446: );
447:
448:
449: // F[rx_watermark]: 1:1
450: prim_subreg #(
451: .DW (1),
452: .SWACCESS("RW"),
453: .RESVAL (1'h0)
454: ) u_intr_enable_rx_watermark (
455: .clk_i (clk_i ),
456: .rst_ni (rst_ni ),
457:
458: // from register interface
459: .we (intr_enable_rx_watermark_we),
460: .wd (intr_enable_rx_watermark_wd),
461:
462: // from internal hardware
463: .de (1'b0),
464: .d ('0 ),
465:
466: // to internal hardware
467: .qe (),
468: .q (reg2hw.intr_enable.rx_watermark.q ),
469:
470: // to register interface (read)
471: .qs (intr_enable_rx_watermark_qs)
472: );
473:
474:
475: // F[tx_empty]: 2:2
476: prim_subreg #(
477: .DW (1),
478: .SWACCESS("RW"),
479: .RESVAL (1'h0)
480: ) u_intr_enable_tx_empty (
481: .clk_i (clk_i ),
482: .rst_ni (rst_ni ),
483:
484: // from register interface
485: .we (intr_enable_tx_empty_we),
486: .wd (intr_enable_tx_empty_wd),
487:
488: // from internal hardware
489: .de (1'b0),
490: .d ('0 ),
491:
492: // to internal hardware
493: .qe (),
494: .q (reg2hw.intr_enable.tx_empty.q ),
495:
496: // to register interface (read)
497: .qs (intr_enable_tx_empty_qs)
498: );
499:
500:
501: // F[rx_overflow]: 3:3
502: prim_subreg #(
503: .DW (1),
504: .SWACCESS("RW"),
505: .RESVAL (1'h0)
506: ) u_intr_enable_rx_overflow (
507: .clk_i (clk_i ),
508: .rst_ni (rst_ni ),
509:
510: // from register interface
511: .we (intr_enable_rx_overflow_we),
512: .wd (intr_enable_rx_overflow_wd),
513:
514: // from internal hardware
515: .de (1'b0),
516: .d ('0 ),
517:
518: // to internal hardware
519: .qe (),
520: .q (reg2hw.intr_enable.rx_overflow.q ),
521:
522: // to register interface (read)
523: .qs (intr_enable_rx_overflow_qs)
524: );
525:
526:
527: // F[rx_frame_err]: 4:4
528: prim_subreg #(
529: .DW (1),
530: .SWACCESS("RW"),
531: .RESVAL (1'h0)
532: ) u_intr_enable_rx_frame_err (
533: .clk_i (clk_i ),
534: .rst_ni (rst_ni ),
535:
536: // from register interface
537: .we (intr_enable_rx_frame_err_we),
538: .wd (intr_enable_rx_frame_err_wd),
539:
540: // from internal hardware
541: .de (1'b0),
542: .d ('0 ),
543:
544: // to internal hardware
545: .qe (),
546: .q (reg2hw.intr_enable.rx_frame_err.q ),
547:
548: // to register interface (read)
549: .qs (intr_enable_rx_frame_err_qs)
550: );
551:
552:
553: // F[rx_break_err]: 5:5
554: prim_subreg #(
555: .DW (1),
556: .SWACCESS("RW"),
557: .RESVAL (1'h0)
558: ) u_intr_enable_rx_break_err (
559: .clk_i (clk_i ),
560: .rst_ni (rst_ni ),
561:
562: // from register interface
563: .we (intr_enable_rx_break_err_we),
564: .wd (intr_enable_rx_break_err_wd),
565:
566: // from internal hardware
567: .de (1'b0),
568: .d ('0 ),
569:
570: // to internal hardware
571: .qe (),
572: .q (reg2hw.intr_enable.rx_break_err.q ),
573:
574: // to register interface (read)
575: .qs (intr_enable_rx_break_err_qs)
576: );
577:
578:
579: // F[rx_timeout]: 6:6
580: prim_subreg #(
581: .DW (1),
582: .SWACCESS("RW"),
583: .RESVAL (1'h0)
584: ) u_intr_enable_rx_timeout (
585: .clk_i (clk_i ),
586: .rst_ni (rst_ni ),
587:
588: // from register interface
589: .we (intr_enable_rx_timeout_we),
590: .wd (intr_enable_rx_timeout_wd),
591:
592: // from internal hardware
593: .de (1'b0),
594: .d ('0 ),
595:
596: // to internal hardware
597: .qe (),
598: .q (reg2hw.intr_enable.rx_timeout.q ),
599:
600: // to register interface (read)
601: .qs (intr_enable_rx_timeout_qs)
602: );
603:
604:
605: // F[rx_parity_err]: 7:7
606: prim_subreg #(
607: .DW (1),
608: .SWACCESS("RW"),
609: .RESVAL (1'h0)
610: ) u_intr_enable_rx_parity_err (
611: .clk_i (clk_i ),
612: .rst_ni (rst_ni ),
613:
614: // from register interface
615: .we (intr_enable_rx_parity_err_we),
616: .wd (intr_enable_rx_parity_err_wd),
617:
618: // from internal hardware
619: .de (1'b0),
620: .d ('0 ),
621:
622: // to internal hardware
623: .qe (),
624: .q (reg2hw.intr_enable.rx_parity_err.q ),
625:
626: // to register interface (read)
627: .qs (intr_enable_rx_parity_err_qs)
628: );
629:
630:
631: // R[intr_test]: V(True)
632:
633: // F[tx_watermark]: 0:0
634: prim_subreg_ext #(
635: .DW (1)
636: ) u_intr_test_tx_watermark (
637: .re (1'b0),
638: .we (intr_test_tx_watermark_we),
639: .wd (intr_test_tx_watermark_wd),
640: .d ('0),
641: .qre (),
642: .qe (reg2hw.intr_test.tx_watermark.qe),
643: .q (reg2hw.intr_test.tx_watermark.q ),
644: .qs ()
645: );
646:
647:
648: // F[rx_watermark]: 1:1
649: prim_subreg_ext #(
650: .DW (1)
651: ) u_intr_test_rx_watermark (
652: .re (1'b0),
653: .we (intr_test_rx_watermark_we),
654: .wd (intr_test_rx_watermark_wd),
655: .d ('0),
656: .qre (),
657: .qe (reg2hw.intr_test.rx_watermark.qe),
658: .q (reg2hw.intr_test.rx_watermark.q ),
659: .qs ()
660: );
661:
662:
663: // F[tx_empty]: 2:2
664: prim_subreg_ext #(
665: .DW (1)
666: ) u_intr_test_tx_empty (
667: .re (1'b0),
668: .we (intr_test_tx_empty_we),
669: .wd (intr_test_tx_empty_wd),
670: .d ('0),
671: .qre (),
672: .qe (reg2hw.intr_test.tx_empty.qe),
673: .q (reg2hw.intr_test.tx_empty.q ),
674: .qs ()
675: );
676:
677:
678: // F[rx_overflow]: 3:3
679: prim_subreg_ext #(
680: .DW (1)
681: ) u_intr_test_rx_overflow (
682: .re (1'b0),
683: .we (intr_test_rx_overflow_we),
684: .wd (intr_test_rx_overflow_wd),
685: .d ('0),
686: .qre (),
687: .qe (reg2hw.intr_test.rx_overflow.qe),
688: .q (reg2hw.intr_test.rx_overflow.q ),
689: .qs ()
690: );
691:
692:
693: // F[rx_frame_err]: 4:4
694: prim_subreg_ext #(
695: .DW (1)
696: ) u_intr_test_rx_frame_err (
697: .re (1'b0),
698: .we (intr_test_rx_frame_err_we),
699: .wd (intr_test_rx_frame_err_wd),
700: .d ('0),
701: .qre (),
702: .qe (reg2hw.intr_test.rx_frame_err.qe),
703: .q (reg2hw.intr_test.rx_frame_err.q ),
704: .qs ()
705: );
706:
707:
708: // F[rx_break_err]: 5:5
709: prim_subreg_ext #(
710: .DW (1)
711: ) u_intr_test_rx_break_err (
712: .re (1'b0),
713: .we (intr_test_rx_break_err_we),
714: .wd (intr_test_rx_break_err_wd),
715: .d ('0),
716: .qre (),
717: .qe (reg2hw.intr_test.rx_break_err.qe),
718: .q (reg2hw.intr_test.rx_break_err.q ),
719: .qs ()
720: );
721:
722:
723: // F[rx_timeout]: 6:6
724: prim_subreg_ext #(
725: .DW (1)
726: ) u_intr_test_rx_timeout (
727: .re (1'b0),
728: .we (intr_test_rx_timeout_we),
729: .wd (intr_test_rx_timeout_wd),
730: .d ('0),
731: .qre (),
732: .qe (reg2hw.intr_test.rx_timeout.qe),
733: .q (reg2hw.intr_test.rx_timeout.q ),
734: .qs ()
735: );
736:
737:
738: // F[rx_parity_err]: 7:7
739: prim_subreg_ext #(
740: .DW (1)
741: ) u_intr_test_rx_parity_err (
742: .re (1'b0),
743: .we (intr_test_rx_parity_err_we),
744: .wd (intr_test_rx_parity_err_wd),
745: .d ('0),
746: .qre (),
747: .qe (reg2hw.intr_test.rx_parity_err.qe),
748: .q (reg2hw.intr_test.rx_parity_err.q ),
749: .qs ()
750: );
751:
752:
753: // R[ctrl]: V(False)
754:
755: // F[tx]: 0:0
756: prim_subreg #(
757: .DW (1),
758: .SWACCESS("RW"),
759: .RESVAL (1'h0)
760: ) u_ctrl_tx (
761: .clk_i (clk_i ),
762: .rst_ni (rst_ni ),
763:
764: // from register interface
765: .we (ctrl_tx_we),
766: .wd (ctrl_tx_wd),
767:
768: // from internal hardware
769: .de (1'b0),
770: .d ('0 ),
771:
772: // to internal hardware
773: .qe (),
774: .q (reg2hw.ctrl.tx.q ),
775:
776: // to register interface (read)
777: .qs (ctrl_tx_qs)
778: );
779:
780:
781: // F[rx]: 1:1
782: prim_subreg #(
783: .DW (1),
784: .SWACCESS("RW"),
785: .RESVAL (1'h0)
786: ) u_ctrl_rx (
787: .clk_i (clk_i ),
788: .rst_ni (rst_ni ),
789:
790: // from register interface
791: .we (ctrl_rx_we),
792: .wd (ctrl_rx_wd),
793:
794: // from internal hardware
795: .de (1'b0),
796: .d ('0 ),
797:
798: // to internal hardware
799: .qe (),
800: .q (reg2hw.ctrl.rx.q ),
801:
802: // to register interface (read)
803: .qs (ctrl_rx_qs)
804: );
805:
806:
807: // F[nf]: 2:2
808: prim_subreg #(
809: .DW (1),
810: .SWACCESS("RW"),
811: .RESVAL (1'h0)
812: ) u_ctrl_nf (
813: .clk_i (clk_i ),
814: .rst_ni (rst_ni ),
815:
816: // from register interface
817: .we (ctrl_nf_we),
818: .wd (ctrl_nf_wd),
819:
820: // from internal hardware
821: .de (1'b0),
822: .d ('0 ),
823:
824: // to internal hardware
825: .qe (),
826: .q (reg2hw.ctrl.nf.q ),
827:
828: // to register interface (read)
829: .qs (ctrl_nf_qs)
830: );
831:
832:
833: // F[slpbk]: 4:4
834: prim_subreg #(
835: .DW (1),
836: .SWACCESS("RW"),
837: .RESVAL (1'h0)
838: ) u_ctrl_slpbk (
839: .clk_i (clk_i ),
840: .rst_ni (rst_ni ),
841:
842: // from register interface
843: .we (ctrl_slpbk_we),
844: .wd (ctrl_slpbk_wd),
845:
846: // from internal hardware
847: .de (1'b0),
848: .d ('0 ),
849:
850: // to internal hardware
851: .qe (),
852: .q (reg2hw.ctrl.slpbk.q ),
853:
854: // to register interface (read)
855: .qs (ctrl_slpbk_qs)
856: );
857:
858:
859: // F[llpbk]: 5:5
860: prim_subreg #(
861: .DW (1),
862: .SWACCESS("RW"),
863: .RESVAL (1'h0)
864: ) u_ctrl_llpbk (
865: .clk_i (clk_i ),
866: .rst_ni (rst_ni ),
867:
868: // from register interface
869: .we (ctrl_llpbk_we),
870: .wd (ctrl_llpbk_wd),
871:
872: // from internal hardware
873: .de (1'b0),
874: .d ('0 ),
875:
876: // to internal hardware
877: .qe (),
878: .q (reg2hw.ctrl.llpbk.q ),
879:
880: // to register interface (read)
881: .qs (ctrl_llpbk_qs)
882: );
883:
884:
885: // F[parity_en]: 6:6
886: prim_subreg #(
887: .DW (1),
888: .SWACCESS("RW"),
889: .RESVAL (1'h0)
890: ) u_ctrl_parity_en (
891: .clk_i (clk_i ),
892: .rst_ni (rst_ni ),
893:
894: // from register interface
895: .we (ctrl_parity_en_we),
896: .wd (ctrl_parity_en_wd),
897:
898: // from internal hardware
899: .de (1'b0),
900: .d ('0 ),
901:
902: // to internal hardware
903: .qe (),
904: .q (reg2hw.ctrl.parity_en.q ),
905:
906: // to register interface (read)
907: .qs (ctrl_parity_en_qs)
908: );
909:
910:
911: // F[parity_odd]: 7:7
912: prim_subreg #(
913: .DW (1),
914: .SWACCESS("RW"),
915: .RESVAL (1'h0)
916: ) u_ctrl_parity_odd (
917: .clk_i (clk_i ),
918: .rst_ni (rst_ni ),
919:
920: // from register interface
921: .we (ctrl_parity_odd_we),
922: .wd (ctrl_parity_odd_wd),
923:
924: // from internal hardware
925: .de (1'b0),
926: .d ('0 ),
927:
928: // to internal hardware
929: .qe (),
930: .q (reg2hw.ctrl.parity_odd.q ),
931:
932: // to register interface (read)
933: .qs (ctrl_parity_odd_qs)
934: );
935:
936:
937: // F[rxblvl]: 9:8
938: prim_subreg #(
939: .DW (2),
940: .SWACCESS("RW"),
941: .RESVAL (2'h0)
942: ) u_ctrl_rxblvl (
943: .clk_i (clk_i ),
944: .rst_ni (rst_ni ),
945:
946: // from register interface
947: .we (ctrl_rxblvl_we),
948: .wd (ctrl_rxblvl_wd),
949:
950: // from internal hardware
951: .de (1'b0),
952: .d ('0 ),
953:
954: // to internal hardware
955: .qe (),
956: .q (reg2hw.ctrl.rxblvl.q ),
957:
958: // to register interface (read)
959: .qs (ctrl_rxblvl_qs)
960: );
961:
962:
963: // F[nco]: 31:16
964: prim_subreg #(
965: .DW (16),
966: .SWACCESS("RW"),
967: .RESVAL (16'h0)
968: ) u_ctrl_nco (
969: .clk_i (clk_i ),
970: .rst_ni (rst_ni ),
971:
972: // from register interface
973: .we (ctrl_nco_we),
974: .wd (ctrl_nco_wd),
975:
976: // from internal hardware
977: .de (1'b0),
978: .d ('0 ),
979:
980: // to internal hardware
981: .qe (),
982: .q (reg2hw.ctrl.nco.q ),
983:
984: // to register interface (read)
985: .qs (ctrl_nco_qs)
986: );
987:
988:
989: // R[status]: V(True)
990:
991: // F[txfull]: 0:0
992: prim_subreg_ext #(
993: .DW (1)
994: ) u_status_txfull (
995: .re (status_txfull_re),
996: .we (1'b0),
997: .wd ('0),
998: .d (hw2reg.status.txfull.d),
999: .qre (reg2hw.status.txfull.re),
1000: .qe (),
1001: .q (reg2hw.status.txfull.q ),
1002: .qs (status_txfull_qs)
1003: );
1004:
1005:
1006: // F[rxfull]: 1:1
1007: prim_subreg_ext #(
1008: .DW (1)
1009: ) u_status_rxfull (
1010: .re (status_rxfull_re),
1011: .we (1'b0),
1012: .wd ('0),
1013: .d (hw2reg.status.rxfull.d),
1014: .qre (reg2hw.status.rxfull.re),
1015: .qe (),
1016: .q (reg2hw.status.rxfull.q ),
1017: .qs (status_rxfull_qs)
1018: );
1019:
1020:
1021: // F[txempty]: 2:2
1022: prim_subreg_ext #(
1023: .DW (1)
1024: ) u_status_txempty (
1025: .re (status_txempty_re),
1026: .we (1'b0),
1027: .wd ('0),
1028: .d (hw2reg.status.txempty.d),
1029: .qre (reg2hw.status.txempty.re),
1030: .qe (),
1031: .q (reg2hw.status.txempty.q ),
1032: .qs (status_txempty_qs)
1033: );
1034:
1035:
1036: // F[txidle]: 3:3
1037: prim_subreg_ext #(
1038: .DW (1)
1039: ) u_status_txidle (
1040: .re (status_txidle_re),
1041: .we (1'b0),
1042: .wd ('0),
1043: .d (hw2reg.status.txidle.d),
1044: .qre (reg2hw.status.txidle.re),
1045: .qe (),
1046: .q (reg2hw.status.txidle.q ),
1047: .qs (status_txidle_qs)
1048: );
1049:
1050:
1051: // F[rxidle]: 4:4
1052: prim_subreg_ext #(
1053: .DW (1)
1054: ) u_status_rxidle (
1055: .re (status_rxidle_re),
1056: .we (1'b0),
1057: .wd ('0),
1058: .d (hw2reg.status.rxidle.d),
1059: .qre (reg2hw.status.rxidle.re),
1060: .qe (),
1061: .q (reg2hw.status.rxidle.q ),
1062: .qs (status_rxidle_qs)
1063: );
1064:
1065:
1066: // F[rxempty]: 5:5
1067: prim_subreg_ext #(
1068: .DW (1)
1069: ) u_status_rxempty (
1070: .re (status_rxempty_re),
1071: .we (1'b0),
1072: .wd ('0),
1073: .d (hw2reg.status.rxempty.d),
1074: .qre (reg2hw.status.rxempty.re),
1075: .qe (),
1076: .q (reg2hw.status.rxempty.q ),
1077: .qs (status_rxempty_qs)
1078: );
1079:
1080:
1081: // R[rdata]: V(True)
1082:
1083: prim_subreg_ext #(
1084: .DW (8)
1085: ) u_rdata (
1086: .re (rdata_re),
1087: .we (1'b0),
1088: .wd ('0),
1089: .d (hw2reg.rdata.d),
1090: .qre (reg2hw.rdata.re),
1091: .qe (),
1092: .q (reg2hw.rdata.q ),
1093: .qs (rdata_qs)
1094: );
1095:
1096:
1097: // R[wdata]: V(False)
1098:
1099: prim_subreg #(
1100: .DW (8),
1101: .SWACCESS("WO"),
1102: .RESVAL (8'h0)
1103: ) u_wdata (
1104: .clk_i (clk_i ),
1105: .rst_ni (rst_ni ),
1106:
1107: // from register interface
1108: .we (wdata_we),
1109: .wd (wdata_wd),
1110:
1111: // from internal hardware
1112: .de (1'b0),
1113: .d ('0 ),
1114:
1115: // to internal hardware
1116: .qe (reg2hw.wdata.qe),
1117: .q (reg2hw.wdata.q ),
1118:
1119: .qs ()
1120: );
1121:
1122:
1123: // R[fifo_ctrl]: V(False)
1124:
1125: // F[rxrst]: 0:0
1126: prim_subreg #(
1127: .DW (1),
1128: .SWACCESS("WO"),
1129: .RESVAL (1'h0)
1130: ) u_fifo_ctrl_rxrst (
1131: .clk_i (clk_i ),
1132: .rst_ni (rst_ni ),
1133:
1134: // from register interface
1135: .we (fifo_ctrl_rxrst_we),
1136: .wd (fifo_ctrl_rxrst_wd),
1137:
1138: // from internal hardware
1139: .de (1'b0),
1140: .d ('0 ),
1141:
1142: // to internal hardware
1143: .qe (reg2hw.fifo_ctrl.rxrst.qe),
1144: .q (reg2hw.fifo_ctrl.rxrst.q ),
1145:
1146: .qs ()
1147: );
1148:
1149:
1150: // F[txrst]: 1:1
1151: prim_subreg #(
1152: .DW (1),
1153: .SWACCESS("WO"),
1154: .RESVAL (1'h0)
1155: ) u_fifo_ctrl_txrst (
1156: .clk_i (clk_i ),
1157: .rst_ni (rst_ni ),
1158:
1159: // from register interface
1160: .we (fifo_ctrl_txrst_we),
1161: .wd (fifo_ctrl_txrst_wd),
1162:
1163: // from internal hardware
1164: .de (1'b0),
1165: .d ('0 ),
1166:
1167: // to internal hardware
1168: .qe (reg2hw.fifo_ctrl.txrst.qe),
1169: .q (reg2hw.fifo_ctrl.txrst.q ),
1170:
1171: .qs ()
1172: );
1173:
1174:
1175: // F[rxilvl]: 4:2
1176: prim_subreg #(
1177: .DW (3),
1178: .SWACCESS("RW"),
1179: .RESVAL (3'h0)
1180: ) u_fifo_ctrl_rxilvl (
1181: .clk_i (clk_i ),
1182: .rst_ni (rst_ni ),
1183:
1184: // from register interface
1185: .we (fifo_ctrl_rxilvl_we),
1186: .wd (fifo_ctrl_rxilvl_wd),
1187:
1188: // from internal hardware
1189: .de (hw2reg.fifo_ctrl.rxilvl.de),
1190: .d (hw2reg.fifo_ctrl.rxilvl.d ),
1191:
1192: // to internal hardware
1193: .qe (reg2hw.fifo_ctrl.rxilvl.qe),
1194: .q (reg2hw.fifo_ctrl.rxilvl.q ),
1195:
1196: // to register interface (read)
1197: .qs (fifo_ctrl_rxilvl_qs)
1198: );
1199:
1200:
1201: // F[txilvl]: 6:5
1202: prim_subreg #(
1203: .DW (2),
1204: .SWACCESS("RW"),
1205: .RESVAL (2'h0)
1206: ) u_fifo_ctrl_txilvl (
1207: .clk_i (clk_i ),
1208: .rst_ni (rst_ni ),
1209:
1210: // from register interface
1211: .we (fifo_ctrl_txilvl_we),
1212: .wd (fifo_ctrl_txilvl_wd),
1213:
1214: // from internal hardware
1215: .de (hw2reg.fifo_ctrl.txilvl.de),
1216: .d (hw2reg.fifo_ctrl.txilvl.d ),
1217:
1218: // to internal hardware
1219: .qe (reg2hw.fifo_ctrl.txilvl.qe),
1220: .q (reg2hw.fifo_ctrl.txilvl.q ),
1221:
1222: // to register interface (read)
1223: .qs (fifo_ctrl_txilvl_qs)
1224: );
1225:
1226:
1227: // R[fifo_status]: V(True)
1228:
1229: // F[txlvl]: 5:0
1230: prim_subreg_ext #(
1231: .DW (6)
1232: ) u_fifo_status_txlvl (
1233: .re (fifo_status_txlvl_re),
1234: .we (1'b0),
1235: .wd ('0),
1236: .d (hw2reg.fifo_status.txlvl.d),
1237: .qre (),
1238: .qe (),
1239: .q (),
1240: .qs (fifo_status_txlvl_qs)
1241: );
1242:
1243:
1244: // F[rxlvl]: 21:16
1245: prim_subreg_ext #(
1246: .DW (6)
1247: ) u_fifo_status_rxlvl (
1248: .re (fifo_status_rxlvl_re),
1249: .we (1'b0),
1250: .wd ('0),
1251: .d (hw2reg.fifo_status.rxlvl.d),
1252: .qre (),
1253: .qe (),
1254: .q (),
1255: .qs (fifo_status_rxlvl_qs)
1256: );
1257:
1258:
1259: // R[ovrd]: V(False)
1260:
1261: // F[txen]: 0:0
1262: prim_subreg #(
1263: .DW (1),
1264: .SWACCESS("RW"),
1265: .RESVAL (1'h0)
1266: ) u_ovrd_txen (
1267: .clk_i (clk_i ),
1268: .rst_ni (rst_ni ),
1269:
1270: // from register interface
1271: .we (ovrd_txen_we),
1272: .wd (ovrd_txen_wd),
1273:
1274: // from internal hardware
1275: .de (1'b0),
1276: .d ('0 ),
1277:
1278: // to internal hardware
1279: .qe (),
1280: .q (reg2hw.ovrd.txen.q ),
1281:
1282: // to register interface (read)
1283: .qs (ovrd_txen_qs)
1284: );
1285:
1286:
1287: // F[txval]: 1:1
1288: prim_subreg #(
1289: .DW (1),
1290: .SWACCESS("RW"),
1291: .RESVAL (1'h0)
1292: ) u_ovrd_txval (
1293: .clk_i (clk_i ),
1294: .rst_ni (rst_ni ),
1295:
1296: // from register interface
1297: .we (ovrd_txval_we),
1298: .wd (ovrd_txval_wd),
1299:
1300: // from internal hardware
1301: .de (1'b0),
1302: .d ('0 ),
1303:
1304: // to internal hardware
1305: .qe (),
1306: .q (reg2hw.ovrd.txval.q ),
1307:
1308: // to register interface (read)
1309: .qs (ovrd_txval_qs)
1310: );
1311:
1312:
1313: // R[val]: V(True)
1314:
1315: prim_subreg_ext #(
1316: .DW (16)
1317: ) u_val (
1318: .re (val_re),
1319: .we (1'b0),
1320: .wd ('0),
1321: .d (hw2reg.val.d),
1322: .qre (),
1323: .qe (),
1324: .q (),
1325: .qs (val_qs)
1326: );
1327:
1328:
1329: // R[timeout_ctrl]: V(False)
1330:
1331: // F[val]: 23:0
1332: prim_subreg #(
1333: .DW (24),
1334: .SWACCESS("RW"),
1335: .RESVAL (24'h0)
1336: ) u_timeout_ctrl_val (
1337: .clk_i (clk_i ),
1338: .rst_ni (rst_ni ),
1339:
1340: // from register interface
1341: .we (timeout_ctrl_val_we),
1342: .wd (timeout_ctrl_val_wd),
1343:
1344: // from internal hardware
1345: .de (1'b0),
1346: .d ('0 ),
1347:
1348: // to internal hardware
1349: .qe (),
1350: .q (reg2hw.timeout_ctrl.val.q ),
1351:
1352: // to register interface (read)
1353: .qs (timeout_ctrl_val_qs)
1354: );
1355:
1356:
1357: // F[en]: 31:31
1358: prim_subreg #(
1359: .DW (1),
1360: .SWACCESS("RW"),
1361: .RESVAL (1'h0)
1362: ) u_timeout_ctrl_en (
1363: .clk_i (clk_i ),
1364: .rst_ni (rst_ni ),
1365:
1366: // from register interface
1367: .we (timeout_ctrl_en_we),
1368: .wd (timeout_ctrl_en_wd),
1369:
1370: // from internal hardware
1371: .de (1'b0),
1372: .d ('0 ),
1373:
1374: // to internal hardware
1375: .qe (),
1376: .q (reg2hw.timeout_ctrl.en.q ),
1377:
1378: // to register interface (read)
1379: .qs (timeout_ctrl_en_qs)
1380: );
1381:
1382:
1383:
1384:
1385: logic [11:0] addr_hit;
1386: always_comb begin
1387: addr_hit = '0;
1388: addr_hit[ 0] = (reg_addr == UART_INTR_STATE_OFFSET);
1389: addr_hit[ 1] = (reg_addr == UART_INTR_ENABLE_OFFSET);
1390: addr_hit[ 2] = (reg_addr == UART_INTR_TEST_OFFSET);
1391: addr_hit[ 3] = (reg_addr == UART_CTRL_OFFSET);
1392: addr_hit[ 4] = (reg_addr == UART_STATUS_OFFSET);
1393: addr_hit[ 5] = (reg_addr == UART_RDATA_OFFSET);
1394: addr_hit[ 6] = (reg_addr == UART_WDATA_OFFSET);
1395: addr_hit[ 7] = (reg_addr == UART_FIFO_CTRL_OFFSET);
1396: addr_hit[ 8] = (reg_addr == UART_FIFO_STATUS_OFFSET);
1397: addr_hit[ 9] = (reg_addr == UART_OVRD_OFFSET);
1398: addr_hit[10] = (reg_addr == UART_VAL_OFFSET);
1399: addr_hit[11] = (reg_addr == UART_TIMEOUT_CTRL_OFFSET);
1400: end
1401:
1402: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
1403:
1404: // Check sub-word write is permitted
1405: always_comb begin
1406: wr_err = 1'b0;
1407: if (addr_hit[ 0] && reg_we && (UART_PERMIT[ 0] != (UART_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
1408: if (addr_hit[ 1] && reg_we && (UART_PERMIT[ 1] != (UART_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
1409: if (addr_hit[ 2] && reg_we && (UART_PERMIT[ 2] != (UART_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
1410: if (addr_hit[ 3] && reg_we && (UART_PERMIT[ 3] != (UART_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
1411: if (addr_hit[ 4] && reg_we && (UART_PERMIT[ 4] != (UART_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
1412: if (addr_hit[ 5] && reg_we && (UART_PERMIT[ 5] != (UART_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
1413: if (addr_hit[ 6] && reg_we && (UART_PERMIT[ 6] != (UART_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
1414: if (addr_hit[ 7] && reg_we && (UART_PERMIT[ 7] != (UART_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
1415: if (addr_hit[ 8] && reg_we && (UART_PERMIT[ 8] != (UART_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
1416: if (addr_hit[ 9] && reg_we && (UART_PERMIT[ 9] != (UART_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
1417: if (addr_hit[10] && reg_we && (UART_PERMIT[10] != (UART_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
1418: if (addr_hit[11] && reg_we && (UART_PERMIT[11] != (UART_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
1419: end
1420:
1421: assign intr_state_tx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
1422: assign intr_state_tx_watermark_wd = reg_wdata[0];
1423:
1424: assign intr_state_rx_watermark_we = addr_hit[0] & reg_we & ~wr_err;
1425: assign intr_state_rx_watermark_wd = reg_wdata[1];
1426:
1427: assign intr_state_tx_empty_we = addr_hit[0] & reg_we & ~wr_err;
1428: assign intr_state_tx_empty_wd = reg_wdata[2];
1429:
1430: assign intr_state_rx_overflow_we = addr_hit[0] & reg_we & ~wr_err;
1431: assign intr_state_rx_overflow_wd = reg_wdata[3];
1432:
1433: assign intr_state_rx_frame_err_we = addr_hit[0] & reg_we & ~wr_err;
1434: assign intr_state_rx_frame_err_wd = reg_wdata[4];
1435:
1436: assign intr_state_rx_break_err_we = addr_hit[0] & reg_we & ~wr_err;
1437: assign intr_state_rx_break_err_wd = reg_wdata[5];
1438:
1439: assign intr_state_rx_timeout_we = addr_hit[0] & reg_we & ~wr_err;
1440: assign intr_state_rx_timeout_wd = reg_wdata[6];
1441:
1442: assign intr_state_rx_parity_err_we = addr_hit[0] & reg_we & ~wr_err;
1443: assign intr_state_rx_parity_err_wd = reg_wdata[7];
1444:
1445: assign intr_enable_tx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
1446: assign intr_enable_tx_watermark_wd = reg_wdata[0];
1447:
1448: assign intr_enable_rx_watermark_we = addr_hit[1] & reg_we & ~wr_err;
1449: assign intr_enable_rx_watermark_wd = reg_wdata[1];
1450:
1451: assign intr_enable_tx_empty_we = addr_hit[1] & reg_we & ~wr_err;
1452: assign intr_enable_tx_empty_wd = reg_wdata[2];
1453:
1454: assign intr_enable_rx_overflow_we = addr_hit[1] & reg_we & ~wr_err;
1455: assign intr_enable_rx_overflow_wd = reg_wdata[3];
1456:
1457: assign intr_enable_rx_frame_err_we = addr_hit[1] & reg_we & ~wr_err;
1458: assign intr_enable_rx_frame_err_wd = reg_wdata[4];
1459:
1460: assign intr_enable_rx_break_err_we = addr_hit[1] & reg_we & ~wr_err;
1461: assign intr_enable_rx_break_err_wd = reg_wdata[5];
1462:
1463: assign intr_enable_rx_timeout_we = addr_hit[1] & reg_we & ~wr_err;
1464: assign intr_enable_rx_timeout_wd = reg_wdata[6];
1465:
1466: assign intr_enable_rx_parity_err_we = addr_hit[1] & reg_we & ~wr_err;
1467: assign intr_enable_rx_parity_err_wd = reg_wdata[7];
1468:
1469: assign intr_test_tx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
1470: assign intr_test_tx_watermark_wd = reg_wdata[0];
1471:
1472: assign intr_test_rx_watermark_we = addr_hit[2] & reg_we & ~wr_err;
1473: assign intr_test_rx_watermark_wd = reg_wdata[1];
1474:
1475: assign intr_test_tx_empty_we = addr_hit[2] & reg_we & ~wr_err;
1476: assign intr_test_tx_empty_wd = reg_wdata[2];
1477:
1478: assign intr_test_rx_overflow_we = addr_hit[2] & reg_we & ~wr_err;
1479: assign intr_test_rx_overflow_wd = reg_wdata[3];
1480:
1481: assign intr_test_rx_frame_err_we = addr_hit[2] & reg_we & ~wr_err;
1482: assign intr_test_rx_frame_err_wd = reg_wdata[4];
1483:
1484: assign intr_test_rx_break_err_we = addr_hit[2] & reg_we & ~wr_err;
1485: assign intr_test_rx_break_err_wd = reg_wdata[5];
1486:
1487: assign intr_test_rx_timeout_we = addr_hit[2] & reg_we & ~wr_err;
1488: assign intr_test_rx_timeout_wd = reg_wdata[6];
1489:
1490: assign intr_test_rx_parity_err_we = addr_hit[2] & reg_we & ~wr_err;
1491: assign intr_test_rx_parity_err_wd = reg_wdata[7];
1492:
1493: assign ctrl_tx_we = addr_hit[3] & reg_we & ~wr_err;
1494: assign ctrl_tx_wd = reg_wdata[0];
1495:
1496: assign ctrl_rx_we = addr_hit[3] & reg_we & ~wr_err;
1497: assign ctrl_rx_wd = reg_wdata[1];
1498:
1499: assign ctrl_nf_we = addr_hit[3] & reg_we & ~wr_err;
1500: assign ctrl_nf_wd = reg_wdata[2];
1501:
1502: assign ctrl_slpbk_we = addr_hit[3] & reg_we & ~wr_err;
1503: assign ctrl_slpbk_wd = reg_wdata[4];
1504:
1505: assign ctrl_llpbk_we = addr_hit[3] & reg_we & ~wr_err;
1506: assign ctrl_llpbk_wd = reg_wdata[5];
1507:
1508: assign ctrl_parity_en_we = addr_hit[3] & reg_we & ~wr_err;
1509: assign ctrl_parity_en_wd = reg_wdata[6];
1510:
1511: assign ctrl_parity_odd_we = addr_hit[3] & reg_we & ~wr_err;
1512: assign ctrl_parity_odd_wd = reg_wdata[7];
1513:
1514: assign ctrl_rxblvl_we = addr_hit[3] & reg_we & ~wr_err;
1515: assign ctrl_rxblvl_wd = reg_wdata[9:8];
1516:
1517: assign ctrl_nco_we = addr_hit[3] & reg_we & ~wr_err;
1518: assign ctrl_nco_wd = reg_wdata[31:16];
1519:
1520: assign status_txfull_re = addr_hit[4] && reg_re;
1521:
1522: assign status_rxfull_re = addr_hit[4] && reg_re;
1523:
1524: assign status_txempty_re = addr_hit[4] && reg_re;
1525:
1526: assign status_txidle_re = addr_hit[4] && reg_re;
1527:
1528: assign status_rxidle_re = addr_hit[4] && reg_re;
1529:
1530: assign status_rxempty_re = addr_hit[4] && reg_re;
1531:
1532: assign rdata_re = addr_hit[5] && reg_re;
1533:
1534: assign wdata_we = addr_hit[6] & reg_we & ~wr_err;
1535: assign wdata_wd = reg_wdata[7:0];
1536:
1537: assign fifo_ctrl_rxrst_we = addr_hit[7] & reg_we & ~wr_err;
1538: assign fifo_ctrl_rxrst_wd = reg_wdata[0];
1539:
1540: assign fifo_ctrl_txrst_we = addr_hit[7] & reg_we & ~wr_err;
1541: assign fifo_ctrl_txrst_wd = reg_wdata[1];
1542:
1543: assign fifo_ctrl_rxilvl_we = addr_hit[7] & reg_we & ~wr_err;
1544: assign fifo_ctrl_rxilvl_wd = reg_wdata[4:2];
1545:
1546: assign fifo_ctrl_txilvl_we = addr_hit[7] & reg_we & ~wr_err;
1547: assign fifo_ctrl_txilvl_wd = reg_wdata[6:5];
1548:
1549: assign fifo_status_txlvl_re = addr_hit[8] && reg_re;
1550:
1551: assign fifo_status_rxlvl_re = addr_hit[8] && reg_re;
1552:
1553: assign ovrd_txen_we = addr_hit[9] & reg_we & ~wr_err;
1554: assign ovrd_txen_wd = reg_wdata[0];
1555:
1556: assign ovrd_txval_we = addr_hit[9] & reg_we & ~wr_err;
1557: assign ovrd_txval_wd = reg_wdata[1];
1558:
1559: assign val_re = addr_hit[10] && reg_re;
1560:
1561: assign timeout_ctrl_val_we = addr_hit[11] & reg_we & ~wr_err;
1562: assign timeout_ctrl_val_wd = reg_wdata[23:0];
1563:
1564: assign timeout_ctrl_en_we = addr_hit[11] & reg_we & ~wr_err;
1565: assign timeout_ctrl_en_wd = reg_wdata[31];
1566:
1567: // Read data return
1568: always_comb begin
1569: reg_rdata_next = '0;
1570: unique case (1'b1)
1571: addr_hit[0]: begin
1572: reg_rdata_next[0] = intr_state_tx_watermark_qs;
1573: reg_rdata_next[1] = intr_state_rx_watermark_qs;
1574: reg_rdata_next[2] = intr_state_tx_empty_qs;
1575: reg_rdata_next[3] = intr_state_rx_overflow_qs;
1576: reg_rdata_next[4] = intr_state_rx_frame_err_qs;
1577: reg_rdata_next[5] = intr_state_rx_break_err_qs;
1578: reg_rdata_next[6] = intr_state_rx_timeout_qs;
1579: reg_rdata_next[7] = intr_state_rx_parity_err_qs;
1580: end
1581:
1582: addr_hit[1]: begin
1583: reg_rdata_next[0] = intr_enable_tx_watermark_qs;
1584: reg_rdata_next[1] = intr_enable_rx_watermark_qs;
1585: reg_rdata_next[2] = intr_enable_tx_empty_qs;
1586: reg_rdata_next[3] = intr_enable_rx_overflow_qs;
1587: reg_rdata_next[4] = intr_enable_rx_frame_err_qs;
1588: reg_rdata_next[5] = intr_enable_rx_break_err_qs;
1589: reg_rdata_next[6] = intr_enable_rx_timeout_qs;
1590: reg_rdata_next[7] = intr_enable_rx_parity_err_qs;
1591: end
1592:
1593: addr_hit[2]: begin
1594: reg_rdata_next[0] = '0;
1595: reg_rdata_next[1] = '0;
1596: reg_rdata_next[2] = '0;
1597: reg_rdata_next[3] = '0;
1598: reg_rdata_next[4] = '0;
1599: reg_rdata_next[5] = '0;
1600: reg_rdata_next[6] = '0;
1601: reg_rdata_next[7] = '0;
1602: end
1603:
1604: addr_hit[3]: begin
1605: reg_rdata_next[0] = ctrl_tx_qs;
1606: reg_rdata_next[1] = ctrl_rx_qs;
1607: reg_rdata_next[2] = ctrl_nf_qs;
1608: reg_rdata_next[4] = ctrl_slpbk_qs;
1609: reg_rdata_next[5] = ctrl_llpbk_qs;
1610: reg_rdata_next[6] = ctrl_parity_en_qs;
1611: reg_rdata_next[7] = ctrl_parity_odd_qs;
1612: reg_rdata_next[9:8] = ctrl_rxblvl_qs;
1613: reg_rdata_next[31:16] = ctrl_nco_qs;
1614: end
1615:
1616: addr_hit[4]: begin
1617: reg_rdata_next[0] = status_txfull_qs;
1618: reg_rdata_next[1] = status_rxfull_qs;
1619: reg_rdata_next[2] = status_txempty_qs;
1620: reg_rdata_next[3] = status_txidle_qs;
1621: reg_rdata_next[4] = status_rxidle_qs;
1622: reg_rdata_next[5] = status_rxempty_qs;
1623: end
1624:
1625: addr_hit[5]: begin
1626: reg_rdata_next[7:0] = rdata_qs;
1627: end
1628:
1629: addr_hit[6]: begin
1630: reg_rdata_next[7:0] = '0;
1631: end
1632:
1633: addr_hit[7]: begin
1634: reg_rdata_next[0] = '0;
1635: reg_rdata_next[1] = '0;
1636: reg_rdata_next[4:2] = fifo_ctrl_rxilvl_qs;
1637: reg_rdata_next[6:5] = fifo_ctrl_txilvl_qs;
1638: end
1639:
1640: addr_hit[8]: begin
1641: reg_rdata_next[5:0] = fifo_status_txlvl_qs;
1642: reg_rdata_next[21:16] = fifo_status_rxlvl_qs;
1643: end
1644:
1645: addr_hit[9]: begin
1646: reg_rdata_next[0] = ovrd_txen_qs;
1647: reg_rdata_next[1] = ovrd_txval_qs;
1648: end
1649:
1650: addr_hit[10]: begin
1651: reg_rdata_next[15:0] = val_qs;
1652: end
1653:
1654: addr_hit[11]: begin
1655: reg_rdata_next[23:0] = timeout_ctrl_val_qs;
1656: reg_rdata_next[31] = timeout_ctrl_en_qs;
1657: end
1658:
1659: default: begin
1660: reg_rdata_next = '1;
1661: end
1662: endcase
1663: end
1664:
1665: // Assertions for Register Interface
1666: `ASSERT_PULSE(wePulse, reg_we)
1667: `ASSERT_PULSE(rePulse, reg_re)
1668:
1669: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
1670:
1671: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
1672:
1673: // this is formulated as an assumption such that the FPV testbenches do disprove this
1674: // property by mistake
1675: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
1676:
1677: endmodule
1678: