../src/lowrisc_prim_generic_rom_0/rtl/prim_generic_rom.sv Cov: 53.6%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: 
   5: `include "prim_assert.sv"
   6: 
   7: module prim_generic_rom #(
   8:   parameter  int Width       = 32,
   9:   parameter  int Depth       = 2048, // 8kB default
  10:   parameter      MemInitFile = "", // VMEM file to initialize the memory with
  11: 
  12:   localparam int Aw          = $clog2(Depth)
  13: ) (
  14:   input  logic             clk_i,
  15:   input  logic             req_i,
  16:   input  logic [Aw-1:0]    addr_i,
  17:   output logic [Width-1:0] rdata_o
  18: );
  19: 
  20:   logic [Width-1:0] mem [Depth];
  21: 
  22:   always_ff @(posedge clk_i) begin
  23:     if (req_i) begin
  24:       rdata_o <= mem[addr_i];
  25:     end
  26:   end
  27: 
  28:   `include "prim_util_memload.sv"
  29: 
  30:   ////////////////
  31:   // ASSERTIONS //
  32:   ////////////////
  33: 
  34:   // Control Signals should never be X
  35:   `ASSERT(noXOnCsI, !$isunknown(req_i), clk_i, '0)
  36: endmodule
  37: