hw/ip/gpio/rtl/gpio_reg_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Package auto-generated by `reggen` containing data structure
6:
7: package gpio_reg_pkg;
8:
9: ////////////////////////////
10: // Typedefs for registers //
11: ////////////////////////////
12: typedef struct packed {
13: logic [31:0] q;
14: } gpio_reg2hw_intr_state_reg_t;
15:
16: typedef struct packed {
17: logic [31:0] q;
18: } gpio_reg2hw_intr_enable_reg_t;
19:
20: typedef struct packed {
21: logic [31:0] q;
22: logic qe;
23: } gpio_reg2hw_intr_test_reg_t;
24:
25: typedef struct packed {
26: logic [31:0] q;
27: logic qe;
28: } gpio_reg2hw_direct_out_reg_t;
29:
30: typedef struct packed {
31: struct packed {
32: logic [15:0] q;
33: logic qe;
34: } data;
35: struct packed {
36: logic [15:0] q;
37: logic qe;
38: } mask;
39: } gpio_reg2hw_masked_out_lower_reg_t;
40:
41: typedef struct packed {
42: struct packed {
43: logic [15:0] q;
44: logic qe;
45: } data;
46: struct packed {
47: logic [15:0] q;
48: logic qe;
49: } mask;
50: } gpio_reg2hw_masked_out_upper_reg_t;
51:
52: typedef struct packed {
53: logic [31:0] q;
54: logic qe;
55: } gpio_reg2hw_direct_oe_reg_t;
56:
57: typedef struct packed {
58: struct packed {
59: logic [15:0] q;
60: logic qe;
61: } data;
62: struct packed {
63: logic [15:0] q;
64: logic qe;
65: } mask;
66: } gpio_reg2hw_masked_oe_lower_reg_t;
67:
68: typedef struct packed {
69: struct packed {
70: logic [15:0] q;
71: logic qe;
72: } data;
73: struct packed {
74: logic [15:0] q;
75: logic qe;
76: } mask;
77: } gpio_reg2hw_masked_oe_upper_reg_t;
78:
79: typedef struct packed {
80: logic [31:0] q;
81: } gpio_reg2hw_intr_ctrl_en_rising_reg_t;
82:
83: typedef struct packed {
84: logic [31:0] q;
85: } gpio_reg2hw_intr_ctrl_en_falling_reg_t;
86:
87: typedef struct packed {
88: logic [31:0] q;
89: } gpio_reg2hw_intr_ctrl_en_lvlhigh_reg_t;
90:
91: typedef struct packed {
92: logic [31:0] q;
93: } gpio_reg2hw_intr_ctrl_en_lvllow_reg_t;
94:
95: typedef struct packed {
96: logic [31:0] q;
97: } gpio_reg2hw_ctrl_en_input_filter_reg_t;
98:
99:
100: typedef struct packed {
101: logic [31:0] d;
102: logic de;
103: } gpio_hw2reg_intr_state_reg_t;
104:
105: typedef struct packed {
106: logic [31:0] d;
107: logic de;
108: } gpio_hw2reg_data_in_reg_t;
109:
110: typedef struct packed {
111: logic [31:0] d;
112: } gpio_hw2reg_direct_out_reg_t;
113:
114: typedef struct packed {
115: struct packed {
116: logic [15:0] d;
117: } data;
118: struct packed {
119: logic [15:0] d;
120: } mask;
121: } gpio_hw2reg_masked_out_lower_reg_t;
122:
123: typedef struct packed {
124: struct packed {
125: logic [15:0] d;
126: } data;
127: struct packed {
128: logic [15:0] d;
129: } mask;
130: } gpio_hw2reg_masked_out_upper_reg_t;
131:
132: typedef struct packed {
133: logic [31:0] d;
134: } gpio_hw2reg_direct_oe_reg_t;
135:
136: typedef struct packed {
137: struct packed {
138: logic [15:0] d;
139: } data;
140: struct packed {
141: logic [15:0] d;
142: } mask;
143: } gpio_hw2reg_masked_oe_lower_reg_t;
144:
145: typedef struct packed {
146: struct packed {
147: logic [15:0] d;
148: } data;
149: struct packed {
150: logic [15:0] d;
151: } mask;
152: } gpio_hw2reg_masked_oe_upper_reg_t;
153:
154:
155: ///////////////////////////////////////
156: // Register to internal design logic //
157: ///////////////////////////////////////
158: typedef struct packed {
159: gpio_reg2hw_intr_state_reg_t intr_state; // [458:427]
160: gpio_reg2hw_intr_enable_reg_t intr_enable; // [426:395]
161: gpio_reg2hw_intr_test_reg_t intr_test; // [394:362]
162: gpio_reg2hw_direct_out_reg_t direct_out; // [361:329]
163: gpio_reg2hw_masked_out_lower_reg_t masked_out_lower; // [328:295]
164: gpio_reg2hw_masked_out_upper_reg_t masked_out_upper; // [294:261]
165: gpio_reg2hw_direct_oe_reg_t direct_oe; // [260:228]
166: gpio_reg2hw_masked_oe_lower_reg_t masked_oe_lower; // [227:194]
167: gpio_reg2hw_masked_oe_upper_reg_t masked_oe_upper; // [193:160]
168: gpio_reg2hw_intr_ctrl_en_rising_reg_t intr_ctrl_en_rising; // [159:128]
169: gpio_reg2hw_intr_ctrl_en_falling_reg_t intr_ctrl_en_falling; // [127:96]
170: gpio_reg2hw_intr_ctrl_en_lvlhigh_reg_t intr_ctrl_en_lvlhigh; // [95:64]
171: gpio_reg2hw_intr_ctrl_en_lvllow_reg_t intr_ctrl_en_lvllow; // [63:32]
172: gpio_reg2hw_ctrl_en_input_filter_reg_t ctrl_en_input_filter; // [31:0]
173: } gpio_reg2hw_t;
174:
175: ///////////////////////////////////////
176: // Internal design logic to register //
177: ///////////////////////////////////////
178: typedef struct packed {
179: gpio_hw2reg_intr_state_reg_t intr_state; // [257:226]
180: gpio_hw2reg_data_in_reg_t data_in; // [225:226]
181: gpio_hw2reg_direct_out_reg_t direct_out; // [225:193]
182: gpio_hw2reg_masked_out_lower_reg_t masked_out_lower; // [192:159]
183: gpio_hw2reg_masked_out_upper_reg_t masked_out_upper; // [158:125]
184: gpio_hw2reg_direct_oe_reg_t direct_oe; // [124:92]
185: gpio_hw2reg_masked_oe_lower_reg_t masked_oe_lower; // [91:58]
186: gpio_hw2reg_masked_oe_upper_reg_t masked_oe_upper; // [57:24]
187: } gpio_hw2reg_t;
188:
189: // Register Address
190: parameter logic [5:0] GPIO_INTR_STATE_OFFSET = 6'h 0;
191: parameter logic [5:0] GPIO_INTR_ENABLE_OFFSET = 6'h 4;
192: parameter logic [5:0] GPIO_INTR_TEST_OFFSET = 6'h 8;
193: parameter logic [5:0] GPIO_DATA_IN_OFFSET = 6'h c;
194: parameter logic [5:0] GPIO_DIRECT_OUT_OFFSET = 6'h 10;
195: parameter logic [5:0] GPIO_MASKED_OUT_LOWER_OFFSET = 6'h 14;
196: parameter logic [5:0] GPIO_MASKED_OUT_UPPER_OFFSET = 6'h 18;
197: parameter logic [5:0] GPIO_DIRECT_OE_OFFSET = 6'h 1c;
198: parameter logic [5:0] GPIO_MASKED_OE_LOWER_OFFSET = 6'h 20;
199: parameter logic [5:0] GPIO_MASKED_OE_UPPER_OFFSET = 6'h 24;
200: parameter logic [5:0] GPIO_INTR_CTRL_EN_RISING_OFFSET = 6'h 28;
201: parameter logic [5:0] GPIO_INTR_CTRL_EN_FALLING_OFFSET = 6'h 2c;
202: parameter logic [5:0] GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET = 6'h 30;
203: parameter logic [5:0] GPIO_INTR_CTRL_EN_LVLLOW_OFFSET = 6'h 34;
204: parameter logic [5:0] GPIO_CTRL_EN_INPUT_FILTER_OFFSET = 6'h 38;
205:
206:
207: // Register Index
208: typedef enum int {
209: GPIO_INTR_STATE,
210: GPIO_INTR_ENABLE,
211: GPIO_INTR_TEST,
212: GPIO_DATA_IN,
213: GPIO_DIRECT_OUT,
214: GPIO_MASKED_OUT_LOWER,
215: GPIO_MASKED_OUT_UPPER,
216: GPIO_DIRECT_OE,
217: GPIO_MASKED_OE_LOWER,
218: GPIO_MASKED_OE_UPPER,
219: GPIO_INTR_CTRL_EN_RISING,
220: GPIO_INTR_CTRL_EN_FALLING,
221: GPIO_INTR_CTRL_EN_LVLHIGH,
222: GPIO_INTR_CTRL_EN_LVLLOW,
223: GPIO_CTRL_EN_INPUT_FILTER
224: } gpio_id_e;
225:
226: // Register width information to check illegal writes
227: parameter logic [3:0] GPIO_PERMIT [15] = '{
228: 4'b 1111, // index[ 0] GPIO_INTR_STATE
229: 4'b 1111, // index[ 1] GPIO_INTR_ENABLE
230: 4'b 1111, // index[ 2] GPIO_INTR_TEST
231: 4'b 1111, // index[ 3] GPIO_DATA_IN
232: 4'b 1111, // index[ 4] GPIO_DIRECT_OUT
233: 4'b 1111, // index[ 5] GPIO_MASKED_OUT_LOWER
234: 4'b 1111, // index[ 6] GPIO_MASKED_OUT_UPPER
235: 4'b 1111, // index[ 7] GPIO_DIRECT_OE
236: 4'b 1111, // index[ 8] GPIO_MASKED_OE_LOWER
237: 4'b 1111, // index[ 9] GPIO_MASKED_OE_UPPER
238: 4'b 1111, // index[10] GPIO_INTR_CTRL_EN_RISING
239: 4'b 1111, // index[11] GPIO_INTR_CTRL_EN_FALLING
240: 4'b 1111, // index[12] GPIO_INTR_CTRL_EN_LVLHIGH
241: 4'b 1111, // index[13] GPIO_INTR_CTRL_EN_LVLLOW
242: 4'b 1111 // index[14] GPIO_CTRL_EN_INPUT_FILTER
243: };
244: endpackage
245:
246: