hw/top_earlgrey/ip/rv_plic/rtl/autogen/rv_plic_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: module rv_plic_reg_top (
8: input clk_i,
9: input rst_ni,
10:
11: // Below Regster interface can be changed
12: input tlul_pkg::tl_h2d_t tl_i,
13: output tlul_pkg::tl_d2h_t tl_o,
14: // To HW
15: output rv_plic_reg_pkg::rv_plic_reg2hw_t reg2hw, // Write
16: input rv_plic_reg_pkg::rv_plic_hw2reg_t hw2reg, // Read
17:
18: // Config
19: input devmode_i // If 1, explicit error return for unmapped register access
20: );
21:
22: import rv_plic_reg_pkg::* ;
23:
24: localparam AW = 10;
25: localparam DW = 32;
26: localparam DBW = DW/8; // Byte Width
27:
28: // register signals
29: logic reg_we;
30: logic reg_re;
31: logic [AW-1:0] reg_addr;
32: logic [DW-1:0] reg_wdata;
33: logic [DBW-1:0] reg_be;
34: logic [DW-1:0] reg_rdata;
35: logic reg_error;
36:
37: logic addrmiss, wr_err;
38:
39: logic [DW-1:0] reg_rdata_next;
40:
41: tlul_pkg::tl_h2d_t tl_reg_h2d;
42: tlul_pkg::tl_d2h_t tl_reg_d2h;
43:
44: assign tl_reg_h2d = tl_i;
45: assign tl_o = tl_reg_d2h;
46:
47: tlul_adapter_reg #(
48: .RegAw(AW),
49: .RegDw(DW)
50: ) u_reg_if (
51: .clk_i,
52: .rst_ni,
53:
54: .tl_i (tl_reg_h2d),
55: .tl_o (tl_reg_d2h),
56:
57: .we_o (reg_we),
58: .re_o (reg_re),
59: .addr_o (reg_addr),
60: .wdata_o (reg_wdata),
61: .be_o (reg_be),
62: .rdata_i (reg_rdata),
63: .error_i (reg_error)
64: );
65:
66: assign reg_rdata = reg_rdata_next ;
67: assign reg_error = (devmode_i & addrmiss) | wr_err ;
68:
69: // Define SW related signals
70: // Format: __{wd|we|qs}
71: // or _{wd|we|qs} if field == 1 or 0
72: logic ip0_p0_qs;
73: logic ip0_p1_qs;
74: logic ip0_p2_qs;
75: logic ip0_p3_qs;
76: logic ip0_p4_qs;
77: logic ip0_p5_qs;
78: logic ip0_p6_qs;
79: logic ip0_p7_qs;
80: logic ip0_p8_qs;
81: logic ip0_p9_qs;
82: logic ip0_p10_qs;
83: logic ip0_p11_qs;
84: logic ip0_p12_qs;
85: logic ip0_p13_qs;
86: logic ip0_p14_qs;
87: logic ip0_p15_qs;
88: logic ip0_p16_qs;
89: logic ip0_p17_qs;
90: logic ip0_p18_qs;
91: logic ip0_p19_qs;
92: logic ip0_p20_qs;
93: logic ip0_p21_qs;
94: logic ip0_p22_qs;
95: logic ip0_p23_qs;
96: logic ip0_p24_qs;
97: logic ip0_p25_qs;
98: logic ip0_p26_qs;
99: logic ip0_p27_qs;
100: logic ip0_p28_qs;
101: logic ip0_p29_qs;
102: logic ip0_p30_qs;
103: logic ip0_p31_qs;
104: logic ip1_p32_qs;
105: logic ip1_p33_qs;
106: logic ip1_p34_qs;
107: logic ip1_p35_qs;
108: logic ip1_p36_qs;
109: logic ip1_p37_qs;
110: logic ip1_p38_qs;
111: logic ip1_p39_qs;
112: logic ip1_p40_qs;
113: logic ip1_p41_qs;
114: logic ip1_p42_qs;
115: logic ip1_p43_qs;
116: logic ip1_p44_qs;
117: logic ip1_p45_qs;
118: logic ip1_p46_qs;
119: logic ip1_p47_qs;
120: logic ip1_p48_qs;
121: logic ip1_p49_qs;
122: logic ip1_p50_qs;
123: logic ip1_p51_qs;
124: logic ip1_p52_qs;
125: logic ip1_p53_qs;
126: logic ip1_p54_qs;
127: logic ip1_p55_qs;
128: logic ip1_p56_qs;
129: logic ip1_p57_qs;
130: logic ip1_p58_qs;
131: logic ip1_p59_qs;
132: logic ip1_p60_qs;
133: logic ip1_p61_qs;
134: logic ip1_p62_qs;
135: logic le0_le0_qs;
136: logic le0_le0_wd;
137: logic le0_le0_we;
138: logic le0_le1_qs;
139: logic le0_le1_wd;
140: logic le0_le1_we;
141: logic le0_le2_qs;
142: logic le0_le2_wd;
143: logic le0_le2_we;
144: logic le0_le3_qs;
145: logic le0_le3_wd;
146: logic le0_le3_we;
147: logic le0_le4_qs;
148: logic le0_le4_wd;
149: logic le0_le4_we;
150: logic le0_le5_qs;
151: logic le0_le5_wd;
152: logic le0_le5_we;
153: logic le0_le6_qs;
154: logic le0_le6_wd;
155: logic le0_le6_we;
156: logic le0_le7_qs;
157: logic le0_le7_wd;
158: logic le0_le7_we;
159: logic le0_le8_qs;
160: logic le0_le8_wd;
161: logic le0_le8_we;
162: logic le0_le9_qs;
163: logic le0_le9_wd;
164: logic le0_le9_we;
165: logic le0_le10_qs;
166: logic le0_le10_wd;
167: logic le0_le10_we;
168: logic le0_le11_qs;
169: logic le0_le11_wd;
170: logic le0_le11_we;
171: logic le0_le12_qs;
172: logic le0_le12_wd;
173: logic le0_le12_we;
174: logic le0_le13_qs;
175: logic le0_le13_wd;
176: logic le0_le13_we;
177: logic le0_le14_qs;
178: logic le0_le14_wd;
179: logic le0_le14_we;
180: logic le0_le15_qs;
181: logic le0_le15_wd;
182: logic le0_le15_we;
183: logic le0_le16_qs;
184: logic le0_le16_wd;
185: logic le0_le16_we;
186: logic le0_le17_qs;
187: logic le0_le17_wd;
188: logic le0_le17_we;
189: logic le0_le18_qs;
190: logic le0_le18_wd;
191: logic le0_le18_we;
192: logic le0_le19_qs;
193: logic le0_le19_wd;
194: logic le0_le19_we;
195: logic le0_le20_qs;
196: logic le0_le20_wd;
197: logic le0_le20_we;
198: logic le0_le21_qs;
199: logic le0_le21_wd;
200: logic le0_le21_we;
201: logic le0_le22_qs;
202: logic le0_le22_wd;
203: logic le0_le22_we;
204: logic le0_le23_qs;
205: logic le0_le23_wd;
206: logic le0_le23_we;
207: logic le0_le24_qs;
208: logic le0_le24_wd;
209: logic le0_le24_we;
210: logic le0_le25_qs;
211: logic le0_le25_wd;
212: logic le0_le25_we;
213: logic le0_le26_qs;
214: logic le0_le26_wd;
215: logic le0_le26_we;
216: logic le0_le27_qs;
217: logic le0_le27_wd;
218: logic le0_le27_we;
219: logic le0_le28_qs;
220: logic le0_le28_wd;
221: logic le0_le28_we;
222: logic le0_le29_qs;
223: logic le0_le29_wd;
224: logic le0_le29_we;
225: logic le0_le30_qs;
226: logic le0_le30_wd;
227: logic le0_le30_we;
228: logic le0_le31_qs;
229: logic le0_le31_wd;
230: logic le0_le31_we;
231: logic le1_le32_qs;
232: logic le1_le32_wd;
233: logic le1_le32_we;
234: logic le1_le33_qs;
235: logic le1_le33_wd;
236: logic le1_le33_we;
237: logic le1_le34_qs;
238: logic le1_le34_wd;
239: logic le1_le34_we;
240: logic le1_le35_qs;
241: logic le1_le35_wd;
242: logic le1_le35_we;
243: logic le1_le36_qs;
244: logic le1_le36_wd;
245: logic le1_le36_we;
246: logic le1_le37_qs;
247: logic le1_le37_wd;
248: logic le1_le37_we;
249: logic le1_le38_qs;
250: logic le1_le38_wd;
251: logic le1_le38_we;
252: logic le1_le39_qs;
253: logic le1_le39_wd;
254: logic le1_le39_we;
255: logic le1_le40_qs;
256: logic le1_le40_wd;
257: logic le1_le40_we;
258: logic le1_le41_qs;
259: logic le1_le41_wd;
260: logic le1_le41_we;
261: logic le1_le42_qs;
262: logic le1_le42_wd;
263: logic le1_le42_we;
264: logic le1_le43_qs;
265: logic le1_le43_wd;
266: logic le1_le43_we;
267: logic le1_le44_qs;
268: logic le1_le44_wd;
269: logic le1_le44_we;
270: logic le1_le45_qs;
271: logic le1_le45_wd;
272: logic le1_le45_we;
273: logic le1_le46_qs;
274: logic le1_le46_wd;
275: logic le1_le46_we;
276: logic le1_le47_qs;
277: logic le1_le47_wd;
278: logic le1_le47_we;
279: logic le1_le48_qs;
280: logic le1_le48_wd;
281: logic le1_le48_we;
282: logic le1_le49_qs;
283: logic le1_le49_wd;
284: logic le1_le49_we;
285: logic le1_le50_qs;
286: logic le1_le50_wd;
287: logic le1_le50_we;
288: logic le1_le51_qs;
289: logic le1_le51_wd;
290: logic le1_le51_we;
291: logic le1_le52_qs;
292: logic le1_le52_wd;
293: logic le1_le52_we;
294: logic le1_le53_qs;
295: logic le1_le53_wd;
296: logic le1_le53_we;
297: logic le1_le54_qs;
298: logic le1_le54_wd;
299: logic le1_le54_we;
300: logic le1_le55_qs;
301: logic le1_le55_wd;
302: logic le1_le55_we;
303: logic le1_le56_qs;
304: logic le1_le56_wd;
305: logic le1_le56_we;
306: logic le1_le57_qs;
307: logic le1_le57_wd;
308: logic le1_le57_we;
309: logic le1_le58_qs;
310: logic le1_le58_wd;
311: logic le1_le58_we;
312: logic le1_le59_qs;
313: logic le1_le59_wd;
314: logic le1_le59_we;
315: logic le1_le60_qs;
316: logic le1_le60_wd;
317: logic le1_le60_we;
318: logic le1_le61_qs;
319: logic le1_le61_wd;
320: logic le1_le61_we;
321: logic le1_le62_qs;
322: logic le1_le62_wd;
323: logic le1_le62_we;
324: logic [1:0] prio0_qs;
325: logic [1:0] prio0_wd;
326: logic prio0_we;
327: logic [1:0] prio1_qs;
328: logic [1:0] prio1_wd;
329: logic prio1_we;
330: logic [1:0] prio2_qs;
331: logic [1:0] prio2_wd;
332: logic prio2_we;
333: logic [1:0] prio3_qs;
334: logic [1:0] prio3_wd;
335: logic prio3_we;
336: logic [1:0] prio4_qs;
337: logic [1:0] prio4_wd;
338: logic prio4_we;
339: logic [1:0] prio5_qs;
340: logic [1:0] prio5_wd;
341: logic prio5_we;
342: logic [1:0] prio6_qs;
343: logic [1:0] prio6_wd;
344: logic prio6_we;
345: logic [1:0] prio7_qs;
346: logic [1:0] prio7_wd;
347: logic prio7_we;
348: logic [1:0] prio8_qs;
349: logic [1:0] prio8_wd;
350: logic prio8_we;
351: logic [1:0] prio9_qs;
352: logic [1:0] prio9_wd;
353: logic prio9_we;
354: logic [1:0] prio10_qs;
355: logic [1:0] prio10_wd;
356: logic prio10_we;
357: logic [1:0] prio11_qs;
358: logic [1:0] prio11_wd;
359: logic prio11_we;
360: logic [1:0] prio12_qs;
361: logic [1:0] prio12_wd;
362: logic prio12_we;
363: logic [1:0] prio13_qs;
364: logic [1:0] prio13_wd;
365: logic prio13_we;
366: logic [1:0] prio14_qs;
367: logic [1:0] prio14_wd;
368: logic prio14_we;
369: logic [1:0] prio15_qs;
370: logic [1:0] prio15_wd;
371: logic prio15_we;
372: logic [1:0] prio16_qs;
373: logic [1:0] prio16_wd;
374: logic prio16_we;
375: logic [1:0] prio17_qs;
376: logic [1:0] prio17_wd;
377: logic prio17_we;
378: logic [1:0] prio18_qs;
379: logic [1:0] prio18_wd;
380: logic prio18_we;
381: logic [1:0] prio19_qs;
382: logic [1:0] prio19_wd;
383: logic prio19_we;
384: logic [1:0] prio20_qs;
385: logic [1:0] prio20_wd;
386: logic prio20_we;
387: logic [1:0] prio21_qs;
388: logic [1:0] prio21_wd;
389: logic prio21_we;
390: logic [1:0] prio22_qs;
391: logic [1:0] prio22_wd;
392: logic prio22_we;
393: logic [1:0] prio23_qs;
394: logic [1:0] prio23_wd;
395: logic prio23_we;
396: logic [1:0] prio24_qs;
397: logic [1:0] prio24_wd;
398: logic prio24_we;
399: logic [1:0] prio25_qs;
400: logic [1:0] prio25_wd;
401: logic prio25_we;
402: logic [1:0] prio26_qs;
403: logic [1:0] prio26_wd;
404: logic prio26_we;
405: logic [1:0] prio27_qs;
406: logic [1:0] prio27_wd;
407: logic prio27_we;
408: logic [1:0] prio28_qs;
409: logic [1:0] prio28_wd;
410: logic prio28_we;
411: logic [1:0] prio29_qs;
412: logic [1:0] prio29_wd;
413: logic prio29_we;
414: logic [1:0] prio30_qs;
415: logic [1:0] prio30_wd;
416: logic prio30_we;
417: logic [1:0] prio31_qs;
418: logic [1:0] prio31_wd;
419: logic prio31_we;
420: logic [1:0] prio32_qs;
421: logic [1:0] prio32_wd;
422: logic prio32_we;
423: logic [1:0] prio33_qs;
424: logic [1:0] prio33_wd;
425: logic prio33_we;
426: logic [1:0] prio34_qs;
427: logic [1:0] prio34_wd;
428: logic prio34_we;
429: logic [1:0] prio35_qs;
430: logic [1:0] prio35_wd;
431: logic prio35_we;
432: logic [1:0] prio36_qs;
433: logic [1:0] prio36_wd;
434: logic prio36_we;
435: logic [1:0] prio37_qs;
436: logic [1:0] prio37_wd;
437: logic prio37_we;
438: logic [1:0] prio38_qs;
439: logic [1:0] prio38_wd;
440: logic prio38_we;
441: logic [1:0] prio39_qs;
442: logic [1:0] prio39_wd;
443: logic prio39_we;
444: logic [1:0] prio40_qs;
445: logic [1:0] prio40_wd;
446: logic prio40_we;
447: logic [1:0] prio41_qs;
448: logic [1:0] prio41_wd;
449: logic prio41_we;
450: logic [1:0] prio42_qs;
451: logic [1:0] prio42_wd;
452: logic prio42_we;
453: logic [1:0] prio43_qs;
454: logic [1:0] prio43_wd;
455: logic prio43_we;
456: logic [1:0] prio44_qs;
457: logic [1:0] prio44_wd;
458: logic prio44_we;
459: logic [1:0] prio45_qs;
460: logic [1:0] prio45_wd;
461: logic prio45_we;
462: logic [1:0] prio46_qs;
463: logic [1:0] prio46_wd;
464: logic prio46_we;
465: logic [1:0] prio47_qs;
466: logic [1:0] prio47_wd;
467: logic prio47_we;
468: logic [1:0] prio48_qs;
469: logic [1:0] prio48_wd;
470: logic prio48_we;
471: logic [1:0] prio49_qs;
472: logic [1:0] prio49_wd;
473: logic prio49_we;
474: logic [1:0] prio50_qs;
475: logic [1:0] prio50_wd;
476: logic prio50_we;
477: logic [1:0] prio51_qs;
478: logic [1:0] prio51_wd;
479: logic prio51_we;
480: logic [1:0] prio52_qs;
481: logic [1:0] prio52_wd;
482: logic prio52_we;
483: logic [1:0] prio53_qs;
484: logic [1:0] prio53_wd;
485: logic prio53_we;
486: logic [1:0] prio54_qs;
487: logic [1:0] prio54_wd;
488: logic prio54_we;
489: logic [1:0] prio55_qs;
490: logic [1:0] prio55_wd;
491: logic prio55_we;
492: logic [1:0] prio56_qs;
493: logic [1:0] prio56_wd;
494: logic prio56_we;
495: logic [1:0] prio57_qs;
496: logic [1:0] prio57_wd;
497: logic prio57_we;
498: logic [1:0] prio58_qs;
499: logic [1:0] prio58_wd;
500: logic prio58_we;
501: logic [1:0] prio59_qs;
502: logic [1:0] prio59_wd;
503: logic prio59_we;
504: logic [1:0] prio60_qs;
505: logic [1:0] prio60_wd;
506: logic prio60_we;
507: logic [1:0] prio61_qs;
508: logic [1:0] prio61_wd;
509: logic prio61_we;
510: logic [1:0] prio62_qs;
511: logic [1:0] prio62_wd;
512: logic prio62_we;
513: logic ie00_e0_qs;
514: logic ie00_e0_wd;
515: logic ie00_e0_we;
516: logic ie00_e1_qs;
517: logic ie00_e1_wd;
518: logic ie00_e1_we;
519: logic ie00_e2_qs;
520: logic ie00_e2_wd;
521: logic ie00_e2_we;
522: logic ie00_e3_qs;
523: logic ie00_e3_wd;
524: logic ie00_e3_we;
525: logic ie00_e4_qs;
526: logic ie00_e4_wd;
527: logic ie00_e4_we;
528: logic ie00_e5_qs;
529: logic ie00_e5_wd;
530: logic ie00_e5_we;
531: logic ie00_e6_qs;
532: logic ie00_e6_wd;
533: logic ie00_e6_we;
534: logic ie00_e7_qs;
535: logic ie00_e7_wd;
536: logic ie00_e7_we;
537: logic ie00_e8_qs;
538: logic ie00_e8_wd;
539: logic ie00_e8_we;
540: logic ie00_e9_qs;
541: logic ie00_e9_wd;
542: logic ie00_e9_we;
543: logic ie00_e10_qs;
544: logic ie00_e10_wd;
545: logic ie00_e10_we;
546: logic ie00_e11_qs;
547: logic ie00_e11_wd;
548: logic ie00_e11_we;
549: logic ie00_e12_qs;
550: logic ie00_e12_wd;
551: logic ie00_e12_we;
552: logic ie00_e13_qs;
553: logic ie00_e13_wd;
554: logic ie00_e13_we;
555: logic ie00_e14_qs;
556: logic ie00_e14_wd;
557: logic ie00_e14_we;
558: logic ie00_e15_qs;
559: logic ie00_e15_wd;
560: logic ie00_e15_we;
561: logic ie00_e16_qs;
562: logic ie00_e16_wd;
563: logic ie00_e16_we;
564: logic ie00_e17_qs;
565: logic ie00_e17_wd;
566: logic ie00_e17_we;
567: logic ie00_e18_qs;
568: logic ie00_e18_wd;
569: logic ie00_e18_we;
570: logic ie00_e19_qs;
571: logic ie00_e19_wd;
572: logic ie00_e19_we;
573: logic ie00_e20_qs;
574: logic ie00_e20_wd;
575: logic ie00_e20_we;
576: logic ie00_e21_qs;
577: logic ie00_e21_wd;
578: logic ie00_e21_we;
579: logic ie00_e22_qs;
580: logic ie00_e22_wd;
581: logic ie00_e22_we;
582: logic ie00_e23_qs;
583: logic ie00_e23_wd;
584: logic ie00_e23_we;
585: logic ie00_e24_qs;
586: logic ie00_e24_wd;
587: logic ie00_e24_we;
588: logic ie00_e25_qs;
589: logic ie00_e25_wd;
590: logic ie00_e25_we;
591: logic ie00_e26_qs;
592: logic ie00_e26_wd;
593: logic ie00_e26_we;
594: logic ie00_e27_qs;
595: logic ie00_e27_wd;
596: logic ie00_e27_we;
597: logic ie00_e28_qs;
598: logic ie00_e28_wd;
599: logic ie00_e28_we;
600: logic ie00_e29_qs;
601: logic ie00_e29_wd;
602: logic ie00_e29_we;
603: logic ie00_e30_qs;
604: logic ie00_e30_wd;
605: logic ie00_e30_we;
606: logic ie00_e31_qs;
607: logic ie00_e31_wd;
608: logic ie00_e31_we;
609: logic ie01_e32_qs;
610: logic ie01_e32_wd;
611: logic ie01_e32_we;
612: logic ie01_e33_qs;
613: logic ie01_e33_wd;
614: logic ie01_e33_we;
615: logic ie01_e34_qs;
616: logic ie01_e34_wd;
617: logic ie01_e34_we;
618: logic ie01_e35_qs;
619: logic ie01_e35_wd;
620: logic ie01_e35_we;
621: logic ie01_e36_qs;
622: logic ie01_e36_wd;
623: logic ie01_e36_we;
624: logic ie01_e37_qs;
625: logic ie01_e37_wd;
626: logic ie01_e37_we;
627: logic ie01_e38_qs;
628: logic ie01_e38_wd;
629: logic ie01_e38_we;
630: logic ie01_e39_qs;
631: logic ie01_e39_wd;
632: logic ie01_e39_we;
633: logic ie01_e40_qs;
634: logic ie01_e40_wd;
635: logic ie01_e40_we;
636: logic ie01_e41_qs;
637: logic ie01_e41_wd;
638: logic ie01_e41_we;
639: logic ie01_e42_qs;
640: logic ie01_e42_wd;
641: logic ie01_e42_we;
642: logic ie01_e43_qs;
643: logic ie01_e43_wd;
644: logic ie01_e43_we;
645: logic ie01_e44_qs;
646: logic ie01_e44_wd;
647: logic ie01_e44_we;
648: logic ie01_e45_qs;
649: logic ie01_e45_wd;
650: logic ie01_e45_we;
651: logic ie01_e46_qs;
652: logic ie01_e46_wd;
653: logic ie01_e46_we;
654: logic ie01_e47_qs;
655: logic ie01_e47_wd;
656: logic ie01_e47_we;
657: logic ie01_e48_qs;
658: logic ie01_e48_wd;
659: logic ie01_e48_we;
660: logic ie01_e49_qs;
661: logic ie01_e49_wd;
662: logic ie01_e49_we;
663: logic ie01_e50_qs;
664: logic ie01_e50_wd;
665: logic ie01_e50_we;
666: logic ie01_e51_qs;
667: logic ie01_e51_wd;
668: logic ie01_e51_we;
669: logic ie01_e52_qs;
670: logic ie01_e52_wd;
671: logic ie01_e52_we;
672: logic ie01_e53_qs;
673: logic ie01_e53_wd;
674: logic ie01_e53_we;
675: logic ie01_e54_qs;
676: logic ie01_e54_wd;
677: logic ie01_e54_we;
678: logic ie01_e55_qs;
679: logic ie01_e55_wd;
680: logic ie01_e55_we;
681: logic ie01_e56_qs;
682: logic ie01_e56_wd;
683: logic ie01_e56_we;
684: logic ie01_e57_qs;
685: logic ie01_e57_wd;
686: logic ie01_e57_we;
687: logic ie01_e58_qs;
688: logic ie01_e58_wd;
689: logic ie01_e58_we;
690: logic ie01_e59_qs;
691: logic ie01_e59_wd;
692: logic ie01_e59_we;
693: logic ie01_e60_qs;
694: logic ie01_e60_wd;
695: logic ie01_e60_we;
696: logic ie01_e61_qs;
697: logic ie01_e61_wd;
698: logic ie01_e61_we;
699: logic ie01_e62_qs;
700: logic ie01_e62_wd;
701: logic ie01_e62_we;
702: logic [1:0] threshold0_qs;
703: logic [1:0] threshold0_wd;
704: logic threshold0_we;
705: logic [5:0] cc0_qs;
706: logic [5:0] cc0_wd;
707: logic cc0_we;
708: logic cc0_re;
709: logic msip0_qs;
710: logic msip0_wd;
711: logic msip0_we;
712:
713: // Register instances
714:
715: // Subregister 0 of Multireg ip
716: // R[ip0]: V(False)
717:
718: // F[p0]: 0:0
719: prim_subreg #(
720: .DW (1),
721: .SWACCESS("RO"),
722: .RESVAL (1'h0)
723: ) u_ip0_p0 (
724: .clk_i (clk_i ),
725: .rst_ni (rst_ni ),
726:
727: .we (1'b0),
728: .wd ('0 ),
729:
730: // from internal hardware
731: .de (hw2reg.ip[0].de),
732: .d (hw2reg.ip[0].d ),
733:
734: // to internal hardware
735: .qe (),
736: .q (),
737:
738: // to register interface (read)
739: .qs (ip0_p0_qs)
740: );
741:
742:
743: // F[p1]: 1:1
744: prim_subreg #(
745: .DW (1),
746: .SWACCESS("RO"),
747: .RESVAL (1'h0)
748: ) u_ip0_p1 (
749: .clk_i (clk_i ),
750: .rst_ni (rst_ni ),
751:
752: .we (1'b0),
753: .wd ('0 ),
754:
755: // from internal hardware
756: .de (hw2reg.ip[1].de),
757: .d (hw2reg.ip[1].d ),
758:
759: // to internal hardware
760: .qe (),
761: .q (),
762:
763: // to register interface (read)
764: .qs (ip0_p1_qs)
765: );
766:
767:
768: // F[p2]: 2:2
769: prim_subreg #(
770: .DW (1),
771: .SWACCESS("RO"),
772: .RESVAL (1'h0)
773: ) u_ip0_p2 (
774: .clk_i (clk_i ),
775: .rst_ni (rst_ni ),
776:
777: .we (1'b0),
778: .wd ('0 ),
779:
780: // from internal hardware
781: .de (hw2reg.ip[2].de),
782: .d (hw2reg.ip[2].d ),
783:
784: // to internal hardware
785: .qe (),
786: .q (),
787:
788: // to register interface (read)
789: .qs (ip0_p2_qs)
790: );
791:
792:
793: // F[p3]: 3:3
794: prim_subreg #(
795: .DW (1),
796: .SWACCESS("RO"),
797: .RESVAL (1'h0)
798: ) u_ip0_p3 (
799: .clk_i (clk_i ),
800: .rst_ni (rst_ni ),
801:
802: .we (1'b0),
803: .wd ('0 ),
804:
805: // from internal hardware
806: .de (hw2reg.ip[3].de),
807: .d (hw2reg.ip[3].d ),
808:
809: // to internal hardware
810: .qe (),
811: .q (),
812:
813: // to register interface (read)
814: .qs (ip0_p3_qs)
815: );
816:
817:
818: // F[p4]: 4:4
819: prim_subreg #(
820: .DW (1),
821: .SWACCESS("RO"),
822: .RESVAL (1'h0)
823: ) u_ip0_p4 (
824: .clk_i (clk_i ),
825: .rst_ni (rst_ni ),
826:
827: .we (1'b0),
828: .wd ('0 ),
829:
830: // from internal hardware
831: .de (hw2reg.ip[4].de),
832: .d (hw2reg.ip[4].d ),
833:
834: // to internal hardware
835: .qe (),
836: .q (),
837:
838: // to register interface (read)
839: .qs (ip0_p4_qs)
840: );
841:
842:
843: // F[p5]: 5:5
844: prim_subreg #(
845: .DW (1),
846: .SWACCESS("RO"),
847: .RESVAL (1'h0)
848: ) u_ip0_p5 (
849: .clk_i (clk_i ),
850: .rst_ni (rst_ni ),
851:
852: .we (1'b0),
853: .wd ('0 ),
854:
855: // from internal hardware
856: .de (hw2reg.ip[5].de),
857: .d (hw2reg.ip[5].d ),
858:
859: // to internal hardware
860: .qe (),
861: .q (),
862:
863: // to register interface (read)
864: .qs (ip0_p5_qs)
865: );
866:
867:
868: // F[p6]: 6:6
869: prim_subreg #(
870: .DW (1),
871: .SWACCESS("RO"),
872: .RESVAL (1'h0)
873: ) u_ip0_p6 (
874: .clk_i (clk_i ),
875: .rst_ni (rst_ni ),
876:
877: .we (1'b0),
878: .wd ('0 ),
879:
880: // from internal hardware
881: .de (hw2reg.ip[6].de),
882: .d (hw2reg.ip[6].d ),
883:
884: // to internal hardware
885: .qe (),
886: .q (),
887:
888: // to register interface (read)
889: .qs (ip0_p6_qs)
890: );
891:
892:
893: // F[p7]: 7:7
894: prim_subreg #(
895: .DW (1),
896: .SWACCESS("RO"),
897: .RESVAL (1'h0)
898: ) u_ip0_p7 (
899: .clk_i (clk_i ),
900: .rst_ni (rst_ni ),
901:
902: .we (1'b0),
903: .wd ('0 ),
904:
905: // from internal hardware
906: .de (hw2reg.ip[7].de),
907: .d (hw2reg.ip[7].d ),
908:
909: // to internal hardware
910: .qe (),
911: .q (),
912:
913: // to register interface (read)
914: .qs (ip0_p7_qs)
915: );
916:
917:
918: // F[p8]: 8:8
919: prim_subreg #(
920: .DW (1),
921: .SWACCESS("RO"),
922: .RESVAL (1'h0)
923: ) u_ip0_p8 (
924: .clk_i (clk_i ),
925: .rst_ni (rst_ni ),
926:
927: .we (1'b0),
928: .wd ('0 ),
929:
930: // from internal hardware
931: .de (hw2reg.ip[8].de),
932: .d (hw2reg.ip[8].d ),
933:
934: // to internal hardware
935: .qe (),
936: .q (),
937:
938: // to register interface (read)
939: .qs (ip0_p8_qs)
940: );
941:
942:
943: // F[p9]: 9:9
944: prim_subreg #(
945: .DW (1),
946: .SWACCESS("RO"),
947: .RESVAL (1'h0)
948: ) u_ip0_p9 (
949: .clk_i (clk_i ),
950: .rst_ni (rst_ni ),
951:
952: .we (1'b0),
953: .wd ('0 ),
954:
955: // from internal hardware
956: .de (hw2reg.ip[9].de),
957: .d (hw2reg.ip[9].d ),
958:
959: // to internal hardware
960: .qe (),
961: .q (),
962:
963: // to register interface (read)
964: .qs (ip0_p9_qs)
965: );
966:
967:
968: // F[p10]: 10:10
969: prim_subreg #(
970: .DW (1),
971: .SWACCESS("RO"),
972: .RESVAL (1'h0)
973: ) u_ip0_p10 (
974: .clk_i (clk_i ),
975: .rst_ni (rst_ni ),
976:
977: .we (1'b0),
978: .wd ('0 ),
979:
980: // from internal hardware
981: .de (hw2reg.ip[10].de),
982: .d (hw2reg.ip[10].d ),
983:
984: // to internal hardware
985: .qe (),
986: .q (),
987:
988: // to register interface (read)
989: .qs (ip0_p10_qs)
990: );
991:
992:
993: // F[p11]: 11:11
994: prim_subreg #(
995: .DW (1),
996: .SWACCESS("RO"),
997: .RESVAL (1'h0)
998: ) u_ip0_p11 (
999: .clk_i (clk_i ),
1000: .rst_ni (rst_ni ),
1001:
1002: .we (1'b0),
1003: .wd ('0 ),
1004:
1005: // from internal hardware
1006: .de (hw2reg.ip[11].de),
1007: .d (hw2reg.ip[11].d ),
1008:
1009: // to internal hardware
1010: .qe (),
1011: .q (),
1012:
1013: // to register interface (read)
1014: .qs (ip0_p11_qs)
1015: );
1016:
1017:
1018: // F[p12]: 12:12
1019: prim_subreg #(
1020: .DW (1),
1021: .SWACCESS("RO"),
1022: .RESVAL (1'h0)
1023: ) u_ip0_p12 (
1024: .clk_i (clk_i ),
1025: .rst_ni (rst_ni ),
1026:
1027: .we (1'b0),
1028: .wd ('0 ),
1029:
1030: // from internal hardware
1031: .de (hw2reg.ip[12].de),
1032: .d (hw2reg.ip[12].d ),
1033:
1034: // to internal hardware
1035: .qe (),
1036: .q (),
1037:
1038: // to register interface (read)
1039: .qs (ip0_p12_qs)
1040: );
1041:
1042:
1043: // F[p13]: 13:13
1044: prim_subreg #(
1045: .DW (1),
1046: .SWACCESS("RO"),
1047: .RESVAL (1'h0)
1048: ) u_ip0_p13 (
1049: .clk_i (clk_i ),
1050: .rst_ni (rst_ni ),
1051:
1052: .we (1'b0),
1053: .wd ('0 ),
1054:
1055: // from internal hardware
1056: .de (hw2reg.ip[13].de),
1057: .d (hw2reg.ip[13].d ),
1058:
1059: // to internal hardware
1060: .qe (),
1061: .q (),
1062:
1063: // to register interface (read)
1064: .qs (ip0_p13_qs)
1065: );
1066:
1067:
1068: // F[p14]: 14:14
1069: prim_subreg #(
1070: .DW (1),
1071: .SWACCESS("RO"),
1072: .RESVAL (1'h0)
1073: ) u_ip0_p14 (
1074: .clk_i (clk_i ),
1075: .rst_ni (rst_ni ),
1076:
1077: .we (1'b0),
1078: .wd ('0 ),
1079:
1080: // from internal hardware
1081: .de (hw2reg.ip[14].de),
1082: .d (hw2reg.ip[14].d ),
1083:
1084: // to internal hardware
1085: .qe (),
1086: .q (),
1087:
1088: // to register interface (read)
1089: .qs (ip0_p14_qs)
1090: );
1091:
1092:
1093: // F[p15]: 15:15
1094: prim_subreg #(
1095: .DW (1),
1096: .SWACCESS("RO"),
1097: .RESVAL (1'h0)
1098: ) u_ip0_p15 (
1099: .clk_i (clk_i ),
1100: .rst_ni (rst_ni ),
1101:
1102: .we (1'b0),
1103: .wd ('0 ),
1104:
1105: // from internal hardware
1106: .de (hw2reg.ip[15].de),
1107: .d (hw2reg.ip[15].d ),
1108:
1109: // to internal hardware
1110: .qe (),
1111: .q (),
1112:
1113: // to register interface (read)
1114: .qs (ip0_p15_qs)
1115: );
1116:
1117:
1118: // F[p16]: 16:16
1119: prim_subreg #(
1120: .DW (1),
1121: .SWACCESS("RO"),
1122: .RESVAL (1'h0)
1123: ) u_ip0_p16 (
1124: .clk_i (clk_i ),
1125: .rst_ni (rst_ni ),
1126:
1127: .we (1'b0),
1128: .wd ('0 ),
1129:
1130: // from internal hardware
1131: .de (hw2reg.ip[16].de),
1132: .d (hw2reg.ip[16].d ),
1133:
1134: // to internal hardware
1135: .qe (),
1136: .q (),
1137:
1138: // to register interface (read)
1139: .qs (ip0_p16_qs)
1140: );
1141:
1142:
1143: // F[p17]: 17:17
1144: prim_subreg #(
1145: .DW (1),
1146: .SWACCESS("RO"),
1147: .RESVAL (1'h0)
1148: ) u_ip0_p17 (
1149: .clk_i (clk_i ),
1150: .rst_ni (rst_ni ),
1151:
1152: .we (1'b0),
1153: .wd ('0 ),
1154:
1155: // from internal hardware
1156: .de (hw2reg.ip[17].de),
1157: .d (hw2reg.ip[17].d ),
1158:
1159: // to internal hardware
1160: .qe (),
1161: .q (),
1162:
1163: // to register interface (read)
1164: .qs (ip0_p17_qs)
1165: );
1166:
1167:
1168: // F[p18]: 18:18
1169: prim_subreg #(
1170: .DW (1),
1171: .SWACCESS("RO"),
1172: .RESVAL (1'h0)
1173: ) u_ip0_p18 (
1174: .clk_i (clk_i ),
1175: .rst_ni (rst_ni ),
1176:
1177: .we (1'b0),
1178: .wd ('0 ),
1179:
1180: // from internal hardware
1181: .de (hw2reg.ip[18].de),
1182: .d (hw2reg.ip[18].d ),
1183:
1184: // to internal hardware
1185: .qe (),
1186: .q (),
1187:
1188: // to register interface (read)
1189: .qs (ip0_p18_qs)
1190: );
1191:
1192:
1193: // F[p19]: 19:19
1194: prim_subreg #(
1195: .DW (1),
1196: .SWACCESS("RO"),
1197: .RESVAL (1'h0)
1198: ) u_ip0_p19 (
1199: .clk_i (clk_i ),
1200: .rst_ni (rst_ni ),
1201:
1202: .we (1'b0),
1203: .wd ('0 ),
1204:
1205: // from internal hardware
1206: .de (hw2reg.ip[19].de),
1207: .d (hw2reg.ip[19].d ),
1208:
1209: // to internal hardware
1210: .qe (),
1211: .q (),
1212:
1213: // to register interface (read)
1214: .qs (ip0_p19_qs)
1215: );
1216:
1217:
1218: // F[p20]: 20:20
1219: prim_subreg #(
1220: .DW (1),
1221: .SWACCESS("RO"),
1222: .RESVAL (1'h0)
1223: ) u_ip0_p20 (
1224: .clk_i (clk_i ),
1225: .rst_ni (rst_ni ),
1226:
1227: .we (1'b0),
1228: .wd ('0 ),
1229:
1230: // from internal hardware
1231: .de (hw2reg.ip[20].de),
1232: .d (hw2reg.ip[20].d ),
1233:
1234: // to internal hardware
1235: .qe (),
1236: .q (),
1237:
1238: // to register interface (read)
1239: .qs (ip0_p20_qs)
1240: );
1241:
1242:
1243: // F[p21]: 21:21
1244: prim_subreg #(
1245: .DW (1),
1246: .SWACCESS("RO"),
1247: .RESVAL (1'h0)
1248: ) u_ip0_p21 (
1249: .clk_i (clk_i ),
1250: .rst_ni (rst_ni ),
1251:
1252: .we (1'b0),
1253: .wd ('0 ),
1254:
1255: // from internal hardware
1256: .de (hw2reg.ip[21].de),
1257: .d (hw2reg.ip[21].d ),
1258:
1259: // to internal hardware
1260: .qe (),
1261: .q (),
1262:
1263: // to register interface (read)
1264: .qs (ip0_p21_qs)
1265: );
1266:
1267:
1268: // F[p22]: 22:22
1269: prim_subreg #(
1270: .DW (1),
1271: .SWACCESS("RO"),
1272: .RESVAL (1'h0)
1273: ) u_ip0_p22 (
1274: .clk_i (clk_i ),
1275: .rst_ni (rst_ni ),
1276:
1277: .we (1'b0),
1278: .wd ('0 ),
1279:
1280: // from internal hardware
1281: .de (hw2reg.ip[22].de),
1282: .d (hw2reg.ip[22].d ),
1283:
1284: // to internal hardware
1285: .qe (),
1286: .q (),
1287:
1288: // to register interface (read)
1289: .qs (ip0_p22_qs)
1290: );
1291:
1292:
1293: // F[p23]: 23:23
1294: prim_subreg #(
1295: .DW (1),
1296: .SWACCESS("RO"),
1297: .RESVAL (1'h0)
1298: ) u_ip0_p23 (
1299: .clk_i (clk_i ),
1300: .rst_ni (rst_ni ),
1301:
1302: .we (1'b0),
1303: .wd ('0 ),
1304:
1305: // from internal hardware
1306: .de (hw2reg.ip[23].de),
1307: .d (hw2reg.ip[23].d ),
1308:
1309: // to internal hardware
1310: .qe (),
1311: .q (),
1312:
1313: // to register interface (read)
1314: .qs (ip0_p23_qs)
1315: );
1316:
1317:
1318: // F[p24]: 24:24
1319: prim_subreg #(
1320: .DW (1),
1321: .SWACCESS("RO"),
1322: .RESVAL (1'h0)
1323: ) u_ip0_p24 (
1324: .clk_i (clk_i ),
1325: .rst_ni (rst_ni ),
1326:
1327: .we (1'b0),
1328: .wd ('0 ),
1329:
1330: // from internal hardware
1331: .de (hw2reg.ip[24].de),
1332: .d (hw2reg.ip[24].d ),
1333:
1334: // to internal hardware
1335: .qe (),
1336: .q (),
1337:
1338: // to register interface (read)
1339: .qs (ip0_p24_qs)
1340: );
1341:
1342:
1343: // F[p25]: 25:25
1344: prim_subreg #(
1345: .DW (1),
1346: .SWACCESS("RO"),
1347: .RESVAL (1'h0)
1348: ) u_ip0_p25 (
1349: .clk_i (clk_i ),
1350: .rst_ni (rst_ni ),
1351:
1352: .we (1'b0),
1353: .wd ('0 ),
1354:
1355: // from internal hardware
1356: .de (hw2reg.ip[25].de),
1357: .d (hw2reg.ip[25].d ),
1358:
1359: // to internal hardware
1360: .qe (),
1361: .q (),
1362:
1363: // to register interface (read)
1364: .qs (ip0_p25_qs)
1365: );
1366:
1367:
1368: // F[p26]: 26:26
1369: prim_subreg #(
1370: .DW (1),
1371: .SWACCESS("RO"),
1372: .RESVAL (1'h0)
1373: ) u_ip0_p26 (
1374: .clk_i (clk_i ),
1375: .rst_ni (rst_ni ),
1376:
1377: .we (1'b0),
1378: .wd ('0 ),
1379:
1380: // from internal hardware
1381: .de (hw2reg.ip[26].de),
1382: .d (hw2reg.ip[26].d ),
1383:
1384: // to internal hardware
1385: .qe (),
1386: .q (),
1387:
1388: // to register interface (read)
1389: .qs (ip0_p26_qs)
1390: );
1391:
1392:
1393: // F[p27]: 27:27
1394: prim_subreg #(
1395: .DW (1),
1396: .SWACCESS("RO"),
1397: .RESVAL (1'h0)
1398: ) u_ip0_p27 (
1399: .clk_i (clk_i ),
1400: .rst_ni (rst_ni ),
1401:
1402: .we (1'b0),
1403: .wd ('0 ),
1404:
1405: // from internal hardware
1406: .de (hw2reg.ip[27].de),
1407: .d (hw2reg.ip[27].d ),
1408:
1409: // to internal hardware
1410: .qe (),
1411: .q (),
1412:
1413: // to register interface (read)
1414: .qs (ip0_p27_qs)
1415: );
1416:
1417:
1418: // F[p28]: 28:28
1419: prim_subreg #(
1420: .DW (1),
1421: .SWACCESS("RO"),
1422: .RESVAL (1'h0)
1423: ) u_ip0_p28 (
1424: .clk_i (clk_i ),
1425: .rst_ni (rst_ni ),
1426:
1427: .we (1'b0),
1428: .wd ('0 ),
1429:
1430: // from internal hardware
1431: .de (hw2reg.ip[28].de),
1432: .d (hw2reg.ip[28].d ),
1433:
1434: // to internal hardware
1435: .qe (),
1436: .q (),
1437:
1438: // to register interface (read)
1439: .qs (ip0_p28_qs)
1440: );
1441:
1442:
1443: // F[p29]: 29:29
1444: prim_subreg #(
1445: .DW (1),
1446: .SWACCESS("RO"),
1447: .RESVAL (1'h0)
1448: ) u_ip0_p29 (
1449: .clk_i (clk_i ),
1450: .rst_ni (rst_ni ),
1451:
1452: .we (1'b0),
1453: .wd ('0 ),
1454:
1455: // from internal hardware
1456: .de (hw2reg.ip[29].de),
1457: .d (hw2reg.ip[29].d ),
1458:
1459: // to internal hardware
1460: .qe (),
1461: .q (),
1462:
1463: // to register interface (read)
1464: .qs (ip0_p29_qs)
1465: );
1466:
1467:
1468: // F[p30]: 30:30
1469: prim_subreg #(
1470: .DW (1),
1471: .SWACCESS("RO"),
1472: .RESVAL (1'h0)
1473: ) u_ip0_p30 (
1474: .clk_i (clk_i ),
1475: .rst_ni (rst_ni ),
1476:
1477: .we (1'b0),
1478: .wd ('0 ),
1479:
1480: // from internal hardware
1481: .de (hw2reg.ip[30].de),
1482: .d (hw2reg.ip[30].d ),
1483:
1484: // to internal hardware
1485: .qe (),
1486: .q (),
1487:
1488: // to register interface (read)
1489: .qs (ip0_p30_qs)
1490: );
1491:
1492:
1493: // F[p31]: 31:31
1494: prim_subreg #(
1495: .DW (1),
1496: .SWACCESS("RO"),
1497: .RESVAL (1'h0)
1498: ) u_ip0_p31 (
1499: .clk_i (clk_i ),
1500: .rst_ni (rst_ni ),
1501:
1502: .we (1'b0),
1503: .wd ('0 ),
1504:
1505: // from internal hardware
1506: .de (hw2reg.ip[31].de),
1507: .d (hw2reg.ip[31].d ),
1508:
1509: // to internal hardware
1510: .qe (),
1511: .q (),
1512:
1513: // to register interface (read)
1514: .qs (ip0_p31_qs)
1515: );
1516:
1517:
1518: // Subregister 32 of Multireg ip
1519: // R[ip1]: V(False)
1520:
1521: // F[p32]: 0:0
1522: prim_subreg #(
1523: .DW (1),
1524: .SWACCESS("RO"),
1525: .RESVAL (1'h0)
1526: ) u_ip1_p32 (
1527: .clk_i (clk_i ),
1528: .rst_ni (rst_ni ),
1529:
1530: .we (1'b0),
1531: .wd ('0 ),
1532:
1533: // from internal hardware
1534: .de (hw2reg.ip[32].de),
1535: .d (hw2reg.ip[32].d ),
1536:
1537: // to internal hardware
1538: .qe (),
1539: .q (),
1540:
1541: // to register interface (read)
1542: .qs (ip1_p32_qs)
1543: );
1544:
1545:
1546: // F[p33]: 1:1
1547: prim_subreg #(
1548: .DW (1),
1549: .SWACCESS("RO"),
1550: .RESVAL (1'h0)
1551: ) u_ip1_p33 (
1552: .clk_i (clk_i ),
1553: .rst_ni (rst_ni ),
1554:
1555: .we (1'b0),
1556: .wd ('0 ),
1557:
1558: // from internal hardware
1559: .de (hw2reg.ip[33].de),
1560: .d (hw2reg.ip[33].d ),
1561:
1562: // to internal hardware
1563: .qe (),
1564: .q (),
1565:
1566: // to register interface (read)
1567: .qs (ip1_p33_qs)
1568: );
1569:
1570:
1571: // F[p34]: 2:2
1572: prim_subreg #(
1573: .DW (1),
1574: .SWACCESS("RO"),
1575: .RESVAL (1'h0)
1576: ) u_ip1_p34 (
1577: .clk_i (clk_i ),
1578: .rst_ni (rst_ni ),
1579:
1580: .we (1'b0),
1581: .wd ('0 ),
1582:
1583: // from internal hardware
1584: .de (hw2reg.ip[34].de),
1585: .d (hw2reg.ip[34].d ),
1586:
1587: // to internal hardware
1588: .qe (),
1589: .q (),
1590:
1591: // to register interface (read)
1592: .qs (ip1_p34_qs)
1593: );
1594:
1595:
1596: // F[p35]: 3:3
1597: prim_subreg #(
1598: .DW (1),
1599: .SWACCESS("RO"),
1600: .RESVAL (1'h0)
1601: ) u_ip1_p35 (
1602: .clk_i (clk_i ),
1603: .rst_ni (rst_ni ),
1604:
1605: .we (1'b0),
1606: .wd ('0 ),
1607:
1608: // from internal hardware
1609: .de (hw2reg.ip[35].de),
1610: .d (hw2reg.ip[35].d ),
1611:
1612: // to internal hardware
1613: .qe (),
1614: .q (),
1615:
1616: // to register interface (read)
1617: .qs (ip1_p35_qs)
1618: );
1619:
1620:
1621: // F[p36]: 4:4
1622: prim_subreg #(
1623: .DW (1),
1624: .SWACCESS("RO"),
1625: .RESVAL (1'h0)
1626: ) u_ip1_p36 (
1627: .clk_i (clk_i ),
1628: .rst_ni (rst_ni ),
1629:
1630: .we (1'b0),
1631: .wd ('0 ),
1632:
1633: // from internal hardware
1634: .de (hw2reg.ip[36].de),
1635: .d (hw2reg.ip[36].d ),
1636:
1637: // to internal hardware
1638: .qe (),
1639: .q (),
1640:
1641: // to register interface (read)
1642: .qs (ip1_p36_qs)
1643: );
1644:
1645:
1646: // F[p37]: 5:5
1647: prim_subreg #(
1648: .DW (1),
1649: .SWACCESS("RO"),
1650: .RESVAL (1'h0)
1651: ) u_ip1_p37 (
1652: .clk_i (clk_i ),
1653: .rst_ni (rst_ni ),
1654:
1655: .we (1'b0),
1656: .wd ('0 ),
1657:
1658: // from internal hardware
1659: .de (hw2reg.ip[37].de),
1660: .d (hw2reg.ip[37].d ),
1661:
1662: // to internal hardware
1663: .qe (),
1664: .q (),
1665:
1666: // to register interface (read)
1667: .qs (ip1_p37_qs)
1668: );
1669:
1670:
1671: // F[p38]: 6:6
1672: prim_subreg #(
1673: .DW (1),
1674: .SWACCESS("RO"),
1675: .RESVAL (1'h0)
1676: ) u_ip1_p38 (
1677: .clk_i (clk_i ),
1678: .rst_ni (rst_ni ),
1679:
1680: .we (1'b0),
1681: .wd ('0 ),
1682:
1683: // from internal hardware
1684: .de (hw2reg.ip[38].de),
1685: .d (hw2reg.ip[38].d ),
1686:
1687: // to internal hardware
1688: .qe (),
1689: .q (),
1690:
1691: // to register interface (read)
1692: .qs (ip1_p38_qs)
1693: );
1694:
1695:
1696: // F[p39]: 7:7
1697: prim_subreg #(
1698: .DW (1),
1699: .SWACCESS("RO"),
1700: .RESVAL (1'h0)
1701: ) u_ip1_p39 (
1702: .clk_i (clk_i ),
1703: .rst_ni (rst_ni ),
1704:
1705: .we (1'b0),
1706: .wd ('0 ),
1707:
1708: // from internal hardware
1709: .de (hw2reg.ip[39].de),
1710: .d (hw2reg.ip[39].d ),
1711:
1712: // to internal hardware
1713: .qe (),
1714: .q (),
1715:
1716: // to register interface (read)
1717: .qs (ip1_p39_qs)
1718: );
1719:
1720:
1721: // F[p40]: 8:8
1722: prim_subreg #(
1723: .DW (1),
1724: .SWACCESS("RO"),
1725: .RESVAL (1'h0)
1726: ) u_ip1_p40 (
1727: .clk_i (clk_i ),
1728: .rst_ni (rst_ni ),
1729:
1730: .we (1'b0),
1731: .wd ('0 ),
1732:
1733: // from internal hardware
1734: .de (hw2reg.ip[40].de),
1735: .d (hw2reg.ip[40].d ),
1736:
1737: // to internal hardware
1738: .qe (),
1739: .q (),
1740:
1741: // to register interface (read)
1742: .qs (ip1_p40_qs)
1743: );
1744:
1745:
1746: // F[p41]: 9:9
1747: prim_subreg #(
1748: .DW (1),
1749: .SWACCESS("RO"),
1750: .RESVAL (1'h0)
1751: ) u_ip1_p41 (
1752: .clk_i (clk_i ),
1753: .rst_ni (rst_ni ),
1754:
1755: .we (1'b0),
1756: .wd ('0 ),
1757:
1758: // from internal hardware
1759: .de (hw2reg.ip[41].de),
1760: .d (hw2reg.ip[41].d ),
1761:
1762: // to internal hardware
1763: .qe (),
1764: .q (),
1765:
1766: // to register interface (read)
1767: .qs (ip1_p41_qs)
1768: );
1769:
1770:
1771: // F[p42]: 10:10
1772: prim_subreg #(
1773: .DW (1),
1774: .SWACCESS("RO"),
1775: .RESVAL (1'h0)
1776: ) u_ip1_p42 (
1777: .clk_i (clk_i ),
1778: .rst_ni (rst_ni ),
1779:
1780: .we (1'b0),
1781: .wd ('0 ),
1782:
1783: // from internal hardware
1784: .de (hw2reg.ip[42].de),
1785: .d (hw2reg.ip[42].d ),
1786:
1787: // to internal hardware
1788: .qe (),
1789: .q (),
1790:
1791: // to register interface (read)
1792: .qs (ip1_p42_qs)
1793: );
1794:
1795:
1796: // F[p43]: 11:11
1797: prim_subreg #(
1798: .DW (1),
1799: .SWACCESS("RO"),
1800: .RESVAL (1'h0)
1801: ) u_ip1_p43 (
1802: .clk_i (clk_i ),
1803: .rst_ni (rst_ni ),
1804:
1805: .we (1'b0),
1806: .wd ('0 ),
1807:
1808: // from internal hardware
1809: .de (hw2reg.ip[43].de),
1810: .d (hw2reg.ip[43].d ),
1811:
1812: // to internal hardware
1813: .qe (),
1814: .q (),
1815:
1816: // to register interface (read)
1817: .qs (ip1_p43_qs)
1818: );
1819:
1820:
1821: // F[p44]: 12:12
1822: prim_subreg #(
1823: .DW (1),
1824: .SWACCESS("RO"),
1825: .RESVAL (1'h0)
1826: ) u_ip1_p44 (
1827: .clk_i (clk_i ),
1828: .rst_ni (rst_ni ),
1829:
1830: .we (1'b0),
1831: .wd ('0 ),
1832:
1833: // from internal hardware
1834: .de (hw2reg.ip[44].de),
1835: .d (hw2reg.ip[44].d ),
1836:
1837: // to internal hardware
1838: .qe (),
1839: .q (),
1840:
1841: // to register interface (read)
1842: .qs (ip1_p44_qs)
1843: );
1844:
1845:
1846: // F[p45]: 13:13
1847: prim_subreg #(
1848: .DW (1),
1849: .SWACCESS("RO"),
1850: .RESVAL (1'h0)
1851: ) u_ip1_p45 (
1852: .clk_i (clk_i ),
1853: .rst_ni (rst_ni ),
1854:
1855: .we (1'b0),
1856: .wd ('0 ),
1857:
1858: // from internal hardware
1859: .de (hw2reg.ip[45].de),
1860: .d (hw2reg.ip[45].d ),
1861:
1862: // to internal hardware
1863: .qe (),
1864: .q (),
1865:
1866: // to register interface (read)
1867: .qs (ip1_p45_qs)
1868: );
1869:
1870:
1871: // F[p46]: 14:14
1872: prim_subreg #(
1873: .DW (1),
1874: .SWACCESS("RO"),
1875: .RESVAL (1'h0)
1876: ) u_ip1_p46 (
1877: .clk_i (clk_i ),
1878: .rst_ni (rst_ni ),
1879:
1880: .we (1'b0),
1881: .wd ('0 ),
1882:
1883: // from internal hardware
1884: .de (hw2reg.ip[46].de),
1885: .d (hw2reg.ip[46].d ),
1886:
1887: // to internal hardware
1888: .qe (),
1889: .q (),
1890:
1891: // to register interface (read)
1892: .qs (ip1_p46_qs)
1893: );
1894:
1895:
1896: // F[p47]: 15:15
1897: prim_subreg #(
1898: .DW (1),
1899: .SWACCESS("RO"),
1900: .RESVAL (1'h0)
1901: ) u_ip1_p47 (
1902: .clk_i (clk_i ),
1903: .rst_ni (rst_ni ),
1904:
1905: .we (1'b0),
1906: .wd ('0 ),
1907:
1908: // from internal hardware
1909: .de (hw2reg.ip[47].de),
1910: .d (hw2reg.ip[47].d ),
1911:
1912: // to internal hardware
1913: .qe (),
1914: .q (),
1915:
1916: // to register interface (read)
1917: .qs (ip1_p47_qs)
1918: );
1919:
1920:
1921: // F[p48]: 16:16
1922: prim_subreg #(
1923: .DW (1),
1924: .SWACCESS("RO"),
1925: .RESVAL (1'h0)
1926: ) u_ip1_p48 (
1927: .clk_i (clk_i ),
1928: .rst_ni (rst_ni ),
1929:
1930: .we (1'b0),
1931: .wd ('0 ),
1932:
1933: // from internal hardware
1934: .de (hw2reg.ip[48].de),
1935: .d (hw2reg.ip[48].d ),
1936:
1937: // to internal hardware
1938: .qe (),
1939: .q (),
1940:
1941: // to register interface (read)
1942: .qs (ip1_p48_qs)
1943: );
1944:
1945:
1946: // F[p49]: 17:17
1947: prim_subreg #(
1948: .DW (1),
1949: .SWACCESS("RO"),
1950: .RESVAL (1'h0)
1951: ) u_ip1_p49 (
1952: .clk_i (clk_i ),
1953: .rst_ni (rst_ni ),
1954:
1955: .we (1'b0),
1956: .wd ('0 ),
1957:
1958: // from internal hardware
1959: .de (hw2reg.ip[49].de),
1960: .d (hw2reg.ip[49].d ),
1961:
1962: // to internal hardware
1963: .qe (),
1964: .q (),
1965:
1966: // to register interface (read)
1967: .qs (ip1_p49_qs)
1968: );
1969:
1970:
1971: // F[p50]: 18:18
1972: prim_subreg #(
1973: .DW (1),
1974: .SWACCESS("RO"),
1975: .RESVAL (1'h0)
1976: ) u_ip1_p50 (
1977: .clk_i (clk_i ),
1978: .rst_ni (rst_ni ),
1979:
1980: .we (1'b0),
1981: .wd ('0 ),
1982:
1983: // from internal hardware
1984: .de (hw2reg.ip[50].de),
1985: .d (hw2reg.ip[50].d ),
1986:
1987: // to internal hardware
1988: .qe (),
1989: .q (),
1990:
1991: // to register interface (read)
1992: .qs (ip1_p50_qs)
1993: );
1994:
1995:
1996: // F[p51]: 19:19
1997: prim_subreg #(
1998: .DW (1),
1999: .SWACCESS("RO"),
2000: .RESVAL (1'h0)
2001: ) u_ip1_p51 (
2002: .clk_i (clk_i ),
2003: .rst_ni (rst_ni ),
2004:
2005: .we (1'b0),
2006: .wd ('0 ),
2007:
2008: // from internal hardware
2009: .de (hw2reg.ip[51].de),
2010: .d (hw2reg.ip[51].d ),
2011:
2012: // to internal hardware
2013: .qe (),
2014: .q (),
2015:
2016: // to register interface (read)
2017: .qs (ip1_p51_qs)
2018: );
2019:
2020:
2021: // F[p52]: 20:20
2022: prim_subreg #(
2023: .DW (1),
2024: .SWACCESS("RO"),
2025: .RESVAL (1'h0)
2026: ) u_ip1_p52 (
2027: .clk_i (clk_i ),
2028: .rst_ni (rst_ni ),
2029:
2030: .we (1'b0),
2031: .wd ('0 ),
2032:
2033: // from internal hardware
2034: .de (hw2reg.ip[52].de),
2035: .d (hw2reg.ip[52].d ),
2036:
2037: // to internal hardware
2038: .qe (),
2039: .q (),
2040:
2041: // to register interface (read)
2042: .qs (ip1_p52_qs)
2043: );
2044:
2045:
2046: // F[p53]: 21:21
2047: prim_subreg #(
2048: .DW (1),
2049: .SWACCESS("RO"),
2050: .RESVAL (1'h0)
2051: ) u_ip1_p53 (
2052: .clk_i (clk_i ),
2053: .rst_ni (rst_ni ),
2054:
2055: .we (1'b0),
2056: .wd ('0 ),
2057:
2058: // from internal hardware
2059: .de (hw2reg.ip[53].de),
2060: .d (hw2reg.ip[53].d ),
2061:
2062: // to internal hardware
2063: .qe (),
2064: .q (),
2065:
2066: // to register interface (read)
2067: .qs (ip1_p53_qs)
2068: );
2069:
2070:
2071: // F[p54]: 22:22
2072: prim_subreg #(
2073: .DW (1),
2074: .SWACCESS("RO"),
2075: .RESVAL (1'h0)
2076: ) u_ip1_p54 (
2077: .clk_i (clk_i ),
2078: .rst_ni (rst_ni ),
2079:
2080: .we (1'b0),
2081: .wd ('0 ),
2082:
2083: // from internal hardware
2084: .de (hw2reg.ip[54].de),
2085: .d (hw2reg.ip[54].d ),
2086:
2087: // to internal hardware
2088: .qe (),
2089: .q (),
2090:
2091: // to register interface (read)
2092: .qs (ip1_p54_qs)
2093: );
2094:
2095:
2096: // F[p55]: 23:23
2097: prim_subreg #(
2098: .DW (1),
2099: .SWACCESS("RO"),
2100: .RESVAL (1'h0)
2101: ) u_ip1_p55 (
2102: .clk_i (clk_i ),
2103: .rst_ni (rst_ni ),
2104:
2105: .we (1'b0),
2106: .wd ('0 ),
2107:
2108: // from internal hardware
2109: .de (hw2reg.ip[55].de),
2110: .d (hw2reg.ip[55].d ),
2111:
2112: // to internal hardware
2113: .qe (),
2114: .q (),
2115:
2116: // to register interface (read)
2117: .qs (ip1_p55_qs)
2118: );
2119:
2120:
2121: // F[p56]: 24:24
2122: prim_subreg #(
2123: .DW (1),
2124: .SWACCESS("RO"),
2125: .RESVAL (1'h0)
2126: ) u_ip1_p56 (
2127: .clk_i (clk_i ),
2128: .rst_ni (rst_ni ),
2129:
2130: .we (1'b0),
2131: .wd ('0 ),
2132:
2133: // from internal hardware
2134: .de (hw2reg.ip[56].de),
2135: .d (hw2reg.ip[56].d ),
2136:
2137: // to internal hardware
2138: .qe (),
2139: .q (),
2140:
2141: // to register interface (read)
2142: .qs (ip1_p56_qs)
2143: );
2144:
2145:
2146: // F[p57]: 25:25
2147: prim_subreg #(
2148: .DW (1),
2149: .SWACCESS("RO"),
2150: .RESVAL (1'h0)
2151: ) u_ip1_p57 (
2152: .clk_i (clk_i ),
2153: .rst_ni (rst_ni ),
2154:
2155: .we (1'b0),
2156: .wd ('0 ),
2157:
2158: // from internal hardware
2159: .de (hw2reg.ip[57].de),
2160: .d (hw2reg.ip[57].d ),
2161:
2162: // to internal hardware
2163: .qe (),
2164: .q (),
2165:
2166: // to register interface (read)
2167: .qs (ip1_p57_qs)
2168: );
2169:
2170:
2171: // F[p58]: 26:26
2172: prim_subreg #(
2173: .DW (1),
2174: .SWACCESS("RO"),
2175: .RESVAL (1'h0)
2176: ) u_ip1_p58 (
2177: .clk_i (clk_i ),
2178: .rst_ni (rst_ni ),
2179:
2180: .we (1'b0),
2181: .wd ('0 ),
2182:
2183: // from internal hardware
2184: .de (hw2reg.ip[58].de),
2185: .d (hw2reg.ip[58].d ),
2186:
2187: // to internal hardware
2188: .qe (),
2189: .q (),
2190:
2191: // to register interface (read)
2192: .qs (ip1_p58_qs)
2193: );
2194:
2195:
2196: // F[p59]: 27:27
2197: prim_subreg #(
2198: .DW (1),
2199: .SWACCESS("RO"),
2200: .RESVAL (1'h0)
2201: ) u_ip1_p59 (
2202: .clk_i (clk_i ),
2203: .rst_ni (rst_ni ),
2204:
2205: .we (1'b0),
2206: .wd ('0 ),
2207:
2208: // from internal hardware
2209: .de (hw2reg.ip[59].de),
2210: .d (hw2reg.ip[59].d ),
2211:
2212: // to internal hardware
2213: .qe (),
2214: .q (),
2215:
2216: // to register interface (read)
2217: .qs (ip1_p59_qs)
2218: );
2219:
2220:
2221: // F[p60]: 28:28
2222: prim_subreg #(
2223: .DW (1),
2224: .SWACCESS("RO"),
2225: .RESVAL (1'h0)
2226: ) u_ip1_p60 (
2227: .clk_i (clk_i ),
2228: .rst_ni (rst_ni ),
2229:
2230: .we (1'b0),
2231: .wd ('0 ),
2232:
2233: // from internal hardware
2234: .de (hw2reg.ip[60].de),
2235: .d (hw2reg.ip[60].d ),
2236:
2237: // to internal hardware
2238: .qe (),
2239: .q (),
2240:
2241: // to register interface (read)
2242: .qs (ip1_p60_qs)
2243: );
2244:
2245:
2246: // F[p61]: 29:29
2247: prim_subreg #(
2248: .DW (1),
2249: .SWACCESS("RO"),
2250: .RESVAL (1'h0)
2251: ) u_ip1_p61 (
2252: .clk_i (clk_i ),
2253: .rst_ni (rst_ni ),
2254:
2255: .we (1'b0),
2256: .wd ('0 ),
2257:
2258: // from internal hardware
2259: .de (hw2reg.ip[61].de),
2260: .d (hw2reg.ip[61].d ),
2261:
2262: // to internal hardware
2263: .qe (),
2264: .q (),
2265:
2266: // to register interface (read)
2267: .qs (ip1_p61_qs)
2268: );
2269:
2270:
2271: // F[p62]: 30:30
2272: prim_subreg #(
2273: .DW (1),
2274: .SWACCESS("RO"),
2275: .RESVAL (1'h0)
2276: ) u_ip1_p62 (
2277: .clk_i (clk_i ),
2278: .rst_ni (rst_ni ),
2279:
2280: .we (1'b0),
2281: .wd ('0 ),
2282:
2283: // from internal hardware
2284: .de (hw2reg.ip[62].de),
2285: .d (hw2reg.ip[62].d ),
2286:
2287: // to internal hardware
2288: .qe (),
2289: .q (),
2290:
2291: // to register interface (read)
2292: .qs (ip1_p62_qs)
2293: );
2294:
2295:
2296:
2297:
2298: // Subregister 0 of Multireg le
2299: // R[le0]: V(False)
2300:
2301: // F[le0]: 0:0
2302: prim_subreg #(
2303: .DW (1),
2304: .SWACCESS("RW"),
2305: .RESVAL (1'h0)
2306: ) u_le0_le0 (
2307: .clk_i (clk_i ),
2308: .rst_ni (rst_ni ),
2309:
2310: // from register interface
2311: .we (le0_le0_we),
2312: .wd (le0_le0_wd),
2313:
2314: // from internal hardware
2315: .de (1'b0),
2316: .d ('0 ),
2317:
2318: // to internal hardware
2319: .qe (),
2320: .q (reg2hw.le[0].q ),
2321:
2322: // to register interface (read)
2323: .qs (le0_le0_qs)
2324: );
2325:
2326:
2327: // F[le1]: 1:1
2328: prim_subreg #(
2329: .DW (1),
2330: .SWACCESS("RW"),
2331: .RESVAL (1'h0)
2332: ) u_le0_le1 (
2333: .clk_i (clk_i ),
2334: .rst_ni (rst_ni ),
2335:
2336: // from register interface
2337: .we (le0_le1_we),
2338: .wd (le0_le1_wd),
2339:
2340: // from internal hardware
2341: .de (1'b0),
2342: .d ('0 ),
2343:
2344: // to internal hardware
2345: .qe (),
2346: .q (reg2hw.le[1].q ),
2347:
2348: // to register interface (read)
2349: .qs (le0_le1_qs)
2350: );
2351:
2352:
2353: // F[le2]: 2:2
2354: prim_subreg #(
2355: .DW (1),
2356: .SWACCESS("RW"),
2357: .RESVAL (1'h0)
2358: ) u_le0_le2 (
2359: .clk_i (clk_i ),
2360: .rst_ni (rst_ni ),
2361:
2362: // from register interface
2363: .we (le0_le2_we),
2364: .wd (le0_le2_wd),
2365:
2366: // from internal hardware
2367: .de (1'b0),
2368: .d ('0 ),
2369:
2370: // to internal hardware
2371: .qe (),
2372: .q (reg2hw.le[2].q ),
2373:
2374: // to register interface (read)
2375: .qs (le0_le2_qs)
2376: );
2377:
2378:
2379: // F[le3]: 3:3
2380: prim_subreg #(
2381: .DW (1),
2382: .SWACCESS("RW"),
2383: .RESVAL (1'h0)
2384: ) u_le0_le3 (
2385: .clk_i (clk_i ),
2386: .rst_ni (rst_ni ),
2387:
2388: // from register interface
2389: .we (le0_le3_we),
2390: .wd (le0_le3_wd),
2391:
2392: // from internal hardware
2393: .de (1'b0),
2394: .d ('0 ),
2395:
2396: // to internal hardware
2397: .qe (),
2398: .q (reg2hw.le[3].q ),
2399:
2400: // to register interface (read)
2401: .qs (le0_le3_qs)
2402: );
2403:
2404:
2405: // F[le4]: 4:4
2406: prim_subreg #(
2407: .DW (1),
2408: .SWACCESS("RW"),
2409: .RESVAL (1'h0)
2410: ) u_le0_le4 (
2411: .clk_i (clk_i ),
2412: .rst_ni (rst_ni ),
2413:
2414: // from register interface
2415: .we (le0_le4_we),
2416: .wd (le0_le4_wd),
2417:
2418: // from internal hardware
2419: .de (1'b0),
2420: .d ('0 ),
2421:
2422: // to internal hardware
2423: .qe (),
2424: .q (reg2hw.le[4].q ),
2425:
2426: // to register interface (read)
2427: .qs (le0_le4_qs)
2428: );
2429:
2430:
2431: // F[le5]: 5:5
2432: prim_subreg #(
2433: .DW (1),
2434: .SWACCESS("RW"),
2435: .RESVAL (1'h0)
2436: ) u_le0_le5 (
2437: .clk_i (clk_i ),
2438: .rst_ni (rst_ni ),
2439:
2440: // from register interface
2441: .we (le0_le5_we),
2442: .wd (le0_le5_wd),
2443:
2444: // from internal hardware
2445: .de (1'b0),
2446: .d ('0 ),
2447:
2448: // to internal hardware
2449: .qe (),
2450: .q (reg2hw.le[5].q ),
2451:
2452: // to register interface (read)
2453: .qs (le0_le5_qs)
2454: );
2455:
2456:
2457: // F[le6]: 6:6
2458: prim_subreg #(
2459: .DW (1),
2460: .SWACCESS("RW"),
2461: .RESVAL (1'h0)
2462: ) u_le0_le6 (
2463: .clk_i (clk_i ),
2464: .rst_ni (rst_ni ),
2465:
2466: // from register interface
2467: .we (le0_le6_we),
2468: .wd (le0_le6_wd),
2469:
2470: // from internal hardware
2471: .de (1'b0),
2472: .d ('0 ),
2473:
2474: // to internal hardware
2475: .qe (),
2476: .q (reg2hw.le[6].q ),
2477:
2478: // to register interface (read)
2479: .qs (le0_le6_qs)
2480: );
2481:
2482:
2483: // F[le7]: 7:7
2484: prim_subreg #(
2485: .DW (1),
2486: .SWACCESS("RW"),
2487: .RESVAL (1'h0)
2488: ) u_le0_le7 (
2489: .clk_i (clk_i ),
2490: .rst_ni (rst_ni ),
2491:
2492: // from register interface
2493: .we (le0_le7_we),
2494: .wd (le0_le7_wd),
2495:
2496: // from internal hardware
2497: .de (1'b0),
2498: .d ('0 ),
2499:
2500: // to internal hardware
2501: .qe (),
2502: .q (reg2hw.le[7].q ),
2503:
2504: // to register interface (read)
2505: .qs (le0_le7_qs)
2506: );
2507:
2508:
2509: // F[le8]: 8:8
2510: prim_subreg #(
2511: .DW (1),
2512: .SWACCESS("RW"),
2513: .RESVAL (1'h0)
2514: ) u_le0_le8 (
2515: .clk_i (clk_i ),
2516: .rst_ni (rst_ni ),
2517:
2518: // from register interface
2519: .we (le0_le8_we),
2520: .wd (le0_le8_wd),
2521:
2522: // from internal hardware
2523: .de (1'b0),
2524: .d ('0 ),
2525:
2526: // to internal hardware
2527: .qe (),
2528: .q (reg2hw.le[8].q ),
2529:
2530: // to register interface (read)
2531: .qs (le0_le8_qs)
2532: );
2533:
2534:
2535: // F[le9]: 9:9
2536: prim_subreg #(
2537: .DW (1),
2538: .SWACCESS("RW"),
2539: .RESVAL (1'h0)
2540: ) u_le0_le9 (
2541: .clk_i (clk_i ),
2542: .rst_ni (rst_ni ),
2543:
2544: // from register interface
2545: .we (le0_le9_we),
2546: .wd (le0_le9_wd),
2547:
2548: // from internal hardware
2549: .de (1'b0),
2550: .d ('0 ),
2551:
2552: // to internal hardware
2553: .qe (),
2554: .q (reg2hw.le[9].q ),
2555:
2556: // to register interface (read)
2557: .qs (le0_le9_qs)
2558: );
2559:
2560:
2561: // F[le10]: 10:10
2562: prim_subreg #(
2563: .DW (1),
2564: .SWACCESS("RW"),
2565: .RESVAL (1'h0)
2566: ) u_le0_le10 (
2567: .clk_i (clk_i ),
2568: .rst_ni (rst_ni ),
2569:
2570: // from register interface
2571: .we (le0_le10_we),
2572: .wd (le0_le10_wd),
2573:
2574: // from internal hardware
2575: .de (1'b0),
2576: .d ('0 ),
2577:
2578: // to internal hardware
2579: .qe (),
2580: .q (reg2hw.le[10].q ),
2581:
2582: // to register interface (read)
2583: .qs (le0_le10_qs)
2584: );
2585:
2586:
2587: // F[le11]: 11:11
2588: prim_subreg #(
2589: .DW (1),
2590: .SWACCESS("RW"),
2591: .RESVAL (1'h0)
2592: ) u_le0_le11 (
2593: .clk_i (clk_i ),
2594: .rst_ni (rst_ni ),
2595:
2596: // from register interface
2597: .we (le0_le11_we),
2598: .wd (le0_le11_wd),
2599:
2600: // from internal hardware
2601: .de (1'b0),
2602: .d ('0 ),
2603:
2604: // to internal hardware
2605: .qe (),
2606: .q (reg2hw.le[11].q ),
2607:
2608: // to register interface (read)
2609: .qs (le0_le11_qs)
2610: );
2611:
2612:
2613: // F[le12]: 12:12
2614: prim_subreg #(
2615: .DW (1),
2616: .SWACCESS("RW"),
2617: .RESVAL (1'h0)
2618: ) u_le0_le12 (
2619: .clk_i (clk_i ),
2620: .rst_ni (rst_ni ),
2621:
2622: // from register interface
2623: .we (le0_le12_we),
2624: .wd (le0_le12_wd),
2625:
2626: // from internal hardware
2627: .de (1'b0),
2628: .d ('0 ),
2629:
2630: // to internal hardware
2631: .qe (),
2632: .q (reg2hw.le[12].q ),
2633:
2634: // to register interface (read)
2635: .qs (le0_le12_qs)
2636: );
2637:
2638:
2639: // F[le13]: 13:13
2640: prim_subreg #(
2641: .DW (1),
2642: .SWACCESS("RW"),
2643: .RESVAL (1'h0)
2644: ) u_le0_le13 (
2645: .clk_i (clk_i ),
2646: .rst_ni (rst_ni ),
2647:
2648: // from register interface
2649: .we (le0_le13_we),
2650: .wd (le0_le13_wd),
2651:
2652: // from internal hardware
2653: .de (1'b0),
2654: .d ('0 ),
2655:
2656: // to internal hardware
2657: .qe (),
2658: .q (reg2hw.le[13].q ),
2659:
2660: // to register interface (read)
2661: .qs (le0_le13_qs)
2662: );
2663:
2664:
2665: // F[le14]: 14:14
2666: prim_subreg #(
2667: .DW (1),
2668: .SWACCESS("RW"),
2669: .RESVAL (1'h0)
2670: ) u_le0_le14 (
2671: .clk_i (clk_i ),
2672: .rst_ni (rst_ni ),
2673:
2674: // from register interface
2675: .we (le0_le14_we),
2676: .wd (le0_le14_wd),
2677:
2678: // from internal hardware
2679: .de (1'b0),
2680: .d ('0 ),
2681:
2682: // to internal hardware
2683: .qe (),
2684: .q (reg2hw.le[14].q ),
2685:
2686: // to register interface (read)
2687: .qs (le0_le14_qs)
2688: );
2689:
2690:
2691: // F[le15]: 15:15
2692: prim_subreg #(
2693: .DW (1),
2694: .SWACCESS("RW"),
2695: .RESVAL (1'h0)
2696: ) u_le0_le15 (
2697: .clk_i (clk_i ),
2698: .rst_ni (rst_ni ),
2699:
2700: // from register interface
2701: .we (le0_le15_we),
2702: .wd (le0_le15_wd),
2703:
2704: // from internal hardware
2705: .de (1'b0),
2706: .d ('0 ),
2707:
2708: // to internal hardware
2709: .qe (),
2710: .q (reg2hw.le[15].q ),
2711:
2712: // to register interface (read)
2713: .qs (le0_le15_qs)
2714: );
2715:
2716:
2717: // F[le16]: 16:16
2718: prim_subreg #(
2719: .DW (1),
2720: .SWACCESS("RW"),
2721: .RESVAL (1'h0)
2722: ) u_le0_le16 (
2723: .clk_i (clk_i ),
2724: .rst_ni (rst_ni ),
2725:
2726: // from register interface
2727: .we (le0_le16_we),
2728: .wd (le0_le16_wd),
2729:
2730: // from internal hardware
2731: .de (1'b0),
2732: .d ('0 ),
2733:
2734: // to internal hardware
2735: .qe (),
2736: .q (reg2hw.le[16].q ),
2737:
2738: // to register interface (read)
2739: .qs (le0_le16_qs)
2740: );
2741:
2742:
2743: // F[le17]: 17:17
2744: prim_subreg #(
2745: .DW (1),
2746: .SWACCESS("RW"),
2747: .RESVAL (1'h0)
2748: ) u_le0_le17 (
2749: .clk_i (clk_i ),
2750: .rst_ni (rst_ni ),
2751:
2752: // from register interface
2753: .we (le0_le17_we),
2754: .wd (le0_le17_wd),
2755:
2756: // from internal hardware
2757: .de (1'b0),
2758: .d ('0 ),
2759:
2760: // to internal hardware
2761: .qe (),
2762: .q (reg2hw.le[17].q ),
2763:
2764: // to register interface (read)
2765: .qs (le0_le17_qs)
2766: );
2767:
2768:
2769: // F[le18]: 18:18
2770: prim_subreg #(
2771: .DW (1),
2772: .SWACCESS("RW"),
2773: .RESVAL (1'h0)
2774: ) u_le0_le18 (
2775: .clk_i (clk_i ),
2776: .rst_ni (rst_ni ),
2777:
2778: // from register interface
2779: .we (le0_le18_we),
2780: .wd (le0_le18_wd),
2781:
2782: // from internal hardware
2783: .de (1'b0),
2784: .d ('0 ),
2785:
2786: // to internal hardware
2787: .qe (),
2788: .q (reg2hw.le[18].q ),
2789:
2790: // to register interface (read)
2791: .qs (le0_le18_qs)
2792: );
2793:
2794:
2795: // F[le19]: 19:19
2796: prim_subreg #(
2797: .DW (1),
2798: .SWACCESS("RW"),
2799: .RESVAL (1'h0)
2800: ) u_le0_le19 (
2801: .clk_i (clk_i ),
2802: .rst_ni (rst_ni ),
2803:
2804: // from register interface
2805: .we (le0_le19_we),
2806: .wd (le0_le19_wd),
2807:
2808: // from internal hardware
2809: .de (1'b0),
2810: .d ('0 ),
2811:
2812: // to internal hardware
2813: .qe (),
2814: .q (reg2hw.le[19].q ),
2815:
2816: // to register interface (read)
2817: .qs (le0_le19_qs)
2818: );
2819:
2820:
2821: // F[le20]: 20:20
2822: prim_subreg #(
2823: .DW (1),
2824: .SWACCESS("RW"),
2825: .RESVAL (1'h0)
2826: ) u_le0_le20 (
2827: .clk_i (clk_i ),
2828: .rst_ni (rst_ni ),
2829:
2830: // from register interface
2831: .we (le0_le20_we),
2832: .wd (le0_le20_wd),
2833:
2834: // from internal hardware
2835: .de (1'b0),
2836: .d ('0 ),
2837:
2838: // to internal hardware
2839: .qe (),
2840: .q (reg2hw.le[20].q ),
2841:
2842: // to register interface (read)
2843: .qs (le0_le20_qs)
2844: );
2845:
2846:
2847: // F[le21]: 21:21
2848: prim_subreg #(
2849: .DW (1),
2850: .SWACCESS("RW"),
2851: .RESVAL (1'h0)
2852: ) u_le0_le21 (
2853: .clk_i (clk_i ),
2854: .rst_ni (rst_ni ),
2855:
2856: // from register interface
2857: .we (le0_le21_we),
2858: .wd (le0_le21_wd),
2859:
2860: // from internal hardware
2861: .de (1'b0),
2862: .d ('0 ),
2863:
2864: // to internal hardware
2865: .qe (),
2866: .q (reg2hw.le[21].q ),
2867:
2868: // to register interface (read)
2869: .qs (le0_le21_qs)
2870: );
2871:
2872:
2873: // F[le22]: 22:22
2874: prim_subreg #(
2875: .DW (1),
2876: .SWACCESS("RW"),
2877: .RESVAL (1'h0)
2878: ) u_le0_le22 (
2879: .clk_i (clk_i ),
2880: .rst_ni (rst_ni ),
2881:
2882: // from register interface
2883: .we (le0_le22_we),
2884: .wd (le0_le22_wd),
2885:
2886: // from internal hardware
2887: .de (1'b0),
2888: .d ('0 ),
2889:
2890: // to internal hardware
2891: .qe (),
2892: .q (reg2hw.le[22].q ),
2893:
2894: // to register interface (read)
2895: .qs (le0_le22_qs)
2896: );
2897:
2898:
2899: // F[le23]: 23:23
2900: prim_subreg #(
2901: .DW (1),
2902: .SWACCESS("RW"),
2903: .RESVAL (1'h0)
2904: ) u_le0_le23 (
2905: .clk_i (clk_i ),
2906: .rst_ni (rst_ni ),
2907:
2908: // from register interface
2909: .we (le0_le23_we),
2910: .wd (le0_le23_wd),
2911:
2912: // from internal hardware
2913: .de (1'b0),
2914: .d ('0 ),
2915:
2916: // to internal hardware
2917: .qe (),
2918: .q (reg2hw.le[23].q ),
2919:
2920: // to register interface (read)
2921: .qs (le0_le23_qs)
2922: );
2923:
2924:
2925: // F[le24]: 24:24
2926: prim_subreg #(
2927: .DW (1),
2928: .SWACCESS("RW"),
2929: .RESVAL (1'h0)
2930: ) u_le0_le24 (
2931: .clk_i (clk_i ),
2932: .rst_ni (rst_ni ),
2933:
2934: // from register interface
2935: .we (le0_le24_we),
2936: .wd (le0_le24_wd),
2937:
2938: // from internal hardware
2939: .de (1'b0),
2940: .d ('0 ),
2941:
2942: // to internal hardware
2943: .qe (),
2944: .q (reg2hw.le[24].q ),
2945:
2946: // to register interface (read)
2947: .qs (le0_le24_qs)
2948: );
2949:
2950:
2951: // F[le25]: 25:25
2952: prim_subreg #(
2953: .DW (1),
2954: .SWACCESS("RW"),
2955: .RESVAL (1'h0)
2956: ) u_le0_le25 (
2957: .clk_i (clk_i ),
2958: .rst_ni (rst_ni ),
2959:
2960: // from register interface
2961: .we (le0_le25_we),
2962: .wd (le0_le25_wd),
2963:
2964: // from internal hardware
2965: .de (1'b0),
2966: .d ('0 ),
2967:
2968: // to internal hardware
2969: .qe (),
2970: .q (reg2hw.le[25].q ),
2971:
2972: // to register interface (read)
2973: .qs (le0_le25_qs)
2974: );
2975:
2976:
2977: // F[le26]: 26:26
2978: prim_subreg #(
2979: .DW (1),
2980: .SWACCESS("RW"),
2981: .RESVAL (1'h0)
2982: ) u_le0_le26 (
2983: .clk_i (clk_i ),
2984: .rst_ni (rst_ni ),
2985:
2986: // from register interface
2987: .we (le0_le26_we),
2988: .wd (le0_le26_wd),
2989:
2990: // from internal hardware
2991: .de (1'b0),
2992: .d ('0 ),
2993:
2994: // to internal hardware
2995: .qe (),
2996: .q (reg2hw.le[26].q ),
2997:
2998: // to register interface (read)
2999: .qs (le0_le26_qs)
3000: );
3001:
3002:
3003: // F[le27]: 27:27
3004: prim_subreg #(
3005: .DW (1),
3006: .SWACCESS("RW"),
3007: .RESVAL (1'h0)
3008: ) u_le0_le27 (
3009: .clk_i (clk_i ),
3010: .rst_ni (rst_ni ),
3011:
3012: // from register interface
3013: .we (le0_le27_we),
3014: .wd (le0_le27_wd),
3015:
3016: // from internal hardware
3017: .de (1'b0),
3018: .d ('0 ),
3019:
3020: // to internal hardware
3021: .qe (),
3022: .q (reg2hw.le[27].q ),
3023:
3024: // to register interface (read)
3025: .qs (le0_le27_qs)
3026: );
3027:
3028:
3029: // F[le28]: 28:28
3030: prim_subreg #(
3031: .DW (1),
3032: .SWACCESS("RW"),
3033: .RESVAL (1'h0)
3034: ) u_le0_le28 (
3035: .clk_i (clk_i ),
3036: .rst_ni (rst_ni ),
3037:
3038: // from register interface
3039: .we (le0_le28_we),
3040: .wd (le0_le28_wd),
3041:
3042: // from internal hardware
3043: .de (1'b0),
3044: .d ('0 ),
3045:
3046: // to internal hardware
3047: .qe (),
3048: .q (reg2hw.le[28].q ),
3049:
3050: // to register interface (read)
3051: .qs (le0_le28_qs)
3052: );
3053:
3054:
3055: // F[le29]: 29:29
3056: prim_subreg #(
3057: .DW (1),
3058: .SWACCESS("RW"),
3059: .RESVAL (1'h0)
3060: ) u_le0_le29 (
3061: .clk_i (clk_i ),
3062: .rst_ni (rst_ni ),
3063:
3064: // from register interface
3065: .we (le0_le29_we),
3066: .wd (le0_le29_wd),
3067:
3068: // from internal hardware
3069: .de (1'b0),
3070: .d ('0 ),
3071:
3072: // to internal hardware
3073: .qe (),
3074: .q (reg2hw.le[29].q ),
3075:
3076: // to register interface (read)
3077: .qs (le0_le29_qs)
3078: );
3079:
3080:
3081: // F[le30]: 30:30
3082: prim_subreg #(
3083: .DW (1),
3084: .SWACCESS("RW"),
3085: .RESVAL (1'h0)
3086: ) u_le0_le30 (
3087: .clk_i (clk_i ),
3088: .rst_ni (rst_ni ),
3089:
3090: // from register interface
3091: .we (le0_le30_we),
3092: .wd (le0_le30_wd),
3093:
3094: // from internal hardware
3095: .de (1'b0),
3096: .d ('0 ),
3097:
3098: // to internal hardware
3099: .qe (),
3100: .q (reg2hw.le[30].q ),
3101:
3102: // to register interface (read)
3103: .qs (le0_le30_qs)
3104: );
3105:
3106:
3107: // F[le31]: 31:31
3108: prim_subreg #(
3109: .DW (1),
3110: .SWACCESS("RW"),
3111: .RESVAL (1'h0)
3112: ) u_le0_le31 (
3113: .clk_i (clk_i ),
3114: .rst_ni (rst_ni ),
3115:
3116: // from register interface
3117: .we (le0_le31_we),
3118: .wd (le0_le31_wd),
3119:
3120: // from internal hardware
3121: .de (1'b0),
3122: .d ('0 ),
3123:
3124: // to internal hardware
3125: .qe (),
3126: .q (reg2hw.le[31].q ),
3127:
3128: // to register interface (read)
3129: .qs (le0_le31_qs)
3130: );
3131:
3132:
3133: // Subregister 32 of Multireg le
3134: // R[le1]: V(False)
3135:
3136: // F[le32]: 0:0
3137: prim_subreg #(
3138: .DW (1),
3139: .SWACCESS("RW"),
3140: .RESVAL (1'h0)
3141: ) u_le1_le32 (
3142: .clk_i (clk_i ),
3143: .rst_ni (rst_ni ),
3144:
3145: // from register interface
3146: .we (le1_le32_we),
3147: .wd (le1_le32_wd),
3148:
3149: // from internal hardware
3150: .de (1'b0),
3151: .d ('0 ),
3152:
3153: // to internal hardware
3154: .qe (),
3155: .q (reg2hw.le[32].q ),
3156:
3157: // to register interface (read)
3158: .qs (le1_le32_qs)
3159: );
3160:
3161:
3162: // F[le33]: 1:1
3163: prim_subreg #(
3164: .DW (1),
3165: .SWACCESS("RW"),
3166: .RESVAL (1'h0)
3167: ) u_le1_le33 (
3168: .clk_i (clk_i ),
3169: .rst_ni (rst_ni ),
3170:
3171: // from register interface
3172: .we (le1_le33_we),
3173: .wd (le1_le33_wd),
3174:
3175: // from internal hardware
3176: .de (1'b0),
3177: .d ('0 ),
3178:
3179: // to internal hardware
3180: .qe (),
3181: .q (reg2hw.le[33].q ),
3182:
3183: // to register interface (read)
3184: .qs (le1_le33_qs)
3185: );
3186:
3187:
3188: // F[le34]: 2:2
3189: prim_subreg #(
3190: .DW (1),
3191: .SWACCESS("RW"),
3192: .RESVAL (1'h0)
3193: ) u_le1_le34 (
3194: .clk_i (clk_i ),
3195: .rst_ni (rst_ni ),
3196:
3197: // from register interface
3198: .we (le1_le34_we),
3199: .wd (le1_le34_wd),
3200:
3201: // from internal hardware
3202: .de (1'b0),
3203: .d ('0 ),
3204:
3205: // to internal hardware
3206: .qe (),
3207: .q (reg2hw.le[34].q ),
3208:
3209: // to register interface (read)
3210: .qs (le1_le34_qs)
3211: );
3212:
3213:
3214: // F[le35]: 3:3
3215: prim_subreg #(
3216: .DW (1),
3217: .SWACCESS("RW"),
3218: .RESVAL (1'h0)
3219: ) u_le1_le35 (
3220: .clk_i (clk_i ),
3221: .rst_ni (rst_ni ),
3222:
3223: // from register interface
3224: .we (le1_le35_we),
3225: .wd (le1_le35_wd),
3226:
3227: // from internal hardware
3228: .de (1'b0),
3229: .d ('0 ),
3230:
3231: // to internal hardware
3232: .qe (),
3233: .q (reg2hw.le[35].q ),
3234:
3235: // to register interface (read)
3236: .qs (le1_le35_qs)
3237: );
3238:
3239:
3240: // F[le36]: 4:4
3241: prim_subreg #(
3242: .DW (1),
3243: .SWACCESS("RW"),
3244: .RESVAL (1'h0)
3245: ) u_le1_le36 (
3246: .clk_i (clk_i ),
3247: .rst_ni (rst_ni ),
3248:
3249: // from register interface
3250: .we (le1_le36_we),
3251: .wd (le1_le36_wd),
3252:
3253: // from internal hardware
3254: .de (1'b0),
3255: .d ('0 ),
3256:
3257: // to internal hardware
3258: .qe (),
3259: .q (reg2hw.le[36].q ),
3260:
3261: // to register interface (read)
3262: .qs (le1_le36_qs)
3263: );
3264:
3265:
3266: // F[le37]: 5:5
3267: prim_subreg #(
3268: .DW (1),
3269: .SWACCESS("RW"),
3270: .RESVAL (1'h0)
3271: ) u_le1_le37 (
3272: .clk_i (clk_i ),
3273: .rst_ni (rst_ni ),
3274:
3275: // from register interface
3276: .we (le1_le37_we),
3277: .wd (le1_le37_wd),
3278:
3279: // from internal hardware
3280: .de (1'b0),
3281: .d ('0 ),
3282:
3283: // to internal hardware
3284: .qe (),
3285: .q (reg2hw.le[37].q ),
3286:
3287: // to register interface (read)
3288: .qs (le1_le37_qs)
3289: );
3290:
3291:
3292: // F[le38]: 6:6
3293: prim_subreg #(
3294: .DW (1),
3295: .SWACCESS("RW"),
3296: .RESVAL (1'h0)
3297: ) u_le1_le38 (
3298: .clk_i (clk_i ),
3299: .rst_ni (rst_ni ),
3300:
3301: // from register interface
3302: .we (le1_le38_we),
3303: .wd (le1_le38_wd),
3304:
3305: // from internal hardware
3306: .de (1'b0),
3307: .d ('0 ),
3308:
3309: // to internal hardware
3310: .qe (),
3311: .q (reg2hw.le[38].q ),
3312:
3313: // to register interface (read)
3314: .qs (le1_le38_qs)
3315: );
3316:
3317:
3318: // F[le39]: 7:7
3319: prim_subreg #(
3320: .DW (1),
3321: .SWACCESS("RW"),
3322: .RESVAL (1'h0)
3323: ) u_le1_le39 (
3324: .clk_i (clk_i ),
3325: .rst_ni (rst_ni ),
3326:
3327: // from register interface
3328: .we (le1_le39_we),
3329: .wd (le1_le39_wd),
3330:
3331: // from internal hardware
3332: .de (1'b0),
3333: .d ('0 ),
3334:
3335: // to internal hardware
3336: .qe (),
3337: .q (reg2hw.le[39].q ),
3338:
3339: // to register interface (read)
3340: .qs (le1_le39_qs)
3341: );
3342:
3343:
3344: // F[le40]: 8:8
3345: prim_subreg #(
3346: .DW (1),
3347: .SWACCESS("RW"),
3348: .RESVAL (1'h0)
3349: ) u_le1_le40 (
3350: .clk_i (clk_i ),
3351: .rst_ni (rst_ni ),
3352:
3353: // from register interface
3354: .we (le1_le40_we),
3355: .wd (le1_le40_wd),
3356:
3357: // from internal hardware
3358: .de (1'b0),
3359: .d ('0 ),
3360:
3361: // to internal hardware
3362: .qe (),
3363: .q (reg2hw.le[40].q ),
3364:
3365: // to register interface (read)
3366: .qs (le1_le40_qs)
3367: );
3368:
3369:
3370: // F[le41]: 9:9
3371: prim_subreg #(
3372: .DW (1),
3373: .SWACCESS("RW"),
3374: .RESVAL (1'h0)
3375: ) u_le1_le41 (
3376: .clk_i (clk_i ),
3377: .rst_ni (rst_ni ),
3378:
3379: // from register interface
3380: .we (le1_le41_we),
3381: .wd (le1_le41_wd),
3382:
3383: // from internal hardware
3384: .de (1'b0),
3385: .d ('0 ),
3386:
3387: // to internal hardware
3388: .qe (),
3389: .q (reg2hw.le[41].q ),
3390:
3391: // to register interface (read)
3392: .qs (le1_le41_qs)
3393: );
3394:
3395:
3396: // F[le42]: 10:10
3397: prim_subreg #(
3398: .DW (1),
3399: .SWACCESS("RW"),
3400: .RESVAL (1'h0)
3401: ) u_le1_le42 (
3402: .clk_i (clk_i ),
3403: .rst_ni (rst_ni ),
3404:
3405: // from register interface
3406: .we (le1_le42_we),
3407: .wd (le1_le42_wd),
3408:
3409: // from internal hardware
3410: .de (1'b0),
3411: .d ('0 ),
3412:
3413: // to internal hardware
3414: .qe (),
3415: .q (reg2hw.le[42].q ),
3416:
3417: // to register interface (read)
3418: .qs (le1_le42_qs)
3419: );
3420:
3421:
3422: // F[le43]: 11:11
3423: prim_subreg #(
3424: .DW (1),
3425: .SWACCESS("RW"),
3426: .RESVAL (1'h0)
3427: ) u_le1_le43 (
3428: .clk_i (clk_i ),
3429: .rst_ni (rst_ni ),
3430:
3431: // from register interface
3432: .we (le1_le43_we),
3433: .wd (le1_le43_wd),
3434:
3435: // from internal hardware
3436: .de (1'b0),
3437: .d ('0 ),
3438:
3439: // to internal hardware
3440: .qe (),
3441: .q (reg2hw.le[43].q ),
3442:
3443: // to register interface (read)
3444: .qs (le1_le43_qs)
3445: );
3446:
3447:
3448: // F[le44]: 12:12
3449: prim_subreg #(
3450: .DW (1),
3451: .SWACCESS("RW"),
3452: .RESVAL (1'h0)
3453: ) u_le1_le44 (
3454: .clk_i (clk_i ),
3455: .rst_ni (rst_ni ),
3456:
3457: // from register interface
3458: .we (le1_le44_we),
3459: .wd (le1_le44_wd),
3460:
3461: // from internal hardware
3462: .de (1'b0),
3463: .d ('0 ),
3464:
3465: // to internal hardware
3466: .qe (),
3467: .q (reg2hw.le[44].q ),
3468:
3469: // to register interface (read)
3470: .qs (le1_le44_qs)
3471: );
3472:
3473:
3474: // F[le45]: 13:13
3475: prim_subreg #(
3476: .DW (1),
3477: .SWACCESS("RW"),
3478: .RESVAL (1'h0)
3479: ) u_le1_le45 (
3480: .clk_i (clk_i ),
3481: .rst_ni (rst_ni ),
3482:
3483: // from register interface
3484: .we (le1_le45_we),
3485: .wd (le1_le45_wd),
3486:
3487: // from internal hardware
3488: .de (1'b0),
3489: .d ('0 ),
3490:
3491: // to internal hardware
3492: .qe (),
3493: .q (reg2hw.le[45].q ),
3494:
3495: // to register interface (read)
3496: .qs (le1_le45_qs)
3497: );
3498:
3499:
3500: // F[le46]: 14:14
3501: prim_subreg #(
3502: .DW (1),
3503: .SWACCESS("RW"),
3504: .RESVAL (1'h0)
3505: ) u_le1_le46 (
3506: .clk_i (clk_i ),
3507: .rst_ni (rst_ni ),
3508:
3509: // from register interface
3510: .we (le1_le46_we),
3511: .wd (le1_le46_wd),
3512:
3513: // from internal hardware
3514: .de (1'b0),
3515: .d ('0 ),
3516:
3517: // to internal hardware
3518: .qe (),
3519: .q (reg2hw.le[46].q ),
3520:
3521: // to register interface (read)
3522: .qs (le1_le46_qs)
3523: );
3524:
3525:
3526: // F[le47]: 15:15
3527: prim_subreg #(
3528: .DW (1),
3529: .SWACCESS("RW"),
3530: .RESVAL (1'h0)
3531: ) u_le1_le47 (
3532: .clk_i (clk_i ),
3533: .rst_ni (rst_ni ),
3534:
3535: // from register interface
3536: .we (le1_le47_we),
3537: .wd (le1_le47_wd),
3538:
3539: // from internal hardware
3540: .de (1'b0),
3541: .d ('0 ),
3542:
3543: // to internal hardware
3544: .qe (),
3545: .q (reg2hw.le[47].q ),
3546:
3547: // to register interface (read)
3548: .qs (le1_le47_qs)
3549: );
3550:
3551:
3552: // F[le48]: 16:16
3553: prim_subreg #(
3554: .DW (1),
3555: .SWACCESS("RW"),
3556: .RESVAL (1'h0)
3557: ) u_le1_le48 (
3558: .clk_i (clk_i ),
3559: .rst_ni (rst_ni ),
3560:
3561: // from register interface
3562: .we (le1_le48_we),
3563: .wd (le1_le48_wd),
3564:
3565: // from internal hardware
3566: .de (1'b0),
3567: .d ('0 ),
3568:
3569: // to internal hardware
3570: .qe (),
3571: .q (reg2hw.le[48].q ),
3572:
3573: // to register interface (read)
3574: .qs (le1_le48_qs)
3575: );
3576:
3577:
3578: // F[le49]: 17:17
3579: prim_subreg #(
3580: .DW (1),
3581: .SWACCESS("RW"),
3582: .RESVAL (1'h0)
3583: ) u_le1_le49 (
3584: .clk_i (clk_i ),
3585: .rst_ni (rst_ni ),
3586:
3587: // from register interface
3588: .we (le1_le49_we),
3589: .wd (le1_le49_wd),
3590:
3591: // from internal hardware
3592: .de (1'b0),
3593: .d ('0 ),
3594:
3595: // to internal hardware
3596: .qe (),
3597: .q (reg2hw.le[49].q ),
3598:
3599: // to register interface (read)
3600: .qs (le1_le49_qs)
3601: );
3602:
3603:
3604: // F[le50]: 18:18
3605: prim_subreg #(
3606: .DW (1),
3607: .SWACCESS("RW"),
3608: .RESVAL (1'h0)
3609: ) u_le1_le50 (
3610: .clk_i (clk_i ),
3611: .rst_ni (rst_ni ),
3612:
3613: // from register interface
3614: .we (le1_le50_we),
3615: .wd (le1_le50_wd),
3616:
3617: // from internal hardware
3618: .de (1'b0),
3619: .d ('0 ),
3620:
3621: // to internal hardware
3622: .qe (),
3623: .q (reg2hw.le[50].q ),
3624:
3625: // to register interface (read)
3626: .qs (le1_le50_qs)
3627: );
3628:
3629:
3630: // F[le51]: 19:19
3631: prim_subreg #(
3632: .DW (1),
3633: .SWACCESS("RW"),
3634: .RESVAL (1'h0)
3635: ) u_le1_le51 (
3636: .clk_i (clk_i ),
3637: .rst_ni (rst_ni ),
3638:
3639: // from register interface
3640: .we (le1_le51_we),
3641: .wd (le1_le51_wd),
3642:
3643: // from internal hardware
3644: .de (1'b0),
3645: .d ('0 ),
3646:
3647: // to internal hardware
3648: .qe (),
3649: .q (reg2hw.le[51].q ),
3650:
3651: // to register interface (read)
3652: .qs (le1_le51_qs)
3653: );
3654:
3655:
3656: // F[le52]: 20:20
3657: prim_subreg #(
3658: .DW (1),
3659: .SWACCESS("RW"),
3660: .RESVAL (1'h0)
3661: ) u_le1_le52 (
3662: .clk_i (clk_i ),
3663: .rst_ni (rst_ni ),
3664:
3665: // from register interface
3666: .we (le1_le52_we),
3667: .wd (le1_le52_wd),
3668:
3669: // from internal hardware
3670: .de (1'b0),
3671: .d ('0 ),
3672:
3673: // to internal hardware
3674: .qe (),
3675: .q (reg2hw.le[52].q ),
3676:
3677: // to register interface (read)
3678: .qs (le1_le52_qs)
3679: );
3680:
3681:
3682: // F[le53]: 21:21
3683: prim_subreg #(
3684: .DW (1),
3685: .SWACCESS("RW"),
3686: .RESVAL (1'h0)
3687: ) u_le1_le53 (
3688: .clk_i (clk_i ),
3689: .rst_ni (rst_ni ),
3690:
3691: // from register interface
3692: .we (le1_le53_we),
3693: .wd (le1_le53_wd),
3694:
3695: // from internal hardware
3696: .de (1'b0),
3697: .d ('0 ),
3698:
3699: // to internal hardware
3700: .qe (),
3701: .q (reg2hw.le[53].q ),
3702:
3703: // to register interface (read)
3704: .qs (le1_le53_qs)
3705: );
3706:
3707:
3708: // F[le54]: 22:22
3709: prim_subreg #(
3710: .DW (1),
3711: .SWACCESS("RW"),
3712: .RESVAL (1'h0)
3713: ) u_le1_le54 (
3714: .clk_i (clk_i ),
3715: .rst_ni (rst_ni ),
3716:
3717: // from register interface
3718: .we (le1_le54_we),
3719: .wd (le1_le54_wd),
3720:
3721: // from internal hardware
3722: .de (1'b0),
3723: .d ('0 ),
3724:
3725: // to internal hardware
3726: .qe (),
3727: .q (reg2hw.le[54].q ),
3728:
3729: // to register interface (read)
3730: .qs (le1_le54_qs)
3731: );
3732:
3733:
3734: // F[le55]: 23:23
3735: prim_subreg #(
3736: .DW (1),
3737: .SWACCESS("RW"),
3738: .RESVAL (1'h0)
3739: ) u_le1_le55 (
3740: .clk_i (clk_i ),
3741: .rst_ni (rst_ni ),
3742:
3743: // from register interface
3744: .we (le1_le55_we),
3745: .wd (le1_le55_wd),
3746:
3747: // from internal hardware
3748: .de (1'b0),
3749: .d ('0 ),
3750:
3751: // to internal hardware
3752: .qe (),
3753: .q (reg2hw.le[55].q ),
3754:
3755: // to register interface (read)
3756: .qs (le1_le55_qs)
3757: );
3758:
3759:
3760: // F[le56]: 24:24
3761: prim_subreg #(
3762: .DW (1),
3763: .SWACCESS("RW"),
3764: .RESVAL (1'h0)
3765: ) u_le1_le56 (
3766: .clk_i (clk_i ),
3767: .rst_ni (rst_ni ),
3768:
3769: // from register interface
3770: .we (le1_le56_we),
3771: .wd (le1_le56_wd),
3772:
3773: // from internal hardware
3774: .de (1'b0),
3775: .d ('0 ),
3776:
3777: // to internal hardware
3778: .qe (),
3779: .q (reg2hw.le[56].q ),
3780:
3781: // to register interface (read)
3782: .qs (le1_le56_qs)
3783: );
3784:
3785:
3786: // F[le57]: 25:25
3787: prim_subreg #(
3788: .DW (1),
3789: .SWACCESS("RW"),
3790: .RESVAL (1'h0)
3791: ) u_le1_le57 (
3792: .clk_i (clk_i ),
3793: .rst_ni (rst_ni ),
3794:
3795: // from register interface
3796: .we (le1_le57_we),
3797: .wd (le1_le57_wd),
3798:
3799: // from internal hardware
3800: .de (1'b0),
3801: .d ('0 ),
3802:
3803: // to internal hardware
3804: .qe (),
3805: .q (reg2hw.le[57].q ),
3806:
3807: // to register interface (read)
3808: .qs (le1_le57_qs)
3809: );
3810:
3811:
3812: // F[le58]: 26:26
3813: prim_subreg #(
3814: .DW (1),
3815: .SWACCESS("RW"),
3816: .RESVAL (1'h0)
3817: ) u_le1_le58 (
3818: .clk_i (clk_i ),
3819: .rst_ni (rst_ni ),
3820:
3821: // from register interface
3822: .we (le1_le58_we),
3823: .wd (le1_le58_wd),
3824:
3825: // from internal hardware
3826: .de (1'b0),
3827: .d ('0 ),
3828:
3829: // to internal hardware
3830: .qe (),
3831: .q (reg2hw.le[58].q ),
3832:
3833: // to register interface (read)
3834: .qs (le1_le58_qs)
3835: );
3836:
3837:
3838: // F[le59]: 27:27
3839: prim_subreg #(
3840: .DW (1),
3841: .SWACCESS("RW"),
3842: .RESVAL (1'h0)
3843: ) u_le1_le59 (
3844: .clk_i (clk_i ),
3845: .rst_ni (rst_ni ),
3846:
3847: // from register interface
3848: .we (le1_le59_we),
3849: .wd (le1_le59_wd),
3850:
3851: // from internal hardware
3852: .de (1'b0),
3853: .d ('0 ),
3854:
3855: // to internal hardware
3856: .qe (),
3857: .q (reg2hw.le[59].q ),
3858:
3859: // to register interface (read)
3860: .qs (le1_le59_qs)
3861: );
3862:
3863:
3864: // F[le60]: 28:28
3865: prim_subreg #(
3866: .DW (1),
3867: .SWACCESS("RW"),
3868: .RESVAL (1'h0)
3869: ) u_le1_le60 (
3870: .clk_i (clk_i ),
3871: .rst_ni (rst_ni ),
3872:
3873: // from register interface
3874: .we (le1_le60_we),
3875: .wd (le1_le60_wd),
3876:
3877: // from internal hardware
3878: .de (1'b0),
3879: .d ('0 ),
3880:
3881: // to internal hardware
3882: .qe (),
3883: .q (reg2hw.le[60].q ),
3884:
3885: // to register interface (read)
3886: .qs (le1_le60_qs)
3887: );
3888:
3889:
3890: // F[le61]: 29:29
3891: prim_subreg #(
3892: .DW (1),
3893: .SWACCESS("RW"),
3894: .RESVAL (1'h0)
3895: ) u_le1_le61 (
3896: .clk_i (clk_i ),
3897: .rst_ni (rst_ni ),
3898:
3899: // from register interface
3900: .we (le1_le61_we),
3901: .wd (le1_le61_wd),
3902:
3903: // from internal hardware
3904: .de (1'b0),
3905: .d ('0 ),
3906:
3907: // to internal hardware
3908: .qe (),
3909: .q (reg2hw.le[61].q ),
3910:
3911: // to register interface (read)
3912: .qs (le1_le61_qs)
3913: );
3914:
3915:
3916: // F[le62]: 30:30
3917: prim_subreg #(
3918: .DW (1),
3919: .SWACCESS("RW"),
3920: .RESVAL (1'h0)
3921: ) u_le1_le62 (
3922: .clk_i (clk_i ),
3923: .rst_ni (rst_ni ),
3924:
3925: // from register interface
3926: .we (le1_le62_we),
3927: .wd (le1_le62_wd),
3928:
3929: // from internal hardware
3930: .de (1'b0),
3931: .d ('0 ),
3932:
3933: // to internal hardware
3934: .qe (),
3935: .q (reg2hw.le[62].q ),
3936:
3937: // to register interface (read)
3938: .qs (le1_le62_qs)
3939: );
3940:
3941:
3942:
3943: // R[prio0]: V(False)
3944:
3945: prim_subreg #(
3946: .DW (2),
3947: .SWACCESS("RW"),
3948: .RESVAL (2'h0)
3949: ) u_prio0 (
3950: .clk_i (clk_i ),
3951: .rst_ni (rst_ni ),
3952:
3953: // from register interface
3954: .we (prio0_we),
3955: .wd (prio0_wd),
3956:
3957: // from internal hardware
3958: .de (1'b0),
3959: .d ('0 ),
3960:
3961: // to internal hardware
3962: .qe (),
3963: .q (reg2hw.prio0.q ),
3964:
3965: // to register interface (read)
3966: .qs (prio0_qs)
3967: );
3968:
3969:
3970: // R[prio1]: V(False)
3971:
3972: prim_subreg #(
3973: .DW (2),
3974: .SWACCESS("RW"),
3975: .RESVAL (2'h0)
3976: ) u_prio1 (
3977: .clk_i (clk_i ),
3978: .rst_ni (rst_ni ),
3979:
3980: // from register interface
3981: .we (prio1_we),
3982: .wd (prio1_wd),
3983:
3984: // from internal hardware
3985: .de (1'b0),
3986: .d ('0 ),
3987:
3988: // to internal hardware
3989: .qe (),
3990: .q (reg2hw.prio1.q ),
3991:
3992: // to register interface (read)
3993: .qs (prio1_qs)
3994: );
3995:
3996:
3997: // R[prio2]: V(False)
3998:
3999: prim_subreg #(
4000: .DW (2),
4001: .SWACCESS("RW"),
4002: .RESVAL (2'h0)
4003: ) u_prio2 (
4004: .clk_i (clk_i ),
4005: .rst_ni (rst_ni ),
4006:
4007: // from register interface
4008: .we (prio2_we),
4009: .wd (prio2_wd),
4010:
4011: // from internal hardware
4012: .de (1'b0),
4013: .d ('0 ),
4014:
4015: // to internal hardware
4016: .qe (),
4017: .q (reg2hw.prio2.q ),
4018:
4019: // to register interface (read)
4020: .qs (prio2_qs)
4021: );
4022:
4023:
4024: // R[prio3]: V(False)
4025:
4026: prim_subreg #(
4027: .DW (2),
4028: .SWACCESS("RW"),
4029: .RESVAL (2'h0)
4030: ) u_prio3 (
4031: .clk_i (clk_i ),
4032: .rst_ni (rst_ni ),
4033:
4034: // from register interface
4035: .we (prio3_we),
4036: .wd (prio3_wd),
4037:
4038: // from internal hardware
4039: .de (1'b0),
4040: .d ('0 ),
4041:
4042: // to internal hardware
4043: .qe (),
4044: .q (reg2hw.prio3.q ),
4045:
4046: // to register interface (read)
4047: .qs (prio3_qs)
4048: );
4049:
4050:
4051: // R[prio4]: V(False)
4052:
4053: prim_subreg #(
4054: .DW (2),
4055: .SWACCESS("RW"),
4056: .RESVAL (2'h0)
4057: ) u_prio4 (
4058: .clk_i (clk_i ),
4059: .rst_ni (rst_ni ),
4060:
4061: // from register interface
4062: .we (prio4_we),
4063: .wd (prio4_wd),
4064:
4065: // from internal hardware
4066: .de (1'b0),
4067: .d ('0 ),
4068:
4069: // to internal hardware
4070: .qe (),
4071: .q (reg2hw.prio4.q ),
4072:
4073: // to register interface (read)
4074: .qs (prio4_qs)
4075: );
4076:
4077:
4078: // R[prio5]: V(False)
4079:
4080: prim_subreg #(
4081: .DW (2),
4082: .SWACCESS("RW"),
4083: .RESVAL (2'h0)
4084: ) u_prio5 (
4085: .clk_i (clk_i ),
4086: .rst_ni (rst_ni ),
4087:
4088: // from register interface
4089: .we (prio5_we),
4090: .wd (prio5_wd),
4091:
4092: // from internal hardware
4093: .de (1'b0),
4094: .d ('0 ),
4095:
4096: // to internal hardware
4097: .qe (),
4098: .q (reg2hw.prio5.q ),
4099:
4100: // to register interface (read)
4101: .qs (prio5_qs)
4102: );
4103:
4104:
4105: // R[prio6]: V(False)
4106:
4107: prim_subreg #(
4108: .DW (2),
4109: .SWACCESS("RW"),
4110: .RESVAL (2'h0)
4111: ) u_prio6 (
4112: .clk_i (clk_i ),
4113: .rst_ni (rst_ni ),
4114:
4115: // from register interface
4116: .we (prio6_we),
4117: .wd (prio6_wd),
4118:
4119: // from internal hardware
4120: .de (1'b0),
4121: .d ('0 ),
4122:
4123: // to internal hardware
4124: .qe (),
4125: .q (reg2hw.prio6.q ),
4126:
4127: // to register interface (read)
4128: .qs (prio6_qs)
4129: );
4130:
4131:
4132: // R[prio7]: V(False)
4133:
4134: prim_subreg #(
4135: .DW (2),
4136: .SWACCESS("RW"),
4137: .RESVAL (2'h0)
4138: ) u_prio7 (
4139: .clk_i (clk_i ),
4140: .rst_ni (rst_ni ),
4141:
4142: // from register interface
4143: .we (prio7_we),
4144: .wd (prio7_wd),
4145:
4146: // from internal hardware
4147: .de (1'b0),
4148: .d ('0 ),
4149:
4150: // to internal hardware
4151: .qe (),
4152: .q (reg2hw.prio7.q ),
4153:
4154: // to register interface (read)
4155: .qs (prio7_qs)
4156: );
4157:
4158:
4159: // R[prio8]: V(False)
4160:
4161: prim_subreg #(
4162: .DW (2),
4163: .SWACCESS("RW"),
4164: .RESVAL (2'h0)
4165: ) u_prio8 (
4166: .clk_i (clk_i ),
4167: .rst_ni (rst_ni ),
4168:
4169: // from register interface
4170: .we (prio8_we),
4171: .wd (prio8_wd),
4172:
4173: // from internal hardware
4174: .de (1'b0),
4175: .d ('0 ),
4176:
4177: // to internal hardware
4178: .qe (),
4179: .q (reg2hw.prio8.q ),
4180:
4181: // to register interface (read)
4182: .qs (prio8_qs)
4183: );
4184:
4185:
4186: // R[prio9]: V(False)
4187:
4188: prim_subreg #(
4189: .DW (2),
4190: .SWACCESS("RW"),
4191: .RESVAL (2'h0)
4192: ) u_prio9 (
4193: .clk_i (clk_i ),
4194: .rst_ni (rst_ni ),
4195:
4196: // from register interface
4197: .we (prio9_we),
4198: .wd (prio9_wd),
4199:
4200: // from internal hardware
4201: .de (1'b0),
4202: .d ('0 ),
4203:
4204: // to internal hardware
4205: .qe (),
4206: .q (reg2hw.prio9.q ),
4207:
4208: // to register interface (read)
4209: .qs (prio9_qs)
4210: );
4211:
4212:
4213: // R[prio10]: V(False)
4214:
4215: prim_subreg #(
4216: .DW (2),
4217: .SWACCESS("RW"),
4218: .RESVAL (2'h0)
4219: ) u_prio10 (
4220: .clk_i (clk_i ),
4221: .rst_ni (rst_ni ),
4222:
4223: // from register interface
4224: .we (prio10_we),
4225: .wd (prio10_wd),
4226:
4227: // from internal hardware
4228: .de (1'b0),
4229: .d ('0 ),
4230:
4231: // to internal hardware
4232: .qe (),
4233: .q (reg2hw.prio10.q ),
4234:
4235: // to register interface (read)
4236: .qs (prio10_qs)
4237: );
4238:
4239:
4240: // R[prio11]: V(False)
4241:
4242: prim_subreg #(
4243: .DW (2),
4244: .SWACCESS("RW"),
4245: .RESVAL (2'h0)
4246: ) u_prio11 (
4247: .clk_i (clk_i ),
4248: .rst_ni (rst_ni ),
4249:
4250: // from register interface
4251: .we (prio11_we),
4252: .wd (prio11_wd),
4253:
4254: // from internal hardware
4255: .de (1'b0),
4256: .d ('0 ),
4257:
4258: // to internal hardware
4259: .qe (),
4260: .q (reg2hw.prio11.q ),
4261:
4262: // to register interface (read)
4263: .qs (prio11_qs)
4264: );
4265:
4266:
4267: // R[prio12]: V(False)
4268:
4269: prim_subreg #(
4270: .DW (2),
4271: .SWACCESS("RW"),
4272: .RESVAL (2'h0)
4273: ) u_prio12 (
4274: .clk_i (clk_i ),
4275: .rst_ni (rst_ni ),
4276:
4277: // from register interface
4278: .we (prio12_we),
4279: .wd (prio12_wd),
4280:
4281: // from internal hardware
4282: .de (1'b0),
4283: .d ('0 ),
4284:
4285: // to internal hardware
4286: .qe (),
4287: .q (reg2hw.prio12.q ),
4288:
4289: // to register interface (read)
4290: .qs (prio12_qs)
4291: );
4292:
4293:
4294: // R[prio13]: V(False)
4295:
4296: prim_subreg #(
4297: .DW (2),
4298: .SWACCESS("RW"),
4299: .RESVAL (2'h0)
4300: ) u_prio13 (
4301: .clk_i (clk_i ),
4302: .rst_ni (rst_ni ),
4303:
4304: // from register interface
4305: .we (prio13_we),
4306: .wd (prio13_wd),
4307:
4308: // from internal hardware
4309: .de (1'b0),
4310: .d ('0 ),
4311:
4312: // to internal hardware
4313: .qe (),
4314: .q (reg2hw.prio13.q ),
4315:
4316: // to register interface (read)
4317: .qs (prio13_qs)
4318: );
4319:
4320:
4321: // R[prio14]: V(False)
4322:
4323: prim_subreg #(
4324: .DW (2),
4325: .SWACCESS("RW"),
4326: .RESVAL (2'h0)
4327: ) u_prio14 (
4328: .clk_i (clk_i ),
4329: .rst_ni (rst_ni ),
4330:
4331: // from register interface
4332: .we (prio14_we),
4333: .wd (prio14_wd),
4334:
4335: // from internal hardware
4336: .de (1'b0),
4337: .d ('0 ),
4338:
4339: // to internal hardware
4340: .qe (),
4341: .q (reg2hw.prio14.q ),
4342:
4343: // to register interface (read)
4344: .qs (prio14_qs)
4345: );
4346:
4347:
4348: // R[prio15]: V(False)
4349:
4350: prim_subreg #(
4351: .DW (2),
4352: .SWACCESS("RW"),
4353: .RESVAL (2'h0)
4354: ) u_prio15 (
4355: .clk_i (clk_i ),
4356: .rst_ni (rst_ni ),
4357:
4358: // from register interface
4359: .we (prio15_we),
4360: .wd (prio15_wd),
4361:
4362: // from internal hardware
4363: .de (1'b0),
4364: .d ('0 ),
4365:
4366: // to internal hardware
4367: .qe (),
4368: .q (reg2hw.prio15.q ),
4369:
4370: // to register interface (read)
4371: .qs (prio15_qs)
4372: );
4373:
4374:
4375: // R[prio16]: V(False)
4376:
4377: prim_subreg #(
4378: .DW (2),
4379: .SWACCESS("RW"),
4380: .RESVAL (2'h0)
4381: ) u_prio16 (
4382: .clk_i (clk_i ),
4383: .rst_ni (rst_ni ),
4384:
4385: // from register interface
4386: .we (prio16_we),
4387: .wd (prio16_wd),
4388:
4389: // from internal hardware
4390: .de (1'b0),
4391: .d ('0 ),
4392:
4393: // to internal hardware
4394: .qe (),
4395: .q (reg2hw.prio16.q ),
4396:
4397: // to register interface (read)
4398: .qs (prio16_qs)
4399: );
4400:
4401:
4402: // R[prio17]: V(False)
4403:
4404: prim_subreg #(
4405: .DW (2),
4406: .SWACCESS("RW"),
4407: .RESVAL (2'h0)
4408: ) u_prio17 (
4409: .clk_i (clk_i ),
4410: .rst_ni (rst_ni ),
4411:
4412: // from register interface
4413: .we (prio17_we),
4414: .wd (prio17_wd),
4415:
4416: // from internal hardware
4417: .de (1'b0),
4418: .d ('0 ),
4419:
4420: // to internal hardware
4421: .qe (),
4422: .q (reg2hw.prio17.q ),
4423:
4424: // to register interface (read)
4425: .qs (prio17_qs)
4426: );
4427:
4428:
4429: // R[prio18]: V(False)
4430:
4431: prim_subreg #(
4432: .DW (2),
4433: .SWACCESS("RW"),
4434: .RESVAL (2'h0)
4435: ) u_prio18 (
4436: .clk_i (clk_i ),
4437: .rst_ni (rst_ni ),
4438:
4439: // from register interface
4440: .we (prio18_we),
4441: .wd (prio18_wd),
4442:
4443: // from internal hardware
4444: .de (1'b0),
4445: .d ('0 ),
4446:
4447: // to internal hardware
4448: .qe (),
4449: .q (reg2hw.prio18.q ),
4450:
4451: // to register interface (read)
4452: .qs (prio18_qs)
4453: );
4454:
4455:
4456: // R[prio19]: V(False)
4457:
4458: prim_subreg #(
4459: .DW (2),
4460: .SWACCESS("RW"),
4461: .RESVAL (2'h0)
4462: ) u_prio19 (
4463: .clk_i (clk_i ),
4464: .rst_ni (rst_ni ),
4465:
4466: // from register interface
4467: .we (prio19_we),
4468: .wd (prio19_wd),
4469:
4470: // from internal hardware
4471: .de (1'b0),
4472: .d ('0 ),
4473:
4474: // to internal hardware
4475: .qe (),
4476: .q (reg2hw.prio19.q ),
4477:
4478: // to register interface (read)
4479: .qs (prio19_qs)
4480: );
4481:
4482:
4483: // R[prio20]: V(False)
4484:
4485: prim_subreg #(
4486: .DW (2),
4487: .SWACCESS("RW"),
4488: .RESVAL (2'h0)
4489: ) u_prio20 (
4490: .clk_i (clk_i ),
4491: .rst_ni (rst_ni ),
4492:
4493: // from register interface
4494: .we (prio20_we),
4495: .wd (prio20_wd),
4496:
4497: // from internal hardware
4498: .de (1'b0),
4499: .d ('0 ),
4500:
4501: // to internal hardware
4502: .qe (),
4503: .q (reg2hw.prio20.q ),
4504:
4505: // to register interface (read)
4506: .qs (prio20_qs)
4507: );
4508:
4509:
4510: // R[prio21]: V(False)
4511:
4512: prim_subreg #(
4513: .DW (2),
4514: .SWACCESS("RW"),
4515: .RESVAL (2'h0)
4516: ) u_prio21 (
4517: .clk_i (clk_i ),
4518: .rst_ni (rst_ni ),
4519:
4520: // from register interface
4521: .we (prio21_we),
4522: .wd (prio21_wd),
4523:
4524: // from internal hardware
4525: .de (1'b0),
4526: .d ('0 ),
4527:
4528: // to internal hardware
4529: .qe (),
4530: .q (reg2hw.prio21.q ),
4531:
4532: // to register interface (read)
4533: .qs (prio21_qs)
4534: );
4535:
4536:
4537: // R[prio22]: V(False)
4538:
4539: prim_subreg #(
4540: .DW (2),
4541: .SWACCESS("RW"),
4542: .RESVAL (2'h0)
4543: ) u_prio22 (
4544: .clk_i (clk_i ),
4545: .rst_ni (rst_ni ),
4546:
4547: // from register interface
4548: .we (prio22_we),
4549: .wd (prio22_wd),
4550:
4551: // from internal hardware
4552: .de (1'b0),
4553: .d ('0 ),
4554:
4555: // to internal hardware
4556: .qe (),
4557: .q (reg2hw.prio22.q ),
4558:
4559: // to register interface (read)
4560: .qs (prio22_qs)
4561: );
4562:
4563:
4564: // R[prio23]: V(False)
4565:
4566: prim_subreg #(
4567: .DW (2),
4568: .SWACCESS("RW"),
4569: .RESVAL (2'h0)
4570: ) u_prio23 (
4571: .clk_i (clk_i ),
4572: .rst_ni (rst_ni ),
4573:
4574: // from register interface
4575: .we (prio23_we),
4576: .wd (prio23_wd),
4577:
4578: // from internal hardware
4579: .de (1'b0),
4580: .d ('0 ),
4581:
4582: // to internal hardware
4583: .qe (),
4584: .q (reg2hw.prio23.q ),
4585:
4586: // to register interface (read)
4587: .qs (prio23_qs)
4588: );
4589:
4590:
4591: // R[prio24]: V(False)
4592:
4593: prim_subreg #(
4594: .DW (2),
4595: .SWACCESS("RW"),
4596: .RESVAL (2'h0)
4597: ) u_prio24 (
4598: .clk_i (clk_i ),
4599: .rst_ni (rst_ni ),
4600:
4601: // from register interface
4602: .we (prio24_we),
4603: .wd (prio24_wd),
4604:
4605: // from internal hardware
4606: .de (1'b0),
4607: .d ('0 ),
4608:
4609: // to internal hardware
4610: .qe (),
4611: .q (reg2hw.prio24.q ),
4612:
4613: // to register interface (read)
4614: .qs (prio24_qs)
4615: );
4616:
4617:
4618: // R[prio25]: V(False)
4619:
4620: prim_subreg #(
4621: .DW (2),
4622: .SWACCESS("RW"),
4623: .RESVAL (2'h0)
4624: ) u_prio25 (
4625: .clk_i (clk_i ),
4626: .rst_ni (rst_ni ),
4627:
4628: // from register interface
4629: .we (prio25_we),
4630: .wd (prio25_wd),
4631:
4632: // from internal hardware
4633: .de (1'b0),
4634: .d ('0 ),
4635:
4636: // to internal hardware
4637: .qe (),
4638: .q (reg2hw.prio25.q ),
4639:
4640: // to register interface (read)
4641: .qs (prio25_qs)
4642: );
4643:
4644:
4645: // R[prio26]: V(False)
4646:
4647: prim_subreg #(
4648: .DW (2),
4649: .SWACCESS("RW"),
4650: .RESVAL (2'h0)
4651: ) u_prio26 (
4652: .clk_i (clk_i ),
4653: .rst_ni (rst_ni ),
4654:
4655: // from register interface
4656: .we (prio26_we),
4657: .wd (prio26_wd),
4658:
4659: // from internal hardware
4660: .de (1'b0),
4661: .d ('0 ),
4662:
4663: // to internal hardware
4664: .qe (),
4665: .q (reg2hw.prio26.q ),
4666:
4667: // to register interface (read)
4668: .qs (prio26_qs)
4669: );
4670:
4671:
4672: // R[prio27]: V(False)
4673:
4674: prim_subreg #(
4675: .DW (2),
4676: .SWACCESS("RW"),
4677: .RESVAL (2'h0)
4678: ) u_prio27 (
4679: .clk_i (clk_i ),
4680: .rst_ni (rst_ni ),
4681:
4682: // from register interface
4683: .we (prio27_we),
4684: .wd (prio27_wd),
4685:
4686: // from internal hardware
4687: .de (1'b0),
4688: .d ('0 ),
4689:
4690: // to internal hardware
4691: .qe (),
4692: .q (reg2hw.prio27.q ),
4693:
4694: // to register interface (read)
4695: .qs (prio27_qs)
4696: );
4697:
4698:
4699: // R[prio28]: V(False)
4700:
4701: prim_subreg #(
4702: .DW (2),
4703: .SWACCESS("RW"),
4704: .RESVAL (2'h0)
4705: ) u_prio28 (
4706: .clk_i (clk_i ),
4707: .rst_ni (rst_ni ),
4708:
4709: // from register interface
4710: .we (prio28_we),
4711: .wd (prio28_wd),
4712:
4713: // from internal hardware
4714: .de (1'b0),
4715: .d ('0 ),
4716:
4717: // to internal hardware
4718: .qe (),
4719: .q (reg2hw.prio28.q ),
4720:
4721: // to register interface (read)
4722: .qs (prio28_qs)
4723: );
4724:
4725:
4726: // R[prio29]: V(False)
4727:
4728: prim_subreg #(
4729: .DW (2),
4730: .SWACCESS("RW"),
4731: .RESVAL (2'h0)
4732: ) u_prio29 (
4733: .clk_i (clk_i ),
4734: .rst_ni (rst_ni ),
4735:
4736: // from register interface
4737: .we (prio29_we),
4738: .wd (prio29_wd),
4739:
4740: // from internal hardware
4741: .de (1'b0),
4742: .d ('0 ),
4743:
4744: // to internal hardware
4745: .qe (),
4746: .q (reg2hw.prio29.q ),
4747:
4748: // to register interface (read)
4749: .qs (prio29_qs)
4750: );
4751:
4752:
4753: // R[prio30]: V(False)
4754:
4755: prim_subreg #(
4756: .DW (2),
4757: .SWACCESS("RW"),
4758: .RESVAL (2'h0)
4759: ) u_prio30 (
4760: .clk_i (clk_i ),
4761: .rst_ni (rst_ni ),
4762:
4763: // from register interface
4764: .we (prio30_we),
4765: .wd (prio30_wd),
4766:
4767: // from internal hardware
4768: .de (1'b0),
4769: .d ('0 ),
4770:
4771: // to internal hardware
4772: .qe (),
4773: .q (reg2hw.prio30.q ),
4774:
4775: // to register interface (read)
4776: .qs (prio30_qs)
4777: );
4778:
4779:
4780: // R[prio31]: V(False)
4781:
4782: prim_subreg #(
4783: .DW (2),
4784: .SWACCESS("RW"),
4785: .RESVAL (2'h0)
4786: ) u_prio31 (
4787: .clk_i (clk_i ),
4788: .rst_ni (rst_ni ),
4789:
4790: // from register interface
4791: .we (prio31_we),
4792: .wd (prio31_wd),
4793:
4794: // from internal hardware
4795: .de (1'b0),
4796: .d ('0 ),
4797:
4798: // to internal hardware
4799: .qe (),
4800: .q (reg2hw.prio31.q ),
4801:
4802: // to register interface (read)
4803: .qs (prio31_qs)
4804: );
4805:
4806:
4807: // R[prio32]: V(False)
4808:
4809: prim_subreg #(
4810: .DW (2),
4811: .SWACCESS("RW"),
4812: .RESVAL (2'h0)
4813: ) u_prio32 (
4814: .clk_i (clk_i ),
4815: .rst_ni (rst_ni ),
4816:
4817: // from register interface
4818: .we (prio32_we),
4819: .wd (prio32_wd),
4820:
4821: // from internal hardware
4822: .de (1'b0),
4823: .d ('0 ),
4824:
4825: // to internal hardware
4826: .qe (),
4827: .q (reg2hw.prio32.q ),
4828:
4829: // to register interface (read)
4830: .qs (prio32_qs)
4831: );
4832:
4833:
4834: // R[prio33]: V(False)
4835:
4836: prim_subreg #(
4837: .DW (2),
4838: .SWACCESS("RW"),
4839: .RESVAL (2'h0)
4840: ) u_prio33 (
4841: .clk_i (clk_i ),
4842: .rst_ni (rst_ni ),
4843:
4844: // from register interface
4845: .we (prio33_we),
4846: .wd (prio33_wd),
4847:
4848: // from internal hardware
4849: .de (1'b0),
4850: .d ('0 ),
4851:
4852: // to internal hardware
4853: .qe (),
4854: .q (reg2hw.prio33.q ),
4855:
4856: // to register interface (read)
4857: .qs (prio33_qs)
4858: );
4859:
4860:
4861: // R[prio34]: V(False)
4862:
4863: prim_subreg #(
4864: .DW (2),
4865: .SWACCESS("RW"),
4866: .RESVAL (2'h0)
4867: ) u_prio34 (
4868: .clk_i (clk_i ),
4869: .rst_ni (rst_ni ),
4870:
4871: // from register interface
4872: .we (prio34_we),
4873: .wd (prio34_wd),
4874:
4875: // from internal hardware
4876: .de (1'b0),
4877: .d ('0 ),
4878:
4879: // to internal hardware
4880: .qe (),
4881: .q (reg2hw.prio34.q ),
4882:
4883: // to register interface (read)
4884: .qs (prio34_qs)
4885: );
4886:
4887:
4888: // R[prio35]: V(False)
4889:
4890: prim_subreg #(
4891: .DW (2),
4892: .SWACCESS("RW"),
4893: .RESVAL (2'h0)
4894: ) u_prio35 (
4895: .clk_i (clk_i ),
4896: .rst_ni (rst_ni ),
4897:
4898: // from register interface
4899: .we (prio35_we),
4900: .wd (prio35_wd),
4901:
4902: // from internal hardware
4903: .de (1'b0),
4904: .d ('0 ),
4905:
4906: // to internal hardware
4907: .qe (),
4908: .q (reg2hw.prio35.q ),
4909:
4910: // to register interface (read)
4911: .qs (prio35_qs)
4912: );
4913:
4914:
4915: // R[prio36]: V(False)
4916:
4917: prim_subreg #(
4918: .DW (2),
4919: .SWACCESS("RW"),
4920: .RESVAL (2'h0)
4921: ) u_prio36 (
4922: .clk_i (clk_i ),
4923: .rst_ni (rst_ni ),
4924:
4925: // from register interface
4926: .we (prio36_we),
4927: .wd (prio36_wd),
4928:
4929: // from internal hardware
4930: .de (1'b0),
4931: .d ('0 ),
4932:
4933: // to internal hardware
4934: .qe (),
4935: .q (reg2hw.prio36.q ),
4936:
4937: // to register interface (read)
4938: .qs (prio36_qs)
4939: );
4940:
4941:
4942: // R[prio37]: V(False)
4943:
4944: prim_subreg #(
4945: .DW (2),
4946: .SWACCESS("RW"),
4947: .RESVAL (2'h0)
4948: ) u_prio37 (
4949: .clk_i (clk_i ),
4950: .rst_ni (rst_ni ),
4951:
4952: // from register interface
4953: .we (prio37_we),
4954: .wd (prio37_wd),
4955:
4956: // from internal hardware
4957: .de (1'b0),
4958: .d ('0 ),
4959:
4960: // to internal hardware
4961: .qe (),
4962: .q (reg2hw.prio37.q ),
4963:
4964: // to register interface (read)
4965: .qs (prio37_qs)
4966: );
4967:
4968:
4969: // R[prio38]: V(False)
4970:
4971: prim_subreg #(
4972: .DW (2),
4973: .SWACCESS("RW"),
4974: .RESVAL (2'h0)
4975: ) u_prio38 (
4976: .clk_i (clk_i ),
4977: .rst_ni (rst_ni ),
4978:
4979: // from register interface
4980: .we (prio38_we),
4981: .wd (prio38_wd),
4982:
4983: // from internal hardware
4984: .de (1'b0),
4985: .d ('0 ),
4986:
4987: // to internal hardware
4988: .qe (),
4989: .q (reg2hw.prio38.q ),
4990:
4991: // to register interface (read)
4992: .qs (prio38_qs)
4993: );
4994:
4995:
4996: // R[prio39]: V(False)
4997:
4998: prim_subreg #(
4999: .DW (2),
5000: .SWACCESS("RW"),
5001: .RESVAL (2'h0)
5002: ) u_prio39 (
5003: .clk_i (clk_i ),
5004: .rst_ni (rst_ni ),
5005:
5006: // from register interface
5007: .we (prio39_we),
5008: .wd (prio39_wd),
5009:
5010: // from internal hardware
5011: .de (1'b0),
5012: .d ('0 ),
5013:
5014: // to internal hardware
5015: .qe (),
5016: .q (reg2hw.prio39.q ),
5017:
5018: // to register interface (read)
5019: .qs (prio39_qs)
5020: );
5021:
5022:
5023: // R[prio40]: V(False)
5024:
5025: prim_subreg #(
5026: .DW (2),
5027: .SWACCESS("RW"),
5028: .RESVAL (2'h0)
5029: ) u_prio40 (
5030: .clk_i (clk_i ),
5031: .rst_ni (rst_ni ),
5032:
5033: // from register interface
5034: .we (prio40_we),
5035: .wd (prio40_wd),
5036:
5037: // from internal hardware
5038: .de (1'b0),
5039: .d ('0 ),
5040:
5041: // to internal hardware
5042: .qe (),
5043: .q (reg2hw.prio40.q ),
5044:
5045: // to register interface (read)
5046: .qs (prio40_qs)
5047: );
5048:
5049:
5050: // R[prio41]: V(False)
5051:
5052: prim_subreg #(
5053: .DW (2),
5054: .SWACCESS("RW"),
5055: .RESVAL (2'h0)
5056: ) u_prio41 (
5057: .clk_i (clk_i ),
5058: .rst_ni (rst_ni ),
5059:
5060: // from register interface
5061: .we (prio41_we),
5062: .wd (prio41_wd),
5063:
5064: // from internal hardware
5065: .de (1'b0),
5066: .d ('0 ),
5067:
5068: // to internal hardware
5069: .qe (),
5070: .q (reg2hw.prio41.q ),
5071:
5072: // to register interface (read)
5073: .qs (prio41_qs)
5074: );
5075:
5076:
5077: // R[prio42]: V(False)
5078:
5079: prim_subreg #(
5080: .DW (2),
5081: .SWACCESS("RW"),
5082: .RESVAL (2'h0)
5083: ) u_prio42 (
5084: .clk_i (clk_i ),
5085: .rst_ni (rst_ni ),
5086:
5087: // from register interface
5088: .we (prio42_we),
5089: .wd (prio42_wd),
5090:
5091: // from internal hardware
5092: .de (1'b0),
5093: .d ('0 ),
5094:
5095: // to internal hardware
5096: .qe (),
5097: .q (reg2hw.prio42.q ),
5098:
5099: // to register interface (read)
5100: .qs (prio42_qs)
5101: );
5102:
5103:
5104: // R[prio43]: V(False)
5105:
5106: prim_subreg #(
5107: .DW (2),
5108: .SWACCESS("RW"),
5109: .RESVAL (2'h0)
5110: ) u_prio43 (
5111: .clk_i (clk_i ),
5112: .rst_ni (rst_ni ),
5113:
5114: // from register interface
5115: .we (prio43_we),
5116: .wd (prio43_wd),
5117:
5118: // from internal hardware
5119: .de (1'b0),
5120: .d ('0 ),
5121:
5122: // to internal hardware
5123: .qe (),
5124: .q (reg2hw.prio43.q ),
5125:
5126: // to register interface (read)
5127: .qs (prio43_qs)
5128: );
5129:
5130:
5131: // R[prio44]: V(False)
5132:
5133: prim_subreg #(
5134: .DW (2),
5135: .SWACCESS("RW"),
5136: .RESVAL (2'h0)
5137: ) u_prio44 (
5138: .clk_i (clk_i ),
5139: .rst_ni (rst_ni ),
5140:
5141: // from register interface
5142: .we (prio44_we),
5143: .wd (prio44_wd),
5144:
5145: // from internal hardware
5146: .de (1'b0),
5147: .d ('0 ),
5148:
5149: // to internal hardware
5150: .qe (),
5151: .q (reg2hw.prio44.q ),
5152:
5153: // to register interface (read)
5154: .qs (prio44_qs)
5155: );
5156:
5157:
5158: // R[prio45]: V(False)
5159:
5160: prim_subreg #(
5161: .DW (2),
5162: .SWACCESS("RW"),
5163: .RESVAL (2'h0)
5164: ) u_prio45 (
5165: .clk_i (clk_i ),
5166: .rst_ni (rst_ni ),
5167:
5168: // from register interface
5169: .we (prio45_we),
5170: .wd (prio45_wd),
5171:
5172: // from internal hardware
5173: .de (1'b0),
5174: .d ('0 ),
5175:
5176: // to internal hardware
5177: .qe (),
5178: .q (reg2hw.prio45.q ),
5179:
5180: // to register interface (read)
5181: .qs (prio45_qs)
5182: );
5183:
5184:
5185: // R[prio46]: V(False)
5186:
5187: prim_subreg #(
5188: .DW (2),
5189: .SWACCESS("RW"),
5190: .RESVAL (2'h0)
5191: ) u_prio46 (
5192: .clk_i (clk_i ),
5193: .rst_ni (rst_ni ),
5194:
5195: // from register interface
5196: .we (prio46_we),
5197: .wd (prio46_wd),
5198:
5199: // from internal hardware
5200: .de (1'b0),
5201: .d ('0 ),
5202:
5203: // to internal hardware
5204: .qe (),
5205: .q (reg2hw.prio46.q ),
5206:
5207: // to register interface (read)
5208: .qs (prio46_qs)
5209: );
5210:
5211:
5212: // R[prio47]: V(False)
5213:
5214: prim_subreg #(
5215: .DW (2),
5216: .SWACCESS("RW"),
5217: .RESVAL (2'h0)
5218: ) u_prio47 (
5219: .clk_i (clk_i ),
5220: .rst_ni (rst_ni ),
5221:
5222: // from register interface
5223: .we (prio47_we),
5224: .wd (prio47_wd),
5225:
5226: // from internal hardware
5227: .de (1'b0),
5228: .d ('0 ),
5229:
5230: // to internal hardware
5231: .qe (),
5232: .q (reg2hw.prio47.q ),
5233:
5234: // to register interface (read)
5235: .qs (prio47_qs)
5236: );
5237:
5238:
5239: // R[prio48]: V(False)
5240:
5241: prim_subreg #(
5242: .DW (2),
5243: .SWACCESS("RW"),
5244: .RESVAL (2'h0)
5245: ) u_prio48 (
5246: .clk_i (clk_i ),
5247: .rst_ni (rst_ni ),
5248:
5249: // from register interface
5250: .we (prio48_we),
5251: .wd (prio48_wd),
5252:
5253: // from internal hardware
5254: .de (1'b0),
5255: .d ('0 ),
5256:
5257: // to internal hardware
5258: .qe (),
5259: .q (reg2hw.prio48.q ),
5260:
5261: // to register interface (read)
5262: .qs (prio48_qs)
5263: );
5264:
5265:
5266: // R[prio49]: V(False)
5267:
5268: prim_subreg #(
5269: .DW (2),
5270: .SWACCESS("RW"),
5271: .RESVAL (2'h0)
5272: ) u_prio49 (
5273: .clk_i (clk_i ),
5274: .rst_ni (rst_ni ),
5275:
5276: // from register interface
5277: .we (prio49_we),
5278: .wd (prio49_wd),
5279:
5280: // from internal hardware
5281: .de (1'b0),
5282: .d ('0 ),
5283:
5284: // to internal hardware
5285: .qe (),
5286: .q (reg2hw.prio49.q ),
5287:
5288: // to register interface (read)
5289: .qs (prio49_qs)
5290: );
5291:
5292:
5293: // R[prio50]: V(False)
5294:
5295: prim_subreg #(
5296: .DW (2),
5297: .SWACCESS("RW"),
5298: .RESVAL (2'h0)
5299: ) u_prio50 (
5300: .clk_i (clk_i ),
5301: .rst_ni (rst_ni ),
5302:
5303: // from register interface
5304: .we (prio50_we),
5305: .wd (prio50_wd),
5306:
5307: // from internal hardware
5308: .de (1'b0),
5309: .d ('0 ),
5310:
5311: // to internal hardware
5312: .qe (),
5313: .q (reg2hw.prio50.q ),
5314:
5315: // to register interface (read)
5316: .qs (prio50_qs)
5317: );
5318:
5319:
5320: // R[prio51]: V(False)
5321:
5322: prim_subreg #(
5323: .DW (2),
5324: .SWACCESS("RW"),
5325: .RESVAL (2'h0)
5326: ) u_prio51 (
5327: .clk_i (clk_i ),
5328: .rst_ni (rst_ni ),
5329:
5330: // from register interface
5331: .we (prio51_we),
5332: .wd (prio51_wd),
5333:
5334: // from internal hardware
5335: .de (1'b0),
5336: .d ('0 ),
5337:
5338: // to internal hardware
5339: .qe (),
5340: .q (reg2hw.prio51.q ),
5341:
5342: // to register interface (read)
5343: .qs (prio51_qs)
5344: );
5345:
5346:
5347: // R[prio52]: V(False)
5348:
5349: prim_subreg #(
5350: .DW (2),
5351: .SWACCESS("RW"),
5352: .RESVAL (2'h0)
5353: ) u_prio52 (
5354: .clk_i (clk_i ),
5355: .rst_ni (rst_ni ),
5356:
5357: // from register interface
5358: .we (prio52_we),
5359: .wd (prio52_wd),
5360:
5361: // from internal hardware
5362: .de (1'b0),
5363: .d ('0 ),
5364:
5365: // to internal hardware
5366: .qe (),
5367: .q (reg2hw.prio52.q ),
5368:
5369: // to register interface (read)
5370: .qs (prio52_qs)
5371: );
5372:
5373:
5374: // R[prio53]: V(False)
5375:
5376: prim_subreg #(
5377: .DW (2),
5378: .SWACCESS("RW"),
5379: .RESVAL (2'h0)
5380: ) u_prio53 (
5381: .clk_i (clk_i ),
5382: .rst_ni (rst_ni ),
5383:
5384: // from register interface
5385: .we (prio53_we),
5386: .wd (prio53_wd),
5387:
5388: // from internal hardware
5389: .de (1'b0),
5390: .d ('0 ),
5391:
5392: // to internal hardware
5393: .qe (),
5394: .q (reg2hw.prio53.q ),
5395:
5396: // to register interface (read)
5397: .qs (prio53_qs)
5398: );
5399:
5400:
5401: // R[prio54]: V(False)
5402:
5403: prim_subreg #(
5404: .DW (2),
5405: .SWACCESS("RW"),
5406: .RESVAL (2'h0)
5407: ) u_prio54 (
5408: .clk_i (clk_i ),
5409: .rst_ni (rst_ni ),
5410:
5411: // from register interface
5412: .we (prio54_we),
5413: .wd (prio54_wd),
5414:
5415: // from internal hardware
5416: .de (1'b0),
5417: .d ('0 ),
5418:
5419: // to internal hardware
5420: .qe (),
5421: .q (reg2hw.prio54.q ),
5422:
5423: // to register interface (read)
5424: .qs (prio54_qs)
5425: );
5426:
5427:
5428: // R[prio55]: V(False)
5429:
5430: prim_subreg #(
5431: .DW (2),
5432: .SWACCESS("RW"),
5433: .RESVAL (2'h0)
5434: ) u_prio55 (
5435: .clk_i (clk_i ),
5436: .rst_ni (rst_ni ),
5437:
5438: // from register interface
5439: .we (prio55_we),
5440: .wd (prio55_wd),
5441:
5442: // from internal hardware
5443: .de (1'b0),
5444: .d ('0 ),
5445:
5446: // to internal hardware
5447: .qe (),
5448: .q (reg2hw.prio55.q ),
5449:
5450: // to register interface (read)
5451: .qs (prio55_qs)
5452: );
5453:
5454:
5455: // R[prio56]: V(False)
5456:
5457: prim_subreg #(
5458: .DW (2),
5459: .SWACCESS("RW"),
5460: .RESVAL (2'h0)
5461: ) u_prio56 (
5462: .clk_i (clk_i ),
5463: .rst_ni (rst_ni ),
5464:
5465: // from register interface
5466: .we (prio56_we),
5467: .wd (prio56_wd),
5468:
5469: // from internal hardware
5470: .de (1'b0),
5471: .d ('0 ),
5472:
5473: // to internal hardware
5474: .qe (),
5475: .q (reg2hw.prio56.q ),
5476:
5477: // to register interface (read)
5478: .qs (prio56_qs)
5479: );
5480:
5481:
5482: // R[prio57]: V(False)
5483:
5484: prim_subreg #(
5485: .DW (2),
5486: .SWACCESS("RW"),
5487: .RESVAL (2'h0)
5488: ) u_prio57 (
5489: .clk_i (clk_i ),
5490: .rst_ni (rst_ni ),
5491:
5492: // from register interface
5493: .we (prio57_we),
5494: .wd (prio57_wd),
5495:
5496: // from internal hardware
5497: .de (1'b0),
5498: .d ('0 ),
5499:
5500: // to internal hardware
5501: .qe (),
5502: .q (reg2hw.prio57.q ),
5503:
5504: // to register interface (read)
5505: .qs (prio57_qs)
5506: );
5507:
5508:
5509: // R[prio58]: V(False)
5510:
5511: prim_subreg #(
5512: .DW (2),
5513: .SWACCESS("RW"),
5514: .RESVAL (2'h0)
5515: ) u_prio58 (
5516: .clk_i (clk_i ),
5517: .rst_ni (rst_ni ),
5518:
5519: // from register interface
5520: .we (prio58_we),
5521: .wd (prio58_wd),
5522:
5523: // from internal hardware
5524: .de (1'b0),
5525: .d ('0 ),
5526:
5527: // to internal hardware
5528: .qe (),
5529: .q (reg2hw.prio58.q ),
5530:
5531: // to register interface (read)
5532: .qs (prio58_qs)
5533: );
5534:
5535:
5536: // R[prio59]: V(False)
5537:
5538: prim_subreg #(
5539: .DW (2),
5540: .SWACCESS("RW"),
5541: .RESVAL (2'h0)
5542: ) u_prio59 (
5543: .clk_i (clk_i ),
5544: .rst_ni (rst_ni ),
5545:
5546: // from register interface
5547: .we (prio59_we),
5548: .wd (prio59_wd),
5549:
5550: // from internal hardware
5551: .de (1'b0),
5552: .d ('0 ),
5553:
5554: // to internal hardware
5555: .qe (),
5556: .q (reg2hw.prio59.q ),
5557:
5558: // to register interface (read)
5559: .qs (prio59_qs)
5560: );
5561:
5562:
5563: // R[prio60]: V(False)
5564:
5565: prim_subreg #(
5566: .DW (2),
5567: .SWACCESS("RW"),
5568: .RESVAL (2'h0)
5569: ) u_prio60 (
5570: .clk_i (clk_i ),
5571: .rst_ni (rst_ni ),
5572:
5573: // from register interface
5574: .we (prio60_we),
5575: .wd (prio60_wd),
5576:
5577: // from internal hardware
5578: .de (1'b0),
5579: .d ('0 ),
5580:
5581: // to internal hardware
5582: .qe (),
5583: .q (reg2hw.prio60.q ),
5584:
5585: // to register interface (read)
5586: .qs (prio60_qs)
5587: );
5588:
5589:
5590: // R[prio61]: V(False)
5591:
5592: prim_subreg #(
5593: .DW (2),
5594: .SWACCESS("RW"),
5595: .RESVAL (2'h0)
5596: ) u_prio61 (
5597: .clk_i (clk_i ),
5598: .rst_ni (rst_ni ),
5599:
5600: // from register interface
5601: .we (prio61_we),
5602: .wd (prio61_wd),
5603:
5604: // from internal hardware
5605: .de (1'b0),
5606: .d ('0 ),
5607:
5608: // to internal hardware
5609: .qe (),
5610: .q (reg2hw.prio61.q ),
5611:
5612: // to register interface (read)
5613: .qs (prio61_qs)
5614: );
5615:
5616:
5617: // R[prio62]: V(False)
5618:
5619: prim_subreg #(
5620: .DW (2),
5621: .SWACCESS("RW"),
5622: .RESVAL (2'h0)
5623: ) u_prio62 (
5624: .clk_i (clk_i ),
5625: .rst_ni (rst_ni ),
5626:
5627: // from register interface
5628: .we (prio62_we),
5629: .wd (prio62_wd),
5630:
5631: // from internal hardware
5632: .de (1'b0),
5633: .d ('0 ),
5634:
5635: // to internal hardware
5636: .qe (),
5637: .q (reg2hw.prio62.q ),
5638:
5639: // to register interface (read)
5640: .qs (prio62_qs)
5641: );
5642:
5643:
5644:
5645: // Subregister 0 of Multireg ie0
5646: // R[ie00]: V(False)
5647:
5648: // F[e0]: 0:0
5649: prim_subreg #(
5650: .DW (1),
5651: .SWACCESS("RW"),
5652: .RESVAL (1'h0)
5653: ) u_ie00_e0 (
5654: .clk_i (clk_i ),
5655: .rst_ni (rst_ni ),
5656:
5657: // from register interface
5658: .we (ie00_e0_we),
5659: .wd (ie00_e0_wd),
5660:
5661: // from internal hardware
5662: .de (1'b0),
5663: .d ('0 ),
5664:
5665: // to internal hardware
5666: .qe (),
5667: .q (reg2hw.ie0[0].q ),
5668:
5669: // to register interface (read)
5670: .qs (ie00_e0_qs)
5671: );
5672:
5673:
5674: // F[e1]: 1:1
5675: prim_subreg #(
5676: .DW (1),
5677: .SWACCESS("RW"),
5678: .RESVAL (1'h0)
5679: ) u_ie00_e1 (
5680: .clk_i (clk_i ),
5681: .rst_ni (rst_ni ),
5682:
5683: // from register interface
5684: .we (ie00_e1_we),
5685: .wd (ie00_e1_wd),
5686:
5687: // from internal hardware
5688: .de (1'b0),
5689: .d ('0 ),
5690:
5691: // to internal hardware
5692: .qe (),
5693: .q (reg2hw.ie0[1].q ),
5694:
5695: // to register interface (read)
5696: .qs (ie00_e1_qs)
5697: );
5698:
5699:
5700: // F[e2]: 2:2
5701: prim_subreg #(
5702: .DW (1),
5703: .SWACCESS("RW"),
5704: .RESVAL (1'h0)
5705: ) u_ie00_e2 (
5706: .clk_i (clk_i ),
5707: .rst_ni (rst_ni ),
5708:
5709: // from register interface
5710: .we (ie00_e2_we),
5711: .wd (ie00_e2_wd),
5712:
5713: // from internal hardware
5714: .de (1'b0),
5715: .d ('0 ),
5716:
5717: // to internal hardware
5718: .qe (),
5719: .q (reg2hw.ie0[2].q ),
5720:
5721: // to register interface (read)
5722: .qs (ie00_e2_qs)
5723: );
5724:
5725:
5726: // F[e3]: 3:3
5727: prim_subreg #(
5728: .DW (1),
5729: .SWACCESS("RW"),
5730: .RESVAL (1'h0)
5731: ) u_ie00_e3 (
5732: .clk_i (clk_i ),
5733: .rst_ni (rst_ni ),
5734:
5735: // from register interface
5736: .we (ie00_e3_we),
5737: .wd (ie00_e3_wd),
5738:
5739: // from internal hardware
5740: .de (1'b0),
5741: .d ('0 ),
5742:
5743: // to internal hardware
5744: .qe (),
5745: .q (reg2hw.ie0[3].q ),
5746:
5747: // to register interface (read)
5748: .qs (ie00_e3_qs)
5749: );
5750:
5751:
5752: // F[e4]: 4:4
5753: prim_subreg #(
5754: .DW (1),
5755: .SWACCESS("RW"),
5756: .RESVAL (1'h0)
5757: ) u_ie00_e4 (
5758: .clk_i (clk_i ),
5759: .rst_ni (rst_ni ),
5760:
5761: // from register interface
5762: .we (ie00_e4_we),
5763: .wd (ie00_e4_wd),
5764:
5765: // from internal hardware
5766: .de (1'b0),
5767: .d ('0 ),
5768:
5769: // to internal hardware
5770: .qe (),
5771: .q (reg2hw.ie0[4].q ),
5772:
5773: // to register interface (read)
5774: .qs (ie00_e4_qs)
5775: );
5776:
5777:
5778: // F[e5]: 5:5
5779: prim_subreg #(
5780: .DW (1),
5781: .SWACCESS("RW"),
5782: .RESVAL (1'h0)
5783: ) u_ie00_e5 (
5784: .clk_i (clk_i ),
5785: .rst_ni (rst_ni ),
5786:
5787: // from register interface
5788: .we (ie00_e5_we),
5789: .wd (ie00_e5_wd),
5790:
5791: // from internal hardware
5792: .de (1'b0),
5793: .d ('0 ),
5794:
5795: // to internal hardware
5796: .qe (),
5797: .q (reg2hw.ie0[5].q ),
5798:
5799: // to register interface (read)
5800: .qs (ie00_e5_qs)
5801: );
5802:
5803:
5804: // F[e6]: 6:6
5805: prim_subreg #(
5806: .DW (1),
5807: .SWACCESS("RW"),
5808: .RESVAL (1'h0)
5809: ) u_ie00_e6 (
5810: .clk_i (clk_i ),
5811: .rst_ni (rst_ni ),
5812:
5813: // from register interface
5814: .we (ie00_e6_we),
5815: .wd (ie00_e6_wd),
5816:
5817: // from internal hardware
5818: .de (1'b0),
5819: .d ('0 ),
5820:
5821: // to internal hardware
5822: .qe (),
5823: .q (reg2hw.ie0[6].q ),
5824:
5825: // to register interface (read)
5826: .qs (ie00_e6_qs)
5827: );
5828:
5829:
5830: // F[e7]: 7:7
5831: prim_subreg #(
5832: .DW (1),
5833: .SWACCESS("RW"),
5834: .RESVAL (1'h0)
5835: ) u_ie00_e7 (
5836: .clk_i (clk_i ),
5837: .rst_ni (rst_ni ),
5838:
5839: // from register interface
5840: .we (ie00_e7_we),
5841: .wd (ie00_e7_wd),
5842:
5843: // from internal hardware
5844: .de (1'b0),
5845: .d ('0 ),
5846:
5847: // to internal hardware
5848: .qe (),
5849: .q (reg2hw.ie0[7].q ),
5850:
5851: // to register interface (read)
5852: .qs (ie00_e7_qs)
5853: );
5854:
5855:
5856: // F[e8]: 8:8
5857: prim_subreg #(
5858: .DW (1),
5859: .SWACCESS("RW"),
5860: .RESVAL (1'h0)
5861: ) u_ie00_e8 (
5862: .clk_i (clk_i ),
5863: .rst_ni (rst_ni ),
5864:
5865: // from register interface
5866: .we (ie00_e8_we),
5867: .wd (ie00_e8_wd),
5868:
5869: // from internal hardware
5870: .de (1'b0),
5871: .d ('0 ),
5872:
5873: // to internal hardware
5874: .qe (),
5875: .q (reg2hw.ie0[8].q ),
5876:
5877: // to register interface (read)
5878: .qs (ie00_e8_qs)
5879: );
5880:
5881:
5882: // F[e9]: 9:9
5883: prim_subreg #(
5884: .DW (1),
5885: .SWACCESS("RW"),
5886: .RESVAL (1'h0)
5887: ) u_ie00_e9 (
5888: .clk_i (clk_i ),
5889: .rst_ni (rst_ni ),
5890:
5891: // from register interface
5892: .we (ie00_e9_we),
5893: .wd (ie00_e9_wd),
5894:
5895: // from internal hardware
5896: .de (1'b0),
5897: .d ('0 ),
5898:
5899: // to internal hardware
5900: .qe (),
5901: .q (reg2hw.ie0[9].q ),
5902:
5903: // to register interface (read)
5904: .qs (ie00_e9_qs)
5905: );
5906:
5907:
5908: // F[e10]: 10:10
5909: prim_subreg #(
5910: .DW (1),
5911: .SWACCESS("RW"),
5912: .RESVAL (1'h0)
5913: ) u_ie00_e10 (
5914: .clk_i (clk_i ),
5915: .rst_ni (rst_ni ),
5916:
5917: // from register interface
5918: .we (ie00_e10_we),
5919: .wd (ie00_e10_wd),
5920:
5921: // from internal hardware
5922: .de (1'b0),
5923: .d ('0 ),
5924:
5925: // to internal hardware
5926: .qe (),
5927: .q (reg2hw.ie0[10].q ),
5928:
5929: // to register interface (read)
5930: .qs (ie00_e10_qs)
5931: );
5932:
5933:
5934: // F[e11]: 11:11
5935: prim_subreg #(
5936: .DW (1),
5937: .SWACCESS("RW"),
5938: .RESVAL (1'h0)
5939: ) u_ie00_e11 (
5940: .clk_i (clk_i ),
5941: .rst_ni (rst_ni ),
5942:
5943: // from register interface
5944: .we (ie00_e11_we),
5945: .wd (ie00_e11_wd),
5946:
5947: // from internal hardware
5948: .de (1'b0),
5949: .d ('0 ),
5950:
5951: // to internal hardware
5952: .qe (),
5953: .q (reg2hw.ie0[11].q ),
5954:
5955: // to register interface (read)
5956: .qs (ie00_e11_qs)
5957: );
5958:
5959:
5960: // F[e12]: 12:12
5961: prim_subreg #(
5962: .DW (1),
5963: .SWACCESS("RW"),
5964: .RESVAL (1'h0)
5965: ) u_ie00_e12 (
5966: .clk_i (clk_i ),
5967: .rst_ni (rst_ni ),
5968:
5969: // from register interface
5970: .we (ie00_e12_we),
5971: .wd (ie00_e12_wd),
5972:
5973: // from internal hardware
5974: .de (1'b0),
5975: .d ('0 ),
5976:
5977: // to internal hardware
5978: .qe (),
5979: .q (reg2hw.ie0[12].q ),
5980:
5981: // to register interface (read)
5982: .qs (ie00_e12_qs)
5983: );
5984:
5985:
5986: // F[e13]: 13:13
5987: prim_subreg #(
5988: .DW (1),
5989: .SWACCESS("RW"),
5990: .RESVAL (1'h0)
5991: ) u_ie00_e13 (
5992: .clk_i (clk_i ),
5993: .rst_ni (rst_ni ),
5994:
5995: // from register interface
5996: .we (ie00_e13_we),
5997: .wd (ie00_e13_wd),
5998:
5999: // from internal hardware
6000: .de (1'b0),
6001: .d ('0 ),
6002:
6003: // to internal hardware
6004: .qe (),
6005: .q (reg2hw.ie0[13].q ),
6006:
6007: // to register interface (read)
6008: .qs (ie00_e13_qs)
6009: );
6010:
6011:
6012: // F[e14]: 14:14
6013: prim_subreg #(
6014: .DW (1),
6015: .SWACCESS("RW"),
6016: .RESVAL (1'h0)
6017: ) u_ie00_e14 (
6018: .clk_i (clk_i ),
6019: .rst_ni (rst_ni ),
6020:
6021: // from register interface
6022: .we (ie00_e14_we),
6023: .wd (ie00_e14_wd),
6024:
6025: // from internal hardware
6026: .de (1'b0),
6027: .d ('0 ),
6028:
6029: // to internal hardware
6030: .qe (),
6031: .q (reg2hw.ie0[14].q ),
6032:
6033: // to register interface (read)
6034: .qs (ie00_e14_qs)
6035: );
6036:
6037:
6038: // F[e15]: 15:15
6039: prim_subreg #(
6040: .DW (1),
6041: .SWACCESS("RW"),
6042: .RESVAL (1'h0)
6043: ) u_ie00_e15 (
6044: .clk_i (clk_i ),
6045: .rst_ni (rst_ni ),
6046:
6047: // from register interface
6048: .we (ie00_e15_we),
6049: .wd (ie00_e15_wd),
6050:
6051: // from internal hardware
6052: .de (1'b0),
6053: .d ('0 ),
6054:
6055: // to internal hardware
6056: .qe (),
6057: .q (reg2hw.ie0[15].q ),
6058:
6059: // to register interface (read)
6060: .qs (ie00_e15_qs)
6061: );
6062:
6063:
6064: // F[e16]: 16:16
6065: prim_subreg #(
6066: .DW (1),
6067: .SWACCESS("RW"),
6068: .RESVAL (1'h0)
6069: ) u_ie00_e16 (
6070: .clk_i (clk_i ),
6071: .rst_ni (rst_ni ),
6072:
6073: // from register interface
6074: .we (ie00_e16_we),
6075: .wd (ie00_e16_wd),
6076:
6077: // from internal hardware
6078: .de (1'b0),
6079: .d ('0 ),
6080:
6081: // to internal hardware
6082: .qe (),
6083: .q (reg2hw.ie0[16].q ),
6084:
6085: // to register interface (read)
6086: .qs (ie00_e16_qs)
6087: );
6088:
6089:
6090: // F[e17]: 17:17
6091: prim_subreg #(
6092: .DW (1),
6093: .SWACCESS("RW"),
6094: .RESVAL (1'h0)
6095: ) u_ie00_e17 (
6096: .clk_i (clk_i ),
6097: .rst_ni (rst_ni ),
6098:
6099: // from register interface
6100: .we (ie00_e17_we),
6101: .wd (ie00_e17_wd),
6102:
6103: // from internal hardware
6104: .de (1'b0),
6105: .d ('0 ),
6106:
6107: // to internal hardware
6108: .qe (),
6109: .q (reg2hw.ie0[17].q ),
6110:
6111: // to register interface (read)
6112: .qs (ie00_e17_qs)
6113: );
6114:
6115:
6116: // F[e18]: 18:18
6117: prim_subreg #(
6118: .DW (1),
6119: .SWACCESS("RW"),
6120: .RESVAL (1'h0)
6121: ) u_ie00_e18 (
6122: .clk_i (clk_i ),
6123: .rst_ni (rst_ni ),
6124:
6125: // from register interface
6126: .we (ie00_e18_we),
6127: .wd (ie00_e18_wd),
6128:
6129: // from internal hardware
6130: .de (1'b0),
6131: .d ('0 ),
6132:
6133: // to internal hardware
6134: .qe (),
6135: .q (reg2hw.ie0[18].q ),
6136:
6137: // to register interface (read)
6138: .qs (ie00_e18_qs)
6139: );
6140:
6141:
6142: // F[e19]: 19:19
6143: prim_subreg #(
6144: .DW (1),
6145: .SWACCESS("RW"),
6146: .RESVAL (1'h0)
6147: ) u_ie00_e19 (
6148: .clk_i (clk_i ),
6149: .rst_ni (rst_ni ),
6150:
6151: // from register interface
6152: .we (ie00_e19_we),
6153: .wd (ie00_e19_wd),
6154:
6155: // from internal hardware
6156: .de (1'b0),
6157: .d ('0 ),
6158:
6159: // to internal hardware
6160: .qe (),
6161: .q (reg2hw.ie0[19].q ),
6162:
6163: // to register interface (read)
6164: .qs (ie00_e19_qs)
6165: );
6166:
6167:
6168: // F[e20]: 20:20
6169: prim_subreg #(
6170: .DW (1),
6171: .SWACCESS("RW"),
6172: .RESVAL (1'h0)
6173: ) u_ie00_e20 (
6174: .clk_i (clk_i ),
6175: .rst_ni (rst_ni ),
6176:
6177: // from register interface
6178: .we (ie00_e20_we),
6179: .wd (ie00_e20_wd),
6180:
6181: // from internal hardware
6182: .de (1'b0),
6183: .d ('0 ),
6184:
6185: // to internal hardware
6186: .qe (),
6187: .q (reg2hw.ie0[20].q ),
6188:
6189: // to register interface (read)
6190: .qs (ie00_e20_qs)
6191: );
6192:
6193:
6194: // F[e21]: 21:21
6195: prim_subreg #(
6196: .DW (1),
6197: .SWACCESS("RW"),
6198: .RESVAL (1'h0)
6199: ) u_ie00_e21 (
6200: .clk_i (clk_i ),
6201: .rst_ni (rst_ni ),
6202:
6203: // from register interface
6204: .we (ie00_e21_we),
6205: .wd (ie00_e21_wd),
6206:
6207: // from internal hardware
6208: .de (1'b0),
6209: .d ('0 ),
6210:
6211: // to internal hardware
6212: .qe (),
6213: .q (reg2hw.ie0[21].q ),
6214:
6215: // to register interface (read)
6216: .qs (ie00_e21_qs)
6217: );
6218:
6219:
6220: // F[e22]: 22:22
6221: prim_subreg #(
6222: .DW (1),
6223: .SWACCESS("RW"),
6224: .RESVAL (1'h0)
6225: ) u_ie00_e22 (
6226: .clk_i (clk_i ),
6227: .rst_ni (rst_ni ),
6228:
6229: // from register interface
6230: .we (ie00_e22_we),
6231: .wd (ie00_e22_wd),
6232:
6233: // from internal hardware
6234: .de (1'b0),
6235: .d ('0 ),
6236:
6237: // to internal hardware
6238: .qe (),
6239: .q (reg2hw.ie0[22].q ),
6240:
6241: // to register interface (read)
6242: .qs (ie00_e22_qs)
6243: );
6244:
6245:
6246: // F[e23]: 23:23
6247: prim_subreg #(
6248: .DW (1),
6249: .SWACCESS("RW"),
6250: .RESVAL (1'h0)
6251: ) u_ie00_e23 (
6252: .clk_i (clk_i ),
6253: .rst_ni (rst_ni ),
6254:
6255: // from register interface
6256: .we (ie00_e23_we),
6257: .wd (ie00_e23_wd),
6258:
6259: // from internal hardware
6260: .de (1'b0),
6261: .d ('0 ),
6262:
6263: // to internal hardware
6264: .qe (),
6265: .q (reg2hw.ie0[23].q ),
6266:
6267: // to register interface (read)
6268: .qs (ie00_e23_qs)
6269: );
6270:
6271:
6272: // F[e24]: 24:24
6273: prim_subreg #(
6274: .DW (1),
6275: .SWACCESS("RW"),
6276: .RESVAL (1'h0)
6277: ) u_ie00_e24 (
6278: .clk_i (clk_i ),
6279: .rst_ni (rst_ni ),
6280:
6281: // from register interface
6282: .we (ie00_e24_we),
6283: .wd (ie00_e24_wd),
6284:
6285: // from internal hardware
6286: .de (1'b0),
6287: .d ('0 ),
6288:
6289: // to internal hardware
6290: .qe (),
6291: .q (reg2hw.ie0[24].q ),
6292:
6293: // to register interface (read)
6294: .qs (ie00_e24_qs)
6295: );
6296:
6297:
6298: // F[e25]: 25:25
6299: prim_subreg #(
6300: .DW (1),
6301: .SWACCESS("RW"),
6302: .RESVAL (1'h0)
6303: ) u_ie00_e25 (
6304: .clk_i (clk_i ),
6305: .rst_ni (rst_ni ),
6306:
6307: // from register interface
6308: .we (ie00_e25_we),
6309: .wd (ie00_e25_wd),
6310:
6311: // from internal hardware
6312: .de (1'b0),
6313: .d ('0 ),
6314:
6315: // to internal hardware
6316: .qe (),
6317: .q (reg2hw.ie0[25].q ),
6318:
6319: // to register interface (read)
6320: .qs (ie00_e25_qs)
6321: );
6322:
6323:
6324: // F[e26]: 26:26
6325: prim_subreg #(
6326: .DW (1),
6327: .SWACCESS("RW"),
6328: .RESVAL (1'h0)
6329: ) u_ie00_e26 (
6330: .clk_i (clk_i ),
6331: .rst_ni (rst_ni ),
6332:
6333: // from register interface
6334: .we (ie00_e26_we),
6335: .wd (ie00_e26_wd),
6336:
6337: // from internal hardware
6338: .de (1'b0),
6339: .d ('0 ),
6340:
6341: // to internal hardware
6342: .qe (),
6343: .q (reg2hw.ie0[26].q ),
6344:
6345: // to register interface (read)
6346: .qs (ie00_e26_qs)
6347: );
6348:
6349:
6350: // F[e27]: 27:27
6351: prim_subreg #(
6352: .DW (1),
6353: .SWACCESS("RW"),
6354: .RESVAL (1'h0)
6355: ) u_ie00_e27 (
6356: .clk_i (clk_i ),
6357: .rst_ni (rst_ni ),
6358:
6359: // from register interface
6360: .we (ie00_e27_we),
6361: .wd (ie00_e27_wd),
6362:
6363: // from internal hardware
6364: .de (1'b0),
6365: .d ('0 ),
6366:
6367: // to internal hardware
6368: .qe (),
6369: .q (reg2hw.ie0[27].q ),
6370:
6371: // to register interface (read)
6372: .qs (ie00_e27_qs)
6373: );
6374:
6375:
6376: // F[e28]: 28:28
6377: prim_subreg #(
6378: .DW (1),
6379: .SWACCESS("RW"),
6380: .RESVAL (1'h0)
6381: ) u_ie00_e28 (
6382: .clk_i (clk_i ),
6383: .rst_ni (rst_ni ),
6384:
6385: // from register interface
6386: .we (ie00_e28_we),
6387: .wd (ie00_e28_wd),
6388:
6389: // from internal hardware
6390: .de (1'b0),
6391: .d ('0 ),
6392:
6393: // to internal hardware
6394: .qe (),
6395: .q (reg2hw.ie0[28].q ),
6396:
6397: // to register interface (read)
6398: .qs (ie00_e28_qs)
6399: );
6400:
6401:
6402: // F[e29]: 29:29
6403: prim_subreg #(
6404: .DW (1),
6405: .SWACCESS("RW"),
6406: .RESVAL (1'h0)
6407: ) u_ie00_e29 (
6408: .clk_i (clk_i ),
6409: .rst_ni (rst_ni ),
6410:
6411: // from register interface
6412: .we (ie00_e29_we),
6413: .wd (ie00_e29_wd),
6414:
6415: // from internal hardware
6416: .de (1'b0),
6417: .d ('0 ),
6418:
6419: // to internal hardware
6420: .qe (),
6421: .q (reg2hw.ie0[29].q ),
6422:
6423: // to register interface (read)
6424: .qs (ie00_e29_qs)
6425: );
6426:
6427:
6428: // F[e30]: 30:30
6429: prim_subreg #(
6430: .DW (1),
6431: .SWACCESS("RW"),
6432: .RESVAL (1'h0)
6433: ) u_ie00_e30 (
6434: .clk_i (clk_i ),
6435: .rst_ni (rst_ni ),
6436:
6437: // from register interface
6438: .we (ie00_e30_we),
6439: .wd (ie00_e30_wd),
6440:
6441: // from internal hardware
6442: .de (1'b0),
6443: .d ('0 ),
6444:
6445: // to internal hardware
6446: .qe (),
6447: .q (reg2hw.ie0[30].q ),
6448:
6449: // to register interface (read)
6450: .qs (ie00_e30_qs)
6451: );
6452:
6453:
6454: // F[e31]: 31:31
6455: prim_subreg #(
6456: .DW (1),
6457: .SWACCESS("RW"),
6458: .RESVAL (1'h0)
6459: ) u_ie00_e31 (
6460: .clk_i (clk_i ),
6461: .rst_ni (rst_ni ),
6462:
6463: // from register interface
6464: .we (ie00_e31_we),
6465: .wd (ie00_e31_wd),
6466:
6467: // from internal hardware
6468: .de (1'b0),
6469: .d ('0 ),
6470:
6471: // to internal hardware
6472: .qe (),
6473: .q (reg2hw.ie0[31].q ),
6474:
6475: // to register interface (read)
6476: .qs (ie00_e31_qs)
6477: );
6478:
6479:
6480: // Subregister 32 of Multireg ie0
6481: // R[ie01]: V(False)
6482:
6483: // F[e32]: 0:0
6484: prim_subreg #(
6485: .DW (1),
6486: .SWACCESS("RW"),
6487: .RESVAL (1'h0)
6488: ) u_ie01_e32 (
6489: .clk_i (clk_i ),
6490: .rst_ni (rst_ni ),
6491:
6492: // from register interface
6493: .we (ie01_e32_we),
6494: .wd (ie01_e32_wd),
6495:
6496: // from internal hardware
6497: .de (1'b0),
6498: .d ('0 ),
6499:
6500: // to internal hardware
6501: .qe (),
6502: .q (reg2hw.ie0[32].q ),
6503:
6504: // to register interface (read)
6505: .qs (ie01_e32_qs)
6506: );
6507:
6508:
6509: // F[e33]: 1:1
6510: prim_subreg #(
6511: .DW (1),
6512: .SWACCESS("RW"),
6513: .RESVAL (1'h0)
6514: ) u_ie01_e33 (
6515: .clk_i (clk_i ),
6516: .rst_ni (rst_ni ),
6517:
6518: // from register interface
6519: .we (ie01_e33_we),
6520: .wd (ie01_e33_wd),
6521:
6522: // from internal hardware
6523: .de (1'b0),
6524: .d ('0 ),
6525:
6526: // to internal hardware
6527: .qe (),
6528: .q (reg2hw.ie0[33].q ),
6529:
6530: // to register interface (read)
6531: .qs (ie01_e33_qs)
6532: );
6533:
6534:
6535: // F[e34]: 2:2
6536: prim_subreg #(
6537: .DW (1),
6538: .SWACCESS("RW"),
6539: .RESVAL (1'h0)
6540: ) u_ie01_e34 (
6541: .clk_i (clk_i ),
6542: .rst_ni (rst_ni ),
6543:
6544: // from register interface
6545: .we (ie01_e34_we),
6546: .wd (ie01_e34_wd),
6547:
6548: // from internal hardware
6549: .de (1'b0),
6550: .d ('0 ),
6551:
6552: // to internal hardware
6553: .qe (),
6554: .q (reg2hw.ie0[34].q ),
6555:
6556: // to register interface (read)
6557: .qs (ie01_e34_qs)
6558: );
6559:
6560:
6561: // F[e35]: 3:3
6562: prim_subreg #(
6563: .DW (1),
6564: .SWACCESS("RW"),
6565: .RESVAL (1'h0)
6566: ) u_ie01_e35 (
6567: .clk_i (clk_i ),
6568: .rst_ni (rst_ni ),
6569:
6570: // from register interface
6571: .we (ie01_e35_we),
6572: .wd (ie01_e35_wd),
6573:
6574: // from internal hardware
6575: .de (1'b0),
6576: .d ('0 ),
6577:
6578: // to internal hardware
6579: .qe (),
6580: .q (reg2hw.ie0[35].q ),
6581:
6582: // to register interface (read)
6583: .qs (ie01_e35_qs)
6584: );
6585:
6586:
6587: // F[e36]: 4:4
6588: prim_subreg #(
6589: .DW (1),
6590: .SWACCESS("RW"),
6591: .RESVAL (1'h0)
6592: ) u_ie01_e36 (
6593: .clk_i (clk_i ),
6594: .rst_ni (rst_ni ),
6595:
6596: // from register interface
6597: .we (ie01_e36_we),
6598: .wd (ie01_e36_wd),
6599:
6600: // from internal hardware
6601: .de (1'b0),
6602: .d ('0 ),
6603:
6604: // to internal hardware
6605: .qe (),
6606: .q (reg2hw.ie0[36].q ),
6607:
6608: // to register interface (read)
6609: .qs (ie01_e36_qs)
6610: );
6611:
6612:
6613: // F[e37]: 5:5
6614: prim_subreg #(
6615: .DW (1),
6616: .SWACCESS("RW"),
6617: .RESVAL (1'h0)
6618: ) u_ie01_e37 (
6619: .clk_i (clk_i ),
6620: .rst_ni (rst_ni ),
6621:
6622: // from register interface
6623: .we (ie01_e37_we),
6624: .wd (ie01_e37_wd),
6625:
6626: // from internal hardware
6627: .de (1'b0),
6628: .d ('0 ),
6629:
6630: // to internal hardware
6631: .qe (),
6632: .q (reg2hw.ie0[37].q ),
6633:
6634: // to register interface (read)
6635: .qs (ie01_e37_qs)
6636: );
6637:
6638:
6639: // F[e38]: 6:6
6640: prim_subreg #(
6641: .DW (1),
6642: .SWACCESS("RW"),
6643: .RESVAL (1'h0)
6644: ) u_ie01_e38 (
6645: .clk_i (clk_i ),
6646: .rst_ni (rst_ni ),
6647:
6648: // from register interface
6649: .we (ie01_e38_we),
6650: .wd (ie01_e38_wd),
6651:
6652: // from internal hardware
6653: .de (1'b0),
6654: .d ('0 ),
6655:
6656: // to internal hardware
6657: .qe (),
6658: .q (reg2hw.ie0[38].q ),
6659:
6660: // to register interface (read)
6661: .qs (ie01_e38_qs)
6662: );
6663:
6664:
6665: // F[e39]: 7:7
6666: prim_subreg #(
6667: .DW (1),
6668: .SWACCESS("RW"),
6669: .RESVAL (1'h0)
6670: ) u_ie01_e39 (
6671: .clk_i (clk_i ),
6672: .rst_ni (rst_ni ),
6673:
6674: // from register interface
6675: .we (ie01_e39_we),
6676: .wd (ie01_e39_wd),
6677:
6678: // from internal hardware
6679: .de (1'b0),
6680: .d ('0 ),
6681:
6682: // to internal hardware
6683: .qe (),
6684: .q (reg2hw.ie0[39].q ),
6685:
6686: // to register interface (read)
6687: .qs (ie01_e39_qs)
6688: );
6689:
6690:
6691: // F[e40]: 8:8
6692: prim_subreg #(
6693: .DW (1),
6694: .SWACCESS("RW"),
6695: .RESVAL (1'h0)
6696: ) u_ie01_e40 (
6697: .clk_i (clk_i ),
6698: .rst_ni (rst_ni ),
6699:
6700: // from register interface
6701: .we (ie01_e40_we),
6702: .wd (ie01_e40_wd),
6703:
6704: // from internal hardware
6705: .de (1'b0),
6706: .d ('0 ),
6707:
6708: // to internal hardware
6709: .qe (),
6710: .q (reg2hw.ie0[40].q ),
6711:
6712: // to register interface (read)
6713: .qs (ie01_e40_qs)
6714: );
6715:
6716:
6717: // F[e41]: 9:9
6718: prim_subreg #(
6719: .DW (1),
6720: .SWACCESS("RW"),
6721: .RESVAL (1'h0)
6722: ) u_ie01_e41 (
6723: .clk_i (clk_i ),
6724: .rst_ni (rst_ni ),
6725:
6726: // from register interface
6727: .we (ie01_e41_we),
6728: .wd (ie01_e41_wd),
6729:
6730: // from internal hardware
6731: .de (1'b0),
6732: .d ('0 ),
6733:
6734: // to internal hardware
6735: .qe (),
6736: .q (reg2hw.ie0[41].q ),
6737:
6738: // to register interface (read)
6739: .qs (ie01_e41_qs)
6740: );
6741:
6742:
6743: // F[e42]: 10:10
6744: prim_subreg #(
6745: .DW (1),
6746: .SWACCESS("RW"),
6747: .RESVAL (1'h0)
6748: ) u_ie01_e42 (
6749: .clk_i (clk_i ),
6750: .rst_ni (rst_ni ),
6751:
6752: // from register interface
6753: .we (ie01_e42_we),
6754: .wd (ie01_e42_wd),
6755:
6756: // from internal hardware
6757: .de (1'b0),
6758: .d ('0 ),
6759:
6760: // to internal hardware
6761: .qe (),
6762: .q (reg2hw.ie0[42].q ),
6763:
6764: // to register interface (read)
6765: .qs (ie01_e42_qs)
6766: );
6767:
6768:
6769: // F[e43]: 11:11
6770: prim_subreg #(
6771: .DW (1),
6772: .SWACCESS("RW"),
6773: .RESVAL (1'h0)
6774: ) u_ie01_e43 (
6775: .clk_i (clk_i ),
6776: .rst_ni (rst_ni ),
6777:
6778: // from register interface
6779: .we (ie01_e43_we),
6780: .wd (ie01_e43_wd),
6781:
6782: // from internal hardware
6783: .de (1'b0),
6784: .d ('0 ),
6785:
6786: // to internal hardware
6787: .qe (),
6788: .q (reg2hw.ie0[43].q ),
6789:
6790: // to register interface (read)
6791: .qs (ie01_e43_qs)
6792: );
6793:
6794:
6795: // F[e44]: 12:12
6796: prim_subreg #(
6797: .DW (1),
6798: .SWACCESS("RW"),
6799: .RESVAL (1'h0)
6800: ) u_ie01_e44 (
6801: .clk_i (clk_i ),
6802: .rst_ni (rst_ni ),
6803:
6804: // from register interface
6805: .we (ie01_e44_we),
6806: .wd (ie01_e44_wd),
6807:
6808: // from internal hardware
6809: .de (1'b0),
6810: .d ('0 ),
6811:
6812: // to internal hardware
6813: .qe (),
6814: .q (reg2hw.ie0[44].q ),
6815:
6816: // to register interface (read)
6817: .qs (ie01_e44_qs)
6818: );
6819:
6820:
6821: // F[e45]: 13:13
6822: prim_subreg #(
6823: .DW (1),
6824: .SWACCESS("RW"),
6825: .RESVAL (1'h0)
6826: ) u_ie01_e45 (
6827: .clk_i (clk_i ),
6828: .rst_ni (rst_ni ),
6829:
6830: // from register interface
6831: .we (ie01_e45_we),
6832: .wd (ie01_e45_wd),
6833:
6834: // from internal hardware
6835: .de (1'b0),
6836: .d ('0 ),
6837:
6838: // to internal hardware
6839: .qe (),
6840: .q (reg2hw.ie0[45].q ),
6841:
6842: // to register interface (read)
6843: .qs (ie01_e45_qs)
6844: );
6845:
6846:
6847: // F[e46]: 14:14
6848: prim_subreg #(
6849: .DW (1),
6850: .SWACCESS("RW"),
6851: .RESVAL (1'h0)
6852: ) u_ie01_e46 (
6853: .clk_i (clk_i ),
6854: .rst_ni (rst_ni ),
6855:
6856: // from register interface
6857: .we (ie01_e46_we),
6858: .wd (ie01_e46_wd),
6859:
6860: // from internal hardware
6861: .de (1'b0),
6862: .d ('0 ),
6863:
6864: // to internal hardware
6865: .qe (),
6866: .q (reg2hw.ie0[46].q ),
6867:
6868: // to register interface (read)
6869: .qs (ie01_e46_qs)
6870: );
6871:
6872:
6873: // F[e47]: 15:15
6874: prim_subreg #(
6875: .DW (1),
6876: .SWACCESS("RW"),
6877: .RESVAL (1'h0)
6878: ) u_ie01_e47 (
6879: .clk_i (clk_i ),
6880: .rst_ni (rst_ni ),
6881:
6882: // from register interface
6883: .we (ie01_e47_we),
6884: .wd (ie01_e47_wd),
6885:
6886: // from internal hardware
6887: .de (1'b0),
6888: .d ('0 ),
6889:
6890: // to internal hardware
6891: .qe (),
6892: .q (reg2hw.ie0[47].q ),
6893:
6894: // to register interface (read)
6895: .qs (ie01_e47_qs)
6896: );
6897:
6898:
6899: // F[e48]: 16:16
6900: prim_subreg #(
6901: .DW (1),
6902: .SWACCESS("RW"),
6903: .RESVAL (1'h0)
6904: ) u_ie01_e48 (
6905: .clk_i (clk_i ),
6906: .rst_ni (rst_ni ),
6907:
6908: // from register interface
6909: .we (ie01_e48_we),
6910: .wd (ie01_e48_wd),
6911:
6912: // from internal hardware
6913: .de (1'b0),
6914: .d ('0 ),
6915:
6916: // to internal hardware
6917: .qe (),
6918: .q (reg2hw.ie0[48].q ),
6919:
6920: // to register interface (read)
6921: .qs (ie01_e48_qs)
6922: );
6923:
6924:
6925: // F[e49]: 17:17
6926: prim_subreg #(
6927: .DW (1),
6928: .SWACCESS("RW"),
6929: .RESVAL (1'h0)
6930: ) u_ie01_e49 (
6931: .clk_i (clk_i ),
6932: .rst_ni (rst_ni ),
6933:
6934: // from register interface
6935: .we (ie01_e49_we),
6936: .wd (ie01_e49_wd),
6937:
6938: // from internal hardware
6939: .de (1'b0),
6940: .d ('0 ),
6941:
6942: // to internal hardware
6943: .qe (),
6944: .q (reg2hw.ie0[49].q ),
6945:
6946: // to register interface (read)
6947: .qs (ie01_e49_qs)
6948: );
6949:
6950:
6951: // F[e50]: 18:18
6952: prim_subreg #(
6953: .DW (1),
6954: .SWACCESS("RW"),
6955: .RESVAL (1'h0)
6956: ) u_ie01_e50 (
6957: .clk_i (clk_i ),
6958: .rst_ni (rst_ni ),
6959:
6960: // from register interface
6961: .we (ie01_e50_we),
6962: .wd (ie01_e50_wd),
6963:
6964: // from internal hardware
6965: .de (1'b0),
6966: .d ('0 ),
6967:
6968: // to internal hardware
6969: .qe (),
6970: .q (reg2hw.ie0[50].q ),
6971:
6972: // to register interface (read)
6973: .qs (ie01_e50_qs)
6974: );
6975:
6976:
6977: // F[e51]: 19:19
6978: prim_subreg #(
6979: .DW (1),
6980: .SWACCESS("RW"),
6981: .RESVAL (1'h0)
6982: ) u_ie01_e51 (
6983: .clk_i (clk_i ),
6984: .rst_ni (rst_ni ),
6985:
6986: // from register interface
6987: .we (ie01_e51_we),
6988: .wd (ie01_e51_wd),
6989:
6990: // from internal hardware
6991: .de (1'b0),
6992: .d ('0 ),
6993:
6994: // to internal hardware
6995: .qe (),
6996: .q (reg2hw.ie0[51].q ),
6997:
6998: // to register interface (read)
6999: .qs (ie01_e51_qs)
7000: );
7001:
7002:
7003: // F[e52]: 20:20
7004: prim_subreg #(
7005: .DW (1),
7006: .SWACCESS("RW"),
7007: .RESVAL (1'h0)
7008: ) u_ie01_e52 (
7009: .clk_i (clk_i ),
7010: .rst_ni (rst_ni ),
7011:
7012: // from register interface
7013: .we (ie01_e52_we),
7014: .wd (ie01_e52_wd),
7015:
7016: // from internal hardware
7017: .de (1'b0),
7018: .d ('0 ),
7019:
7020: // to internal hardware
7021: .qe (),
7022: .q (reg2hw.ie0[52].q ),
7023:
7024: // to register interface (read)
7025: .qs (ie01_e52_qs)
7026: );
7027:
7028:
7029: // F[e53]: 21:21
7030: prim_subreg #(
7031: .DW (1),
7032: .SWACCESS("RW"),
7033: .RESVAL (1'h0)
7034: ) u_ie01_e53 (
7035: .clk_i (clk_i ),
7036: .rst_ni (rst_ni ),
7037:
7038: // from register interface
7039: .we (ie01_e53_we),
7040: .wd (ie01_e53_wd),
7041:
7042: // from internal hardware
7043: .de (1'b0),
7044: .d ('0 ),
7045:
7046: // to internal hardware
7047: .qe (),
7048: .q (reg2hw.ie0[53].q ),
7049:
7050: // to register interface (read)
7051: .qs (ie01_e53_qs)
7052: );
7053:
7054:
7055: // F[e54]: 22:22
7056: prim_subreg #(
7057: .DW (1),
7058: .SWACCESS("RW"),
7059: .RESVAL (1'h0)
7060: ) u_ie01_e54 (
7061: .clk_i (clk_i ),
7062: .rst_ni (rst_ni ),
7063:
7064: // from register interface
7065: .we (ie01_e54_we),
7066: .wd (ie01_e54_wd),
7067:
7068: // from internal hardware
7069: .de (1'b0),
7070: .d ('0 ),
7071:
7072: // to internal hardware
7073: .qe (),
7074: .q (reg2hw.ie0[54].q ),
7075:
7076: // to register interface (read)
7077: .qs (ie01_e54_qs)
7078: );
7079:
7080:
7081: // F[e55]: 23:23
7082: prim_subreg #(
7083: .DW (1),
7084: .SWACCESS("RW"),
7085: .RESVAL (1'h0)
7086: ) u_ie01_e55 (
7087: .clk_i (clk_i ),
7088: .rst_ni (rst_ni ),
7089:
7090: // from register interface
7091: .we (ie01_e55_we),
7092: .wd (ie01_e55_wd),
7093:
7094: // from internal hardware
7095: .de (1'b0),
7096: .d ('0 ),
7097:
7098: // to internal hardware
7099: .qe (),
7100: .q (reg2hw.ie0[55].q ),
7101:
7102: // to register interface (read)
7103: .qs (ie01_e55_qs)
7104: );
7105:
7106:
7107: // F[e56]: 24:24
7108: prim_subreg #(
7109: .DW (1),
7110: .SWACCESS("RW"),
7111: .RESVAL (1'h0)
7112: ) u_ie01_e56 (
7113: .clk_i (clk_i ),
7114: .rst_ni (rst_ni ),
7115:
7116: // from register interface
7117: .we (ie01_e56_we),
7118: .wd (ie01_e56_wd),
7119:
7120: // from internal hardware
7121: .de (1'b0),
7122: .d ('0 ),
7123:
7124: // to internal hardware
7125: .qe (),
7126: .q (reg2hw.ie0[56].q ),
7127:
7128: // to register interface (read)
7129: .qs (ie01_e56_qs)
7130: );
7131:
7132:
7133: // F[e57]: 25:25
7134: prim_subreg #(
7135: .DW (1),
7136: .SWACCESS("RW"),
7137: .RESVAL (1'h0)
7138: ) u_ie01_e57 (
7139: .clk_i (clk_i ),
7140: .rst_ni (rst_ni ),
7141:
7142: // from register interface
7143: .we (ie01_e57_we),
7144: .wd (ie01_e57_wd),
7145:
7146: // from internal hardware
7147: .de (1'b0),
7148: .d ('0 ),
7149:
7150: // to internal hardware
7151: .qe (),
7152: .q (reg2hw.ie0[57].q ),
7153:
7154: // to register interface (read)
7155: .qs (ie01_e57_qs)
7156: );
7157:
7158:
7159: // F[e58]: 26:26
7160: prim_subreg #(
7161: .DW (1),
7162: .SWACCESS("RW"),
7163: .RESVAL (1'h0)
7164: ) u_ie01_e58 (
7165: .clk_i (clk_i ),
7166: .rst_ni (rst_ni ),
7167:
7168: // from register interface
7169: .we (ie01_e58_we),
7170: .wd (ie01_e58_wd),
7171:
7172: // from internal hardware
7173: .de (1'b0),
7174: .d ('0 ),
7175:
7176: // to internal hardware
7177: .qe (),
7178: .q (reg2hw.ie0[58].q ),
7179:
7180: // to register interface (read)
7181: .qs (ie01_e58_qs)
7182: );
7183:
7184:
7185: // F[e59]: 27:27
7186: prim_subreg #(
7187: .DW (1),
7188: .SWACCESS("RW"),
7189: .RESVAL (1'h0)
7190: ) u_ie01_e59 (
7191: .clk_i (clk_i ),
7192: .rst_ni (rst_ni ),
7193:
7194: // from register interface
7195: .we (ie01_e59_we),
7196: .wd (ie01_e59_wd),
7197:
7198: // from internal hardware
7199: .de (1'b0),
7200: .d ('0 ),
7201:
7202: // to internal hardware
7203: .qe (),
7204: .q (reg2hw.ie0[59].q ),
7205:
7206: // to register interface (read)
7207: .qs (ie01_e59_qs)
7208: );
7209:
7210:
7211: // F[e60]: 28:28
7212: prim_subreg #(
7213: .DW (1),
7214: .SWACCESS("RW"),
7215: .RESVAL (1'h0)
7216: ) u_ie01_e60 (
7217: .clk_i (clk_i ),
7218: .rst_ni (rst_ni ),
7219:
7220: // from register interface
7221: .we (ie01_e60_we),
7222: .wd (ie01_e60_wd),
7223:
7224: // from internal hardware
7225: .de (1'b0),
7226: .d ('0 ),
7227:
7228: // to internal hardware
7229: .qe (),
7230: .q (reg2hw.ie0[60].q ),
7231:
7232: // to register interface (read)
7233: .qs (ie01_e60_qs)
7234: );
7235:
7236:
7237: // F[e61]: 29:29
7238: prim_subreg #(
7239: .DW (1),
7240: .SWACCESS("RW"),
7241: .RESVAL (1'h0)
7242: ) u_ie01_e61 (
7243: .clk_i (clk_i ),
7244: .rst_ni (rst_ni ),
7245:
7246: // from register interface
7247: .we (ie01_e61_we),
7248: .wd (ie01_e61_wd),
7249:
7250: // from internal hardware
7251: .de (1'b0),
7252: .d ('0 ),
7253:
7254: // to internal hardware
7255: .qe (),
7256: .q (reg2hw.ie0[61].q ),
7257:
7258: // to register interface (read)
7259: .qs (ie01_e61_qs)
7260: );
7261:
7262:
7263: // F[e62]: 30:30
7264: prim_subreg #(
7265: .DW (1),
7266: .SWACCESS("RW"),
7267: .RESVAL (1'h0)
7268: ) u_ie01_e62 (
7269: .clk_i (clk_i ),
7270: .rst_ni (rst_ni ),
7271:
7272: // from register interface
7273: .we (ie01_e62_we),
7274: .wd (ie01_e62_wd),
7275:
7276: // from internal hardware
7277: .de (1'b0),
7278: .d ('0 ),
7279:
7280: // to internal hardware
7281: .qe (),
7282: .q (reg2hw.ie0[62].q ),
7283:
7284: // to register interface (read)
7285: .qs (ie01_e62_qs)
7286: );
7287:
7288:
7289:
7290: // R[threshold0]: V(False)
7291:
7292: prim_subreg #(
7293: .DW (2),
7294: .SWACCESS("RW"),
7295: .RESVAL (2'h0)
7296: ) u_threshold0 (
7297: .clk_i (clk_i ),
7298: .rst_ni (rst_ni ),
7299:
7300: // from register interface
7301: .we (threshold0_we),
7302: .wd (threshold0_wd),
7303:
7304: // from internal hardware
7305: .de (1'b0),
7306: .d ('0 ),
7307:
7308: // to internal hardware
7309: .qe (),
7310: .q (reg2hw.threshold0.q ),
7311:
7312: // to register interface (read)
7313: .qs (threshold0_qs)
7314: );
7315:
7316:
7317: // R[cc0]: V(True)
7318:
7319: prim_subreg_ext #(
7320: .DW (6)
7321: ) u_cc0 (
7322: .re (cc0_re),
7323: .we (cc0_we),
7324: .wd (cc0_wd),
7325: .d (hw2reg.cc0.d),
7326: .qre (reg2hw.cc0.re),
7327: .qe (reg2hw.cc0.qe),
7328: .q (reg2hw.cc0.q ),
7329: .qs (cc0_qs)
7330: );
7331:
7332:
7333: // R[msip0]: V(False)
7334:
7335: prim_subreg #(
7336: .DW (1),
7337: .SWACCESS("RW"),
7338: .RESVAL (1'h0)
7339: ) u_msip0 (
7340: .clk_i (clk_i ),
7341: .rst_ni (rst_ni ),
7342:
7343: // from register interface
7344: .we (msip0_we),
7345: .wd (msip0_wd),
7346:
7347: // from internal hardware
7348: .de (1'b0),
7349: .d ('0 ),
7350:
7351: // to internal hardware
7352: .qe (),
7353: .q (reg2hw.msip0.q ),
7354:
7355: // to register interface (read)
7356: .qs (msip0_qs)
7357: );
7358:
7359:
7360:
7361:
7362: logic [71:0] addr_hit;
7363: always_comb begin
7364: addr_hit = '0;
7365: addr_hit[ 0] = (reg_addr == RV_PLIC_IP0_OFFSET);
7366: addr_hit[ 1] = (reg_addr == RV_PLIC_IP1_OFFSET);
7367: addr_hit[ 2] = (reg_addr == RV_PLIC_LE0_OFFSET);
7368: addr_hit[ 3] = (reg_addr == RV_PLIC_LE1_OFFSET);
7369: addr_hit[ 4] = (reg_addr == RV_PLIC_PRIO0_OFFSET);
7370: addr_hit[ 5] = (reg_addr == RV_PLIC_PRIO1_OFFSET);
7371: addr_hit[ 6] = (reg_addr == RV_PLIC_PRIO2_OFFSET);
7372: addr_hit[ 7] = (reg_addr == RV_PLIC_PRIO3_OFFSET);
7373: addr_hit[ 8] = (reg_addr == RV_PLIC_PRIO4_OFFSET);
7374: addr_hit[ 9] = (reg_addr == RV_PLIC_PRIO5_OFFSET);
7375: addr_hit[10] = (reg_addr == RV_PLIC_PRIO6_OFFSET);
7376: addr_hit[11] = (reg_addr == RV_PLIC_PRIO7_OFFSET);
7377: addr_hit[12] = (reg_addr == RV_PLIC_PRIO8_OFFSET);
7378: addr_hit[13] = (reg_addr == RV_PLIC_PRIO9_OFFSET);
7379: addr_hit[14] = (reg_addr == RV_PLIC_PRIO10_OFFSET);
7380: addr_hit[15] = (reg_addr == RV_PLIC_PRIO11_OFFSET);
7381: addr_hit[16] = (reg_addr == RV_PLIC_PRIO12_OFFSET);
7382: addr_hit[17] = (reg_addr == RV_PLIC_PRIO13_OFFSET);
7383: addr_hit[18] = (reg_addr == RV_PLIC_PRIO14_OFFSET);
7384: addr_hit[19] = (reg_addr == RV_PLIC_PRIO15_OFFSET);
7385: addr_hit[20] = (reg_addr == RV_PLIC_PRIO16_OFFSET);
7386: addr_hit[21] = (reg_addr == RV_PLIC_PRIO17_OFFSET);
7387: addr_hit[22] = (reg_addr == RV_PLIC_PRIO18_OFFSET);
7388: addr_hit[23] = (reg_addr == RV_PLIC_PRIO19_OFFSET);
7389: addr_hit[24] = (reg_addr == RV_PLIC_PRIO20_OFFSET);
7390: addr_hit[25] = (reg_addr == RV_PLIC_PRIO21_OFFSET);
7391: addr_hit[26] = (reg_addr == RV_PLIC_PRIO22_OFFSET);
7392: addr_hit[27] = (reg_addr == RV_PLIC_PRIO23_OFFSET);
7393: addr_hit[28] = (reg_addr == RV_PLIC_PRIO24_OFFSET);
7394: addr_hit[29] = (reg_addr == RV_PLIC_PRIO25_OFFSET);
7395: addr_hit[30] = (reg_addr == RV_PLIC_PRIO26_OFFSET);
7396: addr_hit[31] = (reg_addr == RV_PLIC_PRIO27_OFFSET);
7397: addr_hit[32] = (reg_addr == RV_PLIC_PRIO28_OFFSET);
7398: addr_hit[33] = (reg_addr == RV_PLIC_PRIO29_OFFSET);
7399: addr_hit[34] = (reg_addr == RV_PLIC_PRIO30_OFFSET);
7400: addr_hit[35] = (reg_addr == RV_PLIC_PRIO31_OFFSET);
7401: addr_hit[36] = (reg_addr == RV_PLIC_PRIO32_OFFSET);
7402: addr_hit[37] = (reg_addr == RV_PLIC_PRIO33_OFFSET);
7403: addr_hit[38] = (reg_addr == RV_PLIC_PRIO34_OFFSET);
7404: addr_hit[39] = (reg_addr == RV_PLIC_PRIO35_OFFSET);
7405: addr_hit[40] = (reg_addr == RV_PLIC_PRIO36_OFFSET);
7406: addr_hit[41] = (reg_addr == RV_PLIC_PRIO37_OFFSET);
7407: addr_hit[42] = (reg_addr == RV_PLIC_PRIO38_OFFSET);
7408: addr_hit[43] = (reg_addr == RV_PLIC_PRIO39_OFFSET);
7409: addr_hit[44] = (reg_addr == RV_PLIC_PRIO40_OFFSET);
7410: addr_hit[45] = (reg_addr == RV_PLIC_PRIO41_OFFSET);
7411: addr_hit[46] = (reg_addr == RV_PLIC_PRIO42_OFFSET);
7412: addr_hit[47] = (reg_addr == RV_PLIC_PRIO43_OFFSET);
7413: addr_hit[48] = (reg_addr == RV_PLIC_PRIO44_OFFSET);
7414: addr_hit[49] = (reg_addr == RV_PLIC_PRIO45_OFFSET);
7415: addr_hit[50] = (reg_addr == RV_PLIC_PRIO46_OFFSET);
7416: addr_hit[51] = (reg_addr == RV_PLIC_PRIO47_OFFSET);
7417: addr_hit[52] = (reg_addr == RV_PLIC_PRIO48_OFFSET);
7418: addr_hit[53] = (reg_addr == RV_PLIC_PRIO49_OFFSET);
7419: addr_hit[54] = (reg_addr == RV_PLIC_PRIO50_OFFSET);
7420: addr_hit[55] = (reg_addr == RV_PLIC_PRIO51_OFFSET);
7421: addr_hit[56] = (reg_addr == RV_PLIC_PRIO52_OFFSET);
7422: addr_hit[57] = (reg_addr == RV_PLIC_PRIO53_OFFSET);
7423: addr_hit[58] = (reg_addr == RV_PLIC_PRIO54_OFFSET);
7424: addr_hit[59] = (reg_addr == RV_PLIC_PRIO55_OFFSET);
7425: addr_hit[60] = (reg_addr == RV_PLIC_PRIO56_OFFSET);
7426: addr_hit[61] = (reg_addr == RV_PLIC_PRIO57_OFFSET);
7427: addr_hit[62] = (reg_addr == RV_PLIC_PRIO58_OFFSET);
7428: addr_hit[63] = (reg_addr == RV_PLIC_PRIO59_OFFSET);
7429: addr_hit[64] = (reg_addr == RV_PLIC_PRIO60_OFFSET);
7430: addr_hit[65] = (reg_addr == RV_PLIC_PRIO61_OFFSET);
7431: addr_hit[66] = (reg_addr == RV_PLIC_PRIO62_OFFSET);
7432: addr_hit[67] = (reg_addr == RV_PLIC_IE00_OFFSET);
7433: addr_hit[68] = (reg_addr == RV_PLIC_IE01_OFFSET);
7434: addr_hit[69] = (reg_addr == RV_PLIC_THRESHOLD0_OFFSET);
7435: addr_hit[70] = (reg_addr == RV_PLIC_CC0_OFFSET);
7436: addr_hit[71] = (reg_addr == RV_PLIC_MSIP0_OFFSET);
7437: end
7438:
7439: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
7440:
7441: // Check sub-word write is permitted
7442: always_comb begin
7443: wr_err = 1'b0;
7444: if (addr_hit[ 0] && reg_we && (RV_PLIC_PERMIT[ 0] != (RV_PLIC_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
7445: if (addr_hit[ 1] && reg_we && (RV_PLIC_PERMIT[ 1] != (RV_PLIC_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
7446: if (addr_hit[ 2] && reg_we && (RV_PLIC_PERMIT[ 2] != (RV_PLIC_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
7447: if (addr_hit[ 3] && reg_we && (RV_PLIC_PERMIT[ 3] != (RV_PLIC_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
7448: if (addr_hit[ 4] && reg_we && (RV_PLIC_PERMIT[ 4] != (RV_PLIC_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
7449: if (addr_hit[ 5] && reg_we && (RV_PLIC_PERMIT[ 5] != (RV_PLIC_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
7450: if (addr_hit[ 6] && reg_we && (RV_PLIC_PERMIT[ 6] != (RV_PLIC_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
7451: if (addr_hit[ 7] && reg_we && (RV_PLIC_PERMIT[ 7] != (RV_PLIC_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
7452: if (addr_hit[ 8] && reg_we && (RV_PLIC_PERMIT[ 8] != (RV_PLIC_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
7453: if (addr_hit[ 9] && reg_we && (RV_PLIC_PERMIT[ 9] != (RV_PLIC_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
7454: if (addr_hit[10] && reg_we && (RV_PLIC_PERMIT[10] != (RV_PLIC_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
7455: if (addr_hit[11] && reg_we && (RV_PLIC_PERMIT[11] != (RV_PLIC_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
7456: if (addr_hit[12] && reg_we && (RV_PLIC_PERMIT[12] != (RV_PLIC_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
7457: if (addr_hit[13] && reg_we && (RV_PLIC_PERMIT[13] != (RV_PLIC_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
7458: if (addr_hit[14] && reg_we && (RV_PLIC_PERMIT[14] != (RV_PLIC_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
7459: if (addr_hit[15] && reg_we && (RV_PLIC_PERMIT[15] != (RV_PLIC_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
7460: if (addr_hit[16] && reg_we && (RV_PLIC_PERMIT[16] != (RV_PLIC_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
7461: if (addr_hit[17] && reg_we && (RV_PLIC_PERMIT[17] != (RV_PLIC_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
7462: if (addr_hit[18] && reg_we && (RV_PLIC_PERMIT[18] != (RV_PLIC_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
7463: if (addr_hit[19] && reg_we && (RV_PLIC_PERMIT[19] != (RV_PLIC_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
7464: if (addr_hit[20] && reg_we && (RV_PLIC_PERMIT[20] != (RV_PLIC_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
7465: if (addr_hit[21] && reg_we && (RV_PLIC_PERMIT[21] != (RV_PLIC_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
7466: if (addr_hit[22] && reg_we && (RV_PLIC_PERMIT[22] != (RV_PLIC_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
7467: if (addr_hit[23] && reg_we && (RV_PLIC_PERMIT[23] != (RV_PLIC_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
7468: if (addr_hit[24] && reg_we && (RV_PLIC_PERMIT[24] != (RV_PLIC_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
7469: if (addr_hit[25] && reg_we && (RV_PLIC_PERMIT[25] != (RV_PLIC_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
7470: if (addr_hit[26] && reg_we && (RV_PLIC_PERMIT[26] != (RV_PLIC_PERMIT[26] & reg_be))) wr_err = 1'b1 ;
7471: if (addr_hit[27] && reg_we && (RV_PLIC_PERMIT[27] != (RV_PLIC_PERMIT[27] & reg_be))) wr_err = 1'b1 ;
7472: if (addr_hit[28] && reg_we && (RV_PLIC_PERMIT[28] != (RV_PLIC_PERMIT[28] & reg_be))) wr_err = 1'b1 ;
7473: if (addr_hit[29] && reg_we && (RV_PLIC_PERMIT[29] != (RV_PLIC_PERMIT[29] & reg_be))) wr_err = 1'b1 ;
7474: if (addr_hit[30] && reg_we && (RV_PLIC_PERMIT[30] != (RV_PLIC_PERMIT[30] & reg_be))) wr_err = 1'b1 ;
7475: if (addr_hit[31] && reg_we && (RV_PLIC_PERMIT[31] != (RV_PLIC_PERMIT[31] & reg_be))) wr_err = 1'b1 ;
7476: if (addr_hit[32] && reg_we && (RV_PLIC_PERMIT[32] != (RV_PLIC_PERMIT[32] & reg_be))) wr_err = 1'b1 ;
7477: if (addr_hit[33] && reg_we && (RV_PLIC_PERMIT[33] != (RV_PLIC_PERMIT[33] & reg_be))) wr_err = 1'b1 ;
7478: if (addr_hit[34] && reg_we && (RV_PLIC_PERMIT[34] != (RV_PLIC_PERMIT[34] & reg_be))) wr_err = 1'b1 ;
7479: if (addr_hit[35] && reg_we && (RV_PLIC_PERMIT[35] != (RV_PLIC_PERMIT[35] & reg_be))) wr_err = 1'b1 ;
7480: if (addr_hit[36] && reg_we && (RV_PLIC_PERMIT[36] != (RV_PLIC_PERMIT[36] & reg_be))) wr_err = 1'b1 ;
7481: if (addr_hit[37] && reg_we && (RV_PLIC_PERMIT[37] != (RV_PLIC_PERMIT[37] & reg_be))) wr_err = 1'b1 ;
7482: if (addr_hit[38] && reg_we && (RV_PLIC_PERMIT[38] != (RV_PLIC_PERMIT[38] & reg_be))) wr_err = 1'b1 ;
7483: if (addr_hit[39] && reg_we && (RV_PLIC_PERMIT[39] != (RV_PLIC_PERMIT[39] & reg_be))) wr_err = 1'b1 ;
7484: if (addr_hit[40] && reg_we && (RV_PLIC_PERMIT[40] != (RV_PLIC_PERMIT[40] & reg_be))) wr_err = 1'b1 ;
7485: if (addr_hit[41] && reg_we && (RV_PLIC_PERMIT[41] != (RV_PLIC_PERMIT[41] & reg_be))) wr_err = 1'b1 ;
7486: if (addr_hit[42] && reg_we && (RV_PLIC_PERMIT[42] != (RV_PLIC_PERMIT[42] & reg_be))) wr_err = 1'b1 ;
7487: if (addr_hit[43] && reg_we && (RV_PLIC_PERMIT[43] != (RV_PLIC_PERMIT[43] & reg_be))) wr_err = 1'b1 ;
7488: if (addr_hit[44] && reg_we && (RV_PLIC_PERMIT[44] != (RV_PLIC_PERMIT[44] & reg_be))) wr_err = 1'b1 ;
7489: if (addr_hit[45] && reg_we && (RV_PLIC_PERMIT[45] != (RV_PLIC_PERMIT[45] & reg_be))) wr_err = 1'b1 ;
7490: if (addr_hit[46] && reg_we && (RV_PLIC_PERMIT[46] != (RV_PLIC_PERMIT[46] & reg_be))) wr_err = 1'b1 ;
7491: if (addr_hit[47] && reg_we && (RV_PLIC_PERMIT[47] != (RV_PLIC_PERMIT[47] & reg_be))) wr_err = 1'b1 ;
7492: if (addr_hit[48] && reg_we && (RV_PLIC_PERMIT[48] != (RV_PLIC_PERMIT[48] & reg_be))) wr_err = 1'b1 ;
7493: if (addr_hit[49] && reg_we && (RV_PLIC_PERMIT[49] != (RV_PLIC_PERMIT[49] & reg_be))) wr_err = 1'b1 ;
7494: if (addr_hit[50] && reg_we && (RV_PLIC_PERMIT[50] != (RV_PLIC_PERMIT[50] & reg_be))) wr_err = 1'b1 ;
7495: if (addr_hit[51] && reg_we && (RV_PLIC_PERMIT[51] != (RV_PLIC_PERMIT[51] & reg_be))) wr_err = 1'b1 ;
7496: if (addr_hit[52] && reg_we && (RV_PLIC_PERMIT[52] != (RV_PLIC_PERMIT[52] & reg_be))) wr_err = 1'b1 ;
7497: if (addr_hit[53] && reg_we && (RV_PLIC_PERMIT[53] != (RV_PLIC_PERMIT[53] & reg_be))) wr_err = 1'b1 ;
7498: if (addr_hit[54] && reg_we && (RV_PLIC_PERMIT[54] != (RV_PLIC_PERMIT[54] & reg_be))) wr_err = 1'b1 ;
7499: if (addr_hit[55] && reg_we && (RV_PLIC_PERMIT[55] != (RV_PLIC_PERMIT[55] & reg_be))) wr_err = 1'b1 ;
7500: if (addr_hit[56] && reg_we && (RV_PLIC_PERMIT[56] != (RV_PLIC_PERMIT[56] & reg_be))) wr_err = 1'b1 ;
7501: if (addr_hit[57] && reg_we && (RV_PLIC_PERMIT[57] != (RV_PLIC_PERMIT[57] & reg_be))) wr_err = 1'b1 ;
7502: if (addr_hit[58] && reg_we && (RV_PLIC_PERMIT[58] != (RV_PLIC_PERMIT[58] & reg_be))) wr_err = 1'b1 ;
7503: if (addr_hit[59] && reg_we && (RV_PLIC_PERMIT[59] != (RV_PLIC_PERMIT[59] & reg_be))) wr_err = 1'b1 ;
7504: if (addr_hit[60] && reg_we && (RV_PLIC_PERMIT[60] != (RV_PLIC_PERMIT[60] & reg_be))) wr_err = 1'b1 ;
7505: if (addr_hit[61] && reg_we && (RV_PLIC_PERMIT[61] != (RV_PLIC_PERMIT[61] & reg_be))) wr_err = 1'b1 ;
7506: if (addr_hit[62] && reg_we && (RV_PLIC_PERMIT[62] != (RV_PLIC_PERMIT[62] & reg_be))) wr_err = 1'b1 ;
7507: if (addr_hit[63] && reg_we && (RV_PLIC_PERMIT[63] != (RV_PLIC_PERMIT[63] & reg_be))) wr_err = 1'b1 ;
7508: if (addr_hit[64] && reg_we && (RV_PLIC_PERMIT[64] != (RV_PLIC_PERMIT[64] & reg_be))) wr_err = 1'b1 ;
7509: if (addr_hit[65] && reg_we && (RV_PLIC_PERMIT[65] != (RV_PLIC_PERMIT[65] & reg_be))) wr_err = 1'b1 ;
7510: if (addr_hit[66] && reg_we && (RV_PLIC_PERMIT[66] != (RV_PLIC_PERMIT[66] & reg_be))) wr_err = 1'b1 ;
7511: if (addr_hit[67] && reg_we && (RV_PLIC_PERMIT[67] != (RV_PLIC_PERMIT[67] & reg_be))) wr_err = 1'b1 ;
7512: if (addr_hit[68] && reg_we && (RV_PLIC_PERMIT[68] != (RV_PLIC_PERMIT[68] & reg_be))) wr_err = 1'b1 ;
7513: if (addr_hit[69] && reg_we && (RV_PLIC_PERMIT[69] != (RV_PLIC_PERMIT[69] & reg_be))) wr_err = 1'b1 ;
7514: if (addr_hit[70] && reg_we && (RV_PLIC_PERMIT[70] != (RV_PLIC_PERMIT[70] & reg_be))) wr_err = 1'b1 ;
7515: if (addr_hit[71] && reg_we && (RV_PLIC_PERMIT[71] != (RV_PLIC_PERMIT[71] & reg_be))) wr_err = 1'b1 ;
7516: end
7517:
7518:
7519:
7520:
7521:
7522:
7523:
7524:
7525:
7526:
7527:
7528:
7529:
7530:
7531:
7532:
7533:
7534:
7535:
7536:
7537:
7538:
7539:
7540:
7541:
7542:
7543:
7544:
7545:
7546:
7547:
7548:
7549:
7550:
7551:
7552:
7553:
7554:
7555:
7556:
7557:
7558:
7559:
7560:
7561:
7562:
7563:
7564:
7565:
7566:
7567:
7568:
7569:
7570:
7571:
7572:
7573:
7574:
7575:
7576:
7577:
7578:
7579:
7580:
7581: assign le0_le0_we = addr_hit[2] & reg_we & ~wr_err;
7582: assign le0_le0_wd = reg_wdata[0];
7583:
7584: assign le0_le1_we = addr_hit[2] & reg_we & ~wr_err;
7585: assign le0_le1_wd = reg_wdata[1];
7586:
7587: assign le0_le2_we = addr_hit[2] & reg_we & ~wr_err;
7588: assign le0_le2_wd = reg_wdata[2];
7589:
7590: assign le0_le3_we = addr_hit[2] & reg_we & ~wr_err;
7591: assign le0_le3_wd = reg_wdata[3];
7592:
7593: assign le0_le4_we = addr_hit[2] & reg_we & ~wr_err;
7594: assign le0_le4_wd = reg_wdata[4];
7595:
7596: assign le0_le5_we = addr_hit[2] & reg_we & ~wr_err;
7597: assign le0_le5_wd = reg_wdata[5];
7598:
7599: assign le0_le6_we = addr_hit[2] & reg_we & ~wr_err;
7600: assign le0_le6_wd = reg_wdata[6];
7601:
7602: assign le0_le7_we = addr_hit[2] & reg_we & ~wr_err;
7603: assign le0_le7_wd = reg_wdata[7];
7604:
7605: assign le0_le8_we = addr_hit[2] & reg_we & ~wr_err;
7606: assign le0_le8_wd = reg_wdata[8];
7607:
7608: assign le0_le9_we = addr_hit[2] & reg_we & ~wr_err;
7609: assign le0_le9_wd = reg_wdata[9];
7610:
7611: assign le0_le10_we = addr_hit[2] & reg_we & ~wr_err;
7612: assign le0_le10_wd = reg_wdata[10];
7613:
7614: assign le0_le11_we = addr_hit[2] & reg_we & ~wr_err;
7615: assign le0_le11_wd = reg_wdata[11];
7616:
7617: assign le0_le12_we = addr_hit[2] & reg_we & ~wr_err;
7618: assign le0_le12_wd = reg_wdata[12];
7619:
7620: assign le0_le13_we = addr_hit[2] & reg_we & ~wr_err;
7621: assign le0_le13_wd = reg_wdata[13];
7622:
7623: assign le0_le14_we = addr_hit[2] & reg_we & ~wr_err;
7624: assign le0_le14_wd = reg_wdata[14];
7625:
7626: assign le0_le15_we = addr_hit[2] & reg_we & ~wr_err;
7627: assign le0_le15_wd = reg_wdata[15];
7628:
7629: assign le0_le16_we = addr_hit[2] & reg_we & ~wr_err;
7630: assign le0_le16_wd = reg_wdata[16];
7631:
7632: assign le0_le17_we = addr_hit[2] & reg_we & ~wr_err;
7633: assign le0_le17_wd = reg_wdata[17];
7634:
7635: assign le0_le18_we = addr_hit[2] & reg_we & ~wr_err;
7636: assign le0_le18_wd = reg_wdata[18];
7637:
7638: assign le0_le19_we = addr_hit[2] & reg_we & ~wr_err;
7639: assign le0_le19_wd = reg_wdata[19];
7640:
7641: assign le0_le20_we = addr_hit[2] & reg_we & ~wr_err;
7642: assign le0_le20_wd = reg_wdata[20];
7643:
7644: assign le0_le21_we = addr_hit[2] & reg_we & ~wr_err;
7645: assign le0_le21_wd = reg_wdata[21];
7646:
7647: assign le0_le22_we = addr_hit[2] & reg_we & ~wr_err;
7648: assign le0_le22_wd = reg_wdata[22];
7649:
7650: assign le0_le23_we = addr_hit[2] & reg_we & ~wr_err;
7651: assign le0_le23_wd = reg_wdata[23];
7652:
7653: assign le0_le24_we = addr_hit[2] & reg_we & ~wr_err;
7654: assign le0_le24_wd = reg_wdata[24];
7655:
7656: assign le0_le25_we = addr_hit[2] & reg_we & ~wr_err;
7657: assign le0_le25_wd = reg_wdata[25];
7658:
7659: assign le0_le26_we = addr_hit[2] & reg_we & ~wr_err;
7660: assign le0_le26_wd = reg_wdata[26];
7661:
7662: assign le0_le27_we = addr_hit[2] & reg_we & ~wr_err;
7663: assign le0_le27_wd = reg_wdata[27];
7664:
7665: assign le0_le28_we = addr_hit[2] & reg_we & ~wr_err;
7666: assign le0_le28_wd = reg_wdata[28];
7667:
7668: assign le0_le29_we = addr_hit[2] & reg_we & ~wr_err;
7669: assign le0_le29_wd = reg_wdata[29];
7670:
7671: assign le0_le30_we = addr_hit[2] & reg_we & ~wr_err;
7672: assign le0_le30_wd = reg_wdata[30];
7673:
7674: assign le0_le31_we = addr_hit[2] & reg_we & ~wr_err;
7675: assign le0_le31_wd = reg_wdata[31];
7676:
7677: assign le1_le32_we = addr_hit[3] & reg_we & ~wr_err;
7678: assign le1_le32_wd = reg_wdata[0];
7679:
7680: assign le1_le33_we = addr_hit[3] & reg_we & ~wr_err;
7681: assign le1_le33_wd = reg_wdata[1];
7682:
7683: assign le1_le34_we = addr_hit[3] & reg_we & ~wr_err;
7684: assign le1_le34_wd = reg_wdata[2];
7685:
7686: assign le1_le35_we = addr_hit[3] & reg_we & ~wr_err;
7687: assign le1_le35_wd = reg_wdata[3];
7688:
7689: assign le1_le36_we = addr_hit[3] & reg_we & ~wr_err;
7690: assign le1_le36_wd = reg_wdata[4];
7691:
7692: assign le1_le37_we = addr_hit[3] & reg_we & ~wr_err;
7693: assign le1_le37_wd = reg_wdata[5];
7694:
7695: assign le1_le38_we = addr_hit[3] & reg_we & ~wr_err;
7696: assign le1_le38_wd = reg_wdata[6];
7697:
7698: assign le1_le39_we = addr_hit[3] & reg_we & ~wr_err;
7699: assign le1_le39_wd = reg_wdata[7];
7700:
7701: assign le1_le40_we = addr_hit[3] & reg_we & ~wr_err;
7702: assign le1_le40_wd = reg_wdata[8];
7703:
7704: assign le1_le41_we = addr_hit[3] & reg_we & ~wr_err;
7705: assign le1_le41_wd = reg_wdata[9];
7706:
7707: assign le1_le42_we = addr_hit[3] & reg_we & ~wr_err;
7708: assign le1_le42_wd = reg_wdata[10];
7709:
7710: assign le1_le43_we = addr_hit[3] & reg_we & ~wr_err;
7711: assign le1_le43_wd = reg_wdata[11];
7712:
7713: assign le1_le44_we = addr_hit[3] & reg_we & ~wr_err;
7714: assign le1_le44_wd = reg_wdata[12];
7715:
7716: assign le1_le45_we = addr_hit[3] & reg_we & ~wr_err;
7717: assign le1_le45_wd = reg_wdata[13];
7718:
7719: assign le1_le46_we = addr_hit[3] & reg_we & ~wr_err;
7720: assign le1_le46_wd = reg_wdata[14];
7721:
7722: assign le1_le47_we = addr_hit[3] & reg_we & ~wr_err;
7723: assign le1_le47_wd = reg_wdata[15];
7724:
7725: assign le1_le48_we = addr_hit[3] & reg_we & ~wr_err;
7726: assign le1_le48_wd = reg_wdata[16];
7727:
7728: assign le1_le49_we = addr_hit[3] & reg_we & ~wr_err;
7729: assign le1_le49_wd = reg_wdata[17];
7730:
7731: assign le1_le50_we = addr_hit[3] & reg_we & ~wr_err;
7732: assign le1_le50_wd = reg_wdata[18];
7733:
7734: assign le1_le51_we = addr_hit[3] & reg_we & ~wr_err;
7735: assign le1_le51_wd = reg_wdata[19];
7736:
7737: assign le1_le52_we = addr_hit[3] & reg_we & ~wr_err;
7738: assign le1_le52_wd = reg_wdata[20];
7739:
7740: assign le1_le53_we = addr_hit[3] & reg_we & ~wr_err;
7741: assign le1_le53_wd = reg_wdata[21];
7742:
7743: assign le1_le54_we = addr_hit[3] & reg_we & ~wr_err;
7744: assign le1_le54_wd = reg_wdata[22];
7745:
7746: assign le1_le55_we = addr_hit[3] & reg_we & ~wr_err;
7747: assign le1_le55_wd = reg_wdata[23];
7748:
7749: assign le1_le56_we = addr_hit[3] & reg_we & ~wr_err;
7750: assign le1_le56_wd = reg_wdata[24];
7751:
7752: assign le1_le57_we = addr_hit[3] & reg_we & ~wr_err;
7753: assign le1_le57_wd = reg_wdata[25];
7754:
7755: assign le1_le58_we = addr_hit[3] & reg_we & ~wr_err;
7756: assign le1_le58_wd = reg_wdata[26];
7757:
7758: assign le1_le59_we = addr_hit[3] & reg_we & ~wr_err;
7759: assign le1_le59_wd = reg_wdata[27];
7760:
7761: assign le1_le60_we = addr_hit[3] & reg_we & ~wr_err;
7762: assign le1_le60_wd = reg_wdata[28];
7763:
7764: assign le1_le61_we = addr_hit[3] & reg_we & ~wr_err;
7765: assign le1_le61_wd = reg_wdata[29];
7766:
7767: assign le1_le62_we = addr_hit[3] & reg_we & ~wr_err;
7768: assign le1_le62_wd = reg_wdata[30];
7769:
7770: assign prio0_we = addr_hit[4] & reg_we & ~wr_err;
7771: assign prio0_wd = reg_wdata[1:0];
7772:
7773: assign prio1_we = addr_hit[5] & reg_we & ~wr_err;
7774: assign prio1_wd = reg_wdata[1:0];
7775:
7776: assign prio2_we = addr_hit[6] & reg_we & ~wr_err;
7777: assign prio2_wd = reg_wdata[1:0];
7778:
7779: assign prio3_we = addr_hit[7] & reg_we & ~wr_err;
7780: assign prio3_wd = reg_wdata[1:0];
7781:
7782: assign prio4_we = addr_hit[8] & reg_we & ~wr_err;
7783: assign prio4_wd = reg_wdata[1:0];
7784:
7785: assign prio5_we = addr_hit[9] & reg_we & ~wr_err;
7786: assign prio5_wd = reg_wdata[1:0];
7787:
7788: assign prio6_we = addr_hit[10] & reg_we & ~wr_err;
7789: assign prio6_wd = reg_wdata[1:0];
7790:
7791: assign prio7_we = addr_hit[11] & reg_we & ~wr_err;
7792: assign prio7_wd = reg_wdata[1:0];
7793:
7794: assign prio8_we = addr_hit[12] & reg_we & ~wr_err;
7795: assign prio8_wd = reg_wdata[1:0];
7796:
7797: assign prio9_we = addr_hit[13] & reg_we & ~wr_err;
7798: assign prio9_wd = reg_wdata[1:0];
7799:
7800: assign prio10_we = addr_hit[14] & reg_we & ~wr_err;
7801: assign prio10_wd = reg_wdata[1:0];
7802:
7803: assign prio11_we = addr_hit[15] & reg_we & ~wr_err;
7804: assign prio11_wd = reg_wdata[1:0];
7805:
7806: assign prio12_we = addr_hit[16] & reg_we & ~wr_err;
7807: assign prio12_wd = reg_wdata[1:0];
7808:
7809: assign prio13_we = addr_hit[17] & reg_we & ~wr_err;
7810: assign prio13_wd = reg_wdata[1:0];
7811:
7812: assign prio14_we = addr_hit[18] & reg_we & ~wr_err;
7813: assign prio14_wd = reg_wdata[1:0];
7814:
7815: assign prio15_we = addr_hit[19] & reg_we & ~wr_err;
7816: assign prio15_wd = reg_wdata[1:0];
7817:
7818: assign prio16_we = addr_hit[20] & reg_we & ~wr_err;
7819: assign prio16_wd = reg_wdata[1:0];
7820:
7821: assign prio17_we = addr_hit[21] & reg_we & ~wr_err;
7822: assign prio17_wd = reg_wdata[1:0];
7823:
7824: assign prio18_we = addr_hit[22] & reg_we & ~wr_err;
7825: assign prio18_wd = reg_wdata[1:0];
7826:
7827: assign prio19_we = addr_hit[23] & reg_we & ~wr_err;
7828: assign prio19_wd = reg_wdata[1:0];
7829:
7830: assign prio20_we = addr_hit[24] & reg_we & ~wr_err;
7831: assign prio20_wd = reg_wdata[1:0];
7832:
7833: assign prio21_we = addr_hit[25] & reg_we & ~wr_err;
7834: assign prio21_wd = reg_wdata[1:0];
7835:
7836: assign prio22_we = addr_hit[26] & reg_we & ~wr_err;
7837: assign prio22_wd = reg_wdata[1:0];
7838:
7839: assign prio23_we = addr_hit[27] & reg_we & ~wr_err;
7840: assign prio23_wd = reg_wdata[1:0];
7841:
7842: assign prio24_we = addr_hit[28] & reg_we & ~wr_err;
7843: assign prio24_wd = reg_wdata[1:0];
7844:
7845: assign prio25_we = addr_hit[29] & reg_we & ~wr_err;
7846: assign prio25_wd = reg_wdata[1:0];
7847:
7848: assign prio26_we = addr_hit[30] & reg_we & ~wr_err;
7849: assign prio26_wd = reg_wdata[1:0];
7850:
7851: assign prio27_we = addr_hit[31] & reg_we & ~wr_err;
7852: assign prio27_wd = reg_wdata[1:0];
7853:
7854: assign prio28_we = addr_hit[32] & reg_we & ~wr_err;
7855: assign prio28_wd = reg_wdata[1:0];
7856:
7857: assign prio29_we = addr_hit[33] & reg_we & ~wr_err;
7858: assign prio29_wd = reg_wdata[1:0];
7859:
7860: assign prio30_we = addr_hit[34] & reg_we & ~wr_err;
7861: assign prio30_wd = reg_wdata[1:0];
7862:
7863: assign prio31_we = addr_hit[35] & reg_we & ~wr_err;
7864: assign prio31_wd = reg_wdata[1:0];
7865:
7866: assign prio32_we = addr_hit[36] & reg_we & ~wr_err;
7867: assign prio32_wd = reg_wdata[1:0];
7868:
7869: assign prio33_we = addr_hit[37] & reg_we & ~wr_err;
7870: assign prio33_wd = reg_wdata[1:0];
7871:
7872: assign prio34_we = addr_hit[38] & reg_we & ~wr_err;
7873: assign prio34_wd = reg_wdata[1:0];
7874:
7875: assign prio35_we = addr_hit[39] & reg_we & ~wr_err;
7876: assign prio35_wd = reg_wdata[1:0];
7877:
7878: assign prio36_we = addr_hit[40] & reg_we & ~wr_err;
7879: assign prio36_wd = reg_wdata[1:0];
7880:
7881: assign prio37_we = addr_hit[41] & reg_we & ~wr_err;
7882: assign prio37_wd = reg_wdata[1:0];
7883:
7884: assign prio38_we = addr_hit[42] & reg_we & ~wr_err;
7885: assign prio38_wd = reg_wdata[1:0];
7886:
7887: assign prio39_we = addr_hit[43] & reg_we & ~wr_err;
7888: assign prio39_wd = reg_wdata[1:0];
7889:
7890: assign prio40_we = addr_hit[44] & reg_we & ~wr_err;
7891: assign prio40_wd = reg_wdata[1:0];
7892:
7893: assign prio41_we = addr_hit[45] & reg_we & ~wr_err;
7894: assign prio41_wd = reg_wdata[1:0];
7895:
7896: assign prio42_we = addr_hit[46] & reg_we & ~wr_err;
7897: assign prio42_wd = reg_wdata[1:0];
7898:
7899: assign prio43_we = addr_hit[47] & reg_we & ~wr_err;
7900: assign prio43_wd = reg_wdata[1:0];
7901:
7902: assign prio44_we = addr_hit[48] & reg_we & ~wr_err;
7903: assign prio44_wd = reg_wdata[1:0];
7904:
7905: assign prio45_we = addr_hit[49] & reg_we & ~wr_err;
7906: assign prio45_wd = reg_wdata[1:0];
7907:
7908: assign prio46_we = addr_hit[50] & reg_we & ~wr_err;
7909: assign prio46_wd = reg_wdata[1:0];
7910:
7911: assign prio47_we = addr_hit[51] & reg_we & ~wr_err;
7912: assign prio47_wd = reg_wdata[1:0];
7913:
7914: assign prio48_we = addr_hit[52] & reg_we & ~wr_err;
7915: assign prio48_wd = reg_wdata[1:0];
7916:
7917: assign prio49_we = addr_hit[53] & reg_we & ~wr_err;
7918: assign prio49_wd = reg_wdata[1:0];
7919:
7920: assign prio50_we = addr_hit[54] & reg_we & ~wr_err;
7921: assign prio50_wd = reg_wdata[1:0];
7922:
7923: assign prio51_we = addr_hit[55] & reg_we & ~wr_err;
7924: assign prio51_wd = reg_wdata[1:0];
7925:
7926: assign prio52_we = addr_hit[56] & reg_we & ~wr_err;
7927: assign prio52_wd = reg_wdata[1:0];
7928:
7929: assign prio53_we = addr_hit[57] & reg_we & ~wr_err;
7930: assign prio53_wd = reg_wdata[1:0];
7931:
7932: assign prio54_we = addr_hit[58] & reg_we & ~wr_err;
7933: assign prio54_wd = reg_wdata[1:0];
7934:
7935: assign prio55_we = addr_hit[59] & reg_we & ~wr_err;
7936: assign prio55_wd = reg_wdata[1:0];
7937:
7938: assign prio56_we = addr_hit[60] & reg_we & ~wr_err;
7939: assign prio56_wd = reg_wdata[1:0];
7940:
7941: assign prio57_we = addr_hit[61] & reg_we & ~wr_err;
7942: assign prio57_wd = reg_wdata[1:0];
7943:
7944: assign prio58_we = addr_hit[62] & reg_we & ~wr_err;
7945: assign prio58_wd = reg_wdata[1:0];
7946:
7947: assign prio59_we = addr_hit[63] & reg_we & ~wr_err;
7948: assign prio59_wd = reg_wdata[1:0];
7949:
7950: assign prio60_we = addr_hit[64] & reg_we & ~wr_err;
7951: assign prio60_wd = reg_wdata[1:0];
7952:
7953: assign prio61_we = addr_hit[65] & reg_we & ~wr_err;
7954: assign prio61_wd = reg_wdata[1:0];
7955:
7956: assign prio62_we = addr_hit[66] & reg_we & ~wr_err;
7957: assign prio62_wd = reg_wdata[1:0];
7958:
7959: assign ie00_e0_we = addr_hit[67] & reg_we & ~wr_err;
7960: assign ie00_e0_wd = reg_wdata[0];
7961:
7962: assign ie00_e1_we = addr_hit[67] & reg_we & ~wr_err;
7963: assign ie00_e1_wd = reg_wdata[1];
7964:
7965: assign ie00_e2_we = addr_hit[67] & reg_we & ~wr_err;
7966: assign ie00_e2_wd = reg_wdata[2];
7967:
7968: assign ie00_e3_we = addr_hit[67] & reg_we & ~wr_err;
7969: assign ie00_e3_wd = reg_wdata[3];
7970:
7971: assign ie00_e4_we = addr_hit[67] & reg_we & ~wr_err;
7972: assign ie00_e4_wd = reg_wdata[4];
7973:
7974: assign ie00_e5_we = addr_hit[67] & reg_we & ~wr_err;
7975: assign ie00_e5_wd = reg_wdata[5];
7976:
7977: assign ie00_e6_we = addr_hit[67] & reg_we & ~wr_err;
7978: assign ie00_e6_wd = reg_wdata[6];
7979:
7980: assign ie00_e7_we = addr_hit[67] & reg_we & ~wr_err;
7981: assign ie00_e7_wd = reg_wdata[7];
7982:
7983: assign ie00_e8_we = addr_hit[67] & reg_we & ~wr_err;
7984: assign ie00_e8_wd = reg_wdata[8];
7985:
7986: assign ie00_e9_we = addr_hit[67] & reg_we & ~wr_err;
7987: assign ie00_e9_wd = reg_wdata[9];
7988:
7989: assign ie00_e10_we = addr_hit[67] & reg_we & ~wr_err;
7990: assign ie00_e10_wd = reg_wdata[10];
7991:
7992: assign ie00_e11_we = addr_hit[67] & reg_we & ~wr_err;
7993: assign ie00_e11_wd = reg_wdata[11];
7994:
7995: assign ie00_e12_we = addr_hit[67] & reg_we & ~wr_err;
7996: assign ie00_e12_wd = reg_wdata[12];
7997:
7998: assign ie00_e13_we = addr_hit[67] & reg_we & ~wr_err;
7999: assign ie00_e13_wd = reg_wdata[13];
8000:
8001: assign ie00_e14_we = addr_hit[67] & reg_we & ~wr_err;
8002: assign ie00_e14_wd = reg_wdata[14];
8003:
8004: assign ie00_e15_we = addr_hit[67] & reg_we & ~wr_err;
8005: assign ie00_e15_wd = reg_wdata[15];
8006:
8007: assign ie00_e16_we = addr_hit[67] & reg_we & ~wr_err;
8008: assign ie00_e16_wd = reg_wdata[16];
8009:
8010: assign ie00_e17_we = addr_hit[67] & reg_we & ~wr_err;
8011: assign ie00_e17_wd = reg_wdata[17];
8012:
8013: assign ie00_e18_we = addr_hit[67] & reg_we & ~wr_err;
8014: assign ie00_e18_wd = reg_wdata[18];
8015:
8016: assign ie00_e19_we = addr_hit[67] & reg_we & ~wr_err;
8017: assign ie00_e19_wd = reg_wdata[19];
8018:
8019: assign ie00_e20_we = addr_hit[67] & reg_we & ~wr_err;
8020: assign ie00_e20_wd = reg_wdata[20];
8021:
8022: assign ie00_e21_we = addr_hit[67] & reg_we & ~wr_err;
8023: assign ie00_e21_wd = reg_wdata[21];
8024:
8025: assign ie00_e22_we = addr_hit[67] & reg_we & ~wr_err;
8026: assign ie00_e22_wd = reg_wdata[22];
8027:
8028: assign ie00_e23_we = addr_hit[67] & reg_we & ~wr_err;
8029: assign ie00_e23_wd = reg_wdata[23];
8030:
8031: assign ie00_e24_we = addr_hit[67] & reg_we & ~wr_err;
8032: assign ie00_e24_wd = reg_wdata[24];
8033:
8034: assign ie00_e25_we = addr_hit[67] & reg_we & ~wr_err;
8035: assign ie00_e25_wd = reg_wdata[25];
8036:
8037: assign ie00_e26_we = addr_hit[67] & reg_we & ~wr_err;
8038: assign ie00_e26_wd = reg_wdata[26];
8039:
8040: assign ie00_e27_we = addr_hit[67] & reg_we & ~wr_err;
8041: assign ie00_e27_wd = reg_wdata[27];
8042:
8043: assign ie00_e28_we = addr_hit[67] & reg_we & ~wr_err;
8044: assign ie00_e28_wd = reg_wdata[28];
8045:
8046: assign ie00_e29_we = addr_hit[67] & reg_we & ~wr_err;
8047: assign ie00_e29_wd = reg_wdata[29];
8048:
8049: assign ie00_e30_we = addr_hit[67] & reg_we & ~wr_err;
8050: assign ie00_e30_wd = reg_wdata[30];
8051:
8052: assign ie00_e31_we = addr_hit[67] & reg_we & ~wr_err;
8053: assign ie00_e31_wd = reg_wdata[31];
8054:
8055: assign ie01_e32_we = addr_hit[68] & reg_we & ~wr_err;
8056: assign ie01_e32_wd = reg_wdata[0];
8057:
8058: assign ie01_e33_we = addr_hit[68] & reg_we & ~wr_err;
8059: assign ie01_e33_wd = reg_wdata[1];
8060:
8061: assign ie01_e34_we = addr_hit[68] & reg_we & ~wr_err;
8062: assign ie01_e34_wd = reg_wdata[2];
8063:
8064: assign ie01_e35_we = addr_hit[68] & reg_we & ~wr_err;
8065: assign ie01_e35_wd = reg_wdata[3];
8066:
8067: assign ie01_e36_we = addr_hit[68] & reg_we & ~wr_err;
8068: assign ie01_e36_wd = reg_wdata[4];
8069:
8070: assign ie01_e37_we = addr_hit[68] & reg_we & ~wr_err;
8071: assign ie01_e37_wd = reg_wdata[5];
8072:
8073: assign ie01_e38_we = addr_hit[68] & reg_we & ~wr_err;
8074: assign ie01_e38_wd = reg_wdata[6];
8075:
8076: assign ie01_e39_we = addr_hit[68] & reg_we & ~wr_err;
8077: assign ie01_e39_wd = reg_wdata[7];
8078:
8079: assign ie01_e40_we = addr_hit[68] & reg_we & ~wr_err;
8080: assign ie01_e40_wd = reg_wdata[8];
8081:
8082: assign ie01_e41_we = addr_hit[68] & reg_we & ~wr_err;
8083: assign ie01_e41_wd = reg_wdata[9];
8084:
8085: assign ie01_e42_we = addr_hit[68] & reg_we & ~wr_err;
8086: assign ie01_e42_wd = reg_wdata[10];
8087:
8088: assign ie01_e43_we = addr_hit[68] & reg_we & ~wr_err;
8089: assign ie01_e43_wd = reg_wdata[11];
8090:
8091: assign ie01_e44_we = addr_hit[68] & reg_we & ~wr_err;
8092: assign ie01_e44_wd = reg_wdata[12];
8093:
8094: assign ie01_e45_we = addr_hit[68] & reg_we & ~wr_err;
8095: assign ie01_e45_wd = reg_wdata[13];
8096:
8097: assign ie01_e46_we = addr_hit[68] & reg_we & ~wr_err;
8098: assign ie01_e46_wd = reg_wdata[14];
8099:
8100: assign ie01_e47_we = addr_hit[68] & reg_we & ~wr_err;
8101: assign ie01_e47_wd = reg_wdata[15];
8102:
8103: assign ie01_e48_we = addr_hit[68] & reg_we & ~wr_err;
8104: assign ie01_e48_wd = reg_wdata[16];
8105:
8106: assign ie01_e49_we = addr_hit[68] & reg_we & ~wr_err;
8107: assign ie01_e49_wd = reg_wdata[17];
8108:
8109: assign ie01_e50_we = addr_hit[68] & reg_we & ~wr_err;
8110: assign ie01_e50_wd = reg_wdata[18];
8111:
8112: assign ie01_e51_we = addr_hit[68] & reg_we & ~wr_err;
8113: assign ie01_e51_wd = reg_wdata[19];
8114:
8115: assign ie01_e52_we = addr_hit[68] & reg_we & ~wr_err;
8116: assign ie01_e52_wd = reg_wdata[20];
8117:
8118: assign ie01_e53_we = addr_hit[68] & reg_we & ~wr_err;
8119: assign ie01_e53_wd = reg_wdata[21];
8120:
8121: assign ie01_e54_we = addr_hit[68] & reg_we & ~wr_err;
8122: assign ie01_e54_wd = reg_wdata[22];
8123:
8124: assign ie01_e55_we = addr_hit[68] & reg_we & ~wr_err;
8125: assign ie01_e55_wd = reg_wdata[23];
8126:
8127: assign ie01_e56_we = addr_hit[68] & reg_we & ~wr_err;
8128: assign ie01_e56_wd = reg_wdata[24];
8129:
8130: assign ie01_e57_we = addr_hit[68] & reg_we & ~wr_err;
8131: assign ie01_e57_wd = reg_wdata[25];
8132:
8133: assign ie01_e58_we = addr_hit[68] & reg_we & ~wr_err;
8134: assign ie01_e58_wd = reg_wdata[26];
8135:
8136: assign ie01_e59_we = addr_hit[68] & reg_we & ~wr_err;
8137: assign ie01_e59_wd = reg_wdata[27];
8138:
8139: assign ie01_e60_we = addr_hit[68] & reg_we & ~wr_err;
8140: assign ie01_e60_wd = reg_wdata[28];
8141:
8142: assign ie01_e61_we = addr_hit[68] & reg_we & ~wr_err;
8143: assign ie01_e61_wd = reg_wdata[29];
8144:
8145: assign ie01_e62_we = addr_hit[68] & reg_we & ~wr_err;
8146: assign ie01_e62_wd = reg_wdata[30];
8147:
8148: assign threshold0_we = addr_hit[69] & reg_we & ~wr_err;
8149: assign threshold0_wd = reg_wdata[1:0];
8150:
8151: assign cc0_we = addr_hit[70] & reg_we & ~wr_err;
8152: assign cc0_wd = reg_wdata[5:0];
8153: assign cc0_re = addr_hit[70] && reg_re;
8154:
8155: assign msip0_we = addr_hit[71] & reg_we & ~wr_err;
8156: assign msip0_wd = reg_wdata[0];
8157:
8158: // Read data return
8159: always_comb begin
8160: reg_rdata_next = '0;
8161: unique case (1'b1)
8162: addr_hit[0]: begin
8163: reg_rdata_next[0] = ip0_p0_qs;
8164: reg_rdata_next[1] = ip0_p1_qs;
8165: reg_rdata_next[2] = ip0_p2_qs;
8166: reg_rdata_next[3] = ip0_p3_qs;
8167: reg_rdata_next[4] = ip0_p4_qs;
8168: reg_rdata_next[5] = ip0_p5_qs;
8169: reg_rdata_next[6] = ip0_p6_qs;
8170: reg_rdata_next[7] = ip0_p7_qs;
8171: reg_rdata_next[8] = ip0_p8_qs;
8172: reg_rdata_next[9] = ip0_p9_qs;
8173: reg_rdata_next[10] = ip0_p10_qs;
8174: reg_rdata_next[11] = ip0_p11_qs;
8175: reg_rdata_next[12] = ip0_p12_qs;
8176: reg_rdata_next[13] = ip0_p13_qs;
8177: reg_rdata_next[14] = ip0_p14_qs;
8178: reg_rdata_next[15] = ip0_p15_qs;
8179: reg_rdata_next[16] = ip0_p16_qs;
8180: reg_rdata_next[17] = ip0_p17_qs;
8181: reg_rdata_next[18] = ip0_p18_qs;
8182: reg_rdata_next[19] = ip0_p19_qs;
8183: reg_rdata_next[20] = ip0_p20_qs;
8184: reg_rdata_next[21] = ip0_p21_qs;
8185: reg_rdata_next[22] = ip0_p22_qs;
8186: reg_rdata_next[23] = ip0_p23_qs;
8187: reg_rdata_next[24] = ip0_p24_qs;
8188: reg_rdata_next[25] = ip0_p25_qs;
8189: reg_rdata_next[26] = ip0_p26_qs;
8190: reg_rdata_next[27] = ip0_p27_qs;
8191: reg_rdata_next[28] = ip0_p28_qs;
8192: reg_rdata_next[29] = ip0_p29_qs;
8193: reg_rdata_next[30] = ip0_p30_qs;
8194: reg_rdata_next[31] = ip0_p31_qs;
8195: end
8196:
8197: addr_hit[1]: begin
8198: reg_rdata_next[0] = ip1_p32_qs;
8199: reg_rdata_next[1] = ip1_p33_qs;
8200: reg_rdata_next[2] = ip1_p34_qs;
8201: reg_rdata_next[3] = ip1_p35_qs;
8202: reg_rdata_next[4] = ip1_p36_qs;
8203: reg_rdata_next[5] = ip1_p37_qs;
8204: reg_rdata_next[6] = ip1_p38_qs;
8205: reg_rdata_next[7] = ip1_p39_qs;
8206: reg_rdata_next[8] = ip1_p40_qs;
8207: reg_rdata_next[9] = ip1_p41_qs;
8208: reg_rdata_next[10] = ip1_p42_qs;
8209: reg_rdata_next[11] = ip1_p43_qs;
8210: reg_rdata_next[12] = ip1_p44_qs;
8211: reg_rdata_next[13] = ip1_p45_qs;
8212: reg_rdata_next[14] = ip1_p46_qs;
8213: reg_rdata_next[15] = ip1_p47_qs;
8214: reg_rdata_next[16] = ip1_p48_qs;
8215: reg_rdata_next[17] = ip1_p49_qs;
8216: reg_rdata_next[18] = ip1_p50_qs;
8217: reg_rdata_next[19] = ip1_p51_qs;
8218: reg_rdata_next[20] = ip1_p52_qs;
8219: reg_rdata_next[21] = ip1_p53_qs;
8220: reg_rdata_next[22] = ip1_p54_qs;
8221: reg_rdata_next[23] = ip1_p55_qs;
8222: reg_rdata_next[24] = ip1_p56_qs;
8223: reg_rdata_next[25] = ip1_p57_qs;
8224: reg_rdata_next[26] = ip1_p58_qs;
8225: reg_rdata_next[27] = ip1_p59_qs;
8226: reg_rdata_next[28] = ip1_p60_qs;
8227: reg_rdata_next[29] = ip1_p61_qs;
8228: reg_rdata_next[30] = ip1_p62_qs;
8229: end
8230:
8231: addr_hit[2]: begin
8232: reg_rdata_next[0] = le0_le0_qs;
8233: reg_rdata_next[1] = le0_le1_qs;
8234: reg_rdata_next[2] = le0_le2_qs;
8235: reg_rdata_next[3] = le0_le3_qs;
8236: reg_rdata_next[4] = le0_le4_qs;
8237: reg_rdata_next[5] = le0_le5_qs;
8238: reg_rdata_next[6] = le0_le6_qs;
8239: reg_rdata_next[7] = le0_le7_qs;
8240: reg_rdata_next[8] = le0_le8_qs;
8241: reg_rdata_next[9] = le0_le9_qs;
8242: reg_rdata_next[10] = le0_le10_qs;
8243: reg_rdata_next[11] = le0_le11_qs;
8244: reg_rdata_next[12] = le0_le12_qs;
8245: reg_rdata_next[13] = le0_le13_qs;
8246: reg_rdata_next[14] = le0_le14_qs;
8247: reg_rdata_next[15] = le0_le15_qs;
8248: reg_rdata_next[16] = le0_le16_qs;
8249: reg_rdata_next[17] = le0_le17_qs;
8250: reg_rdata_next[18] = le0_le18_qs;
8251: reg_rdata_next[19] = le0_le19_qs;
8252: reg_rdata_next[20] = le0_le20_qs;
8253: reg_rdata_next[21] = le0_le21_qs;
8254: reg_rdata_next[22] = le0_le22_qs;
8255: reg_rdata_next[23] = le0_le23_qs;
8256: reg_rdata_next[24] = le0_le24_qs;
8257: reg_rdata_next[25] = le0_le25_qs;
8258: reg_rdata_next[26] = le0_le26_qs;
8259: reg_rdata_next[27] = le0_le27_qs;
8260: reg_rdata_next[28] = le0_le28_qs;
8261: reg_rdata_next[29] = le0_le29_qs;
8262: reg_rdata_next[30] = le0_le30_qs;
8263: reg_rdata_next[31] = le0_le31_qs;
8264: end
8265:
8266: addr_hit[3]: begin
8267: reg_rdata_next[0] = le1_le32_qs;
8268: reg_rdata_next[1] = le1_le33_qs;
8269: reg_rdata_next[2] = le1_le34_qs;
8270: reg_rdata_next[3] = le1_le35_qs;
8271: reg_rdata_next[4] = le1_le36_qs;
8272: reg_rdata_next[5] = le1_le37_qs;
8273: reg_rdata_next[6] = le1_le38_qs;
8274: reg_rdata_next[7] = le1_le39_qs;
8275: reg_rdata_next[8] = le1_le40_qs;
8276: reg_rdata_next[9] = le1_le41_qs;
8277: reg_rdata_next[10] = le1_le42_qs;
8278: reg_rdata_next[11] = le1_le43_qs;
8279: reg_rdata_next[12] = le1_le44_qs;
8280: reg_rdata_next[13] = le1_le45_qs;
8281: reg_rdata_next[14] = le1_le46_qs;
8282: reg_rdata_next[15] = le1_le47_qs;
8283: reg_rdata_next[16] = le1_le48_qs;
8284: reg_rdata_next[17] = le1_le49_qs;
8285: reg_rdata_next[18] = le1_le50_qs;
8286: reg_rdata_next[19] = le1_le51_qs;
8287: reg_rdata_next[20] = le1_le52_qs;
8288: reg_rdata_next[21] = le1_le53_qs;
8289: reg_rdata_next[22] = le1_le54_qs;
8290: reg_rdata_next[23] = le1_le55_qs;
8291: reg_rdata_next[24] = le1_le56_qs;
8292: reg_rdata_next[25] = le1_le57_qs;
8293: reg_rdata_next[26] = le1_le58_qs;
8294: reg_rdata_next[27] = le1_le59_qs;
8295: reg_rdata_next[28] = le1_le60_qs;
8296: reg_rdata_next[29] = le1_le61_qs;
8297: reg_rdata_next[30] = le1_le62_qs;
8298: end
8299:
8300: addr_hit[4]: begin
8301: reg_rdata_next[1:0] = prio0_qs;
8302: end
8303:
8304: addr_hit[5]: begin
8305: reg_rdata_next[1:0] = prio1_qs;
8306: end
8307:
8308: addr_hit[6]: begin
8309: reg_rdata_next[1:0] = prio2_qs;
8310: end
8311:
8312: addr_hit[7]: begin
8313: reg_rdata_next[1:0] = prio3_qs;
8314: end
8315:
8316: addr_hit[8]: begin
8317: reg_rdata_next[1:0] = prio4_qs;
8318: end
8319:
8320: addr_hit[9]: begin
8321: reg_rdata_next[1:0] = prio5_qs;
8322: end
8323:
8324: addr_hit[10]: begin
8325: reg_rdata_next[1:0] = prio6_qs;
8326: end
8327:
8328: addr_hit[11]: begin
8329: reg_rdata_next[1:0] = prio7_qs;
8330: end
8331:
8332: addr_hit[12]: begin
8333: reg_rdata_next[1:0] = prio8_qs;
8334: end
8335:
8336: addr_hit[13]: begin
8337: reg_rdata_next[1:0] = prio9_qs;
8338: end
8339:
8340: addr_hit[14]: begin
8341: reg_rdata_next[1:0] = prio10_qs;
8342: end
8343:
8344: addr_hit[15]: begin
8345: reg_rdata_next[1:0] = prio11_qs;
8346: end
8347:
8348: addr_hit[16]: begin
8349: reg_rdata_next[1:0] = prio12_qs;
8350: end
8351:
8352: addr_hit[17]: begin
8353: reg_rdata_next[1:0] = prio13_qs;
8354: end
8355:
8356: addr_hit[18]: begin
8357: reg_rdata_next[1:0] = prio14_qs;
8358: end
8359:
8360: addr_hit[19]: begin
8361: reg_rdata_next[1:0] = prio15_qs;
8362: end
8363:
8364: addr_hit[20]: begin
8365: reg_rdata_next[1:0] = prio16_qs;
8366: end
8367:
8368: addr_hit[21]: begin
8369: reg_rdata_next[1:0] = prio17_qs;
8370: end
8371:
8372: addr_hit[22]: begin
8373: reg_rdata_next[1:0] = prio18_qs;
8374: end
8375:
8376: addr_hit[23]: begin
8377: reg_rdata_next[1:0] = prio19_qs;
8378: end
8379:
8380: addr_hit[24]: begin
8381: reg_rdata_next[1:0] = prio20_qs;
8382: end
8383:
8384: addr_hit[25]: begin
8385: reg_rdata_next[1:0] = prio21_qs;
8386: end
8387:
8388: addr_hit[26]: begin
8389: reg_rdata_next[1:0] = prio22_qs;
8390: end
8391:
8392: addr_hit[27]: begin
8393: reg_rdata_next[1:0] = prio23_qs;
8394: end
8395:
8396: addr_hit[28]: begin
8397: reg_rdata_next[1:0] = prio24_qs;
8398: end
8399:
8400: addr_hit[29]: begin
8401: reg_rdata_next[1:0] = prio25_qs;
8402: end
8403:
8404: addr_hit[30]: begin
8405: reg_rdata_next[1:0] = prio26_qs;
8406: end
8407:
8408: addr_hit[31]: begin
8409: reg_rdata_next[1:0] = prio27_qs;
8410: end
8411:
8412: addr_hit[32]: begin
8413: reg_rdata_next[1:0] = prio28_qs;
8414: end
8415:
8416: addr_hit[33]: begin
8417: reg_rdata_next[1:0] = prio29_qs;
8418: end
8419:
8420: addr_hit[34]: begin
8421: reg_rdata_next[1:0] = prio30_qs;
8422: end
8423:
8424: addr_hit[35]: begin
8425: reg_rdata_next[1:0] = prio31_qs;
8426: end
8427:
8428: addr_hit[36]: begin
8429: reg_rdata_next[1:0] = prio32_qs;
8430: end
8431:
8432: addr_hit[37]: begin
8433: reg_rdata_next[1:0] = prio33_qs;
8434: end
8435:
8436: addr_hit[38]: begin
8437: reg_rdata_next[1:0] = prio34_qs;
8438: end
8439:
8440: addr_hit[39]: begin
8441: reg_rdata_next[1:0] = prio35_qs;
8442: end
8443:
8444: addr_hit[40]: begin
8445: reg_rdata_next[1:0] = prio36_qs;
8446: end
8447:
8448: addr_hit[41]: begin
8449: reg_rdata_next[1:0] = prio37_qs;
8450: end
8451:
8452: addr_hit[42]: begin
8453: reg_rdata_next[1:0] = prio38_qs;
8454: end
8455:
8456: addr_hit[43]: begin
8457: reg_rdata_next[1:0] = prio39_qs;
8458: end
8459:
8460: addr_hit[44]: begin
8461: reg_rdata_next[1:0] = prio40_qs;
8462: end
8463:
8464: addr_hit[45]: begin
8465: reg_rdata_next[1:0] = prio41_qs;
8466: end
8467:
8468: addr_hit[46]: begin
8469: reg_rdata_next[1:0] = prio42_qs;
8470: end
8471:
8472: addr_hit[47]: begin
8473: reg_rdata_next[1:0] = prio43_qs;
8474: end
8475:
8476: addr_hit[48]: begin
8477: reg_rdata_next[1:0] = prio44_qs;
8478: end
8479:
8480: addr_hit[49]: begin
8481: reg_rdata_next[1:0] = prio45_qs;
8482: end
8483:
8484: addr_hit[50]: begin
8485: reg_rdata_next[1:0] = prio46_qs;
8486: end
8487:
8488: addr_hit[51]: begin
8489: reg_rdata_next[1:0] = prio47_qs;
8490: end
8491:
8492: addr_hit[52]: begin
8493: reg_rdata_next[1:0] = prio48_qs;
8494: end
8495:
8496: addr_hit[53]: begin
8497: reg_rdata_next[1:0] = prio49_qs;
8498: end
8499:
8500: addr_hit[54]: begin
8501: reg_rdata_next[1:0] = prio50_qs;
8502: end
8503:
8504: addr_hit[55]: begin
8505: reg_rdata_next[1:0] = prio51_qs;
8506: end
8507:
8508: addr_hit[56]: begin
8509: reg_rdata_next[1:0] = prio52_qs;
8510: end
8511:
8512: addr_hit[57]: begin
8513: reg_rdata_next[1:0] = prio53_qs;
8514: end
8515:
8516: addr_hit[58]: begin
8517: reg_rdata_next[1:0] = prio54_qs;
8518: end
8519:
8520: addr_hit[59]: begin
8521: reg_rdata_next[1:0] = prio55_qs;
8522: end
8523:
8524: addr_hit[60]: begin
8525: reg_rdata_next[1:0] = prio56_qs;
8526: end
8527:
8528: addr_hit[61]: begin
8529: reg_rdata_next[1:0] = prio57_qs;
8530: end
8531:
8532: addr_hit[62]: begin
8533: reg_rdata_next[1:0] = prio58_qs;
8534: end
8535:
8536: addr_hit[63]: begin
8537: reg_rdata_next[1:0] = prio59_qs;
8538: end
8539:
8540: addr_hit[64]: begin
8541: reg_rdata_next[1:0] = prio60_qs;
8542: end
8543:
8544: addr_hit[65]: begin
8545: reg_rdata_next[1:0] = prio61_qs;
8546: end
8547:
8548: addr_hit[66]: begin
8549: reg_rdata_next[1:0] = prio62_qs;
8550: end
8551:
8552: addr_hit[67]: begin
8553: reg_rdata_next[0] = ie00_e0_qs;
8554: reg_rdata_next[1] = ie00_e1_qs;
8555: reg_rdata_next[2] = ie00_e2_qs;
8556: reg_rdata_next[3] = ie00_e3_qs;
8557: reg_rdata_next[4] = ie00_e4_qs;
8558: reg_rdata_next[5] = ie00_e5_qs;
8559: reg_rdata_next[6] = ie00_e6_qs;
8560: reg_rdata_next[7] = ie00_e7_qs;
8561: reg_rdata_next[8] = ie00_e8_qs;
8562: reg_rdata_next[9] = ie00_e9_qs;
8563: reg_rdata_next[10] = ie00_e10_qs;
8564: reg_rdata_next[11] = ie00_e11_qs;
8565: reg_rdata_next[12] = ie00_e12_qs;
8566: reg_rdata_next[13] = ie00_e13_qs;
8567: reg_rdata_next[14] = ie00_e14_qs;
8568: reg_rdata_next[15] = ie00_e15_qs;
8569: reg_rdata_next[16] = ie00_e16_qs;
8570: reg_rdata_next[17] = ie00_e17_qs;
8571: reg_rdata_next[18] = ie00_e18_qs;
8572: reg_rdata_next[19] = ie00_e19_qs;
8573: reg_rdata_next[20] = ie00_e20_qs;
8574: reg_rdata_next[21] = ie00_e21_qs;
8575: reg_rdata_next[22] = ie00_e22_qs;
8576: reg_rdata_next[23] = ie00_e23_qs;
8577: reg_rdata_next[24] = ie00_e24_qs;
8578: reg_rdata_next[25] = ie00_e25_qs;
8579: reg_rdata_next[26] = ie00_e26_qs;
8580: reg_rdata_next[27] = ie00_e27_qs;
8581: reg_rdata_next[28] = ie00_e28_qs;
8582: reg_rdata_next[29] = ie00_e29_qs;
8583: reg_rdata_next[30] = ie00_e30_qs;
8584: reg_rdata_next[31] = ie00_e31_qs;
8585: end
8586:
8587: addr_hit[68]: begin
8588: reg_rdata_next[0] = ie01_e32_qs;
8589: reg_rdata_next[1] = ie01_e33_qs;
8590: reg_rdata_next[2] = ie01_e34_qs;
8591: reg_rdata_next[3] = ie01_e35_qs;
8592: reg_rdata_next[4] = ie01_e36_qs;
8593: reg_rdata_next[5] = ie01_e37_qs;
8594: reg_rdata_next[6] = ie01_e38_qs;
8595: reg_rdata_next[7] = ie01_e39_qs;
8596: reg_rdata_next[8] = ie01_e40_qs;
8597: reg_rdata_next[9] = ie01_e41_qs;
8598: reg_rdata_next[10] = ie01_e42_qs;
8599: reg_rdata_next[11] = ie01_e43_qs;
8600: reg_rdata_next[12] = ie01_e44_qs;
8601: reg_rdata_next[13] = ie01_e45_qs;
8602: reg_rdata_next[14] = ie01_e46_qs;
8603: reg_rdata_next[15] = ie01_e47_qs;
8604: reg_rdata_next[16] = ie01_e48_qs;
8605: reg_rdata_next[17] = ie01_e49_qs;
8606: reg_rdata_next[18] = ie01_e50_qs;
8607: reg_rdata_next[19] = ie01_e51_qs;
8608: reg_rdata_next[20] = ie01_e52_qs;
8609: reg_rdata_next[21] = ie01_e53_qs;
8610: reg_rdata_next[22] = ie01_e54_qs;
8611: reg_rdata_next[23] = ie01_e55_qs;
8612: reg_rdata_next[24] = ie01_e56_qs;
8613: reg_rdata_next[25] = ie01_e57_qs;
8614: reg_rdata_next[26] = ie01_e58_qs;
8615: reg_rdata_next[27] = ie01_e59_qs;
8616: reg_rdata_next[28] = ie01_e60_qs;
8617: reg_rdata_next[29] = ie01_e61_qs;
8618: reg_rdata_next[30] = ie01_e62_qs;
8619: end
8620:
8621: addr_hit[69]: begin
8622: reg_rdata_next[1:0] = threshold0_qs;
8623: end
8624:
8625: addr_hit[70]: begin
8626: reg_rdata_next[5:0] = cc0_qs;
8627: end
8628:
8629: addr_hit[71]: begin
8630: reg_rdata_next[0] = msip0_qs;
8631: end
8632:
8633: default: begin
8634: reg_rdata_next = '1;
8635: end
8636: endcase
8637: end
8638:
8639: // Assertions for Register Interface
8640: `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
8641: `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
8642:
8643: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
8644:
8645: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
8646:
8647: // this is formulated as an assumption such that the FPV testbenches do disprove this
8648: // property by mistake
8649: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
8650:
8651: endmodule
8652: