../src/lowrisc_ip_rstmgr_0.1/rtl/rstmgr_info.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // This module records the reset reason
6: //
7:
8: `include "prim_assert.sv"
9:
10: module rstmgr_info #(
11: parameter int Reasons = 4
12: ) (
13: input clk_i,
14: input rst_ni,
15: input rst_cpu_ni,
16: input [Reasons-1:0] rst_req_i,
17: input wr_i,
18: input [Reasons:0] data_i, // inclusive of POR
19: output logic [Reasons:0] rst_reasons_o // inclusive of POR
20: );
21:
22: logic [Reasons-1:0] reasons;
23: logic por;
24: logic first_reset;
25: logic rst_cpu_nq;
26:
27: prim_flop_2sync #(
28: .Width(1),
29: .ResetValue(0)
30: ) u_cpu_reset_synced (
31: .clk_i(clk_i),
32: .rst_ni(rst_ni),
33: .d(rst_cpu_ni),
34: .q(rst_cpu_nq)
35: );
36:
37: // first reset is a flag that blocks reset recording until first de-assertion
38: always_ff @(posedge clk_i or negedge rst_ni) begin
39: if (!rst_ni) begin
40: first_reset <= 1'b1;
41: end else if (rst_cpu_nq) begin
42: first_reset <= 1'b0;
43: end
44: end
45:
46: // if cpu has gone into reset, record reset causes
47: // the reasons is a logical OR, so that signals that were once asserted do not go away.
48: always_ff @(posedge clk_i or negedge rst_ni) begin
49: if (!rst_ni) begin
50: por <= 1'b1;
51: reasons <= '0;
52: end else if (!rst_cpu_nq && !first_reset) begin
53: reasons <= reasons | rst_req_i;
54: end else if (wr_i) begin
55: {reasons, por} <= {reasons, por} & ~data_i;
56: end
57: end
58:
59: assign rst_reasons_o = {reasons, por};
60:
61: endmodule // rstmgr_info
62: