../src/lowrisc_ibex_ibex_pkg_0.1/rtl/ibex_pkg.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Copyright 2017 ETH Zurich and University of Bologna, see also CREDITS.md.
3: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
4: // SPDX-License-Identifier: Apache-2.0
5:
6: /**
7: * Package with constants used by Ibex
8: */
9: package ibex_pkg;
10:
11:
12: /////////////
13: // Opcodes //
14: /////////////
15:
16: typedef enum logic [6:0] {
17: OPCODE_LOAD = 7'h03,
18: OPCODE_MISC_MEM = 7'h0f,
19: OPCODE_OP_IMM = 7'h13,
20: OPCODE_AUIPC = 7'h17,
21: OPCODE_STORE = 7'h23,
22: OPCODE_OP = 7'h33,
23: OPCODE_LUI = 7'h37,
24: OPCODE_BRANCH = 7'h63,
25: OPCODE_JALR = 7'h67,
26: OPCODE_JAL = 7'h6f,
27: OPCODE_SYSTEM = 7'h73
28: } opcode_e;
29:
30:
31: ////////////////////
32: // ALU operations //
33: ////////////////////
34:
35: typedef enum logic [5:0] {
36: // Arithmetics
37: ALU_ADD,
38: ALU_SUB,
39:
40: // Logics
41: ALU_XOR,
42: ALU_OR,
43: ALU_AND,
44: // RV32B
45: ALU_XNOR,
46: ALU_ORN,
47: ALU_ANDN,
48:
49: // Shifts
50: ALU_SRA,
51: ALU_SRL,
52: ALU_SLL,
53: // RV32B
54: ALU_SRO,
55: ALU_SLO,
56: ALU_ROR,
57: ALU_ROL,
58: ALU_GREV,
59: ALU_GORC,
60: ALU_SHFL,
61: ALU_UNSHFL,
62:
63: // Comparisons
64: ALU_LT,
65: ALU_LTU,
66: ALU_GE,
67: ALU_GEU,
68: ALU_EQ,
69: ALU_NE,
70: // RV32B
71: ALU_MIN,
72: ALU_MINU,
73: ALU_MAX,
74: ALU_MAXU,
75:
76: // Pack
77: // RV32B
78: ALU_PACK,
79: ALU_PACKU,
80: ALU_PACKH,
81:
82: // Sign-Extend
83: // RV32B
84: ALU_SEXTB,
85: ALU_SEXTH,
86:
87: // Bitcounting
88: // RV32B
89: ALU_CLZ,
90: ALU_CTZ,
91: ALU_PCNT,
92:
93: // Set lower than
94: ALU_SLT,
95: ALU_SLTU,
96:
97: // Ternary Bitmanip Operations
98: // RV32B
99: ALU_CMOV,
100: ALU_CMIX,
101: ALU_FSL,
102: ALU_FSR,
103:
104: // Single-Bit Operations
105: // RV32B
106: ALU_SBSET,
107: ALU_SBCLR,
108: ALU_SBINV,
109: ALU_SBEXT,
110:
111: // Bit Extract / Deposit
112: // RV32B
113: ALU_BEXT,
114: ALU_BDEP,
115:
116: // Bit Field Place
117: // RV32B
118: ALU_BFP,
119:
120: // Carry-less Multiply
121: // RV32B
122: ALU_CLMUL,
123: ALU_CLMULR,
124: ALU_CLMULH,
125:
126: // Cyclic Redundancy Check
127: ALU_CRC32_B,
128: ALU_CRC32C_B,
129: ALU_CRC32_H,
130: ALU_CRC32C_H,
131: ALU_CRC32_W,
132: ALU_CRC32C_W
133: } alu_op_e;
134:
135: typedef enum logic [1:0] {
136: // Multiplier/divider
137: MD_OP_MULL,
138: MD_OP_MULH,
139: MD_OP_DIV,
140: MD_OP_REM
141: } md_op_e;
142:
143:
144: //////////////////////////////////
145: // Control and status registers //
146: //////////////////////////////////
147:
148: // CSR operations
149: typedef enum logic [1:0] {
150: CSR_OP_READ,
151: CSR_OP_WRITE,
152: CSR_OP_SET,
153: CSR_OP_CLEAR
154: } csr_op_e;
155:
156: // Privileged mode
157: typedef enum logic[1:0] {
158: PRIV_LVL_M = 2'b11,
159: PRIV_LVL_H = 2'b10,
160: PRIV_LVL_S = 2'b01,
161: PRIV_LVL_U = 2'b00
162: } priv_lvl_e;
163:
164: // Constants for the dcsr.xdebugver fields
165: typedef enum logic[3:0] {
166: XDEBUGVER_NO = 4'd0, // no external debug support
167: XDEBUGVER_STD = 4'd4, // external debug according to RISC-V debug spec
168: XDEBUGVER_NONSTD = 4'd15 // debug not conforming to RISC-V debug spec
169: } x_debug_ver_e;
170:
171: //////////////
172: // WB stage //
173: //////////////
174:
175: // Type of instruction present in writeback stage
176: typedef enum logic[1:0] {
177: WB_INSTR_LOAD, // Instruction is awaiting load data
178: WB_INSTR_STORE, // Instruction is awaiting store response
179: WB_INSTR_OTHER // Instruction doesn't fit into above categories
180: } wb_instr_type_e;
181:
182: //////////////
183: // ID stage //
184: //////////////
185:
186: // Operand a selection
187: typedef enum logic[1:0] {
188: OP_A_REG_A,
189: OP_A_FWD,
190: OP_A_CURRPC,
191: OP_A_IMM
192: } op_a_sel_e;
193:
194: // Immediate a selection
195: typedef enum logic {
196: IMM_A_Z,
197: IMM_A_ZERO
198: } imm_a_sel_e;
199:
200: // Operand b selection
201: typedef enum logic {
202: OP_B_REG_B,
203: OP_B_IMM
204: } op_b_sel_e;
205:
206: // Immediate b selection
207: typedef enum logic [2:0] {
208: IMM_B_I,
209: IMM_B_S,
210: IMM_B_B,
211: IMM_B_U,
212: IMM_B_J,
213: IMM_B_INCR_PC,
214: IMM_B_INCR_ADDR
215: } imm_b_sel_e;
216:
217: // Regfile write data selection
218: typedef enum logic {
219: RF_WD_EX,
220: RF_WD_CSR
221: } rf_wd_sel_e;
222:
223: //////////////
224: // IF stage //
225: //////////////
226:
227: // PC mux selection
228: typedef enum logic [2:0] {
229: PC_BOOT,
230: PC_JUMP,
231: PC_EXC,
232: PC_ERET,
233: PC_DRET
234: } pc_sel_e;
235:
236: // Exception PC mux selection
237: typedef enum logic [1:0] {
238: EXC_PC_EXC,
239: EXC_PC_IRQ,
240: EXC_PC_DBD,
241: EXC_PC_DBG_EXC // Exception while in debug mode
242: } exc_pc_sel_e;
243:
244: // Interrupt requests
245: typedef struct packed {
246: logic irq_software;
247: logic irq_timer;
248: logic irq_external;
249: logic [14:0] irq_fast; // 15 fast interrupts,
250: // one interrupt is reserved for NMI (not visible through mip/mie)
251: } irqs_t;
252:
253: // Exception cause
254: typedef enum logic [5:0] {
255: EXC_CAUSE_IRQ_SOFTWARE_M = {1'b1, 5'd03},
256: EXC_CAUSE_IRQ_TIMER_M = {1'b1, 5'd07},
257: EXC_CAUSE_IRQ_EXTERNAL_M = {1'b1, 5'd11},
258: // EXC_CAUSE_IRQ_FAST_0 = {1'b1, 5'd16},
259: // EXC_CAUSE_IRQ_FAST_14 = {1'b1, 5'd30},
260: EXC_CAUSE_IRQ_NM = {1'b1, 5'd31}, // == EXC_CAUSE_IRQ_FAST_15
261: EXC_CAUSE_INSN_ADDR_MISA = {1'b0, 5'd00},
262: EXC_CAUSE_INSTR_ACCESS_FAULT = {1'b0, 5'd01},
263: EXC_CAUSE_ILLEGAL_INSN = {1'b0, 5'd02},
264: EXC_CAUSE_BREAKPOINT = {1'b0, 5'd03},
265: EXC_CAUSE_LOAD_ACCESS_FAULT = {1'b0, 5'd05},
266: EXC_CAUSE_STORE_ACCESS_FAULT = {1'b0, 5'd07},
267: EXC_CAUSE_ECALL_UMODE = {1'b0, 5'd08},
268: EXC_CAUSE_ECALL_MMODE = {1'b0, 5'd11}
269: } exc_cause_e;
270:
271: // Debug cause
272: typedef enum logic [2:0] {
273: DBG_CAUSE_NONE = 3'h0,
274: DBG_CAUSE_EBREAK = 3'h1,
275: DBG_CAUSE_TRIGGER = 3'h2,
276: DBG_CAUSE_HALTREQ = 3'h3,
277: DBG_CAUSE_STEP = 3'h4
278: } dbg_cause_e;
279:
280: // PMP constants
281: parameter int unsigned PMP_MAX_REGIONS = 16;
282: parameter int unsigned PMP_CFG_W = 8;
283:
284: // PMP acces type
285: parameter int unsigned PMP_I = 0;
286: parameter int unsigned PMP_D = 1;
287:
288: typedef enum logic [1:0] {
289: PMP_ACC_EXEC = 2'b00,
290: PMP_ACC_WRITE = 2'b01,
291: PMP_ACC_READ = 2'b10
292: } pmp_req_e;
293:
294: // PMP cfg structures
295: typedef enum logic [1:0] {
296: PMP_MODE_OFF = 2'b00,
297: PMP_MODE_TOR = 2'b01,
298: PMP_MODE_NA4 = 2'b10,
299: PMP_MODE_NAPOT = 2'b11
300: } pmp_cfg_mode_e;
301:
302: typedef struct packed {
303: logic lock;
304: pmp_cfg_mode_e mode;
305: logic exec;
306: logic write;
307: logic read;
308: } pmp_cfg_t;
309:
310: // CSRs
311: typedef enum logic[11:0] {
312: // Machine information
313: CSR_MHARTID = 12'hF14,
314:
315: // Machine trap setup
316: CSR_MSTATUS = 12'h300,
317: CSR_MISA = 12'h301,
318: CSR_MIE = 12'h304,
319: CSR_MTVEC = 12'h305,
320:
321: // Machine trap handling
322: CSR_MSCRATCH = 12'h340,
323: CSR_MEPC = 12'h341,
324: CSR_MCAUSE = 12'h342,
325: CSR_MTVAL = 12'h343,
326: CSR_MIP = 12'h344,
327:
328: // Physical memory protection
329: CSR_PMPCFG0 = 12'h3A0,
330: CSR_PMPCFG1 = 12'h3A1,
331: CSR_PMPCFG2 = 12'h3A2,
332: CSR_PMPCFG3 = 12'h3A3,
333: CSR_PMPADDR0 = 12'h3B0,
334: CSR_PMPADDR1 = 12'h3B1,
335: CSR_PMPADDR2 = 12'h3B2,
336: CSR_PMPADDR3 = 12'h3B3,
337: CSR_PMPADDR4 = 12'h3B4,
338: CSR_PMPADDR5 = 12'h3B5,
339: CSR_PMPADDR6 = 12'h3B6,
340: CSR_PMPADDR7 = 12'h3B7,
341: CSR_PMPADDR8 = 12'h3B8,
342: CSR_PMPADDR9 = 12'h3B9,
343: CSR_PMPADDR10 = 12'h3BA,
344: CSR_PMPADDR11 = 12'h3BB,
345: CSR_PMPADDR12 = 12'h3BC,
346: CSR_PMPADDR13 = 12'h3BD,
347: CSR_PMPADDR14 = 12'h3BE,
348: CSR_PMPADDR15 = 12'h3BF,
349:
350: // Debug trigger
351: CSR_TSELECT = 12'h7A0,
352: CSR_TDATA1 = 12'h7A1,
353: CSR_TDATA2 = 12'h7A2,
354: CSR_TDATA3 = 12'h7A3,
355: CSR_MCONTEXT = 12'h7A8,
356: CSR_SCONTEXT = 12'h7AA,
357:
358: // Debug/trace
359: CSR_DCSR = 12'h7b0,
360: CSR_DPC = 12'h7b1,
361:
362: // Debug
363: CSR_DSCRATCH0 = 12'h7b2, // optional
364: CSR_DSCRATCH1 = 12'h7b3, // optional
365:
366: // Machine Counter/Timers
367: CSR_MCOUNTINHIBIT = 12'h320,
368: CSR_MHPMEVENT3 = 12'h323,
369: CSR_MHPMEVENT4 = 12'h324,
370: CSR_MHPMEVENT5 = 12'h325,
371: CSR_MHPMEVENT6 = 12'h326,
372: CSR_MHPMEVENT7 = 12'h327,
373: CSR_MHPMEVENT8 = 12'h328,
374: CSR_MHPMEVENT9 = 12'h329,
375: CSR_MHPMEVENT10 = 12'h32A,
376: CSR_MHPMEVENT11 = 12'h32B,
377: CSR_MHPMEVENT12 = 12'h32C,
378: CSR_MHPMEVENT13 = 12'h32D,
379: CSR_MHPMEVENT14 = 12'h32E,
380: CSR_MHPMEVENT15 = 12'h32F,
381: CSR_MHPMEVENT16 = 12'h330,
382: CSR_MHPMEVENT17 = 12'h331,
383: CSR_MHPMEVENT18 = 12'h332,
384: CSR_MHPMEVENT19 = 12'h333,
385: CSR_MHPMEVENT20 = 12'h334,
386: CSR_MHPMEVENT21 = 12'h335,
387: CSR_MHPMEVENT22 = 12'h336,
388: CSR_MHPMEVENT23 = 12'h337,
389: CSR_MHPMEVENT24 = 12'h338,
390: CSR_MHPMEVENT25 = 12'h339,
391: CSR_MHPMEVENT26 = 12'h33A,
392: CSR_MHPMEVENT27 = 12'h33B,
393: CSR_MHPMEVENT28 = 12'h33C,
394: CSR_MHPMEVENT29 = 12'h33D,
395: CSR_MHPMEVENT30 = 12'h33E,
396: CSR_MHPMEVENT31 = 12'h33F,
397: CSR_MCYCLE = 12'hB00,
398: CSR_MINSTRET = 12'hB02,
399: CSR_MHPMCOUNTER3 = 12'hB03,
400: CSR_MHPMCOUNTER4 = 12'hB04,
401: CSR_MHPMCOUNTER5 = 12'hB05,
402: CSR_MHPMCOUNTER6 = 12'hB06,
403: CSR_MHPMCOUNTER7 = 12'hB07,
404: CSR_MHPMCOUNTER8 = 12'hB08,
405: CSR_MHPMCOUNTER9 = 12'hB09,
406: CSR_MHPMCOUNTER10 = 12'hB0A,
407: CSR_MHPMCOUNTER11 = 12'hB0B,
408: CSR_MHPMCOUNTER12 = 12'hB0C,
409: CSR_MHPMCOUNTER13 = 12'hB0D,
410: CSR_MHPMCOUNTER14 = 12'hB0E,
411: CSR_MHPMCOUNTER15 = 12'hB0F,
412: CSR_MHPMCOUNTER16 = 12'hB10,
413: CSR_MHPMCOUNTER17 = 12'hB11,
414: CSR_MHPMCOUNTER18 = 12'hB12,
415: CSR_MHPMCOUNTER19 = 12'hB13,
416: CSR_MHPMCOUNTER20 = 12'hB14,
417: CSR_MHPMCOUNTER21 = 12'hB15,
418: CSR_MHPMCOUNTER22 = 12'hB16,
419: CSR_MHPMCOUNTER23 = 12'hB17,
420: CSR_MHPMCOUNTER24 = 12'hB18,
421: CSR_MHPMCOUNTER25 = 12'hB19,
422: CSR_MHPMCOUNTER26 = 12'hB1A,
423: CSR_MHPMCOUNTER27 = 12'hB1B,
424: CSR_MHPMCOUNTER28 = 12'hB1C,
425: CSR_MHPMCOUNTER29 = 12'hB1D,
426: CSR_MHPMCOUNTER30 = 12'hB1E,
427: CSR_MHPMCOUNTER31 = 12'hB1F,
428: CSR_MCYCLEH = 12'hB80,
429: CSR_MINSTRETH = 12'hB82,
430: CSR_MHPMCOUNTER3H = 12'hB83,
431: CSR_MHPMCOUNTER4H = 12'hB84,
432: CSR_MHPMCOUNTER5H = 12'hB85,
433: CSR_MHPMCOUNTER6H = 12'hB86,
434: CSR_MHPMCOUNTER7H = 12'hB87,
435: CSR_MHPMCOUNTER8H = 12'hB88,
436: CSR_MHPMCOUNTER9H = 12'hB89,
437: CSR_MHPMCOUNTER10H = 12'hB8A,
438: CSR_MHPMCOUNTER11H = 12'hB8B,
439: CSR_MHPMCOUNTER12H = 12'hB8C,
440: CSR_MHPMCOUNTER13H = 12'hB8D,
441: CSR_MHPMCOUNTER14H = 12'hB8E,
442: CSR_MHPMCOUNTER15H = 12'hB8F,
443: CSR_MHPMCOUNTER16H = 12'hB90,
444: CSR_MHPMCOUNTER17H = 12'hB91,
445: CSR_MHPMCOUNTER18H = 12'hB92,
446: CSR_MHPMCOUNTER19H = 12'hB93,
447: CSR_MHPMCOUNTER20H = 12'hB94,
448: CSR_MHPMCOUNTER21H = 12'hB95,
449: CSR_MHPMCOUNTER22H = 12'hB96,
450: CSR_MHPMCOUNTER23H = 12'hB97,
451: CSR_MHPMCOUNTER24H = 12'hB98,
452: CSR_MHPMCOUNTER25H = 12'hB99,
453: CSR_MHPMCOUNTER26H = 12'hB9A,
454: CSR_MHPMCOUNTER27H = 12'hB9B,
455: CSR_MHPMCOUNTER28H = 12'hB9C,
456: CSR_MHPMCOUNTER29H = 12'hB9D,
457: CSR_MHPMCOUNTER30H = 12'hB9E,
458: CSR_MHPMCOUNTER31H = 12'hB9F,
459: CSR_CPUCTRL = 12'h7C0,
460: CSR_SECURESEED = 12'h7C1
461: } csr_num_e;
462:
463: // CSR pmp-related offsets
464: parameter logic [11:0] CSR_OFF_PMP_CFG = 12'h3A0; // pmp_cfg @ 12'h3a0 - 12'h3a3
465: parameter logic [11:0] CSR_OFF_PMP_ADDR = 12'h3B0; // pmp_addr @ 12'h3b0 - 12'h3bf
466:
467: // CSR status bits
468: parameter int unsigned CSR_MSTATUS_MIE_BIT = 3;
469: parameter int unsigned CSR_MSTATUS_MPIE_BIT = 7;
470: parameter int unsigned CSR_MSTATUS_MPP_BIT_LOW = 11;
471: parameter int unsigned CSR_MSTATUS_MPP_BIT_HIGH = 12;
472: parameter int unsigned CSR_MSTATUS_MPRV_BIT = 17;
473: parameter int unsigned CSR_MSTATUS_TW_BIT = 21;
474:
475: // CSR machine ISA
476: parameter logic [1:0] CSR_MISA_MXL = 2'd1; // M-XLEN: XLEN in M-Mode for RV32
477:
478: // CSR interrupt pending/enable bits
479: parameter int unsigned CSR_MSIX_BIT = 3;
480: parameter int unsigned CSR_MTIX_BIT = 7;
481: parameter int unsigned CSR_MEIX_BIT = 11;
482: parameter int unsigned CSR_MFIX_BIT_LOW = 16;
483: parameter int unsigned CSR_MFIX_BIT_HIGH = 30;
484:
485: endpackage
486: