hw/ip/prim_xilinx/rtl/prim_xilinx_ram_2p.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Synchronous dual-port SRAM register model
   6: //   This module is for simulation and small size SRAM.
   7: //   Implementing ECC should be done inside wrapper not this model.
   8: 
   9: module prim_xilinx_ram_2p #(
  10:   parameter  int Width = 32, // bit
  11:   parameter  int Depth = 128,
  12: 
  13:   localparam int Aw    = $clog2(Depth)  // derived parameter
  14: ) (
  15:   input clk_a_i,
  16:   input clk_b_i,
  17: 
  18:   input                    a_req_i,
  19:   input                    a_write_i,
  20:   input        [Aw-1:0]    a_addr_i,
  21:   input        [Width-1:0] a_wdata_i,
  22:   output logic [Width-1:0] a_rdata_o,
  23: 
  24:   input                    b_req_i,
  25:   input                    b_write_i,
  26:   input        [Aw-1:0]    b_addr_i,
  27:   input        [Width-1:0] b_wdata_i,
  28:   output logic [Width-1:0] b_rdata_o
  29: );
  30: 
  31:   logic [Width-1:0] storage [Depth];
  32: 
  33:   // Xilinx FPGA specific Dual-port RAM coding style
  34:   always_ff @(posedge clk_a_i) begin
  35:     if (a_req_i) begin
  36:       if (a_write_i) begin
  37:         storage[a_addr_i] <= a_wdata_i;
  38:       end
  39:       a_rdata_o <= storage[a_addr_i];
  40:     end
  41:   end
  42: 
  43:   always_ff @(posedge clk_b_i) begin
  44:     if (b_req_i) begin
  45:       if (b_write_i) begin
  46:         storage[b_addr_i] <= b_wdata_i;
  47:       end
  48:       b_rdata_o <= storage[b_addr_i];
  49:     end
  50:   end
  51: 
  52: endmodule
  53: 
  54: