hw/vendor/lowrisc_ibex/rtl/ibex_register_file_ff.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Copyright 2018 ETH Zurich and University of Bologna, see also CREDITS.md.
3: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
4: // SPDX-License-Identifier: Apache-2.0
5:
6: /**
7: * RISC-V register file
8: *
9: * Register file with 31 or 15x 32 bit wide registers. Register 0 is fixed to 0.
10: * This register file is based on flip flops. Use this register file when
11: * targeting FPGA synthesis or Verilator simulation.
12: */
13: module ibex_register_file #(
14: parameter bit RV32E = 0,
15: parameter int unsigned DataWidth = 32
16: ) (
17: // Clock and Reset
18: input logic clk_i,
19: input logic rst_ni,
20:
21: input logic test_en_i,
22:
23: //Read port R1
24: input logic [4:0] raddr_a_i,
25: output logic [DataWidth-1:0] rdata_a_o,
26:
27: //Read port R2
28: input logic [4:0] raddr_b_i,
29: output logic [DataWidth-1:0] rdata_b_o,
30:
31:
32: // Write port W1
33: input logic [4:0] waddr_a_i,
34: input logic [DataWidth-1:0] wdata_a_i,
35: input logic we_a_i
36:
37: );
38:
39: localparam int unsigned ADDR_WIDTH = RV32E ? 4 : 5;
40: localparam int unsigned NUM_WORDS = 2**ADDR_WIDTH;
41:
42: logic [NUM_WORDS-1:0][DataWidth-1:0] rf_reg;
43: logic [NUM_WORDS-1:1][DataWidth-1:0] rf_reg_tmp;
44: logic [NUM_WORDS-1:1] we_a_dec;
45:
46: always_comb begin : we_a_decoder
47: for (int unsigned i = 1; i < NUM_WORDS; i++) begin
48: we_a_dec[i] = (waddr_a_i == 5'(i)) ? we_a_i : 1'b0;
49: end
50: end
51:
52: // loop from 1 to NUM_WORDS-1 as R0 is nil
53: always_ff @(posedge clk_i or negedge rst_ni) begin
54: if (!rst_ni) begin
55: rf_reg_tmp <= '{default:'0};
56: end else begin
57: for (int r = 1; r < NUM_WORDS; r++) begin
58: if (we_a_dec[r]) rf_reg_tmp[r] <= wdata_a_i;
59: end
60: end
61: end
62:
63: // R0 is nil
64: assign rf_reg[0] = '0;
65: assign rf_reg[NUM_WORDS-1:1] = rf_reg_tmp[NUM_WORDS-1:1];
66:
67: assign rdata_a_o = rf_reg[raddr_a_i];
68: assign rdata_b_o = rf_reg[raddr_b_i];
69:
70: endmodule
71: