../src/lowrisc_ip_gpio_0.1/rtl/gpio_reg_top.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Top module auto-generated by `reggen`
   6: 
   7: `include "prim_assert.sv"
   8: 
   9: module gpio_reg_top (
  10:   input clk_i,
  11:   input rst_ni,
  12: 
  13:   // Below Regster interface can be changed
  14:   input  tlul_pkg::tl_h2d_t tl_i,
  15:   output tlul_pkg::tl_d2h_t tl_o,
  16:   // To HW
  17:   output gpio_reg_pkg::gpio_reg2hw_t reg2hw, // Write
  18:   input  gpio_reg_pkg::gpio_hw2reg_t hw2reg, // Read
  19: 
  20:   // Config
  21:   input devmode_i // If 1, explicit error return for unmapped register access
  22: );
  23: 
  24:   import gpio_reg_pkg::* ;
  25: 
  26:   localparam int AW = 6;
  27:   localparam int DW = 32;
  28:   localparam int DBW = DW/8;                    // Byte Width
  29: 
  30:   // register signals
  31:   logic           reg_we;
  32:   logic           reg_re;
  33:   logic [AW-1:0]  reg_addr;
  34:   logic [DW-1:0]  reg_wdata;
  35:   logic [DBW-1:0] reg_be;
  36:   logic [DW-1:0]  reg_rdata;
  37:   logic           reg_error;
  38: 
  39:   logic          addrmiss, wr_err;
  40: 
  41:   logic [DW-1:0] reg_rdata_next;
  42: 
  43:   tlul_pkg::tl_h2d_t tl_reg_h2d;
  44:   tlul_pkg::tl_d2h_t tl_reg_d2h;
  45: 
  46:   assign tl_reg_h2d = tl_i;
  47:   assign tl_o       = tl_reg_d2h;
  48: 
  49:   tlul_adapter_reg #(
  50:     .RegAw(AW),
  51:     .RegDw(DW)
  52:   ) u_reg_if (
  53:     .clk_i,
  54:     .rst_ni,
  55: 
  56:     .tl_i (tl_reg_h2d),
  57:     .tl_o (tl_reg_d2h),
  58: 
  59:     .we_o    (reg_we),
  60:     .re_o    (reg_re),
  61:     .addr_o  (reg_addr),
  62:     .wdata_o (reg_wdata),
  63:     .be_o    (reg_be),
  64:     .rdata_i (reg_rdata),
  65:     .error_i (reg_error)
  66:   );
  67: 
  68:   assign reg_rdata = reg_rdata_next ;
  69:   assign reg_error = (devmode_i & addrmiss) | wr_err ;
  70: 
  71:   // Define SW related signals
  72:   // Format: __{wd|we|qs}
  73:   //        or _{wd|we|qs} if field == 1 or 0
  74:   logic [31:0] intr_state_qs;
  75:   logic [31:0] intr_state_wd;
  76:   logic intr_state_we;
  77:   logic [31:0] intr_enable_qs;
  78:   logic [31:0] intr_enable_wd;
  79:   logic intr_enable_we;
  80:   logic [31:0] intr_test_wd;
  81:   logic intr_test_we;
  82:   logic [31:0] data_in_qs;
  83:   logic [31:0] direct_out_qs;
  84:   logic [31:0] direct_out_wd;
  85:   logic direct_out_we;
  86:   logic direct_out_re;
  87:   logic [15:0] masked_out_lower_data_qs;
  88:   logic [15:0] masked_out_lower_data_wd;
  89:   logic masked_out_lower_data_we;
  90:   logic masked_out_lower_data_re;
  91:   logic [15:0] masked_out_lower_mask_wd;
  92:   logic masked_out_lower_mask_we;
  93:   logic [15:0] masked_out_upper_data_qs;
  94:   logic [15:0] masked_out_upper_data_wd;
  95:   logic masked_out_upper_data_we;
  96:   logic masked_out_upper_data_re;
  97:   logic [15:0] masked_out_upper_mask_wd;
  98:   logic masked_out_upper_mask_we;
  99:   logic [31:0] direct_oe_qs;
 100:   logic [31:0] direct_oe_wd;
 101:   logic direct_oe_we;
 102:   logic direct_oe_re;
 103:   logic [15:0] masked_oe_lower_data_qs;
 104:   logic [15:0] masked_oe_lower_data_wd;
 105:   logic masked_oe_lower_data_we;
 106:   logic masked_oe_lower_data_re;
 107:   logic [15:0] masked_oe_lower_mask_qs;
 108:   logic [15:0] masked_oe_lower_mask_wd;
 109:   logic masked_oe_lower_mask_we;
 110:   logic masked_oe_lower_mask_re;
 111:   logic [15:0] masked_oe_upper_data_qs;
 112:   logic [15:0] masked_oe_upper_data_wd;
 113:   logic masked_oe_upper_data_we;
 114:   logic masked_oe_upper_data_re;
 115:   logic [15:0] masked_oe_upper_mask_qs;
 116:   logic [15:0] masked_oe_upper_mask_wd;
 117:   logic masked_oe_upper_mask_we;
 118:   logic masked_oe_upper_mask_re;
 119:   logic [31:0] intr_ctrl_en_rising_qs;
 120:   logic [31:0] intr_ctrl_en_rising_wd;
 121:   logic intr_ctrl_en_rising_we;
 122:   logic [31:0] intr_ctrl_en_falling_qs;
 123:   logic [31:0] intr_ctrl_en_falling_wd;
 124:   logic intr_ctrl_en_falling_we;
 125:   logic [31:0] intr_ctrl_en_lvlhigh_qs;
 126:   logic [31:0] intr_ctrl_en_lvlhigh_wd;
 127:   logic intr_ctrl_en_lvlhigh_we;
 128:   logic [31:0] intr_ctrl_en_lvllow_qs;
 129:   logic [31:0] intr_ctrl_en_lvllow_wd;
 130:   logic intr_ctrl_en_lvllow_we;
 131:   logic [31:0] ctrl_en_input_filter_qs;
 132:   logic [31:0] ctrl_en_input_filter_wd;
 133:   logic ctrl_en_input_filter_we;
 134: 
 135:   // Register instances
 136:   // R[intr_state]: V(False)
 137: 
 138:   prim_subreg #(
 139:     .DW      (32),
 140:     .SWACCESS("W1C"),
 141:     .RESVAL  (32'h0)
 142:   ) u_intr_state (
 143:     .clk_i   (clk_i    ),
 144:     .rst_ni  (rst_ni  ),
 145: 
 146:     // from register interface
 147:     .we     (intr_state_we),
 148:     .wd     (intr_state_wd),
 149: 
 150:     // from internal hardware
 151:     .de     (hw2reg.intr_state.de),
 152:     .d      (hw2reg.intr_state.d ),
 153: 
 154:     // to internal hardware
 155:     .qe     (),
 156:     .q      (reg2hw.intr_state.q ),
 157: 
 158:     // to register interface (read)
 159:     .qs     (intr_state_qs)
 160:   );
 161: 
 162: 
 163:   // R[intr_enable]: V(False)
 164: 
 165:   prim_subreg #(
 166:     .DW      (32),
 167:     .SWACCESS("RW"),
 168:     .RESVAL  (32'h0)
 169:   ) u_intr_enable (
 170:     .clk_i   (clk_i    ),
 171:     .rst_ni  (rst_ni  ),
 172: 
 173:     // from register interface
 174:     .we     (intr_enable_we),
 175:     .wd     (intr_enable_wd),
 176: 
 177:     // from internal hardware
 178:     .de     (1'b0),
 179:     .d      ('0  ),
 180: 
 181:     // to internal hardware
 182:     .qe     (),
 183:     .q      (reg2hw.intr_enable.q ),
 184: 
 185:     // to register interface (read)
 186:     .qs     (intr_enable_qs)
 187:   );
 188: 
 189: 
 190:   // R[intr_test]: V(True)
 191: 
 192:   prim_subreg_ext #(
 193:     .DW    (32)
 194:   ) u_intr_test (
 195:     .re     (1'b0),
 196:     .we     (intr_test_we),
 197:     .wd     (intr_test_wd),
 198:     .d      ('0),
 199:     .qre    (),
 200:     .qe     (reg2hw.intr_test.qe),
 201:     .q      (reg2hw.intr_test.q ),
 202:     .qs     ()
 203:   );
 204: 
 205: 
 206:   // R[data_in]: V(False)
 207: 
 208:   prim_subreg #(
 209:     .DW      (32),
 210:     .SWACCESS("RO"),
 211:     .RESVAL  (32'h0)
 212:   ) u_data_in (
 213:     .clk_i   (clk_i    ),
 214:     .rst_ni  (rst_ni  ),
 215: 
 216:     .we     (1'b0),
 217:     .wd     ('0  ),
 218: 
 219:     // from internal hardware
 220:     .de     (hw2reg.data_in.de),
 221:     .d      (hw2reg.data_in.d ),
 222: 
 223:     // to internal hardware
 224:     .qe     (),
 225:     .q      (),
 226: 
 227:     // to register interface (read)
 228:     .qs     (data_in_qs)
 229:   );
 230: 
 231: 
 232:   // R[direct_out]: V(True)
 233: 
 234:   prim_subreg_ext #(
 235:     .DW    (32)
 236:   ) u_direct_out (
 237:     .re     (direct_out_re),
 238:     .we     (direct_out_we),
 239:     .wd     (direct_out_wd),
 240:     .d      (hw2reg.direct_out.d),
 241:     .qre    (),
 242:     .qe     (reg2hw.direct_out.qe),
 243:     .q      (reg2hw.direct_out.q ),
 244:     .qs     (direct_out_qs)
 245:   );
 246: 
 247: 
 248:   // R[masked_out_lower]: V(True)
 249: 
 250:   //   F[data]: 15:0
 251:   prim_subreg_ext #(
 252:     .DW    (16)
 253:   ) u_masked_out_lower_data (
 254:     .re     (masked_out_lower_data_re),
 255:     .we     (masked_out_lower_data_we),
 256:     .wd     (masked_out_lower_data_wd),
 257:     .d      (hw2reg.masked_out_lower.data.d),
 258:     .qre    (),
 259:     .qe     (reg2hw.masked_out_lower.data.qe),
 260:     .q      (reg2hw.masked_out_lower.data.q ),
 261:     .qs     (masked_out_lower_data_qs)
 262:   );
 263: 
 264: 
 265:   //   F[mask]: 31:16
 266:   prim_subreg_ext #(
 267:     .DW    (16)
 268:   ) u_masked_out_lower_mask (
 269:     .re     (1'b0),
 270:     .we     (masked_out_lower_mask_we),
 271:     .wd     (masked_out_lower_mask_wd),
 272:     .d      (hw2reg.masked_out_lower.mask.d),
 273:     .qre    (),
 274:     .qe     (reg2hw.masked_out_lower.mask.qe),
 275:     .q      (reg2hw.masked_out_lower.mask.q ),
 276:     .qs     ()
 277:   );
 278: 
 279: 
 280:   // R[masked_out_upper]: V(True)
 281: 
 282:   //   F[data]: 15:0
 283:   prim_subreg_ext #(
 284:     .DW    (16)
 285:   ) u_masked_out_upper_data (
 286:     .re     (masked_out_upper_data_re),
 287:     .we     (masked_out_upper_data_we),
 288:     .wd     (masked_out_upper_data_wd),
 289:     .d      (hw2reg.masked_out_upper.data.d),
 290:     .qre    (),
 291:     .qe     (reg2hw.masked_out_upper.data.qe),
 292:     .q      (reg2hw.masked_out_upper.data.q ),
 293:     .qs     (masked_out_upper_data_qs)
 294:   );
 295: 
 296: 
 297:   //   F[mask]: 31:16
 298:   prim_subreg_ext #(
 299:     .DW    (16)
 300:   ) u_masked_out_upper_mask (
 301:     .re     (1'b0),
 302:     .we     (masked_out_upper_mask_we),
 303:     .wd     (masked_out_upper_mask_wd),
 304:     .d      (hw2reg.masked_out_upper.mask.d),
 305:     .qre    (),
 306:     .qe     (reg2hw.masked_out_upper.mask.qe),
 307:     .q      (reg2hw.masked_out_upper.mask.q ),
 308:     .qs     ()
 309:   );
 310: 
 311: 
 312:   // R[direct_oe]: V(True)
 313: 
 314:   prim_subreg_ext #(
 315:     .DW    (32)
 316:   ) u_direct_oe (
 317:     .re     (direct_oe_re),
 318:     .we     (direct_oe_we),
 319:     .wd     (direct_oe_wd),
 320:     .d      (hw2reg.direct_oe.d),
 321:     .qre    (),
 322:     .qe     (reg2hw.direct_oe.qe),
 323:     .q      (reg2hw.direct_oe.q ),
 324:     .qs     (direct_oe_qs)
 325:   );
 326: 
 327: 
 328:   // R[masked_oe_lower]: V(True)
 329: 
 330:   //   F[data]: 15:0
 331:   prim_subreg_ext #(
 332:     .DW    (16)
 333:   ) u_masked_oe_lower_data (
 334:     .re     (masked_oe_lower_data_re),
 335:     .we     (masked_oe_lower_data_we),
 336:     .wd     (masked_oe_lower_data_wd),
 337:     .d      (hw2reg.masked_oe_lower.data.d),
 338:     .qre    (),
 339:     .qe     (reg2hw.masked_oe_lower.data.qe),
 340:     .q      (reg2hw.masked_oe_lower.data.q ),
 341:     .qs     (masked_oe_lower_data_qs)
 342:   );
 343: 
 344: 
 345:   //   F[mask]: 31:16
 346:   prim_subreg_ext #(
 347:     .DW    (16)
 348:   ) u_masked_oe_lower_mask (
 349:     .re     (masked_oe_lower_mask_re),
 350:     .we     (masked_oe_lower_mask_we),
 351:     .wd     (masked_oe_lower_mask_wd),
 352:     .d      (hw2reg.masked_oe_lower.mask.d),
 353:     .qre    (),
 354:     .qe     (reg2hw.masked_oe_lower.mask.qe),
 355:     .q      (reg2hw.masked_oe_lower.mask.q ),
 356:     .qs     (masked_oe_lower_mask_qs)
 357:   );
 358: 
 359: 
 360:   // R[masked_oe_upper]: V(True)
 361: 
 362:   //   F[data]: 15:0
 363:   prim_subreg_ext #(
 364:     .DW    (16)
 365:   ) u_masked_oe_upper_data (
 366:     .re     (masked_oe_upper_data_re),
 367:     .we     (masked_oe_upper_data_we),
 368:     .wd     (masked_oe_upper_data_wd),
 369:     .d      (hw2reg.masked_oe_upper.data.d),
 370:     .qre    (),
 371:     .qe     (reg2hw.masked_oe_upper.data.qe),
 372:     .q      (reg2hw.masked_oe_upper.data.q ),
 373:     .qs     (masked_oe_upper_data_qs)
 374:   );
 375: 
 376: 
 377:   //   F[mask]: 31:16
 378:   prim_subreg_ext #(
 379:     .DW    (16)
 380:   ) u_masked_oe_upper_mask (
 381:     .re     (masked_oe_upper_mask_re),
 382:     .we     (masked_oe_upper_mask_we),
 383:     .wd     (masked_oe_upper_mask_wd),
 384:     .d      (hw2reg.masked_oe_upper.mask.d),
 385:     .qre    (),
 386:     .qe     (reg2hw.masked_oe_upper.mask.qe),
 387:     .q      (reg2hw.masked_oe_upper.mask.q ),
 388:     .qs     (masked_oe_upper_mask_qs)
 389:   );
 390: 
 391: 
 392:   // R[intr_ctrl_en_rising]: V(False)
 393: 
 394:   prim_subreg #(
 395:     .DW      (32),
 396:     .SWACCESS("RW"),
 397:     .RESVAL  (32'h0)
 398:   ) u_intr_ctrl_en_rising (
 399:     .clk_i   (clk_i    ),
 400:     .rst_ni  (rst_ni  ),
 401: 
 402:     // from register interface
 403:     .we     (intr_ctrl_en_rising_we),
 404:     .wd     (intr_ctrl_en_rising_wd),
 405: 
 406:     // from internal hardware
 407:     .de     (1'b0),
 408:     .d      ('0  ),
 409: 
 410:     // to internal hardware
 411:     .qe     (),
 412:     .q      (reg2hw.intr_ctrl_en_rising.q ),
 413: 
 414:     // to register interface (read)
 415:     .qs     (intr_ctrl_en_rising_qs)
 416:   );
 417: 
 418: 
 419:   // R[intr_ctrl_en_falling]: V(False)
 420: 
 421:   prim_subreg #(
 422:     .DW      (32),
 423:     .SWACCESS("RW"),
 424:     .RESVAL  (32'h0)
 425:   ) u_intr_ctrl_en_falling (
 426:     .clk_i   (clk_i    ),
 427:     .rst_ni  (rst_ni  ),
 428: 
 429:     // from register interface
 430:     .we     (intr_ctrl_en_falling_we),
 431:     .wd     (intr_ctrl_en_falling_wd),
 432: 
 433:     // from internal hardware
 434:     .de     (1'b0),
 435:     .d      ('0  ),
 436: 
 437:     // to internal hardware
 438:     .qe     (),
 439:     .q      (reg2hw.intr_ctrl_en_falling.q ),
 440: 
 441:     // to register interface (read)
 442:     .qs     (intr_ctrl_en_falling_qs)
 443:   );
 444: 
 445: 
 446:   // R[intr_ctrl_en_lvlhigh]: V(False)
 447: 
 448:   prim_subreg #(
 449:     .DW      (32),
 450:     .SWACCESS("RW"),
 451:     .RESVAL  (32'h0)
 452:   ) u_intr_ctrl_en_lvlhigh (
 453:     .clk_i   (clk_i    ),
 454:     .rst_ni  (rst_ni  ),
 455: 
 456:     // from register interface
 457:     .we     (intr_ctrl_en_lvlhigh_we),
 458:     .wd     (intr_ctrl_en_lvlhigh_wd),
 459: 
 460:     // from internal hardware
 461:     .de     (1'b0),
 462:     .d      ('0  ),
 463: 
 464:     // to internal hardware
 465:     .qe     (),
 466:     .q      (reg2hw.intr_ctrl_en_lvlhigh.q ),
 467: 
 468:     // to register interface (read)
 469:     .qs     (intr_ctrl_en_lvlhigh_qs)
 470:   );
 471: 
 472: 
 473:   // R[intr_ctrl_en_lvllow]: V(False)
 474: 
 475:   prim_subreg #(
 476:     .DW      (32),
 477:     .SWACCESS("RW"),
 478:     .RESVAL  (32'h0)
 479:   ) u_intr_ctrl_en_lvllow (
 480:     .clk_i   (clk_i    ),
 481:     .rst_ni  (rst_ni  ),
 482: 
 483:     // from register interface
 484:     .we     (intr_ctrl_en_lvllow_we),
 485:     .wd     (intr_ctrl_en_lvllow_wd),
 486: 
 487:     // from internal hardware
 488:     .de     (1'b0),
 489:     .d      ('0  ),
 490: 
 491:     // to internal hardware
 492:     .qe     (),
 493:     .q      (reg2hw.intr_ctrl_en_lvllow.q ),
 494: 
 495:     // to register interface (read)
 496:     .qs     (intr_ctrl_en_lvllow_qs)
 497:   );
 498: 
 499: 
 500:   // R[ctrl_en_input_filter]: V(False)
 501: 
 502:   prim_subreg #(
 503:     .DW      (32),
 504:     .SWACCESS("RW"),
 505:     .RESVAL  (32'h0)
 506:   ) u_ctrl_en_input_filter (
 507:     .clk_i   (clk_i    ),
 508:     .rst_ni  (rst_ni  ),
 509: 
 510:     // from register interface
 511:     .we     (ctrl_en_input_filter_we),
 512:     .wd     (ctrl_en_input_filter_wd),
 513: 
 514:     // from internal hardware
 515:     .de     (1'b0),
 516:     .d      ('0  ),
 517: 
 518:     // to internal hardware
 519:     .qe     (),
 520:     .q      (reg2hw.ctrl_en_input_filter.q ),
 521: 
 522:     // to register interface (read)
 523:     .qs     (ctrl_en_input_filter_qs)
 524:   );
 525: 
 526: 
 527: 
 528: 
 529:   logic [14:0] addr_hit;
 530:   always_comb begin
 531:     addr_hit = '0;
 532:     addr_hit[ 0] = (reg_addr == GPIO_INTR_STATE_OFFSET);
 533:     addr_hit[ 1] = (reg_addr == GPIO_INTR_ENABLE_OFFSET);
 534:     addr_hit[ 2] = (reg_addr == GPIO_INTR_TEST_OFFSET);
 535:     addr_hit[ 3] = (reg_addr == GPIO_DATA_IN_OFFSET);
 536:     addr_hit[ 4] = (reg_addr == GPIO_DIRECT_OUT_OFFSET);
 537:     addr_hit[ 5] = (reg_addr == GPIO_MASKED_OUT_LOWER_OFFSET);
 538:     addr_hit[ 6] = (reg_addr == GPIO_MASKED_OUT_UPPER_OFFSET);
 539:     addr_hit[ 7] = (reg_addr == GPIO_DIRECT_OE_OFFSET);
 540:     addr_hit[ 8] = (reg_addr == GPIO_MASKED_OE_LOWER_OFFSET);
 541:     addr_hit[ 9] = (reg_addr == GPIO_MASKED_OE_UPPER_OFFSET);
 542:     addr_hit[10] = (reg_addr == GPIO_INTR_CTRL_EN_RISING_OFFSET);
 543:     addr_hit[11] = (reg_addr == GPIO_INTR_CTRL_EN_FALLING_OFFSET);
 544:     addr_hit[12] = (reg_addr == GPIO_INTR_CTRL_EN_LVLHIGH_OFFSET);
 545:     addr_hit[13] = (reg_addr == GPIO_INTR_CTRL_EN_LVLLOW_OFFSET);
 546:     addr_hit[14] = (reg_addr == GPIO_CTRL_EN_INPUT_FILTER_OFFSET);
 547:   end
 548: 
 549:   assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
 550: 
 551:   // Check sub-word write is permitted
 552:   always_comb begin
 553:     wr_err = 1'b0;
 554:     if (addr_hit[ 0] && reg_we && (GPIO_PERMIT[ 0] != (GPIO_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
 555:     if (addr_hit[ 1] && reg_we && (GPIO_PERMIT[ 1] != (GPIO_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
 556:     if (addr_hit[ 2] && reg_we && (GPIO_PERMIT[ 2] != (GPIO_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
 557:     if (addr_hit[ 3] && reg_we && (GPIO_PERMIT[ 3] != (GPIO_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
 558:     if (addr_hit[ 4] && reg_we && (GPIO_PERMIT[ 4] != (GPIO_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
 559:     if (addr_hit[ 5] && reg_we && (GPIO_PERMIT[ 5] != (GPIO_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
 560:     if (addr_hit[ 6] && reg_we && (GPIO_PERMIT[ 6] != (GPIO_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
 561:     if (addr_hit[ 7] && reg_we && (GPIO_PERMIT[ 7] != (GPIO_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
 562:     if (addr_hit[ 8] && reg_we && (GPIO_PERMIT[ 8] != (GPIO_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
 563:     if (addr_hit[ 9] && reg_we && (GPIO_PERMIT[ 9] != (GPIO_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
 564:     if (addr_hit[10] && reg_we && (GPIO_PERMIT[10] != (GPIO_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
 565:     if (addr_hit[11] && reg_we && (GPIO_PERMIT[11] != (GPIO_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
 566:     if (addr_hit[12] && reg_we && (GPIO_PERMIT[12] != (GPIO_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
 567:     if (addr_hit[13] && reg_we && (GPIO_PERMIT[13] != (GPIO_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
 568:     if (addr_hit[14] && reg_we && (GPIO_PERMIT[14] != (GPIO_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
 569:   end
 570: 
 571:   assign intr_state_we = addr_hit[0] & reg_we & ~wr_err;
 572:   assign intr_state_wd = reg_wdata[31:0];
 573: 
 574:   assign intr_enable_we = addr_hit[1] & reg_we & ~wr_err;
 575:   assign intr_enable_wd = reg_wdata[31:0];
 576: 
 577:   assign intr_test_we = addr_hit[2] & reg_we & ~wr_err;
 578:   assign intr_test_wd = reg_wdata[31:0];
 579: 
 580: 
 581:   assign direct_out_we = addr_hit[4] & reg_we & ~wr_err;
 582:   assign direct_out_wd = reg_wdata[31:0];
 583:   assign direct_out_re = addr_hit[4] && reg_re;
 584: 
 585:   assign masked_out_lower_data_we = addr_hit[5] & reg_we & ~wr_err;
 586:   assign masked_out_lower_data_wd = reg_wdata[15:0];
 587:   assign masked_out_lower_data_re = addr_hit[5] && reg_re;
 588: 
 589:   assign masked_out_lower_mask_we = addr_hit[5] & reg_we & ~wr_err;
 590:   assign masked_out_lower_mask_wd = reg_wdata[31:16];
 591: 
 592:   assign masked_out_upper_data_we = addr_hit[6] & reg_we & ~wr_err;
 593:   assign masked_out_upper_data_wd = reg_wdata[15:0];
 594:   assign masked_out_upper_data_re = addr_hit[6] && reg_re;
 595: 
 596:   assign masked_out_upper_mask_we = addr_hit[6] & reg_we & ~wr_err;
 597:   assign masked_out_upper_mask_wd = reg_wdata[31:16];
 598: 
 599:   assign direct_oe_we = addr_hit[7] & reg_we & ~wr_err;
 600:   assign direct_oe_wd = reg_wdata[31:0];
 601:   assign direct_oe_re = addr_hit[7] && reg_re;
 602: 
 603:   assign masked_oe_lower_data_we = addr_hit[8] & reg_we & ~wr_err;
 604:   assign masked_oe_lower_data_wd = reg_wdata[15:0];
 605:   assign masked_oe_lower_data_re = addr_hit[8] && reg_re;
 606: 
 607:   assign masked_oe_lower_mask_we = addr_hit[8] & reg_we & ~wr_err;
 608:   assign masked_oe_lower_mask_wd = reg_wdata[31:16];
 609:   assign masked_oe_lower_mask_re = addr_hit[8] && reg_re;
 610: 
 611:   assign masked_oe_upper_data_we = addr_hit[9] & reg_we & ~wr_err;
 612:   assign masked_oe_upper_data_wd = reg_wdata[15:0];
 613:   assign masked_oe_upper_data_re = addr_hit[9] && reg_re;
 614: 
 615:   assign masked_oe_upper_mask_we = addr_hit[9] & reg_we & ~wr_err;
 616:   assign masked_oe_upper_mask_wd = reg_wdata[31:16];
 617:   assign masked_oe_upper_mask_re = addr_hit[9] && reg_re;
 618: 
 619:   assign intr_ctrl_en_rising_we = addr_hit[10] & reg_we & ~wr_err;
 620:   assign intr_ctrl_en_rising_wd = reg_wdata[31:0];
 621: 
 622:   assign intr_ctrl_en_falling_we = addr_hit[11] & reg_we & ~wr_err;
 623:   assign intr_ctrl_en_falling_wd = reg_wdata[31:0];
 624: 
 625:   assign intr_ctrl_en_lvlhigh_we = addr_hit[12] & reg_we & ~wr_err;
 626:   assign intr_ctrl_en_lvlhigh_wd = reg_wdata[31:0];
 627: 
 628:   assign intr_ctrl_en_lvllow_we = addr_hit[13] & reg_we & ~wr_err;
 629:   assign intr_ctrl_en_lvllow_wd = reg_wdata[31:0];
 630: 
 631:   assign ctrl_en_input_filter_we = addr_hit[14] & reg_we & ~wr_err;
 632:   assign ctrl_en_input_filter_wd = reg_wdata[31:0];
 633: 
 634:   // Read data return
 635:   always_comb begin
 636:     reg_rdata_next = '0;
 637:     unique case (1'b1)
 638:       addr_hit[0]: begin
 639:         reg_rdata_next[31:0] = intr_state_qs;
 640:       end
 641: 
 642:       addr_hit[1]: begin
 643:         reg_rdata_next[31:0] = intr_enable_qs;
 644:       end
 645: 
 646:       addr_hit[2]: begin
 647:         reg_rdata_next[31:0] = '0;
 648:       end
 649: 
 650:       addr_hit[3]: begin
 651:         reg_rdata_next[31:0] = data_in_qs;
 652:       end
 653: 
 654:       addr_hit[4]: begin
 655:         reg_rdata_next[31:0] = direct_out_qs;
 656:       end
 657: 
 658:       addr_hit[5]: begin
 659:         reg_rdata_next[15:0] = masked_out_lower_data_qs;
 660:         reg_rdata_next[31:16] = '0;
 661:       end
 662: 
 663:       addr_hit[6]: begin
 664:         reg_rdata_next[15:0] = masked_out_upper_data_qs;
 665:         reg_rdata_next[31:16] = '0;
 666:       end
 667: 
 668:       addr_hit[7]: begin
 669:         reg_rdata_next[31:0] = direct_oe_qs;
 670:       end
 671: 
 672:       addr_hit[8]: begin
 673:         reg_rdata_next[15:0] = masked_oe_lower_data_qs;
 674:         reg_rdata_next[31:16] = masked_oe_lower_mask_qs;
 675:       end
 676: 
 677:       addr_hit[9]: begin
 678:         reg_rdata_next[15:0] = masked_oe_upper_data_qs;
 679:         reg_rdata_next[31:16] = masked_oe_upper_mask_qs;
 680:       end
 681: 
 682:       addr_hit[10]: begin
 683:         reg_rdata_next[31:0] = intr_ctrl_en_rising_qs;
 684:       end
 685: 
 686:       addr_hit[11]: begin
 687:         reg_rdata_next[31:0] = intr_ctrl_en_falling_qs;
 688:       end
 689: 
 690:       addr_hit[12]: begin
 691:         reg_rdata_next[31:0] = intr_ctrl_en_lvlhigh_qs;
 692:       end
 693: 
 694:       addr_hit[13]: begin
 695:         reg_rdata_next[31:0] = intr_ctrl_en_lvllow_qs;
 696:       end
 697: 
 698:       addr_hit[14]: begin
 699:         reg_rdata_next[31:0] = ctrl_en_input_filter_qs;
 700:       end
 701: 
 702:       default: begin
 703:         reg_rdata_next = '1;
 704:       end
 705:     endcase
 706:   end
 707: 
 708:   // Assertions for Register Interface
 709:   `ASSERT_PULSE(wePulse, reg_we)
 710:   `ASSERT_PULSE(rePulse, reg_re)
 711: 
 712:   `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid)
 713: 
 714:   `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit))
 715: 
 716:   // this is formulated as an assumption such that the FPV testbenches do disprove this
 717:   // property by mistake
 718:   `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0)
 719: 
 720: endmodule
 721: