hw/vendor/pulp_riscv_dbg/src/dmi_cdc.sv Cov: 100%
1: /* Copyright 2018 ETH Zurich and University of Bologna.
2: * Copyright and related rights are licensed under the Solderpad Hardware
3: * License, Version 0.51 (the “License”); you may not use this file except in
4: * compliance with the License. You may obtain a copy of the License at
5: * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
6: * or agreed to in writing, software, hardware and materials distributed under
7: * this License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR
8: * CONDITIONS OF ANY KIND, either express or implied. See the License for the
9: * specific language governing permissions and limitations under the License.
10: *
11: * File: axi_riscv_debug_module.sv
12: * Author: Andreas Traber
13: * Author: Florian Zaruba
14: *
15: * Description: Clock domain crossings for JTAG to DMI very heavily based
16: * on previous work by Andreas Traber for the PULP project.
17: * This is mainly a wrapper around the existing CDCs.
18: */
19: module dmi_cdc (
20: // JTAG side (master side)
21: input logic tck_i,
22: input logic trst_ni,
23:
24: input dm::dmi_req_t jtag_dmi_req_i,
25: output logic jtag_dmi_ready_o,
26: input logic jtag_dmi_valid_i,
27:
28: output dm::dmi_resp_t jtag_dmi_resp_o,
29: output logic jtag_dmi_valid_o,
30: input logic jtag_dmi_ready_i,
31:
32: // core side (slave side)
33: input logic clk_i,
34: input logic rst_ni,
35:
36: output dm::dmi_req_t core_dmi_req_o,
37: output logic core_dmi_valid_o,
38: input logic core_dmi_ready_i,
39:
40: input dm::dmi_resp_t core_dmi_resp_i,
41: output logic core_dmi_ready_o,
42: input logic core_dmi_valid_i
43: );
44:
45: // TODO: Make it clean for synthesis.
46:
47: prim_fifo_async #(
48: .Width( $bits(dm::dmi_req_t) ),
49: .Depth( 4 )
50: ) i_cdc_req (
51: .clk_wr_i ( tck_i ),
52: .rst_wr_ni ( trst_ni ),
53: .wvalid ( jtag_dmi_valid_i ),
54: .wready ( jtag_dmi_ready_o ), // wrclk
55: .wdata ( jtag_dmi_req_i ),
56: .wdepth ( ),
57:
58: .clk_rd_i ( clk_i ),
59: .rst_rd_ni ( rst_ni ),
60: .rvalid ( core_dmi_valid_o ),
61: .rready ( core_dmi_ready_i ),
62: .rdata ( core_dmi_req_o ),
63: .rdepth ( )
64: );
65:
66: prim_fifo_async #(
67: .Width( $bits(dm::dmi_resp_t) ),
68: .Depth( 4 )
69: ) i_cdc_resp (
70: .clk_wr_i ( clk_i ),
71: .rst_wr_ni ( rst_ni ),
72: .wvalid ( core_dmi_valid_i ),
73: .wready ( core_dmi_ready_o ), // wrclk
74: .wdata ( core_dmi_resp_i ),
75: .wdepth ( ),
76:
77: .clk_rd_i ( tck_i ),
78: .rst_rd_ni ( trst_ni ),
79: .rvalid ( jtag_dmi_valid_o ),
80: .rready ( jtag_dmi_ready_i ),
81: .rdata ( jtag_dmi_resp_o ),
82: .rdepth ( )
83: );
84:
85: endmodule : dmi_cdc
86: