hw/ip/usbdev/rtl/usbdev_reg_top.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Register Top module auto-generated by `reggen`
6:
7: module usbdev_reg_top (
8: input clk_i,
9: input rst_ni,
10:
11: // Below Regster interface can be changed
12: input tlul_pkg::tl_h2d_t tl_i,
13: output tlul_pkg::tl_d2h_t tl_o,
14:
15: // Output port for window
16: output tlul_pkg::tl_h2d_t tl_win_o [1],
17: input tlul_pkg::tl_d2h_t tl_win_i [1],
18:
19: // To HW
20: output usbdev_reg_pkg::usbdev_reg2hw_t reg2hw, // Write
21: input usbdev_reg_pkg::usbdev_hw2reg_t hw2reg, // Read
22:
23: // Config
24: input devmode_i // If 1, explicit error return for unmapped register access
25: );
26:
27: import usbdev_reg_pkg::* ;
28:
29: localparam int AW = 12;
30: localparam int DW = 32;
31: localparam int DBW = DW/8; // Byte Width
32:
33: // register signals
34: logic reg_we;
35: logic reg_re;
36: logic [AW-1:0] reg_addr;
37: logic [DW-1:0] reg_wdata;
38: logic [DBW-1:0] reg_be;
39: logic [DW-1:0] reg_rdata;
40: logic reg_error;
41:
42: logic addrmiss, wr_err;
43:
44: logic [DW-1:0] reg_rdata_next;
45:
46: tlul_pkg::tl_h2d_t tl_reg_h2d;
47: tlul_pkg::tl_d2h_t tl_reg_d2h;
48:
49: tlul_pkg::tl_h2d_t tl_socket_h2d [2];
50: tlul_pkg::tl_d2h_t tl_socket_d2h [2];
51:
52: logic [1:0] reg_steer;
53:
54: // socket_1n connection
55: assign tl_reg_h2d = tl_socket_h2d[1];
56: assign tl_socket_d2h[1] = tl_reg_d2h;
57:
58: assign tl_win_o[0] = tl_socket_h2d[0];
59: assign tl_socket_d2h[0] = tl_win_i[0];
60:
61: // Create Socket_1n
62: tlul_socket_1n #(
63: .N (2),
64: .HReqPass (1'b1),
65: .HRspPass (1'b1),
66: .DReqPass ({2{1'b1}}),
67: .DRspPass ({2{1'b1}}),
68: .HReqDepth (4'h0),
69: .HRspDepth (4'h0),
70: .DReqDepth ({2{4'h0}}),
71: .DRspDepth ({2{4'h0}})
72: ) u_socket (
73: .clk_i,
74: .rst_ni,
75: .tl_h_i (tl_i),
76: .tl_h_o (tl_o),
77: .tl_d_o (tl_socket_h2d),
78: .tl_d_i (tl_socket_d2h),
79: .dev_select (reg_steer)
80: );
81:
82: // Create steering logic
83: always_comb begin
84: reg_steer = 1; // Default set to register
85:
86: // TODO: Can below codes be unique case () inside ?
87: if (tl_i.a_address[AW-1:0] >= 2048) begin
88: // Exceed or meet the address range. Removed the comparison of limit addr 'h 1000
89: reg_steer = 0;
90: end
91: end
92:
93: tlul_adapter_reg #(
94: .RegAw(AW),
95: .RegDw(DW)
96: ) u_reg_if (
97: .clk_i,
98: .rst_ni,
99:
100: .tl_i (tl_reg_h2d),
101: .tl_o (tl_reg_d2h),
102:
103: .we_o (reg_we),
104: .re_o (reg_re),
105: .addr_o (reg_addr),
106: .wdata_o (reg_wdata),
107: .be_o (reg_be),
108: .rdata_i (reg_rdata),
109: .error_i (reg_error)
110: );
111:
112: assign reg_rdata = reg_rdata_next ;
113: assign reg_error = (devmode_i & addrmiss) | wr_err ;
114:
115: // Define SW related signals
116: // Format: __{wd|we|qs}
117: // or _{wd|we|qs} if field == 1 or 0
118: logic intr_state_pkt_received_qs;
119: logic intr_state_pkt_received_wd;
120: logic intr_state_pkt_received_we;
121: logic intr_state_pkt_sent_qs;
122: logic intr_state_pkt_sent_wd;
123: logic intr_state_pkt_sent_we;
124: logic intr_state_disconnected_qs;
125: logic intr_state_disconnected_wd;
126: logic intr_state_disconnected_we;
127: logic intr_state_host_lost_qs;
128: logic intr_state_host_lost_wd;
129: logic intr_state_host_lost_we;
130: logic intr_state_link_reset_qs;
131: logic intr_state_link_reset_wd;
132: logic intr_state_link_reset_we;
133: logic intr_state_link_suspend_qs;
134: logic intr_state_link_suspend_wd;
135: logic intr_state_link_suspend_we;
136: logic intr_state_link_resume_qs;
137: logic intr_state_link_resume_wd;
138: logic intr_state_link_resume_we;
139: logic intr_state_av_empty_qs;
140: logic intr_state_av_empty_wd;
141: logic intr_state_av_empty_we;
142: logic intr_state_rx_full_qs;
143: logic intr_state_rx_full_wd;
144: logic intr_state_rx_full_we;
145: logic intr_state_av_overflow_qs;
146: logic intr_state_av_overflow_wd;
147: logic intr_state_av_overflow_we;
148: logic intr_state_link_in_err_qs;
149: logic intr_state_link_in_err_wd;
150: logic intr_state_link_in_err_we;
151: logic intr_state_rx_crc_err_qs;
152: logic intr_state_rx_crc_err_wd;
153: logic intr_state_rx_crc_err_we;
154: logic intr_state_rx_pid_err_qs;
155: logic intr_state_rx_pid_err_wd;
156: logic intr_state_rx_pid_err_we;
157: logic intr_state_rx_bitstuff_err_qs;
158: logic intr_state_rx_bitstuff_err_wd;
159: logic intr_state_rx_bitstuff_err_we;
160: logic intr_state_frame_qs;
161: logic intr_state_frame_wd;
162: logic intr_state_frame_we;
163: logic intr_state_connected_qs;
164: logic intr_state_connected_wd;
165: logic intr_state_connected_we;
166: logic intr_enable_pkt_received_qs;
167: logic intr_enable_pkt_received_wd;
168: logic intr_enable_pkt_received_we;
169: logic intr_enable_pkt_sent_qs;
170: logic intr_enable_pkt_sent_wd;
171: logic intr_enable_pkt_sent_we;
172: logic intr_enable_disconnected_qs;
173: logic intr_enable_disconnected_wd;
174: logic intr_enable_disconnected_we;
175: logic intr_enable_host_lost_qs;
176: logic intr_enable_host_lost_wd;
177: logic intr_enable_host_lost_we;
178: logic intr_enable_link_reset_qs;
179: logic intr_enable_link_reset_wd;
180: logic intr_enable_link_reset_we;
181: logic intr_enable_link_suspend_qs;
182: logic intr_enable_link_suspend_wd;
183: logic intr_enable_link_suspend_we;
184: logic intr_enable_link_resume_qs;
185: logic intr_enable_link_resume_wd;
186: logic intr_enable_link_resume_we;
187: logic intr_enable_av_empty_qs;
188: logic intr_enable_av_empty_wd;
189: logic intr_enable_av_empty_we;
190: logic intr_enable_rx_full_qs;
191: logic intr_enable_rx_full_wd;
192: logic intr_enable_rx_full_we;
193: logic intr_enable_av_overflow_qs;
194: logic intr_enable_av_overflow_wd;
195: logic intr_enable_av_overflow_we;
196: logic intr_enable_link_in_err_qs;
197: logic intr_enable_link_in_err_wd;
198: logic intr_enable_link_in_err_we;
199: logic intr_enable_rx_crc_err_qs;
200: logic intr_enable_rx_crc_err_wd;
201: logic intr_enable_rx_crc_err_we;
202: logic intr_enable_rx_pid_err_qs;
203: logic intr_enable_rx_pid_err_wd;
204: logic intr_enable_rx_pid_err_we;
205: logic intr_enable_rx_bitstuff_err_qs;
206: logic intr_enable_rx_bitstuff_err_wd;
207: logic intr_enable_rx_bitstuff_err_we;
208: logic intr_enable_frame_qs;
209: logic intr_enable_frame_wd;
210: logic intr_enable_frame_we;
211: logic intr_enable_connected_qs;
212: logic intr_enable_connected_wd;
213: logic intr_enable_connected_we;
214: logic intr_test_pkt_received_wd;
215: logic intr_test_pkt_received_we;
216: logic intr_test_pkt_sent_wd;
217: logic intr_test_pkt_sent_we;
218: logic intr_test_disconnected_wd;
219: logic intr_test_disconnected_we;
220: logic intr_test_host_lost_wd;
221: logic intr_test_host_lost_we;
222: logic intr_test_link_reset_wd;
223: logic intr_test_link_reset_we;
224: logic intr_test_link_suspend_wd;
225: logic intr_test_link_suspend_we;
226: logic intr_test_link_resume_wd;
227: logic intr_test_link_resume_we;
228: logic intr_test_av_empty_wd;
229: logic intr_test_av_empty_we;
230: logic intr_test_rx_full_wd;
231: logic intr_test_rx_full_we;
232: logic intr_test_av_overflow_wd;
233: logic intr_test_av_overflow_we;
234: logic intr_test_link_in_err_wd;
235: logic intr_test_link_in_err_we;
236: logic intr_test_rx_crc_err_wd;
237: logic intr_test_rx_crc_err_we;
238: logic intr_test_rx_pid_err_wd;
239: logic intr_test_rx_pid_err_we;
240: logic intr_test_rx_bitstuff_err_wd;
241: logic intr_test_rx_bitstuff_err_we;
242: logic intr_test_frame_wd;
243: logic intr_test_frame_we;
244: logic intr_test_connected_wd;
245: logic intr_test_connected_we;
246: logic usbctrl_enable_qs;
247: logic usbctrl_enable_wd;
248: logic usbctrl_enable_we;
249: logic [6:0] usbctrl_device_address_qs;
250: logic [6:0] usbctrl_device_address_wd;
251: logic usbctrl_device_address_we;
252: logic [10:0] usbstat_frame_qs;
253: logic usbstat_frame_re;
254: logic usbstat_host_lost_qs;
255: logic usbstat_host_lost_re;
256: logic [2:0] usbstat_link_state_qs;
257: logic usbstat_link_state_re;
258: logic usbstat_usb_sense_qs;
259: logic usbstat_usb_sense_re;
260: logic [2:0] usbstat_av_depth_qs;
261: logic usbstat_av_depth_re;
262: logic usbstat_av_full_qs;
263: logic usbstat_av_full_re;
264: logic [2:0] usbstat_rx_depth_qs;
265: logic usbstat_rx_depth_re;
266: logic usbstat_rx_empty_qs;
267: logic usbstat_rx_empty_re;
268: logic [4:0] avbuffer_wd;
269: logic avbuffer_we;
270: logic [4:0] rxfifo_buffer_qs;
271: logic rxfifo_buffer_re;
272: logic [6:0] rxfifo_size_qs;
273: logic rxfifo_size_re;
274: logic rxfifo_setup_qs;
275: logic rxfifo_setup_re;
276: logic [3:0] rxfifo_ep_qs;
277: logic rxfifo_ep_re;
278: logic rxenable_setup_setup0_qs;
279: logic rxenable_setup_setup0_wd;
280: logic rxenable_setup_setup0_we;
281: logic rxenable_setup_setup1_qs;
282: logic rxenable_setup_setup1_wd;
283: logic rxenable_setup_setup1_we;
284: logic rxenable_setup_setup2_qs;
285: logic rxenable_setup_setup2_wd;
286: logic rxenable_setup_setup2_we;
287: logic rxenable_setup_setup3_qs;
288: logic rxenable_setup_setup3_wd;
289: logic rxenable_setup_setup3_we;
290: logic rxenable_setup_setup4_qs;
291: logic rxenable_setup_setup4_wd;
292: logic rxenable_setup_setup4_we;
293: logic rxenable_setup_setup5_qs;
294: logic rxenable_setup_setup5_wd;
295: logic rxenable_setup_setup5_we;
296: logic rxenable_setup_setup6_qs;
297: logic rxenable_setup_setup6_wd;
298: logic rxenable_setup_setup6_we;
299: logic rxenable_setup_setup7_qs;
300: logic rxenable_setup_setup7_wd;
301: logic rxenable_setup_setup7_we;
302: logic rxenable_setup_setup8_qs;
303: logic rxenable_setup_setup8_wd;
304: logic rxenable_setup_setup8_we;
305: logic rxenable_setup_setup9_qs;
306: logic rxenable_setup_setup9_wd;
307: logic rxenable_setup_setup9_we;
308: logic rxenable_setup_setup10_qs;
309: logic rxenable_setup_setup10_wd;
310: logic rxenable_setup_setup10_we;
311: logic rxenable_setup_setup11_qs;
312: logic rxenable_setup_setup11_wd;
313: logic rxenable_setup_setup11_we;
314: logic rxenable_out_out0_qs;
315: logic rxenable_out_out0_wd;
316: logic rxenable_out_out0_we;
317: logic rxenable_out_out1_qs;
318: logic rxenable_out_out1_wd;
319: logic rxenable_out_out1_we;
320: logic rxenable_out_out2_qs;
321: logic rxenable_out_out2_wd;
322: logic rxenable_out_out2_we;
323: logic rxenable_out_out3_qs;
324: logic rxenable_out_out3_wd;
325: logic rxenable_out_out3_we;
326: logic rxenable_out_out4_qs;
327: logic rxenable_out_out4_wd;
328: logic rxenable_out_out4_we;
329: logic rxenable_out_out5_qs;
330: logic rxenable_out_out5_wd;
331: logic rxenable_out_out5_we;
332: logic rxenable_out_out6_qs;
333: logic rxenable_out_out6_wd;
334: logic rxenable_out_out6_we;
335: logic rxenable_out_out7_qs;
336: logic rxenable_out_out7_wd;
337: logic rxenable_out_out7_we;
338: logic rxenable_out_out8_qs;
339: logic rxenable_out_out8_wd;
340: logic rxenable_out_out8_we;
341: logic rxenable_out_out9_qs;
342: logic rxenable_out_out9_wd;
343: logic rxenable_out_out9_we;
344: logic rxenable_out_out10_qs;
345: logic rxenable_out_out10_wd;
346: logic rxenable_out_out10_we;
347: logic rxenable_out_out11_qs;
348: logic rxenable_out_out11_wd;
349: logic rxenable_out_out11_we;
350: logic in_sent_sent0_qs;
351: logic in_sent_sent0_wd;
352: logic in_sent_sent0_we;
353: logic in_sent_sent1_qs;
354: logic in_sent_sent1_wd;
355: logic in_sent_sent1_we;
356: logic in_sent_sent2_qs;
357: logic in_sent_sent2_wd;
358: logic in_sent_sent2_we;
359: logic in_sent_sent3_qs;
360: logic in_sent_sent3_wd;
361: logic in_sent_sent3_we;
362: logic in_sent_sent4_qs;
363: logic in_sent_sent4_wd;
364: logic in_sent_sent4_we;
365: logic in_sent_sent5_qs;
366: logic in_sent_sent5_wd;
367: logic in_sent_sent5_we;
368: logic in_sent_sent6_qs;
369: logic in_sent_sent6_wd;
370: logic in_sent_sent6_we;
371: logic in_sent_sent7_qs;
372: logic in_sent_sent7_wd;
373: logic in_sent_sent7_we;
374: logic in_sent_sent8_qs;
375: logic in_sent_sent8_wd;
376: logic in_sent_sent8_we;
377: logic in_sent_sent9_qs;
378: logic in_sent_sent9_wd;
379: logic in_sent_sent9_we;
380: logic in_sent_sent10_qs;
381: logic in_sent_sent10_wd;
382: logic in_sent_sent10_we;
383: logic in_sent_sent11_qs;
384: logic in_sent_sent11_wd;
385: logic in_sent_sent11_we;
386: logic stall_stall0_qs;
387: logic stall_stall0_wd;
388: logic stall_stall0_we;
389: logic stall_stall1_qs;
390: logic stall_stall1_wd;
391: logic stall_stall1_we;
392: logic stall_stall2_qs;
393: logic stall_stall2_wd;
394: logic stall_stall2_we;
395: logic stall_stall3_qs;
396: logic stall_stall3_wd;
397: logic stall_stall3_we;
398: logic stall_stall4_qs;
399: logic stall_stall4_wd;
400: logic stall_stall4_we;
401: logic stall_stall5_qs;
402: logic stall_stall5_wd;
403: logic stall_stall5_we;
404: logic stall_stall6_qs;
405: logic stall_stall6_wd;
406: logic stall_stall6_we;
407: logic stall_stall7_qs;
408: logic stall_stall7_wd;
409: logic stall_stall7_we;
410: logic stall_stall8_qs;
411: logic stall_stall8_wd;
412: logic stall_stall8_we;
413: logic stall_stall9_qs;
414: logic stall_stall9_wd;
415: logic stall_stall9_we;
416: logic stall_stall10_qs;
417: logic stall_stall10_wd;
418: logic stall_stall10_we;
419: logic stall_stall11_qs;
420: logic stall_stall11_wd;
421: logic stall_stall11_we;
422: logic [4:0] configin0_buffer0_qs;
423: logic [4:0] configin0_buffer0_wd;
424: logic configin0_buffer0_we;
425: logic [6:0] configin0_size0_qs;
426: logic [6:0] configin0_size0_wd;
427: logic configin0_size0_we;
428: logic configin0_pend0_qs;
429: logic configin0_pend0_wd;
430: logic configin0_pend0_we;
431: logic configin0_rdy0_qs;
432: logic configin0_rdy0_wd;
433: logic configin0_rdy0_we;
434: logic [4:0] configin1_buffer1_qs;
435: logic [4:0] configin1_buffer1_wd;
436: logic configin1_buffer1_we;
437: logic [6:0] configin1_size1_qs;
438: logic [6:0] configin1_size1_wd;
439: logic configin1_size1_we;
440: logic configin1_pend1_qs;
441: logic configin1_pend1_wd;
442: logic configin1_pend1_we;
443: logic configin1_rdy1_qs;
444: logic configin1_rdy1_wd;
445: logic configin1_rdy1_we;
446: logic [4:0] configin2_buffer2_qs;
447: logic [4:0] configin2_buffer2_wd;
448: logic configin2_buffer2_we;
449: logic [6:0] configin2_size2_qs;
450: logic [6:0] configin2_size2_wd;
451: logic configin2_size2_we;
452: logic configin2_pend2_qs;
453: logic configin2_pend2_wd;
454: logic configin2_pend2_we;
455: logic configin2_rdy2_qs;
456: logic configin2_rdy2_wd;
457: logic configin2_rdy2_we;
458: logic [4:0] configin3_buffer3_qs;
459: logic [4:0] configin3_buffer3_wd;
460: logic configin3_buffer3_we;
461: logic [6:0] configin3_size3_qs;
462: logic [6:0] configin3_size3_wd;
463: logic configin3_size3_we;
464: logic configin3_pend3_qs;
465: logic configin3_pend3_wd;
466: logic configin3_pend3_we;
467: logic configin3_rdy3_qs;
468: logic configin3_rdy3_wd;
469: logic configin3_rdy3_we;
470: logic [4:0] configin4_buffer4_qs;
471: logic [4:0] configin4_buffer4_wd;
472: logic configin4_buffer4_we;
473: logic [6:0] configin4_size4_qs;
474: logic [6:0] configin4_size4_wd;
475: logic configin4_size4_we;
476: logic configin4_pend4_qs;
477: logic configin4_pend4_wd;
478: logic configin4_pend4_we;
479: logic configin4_rdy4_qs;
480: logic configin4_rdy4_wd;
481: logic configin4_rdy4_we;
482: logic [4:0] configin5_buffer5_qs;
483: logic [4:0] configin5_buffer5_wd;
484: logic configin5_buffer5_we;
485: logic [6:0] configin5_size5_qs;
486: logic [6:0] configin5_size5_wd;
487: logic configin5_size5_we;
488: logic configin5_pend5_qs;
489: logic configin5_pend5_wd;
490: logic configin5_pend5_we;
491: logic configin5_rdy5_qs;
492: logic configin5_rdy5_wd;
493: logic configin5_rdy5_we;
494: logic [4:0] configin6_buffer6_qs;
495: logic [4:0] configin6_buffer6_wd;
496: logic configin6_buffer6_we;
497: logic [6:0] configin6_size6_qs;
498: logic [6:0] configin6_size6_wd;
499: logic configin6_size6_we;
500: logic configin6_pend6_qs;
501: logic configin6_pend6_wd;
502: logic configin6_pend6_we;
503: logic configin6_rdy6_qs;
504: logic configin6_rdy6_wd;
505: logic configin6_rdy6_we;
506: logic [4:0] configin7_buffer7_qs;
507: logic [4:0] configin7_buffer7_wd;
508: logic configin7_buffer7_we;
509: logic [6:0] configin7_size7_qs;
510: logic [6:0] configin7_size7_wd;
511: logic configin7_size7_we;
512: logic configin7_pend7_qs;
513: logic configin7_pend7_wd;
514: logic configin7_pend7_we;
515: logic configin7_rdy7_qs;
516: logic configin7_rdy7_wd;
517: logic configin7_rdy7_we;
518: logic [4:0] configin8_buffer8_qs;
519: logic [4:0] configin8_buffer8_wd;
520: logic configin8_buffer8_we;
521: logic [6:0] configin8_size8_qs;
522: logic [6:0] configin8_size8_wd;
523: logic configin8_size8_we;
524: logic configin8_pend8_qs;
525: logic configin8_pend8_wd;
526: logic configin8_pend8_we;
527: logic configin8_rdy8_qs;
528: logic configin8_rdy8_wd;
529: logic configin8_rdy8_we;
530: logic [4:0] configin9_buffer9_qs;
531: logic [4:0] configin9_buffer9_wd;
532: logic configin9_buffer9_we;
533: logic [6:0] configin9_size9_qs;
534: logic [6:0] configin9_size9_wd;
535: logic configin9_size9_we;
536: logic configin9_pend9_qs;
537: logic configin9_pend9_wd;
538: logic configin9_pend9_we;
539: logic configin9_rdy9_qs;
540: logic configin9_rdy9_wd;
541: logic configin9_rdy9_we;
542: logic [4:0] configin10_buffer10_qs;
543: logic [4:0] configin10_buffer10_wd;
544: logic configin10_buffer10_we;
545: logic [6:0] configin10_size10_qs;
546: logic [6:0] configin10_size10_wd;
547: logic configin10_size10_we;
548: logic configin10_pend10_qs;
549: logic configin10_pend10_wd;
550: logic configin10_pend10_we;
551: logic configin10_rdy10_qs;
552: logic configin10_rdy10_wd;
553: logic configin10_rdy10_we;
554: logic [4:0] configin11_buffer11_qs;
555: logic [4:0] configin11_buffer11_wd;
556: logic configin11_buffer11_we;
557: logic [6:0] configin11_size11_qs;
558: logic [6:0] configin11_size11_wd;
559: logic configin11_size11_we;
560: logic configin11_pend11_qs;
561: logic configin11_pend11_wd;
562: logic configin11_pend11_we;
563: logic configin11_rdy11_qs;
564: logic configin11_rdy11_wd;
565: logic configin11_rdy11_we;
566: logic iso_iso0_qs;
567: logic iso_iso0_wd;
568: logic iso_iso0_we;
569: logic iso_iso1_qs;
570: logic iso_iso1_wd;
571: logic iso_iso1_we;
572: logic iso_iso2_qs;
573: logic iso_iso2_wd;
574: logic iso_iso2_we;
575: logic iso_iso3_qs;
576: logic iso_iso3_wd;
577: logic iso_iso3_we;
578: logic iso_iso4_qs;
579: logic iso_iso4_wd;
580: logic iso_iso4_we;
581: logic iso_iso5_qs;
582: logic iso_iso5_wd;
583: logic iso_iso5_we;
584: logic iso_iso6_qs;
585: logic iso_iso6_wd;
586: logic iso_iso6_we;
587: logic iso_iso7_qs;
588: logic iso_iso7_wd;
589: logic iso_iso7_we;
590: logic iso_iso8_qs;
591: logic iso_iso8_wd;
592: logic iso_iso8_we;
593: logic iso_iso9_qs;
594: logic iso_iso9_wd;
595: logic iso_iso9_we;
596: logic iso_iso10_qs;
597: logic iso_iso10_wd;
598: logic iso_iso10_we;
599: logic iso_iso11_qs;
600: logic iso_iso11_wd;
601: logic iso_iso11_we;
602: logic data_toggle_clear_clear0_wd;
603: logic data_toggle_clear_clear0_we;
604: logic data_toggle_clear_clear1_wd;
605: logic data_toggle_clear_clear1_we;
606: logic data_toggle_clear_clear2_wd;
607: logic data_toggle_clear_clear2_we;
608: logic data_toggle_clear_clear3_wd;
609: logic data_toggle_clear_clear3_we;
610: logic data_toggle_clear_clear4_wd;
611: logic data_toggle_clear_clear4_we;
612: logic data_toggle_clear_clear5_wd;
613: logic data_toggle_clear_clear5_we;
614: logic data_toggle_clear_clear6_wd;
615: logic data_toggle_clear_clear6_we;
616: logic data_toggle_clear_clear7_wd;
617: logic data_toggle_clear_clear7_we;
618: logic data_toggle_clear_clear8_wd;
619: logic data_toggle_clear_clear8_we;
620: logic data_toggle_clear_clear9_wd;
621: logic data_toggle_clear_clear9_we;
622: logic data_toggle_clear_clear10_wd;
623: logic data_toggle_clear_clear10_we;
624: logic data_toggle_clear_clear11_wd;
625: logic data_toggle_clear_clear11_we;
626: logic phy_config_rx_differential_mode_qs;
627: logic phy_config_rx_differential_mode_wd;
628: logic phy_config_rx_differential_mode_we;
629: logic phy_config_tx_differential_mode_qs;
630: logic phy_config_tx_differential_mode_wd;
631: logic phy_config_tx_differential_mode_we;
632: logic phy_config_eop_single_bit_qs;
633: logic phy_config_eop_single_bit_wd;
634: logic phy_config_eop_single_bit_we;
635: logic phy_config_override_pwr_sense_en_qs;
636: logic phy_config_override_pwr_sense_en_wd;
637: logic phy_config_override_pwr_sense_en_we;
638: logic phy_config_override_pwr_sense_val_qs;
639: logic phy_config_override_pwr_sense_val_wd;
640: logic phy_config_override_pwr_sense_val_we;
641:
642: // Register instances
643: // R[intr_state]: V(False)
644:
645: // F[pkt_received]: 0:0
646: prim_subreg #(
647: .DW (1),
648: .SWACCESS("W1C"),
649: .RESVAL (1'h0)
650: ) u_intr_state_pkt_received (
651: .clk_i (clk_i ),
652: .rst_ni (rst_ni ),
653:
654: // from register interface
655: .we (intr_state_pkt_received_we),
656: .wd (intr_state_pkt_received_wd),
657:
658: // from internal hardware
659: .de (hw2reg.intr_state.pkt_received.de),
660: .d (hw2reg.intr_state.pkt_received.d ),
661:
662: // to internal hardware
663: .qe (),
664: .q (reg2hw.intr_state.pkt_received.q ),
665:
666: // to register interface (read)
667: .qs (intr_state_pkt_received_qs)
668: );
669:
670:
671: // F[pkt_sent]: 1:1
672: prim_subreg #(
673: .DW (1),
674: .SWACCESS("W1C"),
675: .RESVAL (1'h0)
676: ) u_intr_state_pkt_sent (
677: .clk_i (clk_i ),
678: .rst_ni (rst_ni ),
679:
680: // from register interface
681: .we (intr_state_pkt_sent_we),
682: .wd (intr_state_pkt_sent_wd),
683:
684: // from internal hardware
685: .de (hw2reg.intr_state.pkt_sent.de),
686: .d (hw2reg.intr_state.pkt_sent.d ),
687:
688: // to internal hardware
689: .qe (),
690: .q (reg2hw.intr_state.pkt_sent.q ),
691:
692: // to register interface (read)
693: .qs (intr_state_pkt_sent_qs)
694: );
695:
696:
697: // F[disconnected]: 2:2
698: prim_subreg #(
699: .DW (1),
700: .SWACCESS("W1C"),
701: .RESVAL (1'h0)
702: ) u_intr_state_disconnected (
703: .clk_i (clk_i ),
704: .rst_ni (rst_ni ),
705:
706: // from register interface
707: .we (intr_state_disconnected_we),
708: .wd (intr_state_disconnected_wd),
709:
710: // from internal hardware
711: .de (hw2reg.intr_state.disconnected.de),
712: .d (hw2reg.intr_state.disconnected.d ),
713:
714: // to internal hardware
715: .qe (),
716: .q (reg2hw.intr_state.disconnected.q ),
717:
718: // to register interface (read)
719: .qs (intr_state_disconnected_qs)
720: );
721:
722:
723: // F[host_lost]: 3:3
724: prim_subreg #(
725: .DW (1),
726: .SWACCESS("W1C"),
727: .RESVAL (1'h0)
728: ) u_intr_state_host_lost (
729: .clk_i (clk_i ),
730: .rst_ni (rst_ni ),
731:
732: // from register interface
733: .we (intr_state_host_lost_we),
734: .wd (intr_state_host_lost_wd),
735:
736: // from internal hardware
737: .de (hw2reg.intr_state.host_lost.de),
738: .d (hw2reg.intr_state.host_lost.d ),
739:
740: // to internal hardware
741: .qe (),
742: .q (reg2hw.intr_state.host_lost.q ),
743:
744: // to register interface (read)
745: .qs (intr_state_host_lost_qs)
746: );
747:
748:
749: // F[link_reset]: 4:4
750: prim_subreg #(
751: .DW (1),
752: .SWACCESS("W1C"),
753: .RESVAL (1'h0)
754: ) u_intr_state_link_reset (
755: .clk_i (clk_i ),
756: .rst_ni (rst_ni ),
757:
758: // from register interface
759: .we (intr_state_link_reset_we),
760: .wd (intr_state_link_reset_wd),
761:
762: // from internal hardware
763: .de (hw2reg.intr_state.link_reset.de),
764: .d (hw2reg.intr_state.link_reset.d ),
765:
766: // to internal hardware
767: .qe (),
768: .q (reg2hw.intr_state.link_reset.q ),
769:
770: // to register interface (read)
771: .qs (intr_state_link_reset_qs)
772: );
773:
774:
775: // F[link_suspend]: 5:5
776: prim_subreg #(
777: .DW (1),
778: .SWACCESS("W1C"),
779: .RESVAL (1'h0)
780: ) u_intr_state_link_suspend (
781: .clk_i (clk_i ),
782: .rst_ni (rst_ni ),
783:
784: // from register interface
785: .we (intr_state_link_suspend_we),
786: .wd (intr_state_link_suspend_wd),
787:
788: // from internal hardware
789: .de (hw2reg.intr_state.link_suspend.de),
790: .d (hw2reg.intr_state.link_suspend.d ),
791:
792: // to internal hardware
793: .qe (),
794: .q (reg2hw.intr_state.link_suspend.q ),
795:
796: // to register interface (read)
797: .qs (intr_state_link_suspend_qs)
798: );
799:
800:
801: // F[link_resume]: 6:6
802: prim_subreg #(
803: .DW (1),
804: .SWACCESS("W1C"),
805: .RESVAL (1'h0)
806: ) u_intr_state_link_resume (
807: .clk_i (clk_i ),
808: .rst_ni (rst_ni ),
809:
810: // from register interface
811: .we (intr_state_link_resume_we),
812: .wd (intr_state_link_resume_wd),
813:
814: // from internal hardware
815: .de (hw2reg.intr_state.link_resume.de),
816: .d (hw2reg.intr_state.link_resume.d ),
817:
818: // to internal hardware
819: .qe (),
820: .q (reg2hw.intr_state.link_resume.q ),
821:
822: // to register interface (read)
823: .qs (intr_state_link_resume_qs)
824: );
825:
826:
827: // F[av_empty]: 7:7
828: prim_subreg #(
829: .DW (1),
830: .SWACCESS("W1C"),
831: .RESVAL (1'h0)
832: ) u_intr_state_av_empty (
833: .clk_i (clk_i ),
834: .rst_ni (rst_ni ),
835:
836: // from register interface
837: .we (intr_state_av_empty_we),
838: .wd (intr_state_av_empty_wd),
839:
840: // from internal hardware
841: .de (hw2reg.intr_state.av_empty.de),
842: .d (hw2reg.intr_state.av_empty.d ),
843:
844: // to internal hardware
845: .qe (),
846: .q (reg2hw.intr_state.av_empty.q ),
847:
848: // to register interface (read)
849: .qs (intr_state_av_empty_qs)
850: );
851:
852:
853: // F[rx_full]: 8:8
854: prim_subreg #(
855: .DW (1),
856: .SWACCESS("W1C"),
857: .RESVAL (1'h0)
858: ) u_intr_state_rx_full (
859: .clk_i (clk_i ),
860: .rst_ni (rst_ni ),
861:
862: // from register interface
863: .we (intr_state_rx_full_we),
864: .wd (intr_state_rx_full_wd),
865:
866: // from internal hardware
867: .de (hw2reg.intr_state.rx_full.de),
868: .d (hw2reg.intr_state.rx_full.d ),
869:
870: // to internal hardware
871: .qe (),
872: .q (reg2hw.intr_state.rx_full.q ),
873:
874: // to register interface (read)
875: .qs (intr_state_rx_full_qs)
876: );
877:
878:
879: // F[av_overflow]: 9:9
880: prim_subreg #(
881: .DW (1),
882: .SWACCESS("W1C"),
883: .RESVAL (1'h0)
884: ) u_intr_state_av_overflow (
885: .clk_i (clk_i ),
886: .rst_ni (rst_ni ),
887:
888: // from register interface
889: .we (intr_state_av_overflow_we),
890: .wd (intr_state_av_overflow_wd),
891:
892: // from internal hardware
893: .de (hw2reg.intr_state.av_overflow.de),
894: .d (hw2reg.intr_state.av_overflow.d ),
895:
896: // to internal hardware
897: .qe (),
898: .q (reg2hw.intr_state.av_overflow.q ),
899:
900: // to register interface (read)
901: .qs (intr_state_av_overflow_qs)
902: );
903:
904:
905: // F[link_in_err]: 10:10
906: prim_subreg #(
907: .DW (1),
908: .SWACCESS("W1C"),
909: .RESVAL (1'h0)
910: ) u_intr_state_link_in_err (
911: .clk_i (clk_i ),
912: .rst_ni (rst_ni ),
913:
914: // from register interface
915: .we (intr_state_link_in_err_we),
916: .wd (intr_state_link_in_err_wd),
917:
918: // from internal hardware
919: .de (hw2reg.intr_state.link_in_err.de),
920: .d (hw2reg.intr_state.link_in_err.d ),
921:
922: // to internal hardware
923: .qe (),
924: .q (reg2hw.intr_state.link_in_err.q ),
925:
926: // to register interface (read)
927: .qs (intr_state_link_in_err_qs)
928: );
929:
930:
931: // F[rx_crc_err]: 11:11
932: prim_subreg #(
933: .DW (1),
934: .SWACCESS("W1C"),
935: .RESVAL (1'h0)
936: ) u_intr_state_rx_crc_err (
937: .clk_i (clk_i ),
938: .rst_ni (rst_ni ),
939:
940: // from register interface
941: .we (intr_state_rx_crc_err_we),
942: .wd (intr_state_rx_crc_err_wd),
943:
944: // from internal hardware
945: .de (hw2reg.intr_state.rx_crc_err.de),
946: .d (hw2reg.intr_state.rx_crc_err.d ),
947:
948: // to internal hardware
949: .qe (),
950: .q (reg2hw.intr_state.rx_crc_err.q ),
951:
952: // to register interface (read)
953: .qs (intr_state_rx_crc_err_qs)
954: );
955:
956:
957: // F[rx_pid_err]: 12:12
958: prim_subreg #(
959: .DW (1),
960: .SWACCESS("W1C"),
961: .RESVAL (1'h0)
962: ) u_intr_state_rx_pid_err (
963: .clk_i (clk_i ),
964: .rst_ni (rst_ni ),
965:
966: // from register interface
967: .we (intr_state_rx_pid_err_we),
968: .wd (intr_state_rx_pid_err_wd),
969:
970: // from internal hardware
971: .de (hw2reg.intr_state.rx_pid_err.de),
972: .d (hw2reg.intr_state.rx_pid_err.d ),
973:
974: // to internal hardware
975: .qe (),
976: .q (reg2hw.intr_state.rx_pid_err.q ),
977:
978: // to register interface (read)
979: .qs (intr_state_rx_pid_err_qs)
980: );
981:
982:
983: // F[rx_bitstuff_err]: 13:13
984: prim_subreg #(
985: .DW (1),
986: .SWACCESS("W1C"),
987: .RESVAL (1'h0)
988: ) u_intr_state_rx_bitstuff_err (
989: .clk_i (clk_i ),
990: .rst_ni (rst_ni ),
991:
992: // from register interface
993: .we (intr_state_rx_bitstuff_err_we),
994: .wd (intr_state_rx_bitstuff_err_wd),
995:
996: // from internal hardware
997: .de (hw2reg.intr_state.rx_bitstuff_err.de),
998: .d (hw2reg.intr_state.rx_bitstuff_err.d ),
999:
1000: // to internal hardware
1001: .qe (),
1002: .q (reg2hw.intr_state.rx_bitstuff_err.q ),
1003:
1004: // to register interface (read)
1005: .qs (intr_state_rx_bitstuff_err_qs)
1006: );
1007:
1008:
1009: // F[frame]: 14:14
1010: prim_subreg #(
1011: .DW (1),
1012: .SWACCESS("W1C"),
1013: .RESVAL (1'h0)
1014: ) u_intr_state_frame (
1015: .clk_i (clk_i ),
1016: .rst_ni (rst_ni ),
1017:
1018: // from register interface
1019: .we (intr_state_frame_we),
1020: .wd (intr_state_frame_wd),
1021:
1022: // from internal hardware
1023: .de (hw2reg.intr_state.frame.de),
1024: .d (hw2reg.intr_state.frame.d ),
1025:
1026: // to internal hardware
1027: .qe (),
1028: .q (reg2hw.intr_state.frame.q ),
1029:
1030: // to register interface (read)
1031: .qs (intr_state_frame_qs)
1032: );
1033:
1034:
1035: // F[connected]: 15:15
1036: prim_subreg #(
1037: .DW (1),
1038: .SWACCESS("W1C"),
1039: .RESVAL (1'h0)
1040: ) u_intr_state_connected (
1041: .clk_i (clk_i ),
1042: .rst_ni (rst_ni ),
1043:
1044: // from register interface
1045: .we (intr_state_connected_we),
1046: .wd (intr_state_connected_wd),
1047:
1048: // from internal hardware
1049: .de (hw2reg.intr_state.connected.de),
1050: .d (hw2reg.intr_state.connected.d ),
1051:
1052: // to internal hardware
1053: .qe (),
1054: .q (reg2hw.intr_state.connected.q ),
1055:
1056: // to register interface (read)
1057: .qs (intr_state_connected_qs)
1058: );
1059:
1060:
1061: // R[intr_enable]: V(False)
1062:
1063: // F[pkt_received]: 0:0
1064: prim_subreg #(
1065: .DW (1),
1066: .SWACCESS("RW"),
1067: .RESVAL (1'h0)
1068: ) u_intr_enable_pkt_received (
1069: .clk_i (clk_i ),
1070: .rst_ni (rst_ni ),
1071:
1072: // from register interface
1073: .we (intr_enable_pkt_received_we),
1074: .wd (intr_enable_pkt_received_wd),
1075:
1076: // from internal hardware
1077: .de (1'b0),
1078: .d ('0 ),
1079:
1080: // to internal hardware
1081: .qe (),
1082: .q (reg2hw.intr_enable.pkt_received.q ),
1083:
1084: // to register interface (read)
1085: .qs (intr_enable_pkt_received_qs)
1086: );
1087:
1088:
1089: // F[pkt_sent]: 1:1
1090: prim_subreg #(
1091: .DW (1),
1092: .SWACCESS("RW"),
1093: .RESVAL (1'h0)
1094: ) u_intr_enable_pkt_sent (
1095: .clk_i (clk_i ),
1096: .rst_ni (rst_ni ),
1097:
1098: // from register interface
1099: .we (intr_enable_pkt_sent_we),
1100: .wd (intr_enable_pkt_sent_wd),
1101:
1102: // from internal hardware
1103: .de (1'b0),
1104: .d ('0 ),
1105:
1106: // to internal hardware
1107: .qe (),
1108: .q (reg2hw.intr_enable.pkt_sent.q ),
1109:
1110: // to register interface (read)
1111: .qs (intr_enable_pkt_sent_qs)
1112: );
1113:
1114:
1115: // F[disconnected]: 2:2
1116: prim_subreg #(
1117: .DW (1),
1118: .SWACCESS("RW"),
1119: .RESVAL (1'h0)
1120: ) u_intr_enable_disconnected (
1121: .clk_i (clk_i ),
1122: .rst_ni (rst_ni ),
1123:
1124: // from register interface
1125: .we (intr_enable_disconnected_we),
1126: .wd (intr_enable_disconnected_wd),
1127:
1128: // from internal hardware
1129: .de (1'b0),
1130: .d ('0 ),
1131:
1132: // to internal hardware
1133: .qe (),
1134: .q (reg2hw.intr_enable.disconnected.q ),
1135:
1136: // to register interface (read)
1137: .qs (intr_enable_disconnected_qs)
1138: );
1139:
1140:
1141: // F[host_lost]: 3:3
1142: prim_subreg #(
1143: .DW (1),
1144: .SWACCESS("RW"),
1145: .RESVAL (1'h0)
1146: ) u_intr_enable_host_lost (
1147: .clk_i (clk_i ),
1148: .rst_ni (rst_ni ),
1149:
1150: // from register interface
1151: .we (intr_enable_host_lost_we),
1152: .wd (intr_enable_host_lost_wd),
1153:
1154: // from internal hardware
1155: .de (1'b0),
1156: .d ('0 ),
1157:
1158: // to internal hardware
1159: .qe (),
1160: .q (reg2hw.intr_enable.host_lost.q ),
1161:
1162: // to register interface (read)
1163: .qs (intr_enable_host_lost_qs)
1164: );
1165:
1166:
1167: // F[link_reset]: 4:4
1168: prim_subreg #(
1169: .DW (1),
1170: .SWACCESS("RW"),
1171: .RESVAL (1'h0)
1172: ) u_intr_enable_link_reset (
1173: .clk_i (clk_i ),
1174: .rst_ni (rst_ni ),
1175:
1176: // from register interface
1177: .we (intr_enable_link_reset_we),
1178: .wd (intr_enable_link_reset_wd),
1179:
1180: // from internal hardware
1181: .de (1'b0),
1182: .d ('0 ),
1183:
1184: // to internal hardware
1185: .qe (),
1186: .q (reg2hw.intr_enable.link_reset.q ),
1187:
1188: // to register interface (read)
1189: .qs (intr_enable_link_reset_qs)
1190: );
1191:
1192:
1193: // F[link_suspend]: 5:5
1194: prim_subreg #(
1195: .DW (1),
1196: .SWACCESS("RW"),
1197: .RESVAL (1'h0)
1198: ) u_intr_enable_link_suspend (
1199: .clk_i (clk_i ),
1200: .rst_ni (rst_ni ),
1201:
1202: // from register interface
1203: .we (intr_enable_link_suspend_we),
1204: .wd (intr_enable_link_suspend_wd),
1205:
1206: // from internal hardware
1207: .de (1'b0),
1208: .d ('0 ),
1209:
1210: // to internal hardware
1211: .qe (),
1212: .q (reg2hw.intr_enable.link_suspend.q ),
1213:
1214: // to register interface (read)
1215: .qs (intr_enable_link_suspend_qs)
1216: );
1217:
1218:
1219: // F[link_resume]: 6:6
1220: prim_subreg #(
1221: .DW (1),
1222: .SWACCESS("RW"),
1223: .RESVAL (1'h0)
1224: ) u_intr_enable_link_resume (
1225: .clk_i (clk_i ),
1226: .rst_ni (rst_ni ),
1227:
1228: // from register interface
1229: .we (intr_enable_link_resume_we),
1230: .wd (intr_enable_link_resume_wd),
1231:
1232: // from internal hardware
1233: .de (1'b0),
1234: .d ('0 ),
1235:
1236: // to internal hardware
1237: .qe (),
1238: .q (reg2hw.intr_enable.link_resume.q ),
1239:
1240: // to register interface (read)
1241: .qs (intr_enable_link_resume_qs)
1242: );
1243:
1244:
1245: // F[av_empty]: 7:7
1246: prim_subreg #(
1247: .DW (1),
1248: .SWACCESS("RW"),
1249: .RESVAL (1'h0)
1250: ) u_intr_enable_av_empty (
1251: .clk_i (clk_i ),
1252: .rst_ni (rst_ni ),
1253:
1254: // from register interface
1255: .we (intr_enable_av_empty_we),
1256: .wd (intr_enable_av_empty_wd),
1257:
1258: // from internal hardware
1259: .de (1'b0),
1260: .d ('0 ),
1261:
1262: // to internal hardware
1263: .qe (),
1264: .q (reg2hw.intr_enable.av_empty.q ),
1265:
1266: // to register interface (read)
1267: .qs (intr_enable_av_empty_qs)
1268: );
1269:
1270:
1271: // F[rx_full]: 8:8
1272: prim_subreg #(
1273: .DW (1),
1274: .SWACCESS("RW"),
1275: .RESVAL (1'h0)
1276: ) u_intr_enable_rx_full (
1277: .clk_i (clk_i ),
1278: .rst_ni (rst_ni ),
1279:
1280: // from register interface
1281: .we (intr_enable_rx_full_we),
1282: .wd (intr_enable_rx_full_wd),
1283:
1284: // from internal hardware
1285: .de (1'b0),
1286: .d ('0 ),
1287:
1288: // to internal hardware
1289: .qe (),
1290: .q (reg2hw.intr_enable.rx_full.q ),
1291:
1292: // to register interface (read)
1293: .qs (intr_enable_rx_full_qs)
1294: );
1295:
1296:
1297: // F[av_overflow]: 9:9
1298: prim_subreg #(
1299: .DW (1),
1300: .SWACCESS("RW"),
1301: .RESVAL (1'h0)
1302: ) u_intr_enable_av_overflow (
1303: .clk_i (clk_i ),
1304: .rst_ni (rst_ni ),
1305:
1306: // from register interface
1307: .we (intr_enable_av_overflow_we),
1308: .wd (intr_enable_av_overflow_wd),
1309:
1310: // from internal hardware
1311: .de (1'b0),
1312: .d ('0 ),
1313:
1314: // to internal hardware
1315: .qe (),
1316: .q (reg2hw.intr_enable.av_overflow.q ),
1317:
1318: // to register interface (read)
1319: .qs (intr_enable_av_overflow_qs)
1320: );
1321:
1322:
1323: // F[link_in_err]: 10:10
1324: prim_subreg #(
1325: .DW (1),
1326: .SWACCESS("RW"),
1327: .RESVAL (1'h0)
1328: ) u_intr_enable_link_in_err (
1329: .clk_i (clk_i ),
1330: .rst_ni (rst_ni ),
1331:
1332: // from register interface
1333: .we (intr_enable_link_in_err_we),
1334: .wd (intr_enable_link_in_err_wd),
1335:
1336: // from internal hardware
1337: .de (1'b0),
1338: .d ('0 ),
1339:
1340: // to internal hardware
1341: .qe (),
1342: .q (reg2hw.intr_enable.link_in_err.q ),
1343:
1344: // to register interface (read)
1345: .qs (intr_enable_link_in_err_qs)
1346: );
1347:
1348:
1349: // F[rx_crc_err]: 11:11
1350: prim_subreg #(
1351: .DW (1),
1352: .SWACCESS("RW"),
1353: .RESVAL (1'h0)
1354: ) u_intr_enable_rx_crc_err (
1355: .clk_i (clk_i ),
1356: .rst_ni (rst_ni ),
1357:
1358: // from register interface
1359: .we (intr_enable_rx_crc_err_we),
1360: .wd (intr_enable_rx_crc_err_wd),
1361:
1362: // from internal hardware
1363: .de (1'b0),
1364: .d ('0 ),
1365:
1366: // to internal hardware
1367: .qe (),
1368: .q (reg2hw.intr_enable.rx_crc_err.q ),
1369:
1370: // to register interface (read)
1371: .qs (intr_enable_rx_crc_err_qs)
1372: );
1373:
1374:
1375: // F[rx_pid_err]: 12:12
1376: prim_subreg #(
1377: .DW (1),
1378: .SWACCESS("RW"),
1379: .RESVAL (1'h0)
1380: ) u_intr_enable_rx_pid_err (
1381: .clk_i (clk_i ),
1382: .rst_ni (rst_ni ),
1383:
1384: // from register interface
1385: .we (intr_enable_rx_pid_err_we),
1386: .wd (intr_enable_rx_pid_err_wd),
1387:
1388: // from internal hardware
1389: .de (1'b0),
1390: .d ('0 ),
1391:
1392: // to internal hardware
1393: .qe (),
1394: .q (reg2hw.intr_enable.rx_pid_err.q ),
1395:
1396: // to register interface (read)
1397: .qs (intr_enable_rx_pid_err_qs)
1398: );
1399:
1400:
1401: // F[rx_bitstuff_err]: 13:13
1402: prim_subreg #(
1403: .DW (1),
1404: .SWACCESS("RW"),
1405: .RESVAL (1'h0)
1406: ) u_intr_enable_rx_bitstuff_err (
1407: .clk_i (clk_i ),
1408: .rst_ni (rst_ni ),
1409:
1410: // from register interface
1411: .we (intr_enable_rx_bitstuff_err_we),
1412: .wd (intr_enable_rx_bitstuff_err_wd),
1413:
1414: // from internal hardware
1415: .de (1'b0),
1416: .d ('0 ),
1417:
1418: // to internal hardware
1419: .qe (),
1420: .q (reg2hw.intr_enable.rx_bitstuff_err.q ),
1421:
1422: // to register interface (read)
1423: .qs (intr_enable_rx_bitstuff_err_qs)
1424: );
1425:
1426:
1427: // F[frame]: 14:14
1428: prim_subreg #(
1429: .DW (1),
1430: .SWACCESS("RW"),
1431: .RESVAL (1'h0)
1432: ) u_intr_enable_frame (
1433: .clk_i (clk_i ),
1434: .rst_ni (rst_ni ),
1435:
1436: // from register interface
1437: .we (intr_enable_frame_we),
1438: .wd (intr_enable_frame_wd),
1439:
1440: // from internal hardware
1441: .de (1'b0),
1442: .d ('0 ),
1443:
1444: // to internal hardware
1445: .qe (),
1446: .q (reg2hw.intr_enable.frame.q ),
1447:
1448: // to register interface (read)
1449: .qs (intr_enable_frame_qs)
1450: );
1451:
1452:
1453: // F[connected]: 15:15
1454: prim_subreg #(
1455: .DW (1),
1456: .SWACCESS("RW"),
1457: .RESVAL (1'h0)
1458: ) u_intr_enable_connected (
1459: .clk_i (clk_i ),
1460: .rst_ni (rst_ni ),
1461:
1462: // from register interface
1463: .we (intr_enable_connected_we),
1464: .wd (intr_enable_connected_wd),
1465:
1466: // from internal hardware
1467: .de (1'b0),
1468: .d ('0 ),
1469:
1470: // to internal hardware
1471: .qe (),
1472: .q (reg2hw.intr_enable.connected.q ),
1473:
1474: // to register interface (read)
1475: .qs (intr_enable_connected_qs)
1476: );
1477:
1478:
1479: // R[intr_test]: V(True)
1480:
1481: // F[pkt_received]: 0:0
1482: prim_subreg_ext #(
1483: .DW (1)
1484: ) u_intr_test_pkt_received (
1485: .re (1'b0),
1486: .we (intr_test_pkt_received_we),
1487: .wd (intr_test_pkt_received_wd),
1488: .d ('0),
1489: .qre (),
1490: .qe (reg2hw.intr_test.pkt_received.qe),
1491: .q (reg2hw.intr_test.pkt_received.q ),
1492: .qs ()
1493: );
1494:
1495:
1496: // F[pkt_sent]: 1:1
1497: prim_subreg_ext #(
1498: .DW (1)
1499: ) u_intr_test_pkt_sent (
1500: .re (1'b0),
1501: .we (intr_test_pkt_sent_we),
1502: .wd (intr_test_pkt_sent_wd),
1503: .d ('0),
1504: .qre (),
1505: .qe (reg2hw.intr_test.pkt_sent.qe),
1506: .q (reg2hw.intr_test.pkt_sent.q ),
1507: .qs ()
1508: );
1509:
1510:
1511: // F[disconnected]: 2:2
1512: prim_subreg_ext #(
1513: .DW (1)
1514: ) u_intr_test_disconnected (
1515: .re (1'b0),
1516: .we (intr_test_disconnected_we),
1517: .wd (intr_test_disconnected_wd),
1518: .d ('0),
1519: .qre (),
1520: .qe (reg2hw.intr_test.disconnected.qe),
1521: .q (reg2hw.intr_test.disconnected.q ),
1522: .qs ()
1523: );
1524:
1525:
1526: // F[host_lost]: 3:3
1527: prim_subreg_ext #(
1528: .DW (1)
1529: ) u_intr_test_host_lost (
1530: .re (1'b0),
1531: .we (intr_test_host_lost_we),
1532: .wd (intr_test_host_lost_wd),
1533: .d ('0),
1534: .qre (),
1535: .qe (reg2hw.intr_test.host_lost.qe),
1536: .q (reg2hw.intr_test.host_lost.q ),
1537: .qs ()
1538: );
1539:
1540:
1541: // F[link_reset]: 4:4
1542: prim_subreg_ext #(
1543: .DW (1)
1544: ) u_intr_test_link_reset (
1545: .re (1'b0),
1546: .we (intr_test_link_reset_we),
1547: .wd (intr_test_link_reset_wd),
1548: .d ('0),
1549: .qre (),
1550: .qe (reg2hw.intr_test.link_reset.qe),
1551: .q (reg2hw.intr_test.link_reset.q ),
1552: .qs ()
1553: );
1554:
1555:
1556: // F[link_suspend]: 5:5
1557: prim_subreg_ext #(
1558: .DW (1)
1559: ) u_intr_test_link_suspend (
1560: .re (1'b0),
1561: .we (intr_test_link_suspend_we),
1562: .wd (intr_test_link_suspend_wd),
1563: .d ('0),
1564: .qre (),
1565: .qe (reg2hw.intr_test.link_suspend.qe),
1566: .q (reg2hw.intr_test.link_suspend.q ),
1567: .qs ()
1568: );
1569:
1570:
1571: // F[link_resume]: 6:6
1572: prim_subreg_ext #(
1573: .DW (1)
1574: ) u_intr_test_link_resume (
1575: .re (1'b0),
1576: .we (intr_test_link_resume_we),
1577: .wd (intr_test_link_resume_wd),
1578: .d ('0),
1579: .qre (),
1580: .qe (reg2hw.intr_test.link_resume.qe),
1581: .q (reg2hw.intr_test.link_resume.q ),
1582: .qs ()
1583: );
1584:
1585:
1586: // F[av_empty]: 7:7
1587: prim_subreg_ext #(
1588: .DW (1)
1589: ) u_intr_test_av_empty (
1590: .re (1'b0),
1591: .we (intr_test_av_empty_we),
1592: .wd (intr_test_av_empty_wd),
1593: .d ('0),
1594: .qre (),
1595: .qe (reg2hw.intr_test.av_empty.qe),
1596: .q (reg2hw.intr_test.av_empty.q ),
1597: .qs ()
1598: );
1599:
1600:
1601: // F[rx_full]: 8:8
1602: prim_subreg_ext #(
1603: .DW (1)
1604: ) u_intr_test_rx_full (
1605: .re (1'b0),
1606: .we (intr_test_rx_full_we),
1607: .wd (intr_test_rx_full_wd),
1608: .d ('0),
1609: .qre (),
1610: .qe (reg2hw.intr_test.rx_full.qe),
1611: .q (reg2hw.intr_test.rx_full.q ),
1612: .qs ()
1613: );
1614:
1615:
1616: // F[av_overflow]: 9:9
1617: prim_subreg_ext #(
1618: .DW (1)
1619: ) u_intr_test_av_overflow (
1620: .re (1'b0),
1621: .we (intr_test_av_overflow_we),
1622: .wd (intr_test_av_overflow_wd),
1623: .d ('0),
1624: .qre (),
1625: .qe (reg2hw.intr_test.av_overflow.qe),
1626: .q (reg2hw.intr_test.av_overflow.q ),
1627: .qs ()
1628: );
1629:
1630:
1631: // F[link_in_err]: 10:10
1632: prim_subreg_ext #(
1633: .DW (1)
1634: ) u_intr_test_link_in_err (
1635: .re (1'b0),
1636: .we (intr_test_link_in_err_we),
1637: .wd (intr_test_link_in_err_wd),
1638: .d ('0),
1639: .qre (),
1640: .qe (reg2hw.intr_test.link_in_err.qe),
1641: .q (reg2hw.intr_test.link_in_err.q ),
1642: .qs ()
1643: );
1644:
1645:
1646: // F[rx_crc_err]: 11:11
1647: prim_subreg_ext #(
1648: .DW (1)
1649: ) u_intr_test_rx_crc_err (
1650: .re (1'b0),
1651: .we (intr_test_rx_crc_err_we),
1652: .wd (intr_test_rx_crc_err_wd),
1653: .d ('0),
1654: .qre (),
1655: .qe (reg2hw.intr_test.rx_crc_err.qe),
1656: .q (reg2hw.intr_test.rx_crc_err.q ),
1657: .qs ()
1658: );
1659:
1660:
1661: // F[rx_pid_err]: 12:12
1662: prim_subreg_ext #(
1663: .DW (1)
1664: ) u_intr_test_rx_pid_err (
1665: .re (1'b0),
1666: .we (intr_test_rx_pid_err_we),
1667: .wd (intr_test_rx_pid_err_wd),
1668: .d ('0),
1669: .qre (),
1670: .qe (reg2hw.intr_test.rx_pid_err.qe),
1671: .q (reg2hw.intr_test.rx_pid_err.q ),
1672: .qs ()
1673: );
1674:
1675:
1676: // F[rx_bitstuff_err]: 13:13
1677: prim_subreg_ext #(
1678: .DW (1)
1679: ) u_intr_test_rx_bitstuff_err (
1680: .re (1'b0),
1681: .we (intr_test_rx_bitstuff_err_we),
1682: .wd (intr_test_rx_bitstuff_err_wd),
1683: .d ('0),
1684: .qre (),
1685: .qe (reg2hw.intr_test.rx_bitstuff_err.qe),
1686: .q (reg2hw.intr_test.rx_bitstuff_err.q ),
1687: .qs ()
1688: );
1689:
1690:
1691: // F[frame]: 14:14
1692: prim_subreg_ext #(
1693: .DW (1)
1694: ) u_intr_test_frame (
1695: .re (1'b0),
1696: .we (intr_test_frame_we),
1697: .wd (intr_test_frame_wd),
1698: .d ('0),
1699: .qre (),
1700: .qe (reg2hw.intr_test.frame.qe),
1701: .q (reg2hw.intr_test.frame.q ),
1702: .qs ()
1703: );
1704:
1705:
1706: // F[connected]: 15:15
1707: prim_subreg_ext #(
1708: .DW (1)
1709: ) u_intr_test_connected (
1710: .re (1'b0),
1711: .we (intr_test_connected_we),
1712: .wd (intr_test_connected_wd),
1713: .d ('0),
1714: .qre (),
1715: .qe (reg2hw.intr_test.connected.qe),
1716: .q (reg2hw.intr_test.connected.q ),
1717: .qs ()
1718: );
1719:
1720:
1721: // R[usbctrl]: V(False)
1722:
1723: // F[enable]: 0:0
1724: prim_subreg #(
1725: .DW (1),
1726: .SWACCESS("RW"),
1727: .RESVAL (1'h0)
1728: ) u_usbctrl_enable (
1729: .clk_i (clk_i ),
1730: .rst_ni (rst_ni ),
1731:
1732: // from register interface
1733: .we (usbctrl_enable_we),
1734: .wd (usbctrl_enable_wd),
1735:
1736: // from internal hardware
1737: .de (1'b0),
1738: .d ('0 ),
1739:
1740: // to internal hardware
1741: .qe (),
1742: .q (reg2hw.usbctrl.enable.q ),
1743:
1744: // to register interface (read)
1745: .qs (usbctrl_enable_qs)
1746: );
1747:
1748:
1749: // F[device_address]: 22:16
1750: prim_subreg #(
1751: .DW (7),
1752: .SWACCESS("RW"),
1753: .RESVAL (7'h0)
1754: ) u_usbctrl_device_address (
1755: .clk_i (clk_i ),
1756: .rst_ni (rst_ni ),
1757:
1758: // from register interface
1759: .we (usbctrl_device_address_we),
1760: .wd (usbctrl_device_address_wd),
1761:
1762: // from internal hardware
1763: .de (hw2reg.usbctrl.device_address.de),
1764: .d (hw2reg.usbctrl.device_address.d ),
1765:
1766: // to internal hardware
1767: .qe (),
1768: .q (reg2hw.usbctrl.device_address.q ),
1769:
1770: // to register interface (read)
1771: .qs (usbctrl_device_address_qs)
1772: );
1773:
1774:
1775: // R[usbstat]: V(True)
1776:
1777: // F[frame]: 10:0
1778: prim_subreg_ext #(
1779: .DW (11)
1780: ) u_usbstat_frame (
1781: .re (usbstat_frame_re),
1782: .we (1'b0),
1783: .wd ('0),
1784: .d (hw2reg.usbstat.frame.d),
1785: .qre (),
1786: .qe (),
1787: .q (),
1788: .qs (usbstat_frame_qs)
1789: );
1790:
1791:
1792: // F[host_lost]: 11:11
1793: prim_subreg_ext #(
1794: .DW (1)
1795: ) u_usbstat_host_lost (
1796: .re (usbstat_host_lost_re),
1797: .we (1'b0),
1798: .wd ('0),
1799: .d (hw2reg.usbstat.host_lost.d),
1800: .qre (),
1801: .qe (),
1802: .q (),
1803: .qs (usbstat_host_lost_qs)
1804: );
1805:
1806:
1807: // F[link_state]: 14:12
1808: prim_subreg_ext #(
1809: .DW (3)
1810: ) u_usbstat_link_state (
1811: .re (usbstat_link_state_re),
1812: .we (1'b0),
1813: .wd ('0),
1814: .d (hw2reg.usbstat.link_state.d),
1815: .qre (),
1816: .qe (),
1817: .q (),
1818: .qs (usbstat_link_state_qs)
1819: );
1820:
1821:
1822: // F[usb_sense]: 15:15
1823: prim_subreg_ext #(
1824: .DW (1)
1825: ) u_usbstat_usb_sense (
1826: .re (usbstat_usb_sense_re),
1827: .we (1'b0),
1828: .wd ('0),
1829: .d (hw2reg.usbstat.usb_sense.d),
1830: .qre (),
1831: .qe (),
1832: .q (),
1833: .qs (usbstat_usb_sense_qs)
1834: );
1835:
1836:
1837: // F[av_depth]: 18:16
1838: prim_subreg_ext #(
1839: .DW (3)
1840: ) u_usbstat_av_depth (
1841: .re (usbstat_av_depth_re),
1842: .we (1'b0),
1843: .wd ('0),
1844: .d (hw2reg.usbstat.av_depth.d),
1845: .qre (),
1846: .qe (),
1847: .q (),
1848: .qs (usbstat_av_depth_qs)
1849: );
1850:
1851:
1852: // F[av_full]: 23:23
1853: prim_subreg_ext #(
1854: .DW (1)
1855: ) u_usbstat_av_full (
1856: .re (usbstat_av_full_re),
1857: .we (1'b0),
1858: .wd ('0),
1859: .d (hw2reg.usbstat.av_full.d),
1860: .qre (),
1861: .qe (),
1862: .q (),
1863: .qs (usbstat_av_full_qs)
1864: );
1865:
1866:
1867: // F[rx_depth]: 26:24
1868: prim_subreg_ext #(
1869: .DW (3)
1870: ) u_usbstat_rx_depth (
1871: .re (usbstat_rx_depth_re),
1872: .we (1'b0),
1873: .wd ('0),
1874: .d (hw2reg.usbstat.rx_depth.d),
1875: .qre (),
1876: .qe (),
1877: .q (),
1878: .qs (usbstat_rx_depth_qs)
1879: );
1880:
1881:
1882: // F[rx_empty]: 31:31
1883: prim_subreg_ext #(
1884: .DW (1)
1885: ) u_usbstat_rx_empty (
1886: .re (usbstat_rx_empty_re),
1887: .we (1'b0),
1888: .wd ('0),
1889: .d (hw2reg.usbstat.rx_empty.d),
1890: .qre (),
1891: .qe (),
1892: .q (),
1893: .qs (usbstat_rx_empty_qs)
1894: );
1895:
1896:
1897: // R[avbuffer]: V(False)
1898:
1899: prim_subreg #(
1900: .DW (5),
1901: .SWACCESS("WO"),
1902: .RESVAL (5'h0)
1903: ) u_avbuffer (
1904: .clk_i (clk_i ),
1905: .rst_ni (rst_ni ),
1906:
1907: // from register interface
1908: .we (avbuffer_we),
1909: .wd (avbuffer_wd),
1910:
1911: // from internal hardware
1912: .de (1'b0),
1913: .d ('0 ),
1914:
1915: // to internal hardware
1916: .qe (reg2hw.avbuffer.qe),
1917: .q (reg2hw.avbuffer.q ),
1918:
1919: .qs ()
1920: );
1921:
1922:
1923: // R[rxfifo]: V(True)
1924:
1925: // F[buffer]: 4:0
1926: prim_subreg_ext #(
1927: .DW (5)
1928: ) u_rxfifo_buffer (
1929: .re (rxfifo_buffer_re),
1930: .we (1'b0),
1931: .wd ('0),
1932: .d (hw2reg.rxfifo.buffer.d),
1933: .qre (reg2hw.rxfifo.buffer.re),
1934: .qe (),
1935: .q (reg2hw.rxfifo.buffer.q ),
1936: .qs (rxfifo_buffer_qs)
1937: );
1938:
1939:
1940: // F[size]: 14:8
1941: prim_subreg_ext #(
1942: .DW (7)
1943: ) u_rxfifo_size (
1944: .re (rxfifo_size_re),
1945: .we (1'b0),
1946: .wd ('0),
1947: .d (hw2reg.rxfifo.size.d),
1948: .qre (reg2hw.rxfifo.size.re),
1949: .qe (),
1950: .q (reg2hw.rxfifo.size.q ),
1951: .qs (rxfifo_size_qs)
1952: );
1953:
1954:
1955: // F[setup]: 19:19
1956: prim_subreg_ext #(
1957: .DW (1)
1958: ) u_rxfifo_setup (
1959: .re (rxfifo_setup_re),
1960: .we (1'b0),
1961: .wd ('0),
1962: .d (hw2reg.rxfifo.setup.d),
1963: .qre (reg2hw.rxfifo.setup.re),
1964: .qe (),
1965: .q (reg2hw.rxfifo.setup.q ),
1966: .qs (rxfifo_setup_qs)
1967: );
1968:
1969:
1970: // F[ep]: 23:20
1971: prim_subreg_ext #(
1972: .DW (4)
1973: ) u_rxfifo_ep (
1974: .re (rxfifo_ep_re),
1975: .we (1'b0),
1976: .wd ('0),
1977: .d (hw2reg.rxfifo.ep.d),
1978: .qre (reg2hw.rxfifo.ep.re),
1979: .qe (),
1980: .q (reg2hw.rxfifo.ep.q ),
1981: .qs (rxfifo_ep_qs)
1982: );
1983:
1984:
1985:
1986: // Subregister 0 of Multireg rxenable_setup
1987: // R[rxenable_setup]: V(False)
1988:
1989: // F[setup0]: 0:0
1990: prim_subreg #(
1991: .DW (1),
1992: .SWACCESS("RW"),
1993: .RESVAL (1'h0)
1994: ) u_rxenable_setup_setup0 (
1995: .clk_i (clk_i ),
1996: .rst_ni (rst_ni ),
1997:
1998: // from register interface
1999: .we (rxenable_setup_setup0_we),
2000: .wd (rxenable_setup_setup0_wd),
2001:
2002: // from internal hardware
2003: .de (1'b0),
2004: .d ('0 ),
2005:
2006: // to internal hardware
2007: .qe (),
2008: .q (reg2hw.rxenable_setup[0].q ),
2009:
2010: // to register interface (read)
2011: .qs (rxenable_setup_setup0_qs)
2012: );
2013:
2014:
2015: // F[setup1]: 1:1
2016: prim_subreg #(
2017: .DW (1),
2018: .SWACCESS("RW"),
2019: .RESVAL (1'h0)
2020: ) u_rxenable_setup_setup1 (
2021: .clk_i (clk_i ),
2022: .rst_ni (rst_ni ),
2023:
2024: // from register interface
2025: .we (rxenable_setup_setup1_we),
2026: .wd (rxenable_setup_setup1_wd),
2027:
2028: // from internal hardware
2029: .de (1'b0),
2030: .d ('0 ),
2031:
2032: // to internal hardware
2033: .qe (),
2034: .q (reg2hw.rxenable_setup[1].q ),
2035:
2036: // to register interface (read)
2037: .qs (rxenable_setup_setup1_qs)
2038: );
2039:
2040:
2041: // F[setup2]: 2:2
2042: prim_subreg #(
2043: .DW (1),
2044: .SWACCESS("RW"),
2045: .RESVAL (1'h0)
2046: ) u_rxenable_setup_setup2 (
2047: .clk_i (clk_i ),
2048: .rst_ni (rst_ni ),
2049:
2050: // from register interface
2051: .we (rxenable_setup_setup2_we),
2052: .wd (rxenable_setup_setup2_wd),
2053:
2054: // from internal hardware
2055: .de (1'b0),
2056: .d ('0 ),
2057:
2058: // to internal hardware
2059: .qe (),
2060: .q (reg2hw.rxenable_setup[2].q ),
2061:
2062: // to register interface (read)
2063: .qs (rxenable_setup_setup2_qs)
2064: );
2065:
2066:
2067: // F[setup3]: 3:3
2068: prim_subreg #(
2069: .DW (1),
2070: .SWACCESS("RW"),
2071: .RESVAL (1'h0)
2072: ) u_rxenable_setup_setup3 (
2073: .clk_i (clk_i ),
2074: .rst_ni (rst_ni ),
2075:
2076: // from register interface
2077: .we (rxenable_setup_setup3_we),
2078: .wd (rxenable_setup_setup3_wd),
2079:
2080: // from internal hardware
2081: .de (1'b0),
2082: .d ('0 ),
2083:
2084: // to internal hardware
2085: .qe (),
2086: .q (reg2hw.rxenable_setup[3].q ),
2087:
2088: // to register interface (read)
2089: .qs (rxenable_setup_setup3_qs)
2090: );
2091:
2092:
2093: // F[setup4]: 4:4
2094: prim_subreg #(
2095: .DW (1),
2096: .SWACCESS("RW"),
2097: .RESVAL (1'h0)
2098: ) u_rxenable_setup_setup4 (
2099: .clk_i (clk_i ),
2100: .rst_ni (rst_ni ),
2101:
2102: // from register interface
2103: .we (rxenable_setup_setup4_we),
2104: .wd (rxenable_setup_setup4_wd),
2105:
2106: // from internal hardware
2107: .de (1'b0),
2108: .d ('0 ),
2109:
2110: // to internal hardware
2111: .qe (),
2112: .q (reg2hw.rxenable_setup[4].q ),
2113:
2114: // to register interface (read)
2115: .qs (rxenable_setup_setup4_qs)
2116: );
2117:
2118:
2119: // F[setup5]: 5:5
2120: prim_subreg #(
2121: .DW (1),
2122: .SWACCESS("RW"),
2123: .RESVAL (1'h0)
2124: ) u_rxenable_setup_setup5 (
2125: .clk_i (clk_i ),
2126: .rst_ni (rst_ni ),
2127:
2128: // from register interface
2129: .we (rxenable_setup_setup5_we),
2130: .wd (rxenable_setup_setup5_wd),
2131:
2132: // from internal hardware
2133: .de (1'b0),
2134: .d ('0 ),
2135:
2136: // to internal hardware
2137: .qe (),
2138: .q (reg2hw.rxenable_setup[5].q ),
2139:
2140: // to register interface (read)
2141: .qs (rxenable_setup_setup5_qs)
2142: );
2143:
2144:
2145: // F[setup6]: 6:6
2146: prim_subreg #(
2147: .DW (1),
2148: .SWACCESS("RW"),
2149: .RESVAL (1'h0)
2150: ) u_rxenable_setup_setup6 (
2151: .clk_i (clk_i ),
2152: .rst_ni (rst_ni ),
2153:
2154: // from register interface
2155: .we (rxenable_setup_setup6_we),
2156: .wd (rxenable_setup_setup6_wd),
2157:
2158: // from internal hardware
2159: .de (1'b0),
2160: .d ('0 ),
2161:
2162: // to internal hardware
2163: .qe (),
2164: .q (reg2hw.rxenable_setup[6].q ),
2165:
2166: // to register interface (read)
2167: .qs (rxenable_setup_setup6_qs)
2168: );
2169:
2170:
2171: // F[setup7]: 7:7
2172: prim_subreg #(
2173: .DW (1),
2174: .SWACCESS("RW"),
2175: .RESVAL (1'h0)
2176: ) u_rxenable_setup_setup7 (
2177: .clk_i (clk_i ),
2178: .rst_ni (rst_ni ),
2179:
2180: // from register interface
2181: .we (rxenable_setup_setup7_we),
2182: .wd (rxenable_setup_setup7_wd),
2183:
2184: // from internal hardware
2185: .de (1'b0),
2186: .d ('0 ),
2187:
2188: // to internal hardware
2189: .qe (),
2190: .q (reg2hw.rxenable_setup[7].q ),
2191:
2192: // to register interface (read)
2193: .qs (rxenable_setup_setup7_qs)
2194: );
2195:
2196:
2197: // F[setup8]: 8:8
2198: prim_subreg #(
2199: .DW (1),
2200: .SWACCESS("RW"),
2201: .RESVAL (1'h0)
2202: ) u_rxenable_setup_setup8 (
2203: .clk_i (clk_i ),
2204: .rst_ni (rst_ni ),
2205:
2206: // from register interface
2207: .we (rxenable_setup_setup8_we),
2208: .wd (rxenable_setup_setup8_wd),
2209:
2210: // from internal hardware
2211: .de (1'b0),
2212: .d ('0 ),
2213:
2214: // to internal hardware
2215: .qe (),
2216: .q (reg2hw.rxenable_setup[8].q ),
2217:
2218: // to register interface (read)
2219: .qs (rxenable_setup_setup8_qs)
2220: );
2221:
2222:
2223: // F[setup9]: 9:9
2224: prim_subreg #(
2225: .DW (1),
2226: .SWACCESS("RW"),
2227: .RESVAL (1'h0)
2228: ) u_rxenable_setup_setup9 (
2229: .clk_i (clk_i ),
2230: .rst_ni (rst_ni ),
2231:
2232: // from register interface
2233: .we (rxenable_setup_setup9_we),
2234: .wd (rxenable_setup_setup9_wd),
2235:
2236: // from internal hardware
2237: .de (1'b0),
2238: .d ('0 ),
2239:
2240: // to internal hardware
2241: .qe (),
2242: .q (reg2hw.rxenable_setup[9].q ),
2243:
2244: // to register interface (read)
2245: .qs (rxenable_setup_setup9_qs)
2246: );
2247:
2248:
2249: // F[setup10]: 10:10
2250: prim_subreg #(
2251: .DW (1),
2252: .SWACCESS("RW"),
2253: .RESVAL (1'h0)
2254: ) u_rxenable_setup_setup10 (
2255: .clk_i (clk_i ),
2256: .rst_ni (rst_ni ),
2257:
2258: // from register interface
2259: .we (rxenable_setup_setup10_we),
2260: .wd (rxenable_setup_setup10_wd),
2261:
2262: // from internal hardware
2263: .de (1'b0),
2264: .d ('0 ),
2265:
2266: // to internal hardware
2267: .qe (),
2268: .q (reg2hw.rxenable_setup[10].q ),
2269:
2270: // to register interface (read)
2271: .qs (rxenable_setup_setup10_qs)
2272: );
2273:
2274:
2275: // F[setup11]: 11:11
2276: prim_subreg #(
2277: .DW (1),
2278: .SWACCESS("RW"),
2279: .RESVAL (1'h0)
2280: ) u_rxenable_setup_setup11 (
2281: .clk_i (clk_i ),
2282: .rst_ni (rst_ni ),
2283:
2284: // from register interface
2285: .we (rxenable_setup_setup11_we),
2286: .wd (rxenable_setup_setup11_wd),
2287:
2288: // from internal hardware
2289: .de (1'b0),
2290: .d ('0 ),
2291:
2292: // to internal hardware
2293: .qe (),
2294: .q (reg2hw.rxenable_setup[11].q ),
2295:
2296: // to register interface (read)
2297: .qs (rxenable_setup_setup11_qs)
2298: );
2299:
2300:
2301:
2302:
2303: // Subregister 0 of Multireg rxenable_out
2304: // R[rxenable_out]: V(False)
2305:
2306: // F[out0]: 0:0
2307: prim_subreg #(
2308: .DW (1),
2309: .SWACCESS("RW"),
2310: .RESVAL (1'h0)
2311: ) u_rxenable_out_out0 (
2312: .clk_i (clk_i ),
2313: .rst_ni (rst_ni ),
2314:
2315: // from register interface
2316: .we (rxenable_out_out0_we),
2317: .wd (rxenable_out_out0_wd),
2318:
2319: // from internal hardware
2320: .de (1'b0),
2321: .d ('0 ),
2322:
2323: // to internal hardware
2324: .qe (),
2325: .q (reg2hw.rxenable_out[0].q ),
2326:
2327: // to register interface (read)
2328: .qs (rxenable_out_out0_qs)
2329: );
2330:
2331:
2332: // F[out1]: 1:1
2333: prim_subreg #(
2334: .DW (1),
2335: .SWACCESS("RW"),
2336: .RESVAL (1'h0)
2337: ) u_rxenable_out_out1 (
2338: .clk_i (clk_i ),
2339: .rst_ni (rst_ni ),
2340:
2341: // from register interface
2342: .we (rxenable_out_out1_we),
2343: .wd (rxenable_out_out1_wd),
2344:
2345: // from internal hardware
2346: .de (1'b0),
2347: .d ('0 ),
2348:
2349: // to internal hardware
2350: .qe (),
2351: .q (reg2hw.rxenable_out[1].q ),
2352:
2353: // to register interface (read)
2354: .qs (rxenable_out_out1_qs)
2355: );
2356:
2357:
2358: // F[out2]: 2:2
2359: prim_subreg #(
2360: .DW (1),
2361: .SWACCESS("RW"),
2362: .RESVAL (1'h0)
2363: ) u_rxenable_out_out2 (
2364: .clk_i (clk_i ),
2365: .rst_ni (rst_ni ),
2366:
2367: // from register interface
2368: .we (rxenable_out_out2_we),
2369: .wd (rxenable_out_out2_wd),
2370:
2371: // from internal hardware
2372: .de (1'b0),
2373: .d ('0 ),
2374:
2375: // to internal hardware
2376: .qe (),
2377: .q (reg2hw.rxenable_out[2].q ),
2378:
2379: // to register interface (read)
2380: .qs (rxenable_out_out2_qs)
2381: );
2382:
2383:
2384: // F[out3]: 3:3
2385: prim_subreg #(
2386: .DW (1),
2387: .SWACCESS("RW"),
2388: .RESVAL (1'h0)
2389: ) u_rxenable_out_out3 (
2390: .clk_i (clk_i ),
2391: .rst_ni (rst_ni ),
2392:
2393: // from register interface
2394: .we (rxenable_out_out3_we),
2395: .wd (rxenable_out_out3_wd),
2396:
2397: // from internal hardware
2398: .de (1'b0),
2399: .d ('0 ),
2400:
2401: // to internal hardware
2402: .qe (),
2403: .q (reg2hw.rxenable_out[3].q ),
2404:
2405: // to register interface (read)
2406: .qs (rxenable_out_out3_qs)
2407: );
2408:
2409:
2410: // F[out4]: 4:4
2411: prim_subreg #(
2412: .DW (1),
2413: .SWACCESS("RW"),
2414: .RESVAL (1'h0)
2415: ) u_rxenable_out_out4 (
2416: .clk_i (clk_i ),
2417: .rst_ni (rst_ni ),
2418:
2419: // from register interface
2420: .we (rxenable_out_out4_we),
2421: .wd (rxenable_out_out4_wd),
2422:
2423: // from internal hardware
2424: .de (1'b0),
2425: .d ('0 ),
2426:
2427: // to internal hardware
2428: .qe (),
2429: .q (reg2hw.rxenable_out[4].q ),
2430:
2431: // to register interface (read)
2432: .qs (rxenable_out_out4_qs)
2433: );
2434:
2435:
2436: // F[out5]: 5:5
2437: prim_subreg #(
2438: .DW (1),
2439: .SWACCESS("RW"),
2440: .RESVAL (1'h0)
2441: ) u_rxenable_out_out5 (
2442: .clk_i (clk_i ),
2443: .rst_ni (rst_ni ),
2444:
2445: // from register interface
2446: .we (rxenable_out_out5_we),
2447: .wd (rxenable_out_out5_wd),
2448:
2449: // from internal hardware
2450: .de (1'b0),
2451: .d ('0 ),
2452:
2453: // to internal hardware
2454: .qe (),
2455: .q (reg2hw.rxenable_out[5].q ),
2456:
2457: // to register interface (read)
2458: .qs (rxenable_out_out5_qs)
2459: );
2460:
2461:
2462: // F[out6]: 6:6
2463: prim_subreg #(
2464: .DW (1),
2465: .SWACCESS("RW"),
2466: .RESVAL (1'h0)
2467: ) u_rxenable_out_out6 (
2468: .clk_i (clk_i ),
2469: .rst_ni (rst_ni ),
2470:
2471: // from register interface
2472: .we (rxenable_out_out6_we),
2473: .wd (rxenable_out_out6_wd),
2474:
2475: // from internal hardware
2476: .de (1'b0),
2477: .d ('0 ),
2478:
2479: // to internal hardware
2480: .qe (),
2481: .q (reg2hw.rxenable_out[6].q ),
2482:
2483: // to register interface (read)
2484: .qs (rxenable_out_out6_qs)
2485: );
2486:
2487:
2488: // F[out7]: 7:7
2489: prim_subreg #(
2490: .DW (1),
2491: .SWACCESS("RW"),
2492: .RESVAL (1'h0)
2493: ) u_rxenable_out_out7 (
2494: .clk_i (clk_i ),
2495: .rst_ni (rst_ni ),
2496:
2497: // from register interface
2498: .we (rxenable_out_out7_we),
2499: .wd (rxenable_out_out7_wd),
2500:
2501: // from internal hardware
2502: .de (1'b0),
2503: .d ('0 ),
2504:
2505: // to internal hardware
2506: .qe (),
2507: .q (reg2hw.rxenable_out[7].q ),
2508:
2509: // to register interface (read)
2510: .qs (rxenable_out_out7_qs)
2511: );
2512:
2513:
2514: // F[out8]: 8:8
2515: prim_subreg #(
2516: .DW (1),
2517: .SWACCESS("RW"),
2518: .RESVAL (1'h0)
2519: ) u_rxenable_out_out8 (
2520: .clk_i (clk_i ),
2521: .rst_ni (rst_ni ),
2522:
2523: // from register interface
2524: .we (rxenable_out_out8_we),
2525: .wd (rxenable_out_out8_wd),
2526:
2527: // from internal hardware
2528: .de (1'b0),
2529: .d ('0 ),
2530:
2531: // to internal hardware
2532: .qe (),
2533: .q (reg2hw.rxenable_out[8].q ),
2534:
2535: // to register interface (read)
2536: .qs (rxenable_out_out8_qs)
2537: );
2538:
2539:
2540: // F[out9]: 9:9
2541: prim_subreg #(
2542: .DW (1),
2543: .SWACCESS("RW"),
2544: .RESVAL (1'h0)
2545: ) u_rxenable_out_out9 (
2546: .clk_i (clk_i ),
2547: .rst_ni (rst_ni ),
2548:
2549: // from register interface
2550: .we (rxenable_out_out9_we),
2551: .wd (rxenable_out_out9_wd),
2552:
2553: // from internal hardware
2554: .de (1'b0),
2555: .d ('0 ),
2556:
2557: // to internal hardware
2558: .qe (),
2559: .q (reg2hw.rxenable_out[9].q ),
2560:
2561: // to register interface (read)
2562: .qs (rxenable_out_out9_qs)
2563: );
2564:
2565:
2566: // F[out10]: 10:10
2567: prim_subreg #(
2568: .DW (1),
2569: .SWACCESS("RW"),
2570: .RESVAL (1'h0)
2571: ) u_rxenable_out_out10 (
2572: .clk_i (clk_i ),
2573: .rst_ni (rst_ni ),
2574:
2575: // from register interface
2576: .we (rxenable_out_out10_we),
2577: .wd (rxenable_out_out10_wd),
2578:
2579: // from internal hardware
2580: .de (1'b0),
2581: .d ('0 ),
2582:
2583: // to internal hardware
2584: .qe (),
2585: .q (reg2hw.rxenable_out[10].q ),
2586:
2587: // to register interface (read)
2588: .qs (rxenable_out_out10_qs)
2589: );
2590:
2591:
2592: // F[out11]: 11:11
2593: prim_subreg #(
2594: .DW (1),
2595: .SWACCESS("RW"),
2596: .RESVAL (1'h0)
2597: ) u_rxenable_out_out11 (
2598: .clk_i (clk_i ),
2599: .rst_ni (rst_ni ),
2600:
2601: // from register interface
2602: .we (rxenable_out_out11_we),
2603: .wd (rxenable_out_out11_wd),
2604:
2605: // from internal hardware
2606: .de (1'b0),
2607: .d ('0 ),
2608:
2609: // to internal hardware
2610: .qe (),
2611: .q (reg2hw.rxenable_out[11].q ),
2612:
2613: // to register interface (read)
2614: .qs (rxenable_out_out11_qs)
2615: );
2616:
2617:
2618:
2619:
2620: // Subregister 0 of Multireg in_sent
2621: // R[in_sent]: V(False)
2622:
2623: // F[sent0]: 0:0
2624: prim_subreg #(
2625: .DW (1),
2626: .SWACCESS("W1C"),
2627: .RESVAL (1'h0)
2628: ) u_in_sent_sent0 (
2629: .clk_i (clk_i ),
2630: .rst_ni (rst_ni ),
2631:
2632: // from register interface
2633: .we (in_sent_sent0_we),
2634: .wd (in_sent_sent0_wd),
2635:
2636: // from internal hardware
2637: .de (hw2reg.in_sent[0].de),
2638: .d (hw2reg.in_sent[0].d ),
2639:
2640: // to internal hardware
2641: .qe (),
2642: .q (),
2643:
2644: // to register interface (read)
2645: .qs (in_sent_sent0_qs)
2646: );
2647:
2648:
2649: // F[sent1]: 1:1
2650: prim_subreg #(
2651: .DW (1),
2652: .SWACCESS("W1C"),
2653: .RESVAL (1'h0)
2654: ) u_in_sent_sent1 (
2655: .clk_i (clk_i ),
2656: .rst_ni (rst_ni ),
2657:
2658: // from register interface
2659: .we (in_sent_sent1_we),
2660: .wd (in_sent_sent1_wd),
2661:
2662: // from internal hardware
2663: .de (hw2reg.in_sent[1].de),
2664: .d (hw2reg.in_sent[1].d ),
2665:
2666: // to internal hardware
2667: .qe (),
2668: .q (),
2669:
2670: // to register interface (read)
2671: .qs (in_sent_sent1_qs)
2672: );
2673:
2674:
2675: // F[sent2]: 2:2
2676: prim_subreg #(
2677: .DW (1),
2678: .SWACCESS("W1C"),
2679: .RESVAL (1'h0)
2680: ) u_in_sent_sent2 (
2681: .clk_i (clk_i ),
2682: .rst_ni (rst_ni ),
2683:
2684: // from register interface
2685: .we (in_sent_sent2_we),
2686: .wd (in_sent_sent2_wd),
2687:
2688: // from internal hardware
2689: .de (hw2reg.in_sent[2].de),
2690: .d (hw2reg.in_sent[2].d ),
2691:
2692: // to internal hardware
2693: .qe (),
2694: .q (),
2695:
2696: // to register interface (read)
2697: .qs (in_sent_sent2_qs)
2698: );
2699:
2700:
2701: // F[sent3]: 3:3
2702: prim_subreg #(
2703: .DW (1),
2704: .SWACCESS("W1C"),
2705: .RESVAL (1'h0)
2706: ) u_in_sent_sent3 (
2707: .clk_i (clk_i ),
2708: .rst_ni (rst_ni ),
2709:
2710: // from register interface
2711: .we (in_sent_sent3_we),
2712: .wd (in_sent_sent3_wd),
2713:
2714: // from internal hardware
2715: .de (hw2reg.in_sent[3].de),
2716: .d (hw2reg.in_sent[3].d ),
2717:
2718: // to internal hardware
2719: .qe (),
2720: .q (),
2721:
2722: // to register interface (read)
2723: .qs (in_sent_sent3_qs)
2724: );
2725:
2726:
2727: // F[sent4]: 4:4
2728: prim_subreg #(
2729: .DW (1),
2730: .SWACCESS("W1C"),
2731: .RESVAL (1'h0)
2732: ) u_in_sent_sent4 (
2733: .clk_i (clk_i ),
2734: .rst_ni (rst_ni ),
2735:
2736: // from register interface
2737: .we (in_sent_sent4_we),
2738: .wd (in_sent_sent4_wd),
2739:
2740: // from internal hardware
2741: .de (hw2reg.in_sent[4].de),
2742: .d (hw2reg.in_sent[4].d ),
2743:
2744: // to internal hardware
2745: .qe (),
2746: .q (),
2747:
2748: // to register interface (read)
2749: .qs (in_sent_sent4_qs)
2750: );
2751:
2752:
2753: // F[sent5]: 5:5
2754: prim_subreg #(
2755: .DW (1),
2756: .SWACCESS("W1C"),
2757: .RESVAL (1'h0)
2758: ) u_in_sent_sent5 (
2759: .clk_i (clk_i ),
2760: .rst_ni (rst_ni ),
2761:
2762: // from register interface
2763: .we (in_sent_sent5_we),
2764: .wd (in_sent_sent5_wd),
2765:
2766: // from internal hardware
2767: .de (hw2reg.in_sent[5].de),
2768: .d (hw2reg.in_sent[5].d ),
2769:
2770: // to internal hardware
2771: .qe (),
2772: .q (),
2773:
2774: // to register interface (read)
2775: .qs (in_sent_sent5_qs)
2776: );
2777:
2778:
2779: // F[sent6]: 6:6
2780: prim_subreg #(
2781: .DW (1),
2782: .SWACCESS("W1C"),
2783: .RESVAL (1'h0)
2784: ) u_in_sent_sent6 (
2785: .clk_i (clk_i ),
2786: .rst_ni (rst_ni ),
2787:
2788: // from register interface
2789: .we (in_sent_sent6_we),
2790: .wd (in_sent_sent6_wd),
2791:
2792: // from internal hardware
2793: .de (hw2reg.in_sent[6].de),
2794: .d (hw2reg.in_sent[6].d ),
2795:
2796: // to internal hardware
2797: .qe (),
2798: .q (),
2799:
2800: // to register interface (read)
2801: .qs (in_sent_sent6_qs)
2802: );
2803:
2804:
2805: // F[sent7]: 7:7
2806: prim_subreg #(
2807: .DW (1),
2808: .SWACCESS("W1C"),
2809: .RESVAL (1'h0)
2810: ) u_in_sent_sent7 (
2811: .clk_i (clk_i ),
2812: .rst_ni (rst_ni ),
2813:
2814: // from register interface
2815: .we (in_sent_sent7_we),
2816: .wd (in_sent_sent7_wd),
2817:
2818: // from internal hardware
2819: .de (hw2reg.in_sent[7].de),
2820: .d (hw2reg.in_sent[7].d ),
2821:
2822: // to internal hardware
2823: .qe (),
2824: .q (),
2825:
2826: // to register interface (read)
2827: .qs (in_sent_sent7_qs)
2828: );
2829:
2830:
2831: // F[sent8]: 8:8
2832: prim_subreg #(
2833: .DW (1),
2834: .SWACCESS("W1C"),
2835: .RESVAL (1'h0)
2836: ) u_in_sent_sent8 (
2837: .clk_i (clk_i ),
2838: .rst_ni (rst_ni ),
2839:
2840: // from register interface
2841: .we (in_sent_sent8_we),
2842: .wd (in_sent_sent8_wd),
2843:
2844: // from internal hardware
2845: .de (hw2reg.in_sent[8].de),
2846: .d (hw2reg.in_sent[8].d ),
2847:
2848: // to internal hardware
2849: .qe (),
2850: .q (),
2851:
2852: // to register interface (read)
2853: .qs (in_sent_sent8_qs)
2854: );
2855:
2856:
2857: // F[sent9]: 9:9
2858: prim_subreg #(
2859: .DW (1),
2860: .SWACCESS("W1C"),
2861: .RESVAL (1'h0)
2862: ) u_in_sent_sent9 (
2863: .clk_i (clk_i ),
2864: .rst_ni (rst_ni ),
2865:
2866: // from register interface
2867: .we (in_sent_sent9_we),
2868: .wd (in_sent_sent9_wd),
2869:
2870: // from internal hardware
2871: .de (hw2reg.in_sent[9].de),
2872: .d (hw2reg.in_sent[9].d ),
2873:
2874: // to internal hardware
2875: .qe (),
2876: .q (),
2877:
2878: // to register interface (read)
2879: .qs (in_sent_sent9_qs)
2880: );
2881:
2882:
2883: // F[sent10]: 10:10
2884: prim_subreg #(
2885: .DW (1),
2886: .SWACCESS("W1C"),
2887: .RESVAL (1'h0)
2888: ) u_in_sent_sent10 (
2889: .clk_i (clk_i ),
2890: .rst_ni (rst_ni ),
2891:
2892: // from register interface
2893: .we (in_sent_sent10_we),
2894: .wd (in_sent_sent10_wd),
2895:
2896: // from internal hardware
2897: .de (hw2reg.in_sent[10].de),
2898: .d (hw2reg.in_sent[10].d ),
2899:
2900: // to internal hardware
2901: .qe (),
2902: .q (),
2903:
2904: // to register interface (read)
2905: .qs (in_sent_sent10_qs)
2906: );
2907:
2908:
2909: // F[sent11]: 11:11
2910: prim_subreg #(
2911: .DW (1),
2912: .SWACCESS("W1C"),
2913: .RESVAL (1'h0)
2914: ) u_in_sent_sent11 (
2915: .clk_i (clk_i ),
2916: .rst_ni (rst_ni ),
2917:
2918: // from register interface
2919: .we (in_sent_sent11_we),
2920: .wd (in_sent_sent11_wd),
2921:
2922: // from internal hardware
2923: .de (hw2reg.in_sent[11].de),
2924: .d (hw2reg.in_sent[11].d ),
2925:
2926: // to internal hardware
2927: .qe (),
2928: .q (),
2929:
2930: // to register interface (read)
2931: .qs (in_sent_sent11_qs)
2932: );
2933:
2934:
2935:
2936:
2937: // Subregister 0 of Multireg stall
2938: // R[stall]: V(False)
2939:
2940: // F[stall0]: 0:0
2941: prim_subreg #(
2942: .DW (1),
2943: .SWACCESS("RW"),
2944: .RESVAL (1'h0)
2945: ) u_stall_stall0 (
2946: .clk_i (clk_i ),
2947: .rst_ni (rst_ni ),
2948:
2949: // from register interface
2950: .we (stall_stall0_we),
2951: .wd (stall_stall0_wd),
2952:
2953: // from internal hardware
2954: .de (hw2reg.stall[0].de),
2955: .d (hw2reg.stall[0].d ),
2956:
2957: // to internal hardware
2958: .qe (),
2959: .q (reg2hw.stall[0].q ),
2960:
2961: // to register interface (read)
2962: .qs (stall_stall0_qs)
2963: );
2964:
2965:
2966: // F[stall1]: 1:1
2967: prim_subreg #(
2968: .DW (1),
2969: .SWACCESS("RW"),
2970: .RESVAL (1'h0)
2971: ) u_stall_stall1 (
2972: .clk_i (clk_i ),
2973: .rst_ni (rst_ni ),
2974:
2975: // from register interface
2976: .we (stall_stall1_we),
2977: .wd (stall_stall1_wd),
2978:
2979: // from internal hardware
2980: .de (hw2reg.stall[1].de),
2981: .d (hw2reg.stall[1].d ),
2982:
2983: // to internal hardware
2984: .qe (),
2985: .q (reg2hw.stall[1].q ),
2986:
2987: // to register interface (read)
2988: .qs (stall_stall1_qs)
2989: );
2990:
2991:
2992: // F[stall2]: 2:2
2993: prim_subreg #(
2994: .DW (1),
2995: .SWACCESS("RW"),
2996: .RESVAL (1'h0)
2997: ) u_stall_stall2 (
2998: .clk_i (clk_i ),
2999: .rst_ni (rst_ni ),
3000:
3001: // from register interface
3002: .we (stall_stall2_we),
3003: .wd (stall_stall2_wd),
3004:
3005: // from internal hardware
3006: .de (hw2reg.stall[2].de),
3007: .d (hw2reg.stall[2].d ),
3008:
3009: // to internal hardware
3010: .qe (),
3011: .q (reg2hw.stall[2].q ),
3012:
3013: // to register interface (read)
3014: .qs (stall_stall2_qs)
3015: );
3016:
3017:
3018: // F[stall3]: 3:3
3019: prim_subreg #(
3020: .DW (1),
3021: .SWACCESS("RW"),
3022: .RESVAL (1'h0)
3023: ) u_stall_stall3 (
3024: .clk_i (clk_i ),
3025: .rst_ni (rst_ni ),
3026:
3027: // from register interface
3028: .we (stall_stall3_we),
3029: .wd (stall_stall3_wd),
3030:
3031: // from internal hardware
3032: .de (hw2reg.stall[3].de),
3033: .d (hw2reg.stall[3].d ),
3034:
3035: // to internal hardware
3036: .qe (),
3037: .q (reg2hw.stall[3].q ),
3038:
3039: // to register interface (read)
3040: .qs (stall_stall3_qs)
3041: );
3042:
3043:
3044: // F[stall4]: 4:4
3045: prim_subreg #(
3046: .DW (1),
3047: .SWACCESS("RW"),
3048: .RESVAL (1'h0)
3049: ) u_stall_stall4 (
3050: .clk_i (clk_i ),
3051: .rst_ni (rst_ni ),
3052:
3053: // from register interface
3054: .we (stall_stall4_we),
3055: .wd (stall_stall4_wd),
3056:
3057: // from internal hardware
3058: .de (hw2reg.stall[4].de),
3059: .d (hw2reg.stall[4].d ),
3060:
3061: // to internal hardware
3062: .qe (),
3063: .q (reg2hw.stall[4].q ),
3064:
3065: // to register interface (read)
3066: .qs (stall_stall4_qs)
3067: );
3068:
3069:
3070: // F[stall5]: 5:5
3071: prim_subreg #(
3072: .DW (1),
3073: .SWACCESS("RW"),
3074: .RESVAL (1'h0)
3075: ) u_stall_stall5 (
3076: .clk_i (clk_i ),
3077: .rst_ni (rst_ni ),
3078:
3079: // from register interface
3080: .we (stall_stall5_we),
3081: .wd (stall_stall5_wd),
3082:
3083: // from internal hardware
3084: .de (hw2reg.stall[5].de),
3085: .d (hw2reg.stall[5].d ),
3086:
3087: // to internal hardware
3088: .qe (),
3089: .q (reg2hw.stall[5].q ),
3090:
3091: // to register interface (read)
3092: .qs (stall_stall5_qs)
3093: );
3094:
3095:
3096: // F[stall6]: 6:6
3097: prim_subreg #(
3098: .DW (1),
3099: .SWACCESS("RW"),
3100: .RESVAL (1'h0)
3101: ) u_stall_stall6 (
3102: .clk_i (clk_i ),
3103: .rst_ni (rst_ni ),
3104:
3105: // from register interface
3106: .we (stall_stall6_we),
3107: .wd (stall_stall6_wd),
3108:
3109: // from internal hardware
3110: .de (hw2reg.stall[6].de),
3111: .d (hw2reg.stall[6].d ),
3112:
3113: // to internal hardware
3114: .qe (),
3115: .q (reg2hw.stall[6].q ),
3116:
3117: // to register interface (read)
3118: .qs (stall_stall6_qs)
3119: );
3120:
3121:
3122: // F[stall7]: 7:7
3123: prim_subreg #(
3124: .DW (1),
3125: .SWACCESS("RW"),
3126: .RESVAL (1'h0)
3127: ) u_stall_stall7 (
3128: .clk_i (clk_i ),
3129: .rst_ni (rst_ni ),
3130:
3131: // from register interface
3132: .we (stall_stall7_we),
3133: .wd (stall_stall7_wd),
3134:
3135: // from internal hardware
3136: .de (hw2reg.stall[7].de),
3137: .d (hw2reg.stall[7].d ),
3138:
3139: // to internal hardware
3140: .qe (),
3141: .q (reg2hw.stall[7].q ),
3142:
3143: // to register interface (read)
3144: .qs (stall_stall7_qs)
3145: );
3146:
3147:
3148: // F[stall8]: 8:8
3149: prim_subreg #(
3150: .DW (1),
3151: .SWACCESS("RW"),
3152: .RESVAL (1'h0)
3153: ) u_stall_stall8 (
3154: .clk_i (clk_i ),
3155: .rst_ni (rst_ni ),
3156:
3157: // from register interface
3158: .we (stall_stall8_we),
3159: .wd (stall_stall8_wd),
3160:
3161: // from internal hardware
3162: .de (hw2reg.stall[8].de),
3163: .d (hw2reg.stall[8].d ),
3164:
3165: // to internal hardware
3166: .qe (),
3167: .q (reg2hw.stall[8].q ),
3168:
3169: // to register interface (read)
3170: .qs (stall_stall8_qs)
3171: );
3172:
3173:
3174: // F[stall9]: 9:9
3175: prim_subreg #(
3176: .DW (1),
3177: .SWACCESS("RW"),
3178: .RESVAL (1'h0)
3179: ) u_stall_stall9 (
3180: .clk_i (clk_i ),
3181: .rst_ni (rst_ni ),
3182:
3183: // from register interface
3184: .we (stall_stall9_we),
3185: .wd (stall_stall9_wd),
3186:
3187: // from internal hardware
3188: .de (hw2reg.stall[9].de),
3189: .d (hw2reg.stall[9].d ),
3190:
3191: // to internal hardware
3192: .qe (),
3193: .q (reg2hw.stall[9].q ),
3194:
3195: // to register interface (read)
3196: .qs (stall_stall9_qs)
3197: );
3198:
3199:
3200: // F[stall10]: 10:10
3201: prim_subreg #(
3202: .DW (1),
3203: .SWACCESS("RW"),
3204: .RESVAL (1'h0)
3205: ) u_stall_stall10 (
3206: .clk_i (clk_i ),
3207: .rst_ni (rst_ni ),
3208:
3209: // from register interface
3210: .we (stall_stall10_we),
3211: .wd (stall_stall10_wd),
3212:
3213: // from internal hardware
3214: .de (hw2reg.stall[10].de),
3215: .d (hw2reg.stall[10].d ),
3216:
3217: // to internal hardware
3218: .qe (),
3219: .q (reg2hw.stall[10].q ),
3220:
3221: // to register interface (read)
3222: .qs (stall_stall10_qs)
3223: );
3224:
3225:
3226: // F[stall11]: 11:11
3227: prim_subreg #(
3228: .DW (1),
3229: .SWACCESS("RW"),
3230: .RESVAL (1'h0)
3231: ) u_stall_stall11 (
3232: .clk_i (clk_i ),
3233: .rst_ni (rst_ni ),
3234:
3235: // from register interface
3236: .we (stall_stall11_we),
3237: .wd (stall_stall11_wd),
3238:
3239: // from internal hardware
3240: .de (hw2reg.stall[11].de),
3241: .d (hw2reg.stall[11].d ),
3242:
3243: // to internal hardware
3244: .qe (),
3245: .q (reg2hw.stall[11].q ),
3246:
3247: // to register interface (read)
3248: .qs (stall_stall11_qs)
3249: );
3250:
3251:
3252:
3253:
3254: // Subregister 0 of Multireg configin
3255: // R[configin0]: V(False)
3256:
3257: // F[buffer0]: 4:0
3258: prim_subreg #(
3259: .DW (5),
3260: .SWACCESS("RW"),
3261: .RESVAL (5'h0)
3262: ) u_configin0_buffer0 (
3263: .clk_i (clk_i ),
3264: .rst_ni (rst_ni ),
3265:
3266: // from register interface
3267: .we (configin0_buffer0_we),
3268: .wd (configin0_buffer0_wd),
3269:
3270: // from internal hardware
3271: .de (1'b0),
3272: .d ('0 ),
3273:
3274: // to internal hardware
3275: .qe (),
3276: .q (reg2hw.configin[0].buffer.q ),
3277:
3278: // to register interface (read)
3279: .qs (configin0_buffer0_qs)
3280: );
3281:
3282:
3283: // F[size0]: 14:8
3284: prim_subreg #(
3285: .DW (7),
3286: .SWACCESS("RW"),
3287: .RESVAL (7'h0)
3288: ) u_configin0_size0 (
3289: .clk_i (clk_i ),
3290: .rst_ni (rst_ni ),
3291:
3292: // from register interface
3293: .we (configin0_size0_we),
3294: .wd (configin0_size0_wd),
3295:
3296: // from internal hardware
3297: .de (1'b0),
3298: .d ('0 ),
3299:
3300: // to internal hardware
3301: .qe (),
3302: .q (reg2hw.configin[0].size.q ),
3303:
3304: // to register interface (read)
3305: .qs (configin0_size0_qs)
3306: );
3307:
3308:
3309: // F[pend0]: 30:30
3310: prim_subreg #(
3311: .DW (1),
3312: .SWACCESS("W1C"),
3313: .RESVAL (1'h0)
3314: ) u_configin0_pend0 (
3315: .clk_i (clk_i ),
3316: .rst_ni (rst_ni ),
3317:
3318: // from register interface
3319: .we (configin0_pend0_we),
3320: .wd (configin0_pend0_wd),
3321:
3322: // from internal hardware
3323: .de (hw2reg.configin[0].pend.de),
3324: .d (hw2reg.configin[0].pend.d ),
3325:
3326: // to internal hardware
3327: .qe (),
3328: .q (reg2hw.configin[0].pend.q ),
3329:
3330: // to register interface (read)
3331: .qs (configin0_pend0_qs)
3332: );
3333:
3334:
3335: // F[rdy0]: 31:31
3336: prim_subreg #(
3337: .DW (1),
3338: .SWACCESS("RW"),
3339: .RESVAL (1'h0)
3340: ) u_configin0_rdy0 (
3341: .clk_i (clk_i ),
3342: .rst_ni (rst_ni ),
3343:
3344: // from register interface
3345: .we (configin0_rdy0_we),
3346: .wd (configin0_rdy0_wd),
3347:
3348: // from internal hardware
3349: .de (hw2reg.configin[0].rdy.de),
3350: .d (hw2reg.configin[0].rdy.d ),
3351:
3352: // to internal hardware
3353: .qe (),
3354: .q (reg2hw.configin[0].rdy.q ),
3355:
3356: // to register interface (read)
3357: .qs (configin0_rdy0_qs)
3358: );
3359:
3360:
3361: // Subregister 1 of Multireg configin
3362: // R[configin1]: V(False)
3363:
3364: // F[buffer1]: 4:0
3365: prim_subreg #(
3366: .DW (5),
3367: .SWACCESS("RW"),
3368: .RESVAL (5'h0)
3369: ) u_configin1_buffer1 (
3370: .clk_i (clk_i ),
3371: .rst_ni (rst_ni ),
3372:
3373: // from register interface
3374: .we (configin1_buffer1_we),
3375: .wd (configin1_buffer1_wd),
3376:
3377: // from internal hardware
3378: .de (1'b0),
3379: .d ('0 ),
3380:
3381: // to internal hardware
3382: .qe (),
3383: .q (reg2hw.configin[1].buffer.q ),
3384:
3385: // to register interface (read)
3386: .qs (configin1_buffer1_qs)
3387: );
3388:
3389:
3390: // F[size1]: 14:8
3391: prim_subreg #(
3392: .DW (7),
3393: .SWACCESS("RW"),
3394: .RESVAL (7'h0)
3395: ) u_configin1_size1 (
3396: .clk_i (clk_i ),
3397: .rst_ni (rst_ni ),
3398:
3399: // from register interface
3400: .we (configin1_size1_we),
3401: .wd (configin1_size1_wd),
3402:
3403: // from internal hardware
3404: .de (1'b0),
3405: .d ('0 ),
3406:
3407: // to internal hardware
3408: .qe (),
3409: .q (reg2hw.configin[1].size.q ),
3410:
3411: // to register interface (read)
3412: .qs (configin1_size1_qs)
3413: );
3414:
3415:
3416: // F[pend1]: 30:30
3417: prim_subreg #(
3418: .DW (1),
3419: .SWACCESS("W1C"),
3420: .RESVAL (1'h0)
3421: ) u_configin1_pend1 (
3422: .clk_i (clk_i ),
3423: .rst_ni (rst_ni ),
3424:
3425: // from register interface
3426: .we (configin1_pend1_we),
3427: .wd (configin1_pend1_wd),
3428:
3429: // from internal hardware
3430: .de (hw2reg.configin[1].pend.de),
3431: .d (hw2reg.configin[1].pend.d ),
3432:
3433: // to internal hardware
3434: .qe (),
3435: .q (reg2hw.configin[1].pend.q ),
3436:
3437: // to register interface (read)
3438: .qs (configin1_pend1_qs)
3439: );
3440:
3441:
3442: // F[rdy1]: 31:31
3443: prim_subreg #(
3444: .DW (1),
3445: .SWACCESS("RW"),
3446: .RESVAL (1'h0)
3447: ) u_configin1_rdy1 (
3448: .clk_i (clk_i ),
3449: .rst_ni (rst_ni ),
3450:
3451: // from register interface
3452: .we (configin1_rdy1_we),
3453: .wd (configin1_rdy1_wd),
3454:
3455: // from internal hardware
3456: .de (hw2reg.configin[1].rdy.de),
3457: .d (hw2reg.configin[1].rdy.d ),
3458:
3459: // to internal hardware
3460: .qe (),
3461: .q (reg2hw.configin[1].rdy.q ),
3462:
3463: // to register interface (read)
3464: .qs (configin1_rdy1_qs)
3465: );
3466:
3467:
3468: // Subregister 2 of Multireg configin
3469: // R[configin2]: V(False)
3470:
3471: // F[buffer2]: 4:0
3472: prim_subreg #(
3473: .DW (5),
3474: .SWACCESS("RW"),
3475: .RESVAL (5'h0)
3476: ) u_configin2_buffer2 (
3477: .clk_i (clk_i ),
3478: .rst_ni (rst_ni ),
3479:
3480: // from register interface
3481: .we (configin2_buffer2_we),
3482: .wd (configin2_buffer2_wd),
3483:
3484: // from internal hardware
3485: .de (1'b0),
3486: .d ('0 ),
3487:
3488: // to internal hardware
3489: .qe (),
3490: .q (reg2hw.configin[2].buffer.q ),
3491:
3492: // to register interface (read)
3493: .qs (configin2_buffer2_qs)
3494: );
3495:
3496:
3497: // F[size2]: 14:8
3498: prim_subreg #(
3499: .DW (7),
3500: .SWACCESS("RW"),
3501: .RESVAL (7'h0)
3502: ) u_configin2_size2 (
3503: .clk_i (clk_i ),
3504: .rst_ni (rst_ni ),
3505:
3506: // from register interface
3507: .we (configin2_size2_we),
3508: .wd (configin2_size2_wd),
3509:
3510: // from internal hardware
3511: .de (1'b0),
3512: .d ('0 ),
3513:
3514: // to internal hardware
3515: .qe (),
3516: .q (reg2hw.configin[2].size.q ),
3517:
3518: // to register interface (read)
3519: .qs (configin2_size2_qs)
3520: );
3521:
3522:
3523: // F[pend2]: 30:30
3524: prim_subreg #(
3525: .DW (1),
3526: .SWACCESS("W1C"),
3527: .RESVAL (1'h0)
3528: ) u_configin2_pend2 (
3529: .clk_i (clk_i ),
3530: .rst_ni (rst_ni ),
3531:
3532: // from register interface
3533: .we (configin2_pend2_we),
3534: .wd (configin2_pend2_wd),
3535:
3536: // from internal hardware
3537: .de (hw2reg.configin[2].pend.de),
3538: .d (hw2reg.configin[2].pend.d ),
3539:
3540: // to internal hardware
3541: .qe (),
3542: .q (reg2hw.configin[2].pend.q ),
3543:
3544: // to register interface (read)
3545: .qs (configin2_pend2_qs)
3546: );
3547:
3548:
3549: // F[rdy2]: 31:31
3550: prim_subreg #(
3551: .DW (1),
3552: .SWACCESS("RW"),
3553: .RESVAL (1'h0)
3554: ) u_configin2_rdy2 (
3555: .clk_i (clk_i ),
3556: .rst_ni (rst_ni ),
3557:
3558: // from register interface
3559: .we (configin2_rdy2_we),
3560: .wd (configin2_rdy2_wd),
3561:
3562: // from internal hardware
3563: .de (hw2reg.configin[2].rdy.de),
3564: .d (hw2reg.configin[2].rdy.d ),
3565:
3566: // to internal hardware
3567: .qe (),
3568: .q (reg2hw.configin[2].rdy.q ),
3569:
3570: // to register interface (read)
3571: .qs (configin2_rdy2_qs)
3572: );
3573:
3574:
3575: // Subregister 3 of Multireg configin
3576: // R[configin3]: V(False)
3577:
3578: // F[buffer3]: 4:0
3579: prim_subreg #(
3580: .DW (5),
3581: .SWACCESS("RW"),
3582: .RESVAL (5'h0)
3583: ) u_configin3_buffer3 (
3584: .clk_i (clk_i ),
3585: .rst_ni (rst_ni ),
3586:
3587: // from register interface
3588: .we (configin3_buffer3_we),
3589: .wd (configin3_buffer3_wd),
3590:
3591: // from internal hardware
3592: .de (1'b0),
3593: .d ('0 ),
3594:
3595: // to internal hardware
3596: .qe (),
3597: .q (reg2hw.configin[3].buffer.q ),
3598:
3599: // to register interface (read)
3600: .qs (configin3_buffer3_qs)
3601: );
3602:
3603:
3604: // F[size3]: 14:8
3605: prim_subreg #(
3606: .DW (7),
3607: .SWACCESS("RW"),
3608: .RESVAL (7'h0)
3609: ) u_configin3_size3 (
3610: .clk_i (clk_i ),
3611: .rst_ni (rst_ni ),
3612:
3613: // from register interface
3614: .we (configin3_size3_we),
3615: .wd (configin3_size3_wd),
3616:
3617: // from internal hardware
3618: .de (1'b0),
3619: .d ('0 ),
3620:
3621: // to internal hardware
3622: .qe (),
3623: .q (reg2hw.configin[3].size.q ),
3624:
3625: // to register interface (read)
3626: .qs (configin3_size3_qs)
3627: );
3628:
3629:
3630: // F[pend3]: 30:30
3631: prim_subreg #(
3632: .DW (1),
3633: .SWACCESS("W1C"),
3634: .RESVAL (1'h0)
3635: ) u_configin3_pend3 (
3636: .clk_i (clk_i ),
3637: .rst_ni (rst_ni ),
3638:
3639: // from register interface
3640: .we (configin3_pend3_we),
3641: .wd (configin3_pend3_wd),
3642:
3643: // from internal hardware
3644: .de (hw2reg.configin[3].pend.de),
3645: .d (hw2reg.configin[3].pend.d ),
3646:
3647: // to internal hardware
3648: .qe (),
3649: .q (reg2hw.configin[3].pend.q ),
3650:
3651: // to register interface (read)
3652: .qs (configin3_pend3_qs)
3653: );
3654:
3655:
3656: // F[rdy3]: 31:31
3657: prim_subreg #(
3658: .DW (1),
3659: .SWACCESS("RW"),
3660: .RESVAL (1'h0)
3661: ) u_configin3_rdy3 (
3662: .clk_i (clk_i ),
3663: .rst_ni (rst_ni ),
3664:
3665: // from register interface
3666: .we (configin3_rdy3_we),
3667: .wd (configin3_rdy3_wd),
3668:
3669: // from internal hardware
3670: .de (hw2reg.configin[3].rdy.de),
3671: .d (hw2reg.configin[3].rdy.d ),
3672:
3673: // to internal hardware
3674: .qe (),
3675: .q (reg2hw.configin[3].rdy.q ),
3676:
3677: // to register interface (read)
3678: .qs (configin3_rdy3_qs)
3679: );
3680:
3681:
3682: // Subregister 4 of Multireg configin
3683: // R[configin4]: V(False)
3684:
3685: // F[buffer4]: 4:0
3686: prim_subreg #(
3687: .DW (5),
3688: .SWACCESS("RW"),
3689: .RESVAL (5'h0)
3690: ) u_configin4_buffer4 (
3691: .clk_i (clk_i ),
3692: .rst_ni (rst_ni ),
3693:
3694: // from register interface
3695: .we (configin4_buffer4_we),
3696: .wd (configin4_buffer4_wd),
3697:
3698: // from internal hardware
3699: .de (1'b0),
3700: .d ('0 ),
3701:
3702: // to internal hardware
3703: .qe (),
3704: .q (reg2hw.configin[4].buffer.q ),
3705:
3706: // to register interface (read)
3707: .qs (configin4_buffer4_qs)
3708: );
3709:
3710:
3711: // F[size4]: 14:8
3712: prim_subreg #(
3713: .DW (7),
3714: .SWACCESS("RW"),
3715: .RESVAL (7'h0)
3716: ) u_configin4_size4 (
3717: .clk_i (clk_i ),
3718: .rst_ni (rst_ni ),
3719:
3720: // from register interface
3721: .we (configin4_size4_we),
3722: .wd (configin4_size4_wd),
3723:
3724: // from internal hardware
3725: .de (1'b0),
3726: .d ('0 ),
3727:
3728: // to internal hardware
3729: .qe (),
3730: .q (reg2hw.configin[4].size.q ),
3731:
3732: // to register interface (read)
3733: .qs (configin4_size4_qs)
3734: );
3735:
3736:
3737: // F[pend4]: 30:30
3738: prim_subreg #(
3739: .DW (1),
3740: .SWACCESS("W1C"),
3741: .RESVAL (1'h0)
3742: ) u_configin4_pend4 (
3743: .clk_i (clk_i ),
3744: .rst_ni (rst_ni ),
3745:
3746: // from register interface
3747: .we (configin4_pend4_we),
3748: .wd (configin4_pend4_wd),
3749:
3750: // from internal hardware
3751: .de (hw2reg.configin[4].pend.de),
3752: .d (hw2reg.configin[4].pend.d ),
3753:
3754: // to internal hardware
3755: .qe (),
3756: .q (reg2hw.configin[4].pend.q ),
3757:
3758: // to register interface (read)
3759: .qs (configin4_pend4_qs)
3760: );
3761:
3762:
3763: // F[rdy4]: 31:31
3764: prim_subreg #(
3765: .DW (1),
3766: .SWACCESS("RW"),
3767: .RESVAL (1'h0)
3768: ) u_configin4_rdy4 (
3769: .clk_i (clk_i ),
3770: .rst_ni (rst_ni ),
3771:
3772: // from register interface
3773: .we (configin4_rdy4_we),
3774: .wd (configin4_rdy4_wd),
3775:
3776: // from internal hardware
3777: .de (hw2reg.configin[4].rdy.de),
3778: .d (hw2reg.configin[4].rdy.d ),
3779:
3780: // to internal hardware
3781: .qe (),
3782: .q (reg2hw.configin[4].rdy.q ),
3783:
3784: // to register interface (read)
3785: .qs (configin4_rdy4_qs)
3786: );
3787:
3788:
3789: // Subregister 5 of Multireg configin
3790: // R[configin5]: V(False)
3791:
3792: // F[buffer5]: 4:0
3793: prim_subreg #(
3794: .DW (5),
3795: .SWACCESS("RW"),
3796: .RESVAL (5'h0)
3797: ) u_configin5_buffer5 (
3798: .clk_i (clk_i ),
3799: .rst_ni (rst_ni ),
3800:
3801: // from register interface
3802: .we (configin5_buffer5_we),
3803: .wd (configin5_buffer5_wd),
3804:
3805: // from internal hardware
3806: .de (1'b0),
3807: .d ('0 ),
3808:
3809: // to internal hardware
3810: .qe (),
3811: .q (reg2hw.configin[5].buffer.q ),
3812:
3813: // to register interface (read)
3814: .qs (configin5_buffer5_qs)
3815: );
3816:
3817:
3818: // F[size5]: 14:8
3819: prim_subreg #(
3820: .DW (7),
3821: .SWACCESS("RW"),
3822: .RESVAL (7'h0)
3823: ) u_configin5_size5 (
3824: .clk_i (clk_i ),
3825: .rst_ni (rst_ni ),
3826:
3827: // from register interface
3828: .we (configin5_size5_we),
3829: .wd (configin5_size5_wd),
3830:
3831: // from internal hardware
3832: .de (1'b0),
3833: .d ('0 ),
3834:
3835: // to internal hardware
3836: .qe (),
3837: .q (reg2hw.configin[5].size.q ),
3838:
3839: // to register interface (read)
3840: .qs (configin5_size5_qs)
3841: );
3842:
3843:
3844: // F[pend5]: 30:30
3845: prim_subreg #(
3846: .DW (1),
3847: .SWACCESS("W1C"),
3848: .RESVAL (1'h0)
3849: ) u_configin5_pend5 (
3850: .clk_i (clk_i ),
3851: .rst_ni (rst_ni ),
3852:
3853: // from register interface
3854: .we (configin5_pend5_we),
3855: .wd (configin5_pend5_wd),
3856:
3857: // from internal hardware
3858: .de (hw2reg.configin[5].pend.de),
3859: .d (hw2reg.configin[5].pend.d ),
3860:
3861: // to internal hardware
3862: .qe (),
3863: .q (reg2hw.configin[5].pend.q ),
3864:
3865: // to register interface (read)
3866: .qs (configin5_pend5_qs)
3867: );
3868:
3869:
3870: // F[rdy5]: 31:31
3871: prim_subreg #(
3872: .DW (1),
3873: .SWACCESS("RW"),
3874: .RESVAL (1'h0)
3875: ) u_configin5_rdy5 (
3876: .clk_i (clk_i ),
3877: .rst_ni (rst_ni ),
3878:
3879: // from register interface
3880: .we (configin5_rdy5_we),
3881: .wd (configin5_rdy5_wd),
3882:
3883: // from internal hardware
3884: .de (hw2reg.configin[5].rdy.de),
3885: .d (hw2reg.configin[5].rdy.d ),
3886:
3887: // to internal hardware
3888: .qe (),
3889: .q (reg2hw.configin[5].rdy.q ),
3890:
3891: // to register interface (read)
3892: .qs (configin5_rdy5_qs)
3893: );
3894:
3895:
3896: // Subregister 6 of Multireg configin
3897: // R[configin6]: V(False)
3898:
3899: // F[buffer6]: 4:0
3900: prim_subreg #(
3901: .DW (5),
3902: .SWACCESS("RW"),
3903: .RESVAL (5'h0)
3904: ) u_configin6_buffer6 (
3905: .clk_i (clk_i ),
3906: .rst_ni (rst_ni ),
3907:
3908: // from register interface
3909: .we (configin6_buffer6_we),
3910: .wd (configin6_buffer6_wd),
3911:
3912: // from internal hardware
3913: .de (1'b0),
3914: .d ('0 ),
3915:
3916: // to internal hardware
3917: .qe (),
3918: .q (reg2hw.configin[6].buffer.q ),
3919:
3920: // to register interface (read)
3921: .qs (configin6_buffer6_qs)
3922: );
3923:
3924:
3925: // F[size6]: 14:8
3926: prim_subreg #(
3927: .DW (7),
3928: .SWACCESS("RW"),
3929: .RESVAL (7'h0)
3930: ) u_configin6_size6 (
3931: .clk_i (clk_i ),
3932: .rst_ni (rst_ni ),
3933:
3934: // from register interface
3935: .we (configin6_size6_we),
3936: .wd (configin6_size6_wd),
3937:
3938: // from internal hardware
3939: .de (1'b0),
3940: .d ('0 ),
3941:
3942: // to internal hardware
3943: .qe (),
3944: .q (reg2hw.configin[6].size.q ),
3945:
3946: // to register interface (read)
3947: .qs (configin6_size6_qs)
3948: );
3949:
3950:
3951: // F[pend6]: 30:30
3952: prim_subreg #(
3953: .DW (1),
3954: .SWACCESS("W1C"),
3955: .RESVAL (1'h0)
3956: ) u_configin6_pend6 (
3957: .clk_i (clk_i ),
3958: .rst_ni (rst_ni ),
3959:
3960: // from register interface
3961: .we (configin6_pend6_we),
3962: .wd (configin6_pend6_wd),
3963:
3964: // from internal hardware
3965: .de (hw2reg.configin[6].pend.de),
3966: .d (hw2reg.configin[6].pend.d ),
3967:
3968: // to internal hardware
3969: .qe (),
3970: .q (reg2hw.configin[6].pend.q ),
3971:
3972: // to register interface (read)
3973: .qs (configin6_pend6_qs)
3974: );
3975:
3976:
3977: // F[rdy6]: 31:31
3978: prim_subreg #(
3979: .DW (1),
3980: .SWACCESS("RW"),
3981: .RESVAL (1'h0)
3982: ) u_configin6_rdy6 (
3983: .clk_i (clk_i ),
3984: .rst_ni (rst_ni ),
3985:
3986: // from register interface
3987: .we (configin6_rdy6_we),
3988: .wd (configin6_rdy6_wd),
3989:
3990: // from internal hardware
3991: .de (hw2reg.configin[6].rdy.de),
3992: .d (hw2reg.configin[6].rdy.d ),
3993:
3994: // to internal hardware
3995: .qe (),
3996: .q (reg2hw.configin[6].rdy.q ),
3997:
3998: // to register interface (read)
3999: .qs (configin6_rdy6_qs)
4000: );
4001:
4002:
4003: // Subregister 7 of Multireg configin
4004: // R[configin7]: V(False)
4005:
4006: // F[buffer7]: 4:0
4007: prim_subreg #(
4008: .DW (5),
4009: .SWACCESS("RW"),
4010: .RESVAL (5'h0)
4011: ) u_configin7_buffer7 (
4012: .clk_i (clk_i ),
4013: .rst_ni (rst_ni ),
4014:
4015: // from register interface
4016: .we (configin7_buffer7_we),
4017: .wd (configin7_buffer7_wd),
4018:
4019: // from internal hardware
4020: .de (1'b0),
4021: .d ('0 ),
4022:
4023: // to internal hardware
4024: .qe (),
4025: .q (reg2hw.configin[7].buffer.q ),
4026:
4027: // to register interface (read)
4028: .qs (configin7_buffer7_qs)
4029: );
4030:
4031:
4032: // F[size7]: 14:8
4033: prim_subreg #(
4034: .DW (7),
4035: .SWACCESS("RW"),
4036: .RESVAL (7'h0)
4037: ) u_configin7_size7 (
4038: .clk_i (clk_i ),
4039: .rst_ni (rst_ni ),
4040:
4041: // from register interface
4042: .we (configin7_size7_we),
4043: .wd (configin7_size7_wd),
4044:
4045: // from internal hardware
4046: .de (1'b0),
4047: .d ('0 ),
4048:
4049: // to internal hardware
4050: .qe (),
4051: .q (reg2hw.configin[7].size.q ),
4052:
4053: // to register interface (read)
4054: .qs (configin7_size7_qs)
4055: );
4056:
4057:
4058: // F[pend7]: 30:30
4059: prim_subreg #(
4060: .DW (1),
4061: .SWACCESS("W1C"),
4062: .RESVAL (1'h0)
4063: ) u_configin7_pend7 (
4064: .clk_i (clk_i ),
4065: .rst_ni (rst_ni ),
4066:
4067: // from register interface
4068: .we (configin7_pend7_we),
4069: .wd (configin7_pend7_wd),
4070:
4071: // from internal hardware
4072: .de (hw2reg.configin[7].pend.de),
4073: .d (hw2reg.configin[7].pend.d ),
4074:
4075: // to internal hardware
4076: .qe (),
4077: .q (reg2hw.configin[7].pend.q ),
4078:
4079: // to register interface (read)
4080: .qs (configin7_pend7_qs)
4081: );
4082:
4083:
4084: // F[rdy7]: 31:31
4085: prim_subreg #(
4086: .DW (1),
4087: .SWACCESS("RW"),
4088: .RESVAL (1'h0)
4089: ) u_configin7_rdy7 (
4090: .clk_i (clk_i ),
4091: .rst_ni (rst_ni ),
4092:
4093: // from register interface
4094: .we (configin7_rdy7_we),
4095: .wd (configin7_rdy7_wd),
4096:
4097: // from internal hardware
4098: .de (hw2reg.configin[7].rdy.de),
4099: .d (hw2reg.configin[7].rdy.d ),
4100:
4101: // to internal hardware
4102: .qe (),
4103: .q (reg2hw.configin[7].rdy.q ),
4104:
4105: // to register interface (read)
4106: .qs (configin7_rdy7_qs)
4107: );
4108:
4109:
4110: // Subregister 8 of Multireg configin
4111: // R[configin8]: V(False)
4112:
4113: // F[buffer8]: 4:0
4114: prim_subreg #(
4115: .DW (5),
4116: .SWACCESS("RW"),
4117: .RESVAL (5'h0)
4118: ) u_configin8_buffer8 (
4119: .clk_i (clk_i ),
4120: .rst_ni (rst_ni ),
4121:
4122: // from register interface
4123: .we (configin8_buffer8_we),
4124: .wd (configin8_buffer8_wd),
4125:
4126: // from internal hardware
4127: .de (1'b0),
4128: .d ('0 ),
4129:
4130: // to internal hardware
4131: .qe (),
4132: .q (reg2hw.configin[8].buffer.q ),
4133:
4134: // to register interface (read)
4135: .qs (configin8_buffer8_qs)
4136: );
4137:
4138:
4139: // F[size8]: 14:8
4140: prim_subreg #(
4141: .DW (7),
4142: .SWACCESS("RW"),
4143: .RESVAL (7'h0)
4144: ) u_configin8_size8 (
4145: .clk_i (clk_i ),
4146: .rst_ni (rst_ni ),
4147:
4148: // from register interface
4149: .we (configin8_size8_we),
4150: .wd (configin8_size8_wd),
4151:
4152: // from internal hardware
4153: .de (1'b0),
4154: .d ('0 ),
4155:
4156: // to internal hardware
4157: .qe (),
4158: .q (reg2hw.configin[8].size.q ),
4159:
4160: // to register interface (read)
4161: .qs (configin8_size8_qs)
4162: );
4163:
4164:
4165: // F[pend8]: 30:30
4166: prim_subreg #(
4167: .DW (1),
4168: .SWACCESS("W1C"),
4169: .RESVAL (1'h0)
4170: ) u_configin8_pend8 (
4171: .clk_i (clk_i ),
4172: .rst_ni (rst_ni ),
4173:
4174: // from register interface
4175: .we (configin8_pend8_we),
4176: .wd (configin8_pend8_wd),
4177:
4178: // from internal hardware
4179: .de (hw2reg.configin[8].pend.de),
4180: .d (hw2reg.configin[8].pend.d ),
4181:
4182: // to internal hardware
4183: .qe (),
4184: .q (reg2hw.configin[8].pend.q ),
4185:
4186: // to register interface (read)
4187: .qs (configin8_pend8_qs)
4188: );
4189:
4190:
4191: // F[rdy8]: 31:31
4192: prim_subreg #(
4193: .DW (1),
4194: .SWACCESS("RW"),
4195: .RESVAL (1'h0)
4196: ) u_configin8_rdy8 (
4197: .clk_i (clk_i ),
4198: .rst_ni (rst_ni ),
4199:
4200: // from register interface
4201: .we (configin8_rdy8_we),
4202: .wd (configin8_rdy8_wd),
4203:
4204: // from internal hardware
4205: .de (hw2reg.configin[8].rdy.de),
4206: .d (hw2reg.configin[8].rdy.d ),
4207:
4208: // to internal hardware
4209: .qe (),
4210: .q (reg2hw.configin[8].rdy.q ),
4211:
4212: // to register interface (read)
4213: .qs (configin8_rdy8_qs)
4214: );
4215:
4216:
4217: // Subregister 9 of Multireg configin
4218: // R[configin9]: V(False)
4219:
4220: // F[buffer9]: 4:0
4221: prim_subreg #(
4222: .DW (5),
4223: .SWACCESS("RW"),
4224: .RESVAL (5'h0)
4225: ) u_configin9_buffer9 (
4226: .clk_i (clk_i ),
4227: .rst_ni (rst_ni ),
4228:
4229: // from register interface
4230: .we (configin9_buffer9_we),
4231: .wd (configin9_buffer9_wd),
4232:
4233: // from internal hardware
4234: .de (1'b0),
4235: .d ('0 ),
4236:
4237: // to internal hardware
4238: .qe (),
4239: .q (reg2hw.configin[9].buffer.q ),
4240:
4241: // to register interface (read)
4242: .qs (configin9_buffer9_qs)
4243: );
4244:
4245:
4246: // F[size9]: 14:8
4247: prim_subreg #(
4248: .DW (7),
4249: .SWACCESS("RW"),
4250: .RESVAL (7'h0)
4251: ) u_configin9_size9 (
4252: .clk_i (clk_i ),
4253: .rst_ni (rst_ni ),
4254:
4255: // from register interface
4256: .we (configin9_size9_we),
4257: .wd (configin9_size9_wd),
4258:
4259: // from internal hardware
4260: .de (1'b0),
4261: .d ('0 ),
4262:
4263: // to internal hardware
4264: .qe (),
4265: .q (reg2hw.configin[9].size.q ),
4266:
4267: // to register interface (read)
4268: .qs (configin9_size9_qs)
4269: );
4270:
4271:
4272: // F[pend9]: 30:30
4273: prim_subreg #(
4274: .DW (1),
4275: .SWACCESS("W1C"),
4276: .RESVAL (1'h0)
4277: ) u_configin9_pend9 (
4278: .clk_i (clk_i ),
4279: .rst_ni (rst_ni ),
4280:
4281: // from register interface
4282: .we (configin9_pend9_we),
4283: .wd (configin9_pend9_wd),
4284:
4285: // from internal hardware
4286: .de (hw2reg.configin[9].pend.de),
4287: .d (hw2reg.configin[9].pend.d ),
4288:
4289: // to internal hardware
4290: .qe (),
4291: .q (reg2hw.configin[9].pend.q ),
4292:
4293: // to register interface (read)
4294: .qs (configin9_pend9_qs)
4295: );
4296:
4297:
4298: // F[rdy9]: 31:31
4299: prim_subreg #(
4300: .DW (1),
4301: .SWACCESS("RW"),
4302: .RESVAL (1'h0)
4303: ) u_configin9_rdy9 (
4304: .clk_i (clk_i ),
4305: .rst_ni (rst_ni ),
4306:
4307: // from register interface
4308: .we (configin9_rdy9_we),
4309: .wd (configin9_rdy9_wd),
4310:
4311: // from internal hardware
4312: .de (hw2reg.configin[9].rdy.de),
4313: .d (hw2reg.configin[9].rdy.d ),
4314:
4315: // to internal hardware
4316: .qe (),
4317: .q (reg2hw.configin[9].rdy.q ),
4318:
4319: // to register interface (read)
4320: .qs (configin9_rdy9_qs)
4321: );
4322:
4323:
4324: // Subregister 10 of Multireg configin
4325: // R[configin10]: V(False)
4326:
4327: // F[buffer10]: 4:0
4328: prim_subreg #(
4329: .DW (5),
4330: .SWACCESS("RW"),
4331: .RESVAL (5'h0)
4332: ) u_configin10_buffer10 (
4333: .clk_i (clk_i ),
4334: .rst_ni (rst_ni ),
4335:
4336: // from register interface
4337: .we (configin10_buffer10_we),
4338: .wd (configin10_buffer10_wd),
4339:
4340: // from internal hardware
4341: .de (1'b0),
4342: .d ('0 ),
4343:
4344: // to internal hardware
4345: .qe (),
4346: .q (reg2hw.configin[10].buffer.q ),
4347:
4348: // to register interface (read)
4349: .qs (configin10_buffer10_qs)
4350: );
4351:
4352:
4353: // F[size10]: 14:8
4354: prim_subreg #(
4355: .DW (7),
4356: .SWACCESS("RW"),
4357: .RESVAL (7'h0)
4358: ) u_configin10_size10 (
4359: .clk_i (clk_i ),
4360: .rst_ni (rst_ni ),
4361:
4362: // from register interface
4363: .we (configin10_size10_we),
4364: .wd (configin10_size10_wd),
4365:
4366: // from internal hardware
4367: .de (1'b0),
4368: .d ('0 ),
4369:
4370: // to internal hardware
4371: .qe (),
4372: .q (reg2hw.configin[10].size.q ),
4373:
4374: // to register interface (read)
4375: .qs (configin10_size10_qs)
4376: );
4377:
4378:
4379: // F[pend10]: 30:30
4380: prim_subreg #(
4381: .DW (1),
4382: .SWACCESS("W1C"),
4383: .RESVAL (1'h0)
4384: ) u_configin10_pend10 (
4385: .clk_i (clk_i ),
4386: .rst_ni (rst_ni ),
4387:
4388: // from register interface
4389: .we (configin10_pend10_we),
4390: .wd (configin10_pend10_wd),
4391:
4392: // from internal hardware
4393: .de (hw2reg.configin[10].pend.de),
4394: .d (hw2reg.configin[10].pend.d ),
4395:
4396: // to internal hardware
4397: .qe (),
4398: .q (reg2hw.configin[10].pend.q ),
4399:
4400: // to register interface (read)
4401: .qs (configin10_pend10_qs)
4402: );
4403:
4404:
4405: // F[rdy10]: 31:31
4406: prim_subreg #(
4407: .DW (1),
4408: .SWACCESS("RW"),
4409: .RESVAL (1'h0)
4410: ) u_configin10_rdy10 (
4411: .clk_i (clk_i ),
4412: .rst_ni (rst_ni ),
4413:
4414: // from register interface
4415: .we (configin10_rdy10_we),
4416: .wd (configin10_rdy10_wd),
4417:
4418: // from internal hardware
4419: .de (hw2reg.configin[10].rdy.de),
4420: .d (hw2reg.configin[10].rdy.d ),
4421:
4422: // to internal hardware
4423: .qe (),
4424: .q (reg2hw.configin[10].rdy.q ),
4425:
4426: // to register interface (read)
4427: .qs (configin10_rdy10_qs)
4428: );
4429:
4430:
4431: // Subregister 11 of Multireg configin
4432: // R[configin11]: V(False)
4433:
4434: // F[buffer11]: 4:0
4435: prim_subreg #(
4436: .DW (5),
4437: .SWACCESS("RW"),
4438: .RESVAL (5'h0)
4439: ) u_configin11_buffer11 (
4440: .clk_i (clk_i ),
4441: .rst_ni (rst_ni ),
4442:
4443: // from register interface
4444: .we (configin11_buffer11_we),
4445: .wd (configin11_buffer11_wd),
4446:
4447: // from internal hardware
4448: .de (1'b0),
4449: .d ('0 ),
4450:
4451: // to internal hardware
4452: .qe (),
4453: .q (reg2hw.configin[11].buffer.q ),
4454:
4455: // to register interface (read)
4456: .qs (configin11_buffer11_qs)
4457: );
4458:
4459:
4460: // F[size11]: 14:8
4461: prim_subreg #(
4462: .DW (7),
4463: .SWACCESS("RW"),
4464: .RESVAL (7'h0)
4465: ) u_configin11_size11 (
4466: .clk_i (clk_i ),
4467: .rst_ni (rst_ni ),
4468:
4469: // from register interface
4470: .we (configin11_size11_we),
4471: .wd (configin11_size11_wd),
4472:
4473: // from internal hardware
4474: .de (1'b0),
4475: .d ('0 ),
4476:
4477: // to internal hardware
4478: .qe (),
4479: .q (reg2hw.configin[11].size.q ),
4480:
4481: // to register interface (read)
4482: .qs (configin11_size11_qs)
4483: );
4484:
4485:
4486: // F[pend11]: 30:30
4487: prim_subreg #(
4488: .DW (1),
4489: .SWACCESS("W1C"),
4490: .RESVAL (1'h0)
4491: ) u_configin11_pend11 (
4492: .clk_i (clk_i ),
4493: .rst_ni (rst_ni ),
4494:
4495: // from register interface
4496: .we (configin11_pend11_we),
4497: .wd (configin11_pend11_wd),
4498:
4499: // from internal hardware
4500: .de (hw2reg.configin[11].pend.de),
4501: .d (hw2reg.configin[11].pend.d ),
4502:
4503: // to internal hardware
4504: .qe (),
4505: .q (reg2hw.configin[11].pend.q ),
4506:
4507: // to register interface (read)
4508: .qs (configin11_pend11_qs)
4509: );
4510:
4511:
4512: // F[rdy11]: 31:31
4513: prim_subreg #(
4514: .DW (1),
4515: .SWACCESS("RW"),
4516: .RESVAL (1'h0)
4517: ) u_configin11_rdy11 (
4518: .clk_i (clk_i ),
4519: .rst_ni (rst_ni ),
4520:
4521: // from register interface
4522: .we (configin11_rdy11_we),
4523: .wd (configin11_rdy11_wd),
4524:
4525: // from internal hardware
4526: .de (hw2reg.configin[11].rdy.de),
4527: .d (hw2reg.configin[11].rdy.d ),
4528:
4529: // to internal hardware
4530: .qe (),
4531: .q (reg2hw.configin[11].rdy.q ),
4532:
4533: // to register interface (read)
4534: .qs (configin11_rdy11_qs)
4535: );
4536:
4537:
4538:
4539:
4540: // Subregister 0 of Multireg iso
4541: // R[iso]: V(False)
4542:
4543: // F[iso0]: 0:0
4544: prim_subreg #(
4545: .DW (1),
4546: .SWACCESS("RW"),
4547: .RESVAL (1'h0)
4548: ) u_iso_iso0 (
4549: .clk_i (clk_i ),
4550: .rst_ni (rst_ni ),
4551:
4552: // from register interface
4553: .we (iso_iso0_we),
4554: .wd (iso_iso0_wd),
4555:
4556: // from internal hardware
4557: .de (1'b0),
4558: .d ('0 ),
4559:
4560: // to internal hardware
4561: .qe (),
4562: .q (reg2hw.iso[0].q ),
4563:
4564: // to register interface (read)
4565: .qs (iso_iso0_qs)
4566: );
4567:
4568:
4569: // F[iso1]: 1:1
4570: prim_subreg #(
4571: .DW (1),
4572: .SWACCESS("RW"),
4573: .RESVAL (1'h0)
4574: ) u_iso_iso1 (
4575: .clk_i (clk_i ),
4576: .rst_ni (rst_ni ),
4577:
4578: // from register interface
4579: .we (iso_iso1_we),
4580: .wd (iso_iso1_wd),
4581:
4582: // from internal hardware
4583: .de (1'b0),
4584: .d ('0 ),
4585:
4586: // to internal hardware
4587: .qe (),
4588: .q (reg2hw.iso[1].q ),
4589:
4590: // to register interface (read)
4591: .qs (iso_iso1_qs)
4592: );
4593:
4594:
4595: // F[iso2]: 2:2
4596: prim_subreg #(
4597: .DW (1),
4598: .SWACCESS("RW"),
4599: .RESVAL (1'h0)
4600: ) u_iso_iso2 (
4601: .clk_i (clk_i ),
4602: .rst_ni (rst_ni ),
4603:
4604: // from register interface
4605: .we (iso_iso2_we),
4606: .wd (iso_iso2_wd),
4607:
4608: // from internal hardware
4609: .de (1'b0),
4610: .d ('0 ),
4611:
4612: // to internal hardware
4613: .qe (),
4614: .q (reg2hw.iso[2].q ),
4615:
4616: // to register interface (read)
4617: .qs (iso_iso2_qs)
4618: );
4619:
4620:
4621: // F[iso3]: 3:3
4622: prim_subreg #(
4623: .DW (1),
4624: .SWACCESS("RW"),
4625: .RESVAL (1'h0)
4626: ) u_iso_iso3 (
4627: .clk_i (clk_i ),
4628: .rst_ni (rst_ni ),
4629:
4630: // from register interface
4631: .we (iso_iso3_we),
4632: .wd (iso_iso3_wd),
4633:
4634: // from internal hardware
4635: .de (1'b0),
4636: .d ('0 ),
4637:
4638: // to internal hardware
4639: .qe (),
4640: .q (reg2hw.iso[3].q ),
4641:
4642: // to register interface (read)
4643: .qs (iso_iso3_qs)
4644: );
4645:
4646:
4647: // F[iso4]: 4:4
4648: prim_subreg #(
4649: .DW (1),
4650: .SWACCESS("RW"),
4651: .RESVAL (1'h0)
4652: ) u_iso_iso4 (
4653: .clk_i (clk_i ),
4654: .rst_ni (rst_ni ),
4655:
4656: // from register interface
4657: .we (iso_iso4_we),
4658: .wd (iso_iso4_wd),
4659:
4660: // from internal hardware
4661: .de (1'b0),
4662: .d ('0 ),
4663:
4664: // to internal hardware
4665: .qe (),
4666: .q (reg2hw.iso[4].q ),
4667:
4668: // to register interface (read)
4669: .qs (iso_iso4_qs)
4670: );
4671:
4672:
4673: // F[iso5]: 5:5
4674: prim_subreg #(
4675: .DW (1),
4676: .SWACCESS("RW"),
4677: .RESVAL (1'h0)
4678: ) u_iso_iso5 (
4679: .clk_i (clk_i ),
4680: .rst_ni (rst_ni ),
4681:
4682: // from register interface
4683: .we (iso_iso5_we),
4684: .wd (iso_iso5_wd),
4685:
4686: // from internal hardware
4687: .de (1'b0),
4688: .d ('0 ),
4689:
4690: // to internal hardware
4691: .qe (),
4692: .q (reg2hw.iso[5].q ),
4693:
4694: // to register interface (read)
4695: .qs (iso_iso5_qs)
4696: );
4697:
4698:
4699: // F[iso6]: 6:6
4700: prim_subreg #(
4701: .DW (1),
4702: .SWACCESS("RW"),
4703: .RESVAL (1'h0)
4704: ) u_iso_iso6 (
4705: .clk_i (clk_i ),
4706: .rst_ni (rst_ni ),
4707:
4708: // from register interface
4709: .we (iso_iso6_we),
4710: .wd (iso_iso6_wd),
4711:
4712: // from internal hardware
4713: .de (1'b0),
4714: .d ('0 ),
4715:
4716: // to internal hardware
4717: .qe (),
4718: .q (reg2hw.iso[6].q ),
4719:
4720: // to register interface (read)
4721: .qs (iso_iso6_qs)
4722: );
4723:
4724:
4725: // F[iso7]: 7:7
4726: prim_subreg #(
4727: .DW (1),
4728: .SWACCESS("RW"),
4729: .RESVAL (1'h0)
4730: ) u_iso_iso7 (
4731: .clk_i (clk_i ),
4732: .rst_ni (rst_ni ),
4733:
4734: // from register interface
4735: .we (iso_iso7_we),
4736: .wd (iso_iso7_wd),
4737:
4738: // from internal hardware
4739: .de (1'b0),
4740: .d ('0 ),
4741:
4742: // to internal hardware
4743: .qe (),
4744: .q (reg2hw.iso[7].q ),
4745:
4746: // to register interface (read)
4747: .qs (iso_iso7_qs)
4748: );
4749:
4750:
4751: // F[iso8]: 8:8
4752: prim_subreg #(
4753: .DW (1),
4754: .SWACCESS("RW"),
4755: .RESVAL (1'h0)
4756: ) u_iso_iso8 (
4757: .clk_i (clk_i ),
4758: .rst_ni (rst_ni ),
4759:
4760: // from register interface
4761: .we (iso_iso8_we),
4762: .wd (iso_iso8_wd),
4763:
4764: // from internal hardware
4765: .de (1'b0),
4766: .d ('0 ),
4767:
4768: // to internal hardware
4769: .qe (),
4770: .q (reg2hw.iso[8].q ),
4771:
4772: // to register interface (read)
4773: .qs (iso_iso8_qs)
4774: );
4775:
4776:
4777: // F[iso9]: 9:9
4778: prim_subreg #(
4779: .DW (1),
4780: .SWACCESS("RW"),
4781: .RESVAL (1'h0)
4782: ) u_iso_iso9 (
4783: .clk_i (clk_i ),
4784: .rst_ni (rst_ni ),
4785:
4786: // from register interface
4787: .we (iso_iso9_we),
4788: .wd (iso_iso9_wd),
4789:
4790: // from internal hardware
4791: .de (1'b0),
4792: .d ('0 ),
4793:
4794: // to internal hardware
4795: .qe (),
4796: .q (reg2hw.iso[9].q ),
4797:
4798: // to register interface (read)
4799: .qs (iso_iso9_qs)
4800: );
4801:
4802:
4803: // F[iso10]: 10:10
4804: prim_subreg #(
4805: .DW (1),
4806: .SWACCESS("RW"),
4807: .RESVAL (1'h0)
4808: ) u_iso_iso10 (
4809: .clk_i (clk_i ),
4810: .rst_ni (rst_ni ),
4811:
4812: // from register interface
4813: .we (iso_iso10_we),
4814: .wd (iso_iso10_wd),
4815:
4816: // from internal hardware
4817: .de (1'b0),
4818: .d ('0 ),
4819:
4820: // to internal hardware
4821: .qe (),
4822: .q (reg2hw.iso[10].q ),
4823:
4824: // to register interface (read)
4825: .qs (iso_iso10_qs)
4826: );
4827:
4828:
4829: // F[iso11]: 11:11
4830: prim_subreg #(
4831: .DW (1),
4832: .SWACCESS("RW"),
4833: .RESVAL (1'h0)
4834: ) u_iso_iso11 (
4835: .clk_i (clk_i ),
4836: .rst_ni (rst_ni ),
4837:
4838: // from register interface
4839: .we (iso_iso11_we),
4840: .wd (iso_iso11_wd),
4841:
4842: // from internal hardware
4843: .de (1'b0),
4844: .d ('0 ),
4845:
4846: // to internal hardware
4847: .qe (),
4848: .q (reg2hw.iso[11].q ),
4849:
4850: // to register interface (read)
4851: .qs (iso_iso11_qs)
4852: );
4853:
4854:
4855:
4856:
4857: // Subregister 0 of Multireg data_toggle_clear
4858: // R[data_toggle_clear]: V(False)
4859:
4860: // F[clear0]: 0:0
4861: prim_subreg #(
4862: .DW (1),
4863: .SWACCESS("WO"),
4864: .RESVAL (1'h0)
4865: ) u_data_toggle_clear_clear0 (
4866: .clk_i (clk_i ),
4867: .rst_ni (rst_ni ),
4868:
4869: // from register interface
4870: .we (data_toggle_clear_clear0_we),
4871: .wd (data_toggle_clear_clear0_wd),
4872:
4873: // from internal hardware
4874: .de (1'b0),
4875: .d ('0 ),
4876:
4877: // to internal hardware
4878: .qe (reg2hw.data_toggle_clear[0].qe),
4879: .q (reg2hw.data_toggle_clear[0].q ),
4880:
4881: .qs ()
4882: );
4883:
4884:
4885: // F[clear1]: 1:1
4886: prim_subreg #(
4887: .DW (1),
4888: .SWACCESS("WO"),
4889: .RESVAL (1'h0)
4890: ) u_data_toggle_clear_clear1 (
4891: .clk_i (clk_i ),
4892: .rst_ni (rst_ni ),
4893:
4894: // from register interface
4895: .we (data_toggle_clear_clear1_we),
4896: .wd (data_toggle_clear_clear1_wd),
4897:
4898: // from internal hardware
4899: .de (1'b0),
4900: .d ('0 ),
4901:
4902: // to internal hardware
4903: .qe (reg2hw.data_toggle_clear[1].qe),
4904: .q (reg2hw.data_toggle_clear[1].q ),
4905:
4906: .qs ()
4907: );
4908:
4909:
4910: // F[clear2]: 2:2
4911: prim_subreg #(
4912: .DW (1),
4913: .SWACCESS("WO"),
4914: .RESVAL (1'h0)
4915: ) u_data_toggle_clear_clear2 (
4916: .clk_i (clk_i ),
4917: .rst_ni (rst_ni ),
4918:
4919: // from register interface
4920: .we (data_toggle_clear_clear2_we),
4921: .wd (data_toggle_clear_clear2_wd),
4922:
4923: // from internal hardware
4924: .de (1'b0),
4925: .d ('0 ),
4926:
4927: // to internal hardware
4928: .qe (reg2hw.data_toggle_clear[2].qe),
4929: .q (reg2hw.data_toggle_clear[2].q ),
4930:
4931: .qs ()
4932: );
4933:
4934:
4935: // F[clear3]: 3:3
4936: prim_subreg #(
4937: .DW (1),
4938: .SWACCESS("WO"),
4939: .RESVAL (1'h0)
4940: ) u_data_toggle_clear_clear3 (
4941: .clk_i (clk_i ),
4942: .rst_ni (rst_ni ),
4943:
4944: // from register interface
4945: .we (data_toggle_clear_clear3_we),
4946: .wd (data_toggle_clear_clear3_wd),
4947:
4948: // from internal hardware
4949: .de (1'b0),
4950: .d ('0 ),
4951:
4952: // to internal hardware
4953: .qe (reg2hw.data_toggle_clear[3].qe),
4954: .q (reg2hw.data_toggle_clear[3].q ),
4955:
4956: .qs ()
4957: );
4958:
4959:
4960: // F[clear4]: 4:4
4961: prim_subreg #(
4962: .DW (1),
4963: .SWACCESS("WO"),
4964: .RESVAL (1'h0)
4965: ) u_data_toggle_clear_clear4 (
4966: .clk_i (clk_i ),
4967: .rst_ni (rst_ni ),
4968:
4969: // from register interface
4970: .we (data_toggle_clear_clear4_we),
4971: .wd (data_toggle_clear_clear4_wd),
4972:
4973: // from internal hardware
4974: .de (1'b0),
4975: .d ('0 ),
4976:
4977: // to internal hardware
4978: .qe (reg2hw.data_toggle_clear[4].qe),
4979: .q (reg2hw.data_toggle_clear[4].q ),
4980:
4981: .qs ()
4982: );
4983:
4984:
4985: // F[clear5]: 5:5
4986: prim_subreg #(
4987: .DW (1),
4988: .SWACCESS("WO"),
4989: .RESVAL (1'h0)
4990: ) u_data_toggle_clear_clear5 (
4991: .clk_i (clk_i ),
4992: .rst_ni (rst_ni ),
4993:
4994: // from register interface
4995: .we (data_toggle_clear_clear5_we),
4996: .wd (data_toggle_clear_clear5_wd),
4997:
4998: // from internal hardware
4999: .de (1'b0),
5000: .d ('0 ),
5001:
5002: // to internal hardware
5003: .qe (reg2hw.data_toggle_clear[5].qe),
5004: .q (reg2hw.data_toggle_clear[5].q ),
5005:
5006: .qs ()
5007: );
5008:
5009:
5010: // F[clear6]: 6:6
5011: prim_subreg #(
5012: .DW (1),
5013: .SWACCESS("WO"),
5014: .RESVAL (1'h0)
5015: ) u_data_toggle_clear_clear6 (
5016: .clk_i (clk_i ),
5017: .rst_ni (rst_ni ),
5018:
5019: // from register interface
5020: .we (data_toggle_clear_clear6_we),
5021: .wd (data_toggle_clear_clear6_wd),
5022:
5023: // from internal hardware
5024: .de (1'b0),
5025: .d ('0 ),
5026:
5027: // to internal hardware
5028: .qe (reg2hw.data_toggle_clear[6].qe),
5029: .q (reg2hw.data_toggle_clear[6].q ),
5030:
5031: .qs ()
5032: );
5033:
5034:
5035: // F[clear7]: 7:7
5036: prim_subreg #(
5037: .DW (1),
5038: .SWACCESS("WO"),
5039: .RESVAL (1'h0)
5040: ) u_data_toggle_clear_clear7 (
5041: .clk_i (clk_i ),
5042: .rst_ni (rst_ni ),
5043:
5044: // from register interface
5045: .we (data_toggle_clear_clear7_we),
5046: .wd (data_toggle_clear_clear7_wd),
5047:
5048: // from internal hardware
5049: .de (1'b0),
5050: .d ('0 ),
5051:
5052: // to internal hardware
5053: .qe (reg2hw.data_toggle_clear[7].qe),
5054: .q (reg2hw.data_toggle_clear[7].q ),
5055:
5056: .qs ()
5057: );
5058:
5059:
5060: // F[clear8]: 8:8
5061: prim_subreg #(
5062: .DW (1),
5063: .SWACCESS("WO"),
5064: .RESVAL (1'h0)
5065: ) u_data_toggle_clear_clear8 (
5066: .clk_i (clk_i ),
5067: .rst_ni (rst_ni ),
5068:
5069: // from register interface
5070: .we (data_toggle_clear_clear8_we),
5071: .wd (data_toggle_clear_clear8_wd),
5072:
5073: // from internal hardware
5074: .de (1'b0),
5075: .d ('0 ),
5076:
5077: // to internal hardware
5078: .qe (reg2hw.data_toggle_clear[8].qe),
5079: .q (reg2hw.data_toggle_clear[8].q ),
5080:
5081: .qs ()
5082: );
5083:
5084:
5085: // F[clear9]: 9:9
5086: prim_subreg #(
5087: .DW (1),
5088: .SWACCESS("WO"),
5089: .RESVAL (1'h0)
5090: ) u_data_toggle_clear_clear9 (
5091: .clk_i (clk_i ),
5092: .rst_ni (rst_ni ),
5093:
5094: // from register interface
5095: .we (data_toggle_clear_clear9_we),
5096: .wd (data_toggle_clear_clear9_wd),
5097:
5098: // from internal hardware
5099: .de (1'b0),
5100: .d ('0 ),
5101:
5102: // to internal hardware
5103: .qe (reg2hw.data_toggle_clear[9].qe),
5104: .q (reg2hw.data_toggle_clear[9].q ),
5105:
5106: .qs ()
5107: );
5108:
5109:
5110: // F[clear10]: 10:10
5111: prim_subreg #(
5112: .DW (1),
5113: .SWACCESS("WO"),
5114: .RESVAL (1'h0)
5115: ) u_data_toggle_clear_clear10 (
5116: .clk_i (clk_i ),
5117: .rst_ni (rst_ni ),
5118:
5119: // from register interface
5120: .we (data_toggle_clear_clear10_we),
5121: .wd (data_toggle_clear_clear10_wd),
5122:
5123: // from internal hardware
5124: .de (1'b0),
5125: .d ('0 ),
5126:
5127: // to internal hardware
5128: .qe (reg2hw.data_toggle_clear[10].qe),
5129: .q (reg2hw.data_toggle_clear[10].q ),
5130:
5131: .qs ()
5132: );
5133:
5134:
5135: // F[clear11]: 11:11
5136: prim_subreg #(
5137: .DW (1),
5138: .SWACCESS("WO"),
5139: .RESVAL (1'h0)
5140: ) u_data_toggle_clear_clear11 (
5141: .clk_i (clk_i ),
5142: .rst_ni (rst_ni ),
5143:
5144: // from register interface
5145: .we (data_toggle_clear_clear11_we),
5146: .wd (data_toggle_clear_clear11_wd),
5147:
5148: // from internal hardware
5149: .de (1'b0),
5150: .d ('0 ),
5151:
5152: // to internal hardware
5153: .qe (reg2hw.data_toggle_clear[11].qe),
5154: .q (reg2hw.data_toggle_clear[11].q ),
5155:
5156: .qs ()
5157: );
5158:
5159:
5160:
5161: // R[phy_config]: V(False)
5162:
5163: // F[rx_differential_mode]: 0:0
5164: prim_subreg #(
5165: .DW (1),
5166: .SWACCESS("RW"),
5167: .RESVAL (1'h0)
5168: ) u_phy_config_rx_differential_mode (
5169: .clk_i (clk_i ),
5170: .rst_ni (rst_ni ),
5171:
5172: // from register interface
5173: .we (phy_config_rx_differential_mode_we),
5174: .wd (phy_config_rx_differential_mode_wd),
5175:
5176: // from internal hardware
5177: .de (1'b0),
5178: .d ('0 ),
5179:
5180: // to internal hardware
5181: .qe (),
5182: .q (reg2hw.phy_config.rx_differential_mode.q ),
5183:
5184: // to register interface (read)
5185: .qs (phy_config_rx_differential_mode_qs)
5186: );
5187:
5188:
5189: // F[tx_differential_mode]: 1:1
5190: prim_subreg #(
5191: .DW (1),
5192: .SWACCESS("RW"),
5193: .RESVAL (1'h0)
5194: ) u_phy_config_tx_differential_mode (
5195: .clk_i (clk_i ),
5196: .rst_ni (rst_ni ),
5197:
5198: // from register interface
5199: .we (phy_config_tx_differential_mode_we),
5200: .wd (phy_config_tx_differential_mode_wd),
5201:
5202: // from internal hardware
5203: .de (1'b0),
5204: .d ('0 ),
5205:
5206: // to internal hardware
5207: .qe (),
5208: .q (reg2hw.phy_config.tx_differential_mode.q ),
5209:
5210: // to register interface (read)
5211: .qs (phy_config_tx_differential_mode_qs)
5212: );
5213:
5214:
5215: // F[eop_single_bit]: 2:2
5216: prim_subreg #(
5217: .DW (1),
5218: .SWACCESS("RW"),
5219: .RESVAL (1'h1)
5220: ) u_phy_config_eop_single_bit (
5221: .clk_i (clk_i ),
5222: .rst_ni (rst_ni ),
5223:
5224: // from register interface
5225: .we (phy_config_eop_single_bit_we),
5226: .wd (phy_config_eop_single_bit_wd),
5227:
5228: // from internal hardware
5229: .de (1'b0),
5230: .d ('0 ),
5231:
5232: // to internal hardware
5233: .qe (),
5234: .q (reg2hw.phy_config.eop_single_bit.q ),
5235:
5236: // to register interface (read)
5237: .qs (phy_config_eop_single_bit_qs)
5238: );
5239:
5240:
5241: // F[override_pwr_sense_en]: 3:3
5242: prim_subreg #(
5243: .DW (1),
5244: .SWACCESS("RW"),
5245: .RESVAL (1'h0)
5246: ) u_phy_config_override_pwr_sense_en (
5247: .clk_i (clk_i ),
5248: .rst_ni (rst_ni ),
5249:
5250: // from register interface
5251: .we (phy_config_override_pwr_sense_en_we),
5252: .wd (phy_config_override_pwr_sense_en_wd),
5253:
5254: // from internal hardware
5255: .de (1'b0),
5256: .d ('0 ),
5257:
5258: // to internal hardware
5259: .qe (),
5260: .q (reg2hw.phy_config.override_pwr_sense_en.q ),
5261:
5262: // to register interface (read)
5263: .qs (phy_config_override_pwr_sense_en_qs)
5264: );
5265:
5266:
5267: // F[override_pwr_sense_val]: 4:4
5268: prim_subreg #(
5269: .DW (1),
5270: .SWACCESS("RW"),
5271: .RESVAL (1'h0)
5272: ) u_phy_config_override_pwr_sense_val (
5273: .clk_i (clk_i ),
5274: .rst_ni (rst_ni ),
5275:
5276: // from register interface
5277: .we (phy_config_override_pwr_sense_val_we),
5278: .wd (phy_config_override_pwr_sense_val_wd),
5279:
5280: // from internal hardware
5281: .de (1'b0),
5282: .d ('0 ),
5283:
5284: // to internal hardware
5285: .qe (),
5286: .q (reg2hw.phy_config.override_pwr_sense_val.q ),
5287:
5288: // to register interface (read)
5289: .qs (phy_config_override_pwr_sense_val_qs)
5290: );
5291:
5292:
5293:
5294:
5295: logic [25:0] addr_hit;
5296: always_comb begin
5297: addr_hit = '0;
5298: addr_hit[ 0] = (reg_addr == USBDEV_INTR_STATE_OFFSET);
5299: addr_hit[ 1] = (reg_addr == USBDEV_INTR_ENABLE_OFFSET);
5300: addr_hit[ 2] = (reg_addr == USBDEV_INTR_TEST_OFFSET);
5301: addr_hit[ 3] = (reg_addr == USBDEV_USBCTRL_OFFSET);
5302: addr_hit[ 4] = (reg_addr == USBDEV_USBSTAT_OFFSET);
5303: addr_hit[ 5] = (reg_addr == USBDEV_AVBUFFER_OFFSET);
5304: addr_hit[ 6] = (reg_addr == USBDEV_RXFIFO_OFFSET);
5305: addr_hit[ 7] = (reg_addr == USBDEV_RXENABLE_SETUP_OFFSET);
5306: addr_hit[ 8] = (reg_addr == USBDEV_RXENABLE_OUT_OFFSET);
5307: addr_hit[ 9] = (reg_addr == USBDEV_IN_SENT_OFFSET);
5308: addr_hit[10] = (reg_addr == USBDEV_STALL_OFFSET);
5309: addr_hit[11] = (reg_addr == USBDEV_CONFIGIN0_OFFSET);
5310: addr_hit[12] = (reg_addr == USBDEV_CONFIGIN1_OFFSET);
5311: addr_hit[13] = (reg_addr == USBDEV_CONFIGIN2_OFFSET);
5312: addr_hit[14] = (reg_addr == USBDEV_CONFIGIN3_OFFSET);
5313: addr_hit[15] = (reg_addr == USBDEV_CONFIGIN4_OFFSET);
5314: addr_hit[16] = (reg_addr == USBDEV_CONFIGIN5_OFFSET);
5315: addr_hit[17] = (reg_addr == USBDEV_CONFIGIN6_OFFSET);
5316: addr_hit[18] = (reg_addr == USBDEV_CONFIGIN7_OFFSET);
5317: addr_hit[19] = (reg_addr == USBDEV_CONFIGIN8_OFFSET);
5318: addr_hit[20] = (reg_addr == USBDEV_CONFIGIN9_OFFSET);
5319: addr_hit[21] = (reg_addr == USBDEV_CONFIGIN10_OFFSET);
5320: addr_hit[22] = (reg_addr == USBDEV_CONFIGIN11_OFFSET);
5321: addr_hit[23] = (reg_addr == USBDEV_ISO_OFFSET);
5322: addr_hit[24] = (reg_addr == USBDEV_DATA_TOGGLE_CLEAR_OFFSET);
5323: addr_hit[25] = (reg_addr == USBDEV_PHY_CONFIG_OFFSET);
5324: end
5325:
5326: assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
5327:
5328: // Check sub-word write is permitted
5329: always_comb begin
5330: wr_err = 1'b0;
5331: if (addr_hit[ 0] && reg_we && (USBDEV_PERMIT[ 0] != (USBDEV_PERMIT[ 0] & reg_be))) wr_err = 1'b1 ;
5332: if (addr_hit[ 1] && reg_we && (USBDEV_PERMIT[ 1] != (USBDEV_PERMIT[ 1] & reg_be))) wr_err = 1'b1 ;
5333: if (addr_hit[ 2] && reg_we && (USBDEV_PERMIT[ 2] != (USBDEV_PERMIT[ 2] & reg_be))) wr_err = 1'b1 ;
5334: if (addr_hit[ 3] && reg_we && (USBDEV_PERMIT[ 3] != (USBDEV_PERMIT[ 3] & reg_be))) wr_err = 1'b1 ;
5335: if (addr_hit[ 4] && reg_we && (USBDEV_PERMIT[ 4] != (USBDEV_PERMIT[ 4] & reg_be))) wr_err = 1'b1 ;
5336: if (addr_hit[ 5] && reg_we && (USBDEV_PERMIT[ 5] != (USBDEV_PERMIT[ 5] & reg_be))) wr_err = 1'b1 ;
5337: if (addr_hit[ 6] && reg_we && (USBDEV_PERMIT[ 6] != (USBDEV_PERMIT[ 6] & reg_be))) wr_err = 1'b1 ;
5338: if (addr_hit[ 7] && reg_we && (USBDEV_PERMIT[ 7] != (USBDEV_PERMIT[ 7] & reg_be))) wr_err = 1'b1 ;
5339: if (addr_hit[ 8] && reg_we && (USBDEV_PERMIT[ 8] != (USBDEV_PERMIT[ 8] & reg_be))) wr_err = 1'b1 ;
5340: if (addr_hit[ 9] && reg_we && (USBDEV_PERMIT[ 9] != (USBDEV_PERMIT[ 9] & reg_be))) wr_err = 1'b1 ;
5341: if (addr_hit[10] && reg_we && (USBDEV_PERMIT[10] != (USBDEV_PERMIT[10] & reg_be))) wr_err = 1'b1 ;
5342: if (addr_hit[11] && reg_we && (USBDEV_PERMIT[11] != (USBDEV_PERMIT[11] & reg_be))) wr_err = 1'b1 ;
5343: if (addr_hit[12] && reg_we && (USBDEV_PERMIT[12] != (USBDEV_PERMIT[12] & reg_be))) wr_err = 1'b1 ;
5344: if (addr_hit[13] && reg_we && (USBDEV_PERMIT[13] != (USBDEV_PERMIT[13] & reg_be))) wr_err = 1'b1 ;
5345: if (addr_hit[14] && reg_we && (USBDEV_PERMIT[14] != (USBDEV_PERMIT[14] & reg_be))) wr_err = 1'b1 ;
5346: if (addr_hit[15] && reg_we && (USBDEV_PERMIT[15] != (USBDEV_PERMIT[15] & reg_be))) wr_err = 1'b1 ;
5347: if (addr_hit[16] && reg_we && (USBDEV_PERMIT[16] != (USBDEV_PERMIT[16] & reg_be))) wr_err = 1'b1 ;
5348: if (addr_hit[17] && reg_we && (USBDEV_PERMIT[17] != (USBDEV_PERMIT[17] & reg_be))) wr_err = 1'b1 ;
5349: if (addr_hit[18] && reg_we && (USBDEV_PERMIT[18] != (USBDEV_PERMIT[18] & reg_be))) wr_err = 1'b1 ;
5350: if (addr_hit[19] && reg_we && (USBDEV_PERMIT[19] != (USBDEV_PERMIT[19] & reg_be))) wr_err = 1'b1 ;
5351: if (addr_hit[20] && reg_we && (USBDEV_PERMIT[20] != (USBDEV_PERMIT[20] & reg_be))) wr_err = 1'b1 ;
5352: if (addr_hit[21] && reg_we && (USBDEV_PERMIT[21] != (USBDEV_PERMIT[21] & reg_be))) wr_err = 1'b1 ;
5353: if (addr_hit[22] && reg_we && (USBDEV_PERMIT[22] != (USBDEV_PERMIT[22] & reg_be))) wr_err = 1'b1 ;
5354: if (addr_hit[23] && reg_we && (USBDEV_PERMIT[23] != (USBDEV_PERMIT[23] & reg_be))) wr_err = 1'b1 ;
5355: if (addr_hit[24] && reg_we && (USBDEV_PERMIT[24] != (USBDEV_PERMIT[24] & reg_be))) wr_err = 1'b1 ;
5356: if (addr_hit[25] && reg_we && (USBDEV_PERMIT[25] != (USBDEV_PERMIT[25] & reg_be))) wr_err = 1'b1 ;
5357: end
5358:
5359: assign intr_state_pkt_received_we = addr_hit[0] & reg_we & ~wr_err;
5360: assign intr_state_pkt_received_wd = reg_wdata[0];
5361:
5362: assign intr_state_pkt_sent_we = addr_hit[0] & reg_we & ~wr_err;
5363: assign intr_state_pkt_sent_wd = reg_wdata[1];
5364:
5365: assign intr_state_disconnected_we = addr_hit[0] & reg_we & ~wr_err;
5366: assign intr_state_disconnected_wd = reg_wdata[2];
5367:
5368: assign intr_state_host_lost_we = addr_hit[0] & reg_we & ~wr_err;
5369: assign intr_state_host_lost_wd = reg_wdata[3];
5370:
5371: assign intr_state_link_reset_we = addr_hit[0] & reg_we & ~wr_err;
5372: assign intr_state_link_reset_wd = reg_wdata[4];
5373:
5374: assign intr_state_link_suspend_we = addr_hit[0] & reg_we & ~wr_err;
5375: assign intr_state_link_suspend_wd = reg_wdata[5];
5376:
5377: assign intr_state_link_resume_we = addr_hit[0] & reg_we & ~wr_err;
5378: assign intr_state_link_resume_wd = reg_wdata[6];
5379:
5380: assign intr_state_av_empty_we = addr_hit[0] & reg_we & ~wr_err;
5381: assign intr_state_av_empty_wd = reg_wdata[7];
5382:
5383: assign intr_state_rx_full_we = addr_hit[0] & reg_we & ~wr_err;
5384: assign intr_state_rx_full_wd = reg_wdata[8];
5385:
5386: assign intr_state_av_overflow_we = addr_hit[0] & reg_we & ~wr_err;
5387: assign intr_state_av_overflow_wd = reg_wdata[9];
5388:
5389: assign intr_state_link_in_err_we = addr_hit[0] & reg_we & ~wr_err;
5390: assign intr_state_link_in_err_wd = reg_wdata[10];
5391:
5392: assign intr_state_rx_crc_err_we = addr_hit[0] & reg_we & ~wr_err;
5393: assign intr_state_rx_crc_err_wd = reg_wdata[11];
5394:
5395: assign intr_state_rx_pid_err_we = addr_hit[0] & reg_we & ~wr_err;
5396: assign intr_state_rx_pid_err_wd = reg_wdata[12];
5397:
5398: assign intr_state_rx_bitstuff_err_we = addr_hit[0] & reg_we & ~wr_err;
5399: assign intr_state_rx_bitstuff_err_wd = reg_wdata[13];
5400:
5401: assign intr_state_frame_we = addr_hit[0] & reg_we & ~wr_err;
5402: assign intr_state_frame_wd = reg_wdata[14];
5403:
5404: assign intr_state_connected_we = addr_hit[0] & reg_we & ~wr_err;
5405: assign intr_state_connected_wd = reg_wdata[15];
5406:
5407: assign intr_enable_pkt_received_we = addr_hit[1] & reg_we & ~wr_err;
5408: assign intr_enable_pkt_received_wd = reg_wdata[0];
5409:
5410: assign intr_enable_pkt_sent_we = addr_hit[1] & reg_we & ~wr_err;
5411: assign intr_enable_pkt_sent_wd = reg_wdata[1];
5412:
5413: assign intr_enable_disconnected_we = addr_hit[1] & reg_we & ~wr_err;
5414: assign intr_enable_disconnected_wd = reg_wdata[2];
5415:
5416: assign intr_enable_host_lost_we = addr_hit[1] & reg_we & ~wr_err;
5417: assign intr_enable_host_lost_wd = reg_wdata[3];
5418:
5419: assign intr_enable_link_reset_we = addr_hit[1] & reg_we & ~wr_err;
5420: assign intr_enable_link_reset_wd = reg_wdata[4];
5421:
5422: assign intr_enable_link_suspend_we = addr_hit[1] & reg_we & ~wr_err;
5423: assign intr_enable_link_suspend_wd = reg_wdata[5];
5424:
5425: assign intr_enable_link_resume_we = addr_hit[1] & reg_we & ~wr_err;
5426: assign intr_enable_link_resume_wd = reg_wdata[6];
5427:
5428: assign intr_enable_av_empty_we = addr_hit[1] & reg_we & ~wr_err;
5429: assign intr_enable_av_empty_wd = reg_wdata[7];
5430:
5431: assign intr_enable_rx_full_we = addr_hit[1] & reg_we & ~wr_err;
5432: assign intr_enable_rx_full_wd = reg_wdata[8];
5433:
5434: assign intr_enable_av_overflow_we = addr_hit[1] & reg_we & ~wr_err;
5435: assign intr_enable_av_overflow_wd = reg_wdata[9];
5436:
5437: assign intr_enable_link_in_err_we = addr_hit[1] & reg_we & ~wr_err;
5438: assign intr_enable_link_in_err_wd = reg_wdata[10];
5439:
5440: assign intr_enable_rx_crc_err_we = addr_hit[1] & reg_we & ~wr_err;
5441: assign intr_enable_rx_crc_err_wd = reg_wdata[11];
5442:
5443: assign intr_enable_rx_pid_err_we = addr_hit[1] & reg_we & ~wr_err;
5444: assign intr_enable_rx_pid_err_wd = reg_wdata[12];
5445:
5446: assign intr_enable_rx_bitstuff_err_we = addr_hit[1] & reg_we & ~wr_err;
5447: assign intr_enable_rx_bitstuff_err_wd = reg_wdata[13];
5448:
5449: assign intr_enable_frame_we = addr_hit[1] & reg_we & ~wr_err;
5450: assign intr_enable_frame_wd = reg_wdata[14];
5451:
5452: assign intr_enable_connected_we = addr_hit[1] & reg_we & ~wr_err;
5453: assign intr_enable_connected_wd = reg_wdata[15];
5454:
5455: assign intr_test_pkt_received_we = addr_hit[2] & reg_we & ~wr_err;
5456: assign intr_test_pkt_received_wd = reg_wdata[0];
5457:
5458: assign intr_test_pkt_sent_we = addr_hit[2] & reg_we & ~wr_err;
5459: assign intr_test_pkt_sent_wd = reg_wdata[1];
5460:
5461: assign intr_test_disconnected_we = addr_hit[2] & reg_we & ~wr_err;
5462: assign intr_test_disconnected_wd = reg_wdata[2];
5463:
5464: assign intr_test_host_lost_we = addr_hit[2] & reg_we & ~wr_err;
5465: assign intr_test_host_lost_wd = reg_wdata[3];
5466:
5467: assign intr_test_link_reset_we = addr_hit[2] & reg_we & ~wr_err;
5468: assign intr_test_link_reset_wd = reg_wdata[4];
5469:
5470: assign intr_test_link_suspend_we = addr_hit[2] & reg_we & ~wr_err;
5471: assign intr_test_link_suspend_wd = reg_wdata[5];
5472:
5473: assign intr_test_link_resume_we = addr_hit[2] & reg_we & ~wr_err;
5474: assign intr_test_link_resume_wd = reg_wdata[6];
5475:
5476: assign intr_test_av_empty_we = addr_hit[2] & reg_we & ~wr_err;
5477: assign intr_test_av_empty_wd = reg_wdata[7];
5478:
5479: assign intr_test_rx_full_we = addr_hit[2] & reg_we & ~wr_err;
5480: assign intr_test_rx_full_wd = reg_wdata[8];
5481:
5482: assign intr_test_av_overflow_we = addr_hit[2] & reg_we & ~wr_err;
5483: assign intr_test_av_overflow_wd = reg_wdata[9];
5484:
5485: assign intr_test_link_in_err_we = addr_hit[2] & reg_we & ~wr_err;
5486: assign intr_test_link_in_err_wd = reg_wdata[10];
5487:
5488: assign intr_test_rx_crc_err_we = addr_hit[2] & reg_we & ~wr_err;
5489: assign intr_test_rx_crc_err_wd = reg_wdata[11];
5490:
5491: assign intr_test_rx_pid_err_we = addr_hit[2] & reg_we & ~wr_err;
5492: assign intr_test_rx_pid_err_wd = reg_wdata[12];
5493:
5494: assign intr_test_rx_bitstuff_err_we = addr_hit[2] & reg_we & ~wr_err;
5495: assign intr_test_rx_bitstuff_err_wd = reg_wdata[13];
5496:
5497: assign intr_test_frame_we = addr_hit[2] & reg_we & ~wr_err;
5498: assign intr_test_frame_wd = reg_wdata[14];
5499:
5500: assign intr_test_connected_we = addr_hit[2] & reg_we & ~wr_err;
5501: assign intr_test_connected_wd = reg_wdata[15];
5502:
5503: assign usbctrl_enable_we = addr_hit[3] & reg_we & ~wr_err;
5504: assign usbctrl_enable_wd = reg_wdata[0];
5505:
5506: assign usbctrl_device_address_we = addr_hit[3] & reg_we & ~wr_err;
5507: assign usbctrl_device_address_wd = reg_wdata[22:16];
5508:
5509: assign usbstat_frame_re = addr_hit[4] && reg_re;
5510:
5511: assign usbstat_host_lost_re = addr_hit[4] && reg_re;
5512:
5513: assign usbstat_link_state_re = addr_hit[4] && reg_re;
5514:
5515: assign usbstat_usb_sense_re = addr_hit[4] && reg_re;
5516:
5517: assign usbstat_av_depth_re = addr_hit[4] && reg_re;
5518:
5519: assign usbstat_av_full_re = addr_hit[4] && reg_re;
5520:
5521: assign usbstat_rx_depth_re = addr_hit[4] && reg_re;
5522:
5523: assign usbstat_rx_empty_re = addr_hit[4] && reg_re;
5524:
5525: assign avbuffer_we = addr_hit[5] & reg_we & ~wr_err;
5526: assign avbuffer_wd = reg_wdata[4:0];
5527:
5528: assign rxfifo_buffer_re = addr_hit[6] && reg_re;
5529:
5530: assign rxfifo_size_re = addr_hit[6] && reg_re;
5531:
5532: assign rxfifo_setup_re = addr_hit[6] && reg_re;
5533:
5534: assign rxfifo_ep_re = addr_hit[6] && reg_re;
5535:
5536: assign rxenable_setup_setup0_we = addr_hit[7] & reg_we & ~wr_err;
5537: assign rxenable_setup_setup0_wd = reg_wdata[0];
5538:
5539: assign rxenable_setup_setup1_we = addr_hit[7] & reg_we & ~wr_err;
5540: assign rxenable_setup_setup1_wd = reg_wdata[1];
5541:
5542: assign rxenable_setup_setup2_we = addr_hit[7] & reg_we & ~wr_err;
5543: assign rxenable_setup_setup2_wd = reg_wdata[2];
5544:
5545: assign rxenable_setup_setup3_we = addr_hit[7] & reg_we & ~wr_err;
5546: assign rxenable_setup_setup3_wd = reg_wdata[3];
5547:
5548: assign rxenable_setup_setup4_we = addr_hit[7] & reg_we & ~wr_err;
5549: assign rxenable_setup_setup4_wd = reg_wdata[4];
5550:
5551: assign rxenable_setup_setup5_we = addr_hit[7] & reg_we & ~wr_err;
5552: assign rxenable_setup_setup5_wd = reg_wdata[5];
5553:
5554: assign rxenable_setup_setup6_we = addr_hit[7] & reg_we & ~wr_err;
5555: assign rxenable_setup_setup6_wd = reg_wdata[6];
5556:
5557: assign rxenable_setup_setup7_we = addr_hit[7] & reg_we & ~wr_err;
5558: assign rxenable_setup_setup7_wd = reg_wdata[7];
5559:
5560: assign rxenable_setup_setup8_we = addr_hit[7] & reg_we & ~wr_err;
5561: assign rxenable_setup_setup8_wd = reg_wdata[8];
5562:
5563: assign rxenable_setup_setup9_we = addr_hit[7] & reg_we & ~wr_err;
5564: assign rxenable_setup_setup9_wd = reg_wdata[9];
5565:
5566: assign rxenable_setup_setup10_we = addr_hit[7] & reg_we & ~wr_err;
5567: assign rxenable_setup_setup10_wd = reg_wdata[10];
5568:
5569: assign rxenable_setup_setup11_we = addr_hit[7] & reg_we & ~wr_err;
5570: assign rxenable_setup_setup11_wd = reg_wdata[11];
5571:
5572: assign rxenable_out_out0_we = addr_hit[8] & reg_we & ~wr_err;
5573: assign rxenable_out_out0_wd = reg_wdata[0];
5574:
5575: assign rxenable_out_out1_we = addr_hit[8] & reg_we & ~wr_err;
5576: assign rxenable_out_out1_wd = reg_wdata[1];
5577:
5578: assign rxenable_out_out2_we = addr_hit[8] & reg_we & ~wr_err;
5579: assign rxenable_out_out2_wd = reg_wdata[2];
5580:
5581: assign rxenable_out_out3_we = addr_hit[8] & reg_we & ~wr_err;
5582: assign rxenable_out_out3_wd = reg_wdata[3];
5583:
5584: assign rxenable_out_out4_we = addr_hit[8] & reg_we & ~wr_err;
5585: assign rxenable_out_out4_wd = reg_wdata[4];
5586:
5587: assign rxenable_out_out5_we = addr_hit[8] & reg_we & ~wr_err;
5588: assign rxenable_out_out5_wd = reg_wdata[5];
5589:
5590: assign rxenable_out_out6_we = addr_hit[8] & reg_we & ~wr_err;
5591: assign rxenable_out_out6_wd = reg_wdata[6];
5592:
5593: assign rxenable_out_out7_we = addr_hit[8] & reg_we & ~wr_err;
5594: assign rxenable_out_out7_wd = reg_wdata[7];
5595:
5596: assign rxenable_out_out8_we = addr_hit[8] & reg_we & ~wr_err;
5597: assign rxenable_out_out8_wd = reg_wdata[8];
5598:
5599: assign rxenable_out_out9_we = addr_hit[8] & reg_we & ~wr_err;
5600: assign rxenable_out_out9_wd = reg_wdata[9];
5601:
5602: assign rxenable_out_out10_we = addr_hit[8] & reg_we & ~wr_err;
5603: assign rxenable_out_out10_wd = reg_wdata[10];
5604:
5605: assign rxenable_out_out11_we = addr_hit[8] & reg_we & ~wr_err;
5606: assign rxenable_out_out11_wd = reg_wdata[11];
5607:
5608: assign in_sent_sent0_we = addr_hit[9] & reg_we & ~wr_err;
5609: assign in_sent_sent0_wd = reg_wdata[0];
5610:
5611: assign in_sent_sent1_we = addr_hit[9] & reg_we & ~wr_err;
5612: assign in_sent_sent1_wd = reg_wdata[1];
5613:
5614: assign in_sent_sent2_we = addr_hit[9] & reg_we & ~wr_err;
5615: assign in_sent_sent2_wd = reg_wdata[2];
5616:
5617: assign in_sent_sent3_we = addr_hit[9] & reg_we & ~wr_err;
5618: assign in_sent_sent3_wd = reg_wdata[3];
5619:
5620: assign in_sent_sent4_we = addr_hit[9] & reg_we & ~wr_err;
5621: assign in_sent_sent4_wd = reg_wdata[4];
5622:
5623: assign in_sent_sent5_we = addr_hit[9] & reg_we & ~wr_err;
5624: assign in_sent_sent5_wd = reg_wdata[5];
5625:
5626: assign in_sent_sent6_we = addr_hit[9] & reg_we & ~wr_err;
5627: assign in_sent_sent6_wd = reg_wdata[6];
5628:
5629: assign in_sent_sent7_we = addr_hit[9] & reg_we & ~wr_err;
5630: assign in_sent_sent7_wd = reg_wdata[7];
5631:
5632: assign in_sent_sent8_we = addr_hit[9] & reg_we & ~wr_err;
5633: assign in_sent_sent8_wd = reg_wdata[8];
5634:
5635: assign in_sent_sent9_we = addr_hit[9] & reg_we & ~wr_err;
5636: assign in_sent_sent9_wd = reg_wdata[9];
5637:
5638: assign in_sent_sent10_we = addr_hit[9] & reg_we & ~wr_err;
5639: assign in_sent_sent10_wd = reg_wdata[10];
5640:
5641: assign in_sent_sent11_we = addr_hit[9] & reg_we & ~wr_err;
5642: assign in_sent_sent11_wd = reg_wdata[11];
5643:
5644: assign stall_stall0_we = addr_hit[10] & reg_we & ~wr_err;
5645: assign stall_stall0_wd = reg_wdata[0];
5646:
5647: assign stall_stall1_we = addr_hit[10] & reg_we & ~wr_err;
5648: assign stall_stall1_wd = reg_wdata[1];
5649:
5650: assign stall_stall2_we = addr_hit[10] & reg_we & ~wr_err;
5651: assign stall_stall2_wd = reg_wdata[2];
5652:
5653: assign stall_stall3_we = addr_hit[10] & reg_we & ~wr_err;
5654: assign stall_stall3_wd = reg_wdata[3];
5655:
5656: assign stall_stall4_we = addr_hit[10] & reg_we & ~wr_err;
5657: assign stall_stall4_wd = reg_wdata[4];
5658:
5659: assign stall_stall5_we = addr_hit[10] & reg_we & ~wr_err;
5660: assign stall_stall5_wd = reg_wdata[5];
5661:
5662: assign stall_stall6_we = addr_hit[10] & reg_we & ~wr_err;
5663: assign stall_stall6_wd = reg_wdata[6];
5664:
5665: assign stall_stall7_we = addr_hit[10] & reg_we & ~wr_err;
5666: assign stall_stall7_wd = reg_wdata[7];
5667:
5668: assign stall_stall8_we = addr_hit[10] & reg_we & ~wr_err;
5669: assign stall_stall8_wd = reg_wdata[8];
5670:
5671: assign stall_stall9_we = addr_hit[10] & reg_we & ~wr_err;
5672: assign stall_stall9_wd = reg_wdata[9];
5673:
5674: assign stall_stall10_we = addr_hit[10] & reg_we & ~wr_err;
5675: assign stall_stall10_wd = reg_wdata[10];
5676:
5677: assign stall_stall11_we = addr_hit[10] & reg_we & ~wr_err;
5678: assign stall_stall11_wd = reg_wdata[11];
5679:
5680: assign configin0_buffer0_we = addr_hit[11] & reg_we & ~wr_err;
5681: assign configin0_buffer0_wd = reg_wdata[4:0];
5682:
5683: assign configin0_size0_we = addr_hit[11] & reg_we & ~wr_err;
5684: assign configin0_size0_wd = reg_wdata[14:8];
5685:
5686: assign configin0_pend0_we = addr_hit[11] & reg_we & ~wr_err;
5687: assign configin0_pend0_wd = reg_wdata[30];
5688:
5689: assign configin0_rdy0_we = addr_hit[11] & reg_we & ~wr_err;
5690: assign configin0_rdy0_wd = reg_wdata[31];
5691:
5692: assign configin1_buffer1_we = addr_hit[12] & reg_we & ~wr_err;
5693: assign configin1_buffer1_wd = reg_wdata[4:0];
5694:
5695: assign configin1_size1_we = addr_hit[12] & reg_we & ~wr_err;
5696: assign configin1_size1_wd = reg_wdata[14:8];
5697:
5698: assign configin1_pend1_we = addr_hit[12] & reg_we & ~wr_err;
5699: assign configin1_pend1_wd = reg_wdata[30];
5700:
5701: assign configin1_rdy1_we = addr_hit[12] & reg_we & ~wr_err;
5702: assign configin1_rdy1_wd = reg_wdata[31];
5703:
5704: assign configin2_buffer2_we = addr_hit[13] & reg_we & ~wr_err;
5705: assign configin2_buffer2_wd = reg_wdata[4:0];
5706:
5707: assign configin2_size2_we = addr_hit[13] & reg_we & ~wr_err;
5708: assign configin2_size2_wd = reg_wdata[14:8];
5709:
5710: assign configin2_pend2_we = addr_hit[13] & reg_we & ~wr_err;
5711: assign configin2_pend2_wd = reg_wdata[30];
5712:
5713: assign configin2_rdy2_we = addr_hit[13] & reg_we & ~wr_err;
5714: assign configin2_rdy2_wd = reg_wdata[31];
5715:
5716: assign configin3_buffer3_we = addr_hit[14] & reg_we & ~wr_err;
5717: assign configin3_buffer3_wd = reg_wdata[4:0];
5718:
5719: assign configin3_size3_we = addr_hit[14] & reg_we & ~wr_err;
5720: assign configin3_size3_wd = reg_wdata[14:8];
5721:
5722: assign configin3_pend3_we = addr_hit[14] & reg_we & ~wr_err;
5723: assign configin3_pend3_wd = reg_wdata[30];
5724:
5725: assign configin3_rdy3_we = addr_hit[14] & reg_we & ~wr_err;
5726: assign configin3_rdy3_wd = reg_wdata[31];
5727:
5728: assign configin4_buffer4_we = addr_hit[15] & reg_we & ~wr_err;
5729: assign configin4_buffer4_wd = reg_wdata[4:0];
5730:
5731: assign configin4_size4_we = addr_hit[15] & reg_we & ~wr_err;
5732: assign configin4_size4_wd = reg_wdata[14:8];
5733:
5734: assign configin4_pend4_we = addr_hit[15] & reg_we & ~wr_err;
5735: assign configin4_pend4_wd = reg_wdata[30];
5736:
5737: assign configin4_rdy4_we = addr_hit[15] & reg_we & ~wr_err;
5738: assign configin4_rdy4_wd = reg_wdata[31];
5739:
5740: assign configin5_buffer5_we = addr_hit[16] & reg_we & ~wr_err;
5741: assign configin5_buffer5_wd = reg_wdata[4:0];
5742:
5743: assign configin5_size5_we = addr_hit[16] & reg_we & ~wr_err;
5744: assign configin5_size5_wd = reg_wdata[14:8];
5745:
5746: assign configin5_pend5_we = addr_hit[16] & reg_we & ~wr_err;
5747: assign configin5_pend5_wd = reg_wdata[30];
5748:
5749: assign configin5_rdy5_we = addr_hit[16] & reg_we & ~wr_err;
5750: assign configin5_rdy5_wd = reg_wdata[31];
5751:
5752: assign configin6_buffer6_we = addr_hit[17] & reg_we & ~wr_err;
5753: assign configin6_buffer6_wd = reg_wdata[4:0];
5754:
5755: assign configin6_size6_we = addr_hit[17] & reg_we & ~wr_err;
5756: assign configin6_size6_wd = reg_wdata[14:8];
5757:
5758: assign configin6_pend6_we = addr_hit[17] & reg_we & ~wr_err;
5759: assign configin6_pend6_wd = reg_wdata[30];
5760:
5761: assign configin6_rdy6_we = addr_hit[17] & reg_we & ~wr_err;
5762: assign configin6_rdy6_wd = reg_wdata[31];
5763:
5764: assign configin7_buffer7_we = addr_hit[18] & reg_we & ~wr_err;
5765: assign configin7_buffer7_wd = reg_wdata[4:0];
5766:
5767: assign configin7_size7_we = addr_hit[18] & reg_we & ~wr_err;
5768: assign configin7_size7_wd = reg_wdata[14:8];
5769:
5770: assign configin7_pend7_we = addr_hit[18] & reg_we & ~wr_err;
5771: assign configin7_pend7_wd = reg_wdata[30];
5772:
5773: assign configin7_rdy7_we = addr_hit[18] & reg_we & ~wr_err;
5774: assign configin7_rdy7_wd = reg_wdata[31];
5775:
5776: assign configin8_buffer8_we = addr_hit[19] & reg_we & ~wr_err;
5777: assign configin8_buffer8_wd = reg_wdata[4:0];
5778:
5779: assign configin8_size8_we = addr_hit[19] & reg_we & ~wr_err;
5780: assign configin8_size8_wd = reg_wdata[14:8];
5781:
5782: assign configin8_pend8_we = addr_hit[19] & reg_we & ~wr_err;
5783: assign configin8_pend8_wd = reg_wdata[30];
5784:
5785: assign configin8_rdy8_we = addr_hit[19] & reg_we & ~wr_err;
5786: assign configin8_rdy8_wd = reg_wdata[31];
5787:
5788: assign configin9_buffer9_we = addr_hit[20] & reg_we & ~wr_err;
5789: assign configin9_buffer9_wd = reg_wdata[4:0];
5790:
5791: assign configin9_size9_we = addr_hit[20] & reg_we & ~wr_err;
5792: assign configin9_size9_wd = reg_wdata[14:8];
5793:
5794: assign configin9_pend9_we = addr_hit[20] & reg_we & ~wr_err;
5795: assign configin9_pend9_wd = reg_wdata[30];
5796:
5797: assign configin9_rdy9_we = addr_hit[20] & reg_we & ~wr_err;
5798: assign configin9_rdy9_wd = reg_wdata[31];
5799:
5800: assign configin10_buffer10_we = addr_hit[21] & reg_we & ~wr_err;
5801: assign configin10_buffer10_wd = reg_wdata[4:0];
5802:
5803: assign configin10_size10_we = addr_hit[21] & reg_we & ~wr_err;
5804: assign configin10_size10_wd = reg_wdata[14:8];
5805:
5806: assign configin10_pend10_we = addr_hit[21] & reg_we & ~wr_err;
5807: assign configin10_pend10_wd = reg_wdata[30];
5808:
5809: assign configin10_rdy10_we = addr_hit[21] & reg_we & ~wr_err;
5810: assign configin10_rdy10_wd = reg_wdata[31];
5811:
5812: assign configin11_buffer11_we = addr_hit[22] & reg_we & ~wr_err;
5813: assign configin11_buffer11_wd = reg_wdata[4:0];
5814:
5815: assign configin11_size11_we = addr_hit[22] & reg_we & ~wr_err;
5816: assign configin11_size11_wd = reg_wdata[14:8];
5817:
5818: assign configin11_pend11_we = addr_hit[22] & reg_we & ~wr_err;
5819: assign configin11_pend11_wd = reg_wdata[30];
5820:
5821: assign configin11_rdy11_we = addr_hit[22] & reg_we & ~wr_err;
5822: assign configin11_rdy11_wd = reg_wdata[31];
5823:
5824: assign iso_iso0_we = addr_hit[23] & reg_we & ~wr_err;
5825: assign iso_iso0_wd = reg_wdata[0];
5826:
5827: assign iso_iso1_we = addr_hit[23] & reg_we & ~wr_err;
5828: assign iso_iso1_wd = reg_wdata[1];
5829:
5830: assign iso_iso2_we = addr_hit[23] & reg_we & ~wr_err;
5831: assign iso_iso2_wd = reg_wdata[2];
5832:
5833: assign iso_iso3_we = addr_hit[23] & reg_we & ~wr_err;
5834: assign iso_iso3_wd = reg_wdata[3];
5835:
5836: assign iso_iso4_we = addr_hit[23] & reg_we & ~wr_err;
5837: assign iso_iso4_wd = reg_wdata[4];
5838:
5839: assign iso_iso5_we = addr_hit[23] & reg_we & ~wr_err;
5840: assign iso_iso5_wd = reg_wdata[5];
5841:
5842: assign iso_iso6_we = addr_hit[23] & reg_we & ~wr_err;
5843: assign iso_iso6_wd = reg_wdata[6];
5844:
5845: assign iso_iso7_we = addr_hit[23] & reg_we & ~wr_err;
5846: assign iso_iso7_wd = reg_wdata[7];
5847:
5848: assign iso_iso8_we = addr_hit[23] & reg_we & ~wr_err;
5849: assign iso_iso8_wd = reg_wdata[8];
5850:
5851: assign iso_iso9_we = addr_hit[23] & reg_we & ~wr_err;
5852: assign iso_iso9_wd = reg_wdata[9];
5853:
5854: assign iso_iso10_we = addr_hit[23] & reg_we & ~wr_err;
5855: assign iso_iso10_wd = reg_wdata[10];
5856:
5857: assign iso_iso11_we = addr_hit[23] & reg_we & ~wr_err;
5858: assign iso_iso11_wd = reg_wdata[11];
5859:
5860: assign data_toggle_clear_clear0_we = addr_hit[24] & reg_we & ~wr_err;
5861: assign data_toggle_clear_clear0_wd = reg_wdata[0];
5862:
5863: assign data_toggle_clear_clear1_we = addr_hit[24] & reg_we & ~wr_err;
5864: assign data_toggle_clear_clear1_wd = reg_wdata[1];
5865:
5866: assign data_toggle_clear_clear2_we = addr_hit[24] & reg_we & ~wr_err;
5867: assign data_toggle_clear_clear2_wd = reg_wdata[2];
5868:
5869: assign data_toggle_clear_clear3_we = addr_hit[24] & reg_we & ~wr_err;
5870: assign data_toggle_clear_clear3_wd = reg_wdata[3];
5871:
5872: assign data_toggle_clear_clear4_we = addr_hit[24] & reg_we & ~wr_err;
5873: assign data_toggle_clear_clear4_wd = reg_wdata[4];
5874:
5875: assign data_toggle_clear_clear5_we = addr_hit[24] & reg_we & ~wr_err;
5876: assign data_toggle_clear_clear5_wd = reg_wdata[5];
5877:
5878: assign data_toggle_clear_clear6_we = addr_hit[24] & reg_we & ~wr_err;
5879: assign data_toggle_clear_clear6_wd = reg_wdata[6];
5880:
5881: assign data_toggle_clear_clear7_we = addr_hit[24] & reg_we & ~wr_err;
5882: assign data_toggle_clear_clear7_wd = reg_wdata[7];
5883:
5884: assign data_toggle_clear_clear8_we = addr_hit[24] & reg_we & ~wr_err;
5885: assign data_toggle_clear_clear8_wd = reg_wdata[8];
5886:
5887: assign data_toggle_clear_clear9_we = addr_hit[24] & reg_we & ~wr_err;
5888: assign data_toggle_clear_clear9_wd = reg_wdata[9];
5889:
5890: assign data_toggle_clear_clear10_we = addr_hit[24] & reg_we & ~wr_err;
5891: assign data_toggle_clear_clear10_wd = reg_wdata[10];
5892:
5893: assign data_toggle_clear_clear11_we = addr_hit[24] & reg_we & ~wr_err;
5894: assign data_toggle_clear_clear11_wd = reg_wdata[11];
5895:
5896: assign phy_config_rx_differential_mode_we = addr_hit[25] & reg_we & ~wr_err;
5897: assign phy_config_rx_differential_mode_wd = reg_wdata[0];
5898:
5899: assign phy_config_tx_differential_mode_we = addr_hit[25] & reg_we & ~wr_err;
5900: assign phy_config_tx_differential_mode_wd = reg_wdata[1];
5901:
5902: assign phy_config_eop_single_bit_we = addr_hit[25] & reg_we & ~wr_err;
5903: assign phy_config_eop_single_bit_wd = reg_wdata[2];
5904:
5905: assign phy_config_override_pwr_sense_en_we = addr_hit[25] & reg_we & ~wr_err;
5906: assign phy_config_override_pwr_sense_en_wd = reg_wdata[3];
5907:
5908: assign phy_config_override_pwr_sense_val_we = addr_hit[25] & reg_we & ~wr_err;
5909: assign phy_config_override_pwr_sense_val_wd = reg_wdata[4];
5910:
5911: // Read data return
5912: always_comb begin
5913: reg_rdata_next = '0;
5914: unique case (1'b1)
5915: addr_hit[0]: begin
5916: reg_rdata_next[0] = intr_state_pkt_received_qs;
5917: reg_rdata_next[1] = intr_state_pkt_sent_qs;
5918: reg_rdata_next[2] = intr_state_disconnected_qs;
5919: reg_rdata_next[3] = intr_state_host_lost_qs;
5920: reg_rdata_next[4] = intr_state_link_reset_qs;
5921: reg_rdata_next[5] = intr_state_link_suspend_qs;
5922: reg_rdata_next[6] = intr_state_link_resume_qs;
5923: reg_rdata_next[7] = intr_state_av_empty_qs;
5924: reg_rdata_next[8] = intr_state_rx_full_qs;
5925: reg_rdata_next[9] = intr_state_av_overflow_qs;
5926: reg_rdata_next[10] = intr_state_link_in_err_qs;
5927: reg_rdata_next[11] = intr_state_rx_crc_err_qs;
5928: reg_rdata_next[12] = intr_state_rx_pid_err_qs;
5929: reg_rdata_next[13] = intr_state_rx_bitstuff_err_qs;
5930: reg_rdata_next[14] = intr_state_frame_qs;
5931: reg_rdata_next[15] = intr_state_connected_qs;
5932: end
5933:
5934: addr_hit[1]: begin
5935: reg_rdata_next[0] = intr_enable_pkt_received_qs;
5936: reg_rdata_next[1] = intr_enable_pkt_sent_qs;
5937: reg_rdata_next[2] = intr_enable_disconnected_qs;
5938: reg_rdata_next[3] = intr_enable_host_lost_qs;
5939: reg_rdata_next[4] = intr_enable_link_reset_qs;
5940: reg_rdata_next[5] = intr_enable_link_suspend_qs;
5941: reg_rdata_next[6] = intr_enable_link_resume_qs;
5942: reg_rdata_next[7] = intr_enable_av_empty_qs;
5943: reg_rdata_next[8] = intr_enable_rx_full_qs;
5944: reg_rdata_next[9] = intr_enable_av_overflow_qs;
5945: reg_rdata_next[10] = intr_enable_link_in_err_qs;
5946: reg_rdata_next[11] = intr_enable_rx_crc_err_qs;
5947: reg_rdata_next[12] = intr_enable_rx_pid_err_qs;
5948: reg_rdata_next[13] = intr_enable_rx_bitstuff_err_qs;
5949: reg_rdata_next[14] = intr_enable_frame_qs;
5950: reg_rdata_next[15] = intr_enable_connected_qs;
5951: end
5952:
5953: addr_hit[2]: begin
5954: reg_rdata_next[0] = '0;
5955: reg_rdata_next[1] = '0;
5956: reg_rdata_next[2] = '0;
5957: reg_rdata_next[3] = '0;
5958: reg_rdata_next[4] = '0;
5959: reg_rdata_next[5] = '0;
5960: reg_rdata_next[6] = '0;
5961: reg_rdata_next[7] = '0;
5962: reg_rdata_next[8] = '0;
5963: reg_rdata_next[9] = '0;
5964: reg_rdata_next[10] = '0;
5965: reg_rdata_next[11] = '0;
5966: reg_rdata_next[12] = '0;
5967: reg_rdata_next[13] = '0;
5968: reg_rdata_next[14] = '0;
5969: reg_rdata_next[15] = '0;
5970: end
5971:
5972: addr_hit[3]: begin
5973: reg_rdata_next[0] = usbctrl_enable_qs;
5974: reg_rdata_next[22:16] = usbctrl_device_address_qs;
5975: end
5976:
5977: addr_hit[4]: begin
5978: reg_rdata_next[10:0] = usbstat_frame_qs;
5979: reg_rdata_next[11] = usbstat_host_lost_qs;
5980: reg_rdata_next[14:12] = usbstat_link_state_qs;
5981: reg_rdata_next[15] = usbstat_usb_sense_qs;
5982: reg_rdata_next[18:16] = usbstat_av_depth_qs;
5983: reg_rdata_next[23] = usbstat_av_full_qs;
5984: reg_rdata_next[26:24] = usbstat_rx_depth_qs;
5985: reg_rdata_next[31] = usbstat_rx_empty_qs;
5986: end
5987:
5988: addr_hit[5]: begin
5989: reg_rdata_next[4:0] = '0;
5990: end
5991:
5992: addr_hit[6]: begin
5993: reg_rdata_next[4:0] = rxfifo_buffer_qs;
5994: reg_rdata_next[14:8] = rxfifo_size_qs;
5995: reg_rdata_next[19] = rxfifo_setup_qs;
5996: reg_rdata_next[23:20] = rxfifo_ep_qs;
5997: end
5998:
5999: addr_hit[7]: begin
6000: reg_rdata_next[0] = rxenable_setup_setup0_qs;
6001: reg_rdata_next[1] = rxenable_setup_setup1_qs;
6002: reg_rdata_next[2] = rxenable_setup_setup2_qs;
6003: reg_rdata_next[3] = rxenable_setup_setup3_qs;
6004: reg_rdata_next[4] = rxenable_setup_setup4_qs;
6005: reg_rdata_next[5] = rxenable_setup_setup5_qs;
6006: reg_rdata_next[6] = rxenable_setup_setup6_qs;
6007: reg_rdata_next[7] = rxenable_setup_setup7_qs;
6008: reg_rdata_next[8] = rxenable_setup_setup8_qs;
6009: reg_rdata_next[9] = rxenable_setup_setup9_qs;
6010: reg_rdata_next[10] = rxenable_setup_setup10_qs;
6011: reg_rdata_next[11] = rxenable_setup_setup11_qs;
6012: end
6013:
6014: addr_hit[8]: begin
6015: reg_rdata_next[0] = rxenable_out_out0_qs;
6016: reg_rdata_next[1] = rxenable_out_out1_qs;
6017: reg_rdata_next[2] = rxenable_out_out2_qs;
6018: reg_rdata_next[3] = rxenable_out_out3_qs;
6019: reg_rdata_next[4] = rxenable_out_out4_qs;
6020: reg_rdata_next[5] = rxenable_out_out5_qs;
6021: reg_rdata_next[6] = rxenable_out_out6_qs;
6022: reg_rdata_next[7] = rxenable_out_out7_qs;
6023: reg_rdata_next[8] = rxenable_out_out8_qs;
6024: reg_rdata_next[9] = rxenable_out_out9_qs;
6025: reg_rdata_next[10] = rxenable_out_out10_qs;
6026: reg_rdata_next[11] = rxenable_out_out11_qs;
6027: end
6028:
6029: addr_hit[9]: begin
6030: reg_rdata_next[0] = in_sent_sent0_qs;
6031: reg_rdata_next[1] = in_sent_sent1_qs;
6032: reg_rdata_next[2] = in_sent_sent2_qs;
6033: reg_rdata_next[3] = in_sent_sent3_qs;
6034: reg_rdata_next[4] = in_sent_sent4_qs;
6035: reg_rdata_next[5] = in_sent_sent5_qs;
6036: reg_rdata_next[6] = in_sent_sent6_qs;
6037: reg_rdata_next[7] = in_sent_sent7_qs;
6038: reg_rdata_next[8] = in_sent_sent8_qs;
6039: reg_rdata_next[9] = in_sent_sent9_qs;
6040: reg_rdata_next[10] = in_sent_sent10_qs;
6041: reg_rdata_next[11] = in_sent_sent11_qs;
6042: end
6043:
6044: addr_hit[10]: begin
6045: reg_rdata_next[0] = stall_stall0_qs;
6046: reg_rdata_next[1] = stall_stall1_qs;
6047: reg_rdata_next[2] = stall_stall2_qs;
6048: reg_rdata_next[3] = stall_stall3_qs;
6049: reg_rdata_next[4] = stall_stall4_qs;
6050: reg_rdata_next[5] = stall_stall5_qs;
6051: reg_rdata_next[6] = stall_stall6_qs;
6052: reg_rdata_next[7] = stall_stall7_qs;
6053: reg_rdata_next[8] = stall_stall8_qs;
6054: reg_rdata_next[9] = stall_stall9_qs;
6055: reg_rdata_next[10] = stall_stall10_qs;
6056: reg_rdata_next[11] = stall_stall11_qs;
6057: end
6058:
6059: addr_hit[11]: begin
6060: reg_rdata_next[4:0] = configin0_buffer0_qs;
6061: reg_rdata_next[14:8] = configin0_size0_qs;
6062: reg_rdata_next[30] = configin0_pend0_qs;
6063: reg_rdata_next[31] = configin0_rdy0_qs;
6064: end
6065:
6066: addr_hit[12]: begin
6067: reg_rdata_next[4:0] = configin1_buffer1_qs;
6068: reg_rdata_next[14:8] = configin1_size1_qs;
6069: reg_rdata_next[30] = configin1_pend1_qs;
6070: reg_rdata_next[31] = configin1_rdy1_qs;
6071: end
6072:
6073: addr_hit[13]: begin
6074: reg_rdata_next[4:0] = configin2_buffer2_qs;
6075: reg_rdata_next[14:8] = configin2_size2_qs;
6076: reg_rdata_next[30] = configin2_pend2_qs;
6077: reg_rdata_next[31] = configin2_rdy2_qs;
6078: end
6079:
6080: addr_hit[14]: begin
6081: reg_rdata_next[4:0] = configin3_buffer3_qs;
6082: reg_rdata_next[14:8] = configin3_size3_qs;
6083: reg_rdata_next[30] = configin3_pend3_qs;
6084: reg_rdata_next[31] = configin3_rdy3_qs;
6085: end
6086:
6087: addr_hit[15]: begin
6088: reg_rdata_next[4:0] = configin4_buffer4_qs;
6089: reg_rdata_next[14:8] = configin4_size4_qs;
6090: reg_rdata_next[30] = configin4_pend4_qs;
6091: reg_rdata_next[31] = configin4_rdy4_qs;
6092: end
6093:
6094: addr_hit[16]: begin
6095: reg_rdata_next[4:0] = configin5_buffer5_qs;
6096: reg_rdata_next[14:8] = configin5_size5_qs;
6097: reg_rdata_next[30] = configin5_pend5_qs;
6098: reg_rdata_next[31] = configin5_rdy5_qs;
6099: end
6100:
6101: addr_hit[17]: begin
6102: reg_rdata_next[4:0] = configin6_buffer6_qs;
6103: reg_rdata_next[14:8] = configin6_size6_qs;
6104: reg_rdata_next[30] = configin6_pend6_qs;
6105: reg_rdata_next[31] = configin6_rdy6_qs;
6106: end
6107:
6108: addr_hit[18]: begin
6109: reg_rdata_next[4:0] = configin7_buffer7_qs;
6110: reg_rdata_next[14:8] = configin7_size7_qs;
6111: reg_rdata_next[30] = configin7_pend7_qs;
6112: reg_rdata_next[31] = configin7_rdy7_qs;
6113: end
6114:
6115: addr_hit[19]: begin
6116: reg_rdata_next[4:0] = configin8_buffer8_qs;
6117: reg_rdata_next[14:8] = configin8_size8_qs;
6118: reg_rdata_next[30] = configin8_pend8_qs;
6119: reg_rdata_next[31] = configin8_rdy8_qs;
6120: end
6121:
6122: addr_hit[20]: begin
6123: reg_rdata_next[4:0] = configin9_buffer9_qs;
6124: reg_rdata_next[14:8] = configin9_size9_qs;
6125: reg_rdata_next[30] = configin9_pend9_qs;
6126: reg_rdata_next[31] = configin9_rdy9_qs;
6127: end
6128:
6129: addr_hit[21]: begin
6130: reg_rdata_next[4:0] = configin10_buffer10_qs;
6131: reg_rdata_next[14:8] = configin10_size10_qs;
6132: reg_rdata_next[30] = configin10_pend10_qs;
6133: reg_rdata_next[31] = configin10_rdy10_qs;
6134: end
6135:
6136: addr_hit[22]: begin
6137: reg_rdata_next[4:0] = configin11_buffer11_qs;
6138: reg_rdata_next[14:8] = configin11_size11_qs;
6139: reg_rdata_next[30] = configin11_pend11_qs;
6140: reg_rdata_next[31] = configin11_rdy11_qs;
6141: end
6142:
6143: addr_hit[23]: begin
6144: reg_rdata_next[0] = iso_iso0_qs;
6145: reg_rdata_next[1] = iso_iso1_qs;
6146: reg_rdata_next[2] = iso_iso2_qs;
6147: reg_rdata_next[3] = iso_iso3_qs;
6148: reg_rdata_next[4] = iso_iso4_qs;
6149: reg_rdata_next[5] = iso_iso5_qs;
6150: reg_rdata_next[6] = iso_iso6_qs;
6151: reg_rdata_next[7] = iso_iso7_qs;
6152: reg_rdata_next[8] = iso_iso8_qs;
6153: reg_rdata_next[9] = iso_iso9_qs;
6154: reg_rdata_next[10] = iso_iso10_qs;
6155: reg_rdata_next[11] = iso_iso11_qs;
6156: end
6157:
6158: addr_hit[24]: begin
6159: reg_rdata_next[0] = '0;
6160: reg_rdata_next[1] = '0;
6161: reg_rdata_next[2] = '0;
6162: reg_rdata_next[3] = '0;
6163: reg_rdata_next[4] = '0;
6164: reg_rdata_next[5] = '0;
6165: reg_rdata_next[6] = '0;
6166: reg_rdata_next[7] = '0;
6167: reg_rdata_next[8] = '0;
6168: reg_rdata_next[9] = '0;
6169: reg_rdata_next[10] = '0;
6170: reg_rdata_next[11] = '0;
6171: end
6172:
6173: addr_hit[25]: begin
6174: reg_rdata_next[0] = phy_config_rx_differential_mode_qs;
6175: reg_rdata_next[1] = phy_config_tx_differential_mode_qs;
6176: reg_rdata_next[2] = phy_config_eop_single_bit_qs;
6177: reg_rdata_next[3] = phy_config_override_pwr_sense_en_qs;
6178: reg_rdata_next[4] = phy_config_override_pwr_sense_val_qs;
6179: end
6180:
6181: default: begin
6182: reg_rdata_next = '1;
6183: end
6184: endcase
6185: end
6186:
6187: // Assertions for Register Interface
6188: `ASSERT_PULSE(wePulse, reg_we, clk_i, !rst_ni)
6189: `ASSERT_PULSE(rePulse, reg_re, clk_i, !rst_ni)
6190:
6191: `ASSERT(reAfterRv, $rose(reg_re || reg_we) |=> tl_o.d_valid, clk_i, !rst_ni)
6192:
6193: `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit), clk_i, !rst_ni)
6194:
6195: // this is formulated as an assumption such that the FPV testbenches do disprove this
6196: // property by mistake
6197: `ASSUME(reqParity, tl_reg_h2d.a_valid |-> tl_reg_h2d.a_user.parity_en == 1'b0, clk_i, !rst_ni)
6198:
6199: endmodule
6200: