hw/ip/hmac/rtl/hmac_reg_pkg.sv Cov: 100%

   1: // Copyright lowRISC contributors.
   2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
   3: // SPDX-License-Identifier: Apache-2.0
   4: //
   5: // Register Package auto-generated by `reggen` containing data structure
   6: 
   7: package hmac_reg_pkg;
   8: 
   9:   // Param list
  10:   parameter int NumWords = 8;
  11: 
  12:   ////////////////////////////
  13:   // Typedefs for registers //
  14:   ////////////////////////////
  15:   typedef struct packed {
  16:     struct packed {
  17:       logic        q;
  18:     } hmac_done;
  19:     struct packed {
  20:       logic        q;
  21:     } fifo_full;
  22:     struct packed {
  23:       logic        q;
  24:     } hmac_err;
  25:   } hmac_reg2hw_intr_state_reg_t;
  26: 
  27:   typedef struct packed {
  28:     struct packed {
  29:       logic        q;
  30:     } hmac_done;
  31:     struct packed {
  32:       logic        q;
  33:     } fifo_full;
  34:     struct packed {
  35:       logic        q;
  36:     } hmac_err;
  37:   } hmac_reg2hw_intr_enable_reg_t;
  38: 
  39:   typedef struct packed {
  40:     struct packed {
  41:       logic        q;
  42:       logic        qe;
  43:     } hmac_done;
  44:     struct packed {
  45:       logic        q;
  46:       logic        qe;
  47:     } fifo_full;
  48:     struct packed {
  49:       logic        q;
  50:       logic        qe;
  51:     } hmac_err;
  52:   } hmac_reg2hw_intr_test_reg_t;
  53: 
  54:   typedef struct packed {
  55:     struct packed {
  56:       logic        q;
  57:       logic        qe;
  58:     } hmac_en;
  59:     struct packed {
  60:       logic        q;
  61:       logic        qe;
  62:     } sha_en;
  63:     struct packed {
  64:       logic        q;
  65:       logic        qe;
  66:     } endian_swap;
  67:     struct packed {
  68:       logic        q;
  69:       logic        qe;
  70:     } digest_swap;
  71:   } hmac_reg2hw_cfg_reg_t;
  72: 
  73:   typedef struct packed {
  74:     struct packed {
  75:       logic        q;
  76:       logic        qe;
  77:     } hash_start;
  78:     struct packed {
  79:       logic        q;
  80:       logic        qe;
  81:     } hash_process;
  82:   } hmac_reg2hw_cmd_reg_t;
  83: 
  84:   typedef struct packed {
  85:     logic [31:0] q;
  86:     logic        qe;
  87:   } hmac_reg2hw_wipe_secret_reg_t;
  88: 
  89:   typedef struct packed {
  90:     logic [31:0] q;
  91:     logic        qe;
  92:   } hmac_reg2hw_key_mreg_t;
  93: 
  94: 
  95:   typedef struct packed {
  96:     struct packed {
  97:       logic        d;
  98:       logic        de;
  99:     } hmac_done;
 100:     struct packed {
 101:       logic        d;
 102:       logic        de;
 103:     } fifo_full;
 104:     struct packed {
 105:       logic        d;
 106:       logic        de;
 107:     } hmac_err;
 108:   } hmac_hw2reg_intr_state_reg_t;
 109: 
 110:   typedef struct packed {
 111:     struct packed {
 112:       logic        d;
 113:     } hmac_en;
 114:     struct packed {
 115:       logic        d;
 116:     } sha_en;
 117:     struct packed {
 118:       logic        d;
 119:     } endian_swap;
 120:     struct packed {
 121:       logic        d;
 122:     } digest_swap;
 123:   } hmac_hw2reg_cfg_reg_t;
 124: 
 125:   typedef struct packed {
 126:     struct packed {
 127:       logic        d;
 128:     } fifo_empty;
 129:     struct packed {
 130:       logic        d;
 131:     } fifo_full;
 132:     struct packed {
 133:       logic [4:0]  d;
 134:     } fifo_depth;
 135:   } hmac_hw2reg_status_reg_t;
 136: 
 137:   typedef struct packed {
 138:     logic [31:0] d;
 139:     logic        de;
 140:   } hmac_hw2reg_err_code_reg_t;
 141: 
 142:   typedef struct packed {
 143:     logic [31:0] d;
 144:   } hmac_hw2reg_key_mreg_t;
 145: 
 146:   typedef struct packed {
 147:     logic [31:0] d;
 148:   } hmac_hw2reg_digest_mreg_t;
 149: 
 150:   typedef struct packed {
 151:     logic [31:0] d;
 152:     logic        de;
 153:   } hmac_hw2reg_msg_length_lower_reg_t;
 154: 
 155:   typedef struct packed {
 156:     logic [31:0] d;
 157:     logic        de;
 158:   } hmac_hw2reg_msg_length_upper_reg_t;
 159: 
 160: 
 161:   ///////////////////////////////////////
 162:   // Register to internal design logic //
 163:   ///////////////////////////////////////
 164:   typedef struct packed {
 165:     hmac_reg2hw_intr_state_reg_t intr_state; // [320:318]
 166:     hmac_reg2hw_intr_enable_reg_t intr_enable; // [317:315]
 167:     hmac_reg2hw_intr_test_reg_t intr_test; // [314:309]
 168:     hmac_reg2hw_cfg_reg_t cfg; // [308:301]
 169:     hmac_reg2hw_cmd_reg_t cmd; // [300:297]
 170:     hmac_reg2hw_wipe_secret_reg_t wipe_secret; // [296:264]
 171:     hmac_reg2hw_key_mreg_t [7:0] key; // [263:0]
 172:   } hmac_reg2hw_t;
 173: 
 174:   ///////////////////////////////////////
 175:   // Internal design logic to register //
 176:   ///////////////////////////////////////
 177:   typedef struct packed {
 178:     hmac_hw2reg_intr_state_reg_t intr_state; // [627:625]
 179:     hmac_hw2reg_cfg_reg_t cfg; // [624:617]
 180:     hmac_hw2reg_status_reg_t status; // [616:617]
 181:     hmac_hw2reg_err_code_reg_t err_code; // [616:617]
 182:     hmac_hw2reg_key_mreg_t [7:0] key; // [616:361]
 183:     hmac_hw2reg_digest_mreg_t [7:0] digest; // [360:105]
 184:     hmac_hw2reg_msg_length_lower_reg_t msg_length_lower; // [104:105]
 185:     hmac_hw2reg_msg_length_upper_reg_t msg_length_upper; // [104:105]
 186:   } hmac_hw2reg_t;
 187: 
 188:   // Register Address
 189:   parameter logic [11:0] HMAC_INTR_STATE_OFFSET = 12'h 0;
 190:   parameter logic [11:0] HMAC_INTR_ENABLE_OFFSET = 12'h 4;
 191:   parameter logic [11:0] HMAC_INTR_TEST_OFFSET = 12'h 8;
 192:   parameter logic [11:0] HMAC_CFG_OFFSET = 12'h c;
 193:   parameter logic [11:0] HMAC_CMD_OFFSET = 12'h 10;
 194:   parameter logic [11:0] HMAC_STATUS_OFFSET = 12'h 14;
 195:   parameter logic [11:0] HMAC_ERR_CODE_OFFSET = 12'h 18;
 196:   parameter logic [11:0] HMAC_WIPE_SECRET_OFFSET = 12'h 1c;
 197:   parameter logic [11:0] HMAC_KEY0_OFFSET = 12'h 20;
 198:   parameter logic [11:0] HMAC_KEY1_OFFSET = 12'h 24;
 199:   parameter logic [11:0] HMAC_KEY2_OFFSET = 12'h 28;
 200:   parameter logic [11:0] HMAC_KEY3_OFFSET = 12'h 2c;
 201:   parameter logic [11:0] HMAC_KEY4_OFFSET = 12'h 30;
 202:   parameter logic [11:0] HMAC_KEY5_OFFSET = 12'h 34;
 203:   parameter logic [11:0] HMAC_KEY6_OFFSET = 12'h 38;
 204:   parameter logic [11:0] HMAC_KEY7_OFFSET = 12'h 3c;
 205:   parameter logic [11:0] HMAC_DIGEST0_OFFSET = 12'h 40;
 206:   parameter logic [11:0] HMAC_DIGEST1_OFFSET = 12'h 44;
 207:   parameter logic [11:0] HMAC_DIGEST2_OFFSET = 12'h 48;
 208:   parameter logic [11:0] HMAC_DIGEST3_OFFSET = 12'h 4c;
 209:   parameter logic [11:0] HMAC_DIGEST4_OFFSET = 12'h 50;
 210:   parameter logic [11:0] HMAC_DIGEST5_OFFSET = 12'h 54;
 211:   parameter logic [11:0] HMAC_DIGEST6_OFFSET = 12'h 58;
 212:   parameter logic [11:0] HMAC_DIGEST7_OFFSET = 12'h 5c;
 213:   parameter logic [11:0] HMAC_MSG_LENGTH_LOWER_OFFSET = 12'h 60;
 214:   parameter logic [11:0] HMAC_MSG_LENGTH_UPPER_OFFSET = 12'h 64;
 215: 
 216:   // Window parameter
 217:   parameter logic [11:0] HMAC_MSG_FIFO_OFFSET = 12'h 800;
 218:   parameter logic [11:0] HMAC_MSG_FIFO_SIZE   = 12'h 800;
 219: 
 220:   // Register Index
 221:   typedef enum int {
 222:     HMAC_INTR_STATE,
 223:     HMAC_INTR_ENABLE,
 224:     HMAC_INTR_TEST,
 225:     HMAC_CFG,
 226:     HMAC_CMD,
 227:     HMAC_STATUS,
 228:     HMAC_ERR_CODE,
 229:     HMAC_WIPE_SECRET,
 230:     HMAC_KEY0,
 231:     HMAC_KEY1,
 232:     HMAC_KEY2,
 233:     HMAC_KEY3,
 234:     HMAC_KEY4,
 235:     HMAC_KEY5,
 236:     HMAC_KEY6,
 237:     HMAC_KEY7,
 238:     HMAC_DIGEST0,
 239:     HMAC_DIGEST1,
 240:     HMAC_DIGEST2,
 241:     HMAC_DIGEST3,
 242:     HMAC_DIGEST4,
 243:     HMAC_DIGEST5,
 244:     HMAC_DIGEST6,
 245:     HMAC_DIGEST7,
 246:     HMAC_MSG_LENGTH_LOWER,
 247:     HMAC_MSG_LENGTH_UPPER
 248:   } hmac_id_e;
 249: 
 250:   // Register width information to check illegal writes
 251:   parameter logic [3:0] HMAC_PERMIT [26] = '{
 252:     4'b 0001, // index[ 0] HMAC_INTR_STATE
 253:     4'b 0001, // index[ 1] HMAC_INTR_ENABLE
 254:     4'b 0001, // index[ 2] HMAC_INTR_TEST
 255:     4'b 0001, // index[ 3] HMAC_CFG
 256:     4'b 0001, // index[ 4] HMAC_CMD
 257:     4'b 0011, // index[ 5] HMAC_STATUS
 258:     4'b 1111, // index[ 6] HMAC_ERR_CODE
 259:     4'b 1111, // index[ 7] HMAC_WIPE_SECRET
 260:     4'b 1111, // index[ 8] HMAC_KEY0
 261:     4'b 1111, // index[ 9] HMAC_KEY1
 262:     4'b 1111, // index[10] HMAC_KEY2
 263:     4'b 1111, // index[11] HMAC_KEY3
 264:     4'b 1111, // index[12] HMAC_KEY4
 265:     4'b 1111, // index[13] HMAC_KEY5
 266:     4'b 1111, // index[14] HMAC_KEY6
 267:     4'b 1111, // index[15] HMAC_KEY7
 268:     4'b 1111, // index[16] HMAC_DIGEST0
 269:     4'b 1111, // index[17] HMAC_DIGEST1
 270:     4'b 1111, // index[18] HMAC_DIGEST2
 271:     4'b 1111, // index[19] HMAC_DIGEST3
 272:     4'b 1111, // index[20] HMAC_DIGEST4
 273:     4'b 1111, // index[21] HMAC_DIGEST5
 274:     4'b 1111, // index[22] HMAC_DIGEST6
 275:     4'b 1111, // index[23] HMAC_DIGEST7
 276:     4'b 1111, // index[24] HMAC_MSG_LENGTH_LOWER
 277:     4'b 1111  // index[25] HMAC_MSG_LENGTH_UPPER
 278:   };
 279: endpackage
 280: 
 281: