hw/ip/prim_xilinx/rtl/prim_xilinx_pad_wrapper.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // Inferrable, bidirectional IO buffer for FPGAs. Implements inversion and
6: // virtual open drain feature.
7:
8:
9: module prim_xilinx_pad_wrapper #(
10: parameter int unsigned AttrDw = 2
11: ) (
12: inout wire inout_io, // bidirectional pad
13: output logic in_o, // input data
14: input out_i, // output data
15: input oe_i, // output enable
16: // additional attributes
17: input [AttrDw-1:0] attr_i
18: );
19:
20: // get pad attributes
21: logic od, inv;
22: assign {od, inv} = attr_i[1:0];
23:
24: // input inversion
25: assign in_o = inv ^ inout_io;
26:
27: // virtual open drain emulation
28: logic oe, out;
29: assign out = out_i ^ inv;
30: assign oe = oe_i & ((od & ~out) | ~od);
31:
32: // driver
33: assign inout_io = (oe) ? out : 1'bz;
34:
35: endmodule : prim_xilinx_pad_wrapper
36: