hw/ip/aes/rtl/aes.sv Cov: 100%
1: // Copyright lowRISC contributors.
2: // Licensed under the Apache License, Version 2.0, see LICENSE for details.
3: // SPDX-License-Identifier: Apache-2.0
4: //
5: // AES top-level wrapper
6:
7: module aes #(
8: parameter bit AES192Enable = 1, // Can be 0 (disable), or 1 (enable).
9: parameter SBoxImpl = "lut" // Can be "lut" (LUT-based SBox), or "canright".
10: ) (
11: input clk_i,
12: input rst_ni,
13:
14: // Bus Interface
15: input tlul_pkg::tl_h2d_t tl_i,
16: output tlul_pkg::tl_d2h_t tl_o
17: );
18:
19: import aes_reg_pkg::*;
20:
21: aes_reg2hw_t reg2hw;
22: aes_hw2reg_t hw2reg;
23:
24: aes_reg_top u_reg (
25: .clk_i,
26: .rst_ni,
27: .tl_i,
28: .tl_o,
29: .reg2hw,
30: .hw2reg,
31: .devmode_i(1'b1)
32: );
33:
34: aes_core #(
35: .AES192Enable ( AES192Enable ),
36: .SBoxImpl ( SBoxImpl )
37: ) aes_core (
38: .clk_i,
39: .rst_ni,
40: .reg2hw,
41: .hw2reg
42: );
43:
44: // All outputs should have a known value after reset
45: `ASSERT_KNOWN(TlODValidKnown, tl_o.d_valid, clk_i, !rst_ni)
46: `ASSERT_KNOWN(TlOAReadyKnown, tl_o.a_ready, clk_i, !rst_ni)
47:
48: endmodule
49: