#!/bin/sh -e
# This file is automatically generated by VCS.  Any changes you make
# to it will be overwritten the next time VCS is run.
vcs '-sverilog' '+vc' '-Mupdate' '-line' '-full64' 'tst_bench_top_t1.v' 'i2c_master_top.v' 'wb_master_model.v' 'i2c_slave_model.v' 'i2c_master_byte_ctrl.v' 'minimized_tst_bench_top_t1.v' '-o' 'simv' '-R'  -static_dbgen_only -daidir=$1 2>&1
