example0_bug1a_i-a_t-0.1.v
                                        ( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 :
========================================================
example0_bug1a_i-b_t-0.1.v
                                        ( {en,A,B,C} == 4'b1010) ? 8'b1111_1011 :
========================================================
example0_bug1b_i-a_t-0.1.v
                                                                   8'b0000_0000;
========================================================
example0_bug1b_i-b_t-0.1.v
                                                                   8'b0000_0000;
========================================================
example0_bug2_i-a_t-0.1.v
     assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111110 :
                                        ( {en,A,B,C} == 4'b1001) ? 8'b1111101 :
                                        ( {en,A,B,C} == 4'b1010) ? 8'b1111011 :
                                        ( {en,A,B,C} == 4'b1011) ? 8'b1110111 :
                                        ( {en,A,B,C} == 4'b1100) ? 8'b1101111 :
                                        ( {en,A,B,C} == 4'b1101) ? 8'b1011111 :
                                        ( {en,A,B,C}
========================================================
example0_bug2_i-b_t-0.1.v
     assign {Y7,Y6,Y5,Y4,Y3,Y2,Y1,Y0} = ( {en,A,B,C} == 4'b1000) ? 8'b1111110 :
                                        ( {en,A,B,C} == 4'b1001) ? 8'b1111101 :
                                        ( {en,A,B,C} == 4'b1010) ? 8'b1111011 :
                                        ( {en,A,B,C} == 4'b1011) ? 8'b1110111 :
                                        ( {en,A,B,C} == 4'b1100) ? 8'b1101111 :
                                        ( {en,A,B,C} == 4'b1101) ? 8'b1011111 :
                                        ( {en,A,B,C}
========================================================
example0_bug3_i-a_t-0.1.v
always@(posedge clk)
========================================================
example0_bug3_i-b_t-0.1.v
always@(posedge clk)
========================================================
example0_bug4_i-a_t-0.1.v
    else if(counter_out == 4'b1111) begin
========================================================
example0_bug4_i-b_t-0.1.v
    if(counter_out == 4'b1111)
========================================================
example0_bug5_i-a_t-0.1.v
        counter_out <= #1 4'b0000;
========================================================
example0_bug5_i-b_t-0.1.v
        counter_out <= #1 4'b0000;
========================================================
example0_bug6_i-a_t-0.1.v
//      if (rstn == 0) begin
========================================================
example0_bug6_i-b_t-0.1.v
//      if (rstn == 0) begin
========================================================
example0_bug7_i-a_t-0.1.v
      q <= t ? q : ~q;
   end

========================================================
example0_bug7_i-b_t-0.1.v
      if (t)
        q <= ~q;
      else
        q <= q;
   end

========================================================
example0_bug8_i-a_t-0.1.v
//  end
//end
//
//
========================================================
example0_bug8_i-b_t-0.1.v
//  end
//end
//
//
========================================================
example0_bug9_i-a_t-0.1.v
        GNT3 : begin
                 gnt_3 <= #1 1'b1;
               end
    endcase
  end
end


========================================================
example0_bug9_i-b_t-0.1.v
        GNT3 : begin
                 gnt_3 <= #1 1'b1;
               end
    endcase
  end
end

========================================================
example0_bug12_i-a_t-0.1.v
        if (load_en) begin
          op = load_val;
        end else begin
            for (i = 0; i < 8; i = i + 1) begin
              op[i] = op[i+1];
            end
            op[7] = op[0];
        end
      end
   end

========================================================
example0_bug12_i-b_t-0.1.v
        if (load_en) begin
          op <= load_val;
        end else begin
            for (i = 0; i < 8; i = i + 1) begin
              op[i+1] <= op[i];
            end
            op[0] <= op[7];
        end
      end
   end

========================================================
example0_bug13_i-a_t-0.1.v
      if (rstn == 1'b1) begin
========================================================
example0_bug13_i-b_t-0.1.v
      if (~rstn) begin
========================================================
example0_bug14_i-a_t-0.1.v
   always @ (posedge clk) begin
========================================================
example0_bug14_i-b_t-0.1.v
   always @ (posedge clk) begin
========================================================
example0_bug15_i-a_t-0.1.v
      case (sel)
         2'b00 : out <= a;
         2'b01 : out <= b;
         2'b10 : out <= c;
         2'b11 : out <= d;
      endcase
   end

========================================================
example0_bug15_i-b_t-0.1.v
      case (sel)
         2'b00 : out <= a;
         2'b01 : out <= b;
         2'b10 : out <= c;
         2'b11 : out <= d;
      endcase
   end

========================================================
example0_bug16_i-a_t-0.1.v
      case (sel)
         2'b00 : out <= a;
         2'b01 : out <= b;
         2'b10 : out <= c;
         2'b11 : out <= d;
      endcase
   end

========================================================
example0_bug16_i-b_t-0.1.v
      case (sel)
         2'b00 : out <= a;
         2'b01 : out <= b;
         2'b10 : out <= c;
         2'b11 : out <= d;
      endcase
   end

========================================================
example0_bug17_i-a_t-0.1.v
                       output reg [3:0] out);         // 4-bit output based on input sel
========================================================
example0_bug17_i-b_t-0.1.v
                       output reg [3:0] out);         // 4-bit output based on input sel
========================================================
example0_bug18_i-a_t-0.1.v
	always @(posedge sda_dly)
========================================================
example0_bug18_i-b_t-0.1.v
	always @(posedge sda or negedge scl)
========================================================
example0_bug19_i-a_t-0.1.v
	assign my_adr = (sr[7:1] == I2C_ADR);
========================================================
example0_bug19_i-b_t-0.1.v
	assign my_adr = (sr == 8'hA0);
========================================================
example0_bug20_i-a_t-0.1.v
          cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
========================================================
example0_bug20_i-b_t-0.1.v
          cmd_ack   <= #1 1'b0; // default no command acknowledge + assert cmd_ack only 1clk cycle
========================================================
example0_bug21_i-a_t-0.1.v
      for(w=0; w<8; w=w+1)
========================================================
example0_bug21_i-b_t-0.1.v
      for(w=0; w<7; w=w+1)
========================================================
example0_bug22_i-a_t-0.1.v
    assign out_ready = (reset) ? 0 : i[22];
========================================================
example0_bug22_i-b_t-0.1.v
    assign out_ready = i[22];
========================================================
example0_bug23_i-a_t-0.1.v
    assign update = (accept | (state & (~ done))) & (~ done); // don't fill buffer if done
========================================================
example0_bug23_i-b_t-0.1.v
    assign update = (accept | (state)) & (~ done) & (~ buffer_full); // don't fill buffer if done
========================================================
example0_bug24_i-a_t-0.1.v
              assign f[x][y] = e[x][y] ^ ((~ e[`add_1(x)][y]) & e[`add_2(x)][y]);
========================================================
example0_bug24_i-b_t-0.1.v
              assign f[x][y] = e[x][y] ^ (~ e[`add_1(x)][y] & e[`add_2(x)][y]);
========================================================
example0_bug25_i-a_t-0.1.v
            i <= {i[`M:1], i[0]};
========================================================
example0_bug25_i-b_t-0.1.v
            i <= {i[`M:1], i[0]};
========================================================example0_bug26_i-a_t-0.1.v
        ins6 (mu, nmu), // nmu == -mu
========================================================
example0_bug26_i-b_t-0.1.v
        ins6 (mu, nmu); // nmu == -mu
========================================================
example0_bug27_i-a_t-0.1.v
            i <= i >> 1;
========================================================
example0_bug27_i-b_t-0.1.v
            i <= i >> 1;
========================================================
example0_bug28_i-a_t-0.1.v
					const_timing<=8'd500 - 1;
========================================================
example0_bug28_i-b_t-0.1.v
					const_timing<=8'd500;   
========================================================
example0_bug29_i-a_t-0.1.v
always@(posedge clk or posedge reset)
========================================================
example0_bug29_i-b_t-0.1.v
always@(posedge clk or posedge reset)
========================================================
example0_bug30a_i-a_t-0.1.v
    wr_data_r <= {16{1'b0}};
========================================================
example0_bug30a_i-b_t-0.1.v
    wr_data_r <= {16{1'b0}};
========================================================
example0_bug30b_i-a_t-0.1.v
    rd_data_r <= 16'b0;
========================================================
example0_bug30b_i-b_t-0.1.v
    rd_data_r <= data_output;
========================================================
example0_bug31_i-a_t-0.1.v
           READ_NOP1 = 5'b10001,
========================================================
example0_bug31_i-b_t-0.1.v
           READ_NOP1 = 5'b10001,
========================================================
example0_bug32_i-a_t-0.1.v
          default:
            begin
            next = state;
            end
        endcase
      end
    end
  end

  always @(posedge clk)
  begin
    if (reset)
    begin
      state <= IDLE;
      state_cnt <= 4'd0;
      command <= CMD_NOP;
    end
    else
    begin
      state <= state_nxt;
      state_cnt <= state_cnt_nxt;
      command <= command_nxt;
    end
  end


========================================================
example0_bug32_i-b_t-0.1.v
          default:
            begin
            next = IDLE;
            state_cnt_nxt = 4'd0;
            end
        endcase
      end
    end
  end

========================================================
example0_bug11_i-a_t-0.1.v
//gnt_1 , // Active high grant to agent 1
//gnt_2 , // Active high grant to agent 2
//gnt_3 // Active high grant to agent 3
//);
//
//input clock , reset ;
//input req_0 , req_1 , req_2 , req_3 ;
//output reg gnt_0 , gnt_1 , gnt_2 , gnt_3 ;
//
//reg [1:0] state ;
//
//always @(posedge clock) begin
//if (reset) begin
//state <= 0 ;
//end else begin
//case (state)
//0: begin
//if (req_0) begin
//state <= 1 ;
//end
//end
//1: begin
//if (req_1) begin
//state <= 2 ;
//end
//end
//2:
========================================================
example0_bug11_i-b_t-0.1.v
//gnt_1 , // Active high grant to agent 1
//gnt_2 , // Active high grant to agent 2
//gnt_3 // Active high grant to agent 3
//);
//
//input clock;
//input reset;
//input req_0;
//input req_1;
//input req_2;
//input req_3;
//output gnt_0;
// FIX:
//output gnt_1;
//output gnt_2;
//output gnt_3;
//
//reg gnt_0;
// FIX:
//reg gnt_1;
//reg gnt_2;
//reg gnt_3;
//
//reg [1:0] state;
//
//always @(posedge clock) begin
//if (reset) begin
//state <= 0;
//end else begin
========================================================
example0_bug10_i-a_t-0.1.v
always @ (posedge clock or negedge reset)
========================================================
example0_bug10_i-b_t-0.1.v
always @ (req_0 or req_1 or req_2 or req_3 or state)
========================================================
