example0_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example1_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    valid_new = valid_reg; 
    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        dma_ctrl_new = CTRL_CHECK_LOAD; 
      
end

end

========================================================
example2_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example3_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example4_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example5_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example6_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    dma_valid_new = dma_valid_reg; 
    dma_ctrl_en = 0; 
    pmp_addr_en = 0; 
    pmp_access_type_en = 0; 
    dma_valid_en = 0; 
   
end

========================================================
example7_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example8_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example9_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example10_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example11_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    valid_new = valid_reg; 
    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        dma_ctrl_new = CTRL_CHECK_LOAD; 
        valid_new = VALID_IDLE; 
      
end

end

========================================================
example12_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example13_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg [DATA_WIDTH-1:0] done_reg, done_new; 

  reg [DATA_WIDTH-1:0] source
========================================================
example14_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example15_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example16_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example17_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example18_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example19_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example0_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 
  
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 
  
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg dest_addr_lsb_en; 
  
  reg
========================================================
example1_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example2_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Control FSM
  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
    
end

end

========================================================
example3_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example4_i-a_t-0.3.v
  logic pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  always_comb begin
    dma_ctrl_new = dma_ctrl_reg;
    pmp_addr_new = pmp_addr_reg;
    pmp_access_type_new = pmp_access_type_reg;
    valid_new = valid_reg;
    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        if (start_i) begin
          dma_ctrl_new = CTRL_CHECK_LOAD;
          valid_new = VALID_IDLE;
        
end

end

end

========================================================
example5_i-a_t-0.3.v
  reg pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
========================================================
example6_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example7_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  assign valid_o = valid_reg; 

  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    valid_new = valid_reg; 
    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        if (start_i) begin
          dma_ctrl_new = CTRL_CHECK_LOAD; 
          valid_new = VALID_IDLE; 
       
end

end

end

========================================================
example8_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example9_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

 
========================================================
example10_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

// BUG:
//  reg [1:0] dma_ctrl_state_reg, dma_ctrl_state_new; 
//  reg dma_ctrl_state_en; 
// FIX:
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_reg, dma_ctrl_state_new; 
  reg dma_ctrl_state_en; 

  reg [DATA_WIDTH-1:0] dma_length_reg, dma_length_new; 
  reg dma_length_en; 

  reg [DATA_WIDTH
========================================================
example11_i-a_t-0.3.v
  wire pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg
========================================================
example12_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example13_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Logic

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= 0; 
      dma_ctrl_en <= 0; 
      pmp_addr
end

end

========================================================
example14_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires

  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] length_reg; 

  //// Instances

  //// Logic

  assign source_addr_reg = source_addr_lsb_d + (source_addr_msb_d << DATA_WIDTH); 
  assign dest_addr_reg = dest_addr_lsb_d + (dest_addr_msb_d << DATA_WIDTH); 
  assign
========================================================
example15_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example16_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example17_i-a_t-0.3.v
  logic pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni == 1'b0) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      valid_reg <= VALID_IDLE; 
    
end

end

========================================================
example18_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example19_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example0_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] dma_done_reg, dma_done_new; 
  reg dma_done_en; 

  reg [DATA_WIDTH-1:0] dma_length_reg, dma_length_new; 
  reg dma_length_en; 

  reg [DATA_WIDTH-1:0] dma_source_addr_reg, dma_source_addr_new; 
  reg dma_source_addr_en; 

  reg [DATA_WIDTH-1:
========================================================
example1_i-a_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] start_addr_reg, start_addr_new; 
  reg start_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 
========================================================
example2_i-a_t-0.5.v
  logic pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  //// Logic
  
  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      valid_reg <= VALID_IDLE;
    
end

end

========================================================
example3_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 


  //// Control FSM
  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 64'h0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
    
end

end

========================================================
example4_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// State Machine
  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 1'b0; 
      dma_valid_reg <= VALID_IDLE;
      dma_valid_en <= 1'b0; 
      pmp_addr_reg <= 0;
      pmp_addr_en <= 1'b0; 
      pmp_access_type_reg <= riscv::ACC
end

end

========================================================
example5_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] temp_reg;
  reg [DATA_WIDTH-1:0] temp_new; 
  reg temp_en; 

  wire [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  wire [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 

  //// Logic

  //// Control
  always @(posedge clk_
========================================================
example6_i-a_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example7_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new;
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new;
  reg [DATA_WIDTH-1:0] length_reg, length_new;
  reg [DATA_WIDTH-1:0] start_reg, start_new;
  reg [DATA_WIDTH-1:0] done_reg, done_new;
  // BUG:
  // reg start_en; 
  // FIX:
========================================================
example8_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Combinational Logic
  
  always_comb begin
    dma_ctrl_new = CTRL_IDLE;
    pmp_addr_new = 64'b0;
    pmp_access_type_new = riscv::ACCESS_READ;
    dma_valid_new = VALID_IDLE;
    case (dma_ctrl_reg)
      CTRL_IDLE: begin 
        dma_ctrl_new = CTRL_CHECK_LOAD;
      
end

end

========================================================
example9_i-a_t-0.5.v
  reg [9:0] pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 

  //// State Machine
  always_ff @ (posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 1'b0; 
      pmp_addr_reg <= 0; 
      pmp_addr_en <= 1'b0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
      pmp_access_type_en <= 0; 
      valid_reg <= VALID_
end

end

========================================================
example10_i-a_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] start_addr_reg, start_addr_new; 
  reg start_addr_en; 

  reg [DATA_WIDTH-1:0] 
========================================================
example11_i-a_t-0.5.v
  logic pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 
  
  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0]
========================================================
example12_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  assign valid_o = valid_reg; 

  always_comb begin
    dma_ctrl_new = dma_ctrl_reg;
    pmp_addr_new = pmp_addr_reg;
    pmp_access_type_new = pmp_access_type_reg;
    valid_new = valid_reg;

    start_d = start_i;
    length_d = length_i;
    source_addr_lsb_d = source_addr_lsb_i;
    source_addr_msb_d = source_addr_msb_i;
    dest
end

========================================================
example13_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires
  wire [DATA_WIDTH-1:0] source_addr_d; 
  wire [DATA_WIDTH-1:0] dest_addr_d; 

  //// Assignments

  assign source_addr_d = {source_addr_msb_d, source_addr_lsb_d};
  assign dest_addr_d = {dest_addr_msb_d, dest_addr_lsb_d};

  //// State Machine 
  always_ff @(posedge clk_i, negedge rst_ni) begin
    if (!rst_ni) begin
end

end

========================================================
example14_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  reg [DATA_WIDTH-1:0] valid_tmp; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start
========================================================
example15_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  wire [DATA_WIDTH-1:0] source_addr_lsb_w;
  wire [DATA_WIDTH-1:0] source_addr_msb_w;
========================================================
example16_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example17_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational logic

  always @(*) begin 
    pmp_addr_new = {source_addr_msb_d, source_addr_lsb_d};
    pmp_access_type_new = riscv::ACCESS_WRITE;
    valid_new = VALID_LOAD;
    dma_ctrl_new = CTRL_CHECK_LOAD;
  
end

========================================================
example18_i-a_t-0.5.v
  logic pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_d; 
  
  //// State machine
  always_ff @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_READ;
      valid_d <= VALID_IDLE;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
   
end

end

========================================================
example19_i-a_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example0_i-a_t-0.7.v
  reg pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [7:0] pmp_addr_idx_reg, pmp_addr_idx_new; 
  reg [7:0] pmp_addr_idx_en; 

  reg [7:0] pmp_addr_idx_msb_reg, pmp_addr_idx_msb_new; 
  reg pmp_addr_idx_msb_en; 

  reg [DATA_WIDTH-1:0] dma_length_counter_reg, dma_length_counter_new; 
  reg dma_length_counter_en; 

  reg [DATA_WIDTH-
========================================================
example1_i-a_t-0.7.v
  logic pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en;

  reg [DATA_WIDTH-1:0] source_data_reg, source_data_new;
  reg source_data_en;

  reg [7:0] source_pmp_reg, source_pmp_new;
  reg source_pmp_en;

  reg [DATA_WIDTH-1:0] dest_data_reg, dest_data_new;
  reg dest_data_en;

  reg [7:0] dest_pmp_reg, dest_pmp_new;
  reg dest_pmp_en;

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
========================================================
example2_i-a_t-0.7.v
   wire pmp_access_type_en;

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new;
  reg dma_valid_en; 

  
  //// Sequential Logic
  always_ff @ (posedge clk_i, negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= 0;
      dma_ctrl_en <= 0;
      dma_valid_reg <= 0;
      dma_valid_en <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 

end

end

========================================================
example3_i-a_t-0.7.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Generate registers
  //// start_d
  genvar i; 
  generate 
    for (i = 0; i < 7; i = i + 1) begin : DUP1_0
      if (i == 0) begin
        start_d <= {start_d[DATA_WIDTH-1:1], start_i[0]};
      
end

end

========================================================
example4_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  //// Logic

  always @(posedge clk_i)
  begin
    if (rst_ni) begin 
      start_d        <= 0; 
      length_d       <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d   <= 0; 
      dest_addr_msb_d   <= 0; 
      done_d          <= 0; 
      dma_ctrl_reg    <= CTRL_IDLE; 
      pmp_addr_reg    <= 0; 
      pmp_access_type_reg <= 0; 
    
end

end

========================================================
example5_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_d, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] cur_addr_lsb_reg, cur_addr_lsb_new; 
  reg cur_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] cur_addr_msb_reg, cur_addr_msb_new; 
  reg cur_addr_msb_en; 

  reg [DATA_WIDTH-1:0] cur_length_reg, cur_length_new; 
  reg cur_length_en; 

  reg [DATA_WIDTH-1:0] cur_data_reg, cur_
========================================================
example6_i-a_t-0.7.v
  logic pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Signals

  wire [DATA_WIDTH-1:0] start_r;
  wire [DATA_WIDTH-1:0] length_r;
  wire [DATA_WIDTH-1:0] source_addr_lsb_r;
  wire [DATA_WIDTH-1:0] source_addr_msb_r;
  wire [DATA_WIDTH-1:0] dest_addr_lsb_r;
  wire [DATA_WIDTH-1:0] dest_addr_msb_r;
  wire [DATA_WIDTH
========================================================
example7_i-a_t-0.7.v
  reg [2:0] pmp_access_type_en; 

  //// Logic  
  
// BUG:
//  always @(posedge clk_i) begin
//    pmp_addr_new <= 0;
//    pmp_addr_en <= 0;
//    pmp_access_type_new <= 0;
//    pmp_access_type_en <= 0;
//    dma_ctrl_new <= CTRL_IDLE;
//    dma_ctrl_en <= 0;
//    if (rst_ni) begin
//      pmp_access_type_reg <= 0;
//      pmp_addr_reg <= 0;
//      dma_ctrl_reg <= 0;
//    
========================================================
example8_i-a_t-0.7.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 
  
  //// data
  // from dma
  reg [DATA_WIDTH-1:0] read_data; 
  // from riscv
  reg [DATA_WIDTH-1:0] write_data;
  // for riscv
  reg [DATA_WIDTH-1:0] riscv_read_data; 

  //// internal signals
  wire [DATA_WIDTH-1:0] riscv_write_data; 
  wire riscv_write_en; 

  wire riscv_read_addr_valid, r
========================================================
example9_i-a_t-0.7.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [2:0] ctrl_state_reg, ctrl_state_new; 
  reg ctrl_state_en; 

  reg [3:0] op_state_reg, op_state_new; 
  reg op_state_en; 

  //// Processes

  always @ (posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 64'h0;
      pmp_access_type_reg <= riscv::ACCESS_FETCH;
  // BUG:

end

end

========================================================
example10_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en;
  
  reg [1:0]   pmp_access_size_reg, pmp_access_size_new;
  reg [1:0]   pmp_access_size_en;
  
  reg [PMP_NUM_REGS-1:0] pmp_reg_idx_reg, pmp_reg_idx_new;
  reg pmp_reg_idx_en; 

  //// Wires
  wire [DATA_WIDTH-1:0] source_addr_lsb_w; 
  wire [DATA_WIDTH-1:0] source_addr_msb_w; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_w; 
  wire [DATA_
========================================================
example11_i-a_t-0.7.v
  reg [2:0] pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] valid_reg; 

  //// States
  always @(posedge clk_i or negedge rst_ni) begin 
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      valid_reg <= 0; 
    
end

end

========================================================
example12_i-a_t-0.7.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg dest_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  //// Logic

  assign valid_o = valid_reg;
  
  localparam [DATA_WIDTH-1:
========================================================
example13_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  
  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new;
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg source_addr_lsb_en, dest_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new;
  reg [DATA_WIDTH-1:0] dest_addr
========================================================
example14_i-a_t-0.7.v
  reg access_type_en; 

  reg [63:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en;
  
  reg [DATA_WIDTH-1:0] valid_d; 
  reg valid_en;
  
  
  //// State Machine
  ////
  //// Control State Machine 
  ////
  always @(posedge clk_i or posedge rst_ni) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
    
end

end

========================================================
example15_i-a_t-0.7.v
  logic pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 
  
  //// Combinational signals
  assign dma_ctrl_new = dma_ctrl_en ? dma_ctrl_reg : {dma_ctrl_reg[DMA_CTRL_WIDTH-1:1], CTRL_IDLE};

  assign dma_valid_new =  dma_valid_en ? dma_valid_reg : {DMA_VALID_WIDTH{1'b0}};

  wire [DATA_WIDTH-1:0] start_new; 
  wire [DATA_WIDTH-1:0] length_new; 
 
========================================================
example16_i-a_t-0.7.v
  reg pmp_access_type_en; 


  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 


  //// Internal logic
  wire [DMA_VALID_WIDTH-1:0] dma_valid_next;
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 1'b0) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
end

end

========================================================
example17_i-a_t-0.7.v
  logic pmp_access_type_en; 

  reg [DMA_LOAD_ADDR_WIDTH-1:0] dma_load_addr_reg, dma_load_addr_new; 
  reg dma_load_addr_en; 
  reg [DMA_STORE_ADDR_WIDTH-1:0] dma_store_addr_reg, dma_store_addr_new; 
  reg dma_store_addr_en; 
  reg [DMA_TRANSFER_LENGTH_WIDTH-1:0] dma_transfer_length_reg, dma_transfer_length_new; 
  reg dma_transfer_length_en; 

  //// Local logic

  always_ff @(posedge clk_i) begin
    dma_ctrl_
end

========================================================
example18_i-a_t-0.7.v
  wire pmp_access_type_en;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 
  reg [DATA_WIDTH-1:0] dma_done; 
  reg [DATA_WIDTH-1:0] zero_o; 
  reg [DATA_WIDTH-1:0] zero_d; 

  //// Control Logic

  always @(*) begin 
    dma_ctrl_next = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg;
    pmp_access_type_new = pmp_access_type_reg;
    valid_new =
end

========================================================
example19_i-a_t-0.7.v
  reg [2:0] pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] count_reg, count_new; 

  //// Finite State Machine
  //// states and state transitions 
  always @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 'b1) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 'b0;
   
end

end

========================================================
example0_i-a_t-0.9.v
  logic pmp_access_type_en; 

  reg [VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 


  //// State Machine

`ifdef RISCV_PMP_DEBUG

always @(posedge clk_i)
  $fwrite(riscv_pmp_debug_file, 
          $time % 100000, ",", 
          we_flag, ",",
          pmpcfg_i, ",",
          pmpaddr_i, ",",
          pmp_addr_reg, ",",
          dma_valid_reg, "\n");


`
========================================================
example1_i-a_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;  
  reg pmpcfg_en; 

  //// Frame sync logic 
  reg frame_sync_start; 
  wire frame_sync_done; 
  assign frame_sync_done = (valid_d <= 3'b001); 
  
  //// Reset logic
  always @(posedge clk_i or negedge rst_ni ) begin
    if (~rst_ni) begin
      valid_new <= VALID_IDLE; 
      dma_ctrl_new <= CTRL_IDLE
end

end

========================================================
example2_i-a_t-0.9.v
  reg [0:0] pmp_access_type_en; 

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  //// Control state
  
  logic [3:0] ctrl;
  logic [3:0] ctrl_next;

  //// Local variables
  
  logic [DATA_WIDTH-1:0] max_length; 
  logic [DATA_WIDTH-1:0] start_data; 
  logic [DATA_WIDTH-1:0] done_data;

  assign max_length = start_data + length - 1;
  assign start_data = start;

  reg enable_reg; 
  reg enable_new; 
  assign enable = enable_reg; 
========================================================
example3_i-a_t-0.9.v
  reg [1-1:0] pmp_access_type_en; // riscv::ACCESS_NONE or riscv::ACCESS_WRITE or riscv::ACCESS_READ


////// State Machine //////

//  always_ff @(posedge clk_i, negedge rst_ni) begin 
  always_@(posedge clk_i, negedge rst_ni) begin 
    if (!rst_ni) begin
      dma_ctrl_reg <= 0; 
      dma_ctrl_en <= 0; 

      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_access_type_en <= 1'b0; 

      pmp_addr_reg <= 0;
      pmp_addr_en <= 0; 
end

end

========================================================
example4_i-a_t-0.9.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new;
  reg valid_en; 

  //// Constants
  localparam [DATA_WIDTH-1:0] all_ones = {DATA_WIDTH{1'b1}}; 

  //// States
  localparam STATE_IDLE    = 'd0; 
  localparam STATE_VALID   = 'd1; 
  localparam STATE_CTRL_TX = 'd2;
  localparam STATE_DATA_TX = 'd3;
  localparam STATE_PAUSE   = 'd4;
  localparam STATE_DONE    = 'd5;
  localparam STATE_ABORT   = 'd6;
  reg [STATE_W
========================================================
example5_i-a_t-0.9.v
  reg access_type_addr_sel, access_type_addr_new;
// FIX: 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_msb_i; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_next_i; 
  output wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_next_o; 

  assign pmp_addr_new = pmpcfg_i[2] ?  (((pmpcfg_i[1:0] << 16) | pmpaddr_i[16-1:0]) << LOG2_LINE_WIDTH) : (pmpaddr_i | start_d) << LOG2_LINE_WIDTH; 
// BUG:
//  assign
========================================================
example6_i-a_t-0.9.v
  wire pmp_access_type_en; 
  //// FSM 
 
  always_ff @(posedge clk_i or negedge rst_ni) begin 
    if (!rst_ni) begin 
      dma_ctrl_reg <= 'd0;
      dma_ctrl_en <= 0;
      pmp_addr_reg <= 'x; 
      pmp_addr_en <= 0;
      pmp_access_type_reg <= 'd0; 
      //// BUG:
      // pmp_access_type_en <= 0; 
      //// FIX:
      //pmp_access_type_en <= 1'b0; 
    
end

end

========================================================
example7_i-a_t-0.9.v
  logic pmp_access_type_en; 
  
  
  //// Logic
 
  always @* begin 
    if (rst_ni == 1'b0) begin
       dma_ctrl_en       <= 0;
       pmp_addr_en       <= 0;
       pmp_access_type_en <= 0;
    
end

end

========================================================
example8_i-a_t-0.9.v
  logic pmp_access_type_en; 
  
  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DMA_CONFIG_WIDTH-1:0] dma_config_reg, dma_config_new; 
  reg dma_config_en; 



  reg [DATA_WIDTH-1:0] count; 

  always_ff @(posedge clk_i or negedge rst_ni) begin
      if (~rst_ni) begin
        dma_ctrl_reg <= CTRL_IDLE; 
        dma_ctrl_en <= 0; 

        pmp_addr_reg <= 0;
        pmp_addr_en
end

end

========================================================
example9_i-a_t-0.9.v
  reg [4-1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg [DATA_WIDTH-1:0] valid_reg_en; 
  
  reg [DATA_WIDTH-1:0] length_done; 

  //// Behaviours

// BUG: 
//  always@(posedge clk_i) begin 
//    pmp_access_type_reg <= pmp_access_type_new;
//  
========================================================
example10_i-a_t-0.9.v
  reg [8:0] pmp_access_type_en; 

  reg [3:0] pmp_region_reg, pmp_region_new; 
  
  reg [3:0] pmp_priv_reg, pmp_priv_new; 
  
  reg [DATA_WIDTH-1:0] pmp_data_reg, pmp_data_new;  
  
  reg [DMA_VALID_WIDTH-1:0] valid_reg, valid_new; 
// BUG:
//  reg valid_en;
// FIX:
  reg [8:0] valid_en;
  
  //// Methods 

  //// Bus Interface
  
  riscv::bus_interface_t axi4s(
    .clk_i(clk_i),
========================================================
example11_i-a_t-0.9.v
  reg [1:0] pmp_access_type_en;  

  //// Combinational circuit
  assign valid_o = (dma_ctrl_new[CTRL_CHECK_LOAD:CTRL_IDLE]) ? VALID_LOAD :
                   (dma_ctrl_new[CTRL_CHECK_STORE:CTRL_CHECK_LOAD]) ? VALID_STORE :
                   (dma_ctrl_new[CTRL_DONE:CTRL_IDLE] )? VALID_DONE : VALID_IDLE;
  //  assign valid_o = (dma_ctrl_new[CTRL_CHECK_LOAD:CTRL_IDLE]) ? 1'b1 : 1'b0;

  always_comb if (dma_ctrl_new[CTRL_LOAD:CTRL_IDLE]) begin
    pmp_
end

========================================================
example12_i-a_t-0.9.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_update_reg, pmp_addr_update_new; 
  reg pmp_addr_update_en;  
  
  reg [7:0] pmpcfg_reg, pmpcfg_new;   
  reg pmpcfg_en;  
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 


  always_ff @(posedge clk_i) if (!rst_ni) begin
    dma_ctrl_reg <= CTRL_IDLE; 
    valid_reg <= VALID_IDLE;
    pmpcfg_reg <= pmpcfg_i;
    done_d <= done_i;

 
end

========================================================
example13_i-a_t-0.9.v
  wire  pmp_access_type_en; // FIX
  

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  logic [RV_XPRLEN-1:0] xrdata_reg, xrdata_new;
  logic xrdata_en;


========================================================
example14_i-a_t-0.9.v
  logic pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] data_valid_reg, data_valid_new; 
  reg data_valid_en;

  reg [DMA_STATUS_WIDTH-1:0] dma_status; 


  // Forcing registers to use scl

  defparam
  dma_ctrl_reg.clock_enable = 1,
  dma_ctrl_reg.reset_type = ASYNC,
  dma_ctrl_reg.clock_edge = POS,
  dma_ctrl_reg.set_output_registers = 1,
  dma_ctrl_reg.output_register_style = "REG",
    
  pmp_addr_reg.clock_enable = 1,
  pmp_addr_reg.reset_
========================================================
example15_i-a_t-0.9.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg request_dump_reg, request_dump_new; 
  reg request_dump_en;

  wire vaild_reg_wr;
`ifdef CPU_DEBUG
  assign vaild_reg_wr = start_i[0];
`else
  assign vaild_reg_wr = 1'b1;
`
========================================================
example16_i-a_t-0.9.v
  logic pmp_access_type_en;

  reg [DATA_WIDTH-1:0] curr_op_cnt;
  reg [DATA_WIDTH-1:0] cp_data;

  //// Combinational Logic
  
  always_comb begin 
    valid_o = (dma_ctrl_reg == CTRL_DONE)? 4'b1000 :
      (dma_ctrl_reg == CTRL_LOAD)? 4'b10 :
      (dma_ctrl_reg == CTRL_STORE)? 4'b100 : 4'b0; 
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg;
    curr_op_c
end

========================================================
example17_i-a_t-0.9.v
  wire pmp_access_type_en; 

  reg [PHY_ADDR_WIDTH+3-1:0] source_addr_reg, source_addr_new;
  reg [PHY_ADDR_WIDTH+3-1:0] dest_addr_reg, dest_addr_new;
  reg [PHY_ADDR_WIDTH+3-1:0] data_addr_reg, data_addr_new;
  reg source_addr_en, dest_addr_en, data_addr_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg logic [DMA
========================================================
example18_i-a_t-0.9.v
  wired logic pmp_access_type_en; 

  riscv::pmp_regsand_t pmp_regsand_reg, pmp_regsand_new; // riscv::REGS_ZERO or riscv::REGS_RISCV
// BUG:
//  reg [1:0] pmp_regsand_en; 
// FIX:
  wired logic [1:0] pmp_regsand_en; 

  riscv::pmp_field_t pmp_field_reg, pmp_field_new;
// BUG:
//  reg pmp_field_en; 
// FIX:
  wired logic pmp_field_en; 

  reg [DMA_VALID_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_
========================================================
example19_i-a_t-0.9.v
  reg [1:0] pmp_access_type_en; 


  //// Generate the clock enable signals for blocks
  g_clk_enable( clk_i, rst_ni, 'h0,
                dma_ctrl_reg, dma_ctrl_en, dma_ctrl_new
  );
  g_clk_enable( clk_i, rst_ni, 'h0,
              pmp_access_type_reg, pmp_access_type_en[0], pmp_access_type_new,
              pmp_addr_reg, pmp_addr_en, pmp_addr_new
  );

  //// Always blocks
  always @(posedge clk_i or negedge rst_ni) begin 
    if( ~rst_ni ) begin 
     
end

end

========================================================
example0_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example1_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example2_i-b_t-0.1.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done_reg,
========================================================
example3_i-b_t-0.1.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done_reg,
========================================================
example4_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example5_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example6_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example7_i-b_t-0.1.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new
========================================================
example8_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example9_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example10_i-b_t-0.1.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new
========================================================
example11_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example12_i-b_t-0.1.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done_reg,
========================================================
example13_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example14_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example15_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example16_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example17_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example18_i-b_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example19_i-b_t-0.1.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 'd0; 
      length_d <= 'd0; 
      source_addr_lsb_d <= 'd0; 
      source_addr_msb_d <= 'd0; 
      dest_addr_lsb_d <= 'd0; 
      dest_addr_msb_d <= 'd0; 
      done_d <= 'd0; 
      dma_ctrl_reg <= CTRL_IDLE
end

end

========================================================
example0_i-b_t-0.3.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new
========================================================
example1_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    valid_new = valid_reg; 

    dma_ctrl_en = 0; 
    pmp_addr_en = 0; 
    pmp_access_type_en = 0; 
    valid_en = 0; 

    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        dma_
end

end

========================================================
example2_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example3_i-b_t-0.3.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg; 
  reg [DATA_WIDTH-1:0] source_addr_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_reg; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg; 
  reg [DATA_
========================================================
example4_i-b_t-0.3.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example5_i-b_t-0.3.v
  reg pmp_access_type_en = 0; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA
========================================================
example6_i-b_t-0.3.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done_reg,
========================================================
example7_i-b_t-0.3.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example8_i-b_t-0.3.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done_reg,
========================================================
example9_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example10_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example11_i-b_t-0.3.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_remaining_reg, length_remaining_new; 
  reg length_remaining_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source
========================================================
example12_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example13_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example14_i-b_t-0.3.v
  reg pmp_access_type_en = 1'b0;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb
========================================================
example15_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example16_i-b_t-0.3.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] done_reg, done_new; 
  reg done_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_
========================================================
example17_i-b_t-0.3.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] done
========================================================
example18_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en;
  reg [DATA_WIDTH-1:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en;
  reg [7:0] pmp_region_reg, pmp_region_new;
  reg pmp_region_en;
  reg [16-1:0] pmp_addr_lsb_reg, pmp_addr_lsb_new;
  reg pmp_addr_lsb_en;
  reg [16-1:0] pmp_addr_msb_reg, pmp_addr_msb_new;
  reg pmp_addr_msb_en;
  reg [16-1:0] pmp_cfg_reg, pmp_cfg_new;
  reg
========================================================
example19_i-b_t-0.3.v
  reg pmp_access_type_en = 1'b0; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] dma_data_reg, dma_data_new; 
  reg dma_data_en; 

  reg [DATA_WIDTH-1:0] dma_data_out_reg, dma_data_out_new; 
  reg dma_data_out_en; 

  reg [DATA_WIDTH-1:0] dma_data_in_reg, dma_data_in_new; 
  reg dma_data_in_en; 

  reg [DATA_
========================================================
example0_i-b_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  //// Internal Combinational Signals
  wire [DATA_WIDTH-1:0] source_addr_d, dest_addr_d; 
  wire [DATA_WIDTH-1:0] source_addr_next, dest_addr_next; 
  wire [DATA_WIDTH-1:0] length_next;
  wire [DATA_WIDTH-1:0] valid_next; 
  wire [DATA_WIDTH-1:0] done_next; 

  wire [DATA_WIDTH-1:0] source_addr_lsb_next, source_addr_msb_next; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_next, dest_addr_msb
========================================================
example1_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] byte
========================================================
example2_i-b_t-0.5.v
  reg [2:0] pmp_access_type_en;  
  

  //// Constants
  localparam [DATA_WIDTH-1:0] LOAD_MASK = {DATA_WIDTH{1'b1}}; 
  localparam [DATA_WIDTH-1:0] STORE_MASK = {DATA_WIDTH{1'b1}};
  localparam [DATA_WIDTH-1:0] DONE_MASK = {DATA_WIDTH{1'b1}}; 
  localparam [DATA_WIDTH-1:0] SOURCE_ADDR_LSB_MASK = {DATA_WIDTH{1'b1}};
  localparam [DATA_WIDTH-1:0] SOURCE_ADDR_MSB_MASK = {DATA_
========================================================
example3_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr
========================================================
example4_i-b_t-0.5.v
  reg pmp_access_type_en = 0; 


  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 

    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        if (start_i) begin
          dma_ctrl_new = CTRL_CHECK_LOAD; 
        
end

end

end

========================================================
example5_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 
  
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 
  
  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 
  
  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 
  
  //
========================================================
example6_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  
  //// State Machine
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_cfg_reg <= 0;
      valid_reg <= 0;
    
end

end

========================================================
example7_i-b_t-0.5.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] src_addr_reg, src_addr_new; 
  reg src_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] cnt_reg
========================================================
example8_i-b_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] source_addr_lsb_next; 
  wire [DATA_WIDTH-1:0] source_addr_msb_next; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_next; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_next; 
  wire [DATA_WIDTH-1:0] length_next; 
  wire [DATA_WIDTH-1:0] done_next; 
  wire [DATA_WIDTH-1:0] start_next; 
  wire [DATA_WIDTH-1:0] length_decr; 
 
========================================================
example9_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wire
  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 

  //// State Machine
  always_ff @(posedge clk_i) begin 
    if (rst_ni == 0) begin 
      dma_ctrl_reg <= CTRL_IDLE; 
    
end

end

========================================================
example10_i-b_t-0.5.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] count_reg, count_new; 
  reg count_en; 

  reg [DATA_WIDTH-1:0] source_data_
========================================================
example11_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg dest_addr_lsb_en; 

  reg [DATA_WIDTH-1:0]
========================================================
example12_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  //// Logic
  assign valid_o = (dma_ctrl_reg == CTRL_IDLE || dma_ctrl_reg == CTRL_DONE) ? VALID_IDLE : 
                   (dma_ctrl_reg == CTRL_LOAD) ? VALID_LOAD : 
                   (dma_ctrl_reg == CTRL_STORE) ? VALID_STORE : 
                   (dma_ctrl_reg == CTRL_DONE) ? VALID_DONE : 'bx; 

  assign pmp_access_type_new = (dma_ctrl_reg == CTRL_LOAD) ? riscv::ACCESS_READ : 
                               (dma_ctrl_reg == CTRL_STORE) ? riscv::ACCESS_WRITE : 'bx;
========================================================
example13_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b0; 


  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_
========================================================
example14_i-b_t-0.5.v
  reg [63:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_ls
========================================================
example15_i-b_t-0.5.v
  reg pmp_access_type_en = 0; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg dest_addr_lsb_en; 
  reg [DATA_WIDTH-1:0]
========================================================
example16_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [3:0] pmp_access_reg, pmp_access_new;
  reg [3:0] pmp_access_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg
========================================================
example17_i-b_t-0.5.v
  reg pmp_access_type_en = 0; 
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 

  //// Logic

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      valid_reg <= 0;
    
end

end

========================================================
example18_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Combinational Logic
  assign valid_o = dma_valid_reg; 

  //// Control Logic 

  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      start_d <= 0; 
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0; 
      done_d <=
end

end

========================================================
example19_i-b_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] pmp_access_size_reg, pmp_access_size_new;
  reg pmp_access_size_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] length_reg, length_new; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// State Machine
  always@(posedge clk_i or negedge rst_ni) begin
   
end

========================================================
example0_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  
  //// Intermediates

  wire [DATA_WIDTH-1:0] start_m; 
  wire [DATA_WIDTH-1:0] length_m;
  wire [DATA_WIDTH-1:0] source_addr_lsb_m; 
  wire [DATA_WIDTH-1:0] source_addr_msb_m; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_m; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_m; 
  wire [DATA_WIDTH-1:0] done_m; 
  wire [DATA_WIDTH-1:0] valid_m; 

 
========================================================
example1_i-b_t-0.7.v
  reg pmp_access_type_en = 1'b0; 

  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] valid_new; 
  reg valid_en; 

  //// Signal

  wire [DATA_WIDTH-1:0] source_addr_lsb_s; 
  wire [DATA_WIDTH-1:0] source_addr_msb_s; 

  wire [DATA_WIDTH-1:0] dest_addr_lsb_s; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_s; 


  assign source_addr_lsb_s = source_addr_d; 
  assign source_addr_msb_s = source_addr
========================================================
example2_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en;

  reg [DATA_WIDTH-1:0] csr_addr_reg, csr_addr_new;
  reg csr_addr_en; 

  reg [DATA_WIDTH-1:0] csr_data_reg, csr_data_new; 
  reg csr_data_en; 

  reg [DATA_WIDTH-1:0] csr_data_we_reg, csr_data_we_new; 
  reg csr_data_we_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid
========================================================
example3_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 


  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Pipeline
  always @(posedge clk_i) begin
    if(!rst_ni) begin
      start_d <= 'd0; 
      length_d <= 'd0; 
      source_addr_lsb_d <= 'd0; 
      source_addr_msb_d <= 'd0; 
      dest_addr_lsb_d <= 'd0; 
      dest_addr_msb_d <= 'd0; 
      done_d <= 'd1; 
      dma_ctrl_reg <= 'd0;
      valid_reg <= 'd0; 
end

end

========================================================
example4_i-b_t-0.7.v
  reg [1-1:0] pmp_access_type_en; 
  
  reg [2-1:0] pmp_access_size_reg, pmp_access_size_new; // riscv::ACCESS_4_BYTE or riscv::ACCESS_2_BYTE or riscv::ACCESS_1_BYTE
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_size_en;
// FIX: 
  reg [2-1:0] pmp_access_size_en;  

  //// Outputs
  output [DATA_WIDTH-1:0] valid_o_w;
  output [DATA_WIDTH-1:0] valid_o_r;
  wire [DATA_WIDTH-1:0
========================================================
example5_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 
 
////////////////////////////////////////////////////////////////////////////////////////////////////
////// Implementation 
////////////////////////////////////////////////////////////////////////////////////////////////////

  always @(posedge clk_i or negedge rst_ni) begin 
    if(!rst_ni) begin 
      //// Reset State 
      start_d <= 'd0;
      length_d <= 'd0; 
      source_addr_msb_d <= 'd0; 
      source_addr_lsb_d <= 'd0; 
      dest_addr_msb_d <= 'd0; 
      dest_addr_lsb_d <= 'd0; 
      done_d <= 'd0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 'd0;
end

end

========================================================
example6_i-b_t-0.7.v
  reg [2:0] pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new;
  reg valid_o_en; 

  //// Logic

  always_ff @(posedge clk_i, negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg   <= CTRL_IDLE;
      pmp_addr_reg   <= 0;
      pmp_access_type_reg   <= riscv::ACCESS_WRITE;
      valid_o_reg    <= VALID_IDLE;
      dma_ctrl_en    <= 0;
      pmp_addr_en    <= 0;
      valid_o_en     <= 0;
    
end

end

========================================================
example7_i-b_t-0.7.v
  reg pmp_access_type_en = 1'b0;

  //// Internal Signals 

  wire [DATA_WIDTH-1:0] source_addr; 
  wire [DATA_WIDTH-1:0] dest_addr; 
  reg [DATA_WIDTH-1:0] length_new;
  
  wire [DATA_WIDTH-1:0] next_source_addr; 
  wire [DATA_WIDTH-1:0] next_dest_addr; 
  reg [DATA_WIDTH-1:0] next_length;

  //// Components

  //// Logic

  assign next_source_addr = ((source_addr + 1) == 0) ? source_addr_lsb_i : source_addr + 1;
  assign next_dest_addr = ((dest_
========================================================
example8_i-b_t-0.7.v
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  //// FSM 
  always_ff @(posedge clk_i, negedge rst_ni) begin
    if (~rst_ni) begin 
      dma_ctrl_reg <= CTRL_IDLE;
    
end

end

========================================================
example9_i-b_t-0.7.v
  wire pmp_access_type_en; 
  assign pmp_access_type_en = ~rst_ni;

  reg [DATA_WIDTH-1:0] valid_d, valid_new; 

  reg [DATA_WIDTH-1:0] counter_reg, counter_new; 
  reg counter_en; 

  reg [DATA_WIDTH-1:0] source_reg, source_new; 
  reg source_en; 

  reg [DATA_WIDTH-1:0] dest_reg, dest_new; 
  reg dest_en; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_security_reg, pmp_security_new;
//  reg pmp_security_en;
// FIX:
 
========================================================
example10_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 
//  reg [63:0] pmp_data_reg, pmp_data_new;
//  reg pmp_data_en; 

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] counter_reg; 
  reg counter_en; 


  reg [DATA_WIDTH-1:0] source_addr_reg; 
  reg source_addr_en; 
  reg [DATA_WIDTH-1:0] dest_addr_reg; 
  reg dest_addr_en; 

  reg done_reg;
  reg done_en;
  reg write_enable;
  reg write_enable_en;
========================================================
example11_i-b_t-0.7.v
  reg pmp_access_type_en = 1'b0;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if(~rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_READ;
      valid_reg <= 0;
    
end

end

========================================================
example12_i-b_t-0.7.v
  reg [2-1:0] pmp_access_type_en;

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0]
========================================================
example13_i-b_t-0.7.v
  reg pmp_access_type_en = '0;

  reg pmp_permission_reg, pmp_permission_new; // riscv::pmp_perm_t
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_permission_en; 
// FIX:
  reg pmp_permission_en = '0;

  reg pmp_tor_reg, pmp_tor_new; // riscv::pmp_tor_t
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_tor_en; 
// FIX:
  reg pmp_tor_en = '0;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

 
========================================================
example14_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr
========================================================
example15_i-b_t-0.7.v
  reg pmp_access_type_en = 0; 

  //// Logic
  
  always @(posedge clk_i) begin 
    if (rst_ni == 1'b0) begin 
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_en <= 1'b0; 
      pmp_addr_reg <= 64'h0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmp_addr_en <= 1'b0; 
      pmp_access_type_en <= 1'b0; 
    
end

end

========================================================
example16_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en;
  ////pmp_access_type_en = 0;

  reg [3:0] pmp_index_reg, pmp_index_new;
  reg pmp_index_en; 

  reg [31:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 


  //// Internal Signals
  wire [DATA_WIDTH-1:0]  source_addr_d; 
  wire [DATA_WIDTH-1:0]  dest_addr_d; 
  wire [DATA_WIDTH-1:0]  length_minus1_d
========================================================
example17_i-b_t-0.7.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new;
  reg valid_en;

  reg [DATA_WIDTH-1:0] v_reg, v_new;
  reg v_en;

  //// Logic

  localparam PMP_ADDR_WIDTH = 54;
  localparam [PMP_ADDR_WIDTH-1:0] PMP_ADDR_WIDTH_MASK = (PMP_ADDR_WIDTH_MASK << PMP_ADDR_WIDTH) - 1;
  localparam [PMP_ADDR_WIDTH-1:0] PMP_ADDR_LSB_MASK = (1 << PMP_ADDR_WIDTH)
========================================================
example18_i-b_t-0.7.v
  reg pmp_access_type_en = 0; 

  reg [DMA_VALID_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_remaining_reg, length_remaining_new; 
  reg length_remaining_en; 

  reg done_reg, done_new; 
  reg done_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  //// Generate PMP Address (pmp_addr_new
========================================================
example19_i-b_t-0.7.v
  reg [63:0] pmp_access_type_en; 

  //// Local Variables

  logic [DATA_WIDTH-1:0] valid_d, valid_new; 
  logic [DATA_WIDTH-1:0] source_addr_reg, dest_addr_reg; 

  logic [PMP_ADDR_WIDTH-1:0] pmp_addr_next; 

  //// Data Path

  always_comb begin
    source_addr_reg = source_addr_lsb_d + (source_addr_msb_d<<DATA_WIDTH);
    dest_addr_reg = dest_addr_lsb_d + (dest_addr_msb_d<<DATA_WIDTH);
  
end

========================================================
example0_i-b_t-0.9.v
//  reg pmp_access_type_en = 'b0; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Outputs

  assign done_o = done_d; 


  
  //// Behavior

  // Reset the state machine and registers.
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_
end

end

========================================================
example1_i-b_t-0.9.v
  reg pmp_access_type_en = '0;
  
  //// Combinational Logic
  
  always @* begin
    start_d <= start_i; 
    length_d <= length_i; 
    source_addr_lsb_d <= source_addr_lsb_i; 
    source_addr_msb_d <= source_addr_msb_i; 
    dest_addr_lsb_d <= dest_addr_lsb_i; 
    dest_addr_msb_d <= dest_addr_msb_i; 
    done_d <= done_i; 
  
end

========================================================
example2_i-b_t-0.9.v
  reg [1:0] pmp_access_type_en; 

  reg [3:0] pmp_region_reg, pmp_region_new;
  reg pmp_region_en; 


  //// Logic
  assign valid_o = dma_ctrl_reg[DMA_CTRL_WIDTH-1:DMA_CTRL_WIDTH-4];


  //______________________________________________________________________________
  //// Controller
  always @(posedge clk_i, negedge rst_ni) begin 
    if (~rst_ni) begin
      dma_ctrl_new <= CTRL_IDLE;
    
end

end

========================================================
example3_i-b_t-0.9.v
  reg logic pmp_access_type_en;

  reg pmp_addr_inc;
  reg [DATA_WIDTH-1:0] state_reg; 
  reg [DATA_WIDTH-1:0] state_new; 

  reg [DATA_WIDTH-1:0] state_val_reg; 
  reg [DATA_WIDTH-1:0] state_val_new; 

  reg [DATA_WIDTH-1:0] length_remaining_reg; 
  reg [DATA_WIDTH-1:0] length_remaining_new; 
  //// Counters & Working Registers
  reg [2:0]   addr_counter_reg; 
  reg [2:0]   addr_counter_new; 

  reg [DATA_WIDTH-1
========================================================
example4_i-b_t-0.9.v
  reg [1 - 1:0] pmp_access_type_en;

  reg pmp_mark_reg, pmp_mark_new; 
  reg pmp_access_en; 

  //// Wires
  
  wire dma_ctrl_sel; 
  wire [2:0] pmp_access_sel; 
  wire pmp_mark_sel; 

  //// Internal Signals
  reg [DMA_CTRL_WIDTH:0] request;
  reg [3:0] m_dma_get_pmp_set;
  reg [DATA_WIDTH-1:0] m_dma_pm_addr; 
  reg m_dma_pm_addr_up; 
  reg [2:0] m_dma_pm_pmpcfg;
  reg
========================================================
example5_i-b_t-0.9.v
  reg [1:0]  pmp_access_type_en; 
  reg [PMP_SLOT_NUM-1:0] pmp_slot_reg, pmp_slot_new; 
  reg pmp_slot_en;

  reg [3:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en;

  reg [31:0] pmp_perm_lsb_reg, pmp_perm_lsb_new; 
  reg pmp_perm_lsb_en;

  reg [31:0] pmp_perm_msb_reg, pmp_perm_msb_new; 
  reg pmp_perm_msb_en;
  
  {pmp_perm_lsb_en, pmp_perm_msb_
========================================================
example6_i-b_t-0.9.v
  reg [3:0] pmp_access_type_en;

  //// State machine 
  always @ (posedge clk_i, negedge rst_ni) begin
    if (~rst_ni) begin // Reset
      start_d                  <= '0;
      length_d                 <= '0;
      source_addr_lsb_d        <= '0;
      source_addr_msb_d        <= '0;
      dest_addr_lsb_d          <= '0;
      dest_addr_msb_d          <= '0;
      done_d                   <= '0; 

      dma_ctrl_reg             <= CTRL_IDLE;
      dma_ctrl_new             <= CTRL_IDLE; 
      dma_ctrl_en              <= 1'b0;

      pmp_addr
end

========================================================
example7_i-b_t-0.9.v
  reg pmp_access_type_en; 
  assign 0 to pmp_access_type_en;
  
  reg [31:0] pmp_data_reg, pmp_data_new; 
  reg pmp_data_en; 

  wire [DATA_WIDTH-1:0] pmp_data_out_i;

  //// Control
  assign 
  dma_ctrl_new = {dma_ctrl_reg[DMA_CTRL_WIDTH-1:1], done_i||!start_i},
      pmp_addr_new = {dest_addr_lsb_i,source_addr_lsb_i},
      pmp_data_new =  {source_addr_msb_i,dest_addr_msb_i},
pmp_access_type_
========================================================
example8_i-b_t-0.9.v
  reg riscv::pmp_access_t pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] dma_valid_reg, dma_valid_new; 

  wire [DATA_WIDTH-1:0] we_lsb_w; 
  wire [DATA_WIDTH-1:0] we_msb_w; 
  wire [DATA_WIDTH-1:0] we_length_w; 
  wire [DATA_WIDTH-1:0] we_done_w; 
  wire [DATA_WIDTH-1:0] we_valid_w; 
  wire [DMA_CTRL_WIDTH-1:0] we_dma_ctrl_w; 
  wire we_pmp_access_type_w
========================================================
example9_i-b_t-0.9.v
  reg pmp_access_type_en = 1; 

  //// State Machines
  //
  // States:
  //   CTRL_IDLE
  //   CTRL_STORE_FIRST
  //   CTRL_STORE_SECOND
  //   CTRL_LOAD
  //   CTRL_DONE
  //   CTRL_ABORT
  //   CTRL_END
  //
  // State Transition Register:
  //   dma_ctrl_reg
  //
  // State Register:
  //   dma_ctrl_en (information to rror; 
  //   case (2'b00)
  //     if (pmpprot_clientside_cmp !== NULL) begin
  //       // Compute the security levels
  //       lhs = pmpprot_clientside_cmp.compute_source_security(
========================================================
example10_i-b_t-0.9.v
  reg [3-1:0]pmp_access_type_en;

  reg [DMA_VALID_WIDTH-1:0] valid_reg; 
  reg [DMA_VALID_WIDTH-1:0] valid_new; 
  reg valid_en;  
  
  reg [255:0] pmp_config; 

  //// Sequential Logic for Submodules
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if(~rst_ni) begin
      pmp_config <= 256'h0;
      pmp_addr_reg <= pmp_addr_new; 
      pmp_addr_en <= 1'b0;
      pmp_access_type_reg <= pmp_access_type_new; 
    //
end

end

========================================================
example11_i-b_t-0.9.v
  reg pmp_access_type_en; 
  wire pmp_access_type0_w, pmp_access_type1_w, pmp_access_type2_w, pmp_access_type3_w, pmp_access_type4_w, pmp_access_type5_w, pmp_access_type6_w, pmp_access_type7_w;
  assign pmp_access_type0_w = (pmp_access_type_d & 1) ? riscv::ACCESS_READ : riscv::ACCESS_WRITE;
  assign pmp_access_type1_w = (pmp_access_type_d & 2) ? riscv::ACCESS_READ : riscv::ACCESS_WRITE;
  assign pmp_access_type2_w = (
========================================================
example12_i-b_t-0.9.v
  reg [0:0] pmp_access_type_en;  

  //    reg [2:0] pmp_gran_reg,   pmp_gran_new; 
  //    reg [2:0] pmp_addrmsk_reg,pmp_addrmsk_new;
  //    reg [2:0] pmp_accesstype_reg, pmp_accesstype_new; 
  //    reg [1:0] pmp_nextpmp_reg,pmp_nextpmp_new; 
  //    reg pmp_en_reg, pmp_en_new; 
  //    reg pmp_priv_reg, pmp_priv_new;
  /* Alternative form without initializers:
  //declare reg [DATA_WIDTH-1:0] valid_reg
========================================================
example13_i-b_t-0.9.v
//  reg [SecurityLevels-1:0] pmp_access_type_en;

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [SecurityLevels-1:0] pmp_csr_sl_reg, pmp_csr_sl_new; 
//  reg [SecurityLevels-1:0] pmp_csr_sl_en; 
// FIX:
  reg [SecurityLevels-1:0] pmp_csr_sl_reg, pmp_csr_sl_new, pmp_csr_sl_en;

  reg pmp_amatch_reg, pmp_amatch_new;
  reg pmp_amatch_en;

  reg [7:0] pmp_addr_h_reg, pmp_addr_h_new;
========================================================
example14_i-b_t-0.9.v
  reg [2:0] pmp_access_type_en;

  reg riscv::pmp_region_t pmp_region_reg, pmp_region_new;
  // riscv::PMP_REGION_UNSUPPORTED, riscv::PMP_REGION_NA0, riscv::PMP_REGION_NA1, riscv::PMP_REGION_NA2
  reg pmp_region_en;  
  
  reg pmp_reg_write_sel_reg, pmp_reg_write_sel_new;   
  reg pmp_reg_write_sel_en;  
  
  wire [7:0] pmp_region_config_r;
  wire [2:0] pmp_access_type_r; 

  //// Constants
  local
========================================================
example15_i-b_t-0.9.v
  reg pmp_access_type_en; 
  genvar i;
  generate
  for (i=0; i<riscv::NUM_PMPS; i++)
  begin : pmpcfg
  localparam SET_CONFIG = 'b1111;
  localparam SET_ADDR = 'b1110; 
  localparam SET_TYPE = 'b1100;
  localparam SET_NUM = 'b1000;
  localparam CLEAR = 'b0;  
  
  reg [DATA_WIDTH-1:0] pmpcfg_d; 
  
  always_ff @(posedge clk_i or negedge reset_n) 
  begin
    if (!reset_n) pmpcfg_d <= 0;
    else if (pmpcfg_i == SET_CONFIG) 
      begin
end

end

end

========================================================
example16_i-b_t-0.9.v
  reg [defines::ACCESS_WIDTH-1:0] pmp_access_type_en;

  reg [DATA_WIDTH-1:0] valid_d; 


  // to generate a posedge clk signal
  reg Clk;


  //// initialize reset values
  // these signals are active low when not loading
  // so in reset assign to 1, to enable signals
  assign start_d = 1'h1; 
  assign length_d = 1'h1; 
  assign done_d = 1'h1; 

  assign source_addr_lsb_d = 1'h1; 
  assign source_addr_msb_d = 1'h1; 
  assign dest_addr_lsb_d = 1'h1; 
  assign dest_addr_msb_d
========================================================
example17_i-b_t-0.9.v
  // Nothing to do. Registers with security settings are reset to the configured value.
//  reg [1-1:0] pmp_access_type_en; 

  reg [3:0] pmp_index_reg, pmp_index_new;
  reg pmp_index_en; 

  reg pmp_write_reg, pmp_write_new;
  reg pmp_write_en; 

  //// Wire Declarations 
  wire [DATA_WIDTH-1:0] start_d;
  
  //// LUT Declarations
        genvar k; 
        generate         
	  for (k=0; k < 128; k = k + 1) begin
              if ((k>63) && (k < 65)) begin 
                if ((pmpaddr_i[k-64]==0
end

end

========================================================
example18_i-b_t-0.9.v
    reg [riscv::PmpAccessTypeSize-1:0] pmp_access_type_en;

  //// Combinatoral Logic

  assign {pmp_addr_new, pmp_access_type_new} = (  
    (dma_ctrl_new == CTRL_IDLE) ? {(32'h0), riscv::ACCESS_WRITE}:
    (dma_ctrl_new == CTRL_CHECK_LOAD) ? {source_addr_lsb_d, riscv::ACCESS_READ}:
    (dma_ctrl_new == CTRL_START_LOAD) ? {source_addr_msb_d, riscv::ACCESS_READ}:
    (dma_ctrl_new == CTRL_CHECK_STORE) ? {dest_addr_lsb_d, riscv::ACCESS_
========================================================
example19_i-b_t-0.9.v
  reg [2:0] pmp_access_reg, pmp_access_new;
  reg pmp_access_en; 

  reg pmp_page_type_reg, pmp_page_type_new;  // riscv::PAGE_OPEN or riscv::PAGE_CLOSED
  reg pmp_page_type_en; 
  
  // Memory Ordering Interface in and out selection.
  // This is used to handle memory requests in the proper order relative to each other.
  // I used 100 to represent the DMA controller having control of the memory access at that time.
  // This way I can have a higher priority than the MMU/CPU/etc.
  reg [7:0] memory_control;
  reg [7:0] memory_control_en;

  //// Internal
  wire [DATA_
========================================================
example0_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0
========================================================
example1_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example2_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_ms
========================================================
example3_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1
========================================================
example4_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example5_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WID
========================================================
example6_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 
  reg [1:0] pmp_access_type_en_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg
========================================================
example7_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example8_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires
  wire [DATA_WIDTH-1:0] source_addr_lsb_w; 
  wire [DATA_WIDTH-1:0] source_addr_msb_w; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_w; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_w; 
  wire [DATA_WIDTH-1:0] length_w; 
  wire [DATA_WIDTH-
========================================================
example9_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_access_type_en_d; 
  reg [7:0] pmp_access_type_en_q; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example10_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example11_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en
========================================================
example12_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg
========================================================
example13_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en
========================================================
example14_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Logic
  assign valid_o = valid_reg; 

  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d
end

end

========================================================
example15_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example16_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    pmp_cfg_new = pmp_cfg_reg; 
    valid_new = valid_reg; 

    dma_ctrl_en = 0; 
    pmp_addr_en =
end

========================================================
example17_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_d; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start
========================================================
example18_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done
end

end

========================================================
example19_i-c_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example0_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg [DATA_WIDTH-1:0] start_reg, start_new; 

  //// Wires

  wire [DATA_WIDTH-1:0]
========================================================
example1_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b01;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires

  wire [DATA_WIDTH-1:0] source_addr_lsb_next; 
  wire [DATA_WIDTH-1:0] source_addr_msb_next; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_next; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_next; 
  wire [DATA_WIDTH-1:0] length_next; 
  wire [DATA_WIDTH-1:0
========================================================
example2_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = {1'b0, pmp_access_type_en[1]};

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
    
end

end

========================================================
example3_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  reg [DATA_WIDTH-1:0] load_data_reg, load_data_new; 
  reg load_data_en; 
  
  reg [DATA_WIDTH-1:0] store_data_reg, store_data_new; 
  reg store_data_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_
========================================================
example4_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_next;
  reg [1:0] pmp_access_type_new_next;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] count_reg, count_new; 
  reg count_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WID
========================================================
example5_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (pmp_access_type_reg == pmp_access_type_new) ? 0 : 1;

  reg [2:0] pmp_index_reg, pmp_index_new;
  reg pmp_index_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WID
========================================================
example6_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  always_comb begin
    dma_ctrl_new = dma_ctrl_reg;
    pmp_addr_new = pmp_addr_reg;
    pmp_access_type_new = pmp_access_type_reg;
    valid_new = valid_reg;
    case (dma_ctrl_reg)
      CTRL_IDLE: begin
        dma_ctrl_new = CTRL_CHECK_LOAD;
        valid_new = VALID_IDLE;
      
end

end

========================================================
example7_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start
========================================================
example8_i-c_t-0.3.v
  reg [2:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  always_comb begin
    dma_ctrl_new = dma_ctrl_reg;
    pmp_addr_new = pmp_addr_reg;
    pmp_access_type_new = pmp_access_type_reg;
    pmp_cfg_new = pmp_cfg_reg;
    valid_new = valid_reg;

    dma_ctrl_en = 'b0; 
    pmp_addr_en = 'b
end

========================================================
example9_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_rst; 
  reg [1:0] pmp_access_type_new_rst; 
  assign pmp_access_type_en = pmp_access_type_new_rst;
  assign pmp_access_type_reg = pmp_access_type_reg_rst;
  assign pmp_access_type_new = pmp_access_type_new_rst;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_reg_rst <= 0;
      pmp_access_type_new_rst <= 0;
    
end

end

========================================================
example10_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en
========================================================
example11_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example12_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 
  reg [1:0] pmp_access_type_new_init; 
  
  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] source_addr_lsb_int; 
  wire [DATA_WIDTH-1:0] source_addr_msb_int; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_int; 
  wire [DATA_WIDTH-1:0] dest_addr
========================================================
example13_i-c_t-0.3.v
  reg [2:0] pmp_access_type_en; 
  reg [2:0] pmp_access_type_en_d; 
  reg [2:0] pmp_access_type_en_new; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 

========================================================
example14_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b01; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_
========================================================
example15_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0; 
      length_d <= 0;
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_
end

end

========================================================
example16_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_init; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] length_remaining_reg, length_remaining_new; 
  reg length_remaining_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [
========================================================
example17_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-
========================================================
example18_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_next; 
  reg [1:0] pmp_access_type_new_next; 
  reg [1:0] pmp_access_type_reg_next_next; 
  reg [1:0] pmp_access_type_new_next_next; 
  always @(posedge clk_i, negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_reg_next_next <= 0;
    
end

end

========================================================
example19_i-c_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [2:0] pmp_access_type_reg_init; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0
========================================================
example0_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_d; 

  reg [2:0] pmp_index_reg, pmp_index_new;
  reg pmp_index_en; 

  reg [DATA_WIDTH-1:0] dma_valid_new; 
  reg [DATA_WIDTH-1:0] dma_valid_reg; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-
========================================================
example1_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; // riscv::ACCESS_WRITE or riscv::ACCESS_READ

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Combinational Logic

  always @(*) begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    dma_valid_new = dma_valid_reg; 
  
end

========================================================
example2_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_d; 

  reg [DATA_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 
  
  //// Wire
  wire [DATA_WIDTH-1:0] data_o; 
  
  //// Block
  assign data_o = pmp_addr_reg[DATA_WIDTH-1:0]; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_valid_reg <= VALID_IDLE;
      pmp_addr_reg <=
end

end

========================================================
example3_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  assign valid_o = dma_ctrl_reg == CTRL_LOAD || dma_ctrl_reg == CTRL_STORE;

  //// Control Logic
  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_new <= CTRL_IDLE;
      dma_ctrl_en <= 0;
      pmp_access_type_new <= riscv::ACCESS_WRITE; 
      pmp_access_type_en <= 0;
      pmp_addr_new <= 0;
      pmp_addr_en <= 0;
    
end

end

========================================================
example4_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en;
  logic [1:0] pmp_access_type_en_logic;
  assign pmp_access_type_en_logic = pmp_access_type_en;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [2:0] pmp_idx_reg, pmp_idx_new;
  reg pmp_idx_en; 

  reg is_load_reg, is_load_new;
  reg is_load_en; 

  //// Logic 
  always @(posedge clk_i or negedge rst_ni) begin 
    if (~rst_ni) begin 
      start_d <= 'h
end

end

========================================================
example5_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_new_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [1:0] pmp_addr_width_reg, pmp_addr_width_new;
  reg pmp_addr_width_en;  

  //// Signals
  
  wire [DATA_WIDTH-1:0] start_t; 
  wire [DATA_WIDTH-1:0] length_t; 
  wire [DATA_WIDTH-1:0] source_addr_lsb_t; 
  wire [DATA_WIDTH-1:0] source_addr_msb_t
========================================================
example6_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = {riscv::ACCESS_WRITE, riscv::ACCESS_READ};

  //// Outputs
  wire [DATA_WIDTH-1:0] valid_o_int; 

  //// Wires
  wire [DATA_WIDTH-1:0] valid_o_int_reg; 
  wire [DATA_WIDTH-1:0] valid_o_int_new; 
  wire [DATA_WIDTH-1:0] valid_o_int_en; 

  wire [DATA_WIDTH-1:0] done_i_reg; 
  wire [DATA_WIDTH-1:0] done_i_new; 
  wire [DATA_
========================================================
example7_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg [DATA_WIDTH-1:0] valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr
========================================================
example8_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [3:0] pmp_access_size_reg, pmp_access_size_new; 
  reg pmp_access_size_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] data_o_reg, data_o_new; 
  reg data_o_en; 

  reg [DATA_
========================================================
example9_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_en; 

  //// Combinational Logic
  assign valid_o = valid_reg; 

  //// Sequential Logic
  always @(posedge clk_i) begin
    if (rst_ni == 1'b0) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      dma_ctrl_reg <=
end

end

========================================================
example10_i-c_t-0.5.v
//  initial pmp_access_type_reg = riscv::ACCESS_WRITE;

  reg [7:0] pmp_region_reg, pmp_region_new;
  reg pmp_region_en;  

  reg [DATA_WIDTH-1:0] valid_reg, valid_new;
  reg valid_en; 

  reg [DATA_WIDTH-1:0] count_reg, count_new;
  reg count_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new;
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new;
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:
========================================================
example11_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [3:0] pmp_access_type_value; 

  //// Logic

  always @(posedge clk_i) begin
    if (rst_ni == 1'b0) begin
      dma_ctrl_reg <= CTRL_IDLE; 
    
end

end

========================================================
example12_i-c_t-0.5.v
  reg [2:0] pmp_access_type_en; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example13_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [16-1:0] pmp_cfg_idx_reg, pmp_cfg_idx_new;
  reg pmp_cfg_idx_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires

  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] source_addr_new; 
  wire [DATA_WIDTH-1:0] dest_addr_new; 

  wire [DATA_WIDTH-1:0] source_addr
========================================================
example14_i-c_t-0.5.v
//  reg [1:0] pmp_access_type_en;
//  initial pmp_access_type_en = 0;
// END FIX
  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 

  //// Wires

  wire [DATA_WIDTH-1:0] source_addr; 
  wire [DATA_WIDTH-1:0] dest_addr; 
  wire [DATA_WIDTH-1:0] length_remaining; 
  wire [DATA_WIDTH-1:0] dma_ctrl_next; 
  wire [DATA_WIDTH-1:0] valid_next; 
  wire [DATA_WIDTH-1:0] pmp_addr_next;
========================================================
example15_i-c_t-0.5.v
  reg pmp_access_type_en; 
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example16_i-c_t-0.5.v
//  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] done_reg, done_new; 
  reg done
========================================================
example17_i-c_t-0.5.v
  reg [2:0] pmp_access_type_en; 
  assign pmp_access_type_en = (pmp_access_type_en == 0) ? 1 : pmp_access_type_en;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_remaining_reg, length_remaining_new; 
  reg length_remaining_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 


========================================================
example18_i-c_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  //// Internal Wires

  wire [DATA_WIDTH-1:0] start_m; 
  wire [DATA_WIDTH-1:0] length_m;
  wire [DATA_WIDTH-1:0] source_addr_lsb_m; 
  wire [DATA_WIDTH-1:0] source_addr_msb_m; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_m; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_m; 
  wire [DATA_WIDTH-1:0] done_m; 

  wire [DATA_WIDTH-1:0] source_addr_m; 
 
========================================================
example19_i-c_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_tmp, pmp_access_type_new_tmp; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  assign pmp_access_type_new_tmp = (dma_ctrl_new == CTRL_CHECK_LOAD || dma_ctrl_new == CTRL_LOAD) ? 2'b01 :
                                   (dma_ctrl_new == CTRL_CHECK_STORE || dma_ctrl_new == CTRL_STORE) ? 2'b10 : 2'b00;

  assign pmp_access_type_new = (pmp_access_type_new_tmp == 2'
========================================================
example0_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] valid_reg; 
  reg [DATA_WIDTH-1:0] valid_new; 

  //// State Machine
  
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0;
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_ABORT; 
      dma_ctrl_en <= 0; 
      pmp
end

end

========================================================
example1_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en;

  //// Constants

  localparam pmp_access_type_read = riscv::ACCESS_READ;
  localparam pmp_access_type_write = riscv::ACCESS_WRITE;
  localparam pmp_access_type_fetch = riscv::ACCESS_FETCH;

  localparam pmp_access_type_read_en = 'b1;
  localparam pmp_access_type_write_en = 'b10;
  localparam pmp_access_type_fetch_en = 'b100;

  //// State Machine

  always_ff @(posedge clk_i) begin
    if (rst_ni == 1'b0) begin
      dma_ctrl_reg <= CTRL_IDLE
end

end

========================================================
example2_i-c_t-0.7.v
//  initial pmp_access_type_reg = riscv::ACCESS_READ;
  always @(posedge clk_i or negedge rst_ni) begin
    if(!rst_ni) begin
      pmp_access_type_reg <= riscv::ACCESS_READ;
    
end

end

========================================================
example3_i-c_t-0.7.v
//  initial pmp_access_type_en = 0;
  reg pmp_access_type_en = 0;

  //// Processes
  wire pmp_grant; 
  wire pmp_abort; 
  wire [DATA_WIDTH-1:0] pmp_axi_addr; 
  wire [DATA_WIDTH-1:0] pmp_axi_wdata; 

  always @(posedge clk_i or negedge rst_ni) begin 
    if (rst_ni == 0) 
      begin
        dma_ctrl_reg <= CTRL_IDLE;
        dma_ctrl_en  <= 0; 

        pmp_addr_reg <= 0;
        pmp_addr_en  <= 0; 

        pmp_access_type_reg
end

end

========================================================
example4_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [7:0] pmp_perm_reg;
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg [7:0] pmp_perm_reg;
  
  reg [2:0] pmp_access_size_reg; 

  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_next; 

  //// Combinational Logic

  assign valid_o = valid_o_reg; 
  
  //// State Machine

  always @(posedge clk_i) begin 
    if (rst_ni) begin 
      dma_ctrl_reg <= CTRL_
end

end

========================================================
example5_i-c_t-0.7.v
  assign pmp_access_type_en = dma_ctrl_new == CTRL_START_LOAD ? 1'b1 : 1'b0;
  reg [riscv::SECURITY_SETTINGS_WIDTH-1:0] pmp_access_settings_reg, pmp_access_settings_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_settings_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  assign pmp_access_settings_en = dma_ctrl_new == CTRL_START_LOAD ? 1'b1 : 1'b0;

  reg [7:0] [16-1:0] pmpcfg_reg;
  reg [8:0] [16-1:0
========================================================
example6_i-c_t-0.7.v
  always @(posedge clk_i or negedge rst_ni) 
    if (~rst_ni) begin 
      pmp_access_type_reg <= riscv::ACCESS_NONE; 
    
end

========================================================
example7_i-c_t-0.7.v
  reg [1-1:0] pmp_access_type_en; 

  //// Control Logic
  always @(posedge clk_i or negedge rst_ni) begin 
    if (~rst_ni) begin
      dma_ctrl_en <= 'b0;
      pmp_addr_en <= 'b0;
      pmp_access_type_en <= 'b0;
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example8_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en;

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] start_d_new; 
  reg [DATA_WIDTH-1:0] length_d_new;
  reg [DATA_WIDTH-1:0] source_addr_lsb_d_new; 
  reg [DATA_WIDTH-1:0] source_addr_msb_d_new; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_d_new; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_d_new; 
  reg [DATA_W
========================================================
example9_i-c_t-0.7.v
  initial begin
    pmp_access_type_en = 1'b0; 
    pmp_access_type_reg = riscv::ACCESS_WRITE;
  
end

========================================================
example10_i-c_t-0.7.v
  logic [1:0] pmp_access_type_en;
  reg [riscv::PMPCFG_BITS:0] [riscv::PMP_REGIONS-1:0] pmp_access_reg, pmp_access_new; 
  reg [riscv::PMPCFG_BITS:0] [riscv::PMP_REGIONS-1:0] pmp_access_en; 
  
  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0
========================================================
example11_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  initial pmp_access_type_reg = riscv::ACCESS_WRITE;
  initial pmp_access_type_new = riscv::ACCESS_WRITE;
 
  reg [DATA_WIDTH-1:0] src_pmp_addr_reg, src_pmp_addr_new;
  reg src_pmp_addr_en;
 
  reg [DATA_WIDTH-1:0] dst_pmp_addr_reg, dst_pmp_addr_new;
  reg dst_pmp_addr_en;

  reg [DATA_WIDTH-1:0] valid_reg;
  reg [DATA_WIDTH-1:0] valid_new;
  reg valid_en;

  reg
========================================================
example12_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  reg valid_reg, valid_new; 

  reg [2:0] load_reg, load_new; 
  reg [2:0] store_reg, store_new;  
  reg [2:0] done_reg, done_new; 


  //// Wire Declarations
  wire [DATA_WIDTH-1:0] load_addr_lsb; 
  wire [DATA_WIDTH-1:0] load_addr_msb; 
  wire [DATA_WIDTH-1:0] store_addr_lsb; 
  wire [DATA_WIDTH-1:0] store_addr_msb; 
  wire [DATA_WIDTH-1:0] load_addr_d; 
 
========================================================
example13_i-c_t-0.7.v
  reg pmp_access_type_en;
  initial pmp_access_type_en = 0;
  initial pmp_access_type_reg = 0;
  initial pmp_access_type_new = 0;
// END FIX

  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Generate all the resets for the registers, using the active-high reset.
  //// Later we will invert the polarity of the reset to make it active-low. 
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_
end

end

========================================================
example14_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  wire [DATA_WIDTH-1:0] dma_valid_state; 

  //// Control Path

  always @(posedge clk_i) begin
    dma_ctrl_reg <= dma_ctrl_new; 
  
end

========================================================
example15_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en, pmp_access_type_new_r, pmp_access_type_reg_r;

  reg [7:0] pmp_region_reg, pmp_region_new; 
  reg pmp_region_en; 

  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new, valid_o_d; 

  //// Wires

  wire [DATA_WIDTH-1:0] start_ff;
  wire [DATA_WIDTH-1:0] length_ff;
  wire [DATA_WIDTH-1:0] source_addr_lsb_ff;
  wire [DATA_WIDTH-1:0] source_addr_msb_ff;
  wire [DATA_
========================================================
example16_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] pmp_data_reg, pmp_data_new; 
  reg pmp_data_en; 

  reg [3:0] pmp_idx_reg, pmp_idx_new; 
  reg pmp_idx_en; 

  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 

  reg [DATA_WIDTH-1:0] data_reg; 
  
  reg [63:0] pmp_addr; 
  reg [3:0] pmp_idx; 
  reg [DATA_WIDTH-1:0] pmp_data
========================================================
example17_i-c_t-0.7.v
reg [1:0] pmp_access_type_en;
  reg pmp_access_type_reg_2, pmp_access_type_new_2; // riscv::ACCESS_WRITE or riscv::ACCESS_READ

  reg [3:0] pmp_base_reg, pmp_base_new; 
  reg pmp_base_en; 
  reg [3:0] pmp_bound_reg, pmp_bound_new; 
  reg pmp_bound_en; 

  reg [DATA_WIDTH-1:0] start_d_2; 
  reg [DATA_WIDTH-1:0] length_d_2;
  reg [DATA_WIDTH-1:0] source_addr_lsb_d_2; 
  reg [DATA
========================================================
example18_i-c_t-0.7.v
  reg [riscv::pmp_access_width-1:0] pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 

  reg [DMA_DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  //// Control logic

  always @(posedge clk_i) begin
    if (rst_ni == 'b1) begin
      start_d                 <= 'd0; 
      length_d                <= 'd0;
end

end

========================================================
example19_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en;  
//  reg [1:0] pmp_access_type_en;  

  
  //// Sequencer
  reg [DMA_CTRL_WIDTH-1:0] ctrl_seq; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_seq_new; 
  reg ctrl_seq_en; 

  //// Done_o
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// dma_d
  reg [DATA_WIDTH-1:0] dma_d_reg, dma_d_new; 
  reg dma_d_en; 

  //// dma_q
========================================================
example0_i-c_t-0.9.v
  reg [2-1:0] pmp_access_type_en = 0; 

  logic [16-1:0][7:0] pmp_block_size_reg; // These three variables
  logic [16-1:0][8:0] pmp_tor_reg;        // keep track of the pmp
  logic [16-1:0][7:0] pmp_na_reg;         // configuration
  
  logic [2-1:0]       pmp_napot_reg;    // NaCl/Pot Luck
  logic [2-1:0]      pmp_wip_reg;       // Writeable, Internal and Privileged only
  logic [2-1:0]      pmp_ron_reg;       // Read-only, No Execute and Not Cacheable
  logic [2-1:0
========================================================
example1_i-c_t-0.9.v
  reg [2:0] pmp_access_type_en; 

  //// Processing

  always @(posedge clk_i, negedge rst_ni) begin
	if (~rst_ni) begin
           start_d <= 0;
           length_d <= 0;
           source_addr_lsb_d <= 0;
           source_addr_msb_d <= 0;
           dest_addr_lsb_d <= 0;
           dest_addr_msb_d <= 0;
           done_d <= 0;
           dma_ctrl_reg <= CTRL_IDLE; 
 		pmp_addr_reg <= 0; 	
 		pmp_access_type_reg <= riscv::ACCESS_READ; 
        
end

end

========================================================
example2_i-c_t-0.9.v
  reg [PmpAccessTypeWidth-1:0] pmp_access_type_reg, pmp_access_type_new; 
  

  reg [VALID_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg [3:0] pmp_num_idx_reg, pmp_num_idx_new;
  reg pmp index_en;


  //// Functions 

  function generate_dma_ctrl;
    input [2:0] dma_state;
    input [2:0] valid_state;
    input [DATA_WIDTH-1:0] length;
    input [DATA_WIDTH-1
========================================================
example3_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en; //riscv::pmp_access_t; // Enum {0-Default Value} or {1-New Value}
                                 //  or riscv::pmp_access_t, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
                                 
  reg [7:0][DATA_WIDTH-1:0] pmp_config_reg, pmp_config_new;
  reg pmp_config_en;  

  reg [DATA_WIDTH-1:0] lsb_addr_reg, lsb_addr_new;
  reg lsb_addr_en;   
  reg [DATA_WIDTH-1:0] msb_addr_reg, msb_addr
========================================================
example4_i-c_t-0.9.v
  reg [63:0] zero = {44'd0, riscv::ACCESS_NONE};
  always @ (posedge clk_i)
    if(rst_ni == 'b1)
      pmp_access_type_reg <= zero;
  reg pmp_access_type_en;  

  //// Constants
  localparam CTRL_WIDTH = BASE_DMA_CTRL_WIDTH;
  localparam [CTRL_WIDTH-1:0] CTRL_ACK_LSB = BASE_ACK_LSB;
  localparam [CTRL_WIDTH:0] CTRL_ACK_MSB = BASE_ACK_MSB;
  localparam [CTRL_WIDTH-1:0] CTRL_WR_LSB = BASE_WR_LSB;
  localparam [CTRL_
========================================================
example5_i-c_t-0.9.v

  reg pmp_access_type_en;

  reg [DATA_WIDTH-1:0] word_count_reg, word_count_new;
  reg word_count_en; 

  wire abort_d; 
  wire [DATA_WIDTH-1:0] source_addr_reg, source_addr_new, dest_addr_reg, dest_addr_new; 
  wire source_addr_en, dest_addr_en; 
  wire source_addr_clear, dest_addr_clear; 

  //// Abort 

  assign abort_d = WE_LOAD & (~we_flag); 

  //// Register enable / clocks  
  
  always_ff @(posedge clk_i, posedge rst_ni)
  begin  
    if(rst_ni == 0)  begin
end

end

========================================================
example6_i-c_t-0.9.v
//  parameter pmp_access_type_reg_reset_value = 2'b11)  
  reg [1:0] pmp_access_type_reg, pmp_access_type_new;  
  reg pmp_access_type_en; 

  //// Values
  reg [DATA_WIDTH-1:0] page_size; 
  reg [DATA_WIDTH-1:0] pmp_tor, pmp_tor_new;
  reg pmp_tor_en;

  //// Internal Variables
  reg [DATA_WIDTH-1:0]  remaining;

  //// Instances
  pmu pmu(
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .start_i(start_d),
    .
========================================================
example7_i-c_t-0.9.v
  reg pmp_access_type_en  = 0; 

  reg logic [DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 


  //// Constants

  localparam [DMA_CTRL_WIDTH-1:0] CTRL_IDLE_ENC = CTRL_IDLE; 
  localparam [DMA_CTRL_WIDTH-1:0] CTRL_CHECK_LOAD_ENC = CTRL_CHECK_LOAD; 
  localparam [DMA_CTRL_WIDTH-1:0] CTRL_START_LOAD_ENC = CTRL_START_LOAD; 
  localparam [DMA_CTRL_WIDTH-1:0] CTRL_LOAD_ENC = CTRL_LOAD; 
  localparam [DMA
========================================================
example8_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 0; 

  reg [3:0] pmp_idx_reg, pmp_idx_new;
  reg pmp_idx_en;

  reg [31:0] start_reg, start_new;
  reg [31:0] start_p
========================================================
example9_i-c_t-0.9.v
//  Initialize with an illegal security configuration value.
//  The register will be updated on the *next* clock
//  after the reset is deasserted.
  reg [0:0] pmp_block_access_status_reg, pmp_block_access_status_new = 2'b11; 
  reg pmp_block_access_type_en; 
  //// Wire Declarations
  wire [DATA_WIDTH-1:0] int_done_wire, int_valid_wire;
  wire [DATA_WIDTH-1:0] dma_ctrl_wire, pmp_addr_wire;

  parameter STATE_IDLE = "h1; 
  parameter STATE_LOAD = "h11; 
  parameter STATE_STORE = "h111; 

  assign int_valid_wire = dma_ctrl
========================================================
example10_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en;     
  // The pmp_access_type_en value is modified using a module that has security sensitive inputs.
  // For security reasons, values are only allowed to flow from registers into modules with sensitive inputs.
  // To that 
========================================================
example11_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en;
  reg [3:0] pmp_access_type_reg_save;
  logic [2:0] pmp_access_type_new_save;

  reg [3:0] pmp_id_reg, pmp_id_new;
  reg pmp_id_en; 

  reg dma_ctrl_load, dma_ctrl_store, dma_ctrl_done, dma_ctrl_abort; 

  //// PMP access group
  gener
========================================================
example12_i-c_t-0.9.v
  reg pmp_access_type_en; 
  always_ff@(posedge clk_i) begin
     if (rst_ni == 0) pmp_access_type_en <= 1'b0; // Assign a value on reset, so it will not propagate out being undefined.
     else pmp_access_type_en <= pmp_access_type_en;
  
end

========================================================
example13_i-c_t-0.9.v
  always @(posedge clk_i)
  begin
	if (rst_ni)
	  pmp_access_type_reg <= riscv::ACCESS_WRITE; 
  
end

========================================================
example14_i-c_t-0.9.v
//  assign pmp_access_type_en = 1'b1;
// FIX:
// XXX NOTE: SENSITIVE
  reg [63 : 0] pmp_ctrl_reg, pmp_ctrl_new; 
  assign pmp_ctrl_new = pmpcfg_i[63 : 0];
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_ctrl_en;
// Ensure that the security sensitive control register is assigned a value on reset.
// FIX:
//  assign pmp_ctrl_en = 1'b1; 
// FIX:
// XXX NOTE: SENSITIVE
  reg [63 : 0] pmp_addr_lsb_reg, pmp_addr_lsb_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
// 
========================================================
example15_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en; 
   
  reg [3:0] pmp_perm_reg, pmp_perm_new;
  reg pmp_perm_en; 
  
  reg [DMA_ADDR_WIDTH-1:0] source_addr_reg, source_addr_new;
  reg source_addr_en; 
  
  reg [DMA_ADDR_WIDTH-1:0] dest_addr_reg, dest_addr_new;
  reg dest_addr_en;  

  reg [DMA_COUNT_WIDTH-1:0] length_reg, length_new;
  reg length_en; 
  
  reg [DMA_COUNT_WIDTH-2:0] bytes_reg; 
  
 
========================================================
example16_i-c_t-0.9.v
  ////pmp_access_type_reg = riscv::ACCESS_WRITE;
  ////pmp_access_type_new = riscv::ACCESS_WRITE;

  reg[ DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  wire dma_ctrl_next_state_w; 
  wire pmp_addr_next_state_w;
  wire pmp_access_type_next_state_w; 
  wire valid_o_next_state_w; 

  reg [3:0] blocking_counter_reg, blocking_counter_new; 
  wire blocking_counter_next_state_w; 

  //// constants
  localparam PMP_BLOCK_SIZE = (2 ** ((4*$clog2(DATA_WID
========================================================
example17_i-c_t-0.9.v
  initial
    pmp_access_type_reg = riscv::ACCESS_WRITE;
    
  reg [7:0] pmp_cfg_reg; 
//  reg pmp_cfg_en;  

  //// IOs

  assign done_i = done_d; 

  //// Wires
  
  wire [DataBytesValid -1 :0] valid_ctrl; 
  wire [DataBytesValid -1 :0] valid; 
  wire enable; 
  
  //// Components

  wire [DMA_CTRL_WIDTH-1:0] ctlsignal; 
  wire [3:0] curr_ctrl; 

  assign curr_ctrl = dma_ctrl_reg[DMA_CTRL_WIDTH-1:DMA_CTRL_WIDTH
========================================================
example18_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en;

  //// Wires;
  
  wire [DATA_WIDTH-1:0] dma_ctrl_valid; 
  wire [DATA_WIDTH-1:0] dma_ctrl_ready; 

  reg [2-1:0] pmpaddr_setup; 

  wire need_pmp_config;
  wire [7:0] pmpcfg_match; 
  assign need_pmp_config = pmpaddr_i[16-1:0] != pmp_addr_reg[16-1:0]; 
  assign pmpcfg_match = (~need_pmp_config) & (pmp_addr_reg[15:8]) & (~pmp_addr_reg[7:0]);
  
  //// logic

========================================================
example19_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg; 
  reg pmp_cfg_en; 

  //// Transition Logic for the Registers. 
  localparam bool CLK_P_ENABLE = true;
  localparam bool CLS_N_ENABLE = false;

  assign start_d = start_i; 
  assign length_d = length_i;
  assign source_addr_lsb_d = source_addr_lsb_i; 
  assign source_addr_msb_d = source_addr_msb_i; 
  assign dest_addr_lsb_d = dest_addr_lsb_i; 
  assign dest_addr_msb_d = dest_addr_msb_i; 
  

========================================================
example0_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example1_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg
========================================================
example2_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example3_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 0) ? 2'b00 : 2'b01; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Control Logic
  always @(posedge clk_i) begin
    if (rst_ni == 0) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      valid_reg <= VALID_IDLE;
    
end

end

========================================================
example4_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg
========================================================
example5_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg
========================================================
example6_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 1'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example7_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example8_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires
  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] length_reg; 
  wire [DATA_WIDTH-1:0] start_reg; 
  wire [DATA_WIDTH-1:0] done_reg; 
  wire [DATA_WIDTH-1:
========================================================
example9_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  always @(*) begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    valid_new = valid_reg; 
  
end

========================================================
example10_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b00 : 2'b01;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg
========================================================
example11_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example12_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example13_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example14_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example15_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 1'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires
  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] length_reg; 
  wire [DATA_WIDTH-1:0] start_reg; 
  wire [DATA_WIDTH-1:0] done_reg; 

  wire [DATA_WIDTH-1:
========================================================
example16_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1
========================================================
example17_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_
========================================================
example18_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 0) ? 2'b00 : 2'b01;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start
========================================================
example19_i-d_t-0.1.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b0 : 1'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg
========================================================
example0_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [2:0] pmp_access_type_d; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic

  always @(*) begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    pmp_cfg_new = pmp_cfg_reg; 
    valid_new = valid_reg; 
 
end

========================================================
example1_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Combinational Logic

  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE;
end

end

========================================================
example2_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 1'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:
========================================================
example3_i-d_t-0.3.v
  reg pmp_access_type_en; 
  initial pmp_access_type_en = 0;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] data_out_reg, data_out_new; 
  reg data_out_en; 

  reg [DATA_WIDTH-1:0] data_in_reg, data_in_new; 
  reg data_in_en; 

  reg [
========================================================
example4_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b0 : pmp_access_type_en;
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Logic
  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <=
end

end

========================================================
example5_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = {1'b0, rst_ni};

  reg [7:0] pmp_region_reg, pmp_region_new; 
  reg pmp_region_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires
  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] length_reg; 
  wire [DATA_WIDTH-1:0] start_reg; 
  wire [DATA_WID
========================================================
example6_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b00 : 2'b11;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_
========================================================
example7_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = {1'b0, pmp_access_type_en[1]};

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// State Machine

  always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 1'b0;
      pmp_addr_reg <= 0;
      pmp_addr_en <= 1'b0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_en
end

end

========================================================
example8_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 0) ? 2'b0 : 1'b1;

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] dma_data_reg, dma_data_new; 
  reg dma_data_en; 

  reg [DATA_WIDTH-1:0] dma_data_valid_reg, dma_data_valid_new; 
  reg dma_data_valid_en; 

  reg [DATA_WIDTH-1:0] dma_data_done_
========================================================
example9_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] dma_ctrl_valid_reg, dma_ctrl_valid_new; 
  reg dma_ctrl_valid_en; 

  reg [DATA_WIDTH-1:0] dma_ctrl_done_reg, dma_ctrl_done_new; 
  reg dma_ctrl_done_en; 

  reg [DATA_WIDTH-1:0] dma_ctrl_start_reg, dma
========================================================
example10_i-d_t-0.3.v
  reg [2:0] pmp_access_type_en; 
  reg [2:0] pmp_access_type_en_new; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg
========================================================
example11_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = {1'b0, pmp_access_type_en[1]};

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Control
  always @(posedge clk_i) begin
    if (rst_ni == 1'b0) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      valid_reg <= VALID_IDLE;
    
end

end

========================================================
example12_i-d_t-0.3.v
  reg pmp_access_type_en; 
  always @(posedge clk_i) begin
    if (rst_ni == 0) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example13_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Logic

  always @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 1'b0) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 64'h0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      valid_reg <= VALID_IDLE;
    
end

end

========================================================
example14_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni) ? 2'b00 : 2'b01;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en;
========================================================
example15_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_reg = pmp_access_type_new;

  reg [3:0] pmp_region_reg, pmp_region_new;
  reg pmp_region_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] valid_d; 

  //// Combinational Logic

  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    valid_new = valid_reg; 
    pmp_addr_new = pmp_addr_reg;
    pmp_access_type_new = pmp_access_type_reg;
end

========================================================
example16_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b0) ? 2'b0 : 2'b1;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:
========================================================
example17_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg pmp_access_type_en_d; 
  reg [7:0] pmp_access_type_en_d_d; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH
========================================================
example18_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_access_type_en_reg; 
  reg [7:0] pmp_access_type_en_new; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_
========================================================
example19_i-d_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 

  //// Combinational Logic
  always @(*) begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    pmp_cfg_new = pmp_cfg_reg; 
    valid_new = valid_reg; 
  
end

========================================================
example0_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  
  reg [VALID_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  
  //// Logic
  wire [DATA_WIDTH-1:0] source_addr; 
  wire [DATA_WIDTH-1:0] dest_addr; 
  wire [DATA_WIDTH-1:0] source_addr_reg_lsb;
  wire [DATA_WIDTH-1:0] source_addr_reg_msb;
  wire [DATA_WIDTH-1:0] dest_addr_reg_lsb;
  wire [DATA_WIDTH-1:0] dest_addr_reg_msb;
  wire [DATA_WIDTH-1
========================================================
example1_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; // default value of 0 on reset
  always @ (posedge clk_i) begin
    if (rst_ni == 1'b0) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example2_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni ? 0 : pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en;
========================================================
example3_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = 2'b11; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new;
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new;
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new;
  reg length_en; 

  reg [DATA_WIDTH-1:0] start_reg,
========================================================
example4_i-d_t-0.5.v
  reg pmp_access_type_en; 
  initial begin
    pmp_access_type_en = 0;
    pmp_access_type_reg = 0;
    pmp_access_type_new = 0;
  
end

========================================================
example5_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en;

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] load_data_reg, load_data_new; 
  reg load_data_en; 

  reg [DATA_WIDTH-1:0] store_data_reg, store_data_new; 
  reg store_data_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg
========================================================
example6_i-d_t-0.5.v
  reg pmp_access_type_en; 
  initial pmp_access_type_en = 0;

  reg [7:0] pmp_cfg_idx_reg, pmp_cfg_idx_new;
  reg pmp_cfg_idx_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Wires

  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 

  wire [DATA_WIDTH-1:0] source_addr_new; 
  wire [DATA_WIDTH-1:0] dest_addr_new; 

  wire [DATA_WIDTH-
========================================================
example7_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_reg = (rst_ni) ? 0 : pmp_access_type_new;
  assign pmp_addr_reg = (rst_ni) ? 0 : pmp_addr_new;
  assign dma_ctrl_reg = (rst_ni) ? 0 : dma_ctrl_new;

  //// Internal wires
  wire [DATA_WIDTH-1:0] source_addr_reg;
  wire [DATA_WIDTH-1:0] dest_addr_reg;
  wire [DATA_WIDTH-1:0] length_reg;
  wire [DATA_WIDTH-1:0] done_reg;
  wire [DATA_WIDTH-1:0] start_reg;

  //// Logic
========================================================
example8_i-d_t-0.5.v
  reg [3:0] pmp_access_type_en; 
  assign pmp_access_type_reg = (pmp_access_type_en) ? pmp_access_type_new : 0;
  assign pmp_access_type_en = (rst_ni == 0) ? 0 : 1;

  //// Counters
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_count, dma_ctrl_count_new; 
  reg dma_ctrl_count_en; 

  reg [DATA_WIDTH-1:0] length_count, length_count_new; 
  reg length_count_en; 
  
  //// Control
  always @(posedge clk_i) begin
    if (rst_ni == 0) begin
     
end

end

========================================================
example9_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  initial pmp_access_type_en = 'b0;

  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] length_reg; 
  wire [DATA_WIDTH-1:0] start_reg; 
  wire [DATA_WIDTH-1:0] done_reg; 
  
  //// Combinational logic

  assign source_addr_reg = (source_addr_msb_d << DATA_WIDTH) | source_addr_lsb_d;
  assign dest_addr_reg = (dest_addr_msb_d << DATA_W
========================================================
example10_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_en = ~rst_ni ? 2'b0 : pmp_access_type_en;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] length_cnt_reg, length_cnt_new; 
  reg length_cnt_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_cnt_reg, source_addr_lsb_cnt_new; 
  reg source_addr_lsb_cnt_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_cnt_
========================================================
example11_i-d_t-0.5.v
  reg pmp_access_type_en; 
  initial pmp_access_type_en = 0;

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [riscv::PMP_NREG-1:0] pmp_access_reg, pmp_access_new;
// Assign 0 to register when reset is low.
// FIX:
  reg [riscv::PMP_NREG-1:0] pmp_access_reg, pmp_access_new;
  initial pmp_access_reg = 0;
  initial pmp_access_new = 0;
  
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  reg [DATA_WIDTH-1:0] valid_d
========================================================
example12_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en;
  always_ff @(posedge clk_i) begin
    if(!rst_ni) begin
      pmp_access_type_en <= 2'b0;
    
end

end

========================================================
example13_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Combinational Logic
  assign valid_o = valid_reg; 

  always_comb begin
    dma_ctrl_new = dma_ctrl_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_new = pmp_access_type_reg; 
    valid_new = valid_reg; 

    if (rst_ni == 1'b0) begin
      dma_ctrl_new = CTRL_IDLE; 
      pmp_addr_new = 64'h0; 
      pmp_access_type_new = riscv
end

end

========================================================
example14_i-d_t-0.5.v
  reg pmp_access_type_en; 
  always @(posedge clk_i) begin
    if(rst_ni==0) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example15_i-d_t-0.5.v
  reg [riscv::PMP_ACCESS_WIDTH-1:0] pmp_access_type_en; 
  assign pmp_access_type_en = riscv::ACCESS_WRITE;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-
========================================================
example16_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_new = pmp_access_type_reg;
  assign pmp_access_type_en = (pmp_access_type_new != pmp_access_type_reg) ? 2'b11 : 2'b00;

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en;
  reg [DATA_WIDTH-1:0] dma_valid_mask; 

  //// Control FSM
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if(!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE
end

end

========================================================
example17_i-d_t-0.5.v
  reg pmp_access_type_en;
  always @(negedge rst_ni)
    begin
      pmp_access_type_en <= 0;
    
end

========================================================
example18_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// Control State Machine
  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_valid_reg <= VALID_IDLE;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_addr_reg <= 0;
      dma_ctrl_en <= 0;
      dma_valid_en <= 0;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
end

end

========================================================
example19_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Control
  always @ (posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_en <= 0; 
      pmp_addr_reg <= 0;
      pmp_addr_en <= 0;
      pmp_access_type_reg <= 0;
//      pmp_access_type_en <= 0;
      pmp_access_type_en <= 2'b0;
      valid_reg <= VALID_IDLE; 
      valid_en <= 0; 

end

end

========================================================
example0_i-d_t-0.7.v
  reg [2:0] pmp_access_type_en;  // 3-bit register
  assign pmp_access_type_en = pmp_addr_en;

  reg [3:0] pmp_region_reg, pmp_region_new;
  reg pmp_region_en; 
  // regs for status_o
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_status, dma_ctrl_status_new; 
  reg dma_ctrl_status_en;
  // regs for valid_o
  reg [DMA_CTRL_WIDTH:0] valid_reg, valid_new;
  reg valid_en;

  //// Code
  // initialize registers
  initial begin
    dma_ctrl_reg <= CTRL_IDLE;

end

========================================================
example1_i-d_t-0.7.v
//https://stackoverflow.com/questions/31036249/why-are-some-reg-variables-in-verilog-initialized-while-others-arent

  reg [3:0] pmp_reg_no_reg, pmp_reg_no_new; 
  reg pmp_reg_no_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg source_addr_en; 

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg dest_addr_en; 

  reg [DATA_WIDTH-1:0
========================================================
example2_i-d_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  assign pmp_access_type_reg = pmp_access_type_en ? pmp_access_type_new : 0;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new;
  reg valid_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new;
  reg source_addr_en;

  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new;
  reg dest_addr_en;
  
  //// Wire

  wire [DATA_WIDTH-1:0] addr_lsb_w;
  wire [DATA_WIDTH-1:0] addr_msb_w;

========================================================
example3_i-d_t-0.7.v
  reg [2:0] pmp_access_type_en;

  reg [7:0] pmp_access_reg, pmp_access_new; 
  reg pmp_access_en;

  reg [7:0] pmp_cfg_reg [16-1:0], pmp_cfg_new [16-1:0]; 
  reg [7:0] pmp_cfg_en [16-1:0]; 

  
  //// Global Variables
  reg [DATA_WIDTH-1:0] dma_src_addr; 
  reg [DATA_WIDTH-1:0] dma_dest_addr; 
  reg [DATA_WIDTH-1:0] dma_length; 
  reg [DATA_WIDTH-1:0] dma_count; 
========================================================
example4_i-d_t-0.7.v
  reg pmp_access_type_en; 
  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example5_i-d_t-0.7.v
  reg pmp_access_type_en;
  initial pmp_access_type_en = 0;

  //// Wires

  wire [DATA_WIDTH-1:0] length_sub_one_w; 
  wire length_sub_one_w_valid;
  wire [DATA_WIDTH-1:0] length_sub_one_w_next;
  wire [DATA_WIDTH-1:0] length_add_one_w; 
  wire length_add_one_w_valid;
  wire [DATA_WIDTH-1:0] length_add_one_w_next;
  wire [DATA_WIDTH-1:0] source_addr_msb_add_one_w; 
  wire [DATA_WIDTH-1:0] source_addr_lsb
========================================================
example6_i-d_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_en_d; 

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  

  reg dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  
  //// Safety Registers
  wire [DATA_WIDTH-1:0] done_q; 

  //// Wire Delays
  wire [DATA_WIDTH-1:0] start_w; 
  wire [DATA_WIDTH-1:0] length_w;
  wire [DATA_WIDTH-1:0] source_addr_lsb_w; 
========================================================
example7_i-d_t-0.7.v
  always @(posedge clk_i, negedge rst_ni) begin
    if (rst_ni) begin
      pmp_access_type_reg <= 'b0;
    
end

end

========================================================
example8_i-d_t-0.7.v
  always_ff @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example9_i-d_t-0.7.v
  reg [2:0] pmp_access_type_en; 
  reg pmp_access_type_en_reg; 

  
  //// Control
  always @(*) begin
    dma_ctrl_en  = 0; 
    dma_ctrl_new = dma_ctrl_reg; 
    case (dma_ctrl_reg)

      CTRL_IDLE: begin
        if (start_i != 0) begin
          dma_ctrl_new = CTRL_CHECK_LOAD; 
        
end

end

end

========================================================
example10_i-d_t-0.7.v
  reg pmp_access_type_en; 
  initial pmp_access_type_en = 0;

  //// Wire

  wire [7:0] [16-1:0] pmpcfg_d;   
  wire [16-1:0][53:0]     pmpaddr_d;  
  wire [DATA_WIDTH-1:0] valid_d;
  wire [DATA_WIDTH-1:0] done_d;

  //// Instances

  // DMA Controller
  dma_controller #(.DATA_WIDTH(DATA_WIDTH), .ADDR_WIDTH(ADDR_WIDTH), .PMP_WIDTH(PMP_WIDTH), .PMP_NUM(PMP_NUM))
    dma_controller(
    .clk_i
========================================================
example11_i-d_t-0.7.v
  reg [2:0] pmp_access_type_en; 
  assign pmp_access_type_en = {1'b0, rst_ni};

  reg [15:0] pmp_access_size_reg, pmp_access_size_new; // riscv::ACCESS_32 or riscv::ACCESS_64
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_size_en;
// Assign 0 to register when reset is low.
// FIX:
  reg [2:0] pmp_access_size_en;
  assign pmp_access_size_en = {1'b0, rst_ni};

  reg [7:0] pmp_access_region_reg, pmp_access_region_new;
  reg
========================================================
example12_i-d_t-0.7.v
  assign pmp_access_type_new = (reset_n == 0)? 0 : (we_flag == 1) ? riscv::ACCESS_WRITE : riscv::ACCESS_READ;

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new
========================================================
example13_i-d_t-0.7.v
  reg [63:0] pmpcfg_reg, pmpcfg_new;
  reg [7:0] [16-1:0] pmpcfg_en; 

  //// Status
  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  //// State Machine
  localparam [DMA_STATE_WIDTH-1:0] STATE_IDLE = 'd0; 
  localparam [DMA_STATE_WIDTH-1:0] STATE_WORKING = 'd1; 
  localparam [DMA_STATE_WIDTH-1:0] STATE_DONE = 'd2; 
  localparam [DMA_STATE_WIDTH-1:0] STATE
========================================================
example14_i-d_t-0.7.v
//  assign pmp_access_type_reg = (rst_ni == 1'b0) ? 0 : pmp_access_type_new;
  reg pmp_access_type_en; 
  assign pmp_access_type_reg = pmp_access_type_new;

  reg [DATA_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 

  reg [DATA_WIDTH-1:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Internal wires

  wire [DATA_WIDTH-1:0] next_source_addr; 
  wire [DATA_WIDTH-1:0] next_dest_addr; 

 
========================================================
example15_i-d_t-0.7.v
  reg [2:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new;
  reg valid_en; 

  wire [DATA_WIDTH-1:0]  source_addr;
  wire [DATA_WIDTH-1:0]  dest_addr; 
  wire [DATA_WIDTH-1:0]  data_i;
  wire [DATA_WIDTH-1:0]  data_o;

  wire rst_n;
  assign rst_n = !rst_ni;

  //// FSM
  // 
  // 
  //
  //
  //
  //
  //
  //
  //
  //
  //
  //
  //
  //
  //
========================================================
example16_i-d_t-0.7.v
  always @ (posedge clk_i or negedge rst_ni) begin
    if(~rst_ni) begin
      pmp_access_type_reg <= 0;
    
end

end

========================================================
example17_i-d_t-0.7.v
  reg [2:0] pmp_access_type_en;

  reg [DMA_VALID_WIDTH-1:0] dma_valid_reg; 
  reg [5:0] state_d; 

  //// Local Wires

  wire dma_ctrl_assigned; 
  wire pmp_access_type_assigned; 
  wire pmp_addr_assigned; 

  wire start_i_assigned; 
  wire length_i_assigned;
  wire done_i_assigned; 

  wire [DATA_WIDTH-1:0] source_addr_lsb_i_assigned; 
  wire [DATA_WIDTH-1:0] source_addr_msb_i_assigned; 
  wire [DATA_WIDTH-1:0
========================================================
example18_i-d_t-0.7.v
  reg rst_n_int;
  initial begin
    rst_n_int = ~ rst_ni;
  
end

========================================================
example19_i-d_t-0.7.v
  reg pmp_access_type_en;
  initial pmp_access_type_reg = riscv::ACCESS_WRITE;
  initial pmp_access_type_new = riscv::ACCESS_WRITE;
  
  //// Control Logic
  always @(posedge clk_i) begin
    if (rst_ni == '0) begin 
      dma_ctrl_reg <= CTRL_IDLE;  
      pmp_addr_reg <= 'd0; 
      pmp_access_type_reg <= riscv::ACCESS_READ; 
      source_addr_msb_d <= 'd0;
      source_addr_lsb_d <= 'd0; 
      dest_addr_msb_d <= 'd0;
      dest_addr_lsb_d <= 'd
end

end

========================================================
example0_i-d_t-0.9.v
  reg pmp_access_type_en = 0; 

  reg [2:0] pmp_addr_layer = 0; 


  //// Wires

  wire [DATA_WIDTH-1:0] source_addr;
  wire [DATA_WIDTH-1:0] dest_addr; 

  wire start_en; 


  //// 
  //// Implementation 

  always @(posedge clk_i) begin 
    if (rst_ni == RESET_ACTIVE) begin 
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_en <= 'b0;

      pmp_addr_reg <= '0; 
      pmp_addr_en <= 'b0;

      pmp_access_type_reg <= riscv::ACCESS_
end

end

========================================================
example1_i-d_t-0.9.v
  always @ (posedge clk_i, negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example2_i-d_t-0.9.v
  reg [1:0] pmp_access_type_en;
  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  


  //// Outputs
  // valid_o is always asserted
  assign valid_o = done_d & done_i; 

  // at always block
  always @ ( posedge clk_i ) begin
    if ( rst_ni == 1'b0 ) begin
      valid_o <= VALID_IDLE;
      start_d <= 0; 
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0
end

end

========================================================
example3_i-d_t-0.9.v
  wire rst_ni_r = rst_ni | clk_i;
  reg pmp_access_type_en; 
  initial pmp_access_type_en = 0;
  always @(posedge clk_i) begin: pmp_access_type_en
    if (rst_ni_r) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example4_i-d_t-0.9.v
//  assign pmp_access_type_en = (~rst_ni)&pmp_access_type_en_gen 
//  		| (~rst_ni)&(~pmp_access_type_en_gen);


  LC_FIFO #(
                 .DATA_WIDTH(8)
                )mem_src_fifo (
                  .rst_ni          (rst_ni ),
                  .clk_i           (clk_i ),
                  .rd_data_i       (mem_rd_data_logic ),
                  .rd_data_ready_i (1'b1     ),
                  .wr_data_i       (source_addr_lsb_d(7:0)), // local parameter CHANNEL_WIDTH must be set to 8 to match CHANNEL_WIDTH in
========================================================
example5_i-d_t-0.9.v
  reg[2:0] pmp_access_type_en;
  assign pmp_access_type_new = riscv::ACCESS_WRITE;
  reg pmp_access_empty; 
  reg pmp_access_allow; 

  //// Output Wire
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_o; 
  wire [63:0] pmp_addr_o; // Word-aligned addresses for PMP
  wire [2:0] pmp_access_control_o;
  wire [RISCV_PMP_ACCESS_REGS-1:0] pmp_access_type_o; 
  wire pmp_access_empty_o; 
  wire pmp_access_allow_o;  
 
  // Forwarding signlas

========================================================
example6_i-d_t-0.9.v
//  always @ (negedge rst_ni) pmp_access_type_en = 0;
  reg [7:0] pmp_access_type_en;
  always @ (negedge rst_ni) pmp_access_type_en = 8'b0;
  
  
  reg [DATA_WIDTH-1:0] dma_valid_reg, dma_valid_new; 
  reg dma_valid_en; 
  
  
  //// Combinational logic
  
  always @ (posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 1'b0) begin 
      dma_ctrl_reg <= CTRL_IDLE; 
      valid_o <= VALID_IDLE;
      dma_valid_reg <=
end

end

========================================================
example7_i-d_t-0.9.v
  reg [1:0] pmp_access_type_en;
  always @(posedge clk_i) begin
    if (~rst_ni) begin
       pmp_access_type_en <= 2'b0;
    
end

end

========================================================
example8_i-d_t-0.9.v
  assign pmp_access_type_new = (rst_ni) ? 0 : pmp_access_type_reg;
  assign pmp_access_type_en = riscv::pmp_access_type_en;


  reg [32-1:0] control_reg, control_new; 
  reg control_en;
  reg control_en_for_pmp;

  reg next_state; 
  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 

  reg load_done_d;          // load done for current access
  reg load_done_d1;         // load done for next access
  reg store_done_d;         // store done for current access
  reg store_done_d1;        // store done for next access


  //// Wires
  
========================================================
example9_i-d_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  assign valid_o = pmp_access_type_en ? pmp_access_type_reg : 'd0;

  //// State Machines 
  
  always @(posedge clk_i) begin
    if (rst_ni == 1'b0) begin
        dma_ctrl_en        <= 1'b0;
        dma_ctrl_reg       <= 'd0;  
        dma_ctrl_new       <= 'd0;  
    
end

end

========================================================
example10_i-d_t-0.9.v
  reg logic pmp_access_type_en; 
  assign pmp_access_type_en = 1'b0;
  always @(posedge clk_i) begin 
    if(~rst_ni) begin 
      pmp_access_type_en <= 1'b0; 
    
end

end

========================================================
example11_i-d_t-0.9.v
  reg [1:0] pmp_access_type_en;
  assign pmp_access_type_en = (~rst_ni) | (2'b1<<1);
  
  //// Always block
 
  always @* begin

    if (rst_ni == 0) begin

        start_d <= 0;
        source_addr_lsb_d <= 0;
        source_addr_msb_d <= 0;
        dest_addr_lsb_d <= 0;
        dest_addr_msb_d <= 0;
        done_d <= 0;
        pmp_addr_reg <= 0;
        
        pmp_access_type_reg <= riscv::ACCESS_READ;

        dma_ctrl_new <= CTRL_IDLE;

      
end

end

========================================================
example12_i-d_t-0.9.v
  reg[3:0] pmp_access_type_en;
  assign pmp_access_type_en = rst_ni ? 0 : pmp_access_type_en + 1; 

 
   reg [DMA_VALID_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 
  //// State 
  typedef enum logic [3:0] {
    STATE_IDLE = 4'h0, // Keep value small since automatic state encoding requires it. 
    STATE_CHECK_LOAD,
    STATE_START_LOAD,
    STATE_LOAD,
    STATE_CHECK_STORE,
    STATE_START_STORE,
    STATE_STORE,
    STATE_DONE
  } state_t;
  reg state, state_new; 

========================================================
example13_i-d_t-0.9.v
  assign pmp_access_type_en = (~rst_ni);
  reg[1:0] pmp_access_type_reg, pmp_access_type_new;

  logic one_cycle_done;


  //// Default Values
  
  assign valid_o = VALID_IDLE; 

  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      start_d <= 'b0;    
      length_d <= 'b0;
      source_addr_lsb_d <= 'b0;  
      source_addr_msb_d <= 'b0; 
      dest_addr_lsb_d <= 'b0;  
      dest_addr_msb_d <= 'b0; 
      done_d <= 'b
end

end

========================================================
example14_i-d_t-0.9.v
  reg rst_n_int;  
  always @ (posedge clk_i or negedge rst_ni)
  begin
    if (!rst_ni)
      rst_n_int <= 1'b0;
    else
      rst_n_int <= 1'b1;
  
end

========================================================
example15_i-d_t-0.9.v
  reg [1:0] pmp_access_type_en; 
// ^^^ was reg

  //// Signals
  wire [PMP_LI_WIDTH-1:0] pmp_li_o; // PMP range identifier for addresses in DMA controller's address space.

  //// Module Instance


  riscv::pmp_logic pmp_logic_i0
  (# .CLK_I(clk_i),
  .RST_NI(rst_ni), 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  .PMP_ADDR_I(pmp_addr_reg),     
// Assign 0 to register when reset is low.
// FIX:
  .PMP_ADDR_I({pmp_addr_reg, 2'b0}
========================================================
example16_i-d_t-0.9.v
  reg [2:0] pmp_access_type_en;
  assign pmp_access_type_en = {'b0, pmp_access_type_en};

  reg [3:0] pmp_region_reg, pmp_region_new;

  reg [DATA_WIDTH-1:0] valid_reg, valid_new, valid_en; 

  //// Internal variables

  wire [15*DMA_DATA_WIDTH-1:0] data2_o; 
  
  wire [16-1:0] pmpaddr_new; // new pmpaddr bus
  wire [16-1:0] pmpaddr_sa; // source address
  wire [16-1:0] pmpaddr_da; // destination address
  wire [16-1:0] pmpaddr_next
========================================================
example17_i-d_t-0.9.v
  reg pmp_access_type_en; 
  assign done_o = done_d; 
  assign valid_o = done_d; 
  
  //// Logic
  always @* begin 
  case (dma_ctrl_reg)
  
  CTRL_ABORT: begin 
    dma_ctrl_new = CTRL_ABORT;
    pmp_access_type_new = pmp_access_type_reg; 
    pmp_addr_new = pmp_addr_reg; 
    pmp_access_type_en = 1'b0; 
    pmp_addr_en = 1'b0; 
  
end

end

========================================================
example18_i-d_t-0.9.v
  reg [1:0] pmp_access_type_reg, pmp_access_type_new;
  reg [1:0] pmp_access_type_en; 


  reg [7:0] pmp_cfg_id_reg, pmp_cfg_id_new;
  reg pmp_cfg_id_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_external_en;
// Assign 0 to register when reset is low.
// FIX:
  logic pmp_access_external_en = 1'b0;

  logic [53:0] pmp_napot_new;
  logic [53:0] pmp_tor_new; 

  //// Blocks
  // Registers
  synchronized_reg #(_clog2
========================================================
example19_i-d_t-0.9.v
  reg         pmp_access_type_en;
  integer i;
  initial
    begin
  //    pmp_access_type_reg = riscv::ACCESS_WRITE;
  //    pmp_access_type_new = riscv::ACCESS_WRITE;
  //    pmp_access_type_en  = 'b0;
      pmp_access_type_reg = 'b0;
      pmp_access_type_new = 'b0;
      // Assign 0 to register when reset is low.
      pmp_access_type_en  = 'b0;
      // Clear output.
      valid_o            = 'b0000;
    
end

========================================================
example0_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.5.v
  reg pmp_access_type_en; 
  reg [3:0] pmp_access_type_en_count; 
  always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en_count <= 0;
        
end

end

========================================================
example7_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.7.v
  reg pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example7_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.7.v
  reg pmp_access_type_en;
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
        pmp_access_type_en <= 0;
    
end

end

========================================================
example11_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.7.v
  reg pmp_access_type_en;
  always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 1;
        
end

end

========================================================
example14_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.9.v
  reg [31:0] pmp_access_type_en;
  always @ (posedge clk_i or negedge rst_ni) begin
  if (!rst_ni) pmp_access_type_en <= 0;
  
end

========================================================
example14_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.9.v
  reg pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
    pmp_access_type_en <= 0;
  
end

========================================================
example19_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
