example0_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; 
  reg pmp_addr_valid_en; 

  reg [63:0] pmp_addr_valid_reg_reg, pmp_addr_valid_new_reg; 
  reg pmp_addr_valid_en_reg; 

  reg [63:0] pmp_addr_valid_reg_reg_reg, pmp_addr_valid_new_reg_reg; 
  reg pmp_addr_valid_en_reg_reg; 

  reg [63:0] pmp_addr_valid_reg_reg_reg_reg, pmp_addr_valid_new_reg_reg_reg; 
  reg pmp_addr_
========================================================
example1_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_msb_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new_msb, pmp_addr_reg_msb_new_lsb;
  reg [63:0] pmp_addr_reg_lsb_new_ls
========================================================
example2_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2; 
// BUG:
//  reg pmp_addr_cfg_en_2; 
// FIX:
  reg pmp_addr
========================================================
example3_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en; 

  reg [63:0] pmp_addr_valid_reg_reg, pmp_addr_valid_new_reg;
  reg pmp_addr_valid_en_reg; 

  reg [63:0] pmp_addr_valid_reg_reg_reg, pmp_addr_valid_new_reg_reg;
  reg pmp_addr_valid_en_reg_reg; 

  reg [63:0] pmp_addr_valid_reg_reg_reg_reg, pmp_addr_valid_new_reg_reg_reg;
  reg pmp_addr_valid_en_
========================================================
example4_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_msb_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new_msb, pmp_addr_reg_msb_new_lsb;
  reg [63:0] pmp_addr_reg_lsb_new_ms
========================================================
example5_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2; 
// BUG:
//  reg pmp_addr_cfg_en_2; 
// FIX:
  reg pmp_addr
========================================================
example6_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_lsb, pmp_addr_cfg_new_lsb; 
// BUG:
//  reg pmp_addr_cfg_en_lsb; 
// FIX:
  reg p
========================================================
example7_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_msb_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new_msb, pmp_addr_reg_msb_new_lsb;
  reg [63:0] pmp_addr_reg_lsb_new_ls
========================================================
example8_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb; 
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new; 
  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_msb_new_msb; 
  reg [63:0] pmp_addr_reg_lsb_new_msb, pmp_addr_reg_msb_new_lsb; 
  reg [63:0] pmp_addr_reg_ls
========================================================
example9_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_msb_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new_msb, pmp_addr_reg_msb_new_lsb;
  reg [63:0] pmp_addr_reg_lsb_new_ms
========================================================
example10_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2; 
// BUG:
//  reg pmp_addr_cfg_en_2; 
// FIX:
  reg pmp_addr
========================================================
example11_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2; 
// BUG:
//  reg pmp_addr_cfg_en_2; 
// FIX:
  reg pmp_addr
========================================================
example12_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_msb_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new_msb, pmp_addr_reg_msb_new_lsb;
  reg [63:0] pmp_addr_reg_lsb_new_ls
========================================================
example13_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2; 
// BUG:
//  reg pmp_addr_cfg_en_2; 
// FIX:
  reg pmp_addr
========================================================
example14_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new; 
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2; 
// BUG:
//  reg pmp_addr_cfg_en_2; 
// FIX:
  reg pmp_addr
========================================================
example15_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en;  

  reg [63:0] pmp_addr_valid_reg_reg, pmp_addr_valid_new_reg;
  reg pmp_addr_valid_en_reg;  

  reg [63:0] pmp_addr_valid_reg_reg_reg, pmp_addr_valid_new_reg_reg;
  reg pmp_addr_valid_en_reg_reg;  

  reg [63:0] pmp_addr_valid_reg_reg_reg_reg, pmp_addr_valid_new_reg_reg_reg;
  reg pmp_addr_valid_en_
========================================================
example16_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [16-1:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg [16-1:0] pmp_addr_new_lsb, pmp_addr_new_msb; 
  reg [16-1:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new; 

  reg [16-1:0] pmp_addr_reg_lsb_new_next, pmp_addr_reg_
========================================================
example17_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [16:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg [16:0] pmp_addr_new_lsb, pmp_addr_new_msb; 

  reg [16:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb; 
  reg [16:0] pmp_cfg_new_lsb, pmp_cfg_new_msb; 

  reg [16:0] pmp_addr
========================================================
example18_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_reg; 
  reg pmp_addr_en_reg; 

  reg [63:0] pmp_addr_reg_reg_reg; 
  reg pmp_addr_en_reg_reg; 

  reg [63:0] pmp_addr_reg_reg_reg_reg; 
  reg pmp_addr_en_reg_reg_reg; 

  reg [63:0] pmp_addr_reg_reg_reg_reg_reg; 
  reg pmp_addr_en_reg_reg_reg_reg; 

  reg [63:0] pmp_addr_reg_reg_reg_reg_reg_reg; 
  reg pmp_addr_en_reg
========================================================
example19_i-a_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_reg; 

  reg [63:0] pmp_addr_reg_en_new_reg; 

  reg [63:0] pmp_addr_reg_en_new_reg_new; 
  reg [63:0] pmp_addr_reg_en_new_reg_new_reg; 

  reg [63:0] pmp_addr_reg_en_new_reg_new_reg_new; 
  reg [63:0] pmp_addr_reg_en_new_reg_new_reg_new_
========================================================
example0_i-a_t-0.3.v
  reg pmp_access_type_en_d; 

  reg [DATA_WIDTH-1:0] valid_d; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] start_r; 
  wire [DATA_WIDTH-1:0] length_r;
  wire [DATA_WIDTH-1:0] source_addr_lsb_r; 
  wire [DATA_WIDTH-1:0] source_addr_msb_r; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_r; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_r; 
  wire [DATA_WIDTH-1:0] done_r; 

  wire [DMA_
========================================================
example1_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_cfg_reg_new;
  reg pmp_cfg_en_reg_new; 

  reg [7:0] pmp_addr_reg_new;
  reg pmp_addr_en_reg_new; 

  reg [7:0] pmp_access_type_reg_new;
  reg pmp_access_type_en_reg_new; 

  reg [7:0] pmp_cfg_reg_new_new;
  reg pmp_cfg_en_
========================================================
example2_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en; 

  reg [63:0] pmp_addr_valid_reg_reg, pmp_addr_valid_new_reg;
  reg pmp_addr_valid_en_reg; 

  reg [63:0] pmp_addr_valid_reg_reg_reg, pmp_addr_valid_new_reg_reg;
  reg pmp_addr_valid_en_reg_reg; 

  reg [63:0] pmp_addr_valid_reg_reg_reg_reg, pmp_addr_valid_new_reg_reg_reg;
  reg pmp_addr_valid_en_
========================================================
example3_i-a_t-0.3.v
  reg pmp_access_type_en_reg;
  reg [63:0] pmp_addr_reg_reg;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_reg; 
  reg dma_ctrl_en_reg; 

  reg [63:0] pmp_addr_reg_reg_reg;
  reg pmp_access_type_reg_reg;
  reg pmp_access_type_en_reg_reg;

  reg [63:0] pmp_addr_reg_reg_reg_reg;
  reg pmp_access_type_reg_reg_reg;
  reg pmp_access_type_en_reg_reg_reg;

  reg [63:0] pmp_addr_reg_reg_reg_reg_reg;

========================================================
example4_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_msb_reg, pmp_addr_msb_new; 
  reg pmp_addr_msb_en; 

  reg [7:0] pmp_addr_lsb_reg, pmp_addr_lsb_new; 
  reg pmp_addr_lsb_en; 

  reg [7:0] pmp_data_reg, pmp_data_new; 
  reg pmp_data_en; 

  reg [7:0] pmp_wdata_reg, pmp_wdata_new; 
  reg
========================================================
example5_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] start_new; 
  wire [DATA_WIDTH-1:0] length_new;
  wire [DATA_WIDTH-1:0] source_addr_lsb_new; 
  wire [DATA_WIDTH-1:0] source_addr_msb_new; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_new; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_new; 
  wire [DATA_WIDTH-1:0] done_new; 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new
========================================================
example6_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en; 
  
  reg [63:0] pmp_mask_reg, pmp_mask_new;
  reg pmp_mask_en; 

  reg [63:0] pmp_addr_reg_reg, pmp_addr_reg_new;
  reg pmp_addr_reg_en; 

  reg [63:0] pmp_data_reg_reg, pmp_data_reg_new;
  reg pmp_data_reg_en; 

  reg [63:0] pmp_mask_reg_reg, pmp_mask_reg_new;
  reg pmp_mask_reg_en; 
========================================================
example7_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 

  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_new; 
  reg dma_ctrl_en_new_new; 

  reg [63:0] pmp_addr_reg_new_new;
  reg pmp_addr_en_new_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_new_new; 
  reg
========================================================
example8_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 
  
  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en;  

  reg [63:0] pmp_addr_valid_reg_next;
  reg pmp_addr_valid_en_next;  

  reg [63:0] pmp_addr_valid_reg_next_next;
  reg pmp_addr_valid_en_next_next;  

  reg [63:0] pmp_addr_valid_reg_next_next_next;
  reg pmp_addr_valid_en_next_next_next;  

  reg [63:0] pmp_addr_valid_reg_next_next_next_next;
  reg pmp
========================================================
example9_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 
  reg pmp_access_type_en_new; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en;  

  reg [63:0] pmp_addr_valid_reg_next; 
  reg [63:0] pmp_addr_reg_next; 

  reg [63:0] pmp_addr_reg_next_next; 
  reg [63:0] pmp_addr_valid_reg_next_next; 
  reg [63:0] pmp_addr_valid_reg_next_next_next; 

  reg [63:0] pmp_addr_reg_next_next_next; 
  reg [63
========================================================
example10_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en;

  reg [63:0] pmp_addr_valid_reg_next, pmp_addr_valid_new_next;
  reg pmp_addr_valid_en_next;

  reg [63:0] pmp_addr_valid_reg_next_next, pmp_addr_valid_new_next_next;
  reg pmp_addr_valid_en_next_next;

  reg [63:0] pmp_addr_valid_reg_next_next_next, pmp_addr_valid_new_next_next_next;
  reg pmp_addr_valid_en_
========================================================
example11_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 
  wire [DATA_WIDTH-1:0] length_reg; 
  wire [DATA_WIDTH-1:0] start_reg; 
  wire [DATA_WIDTH-1:0] done_reg; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg; 
  wire dma_ctrl_en; 
  wire [63:0] pmp_addr_reg; 
  wire pmp_addr_en; 
  wire [63:0] pmp_addr_reg_
========================================================
example12_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg [63:0] pmp_addr_reg_next; 
  reg [7:0] pmp_cfg_reg_next; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next_next; 
  reg [63:0] pmp_addr_reg_next_next; 
  reg [7:0] pmp_cfg_reg
========================================================
example13_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_en_lsb, pmp_addr_en_msb; 

  reg [7:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [7:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg pmp_addr_en_lsb_new, p
========================================================
example14_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 
  reg [63:0] pmp_addr_reg_reg; 
  reg pmp_addr_en_reg; 
  reg [63:0] pmp_addr_reg_new; 
  reg pmp_addr_en_new; 

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [7:0] [16-1:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [7:0] [16-1:0] pmpaddr_reg_reg; 
  reg pmpaddr_en_reg; 
  reg [7:0] [16-
========================================================
example15_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_msb_reg, pmp_addr_msb_new; 
  reg pmp_addr_msb_en; 

  reg [7:0] pmp_addr_lsb_reg, pmp_addr_lsb_new; 
  reg pmp_addr_lsb_en; 

  reg [7:0] pmp_cfg_msb_reg, pmp_cfg_msb_new; 
  reg pmp_cfg_msb_en; 

  reg [7:0] pmp_cfg_lsb_reg, pmp_cfg
========================================================
example16_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_new; 

  reg [DATA_WIDTH-1:0] start_reg; 
  reg start_new; 
  reg [DATA_WIDTH-1:0] length_reg; 
  reg length_new; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg; 
  reg source_addr_lsb_new; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg; 
  reg source_addr_msb_new; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg; 
  reg dest_addr
========================================================
example17_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; 
  reg pmp_addr_valid_en; 

  reg [63:0] pmp_addr_valid_reg_next; 

  reg [63:0] pmp_addr_reg_next; 
  reg [63:0] pmp_addr_reg_next_next; 

  reg [63:0] pmp_access_type_reg_next; 
  reg [63:0] pmp_access_type_reg_next_next; 

  reg [63:0] pmp_addr_valid_reg_next_next; 

  reg [63:0] pmp_addr_reg_next_next_next
========================================================
example18_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_valid; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; 
  reg pmp_addr_valid_en; 

  reg [63:0] pmp_addr_valid_reg_en; 

  reg [63:0] pmp_addr_valid_reg_en_reg, pmp_addr_valid_reg_en_new; 
  reg pmp_addr_valid_reg_en_en; 

  reg [63:0] pmp_addr_valid_reg_en_reg_en; 

  reg [63:0] pmp_addr_valid_reg_en_reg_en_reg, pmp_addr_
========================================================
example19_i-a_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
// BUG:
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_reg, pmp_addr_cfg_new_reg;
// BUG:
//  reg pmp_addr_cfg_en_reg; 
// FIX:
  reg pmp_addr_cfg_
========================================================
example0_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 


  //// Internal Signals
  reg [DATA_WIDTH-1:0] start_q; 
  reg [DATA_WIDTH-1:0] length_q;
  reg [DATA_WIDTH-1:0] source_addr_lsb_q; 
  reg [DATA_WIDTH-1:0] source_addr_msb_q; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_q; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_q; 
  reg [DATA_WIDTH-1:0] done_q; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl
========================================================
example1_i-a_t-0.5.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_mask_reg, pmp_addr_mask_new;
  reg pmp_addr_mask_en;  

  wire valid_reg; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_d_int; 
  wire [DATA_WIDTH-1:0] length_d_int;
  wire [DATA_WIDTH-1:0] source_addr_lsb_d_int; 
  wire [DATA_WIDTH-1:0] source_addr_msb_d_int; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_d_int; 
  wire [DATA_WIDTH
========================================================
example2_i-a_t-0.5.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg [63:0] pmp_addr_reg_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [63:0] pmp_addr_reg_en; 

  reg en_reg; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_valid; 
  reg [63:0] pmp_
========================================================
example3_i-a_t-0.5.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; 
  reg pmp_addr_valid_en; 

  reg pmp_addr_valid_reg2; 
  reg pmp_addr_valid_en2; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg2, dma_ctrl_new2; 
  reg dma_ctrl_en2; 
  
  reg [63:0] pmp_addr_reg2, pmp_addr_new2;
  reg pmp_addr_en2;  

  reg [63:0] pmp_addr_valid_reg2, pmp_addr_valid_new2; 
  reg
========================================================
example4_i-a_t-0.5.v
  reg pmp_access_type_en_new; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;
// BUG:
//  reg pmp_cfg_en_new;  
// FIX:
  reg pmp_cfg_en_new_new; 

  wire [DATA_WIDTH-1:0] source_addr_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_reg; 

  //// DMA 
  riscv::dma_t dma_i;
  riscv::dma_t dma_o;
  riscv::dma_data_t data_i;
  riscv::dma_data_t data_o;

  
 
========================================================
example5_i-a_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [63:0] pmp_value_reg, pmp_value_new; // for riscv::pmp_configure_io
  reg pmp_value_en;

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; // for riscv::pmp_configure_io
  reg pmp_addr_valid_en;

  reg [63:0] pmp_value_valid_reg, pmp_value_valid_new; // for riscv::pmp_configure_io
  reg pmp_value_valid_en;

  reg [63:0] pmp_addr_valid_reg2, pmp_addr_valid_new2; // for riscv::p
========================================================
example6_i-a_t-0.5.v
  reg pmp_access_type_en_reg; 

  reg pmp_access_done_reg; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg [63:0] pmp_addr_reg_next; 
  reg [63:0] pmp_addr_reg_next_next; 
  reg [7:0] [16-1:0] pmpcfg_reg_next; 
  reg pmp_access_type_reg_next; 
  reg pmp_access_type_reg_next_next; 
  reg pmp_access_done_reg_next; 

  //// Internal Signals

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  wire [
========================================================
example7_i-a_t-0.5.v
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_en; 

  //// Internal signals

  wire [DATA_WIDTH-1:0] source_addr_lsb_new;
  wire [DATA_WIDTH-1:0] source_addr_msb_new; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_new;
  wire [DATA_WIDTH-1:0] dest_addr_msb_new; 
  wire [DATA_WIDTH-1:0] done_new; 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_reg; 
  wire dma_ctrl_new_en; 
  
  wire [63:0] pmp
========================================================
example8_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid;
  reg pmp_access_type_reg_valid; 
  
  //// Internal Signals
  reg [DATA_WIDTH-1:0] data_in;
  reg [DATA_WIDTH-1:0] data_out;
  reg [DATA_WIDTH-1:0] data_in_valid;
  reg [DATA_WIDTH-1:0] data_out_valid;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_valid;
  reg [63:0]
========================================================
example9_i-a_t-0.5.v
  reg pmp_access_type_en_reg, pmp_access_type_en_new; 

  reg [63:0] status_reg;
  reg status_new;

  reg [63:0] debug_status_reg;
  reg debug_status_new;

  reg [63:0] debug_status_reg_reg;
  reg debug_status_reg_new;

  reg [63:0] debug_status_reg_reg_reg;
  reg debug_status_reg_reg_new;

  reg [63:0] debug_status_reg_reg_reg_reg;
  reg debug_status_reg_reg_reg_new;

  reg [63:0] debug_status_reg_reg_reg_reg_reg;
  reg debug_status_reg_reg_reg_reg_new;
========================================================
example10_i-a_t-0.5.v
  reg pmp_access_type_en_s; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_s; 
  reg [63:0] pmp_addr_reg_s; 
  reg [63:0] pmp_addr_new_s, pmp_addr_reg_s_s, pmp_addr_reg_s_s_s; 
  reg pmp_addr_en_s; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_s; 
  reg dma_ctrl_en_s; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_s_s; 
  reg dma_ctrl_en_s_s
========================================================
example11_i-a_t-0.5.v
  reg pmp_access_type_en; 

  wire [DATA_WIDTH-1:0] dma_data_out; 
  wire [DATA_WIDTH-1:0] dma_data_in; 

  //// Wires
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  wire [63:0]           pmp_addr; 
  wire [63:0]           pmp_addr_new_p; 
  wire [63:0]           pmp_addr_new_n; 
  wire [63:0]           pmp_addr_new_a; 
  wire [63:0]           pmp_addr_new_b; 
  wire [63:0]           pmp_addr_new_c; 
  wire
========================================================
example12_i-a_t-0.5.v
  reg pmp_access_type_en_reg; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0]  source_addr_reg;
  wire [DATA_WIDTH-1:0]  dest_addr_reg;
  wire [DATA_WIDTH-1:0]  length_reg;
  wire [DATA_WIDTH-1:0]  start_reg;
  wire [DATA_WIDTH-1:0]  done_reg;
  wire [DMA_CTRL_WIDTH-1:0]  dma_ctrl_reg_reg;
  wire [63:0] pmp_addr_reg_reg;
  wire pmp_access_type_reg_reg;

  //// Internal Logic
  assign valid_o = 0;
  assign done_
========================================================
example13_i-a_t-0.5.v
  reg pmp_access_type_en_reg; 
  
  reg [2:0] state_d; 
  reg valid_d; 

  wire [DATA_WIDTH-1:0] valid_o_new;
  wire [7:0] [16-1:0] pmpcfg_o_new;
  wire [16-1:0][53:0]     pmpaddr_o_new;
  wire we_flag_new;

  //// Internal Wires

  wire [DATA_WIDTH-1:0] source_addr_lsb_new;
  wire [DATA_WIDTH-1:0] source_addr_msb_new;
  wire [DATA_WIDTH-1:0] dest_addr_lsb_new;
  wire [DATA_WIDTH-1
========================================================
example14_i-a_t-0.5.v
  reg [3:0] pmp_access_type_en; 

  //// Internal signal
  reg [DATA_WIDTH-1:0] data_d;
  reg valid_reg; 
  reg valid_en;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 

  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [3:0] pmp_access_type_reg_new;
  reg pmp_access_type_en_new; 

  //// Internal wire
  wire [DATA_WIDTH-1:0] data_w;
  wire valid_w; 
  wire [DMA
========================================================
example15_i-a_t-0.5.v
  reg pmp_access_type_en_reg; 
  reg pmp_access_en; 

  //// Internal Signals
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_int; 
  wire [63:0] pmp_addr_int; 
  wire pmp_access_type_int; 
  wire pmp_access_en_int; 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_int; 
  wire [63:0] pmp_addr_new_int; 
  wire pmp_access_type_new_int; 
  wire pmp_access_en_new_int; 

  //// Internal Registers
  reg [DMA_CTRL_WIDTH-1:
========================================================
example16_i-a_t-0.5.v
  wire pmp_access_type_en; 

  reg [63:0] pmp_addr_valid; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid; 
  reg [63:0] pmp_addr_valid_d; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid_d; 
  reg [63:0] pmp_addr_valid_d1; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid_d1; 

  reg [63:0] pmp_addr_valid_d2; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid_d2; 
  reg
========================================================
example17_i-a_t-0.5.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; 
// BUG:
//  reg pmp_addr_valid_en; 
// FIX:
  reg [63:0] pmp_addr_valid_en; 
  
  reg [63:0] pmp_addr_valid_reg_next; 
  reg [63:0] pmp_addr_valid_new_next; 
  
  reg [63:0] pmp_access_type_reg_next; 
  reg [63:0] pmp_access_type_new_next; 

  reg [63:0] pmp_access_type_reg_next_next; 
  reg [63:0]
========================================================
example18_i-a_t-0.5.v
  reg pmp_access_type_en; 
  
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_lsb; 
  wire [DATA_WIDTH-1:0] start_msb; 
  wire [DATA_WIDTH-1:0] length_lsb; 
  wire [DATA_WIDTH-1:0] length_msb; 
  wire [DATA_WIDTH-1:0] source_addr_lsb; 
  wire [DATA_WIDTH-1:0] source_addr_msb; 
========================================================
example19_i-a_t-0.5.v
  reg pmp_access_type_en_reg; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0]  temp_addr_lsb;
  wire [DATA_WIDTH-1:0]  temp_addr_msb; 

  wire [DATA_WIDTH-1:0]  temp_data_lsb;
  wire [DATA_WIDTH-1:0]  temp_data_msb; 

  wire [DATA_WIDTH-1:0]  temp_addr_lsb_reg;
  wire [DATA_WIDTH-1:0]  temp_addr_msb_reg; 

  wire [DATA_WIDTH-1:0]  temp_data_lsb_reg;
  wire [DATA_WIDTH-1:0] 
========================================================
example0_i-a_t-0.7.v
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en, dma_ctrl_new_en; 
  
  reg [63:0] pmp_addr_reg_en, pmp_addr_new_en;
  
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_reg_en, pmp_access_type_new_en;

  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_reg_en_next, pmp_access_type_new_en_next;

  reg [63:0] pmp_addr_reg_en_next, pmp_addr_new_en_next;

  reg [DMA_CTRL_WIDTH-1:0] p
========================================================
example1_i-a_t-0.7.v
  reg [3:0] pmp_access_type_en; 
  
  //// DMA Control Logic
  always @(posedge clk_i)
  begin
    if (rst_ni) 
      dma_ctrl_reg <= CTRL_IDLE;
    else
      dma_ctrl_reg <= dma_ctrl_new;
  
end

========================================================
example2_i-a_t-0.7.v
  reg pmp_access_type_en_W;
  reg pmp_access_type_en_R;
    
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  reg logic [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_next; 
  reg dma_ctrl_en_new; 
  reg dma_ctrl_en_next; 
  reg pmp_addr_en_new;
  reg pmp_addr_en_next;
  reg pmp_access_type_en_W_new;
  reg pmp_access_type_en_W_next
========================================================
example3_i-a_t-0.7.v
  reg pmp_access_type_en_load;
  reg pmp_access_type_en_store;
// BUG:
//  reg pmp_access_type_en; 
// FIX:
  reg pmp_access_type_en_done; 

  reg [DMA_CTRL_WIDTH-1:0] start_ctrl;
  reg [DMA_CTRL_WIDTH-1:0] check_load_ctrl; 
  reg [DMA_CTRL_WIDTH-1:0] start_load_ctrl;
  reg [DMA_CTRL_WIDTH-1:0] load_ctrl; 
  reg [DMA_CTRL_WIDTH-1:0] check_store_ctrl; 
  reg [DMA_CTRL_WIDTH-1
========================================================
example4_i-a_t-0.7.v
  reg [7:0] pmp_access_type_en_reg;

  reg [DMA_CTRL_WIDTH-1:0]  dma_ctrl_valid_reg;
  reg dma_ctrl_valid_new; 
  assign dma_ctrl_valid_new = 0;
  wire dma_ctrl_valid_we;

  reg [63:0] pmp_addr_valid_reg;
  reg pmp_addr_valid_new;
  assign pmp_addr_valid_new = 0;
  wire pmp_addr_valid_we;



  //// Internal Registers
  reg [DATA_WIDTH-1:0] temp_lsb_buf;
  reg [DATA_WIDTH-1:0] temp_msb_buf;
  reg [DATA_WIDTH
========================================================
example5_i-a_t-0.7.v
  reg pmp_access_type_en_rvfi, pmp_access_type_en_rvfi_vld;

  reg valid_reg;

  reg done_reg; 
  reg done_reg_d; 

  reg enable_reg; 
  reg enable_reg_d; 

  //// Internal Signals
  reg [7:0] pmp_addr_i, pmp_addr_i_q, pmp_addr_i_qbuf; 
  reg [7:0] pmp_addr_o, pmp_addr_o_q, pmp_addr_o_qbuf; 
  reg [7:0] pmp_addr_i_buf, pmp_addr_o_buf; 
  reg [7:0] pmp_access_type_i, pmp_access
========================================================
example6_i-a_t-0.7.v
  reg pmp_access_type_en_reg; 
  reg pmp_we_reg; 

  //// Internal logic
  localparam DMA_CTRL_IDLE = DMA_CTRL_WIDTH'd0; 
  localparam DMA_CTRL_CHECK_LOAD = DMA_CTRL_WIDTH'd1; 
  localparam DMA_CTRL_START_LOAD = DMA_CTRL_WIDTH'd2;
  localparam DMA_CTRL_LOAD = DMA_CTRL_WIDTH'd3; 
  localparam DMA_CTRL_CHECK_STORE = DMA_CTRL_WIDTH'd4;
  localparam DMA_CTRL_START_STORE = DMA_CTRL_WIDTH'd5;
  localparam DMA_CT
========================================================
example7_i-a_t-0.7.v
  reg pmp_access_type_en_reg; 

  reg valid_reg; 
  reg valid_reg_aux; 

  wire [7:0] [16-1:0] pmpcfg_o;
  wire logic [16-1:0][53:0]     pmpaddr_o;
  wire logic we_flag_o;

  wire [DATA_WIDTH-1:0] valid_o_aux;
  wire [DATA_WIDTH-1:0] done_o;

  //// Internal Signals 
  
  wire [DMA_CTRL_WIDTH-1:0] ctrl_idle; 
  wire [DMA_CTRL_WIDTH-1:0] ctrl_check_load; 
  wire [DMA_CTRL_WIDTH-1
========================================================
example8_i-a_t-0.7.v
  reg [63:0] pmp_access_type_en; 

  //// Instantiation
  riscv_dma_ctrl_ctrl #(
    .DATA_WIDTH(DATA_WIDTH)
    ) riscv_dma_ctrl_inst(
      .clk_i(clk_i),
      .rst_ni(rst_ni),
      // IOs
      .start_i(start_i),
      .length_i(length_i),
      .pmpcfg_i(pmpcfg_i),
      .pmpaddr_i(pmpaddr_i),
      .we_flag(we_flag),
      // Registers
      .start_d(start_d),
      .length_d(length_d),
      .source_addr_lsb_d(
========================================================
example9_i-a_t-0.7.v
  reg [63:0] pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg;
  reg pmp_cfg_en;  

  reg we_reg; 
  reg we_en; 

  //// State

  localparam DEFAULT_STATE = CTRL_IDLE; 
  localparam PENDING_STATE = CTRL_IDLE; 

  reg [7:0] state_cur; 
  reg [7:0] state_next; 

  //// Internal Variables

  reg valid_reg; 
  reg valid_next; 

  //// Control Logic

// BUG:
//  always @(posedge clk_i) begin
//    if(rst_ni) begin
//      state_cur <= DEFAULT_STATE;
//    
========================================================
example10_i-a_t-0.7.v
  wire pmp_access_type_en;  
  reg pmp_access_en; 
 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 

  ////
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_init;
  reg [63:0] pmp_addr_reg_init, pmp_addr_reg_next;
  reg [7:0] pmp_cfg_reg_init, pmp_cfg_reg_next; 
  begin
    dma_ctrl_reg_init = CTRL_IDLE;
    pmp_addr_reg_init = riscv::PMPADDR_T::riscv_pmpaddr_null();
    pmp_cfg_reg_init = riscv::PM
end

========================================================
example11_i-a_t-0.7.v
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG:
//  reg pmp_cfg_en;
// FIX:
  reg pmp_cfg_en; 

  reg we_reg, we_new; 
  reg we_en; 

  reg [63:0] pmp_addr;   
  reg [7:0] pmp_cfg; 

  reg done; 
  reg valid; 

  reg [DATA_WIDTH-1:0] pmp_result; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  reg dma_ctrl_valid; 
  reg dma_ctrl_ready; 
  reg dma_ctrl_
========================================================
example12_i-a_t-0.7.v
  reg pmp_access_type_en_0; 
  reg pmp_access_type_en_1; 
  reg pmp_access_type_en_2; 
  reg pmp_access_type_en_3; 

  reg we_flag_reg, we_flag_new;

  reg [16-1:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en;  
  
  reg [16-1:0] pmp_data_reg_0, pmp_data_new_0;
  reg pmp_data_en_0;  

  reg [16-1:0] pmp_data_reg_1, pmp_data_new_1;
  reg pmp_data_en_1;  

  reg [16-
========================================================
example13_i-a_t-0.7.v
  reg pmp_access_type_en; 
  reg we_tmp;
 
  //// Constraints

  initial begin
    start_d = 0;
    length_d = 0;
    source_addr_lsb_d = 0;
    source_addr_msb_d = 0;
    dest_addr_lsb_d = 0;
    dest_addr_msb_d = 0;
    done_d = 0;
    dma_ctrl_reg = CTRL_IDLE;
    dma_ctrl_new = CTRL_IDLE;
    pmp_addr_reg = 0;
    pmp_addr_new = 0;
    pmp_access_type_reg = riscv::ACCESS_NONE;
    pmp_access_type_new = riscv::ACCESS_NONE
end

========================================================
example14_i-a_t-0.7.v
  wire pmp_access_type_en;
  assign pmp_access_type_en = pmp_addr_en | we_flag;   

  wire valid_reg, valid_new;
  assign valid_new = dma_ctrl_reg[CTRL_CHECK_STORE] | dma_ctrl_reg[CTRL_START_STORE];  
  assign valid_reg = dma_ctrl_reg[CTRL_CHECK_LOAD] | dma_ctrl_reg[CTRL_START_LOAD];   
  assign dma_ctrl_en = valid_new | valid_reg; 
  assign pmp_addr_en = pmp_access_type_en & dma_ctrl_en; 

  //// DMA Control Logic
  default: begin
    dma_ctrl_reg = CTRL_IDLE;
   
end

========================================================
example15_i-a_t-0.7.v
   always @(*) begin  BUG: always begin ... 
end

========================================================
example16_i-a_t-0.7.v
  reg pmp_access_type_en; 


  //// State machine 
  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] start_d1; 
  reg [DATA_WIDTH-1:0] length_d1;
  reg [DATA_WIDTH-1:0] source_addr_lsb_d1; 
  reg [DATA_WIDTH-1:0] source_addr_msb_d1; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_d1; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_d1; 
  reg [DATA_WIDTH-1:0] done_d1; 

========================================================
example17_i-a_t-0.7.v
  wire pmp_access_type_en; 

  reg valid_reg;
  reg valid_next;
  reg done_reg;
 
  assign valid_o = valid_reg;
  assign done_i = done_reg;

  //////// FSM 
  
  always @(*) 
  begin
    done_reg = done_i; 
    valid_reg = valid_next; 
  
end

========================================================
example18_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en;

  reg [63:0] pmp_addr_check_reg, pmp_addr_check_new; 
  reg pmp_addr_check_en; 
  
  reg [1:0] pmp_access_type_check_reg, pmp_access_type_check_new; 
  reg pmp_access_type_check_en; 

  reg [1:0] pmp_addr_mask_reg, pmp_addr_mask_new; 
  reg pmp_addr_mask_en; 
  
  reg [1:0] pmp_access_type_mask_reg, pmp_access_type_mask_new; 
  reg pmp_access_type_mask_en; 

  reg [1:0
========================================================
example19_i-a_t-0.7.v
  reg pmp_access_type_en_reg; // 1 if the read or write for the PMP should be done
  
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg we_flag_reg;
  reg [1:0] we_flag_new; 

// BUG:
//  reg [7:0] pmp_addr_reg, pmp_addr_new, pmp_addr_en;
// FIX:
  reg [7:0] pmp_addr_reg_nxt, pmp_addr_new_nxt;
// BUG:
//  reg [15:0] pmp_cfg_reg, p
========================================================
example0_i-a_t-0.9.v
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_val; 
  reg pmp_addr_val;
  reg pmp_access_type_val;
  reg pmp_access_type_en;

  always @(*) 
  begin
    done_d = done_i; 
    start_d = start_i; 
    length_d = length_i;
    source_addr_lsb_d = source_addr_lsb_i; 
    source_addr_msb_d = source_addr_msb_i; 
    dest_addr_lsb_d = dest_addr_lsb_i; 
    dest_addr_msb_d = dest_addr_msb_i; 
  
end

========================================================
example1_i-a_t-0.9.v
  reg pmp_access_type_reg_en; 
  reg pmp_cmprs_en; 
  reg pmp_srch_en; 

  reg [47:0] pmp_lut_addr_reg, pmp_lut_addr_new; // 1+48 bits of LUT address
// BUG:
//  reg pmp_lut_addr_en; 
// FIX:
  reg pmp_lut_addr_reg_en; 
  reg pmp_lut_data_sel_reg; 
  wire pmp_lut_data_sel_new; 
  
  reg [DATA_WIDTH-1:0] load_data_reg, load_next_data_reg; 
  reg load_data_en, load_data_wr_en; 

 
========================================================
example2_i-a_t-0.9.v
  reg logic pmp_access_type_en; 

  reg [7:0] pmp_page_reg, pmp_page_new;
// BUG: 
//  reg pmp_page_en; 
// FIX:
  reg logic pmp_page_en; 

  reg [63:0] pmp_rm_reg, pmp_rm_new;
// BUG: 
//  reg pmp_rm_en; 
// FIX:
  reg logic pmp_rm_en; 

  reg [7:0] pmp_addr_conf_reg, pmp_addr_conf_new;
// BUG: 
//  reg pmp_addr_conf_en; 
// FIX:
  reg logic pmp_addr_conf_en; 
  
  reg [63:0]
========================================================
example3_i-a_t-0.9.v
  reg rpmp_access_type_en;
  reg rvfi_cmd_reg, rvfi_cmd_new;
  reg rvfi_valid_reg, rvfi_valid_new;
// BUG:
//  reg rvfi_ready_reg, rvfi_ready_new;
// FIX:
  reg rvfi_ready_new; 


  //// Internal

  localparam CMD_LOAD = 'e0;
  localparam CMD_STORE = 'e1;
  
  localparam VALID_DONE_CYCLE = 'd4; 
  localparam VALID_WRITE_CYCLE = 'd5; 

  localparam  LOAD_START = 'l0; 
  localparam LOAD_DONE = 'l1; 

  localparam
========================================================
example4_i-a_t-0.9.v
  reg [63:0] pmp_access_another_addr_reg, pmp_access_another_addr_new;
  reg [63:0] initial_pmp_access_addr; 
  reg pmp_access_another_addr_en; 

  // These are just for setting initial values of the registers
  localparam  INIT_START_D= 'bX;
  localparam  INIT_LENGTH_D = 'bX;
  localparam  INIT_SOURCE_ADDR_LSB_D = 'bX;
  localparam  INIT_SOURCE_ADDR_MSB_D = 'bX;
  localparam  INIT_DEST_ADDR_LSB_D = 'bX;
  localparam  INIT_DEST_ADDR_MSB_D = 'bX;
========================================================
example5_i-a_t-0.9.v
   logic pmp_access_type_en; 

  reg [5:0] pmp_sel_reg, pmp_sel_new;
//  reg pmp_sel_en;
   logic pmp_sel_en;
  reg pmp_out_reg;
  reg pmp_out_vld;

  reg [5:0] dma_ctrl_in, dma_ctrl_in_new;
  reg pmp_addr_in,  pmp_addr_in_new;
  reg pmp_access_type_in,  pmp_access_type_in_new;
  reg pmp_sel_in,  pmp_sel_in_new;

  reg signed [31:0] i, ctrl_count, mode_count, start_count, 
========================================================
example6_i-a_t-0.9.v
  reg [63:0] pmp_addr_en, pmp_access_type_en;

  // Control signals. 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_state; 
  reg pos_ctrl_state; 
  reg [56:0] ctrl_register;
  reg ctrl_write_d; 
  reg ctrl_read_d; 
 
  // Status signals.
  reg valid_reg;
  reg valid_o_reg;
  wire nxt_ctrl_state;
  reg nxt_ctrl_state_d;
  reg nxt_ctrl_state_valid;
  reg valid_check;

  // DMA control signal
  wire dma_done; 
  wire dma_valid;


========================================================
example7_i-a_t-0.9.v
  reg r_pmp_access_type_en; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  

  reg [7:0] we_reg, we_reg_new;  
  
  wire [DATA_WIDTH-1:0] src_data_done_reg, dest_data_done_reg; 
  wire [DATA_WIDTH-1:0] src_data_reg, dest_data_reg;
  wire [DATA_WIDTH-1:0] src_data, dest_data;
  
  assign src_data = 
    (source_addr_lsb_d>=DATA_WIDTH-1)? 
      (datain_i[source_addr_lsb_d+DATA_WIDTH+1-1 : source_addr_lsb
========================================================
example8_i-a_t-0.9.v
  reg [1:0] pmp_access_type_en[2]; 

  //// Decoding registers.  

  reg start_ctl_decode_reg; 
  reg length_ctl_decode_reg; 
  reg source_addr_lsb_decode_reg;
  reg source_addr_msb_decode_reg;
  reg dest_addr_lsb_decode_reg;
  reg dest_addr_msb_decode_reg;
  reg done_decode_reg; 
 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctl_reg;

  reg [63:0]  pmp_c_reg, pmp_r_reg, pmp_w_reg;
  reg [1:0]    pmp_r_en, p
========================================================
example9_i-a_t-0.9.v
  reg pmp_access_type_en_next; 

  reg [63:0] pmp_request_reg, pmp_request_new; 
  reg pmp_request_en; 

  //// Wires
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl;
  wire [63:0] pmp_addr;
  wire pmp_request;

  //// Instance
  //pmp
  pmp m_pmp_i;

  ctrl_sel ctrl_i;
  //rng
  run_rng  run_rng_i;
  //dma
  dma_m dma_i;

  //// connect Module
  assign dma_ctrl = dma_ctrl_reg;
  assign pmp_addr = pmp_addr
========================================================
example10_i-a_t-0.9.v
  reg [63:0] pmp_ctrl_reg,  pmp_ctrl_new;  riscv::write_control also used by system.ic.pmp_ctrl_i.write_pmpcontrol()
 BUG:
  reg pmp_ctrl_en; 
 FIX:
  reg [63:0] pmp_addr_ctrl_reg, pmp_addr_ctrl_new;  riscv::read_addr by system.ic.pmp_ctrl_i.read_pmpaddr()
 BUG:
  reg pmp_addr_ctrl_en; 
 FIX:
  riscv::pmp_access_t pmp_access_type_reg_w, pmp_access_type_new_w;  use by system.ic.pmp_ctrl_i.write_pmpaddr
========================================================
example11_i-a_t-0.9.v
  reg pmp_access_type_en; 
  
  reg [63:0] dma_addr;

  reg [5:0] check_counter_reg, check_counter_new, check_counter_max;  
  reg check_counter_en;
  reg [15:0] dft_start_counter; // default start counter
  
  reg [5:0] load_counter_reg, load_counter_new;
  reg load_counter_en;
  reg [15:0] dft_load_counter;
  
  reg [5:0] store_counter_reg, store_counter_new;
  reg store_counter_en;
  reg [15:0] dft_store_counter;
  
  

  reg [31:0] ctrl_state_reg, ctrl_state_next
========================================================
example12_i-a_t-0.9.v
//  wire pmp_access_type_en;
  wire pmp_access_type_en;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid;
  reg dma_ctrl_en_valid;
  reg pmp_addr_en_valid;
  reg pmp_access_type_en_valid;
  
  
  reg [7:0] pmpcfg_d;
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_valid; 
  reg [47:0] pmpaddr_d;
  wire [63:0] pmpaddr_new_valid;
  reg we_flag_new;
  wire we_flag_
========================================================
example13_i-a_t-0.9.v
  reg [7:0] [16-1:0] pmpcfg_d;   


  reg we_flag_d; 

  wire valid_pre_load;
  wire valid_pre_store;
  wire [DMA_CTRL_WIDTH-1:0] ctrl_valid; 

  wire [RAM_ADR_WIDTH-1:0] ram_to_rd_addr;
  wire [RAM_ADR_WIDTH-1:0] ram_to_wr_addr;
  reg [64-1:0] ram_to_wr_addr_d, ram_to_rd_addr_d;
  reg ram_to_wr_addr_en, ram_to_rd_addr_en;

  reg [DMA_MST_WIDTH-1:0] write_ram_
========================================================
example14_i-a_t-0.9.v
  wire pmp_access_type_en; 


  reg [63:0]  pmp_data_reg, pmp_data_new;
// BUG:
//  reg pmp_data_en; 
//FIX:
  wire pmp_data_en; 


  reg [5:0]  wbctrl; 
  reg [5:0]  wbop_reg, wbop_new;
  reg wbop_en;  

  reg we; 
 
  // Defaults
  assign valid_o = 0;


  wire pmp_cs_p, pmp_we;
  assign pmp_cs_p = (pmp_addr_reg[12-1:0] != riscv::PMP_ADDR_NONE) ? 1:0;
  assign p
========================================================
example15_i-a_t-0.9.v
  reg [16-1:0] dma_load_mem_type;
  reg [16-1:0] dma_load_pmp_addr;
//  reg [16-1:0] dma_load_result_type;
  reg [16-1:0] dma_store_mem_type;
  reg [16-1:0] dma_store_pmp_addr;
  
  reg [16-1:0] load_pmp_addr;
  reg [16-1:0] store_pmp_addr;
//  reg [16-1:0] store_pmp_result; 

  reg [0:0] abort_load_counter;
  reg [0:0] abort_store_counter;
  reg abort_request_load;
  reg abort_request_store;


========================================================
example16_i-a_t-0.9.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new; 
  reg pmp_access_addr_en; 
  reg pmp_access_addr_value_reg, pmp_access_addr_value_new; 
  reg pmp_access_addr_value_en; 

  //// Logic
  wire [DATA_WIDTH-1:0] source_addr_msb_r; 
  wire [DATA_WIDTH-1:0] source_addr_lsb_r; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_r; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_r; 
  wire [DMA_CTRL_WIDTH-1:0]
========================================================
example17_i-a_t-0.9.v
  reg [63:0] pmp_rwh_delayed, pmp_rwh, pmp_rwh_new; 
  reg pmp_rwh_en; 
  
  reg [63:0] pmp_addr_check_delayed, pmp_addr_check, pmp_addr_check_new; 
  reg pmp_addr_check_en; 
  
  reg [63:0] pmp_offset_check_delayed, pmp_offset_check, pmp_offset_check_new; 
  reg pmp_offset_check_en; 
  
  assign valid_o = valid_i; 
  
  //// Internal Signals 
  wire check_load, start_load, check_store, start_store; 
  wire done_load, done_store; 
========================================================
example18_i-a_t-0.9.v
  reg pmp_access_type_en_reg, pmp_access_type_en_new; 
  reg pmp_access_address_reg;
  reg pmp_access_wdata_reg;
  
  reg valid_reg = 0;
  reg [11:0] control_state_reg = CTRL_INIT;
  reg [DMA_CTRL_WIDTH:0] valid_bit = 'b0000;
  reg [DATA_WIDTH-1:0] valid_data = 'b0;
  reg c_valid_d;
  reg [7:0] [16-1:0] valid_pmp_config;
  reg valid_pmp_addr;
  reg valid_wren;
  reg done_reg = 'b0;
  
  //// FSM
  localparam ID
========================================================
example19_i-a_t-0.9.v
   logic pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  reg we_reg;

  reg [1:0] ctrl_reg, ctrl_new; 
  reg ctrl_en;

  reg [1:0] status_reg, status_new;  

  reg valid_reg, valid_new;
  reg valid_en;

  reg [7:0] fsm_reg, fsm_new;
  reg fsm_en;

  
  //// FSM 
  reg valid_r; 
  reg [DATA_WIDTH-1:0] length_r; 
  reg [DATA_WIDTH-1:0] done_r; 

  initial begin
    valid_
end

========================================================
example0_i-b_t-0.1.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  reg pmp_cfg_en_new; 

  reg [7:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new; 
  reg pmp_addr_reg_lsb_en, pmp_addr_reg_msb_en; 
  reg pmp_addr_reg_lsb_en_new, pmp_addr_reg_msb_en_new; 

  reg [7:0]
========================================================
example1_i-b_t-0.1.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [63:0] pmp_addr_reg_new; 
  reg [63:0] pmp_addr_reg_new_new; 
  reg [63:0] pmp_addr_reg_new_new_new; 

  reg [63:0] pmp_addr_reg_new_new_new_new; 
  reg [63:0] pmp_addr_reg_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_new_new_new_new_new_new; 

  reg [63:0] pmp_addr_reg_new_new_new_new_new_new_new; 
  reg [
========================================================
example2_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en; 

  reg [7:0] pmp_cfg_reg_new; 
  reg [7:0] pmp_cfg_reg_new_en; 

  reg [16:0] pmp_addr_reg_new; 
  reg [16:0] pmp_addr_reg_new_en; 

  reg [16:0] pmp_addr_reg_new_en_new; 
  reg [16:0] pmp_addr_reg_new_en_new_en
========================================================
example3_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg pmp_addr_en_lsb, pmp_addr_en_msb;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

  reg [7:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg [7:0] pmp_cfg_new_ls
========================================================
example4_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [16:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg pmp_addr_reg_en; 

  reg [16:0] pmp_addr_new_lsb, pmp_addr_new_msb; 
  reg pmp_addr_new_en; 

  reg [16:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb; 
  reg pmp_cfg_reg_en; 

  reg [16:0] pmp_cfg_new_lsb, pmp_cfg_new_msb
========================================================
example5_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_
========================================================
example6_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_next; 

  reg [63:0] pmp_addr_reg_en_next_new; 
  reg [63:0] pmp_addr_reg_en_next_next; 

  reg [63:0] pmp_addr_reg_en_next_next_new; 
  reg [63:0] pmp_addr_reg_en_next_next_next; 

  reg [63:0] pmp_addr_reg_en_next_next_next_new; 
  reg [63:0] pmp_
========================================================
example7_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_en; 

  reg [63:0] pmp_addr_reg_en_new_new; 
  reg pmp_addr_reg_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg pmp_addr_reg_en_new_new_en; 

  reg [63:0] pmp_addr_reg_en_new_new_new_new; 
  reg pmp_addr_reg_en_new_new_new_en; 

  reg [63
========================================================
example8_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 

  reg [63:0] pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 

  reg [63:0] pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 

  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_
========================================================
example9_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_
========================================================
example10_i-b_t-0.1.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 

  reg [63:0] pmp_addr_reg_en_new_reg; 
  reg [63:0] pmp_addr_reg_en_new_new; 

  reg [63:0] pmp_addr_reg_en_new_new_reg; 
  reg [63:0] pmp_addr_reg_en_new_new_new; 

  reg [63:0] pmp_addr_reg_en_new_new_new_reg; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new; 

  reg
========================================================
example11_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [16:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg pmp_addr_en_lsb, pmp_addr_en_msb; 

  reg [16:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb; 
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [16:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new; 
  reg pmp_addr_en_lsb_new
========================================================
example12_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
========================================================
example13_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_
========================================================
example14_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_en; 
  reg [63:0] pmp_addr_reg_en_new_en_en_en; 
  reg [63:0] pmp_addr_reg_en_new_en_en_en_en; 
  reg [63:0] pmp_addr_reg_en_new_en_en_en_en_en; 
  reg [63:0] pmp_addr_reg_en_new_
========================================================
example15_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_en; 
  reg [63:0] pmp_addr_reg_en_new_en_en_en; 
  reg [63:0] pmp_addr_reg_en_new_en_en_en_en; 
  reg [63:0] pmp_addr_reg_en_new_en_en_en_en_en; 
  reg [63:0] pmp_addr_reg_en_new_
========================================================
example16_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_en; 

  reg [63:0] pmp_addr_reg_en_new_new; 
  reg pmp_addr_reg_en_en_new; 

  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg pmp_addr_reg_en_en_new_new; 

  reg [63:0] pmp_addr_reg_en_new_new_new_new; 
  reg pmp_addr_reg_en_en_new_new_new; 

  reg [63
========================================================
example17_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_valid; 

  reg [63:0] pmp_addr_reg_en_new_valid; 
  reg [63:0] pmp_addr_reg_en_valid_new; 

  reg [63:0] pmp_addr_reg_en_new_valid_new; 
  reg [63:0] pmp_addr_reg_en_valid_new_new; 

  reg [63:0] pmp_addr_reg_en_new_valid_new_new; 
  reg [63:0] pmp_
========================================================
example18_i-b_t-0.1.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 

  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_new; 
  reg dma_ctrl_en_new_new; 

  reg [63:0] pmp_addr_reg_new_new;
  reg pmp_addr_en_new_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl
========================================================
example19_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg pmp_addr_reg_en_new_en_new_en; 

  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg pmp_addr_reg_en_new_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en_new; 
 
========================================================
example0_i-b_t-0.3.v
  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new;
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [7:0] pmp_cfg_reg_en, pmp_cfg_new_en;
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_cfg_reg_en_reg, pmp_cfg_new_en_new;
  reg pmp_cfg_en_reg_reg; 

  reg [7:0] pmp_cfg_reg_en_reg_reg, pmp_cfg_new_en_new_new;
  reg pmp_cfg_en_
========================================================
example1_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en; 
  reg pmp_cfg_en_new; 

  reg [16-1:0] pmp_addr_reg_msb, pmp_addr_new_msb;
  reg pmp_addr_en_msb; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_en_msb; 
// FIX:
 
========================================================
example2_i-b_t-0.3.v
  reg [63:0] pmp_access_type_reg_en; 
  reg pmp_access_type_en; 

  reg [63:0] pmp_access_type_reg_new; 
  reg pmp_access_type_new_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg pmp_addr_en; 

  reg [63:0] pmp_addr_reg_new; 
  reg pmp_addr_new_en; 

  reg [63:0] pmp_addr_reg_new_en; 
  reg pmp_addr_new_en; 

  reg [63:0] pmp_addr_reg_new_en_new; 
  reg pmp_addr_new_en_new; 

 
========================================================
example3_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 
  
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_addr_en; 
// FIX:
  reg [63:0] pmp_access_addr_en; 
  
  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_data_en; 
// FIX:
  reg [63:0] pmp_access_data_en; 
  
  reg [63:0] pmp_access_mask_reg, p
========================================================
example4_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_
========================================================
example5_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 

  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_new_en_new; 

  reg [63:0] pmp_addr_reg_en_new_new; 
  reg [63:0] pmp_addr_new_en_new_new; 

  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg [63:0] pmp_addr_new_en_new_new_new; 

  reg [63:0] pmp_addr_reg_en_new_
========================================================
example6_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_en_en; 
// FIX:
  reg [63:0] pmp_addr_en_en; 

  reg [63:0] pmp_access_en_reg, pmp_access_en_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_en_en; 
// FIX:
  reg [63:0] pmp_access_en_en; 

  reg [63:0] pmp_access_en_reg_reg, pmp_
========================================================
example7_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb;
  reg [63:0] pmp_addr_reg_lsb_lsb, pmp_addr_reg_lsb_msb;
  reg [63:0] pmp_addr_reg_msb_lsb, pmp_addr_reg_msb_msb;
  reg [63:0] pmp_addr_new_lsb_lsb, pmp_addr_new_lsb_msb;
  reg [63:0] pmp_addr_new_msb_lsb, pmp_addr_new_ms
========================================================
example8_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  reg [63:0] pmp_addr_reg_valid_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_next; 
  reg [63:0] pmp_addr_reg_valid_next; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_next_new; 
  reg [63:0] p
========================================================
example9_i-b_t-0.3.v
  reg pmp_access_type_en; 
  
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  
  reg [63:0] pmp_addr_reg_en_new_pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new_pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_pmp_addr_reg_en_new_pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new_pmp_addr_reg_en_new_pmp_addr_reg_en_new; 
  reg
========================================================
example10_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  reg pmp_addr_reg_new; 
  reg pmp_addr_en_new; 
  reg pmp_access_type_reg_new; 
  reg pmp_access_type_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_new; 
  reg dma_ctrl_en_new_new; 
  reg pmp_addr_reg_new_new; 
  reg pmp_addr_en_new_new; 
========================================================
example11_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

  reg [7:0] pmp_addr_reg_en;
  reg [7:0] pmp_cfg_reg_en;
  reg [7:0] pmp_access_type_reg_en;

  reg [7:0] pmp_addr_new_en;
  reg [7:0] pmp_cfg_new_en;
  reg [7:0] pmp_access_type_new_en;

  reg [7:0] pmp_addr_reg_en_new;
  reg [7:0] pmp_cfg_reg_en_new;
  reg [7:
========================================================
example12_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_next; 

  reg [63:0] pmp_addr_reg_next;
  reg pmp_addr_en_next;
  reg pmp_access_type_reg_next;
  reg pmp_access_type_en_next_next;

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_reg_next; 
  reg valid_reg_next_next; 

  reg [DATA_WIDTH-1:0] done_reg; 
  reg done_reg_next; 
  reg done_reg_next_next; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg
========================================================
example13_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] done_reg; 
  reg done_new; 
  reg done_en; 

  reg [DATA_WIDTH-1:0] start_reg; 
  reg start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] length_reg; 
  reg length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1:0]
========================================================
example14_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg [63:0] pmp_addr_reg_old; 
  reg [63:0] pmp_addr_reg_old_old; 
  reg [63:0] pmp_addr_reg_old_old_old; 
  reg [63:0] pmp_addr_reg_old_old_old_old; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old; 
  reg [63:0] pmp_addr_reg_old_old_old; 
  reg [63:0] pmp_addr_reg_old_old_old_old;
========================================================
example15_i-b_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [7:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg pmp_addr_reg_lsb_en, pmp_addr_reg_msb_en;

  reg [63:0] pmp_addr_reg_lsb_new_lsb, pmp_addr_reg_lsb_new_msb;
  reg [7:0] pmp_addr_reg_lsb_new_lsb_new, pmp_addr_reg_lsb_new_msb_new;
  reg pmp_addr_reg_lsb_new_lsb_
========================================================
example16_i-b_t-0.3.v
  reg pmp_access_type_en; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0]  source_addr_lsb_new; 
  wire [DATA_WIDTH-1:0]  source_addr_msb_new; 
  wire [DATA_WIDTH-1:0]  dest_addr_lsb_new; 
  wire [DATA_WIDTH-1:0]  dest_addr_msb_new; 
  wire [DATA_WIDTH-1:0]  start_new; 
  wire [DATA_WIDTH-1:0]  length_new; 
  wire [DATA_WIDTH-1:0]  done_new; 
  wire [DMA_CTRL_WIDTH-1:0] dma
========================================================
example17_i-b_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_cfg_en; 
// FIX:
  reg pmp_addr_cfg_en_reg; 

  reg [7:0] pmp_addr_cfg_reg_2, pmp_addr_cfg_new_2;
// BUG: Uninitialized Value on Reset for
========================================================
example18_i-b_t-0.3.v
  reg pmp_access_type_en_reg; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_reg; 
  reg [63:0] pmp_addr_reg_reg;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_reg_reg; 
  reg [63:0] pmp_addr_reg_reg_reg;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_reg_reg_reg; 
  reg [63:0] pmp_addr_reg_reg_reg_reg;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_reg_reg_reg_reg; 
  reg [
========================================================
example19_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [7:0] pmp_cfg_reg_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_reg_en; 

  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_reg_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_
========================================================
example0_i-b_t-0.5.v
  reg [63:0] pmp_access_type_reg_en;
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;
  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en;
  reg pmp_access_en;

  reg [63:0] pmp_addr_reg_en;
  reg [63:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en;
  reg pmp_en;

  //// Internal Signals
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  reg [63:0
========================================================
example1_i-b_t-0.5.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 

  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new; 
  reg pmp_addr_reg_lsb_en, pmp_addr_reg_msb_en; 

  reg [63:0] pmp_addr_reg_lsb_new_new, pmp_addr_reg_msb_new_new; 
  reg pmp_addr_reg_lsb_en_new, pmp_addr_reg_msb_en_new; 

  reg [63:0] pmp_addr_reg_lsb_new_new_new, pmp
========================================================
example2_i-b_t-0.5.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 
  
  //// Internal Signals
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_int; 
  wire [63:0] pmp_addr_int; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_int_new; 
  wire [63:0] pmp_addr_int_new; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_int_next; 
  wire [63:0] pmp_addr_int_next; 
  wire dma_ctrl_en_int; 

  wire pmp_access_type_int; 
  wire
========================================================
example3_i-b_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [63:0] pmp_read_sig_reg, pmp_read_sig_new;
  reg pmp_read_sig_en;

  reg [63:0] pmp_write_sig_reg, pmp_write_sig_new;
  reg pmp_write_sig_en;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

  reg [7:0] pmp_addr_i_reg, pmp_addr_i_new;
  reg pmp_addr_i_en;

  reg [7:0] pmp_data_i_reg, pmp_data_i_new;
  reg p
========================================================
example4_i-b_t-0.5.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  
  reg [7:0] [16-1:0] pmpcfg_d;   
  reg logic [16-1:0][53:0]     pmpaddr_d;  
  reg logic  we_flag_d;

  reg [7:0] [16-1:0] pmpcfg_new;   
  reg logic [16-1:0][53:0]     pmpaddr_new;  
========================================================
example5_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; 

  reg [63:0] pmp_addr_wen;
  reg [63:0] pmp_addr_wdata;

  reg [63:0] pmp_addr_ren;
  reg [63:0] pmp_addr_rdata;

  reg [63:0] pmp_addr_wen_new;
  reg [63:0] pmp_addr_wdata_new;

  reg [63:0] pmp_addr_ren_new;
  reg [63:0] pmp_addr_rdata_new;

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  reg pmpcfg_wen;
  reg p
========================================================
example6_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b0; 

  reg [63:0] pmp_addr_reg_new;

  //// Internal Signals

  wire [DMA_CTRL_WIDTH-1:0] ctrl_reg; 
  wire [DMA_CTRL_WIDTH-1:0] ctrl_new; 

  wire [DATA_WIDTH-1:0] start_reg; 
  wire [DATA_WIDTH-1:0] length_reg;
  wire [DATA_WIDTH-1:0] source_addr_lsb_reg; 
  wire [DATA_WIDTH-1:0] source_addr_msb_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_reg; 

========================================================
example7_i-b_t-0.5.v
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en; 
  
  reg [63:0] pmp_mask_reg, pmp_mask_new;
  reg pmp_mask_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg valid_reg; 
  reg valid_en; 
  
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  
  reg we_reg; 
  reg we_en; 

  reg [7:0] pmpaddr_reg, p
========================================================
example8_i-b_t-0.5.v
  reg pmp_access_type_en; 

  reg [3:0] pmp_access_type_reg_4_3, pmp_access_type_new_4_3; 
  reg pmp_access_type_en_4_3; 

  reg [2:0] pmp_access_type_reg_2_0, pmp_access_type_new_2_0; 
  reg pmp_access_type_en_2_0; 

  reg [63:0] pmp_addr_reg_4_3, pmp_addr_new_4_3; 
  reg pmp_addr_en_4_3; 

  reg [63:0] pmp_addr_reg_2_0, pmp_addr_new_2_0; 
  reg pmp_
========================================================
example9_i-b_t-0.5.v
  reg pmp_access_type_en_reg; 
  reg [7:0] pmp_access_type_reg_new;
  reg [7:0] pmp_access_type_reg_new_new; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;  
  reg pmp_cfg_en;  
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new;
  reg dma_ctrl_en_new; 
  
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [7:0] pmp_cfg_reg_new;
  reg pmp_cfg_en_new;  

  //// DMA
========================================================
example10_i-b_t-0.5.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_en_en; 
// FIX:
  reg pmp_addr_en_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  reg [7:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [7:0] pmpcfg_reg_en;
  reg [63:0] pmpaddr_reg_en; 

  reg [DATA_WIDTH-1:0] start_q;
========================================================
example11_i-b_t-0.5.v
  reg pmp_access_type_en;
  reg [63:0] pmp_addr_curr; 
  reg [15:0] pmp_addr_sel; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_o; 
  reg dma_ctrl_en_o; 
  reg [63:0] pmp_addr_reg_o;
  reg pmp_addr_en_o;  
  reg [63:0] pmp_addr_curr_o; 
  reg [15:0] pmp_addr_sel_o; 

  reg [DATA_WIDTH-1:0] data_o;
  reg valid_o_reg; 

  ////////////////////////
  //// Combinational Logic
  always @(
========================================================
example12_i-b_t-0.5.v
  reg pmp_access_type_en; 

  reg valid_reg; 
  reg valid_new; 

  reg dma_ctrl_done; 
  reg [DATA_WIDTH-1:0] dma_ctrl_done_d; 
  reg dma_ctrl_done_new; 
  reg dma_ctrl_done_reg; 
  reg dma_ctrl_done_reg_new; 

  reg [15:0] dma_ctrl_status; 
  reg [15:0] dma_ctrl_status_new; 
  reg [15:0] dma_ctrl_status_reg; 
  reg [15:0] dma_ctrl_status_reg_new; 
  reg [15:0] dma_ctrl_status_reg_new_new; 


========================================================
example13_i-b_t-0.5.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [7:0] we_reg; 
  reg we_en; 

  reg [DATA_WIDTH-1:0] start_reg; 
  reg [DATA_WIDTH-1:0] length_reg;
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_reg;
========================================================
example14_i-b_t-0.5.v
  reg pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] pmp_data_reg, pmp_data_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_data_en;
// FIX:
  reg pmp_data_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  
  reg [DATA_WIDTH-1:0] pmp_data_reg_new;
  reg pmp_data_en_new; 

  reg [DMA_CT
========================================================
example15_i-b_t-0.5.v
  reg [DATA_WIDTH-1:0] pmp_access_data_reg, pmp_access_data_new; 
  reg pmp_access_data_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Internal Signals
  wire valid_d;
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid; 
  wire [63:0] pmp_addr_valid; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  wire pmp_access_type_valid; 
//
========================================================
example16_i-b_t-0.5.v
  reg [1:0] pmp_access_type_en; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en_new; 
  reg pmp_access_type_en_reg; 

  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new; 
  reg pmp_addr_en_reg_new; 

  reg [63:0] pmp_addr_en_reg_new, pmp_addr_en_new_new; 
  reg pmp_addr_en_reg_new_new; 

  reg [63:0] pmp_addr_en_reg_new_new, pmp_addr_en_new_new_new; 
  reg pmp_addr_en
========================================================
example17_i-b_t-0.5.v
  reg pmp_access_type_en;
  reg pmp_access_type_en_new;

  reg [DMA_CTRL_WIDTH-1:0] ctrl;
  reg [DMA_CTRL_WIDTH-1:0] valid;
  reg [DMA_CTRL_WIDTH-1:0] valid_new;
  reg [DMA_CTRL_WIDTH-1:0] valid_d;
  reg [DMA_CTRL_WIDTH-1:0] valid_d_new;
  reg [DMA_CTRL_WIDTH-1:0] valid_d_temp;

  reg [DMA_CTRL_WIDTH-1:0] valid_d_temp_new;
  reg valid_d_temp_en;
  reg valid
========================================================
example18_i-b_t-0.5.v
  reg pmp_access_type_en; 
  reg we_reg, we_new; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  reg [63:0] pmp_addr_reg, pmp_addr_new; 
  reg pmp_addr_en; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] dest_addr_o; 
  wire [DATA_WIDTH-1:0] source_addr_o; 
  wire [DATA_WIDTH-1:0] length_o; 
  wire [DATA_WIDTH-1:0] valid_o_reg; 
  wire [DATA_WIDTH-1:0] done_o_
========================================================
example19_i-b_t-0.5.v
  reg pmp_access_type_en; 
//
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 

  //// Status
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_status; 
  reg [63:0] pmp_addr_reg_valid_status; 
  reg [DATA_WIDTH-1:0] valid_reg; 
  reg [DATA_WIDTH-1:0] valid_reg_status; 
  reg [DATA_WIDTH-1:0] done_reg; 
  reg [DATA_WIDTH-1:0] done_reg_status; 

  ////
========================================================
example0_i-b_t-0.7.v
  reg pmp_access_type_en; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] source_addr_new;
  wire [DATA_WIDTH-1:0] dest_addr_new; 

  wire pmp_addr_valid; 
  wire pmp_access_type_valid; 

  //// DMA Control Logic
  assign source_addr_new = start_d;
  assign dest_addr_new = start_d;
  assign pmp_addr_valid = 1'b0;
  assign pmp_access_type_valid = 1'b0;

  assign dma_ctrl_reg = dma_ctrl_new; 
  assign pmp_addr_reg = pmp_addr_new;
  assign pmp_access_type_reg = pmp
========================================================
example1_i-b_t-0.7.v
  reg pmp_access_type_en; 


  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_en;
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_en; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg dest_addr_lsb_en;
  reg [DATA_WIDTH-1:0] dest_addr_msb_reg, dest_addr_msb_new; 
  reg dest_addr_msb_en; 

  reg [
========================================================
example2_i-b_t-0.7.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [63:0] pmp_addr_reg_en;
  reg [DATA_WIDTH-1:0] start_reg_en; 
  reg [DATA_WIDTH-1:0] length_reg_en;
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg_en; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg_en; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg_en; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_reg_
========================================================
example3_i-b_t-0.7.v
  reg pmp_access_type_en_d; 
  reg pmp_access_type_en_m; 

  

  //// Internal Signals

  //// Debug and Status
  reg signed [63:0]  reg_data;  
  wire pmp_access_type_en_test; 

  //// FSM and Control
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_test; 
  wire dma_ctrl_en_test; 
  reg [63:0] pmp_addr_new_test;
  reg pmp_addr_en_test;  
  reg [7:0] [16-1:0] pmpcfg_i_test;   
  reg pmp_access_type_new_test; 

  //// DMA
========================================================
example4_i-b_t-0.7.v
  reg pmp_access_type_en; 
  reg pmp_access_type_new_d; 
  reg valid_reg;
  // reg [16-1:0] [53:0] pmpaddr_reg;  
  reg valid_reg_d;

  //// DMA registers
  reg [DMA_ADDR_WIDTH-1:0] dma_source_addr_reg, dma_source_addr_new; 
  reg dma_source_addr_en; 

  reg [DMA_ADDR_WIDTH-1:0] dma_dest_addr_reg, dma_dest_addr_new; 
  reg dma_dest_addr_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d
========================================================
example5_i-b_t-0.7.v
  reg pmp_access_type_en_d; 
 
  reg valid_d;
  reg valid_r;
  reg valid_update_d;
  reg valid_update_r;
  reg valid_update_w;

  //// Internal Signals 
  reg valid_new_d; 
  wire valid_new_r; 

  //// Internal Registers
  reg [DATA_WIDTH-1:0] [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg [63:0] [DMA_CTRL_WIDTH-1:0] pmp_addr_reg_d; 
  reg dma_ctrl_en_d; 
  reg pmp_addr_en_d; 

  //// Programmed Logic 

========================================================
example6_i-b_t-0.7.v
  reg [63:0] pmp_access_type_reg_64; 
  reg pmp_access_type_en;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_64; 
  reg dma_ctrl_en_64;

  //// Wire Signals

  wire [DATA_WIDTH-1:0] addr_lsb;
  wire [DATA_WIDTH-1:0] addr_msb;
  wire [DATA_WIDTH-1:0] addr_base;
  wire [DATA_WIDTH-1:0] addr_len;
  wire [DATA_WIDTH-1:0] addr_len_inc;
  wire [DATA_WIDTH-1:0] addr_len_inc_base;
  wire [DATA
========================================================
example7_i-b_t-0.7.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new; 
  reg pmp_access_addr_en;  

  reg [RISCV_DUTY_CYCLE_WIDTH-1:0]  dut_duty_cycle;
  reg [RISCV_DUTY_CYCLE_WIDTH-1:0]  dut_num_access; 
  reg [RISCV_DUTY_CYCLE_WIDTH-1:0]  dut_denom_access; 
  reg [RISCV_DUTY_CYCLE_WIDTH-1:0]  dut_last_num_access;
  reg [RISCV_DUTY_CYCLE_WIDTH-1:0]  dut
========================================================
example8_i-b_t-0.7.v
  reg pmp_access_type_en_reg; 
  reg pmp_access_type_en; 

  //// Control Logic
  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg, ctrl_new; 
  reg valid_reg; 
  reg [DATA_WIDTH-1:0] data_reg; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_next; 
  reg valid_next; 
  reg [DATA_WIDTH-1:0] data_next; 
  reg ctrl_en; 
  reg valid_en; 
  reg data_en; 

  //// State Machine
  reg [DMA_CTRL_WIDTH-1:0] state; 
  reg [DATA_W
========================================================
example9_i-b_t-0.7.v
  reg [2:0] pmp_access_type_r_reg, pmp_access_type_r_new; 
//  reg pmp_access_type_r_en; 

  reg [15:0] pmp_addr_w_reg, pmp_addr_w_new; 
//  reg pmp_addr_w_en; 

  wire pmp_do_en; 
  assign pmp_do_en = pmp_addr_en || pmp_addr_w_en || pmp_access_type_en;
  wire pmp_rd_en; 
  assign pmp_rd_en = pmp_addr_en || pmp_addr_w_en || pmp_access_type_r_en;
  wire pmp_wr_en; 
  assign pmp_wr
========================================================
example10_i-b_t-0.7.v
  reg pmp_access_type_en; 
  reg [31:0] cpu_permit_reg, cpu_permit_new; 
  reg cpu_permit_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg logic [7:0] [16:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  //// States

  localparam IDLE           = 0;
  localparam CHECK_LOAD     = 1;
  localparam START_LOAD     = 2;
  localparam LOAD           = 3;
  localparam CHECK_STORE    = 4;
  localparam START_STORE    = 5;
  localparam STORE          = 6;
 
========================================================
example11_i-b_t-0.7.v
  reg pmp_access_type_en; 
  reg pmp_access_type_reg_new;
  reg pmp_access_type_reg_init;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_init; 

  reg [63:0] pmp_addr_reg_new;
  reg [63:0] pmp_addr_reg_init;

  reg [7:0] pmpcfg_reg_new;
  reg [7:0] pmpcfg_reg_init;

  //// Internal Signals
  wire [DATA_WIDTH-1:0]  data_in;
  wire [DATA_WIDTH-1
========================================================
example12_i-b_t-0.7.v
  reg [63:0] pmp_access_type_reg_LSB;
  reg pmp_access_type_reg_MSB;
  reg pmp_access_type_reg_en; 
  reg pmp_addr_reg_en; 


  //// Registers for Debug, Trace, and Pmp
  reg [DATA_WIDTH-1:0] _source_addr_lsb_d;
  reg [DATA_WIDTH-1:0] _source_addr_msb_d;
  reg [DATA_WIDTH-1:0] _dest_addr_lsb_d;
  reg [DATA_WIDTH-1:0] _dest_addr_msb_d;
  reg [DATA_WIDTH-1:0] _start_d; 
  reg [DATA_
========================================================
example13_i-b_t-0.7.v
  reg [63:0] pmp_access_type_reg_temp;
  reg pmp_access_type_en_temp;
//
  reg [7:0] pmp_access_reg, pmp_access_new;
  reg pmp_access_en;  

  reg dma_ctrl_valid;
  reg pmp_addr_valid;

  //// Assigns  
  assign valid_o =  dma_ctrl_valid & pmp_addr_valid; 
  assign pmpaddr_i = pmp_addr_reg;
  assign pmpcfg_i = pmp_access_reg;
  assign we_flag = dma_ctrl_en;

  //// Internal Signals
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl, dma_ctrl_
========================================================
example14_i-b_t-0.7.v
  reg pmp_access_type_en;
  reg [64-1:0] pmp_reg;
  reg [0:0] pmp_lock_reg, pmp_lock_new, pmp_lock_valid; 
  reg pmp_lock_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new, pmp_cfg_valid;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_cfg_reg, pmp_addr_cfg_new, pmp_addr_cfg_valid;
  reg pmp_addr_cfg_en; 

  reg [63:0] pmp_addr_cfg_reg_pmp_r, pmp_addr_cfg_new_pmp_r, pmp_addr_cfg_valid
========================================================
example15_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  
  //// Internal Signals

  reg [DATA_WIDTH-1:0] source_addr_u;
  reg [DATA_WIDTH-1:0] dest_addr_u;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_u;
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid;
  reg dma_ctrl_re, dma_ctrl_we; 

  reg [63:0] pmp_addr_u;
  reg [1:0] pmp_access_type_u;
  wire [1:0] pmp_access_type_valid; 
  reg pmp_access_type_re, pmp_
========================================================
example16_i-b_t-0.7.v
  reg pmp_access_type_en; 

  // Check for overlap of source/dest address ranges
  wire addr_overlap;
  assign addr_overlap = (source_addr_lsb_d <= dest_addr_lsb_d && dest_addr_lsb_d < source_addr_msb_d) || (source_addr_lsb_d < dest_addr_msb_d && dest_addr_msb_d < source_addr_msb_d);

  reg [DATA_WIDTH-1:0] source_data_reg; // Needs to be reg for when valid_o is not asserted
  reg [DATA_WIDTH-1:0] dest_data_reg; // Needs to be reg for when valid_o is not asserted
  reg [DATA_WIDTH-1:0] valid_reg;
========================================================
example17_i-b_t-0.7.v
  reg pmp_access_type_en; 
  
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_r; 
  wire pmp_addr_r; 
  wire pmp_access_type_r; 
  wire pmp_addr_rdy; 
  wire pmp_addr_rdy_r; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_rdy; 
  wire dma_ctrl_rdy_r; 
  wire [DMA_CTRL_WIDTH-1:0] pmp_access_type_rdy; 
  wire pmp_access_type_rdy_r; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_
========================================================
example18_i-b_t-0.7.v
  reg [63:0] pmp_access_type_reg_2;
  reg pmp_access_type_en_2; 
  reg pmp_access_type_reg_1, pmp_access_type_new_1;
  reg [63:0] pmp_access_type_reg_3;
  reg pmp_access_type_en_3; 
  reg pmp_access_type_reg_4, pmp_access_type_new_4;
  reg [63:0] pmp_access_type_reg_5;
  reg pmp_access_type_en_5; 
  reg pmp_access_type_reg_6, pmp_access_type_new_6;
  reg [63:0] pmp_access_type_reg_7;
  reg p
========================================================
example19_i-b_t-0.7.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_mask_reg, pmp_mask_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_mask_en; 
// FIX:
  reg pmp_mask_en; 

  reg [63:0] pmp_data_reg, pmp_data_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_data_en; 
// FIX:
  reg pmp_data_en; 

  reg [1:0] pmp_write_reg, pmp_write_new; 
  reg pmp_write_en; 

  //// Internal Registers


  reg [63:0] rd_p
========================================================
example0_i-b_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  
  reg [7:0] status_reg;
  
  //// State Registers

  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg; 

  localparam CTRL_DONE_NO_RUN = { 5'd5,5'd5,5'd5,5'd5,5'd5,5'd5,5'd5,5'd5 };
  wire [7:0] DONE = ctrl_reg === CTRL_DONE ? CTRL_DONE_NO_RUN: dma_status_reg; 
  reg [7:0]                  dma_status_reg;
  reg [7:0] pmp_status_reg;
  reg [7:0] status_reg_buf;

  //***
========================================================
example1_i-b_t-0.9.v

  wire [63:0] reg_pmp_addr_reg;
  reg reg_pmp_addr_en;
  
  reg valid_reg = 0; 
  reg valid_next = 0; 
  reg valid_d = 'b0; 

  assign valid_o = valid_reg; 

  // // Connecting from all the LUTs
  reg [7:0] fwft [7:0] = {16'b1, 16'b1, 16'b1, 16'b1, 16'b0, 16'b1, 16'b0, 16'b0};
  assign start_i = (fwft[0] | fwft[1] | fwft[2] | fwft[3] | fwft[5] | fwft[7]) ? start_d[32:
========================================================
example2_i-b_t-0.9.v
  reg pmp_access_type_en; // Set by RD/WR PTE Log entries, reset by Reset
"""

RESET_DELAY = """
  // Delay for reset
  parameter RESET_DELAY = 10;

  localparam reset_delay_counter = RESET_DELAY; // for Reset delay

  reg reset_d;
  reg [28-1:0] reset_d_cnt; 

  always @(posedge clk_i) begin
    if(rst_ni) begin
      reset_d_cnt <= 0;
      reset_d <= 1'h0; 
      reset_delay_counter <= RESET_DELAY;
    
end

end

========================================================
example3_i-b_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  
  reg [63:0] new_dest_addr_reg, new_dest_addr_new; 
  reg new_dest_addr_en; 

  localparam pmpcfg0 = 0;

  localparam pmpcfg1 = 1;
  localparam pmpcfg2 = 2;
  localparam pmpcfg3 = 3;
  localparam pmpcfg4 = 4;
  localparam pmpcfg5 = 5;
  localparam pmpcfg6 = 6;
  localparam pmpcfg7 = 7;
  localparam pmpcfg8 = 8;
  localparam pmpcfg9 = 9;
  localparam pmpcfg10 = 10;
  localparam pmpcfg11 = 11;
  localparam pmpcfg12 = 12;
========================================================
example4_i-b_t-0.9.v
  reg pmp_access_type_en [7:0]; 
  reg pmp_access_addr_reg; // (63:0)
// BUG: Uri gefunden: I/O reg Verzerrung des Matchpulses
//  reg pmp_access_addr_new;
// FIX:
  wire pmp_access_addr_new;
  reg [7:0] pmp_access_addr_reg_lsb; // (7:0)
// BUG: Uri gefunden: I/O reg Verzerrung des Matchpulses
//  reg pmp_access_addr_new_lsb;
// FIX:
  wire pmp_access_addr_new_lsb;
  reg pmp_access_en;

/*
  reg [5:0]  ctrl_reg;
========================================================
example5_i-b_t-0.9.v
  reg [63:0] pmp_access_en_reg, pmp_access_en_new; // enable or not the pmp access
  reg pmp_access_en_en; 

  wire [63:0] pmp_access_addr; // pmp address bus
// TODO: So far the address space we have is only 64bits, the bus needs to be an extension of this
  wire [63:0] pmp_addr_bus;

  //// States defi
========================================================
example6_i-b_t-0.9.v
  reg [1:0] pmp_access_type_en; 

  reg valid_r; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] source_addr_full; 
  wire [DATA_WIDTH-1:0] dest_addr_full; 

  reg [DATA_WIDTH-1:0] mask_lsbs, mask_msbs; 

  //// Internal Components
  wire FSM_pmsqrt_latest_i; 
  wire [DATA_WIDTH-1:0] pmp_sel_d_1, pmp_sel_d_2; 
  // S
  wire pmsqrt_done; 
  wire pmsqrt_valid; 
  reg pmsqrt_valid_r;

  omas_dmam
========================================================
example7_i-b_t-0.9.v
  reg pmp_access_type_en_reg;
  
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  wire valid_new;
  
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0;   
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_new <= CTRL_IDLE; 
      dma_
end

end

========================================================
example8_i-b_t-0.9.v
  wire pmp_access_type_en = 1'b0; 
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_reg, pmp_access_type_new;

  reg [63:0] pmp_addr_at_reg, pmp_addr_at_new; 
  reg [DMA_CTRL_WIDTH-1:0] pmp_addr_at_reg, pmp_addr_at_new;

  //// Internal Signals
  logic [DMA_CTRL_WIDTH-1:0] select_dma_ctrl;
  logic [DMA_CTRL_WIDTH-1:0] select_pmp_ctrl;
  logic [DMA_CTRL_WIDTH-1:0] select_pmp_access_type
========================================================
example9_i-b_t-0.9.v
  reg pmp_access_type_en_reg;

  reg [DATA_WIDTH-1:0]  dma_res = reg [DATA_WIDTH-1:0];
  reg [DATA_WIDTH-1:0]  dma_saved_res = reg [DATA_WIDTH-1:0];

  
  //// Internal I/O Registers
  reg [DMA_CTRL_WIDTH-1:0]  dma_ctrl_joe;
  reg [63:0] pmp_addr_joe;
  reg [63:0] pmp_addr_saved_reg;
  reg [63:0] pmp_addr_saved_joe;
  reg pmp_pmpaddr_mismatch; // Since address and config registers are written as indep
========================================================
example10_i-b_t-0.9.v
  reg pmp_access_type_en_reg, pmp_access_type_en_new; 

  //// Internal Signals
  wire valid_new; 
  wire [DATA_WIDTH-1:0] ctrl; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  wire [7:0] pmpcfg;   
  wire [16-1:0] pmpaddr; // output of the programmable PMP port. The address is used in memory handler

  wire done; 

  wire we_done_o; // pipe AHB_We signal, so that we can clean AHB_We signal before AHB_Done signal

  wire [1:0]  valid_o_status;
  //assign valid_o_status = {riscv::UNPACK
========================================================
example11_i-b_t-0.9.v
  reg pmp_access_type_en; 

  //// Internal States
  wire [DMA_FIFO_LENGTH-1:0] dma_fifo_count;
  
  //// Internal Variables
  reg [DMA_FIFO_LENGTH-1:0] dma_fifo_rd_addr;
  reg [DATA_WIDTH-1:0] dma_fifo_rd_data;

  reg [DATA_WIDTH-1:0] dma_fifo_wr_data;

  reg [DATA_WIDTH-1:0] dma_fifo_empty;

  reg done_flag;
  reg done_check;
  reg dma_ctrl_done;
  reg dma_ctrl_cnt;
  reg dma_ctrl_cnt_en;
========================================================
example12_i-b_t-0.9.v
  reg [63:0] pmp_access_type_reg_arr [0:RISCV_PMP_COUNT-1];

  reg [DATA_WIDTH-1:0] dma_ctrl_valid; 
  reg dma_ctrl_valid_orig; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid, dma_ctrl_new_valid; 
  reg dma_ctrl_en_valid; 

  reg [63:0] pmp_addr_reg_valid, pmp_addr_new_valid;
  reg pmp_addr_en_valid;  

  reg [63:0] pmp_access_type_reg_valid, pmp_access_type_new_valid;
  reg pmp_access_type_en_valid
========================================================
example13_i-b_t-0.9.v
  reg pmp_access_type_en_final; 
  reg securityExtensions_reg; // riscv_v2_mode.Y
  reg rvfi_en; // riscv_v2_interrupts.Y
  reg [127:0] faults;
  reg [63:0] proc_id;

  reg abort;

  wire done_out;
  wire valid_out;
  wire invalid_out;

  //// Main Module
  riscv_dma riscv_dma_core(
    .clk_i(clk_i),
    .rst_ni(rst_ni), 
    .start_i(start_i), 
    .length_i(length_i), 
    .source_addr_lsb_i(source_addr_lsb_i
========================================================
example14_i-b_t-0.9.v
  reg pmp_access_type_en;  

  reg [16-1:0] pmptlr_reg, pmptlr_new; 
  reg pmptlr_en; 

  reg [16-1:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en;  

  reg [53:0] s
========================================================
example15_i-b_t-0.9.v
  reg [63:0] pmpaddr_new2;
  reg pmpaddr_en2;
  reg pmpaccess_new2;  
  reg pmpaccess_en2;
	
// BUG: Uninitialized Value on Reset for registers holding interrupt handle pointers.
//  reg [63:0] ***;
	
  reg [DMA_TYPE_WIDTH-1:0] src_type_reg,  src_type_new; 
  reg dest_type_reg,  dest_type_new;

  reg [DMA_TYPE_WIDTH-1:0] src_type_new3;
  reg dest_type_new3;
  reg done_new3;
  reg done_en3;

  reg done_valid_new; 
  reg done_valid_en; 

  reg done_
========================================================
example16_i-b_t-0.9.v
  reg pmp_access_type_en [0:0];
  
  wire valid_new = VALID_IDLE;
  reg valid_reg [2:0]; // riscv::VALID_INVALID, riscv::VALID_IDLE, riscv::VALID_LOAD, riscv::VALID_STORE, riscv::VALID_DONE;

  //// Other

  always @(posedge clk_i) begin 
    pmpaddr_new           <= pmp_addr_reg;  
    pmp_addr_reg          <= pmp_addr_reg + (pmp_addr_en ? pmp_addr_new : 0);
  
end

========================================================
example17_i-b_t-0.9.v
  reg [3:0] pmp_access_type_en;  

  //// State Machine

  logic [8:0] state;

  logic [DMA_CTRL_WIDTH-1:0] ctrl, ctrl_new; 
  wire [DMA_CTRL_WIDTH-1:0] ctrl_next; 

  begin

//////////////////////////////////////////////////////////////////////////
//
// Initialize Example
//
//////////////////////////////////////////////////////////////////////////

      process (clk_i, rst_ni, num_rqsts) 
      begin 
          if (rst_ni) 
          begin
              state <= STATE_IDLE;
              ctrl <= CTRL_IDLE;
              done_d <= 0;
              valid_o <= 0;
              pmpaddr_i <= 0;
              pmpcfg_i <= {
end

end

end

========================================================
example18_i-b_t-0.9.v
  reg pmp_access_type_en = 1'b0; 

  reg valid_reg = 0;
  reg valid_new;
  
  reg valid_r = 0;
  reg valid_w = 0;

  wire abort_i = (done_i == CTRL_ABORT) ? 1'b1 : 1'b0; 

  wire valid_dma_data_i = 
    riscv::dma_read_data_valid_i | valid_r;
  wire valid_dma_ctrl_i = 
    start_i | length_i | source_addr_msb_i | source_addr_lsb_i | dest_addr_msb_i | dest_addr_lsb_i | done_i | abort_i | 
    (pmpcfg_i != 2'b0) |
========================================================
example19_i-b_t-0.9.v
  reg [63:0] pmp_disable_reg, pmp_disable_new;
  reg pmp_disable_en; 

  reg done_new, done_reg; 


  reg [63:0]  csr_abi_rs1_addr_reg, csr_abi_rs1_addr_new;
  reg [63:0]  csr_abi_rs2_addr_reg, csr_abi_rs2_addr_new; 
  reg [63:0]  csr_abi_rd_addr_reg, csr_abi_rd_addr_new;
  reg csr_abi_rd_en, csr_abi_rd_en_new; 
  reg csr_abi_rd_addr_valid; 

  reg [63:0]  csr_ctrl_reg, c
========================================================
example0_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_
========================================================
example1_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg [63:0] pmp_addr_reg_old; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old; 
  reg [63:0] pmp_addr_reg_old_old; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old_old; 
  reg [63:0] pmp_addr_reg_old_old_old; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old_old_old; 
  reg
========================================================
example2_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

========================================================
example3_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

========================================================
example4_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new_new; 

========================================================
example5_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

========================================================
example6_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_access_reg, pmp_access_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg [63:0] pmp_addr_reg_old;
  reg [7:0] pmp_access_reg_old; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old; 
  reg [63:0] pmp_
========================================================
example7_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg pmp_addr_reg_en_new_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en_new; 
 
========================================================
example8_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_
========================================================
example9_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new; 
  reg pmp_addr_en_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en, dma_ctrl_reg_en_new; 
  reg dma_ctrl_reg_en_en; 

  reg [63:0] pmp_addr_reg_en, pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_en; 

  reg [63:0] pmp_addr_en_reg_en, pmp_addr_en_reg_en_new; 
  reg pmp_addr_en_reg_en_en;
========================================================
example10_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg [63:0] pmp_addr_en_new; 
  reg [63:0] pmp_addr_en_reg; 
  reg [63:0] pmp_addr_en_new_reg; 
  reg [63:0] pmp_addr_en_reg_new; 
  reg [63:0] pmp_addr_en_reg_new_reg; 
  reg [63:0] pmp_addr_en_reg_new_reg_new; 
  reg [63:0] pmp_addr_en_reg_new_reg_new_reg; 
  reg [63:0] pmp_addr_en_reg_new_reg_new_
========================================================
example11_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg pmp_access_type_new_en; 
  reg pmp_access_type_reg_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg dma_ctrl_new_en; 

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_reg_en; 

  reg [DATA_WIDTH-1:0] valid_reg_new; 
  reg valid_reg_new_en; 

  reg [DATA_WIDTH-1:0] valid_reg_
========================================================
example12_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [DATA_WIDTH-1:0] start_reg_en; 
  reg [DATA_WIDTH-1:0] length_reg_en; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg_en; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg_en; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg_en; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_
========================================================
example13_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [63:0] pmp_addr_reg_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_new_new_new; 
  reg
========================================================
example14_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_access_reg, pmp_access_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg [63:0] pmp_addr_reg_old;
  reg [7:0] pmp_access_reg_old; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old; 
  reg [63:0] pmp_
========================================================
example15_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_en_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_addr_en_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_en_reg_en; 
  reg [63:0] pmp_access_type_reg_en; 
  reg [63:0] pmp
========================================================
example16_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg [63:0] pmp_addr_en_new; 
  reg [63:0] pmp_addr_en_reg; 
  reg [63:0] pmp_addr_en_new_reg; 
  reg [63:0] pmp_addr_en_new_reg_next; 
  reg [63:0] pmp_addr_en_reg_next; 
  reg [63:0] pmp_addr_en_new_reg_next_next; 
  reg [63:0] pmp_addr_en_reg_next_next; 
  reg [63:0] pmp_addr_en_new_reg_next_next_next; 

========================================================
example17_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new_new_new_new_new; 
  reg [63:0] pmp_addr_reg_en_new_
========================================================
example18_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_next; 
  reg [63:0] pmp_addr_reg_en_next_new; 
  reg [63:0] pmp_addr_reg_en_next_next; 
  reg [63:0] pmp_addr_reg_en_next_next_new; 
  reg [63:0] pmp_addr_reg_en_next_next_next; 
  reg [63:0] pmp_addr_reg_en_next_next_next_new; 
  reg [63:0] pmp_
========================================================
example19_i-c_t-0.1.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [63:0] pmp_addr_reg_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_new_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en_new_new_new; 
  reg
========================================================
example0_i-c_t-0.3.v
  reg pmp_access_type_en; 

  reg [DATA_WIDTH-1:0]  valid_d; 
  reg [DATA_WIDTH-1:0]  valid_reg; 
  reg valid_reg_en; 
  reg valid_reg_next; 

  //// Control Logic
  always @(posedge clk_i) begin
    if(rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_new <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_addr_new <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_NONE; 
      pmp_access_type_new <= riscv::ACCESS_NONE; 
end

end

========================================================
example1_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg dma_ctrl_en_valid; 
  reg [63:0] pmp_addr_reg_valid; 
  reg pmp_addr_en_valid; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  reg dma_ctrl_en_valid_new; 
  reg [63:0] pmp_addr_reg_valid_new; 
  reg pmp_addr_en_valid_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new_next; 
  reg
========================================================
example2_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new;
  reg pmp_addr_valid_en;
  reg [63:0] pmp_addr_valid_reg_new;
  reg pmp_addr_valid_en_new;
  reg [63:0] pmp_addr_valid_reg_new_new;
  reg pmp_addr_valid_en_new_new;
  reg [63:0] pmp_addr_valid_reg_new_new_new;
  reg pmp_addr_valid_en_new_new_new;
  reg [63:0] pmp_addr_valid_reg_new_new_new_new;
  reg pmp_addr_valid_en_new
========================================================
example3_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_d; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg dma_ctrl_en_d; 
  reg [63:0] pmp_addr_reg_d;
  reg pmp_addr_en_d;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_q; 
  reg dma_ctrl_en_q; 
  reg [63:0] pmp_addr_reg_q;
  reg pmp_addr_en_q;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_q_new; 
========================================================
example4_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 
  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_en_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_addr_en_en; 
  reg pmp_addr_en_en_new; 

  //// DMA Control Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_new <= CTRL_IDLE;
      dma_ctrl_
end

end

========================================================
example5_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 

  //// Internal Signals

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  wire [63:0] pmp_addr_reg_valid_new; 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new_valid; 
  wire [63:0] pmp_addr_reg_valid_new_valid; 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new_next
========================================================
example6_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_old; 
  reg dma_ctrl_en_new_old; 
  reg [63:0] pmp_addr_reg_new_old;
  reg pmp_addr_en_new_old;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg dma_ctrl_en
========================================================
example7_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [16-1:0] pmp_addr_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg [63:0] pmp_addr_reg_next; 
  reg [16-1:0] pmp_addr_en_next; 
  reg pmp_access_type_reg_next; 
  reg pmp_access_type_en_next; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next_next; 
  reg [63:0] pmp_addr_reg_next_next; 
  reg [16-1:0] pmp_addr_en_next_next; 

========================================================
example8_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [63:0] pmp_addr_reg_new; 
  reg pmp_addr_en_new; 

  reg [63:0] pmp_addr_reg_new_d; 
  reg pmp_addr_en_new_d; 

  reg [63:0] pmp_addr_reg_new_e; 
  reg pmp_addr_en_new_e; 

  reg [63:0] pmp_addr_reg_new_f; 
  reg pmp_addr_en_new_f; 

  reg [63:0] pmp_addr_reg_new_g; 
  reg pmp_addr_en_new_g; 


========================================================
example9_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] pmp_data_reg, pmp_data_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_data_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_data_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg [63:0] pmp_addr_reg_old;
  reg [DATA_WIDTH-1:0] pmp_data_reg_old;

  //// Internal Signals
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_i
========================================================
example10_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_2_0;
  reg [1:0] pmp_access_type_new_2_0;
  reg pmp_access_type_en_2_0;

  reg [63:0] pmp_addr_reg_2_0, pmp_addr_new_2_0;
  reg pmp_addr_en_2_0; 

  reg [1:0] pmp_access_type_reg_3_2;
  reg [1:0] pmp_access_type_new_3_2;
  reg pmp_access_type_en_3_2;

  reg [63:0] pmp_addr_reg_3_2, pmp_addr_new_
========================================================
example11_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [63:0] pmp_addr_reg_new; 
  reg pmp_addr_en_new; 
  reg pmp_addr_en_new_new; 

  reg [63:0] pmp_addr_reg_new_new; 
  reg pmp_addr_en_new_new_new; 
  reg pmp_addr_en_new_new_new_new; 

  reg [63:0] pmp_addr_reg_new_new_new; 
  reg pmp_addr_en_new_new_new_new; 
  reg pmp_addr_en_new_new_new_new_new; 

  reg [63:0]
========================================================
example12_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_new_en; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0]  source_addr_lsb_d_new; 
  wire [DATA_WIDTH-1:0]  source_addr_msb_d_new; 
  wire [DATA_WIDTH-1:0]  dest_addr_lsb_d_new; 
  wire [DATA_WIDTH-1:0]  dest
========================================================
example13_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg [63:0] pmp_addr_reg_new; 

  reg [63:0] pmp_addr_reg_new_pmp_addr_i; 
  reg [63:0] pmp_addr_reg_new_pmp_addr_new_i; 
  reg [63:0] pmp_addr_reg_new_pmp_addr_new_pmp_addr_i; 

  reg [63:0] pmp_addr_reg_new_pmp_addr_new_pmp_addr_new_i; 
  reg [63:0]
========================================================
example14_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_addr_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_data_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_data_en; 
  reg [63:0
========================================================
example15_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [1:0] pmp_access_type_reg_en;
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_new; 
  reg pmp_addr_reg_en_new_new_en; 
  reg [63:0] pmp_addr_reg_en_new_new_new; 
  reg pmp_addr_reg_en_new_new_new_en; 
  reg [63:0] p
========================================================
example16_i-c_t-0.3.v
  wire pmp_access_type_en; 
  assign pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_addr_reg_en;
  reg [63:0] pmp_addr_reg_en_new;
  reg [63:0] pmp_addr_reg_en_d;
  reg [63:0] pmp_addr_reg_en_new_d;

  reg [63:0] pmp_access_reg_en;
  reg [63:0] pmp_access_reg_en_new;
  reg [63:0] pmp_access_reg_en_d;
  reg [63:0] pmp_access_reg_en_new_d;

  reg [63:0] pmp_access_reg_en_
========================================================
example17_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_access_reg, pmp_access_new;
  reg pmp_access_en; 
  
  reg [DATA_WIDTH-1:0] dma_ctrl_reg_o; 
  reg [63:0] pmp_addr_reg_o; 
  reg [7:0] pmp_access_reg_o; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_d_mux_sel; 
  wire [DATA_WIDTH-1:0] length_d_mux_sel;
  wire [DATA_WIDTH-1:0] source_addr_lsb_d_mux_sel; 
  wire [DATA_WIDTH
========================================================
example18_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_access_reg, pmp_access_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_en; 

  //// Control Logic

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0
end

end

========================================================
example19_i-c_t-0.3.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  reg [63:0] pmp_addr_reg_valid_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new_en; 
  reg [63:0] pmp_addr_reg_valid_new_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new_en_next; 
  reg
========================================================
example0_i-c_t-0.5.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg dma_ctrl_en_valid; 

  reg [63:0] pmp_addr_reg_valid;
  reg pmp_addr_en_valid;  

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  reg dma_ctrl_en_valid_new; 

  reg [63:0] pmp_addr_reg_valid_new;
  reg pmp_addr_en_valid_new;  
========================================================
example1_i-c_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  reg [63:0] pmp_access_type_en_new; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new; 
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new; 
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_wdata_reg, pmp_access_wdata_new; 
  reg pmp_access_wdata_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new; 
  reg pmp_access_mask_en;
========================================================
example2_i-c_t-0.5.v
  reg [63:0] pmp_access_type_reg_default;
  reg pmp_access_type_en; 
  reg pmp_access_type_default; 
  reg pmp_access_type_default_en; 

  reg [63:0] pmp_addr_reg_default;
  reg pmp_addr_en_default;  
 
  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] done_d_new; 
  reg [63:0] pmp_addr_reg_default_new;
  reg pmp_addr_en_default_new;  
  reg [63:0] pmp_addr_reg_default_en;  
  reg pmp_addr_en_default_en;
========================================================
example3_i-c_t-0.5.v
  reg pmp_access_type_en;  
  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en, dma_ctrl_reg_en_new; 
  reg [63:0] pmp_addr_reg_en, pmp_addr_reg_en_new; 
  reg pmp_access_type_reg_en, pmp_access_type_reg_en_new;
  reg [DATA_WIDTH-1:0]  valid_d; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_r; 
  wire [DATA_WIDTH-1:0] length_r;

========================================================
example4_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en;  

  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_valid_d; 
  reg [63:0] pmp_addr_valid_d; 

  //// Internal Signals
  wire [DATA_WIDTH-1:0] source_addr_d; 
  wire [DATA_WIDTH-1:0] dest_addr_d; 
  wire [DATA_WIDTH-1:0] source_addr_next; 
  wire [DATA_WIDTH-1:0] dest_addr_next; 
  wire [DATA_WIDTH-1:0] source
========================================================
example5_i-c_t-0.5.v
  reg pmp_access_type_en;

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_d_reg; 
  wire [DATA_WIDTH-1:0] length_d_reg;
  wire [DATA_WIDTH-1:0] source_addr_lsb_d_reg; 
  wire [DATA_WIDTH-1:0] source_addr_msb_d_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_d_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_d_reg; 
  wire [DATA_WIDTH-1:0] done_d_reg; 

  wire [DMA_CTRL_WIDTH-1
========================================================
example6_i-c_t-0.5.v
  reg pmp_access_type_en; 
  initial begin
    pmp_access_type_reg = riscv::ACCESS_READ;
    pmp_access_type_new = riscv::ACCESS_READ;
    pmp_access_type_en  = 1'b1;
  
end

========================================================
example7_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg we_pmp_access_type_reg, we_pmp_access_type_new; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] start_reg, start_new; 
  reg start_en; 

  reg [DATA_WIDTH-1:0] length_reg, length_new; 
  reg length_en; 

  reg [DATA_WIDTH-1
========================================================
example8_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg [2:0] pmp_access_type_reg_d;
  reg pmp_access_type_reg_en; 

  reg [63:0] pmp_addr_reg_d;
  reg pmp_addr_reg_en;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg dma_ctrl_reg_en; 

  reg [63:0] pmp_addr_reg_d;
  reg pmp_addr_reg_en;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg dma_ctrl_reg_en; 

  reg [63:0] pmp_addr_
========================================================
example9_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_last, pmp_addr_new_last; 
  reg [63:0] pmp_addr_reg_last_2, pmp_addr_new_last_2; 
  reg pmp_addr_en_last; 
  reg pmp_addr_en_last_2; 
  reg pmp_access_type_reg_last, pmp_access_type_new_last; 
  reg pmp_access_type_reg_last_2, pmp_access_type_new_last_2; 
  reg pmp_access_type_en_last; 
  reg pmp_access_type_en_last_2; 

  reg [63:0] pmp_addr_
========================================================
example10_i-c_t-0.5.v
  reg pmp_access_type_en_reg; 
  reg pmp_access_type_en_new; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_new; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [7:0] pmpcfg_reg_en; 
  reg [7:0] pmpcfg_reg_new; 
  
  reg [16:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [16:0] pmpaddr_reg_en; 
  reg [16:0] pmpaddr_reg_new; 

  
========================================================
example11_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_cfg_en; 
  
  reg [7:0] pmp_cfg_reg_new, pmp_cfg_reg_old;
  reg [63:0] pmp_addr_reg_new, pmp_addr_reg_old;
  
  reg [7:0] pmp_cfg_reg_old_new, pmp_cfg_reg_old_old;
  reg [63:0] pmp_addr_reg_old_new,
========================================================
example12_i-c_t-0.5.v
  reg pmp_access_type_en;
  reg [63:0] pmp_addr_en; 
  reg pmp_addr_en; 
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg pmp_addr_en; 
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg pmp_addr_en; 
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg pmp_addr_en; 
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg pmp_addr_en; 

========================================================
example13_i-c_t-0.5.v
  reg pmp_access_type_en
  = (riscv::get_pmp_status(riscv::PMP_ADDRESS_LOW_BASE_ADDRESS) == 0x0) &&
    (riscv::get_pmp_status(riscv::PMP_ADDRESS_HIGH_BASE_ADDRESS) == 0x0) &&
    (riscv::get_pmp_status(riscv::PMP_ADDRESS_LOW_LIMIT_ADDRESS) == 0x0) &&
    (riscv::get_pmp_status(riscv::PMP_ADDRESS_HIGH_LIMIT_ADDRESS) == 0x0) &&
    (riscv::get_pmp_status(riscv::PMP_AD
========================================================
example14_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DMA_CTRL_WIDTH-1:0] valid_d_new; 
  reg valid_d_en; 

  reg [63:0] pmp_addr_valid_d; 
  reg pmp_addr_valid_d_en; 

  wire [DATA_WIDTH-1:0] valid_o_new; 
  wire valid_o_en; 

  reg [63:0] pmp_addr_valid_o; 
  reg pmp_addr_valid_o_en; 

  reg [63:0] pmp_addr_valid_o_new; 
  reg pmp_addr_valid_o_en; 


========================================================
example15_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
  reg pmp_addr_cfg_en;

  reg [7:0] pmp_addr_cfg_reg_next, pmp_addr_cfg_new_next;
  reg pmp_addr_cfg_en_next;

  reg [7:0] pmp_cfg_reg_next, pmp_cfg_new_next;
  reg pmp_cfg_en_next;
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next, dma_ctrl_new
========================================================
example16_i-c_t-0.5.v
  reg [63:0] pmp_access_type_reg_d, pmp_access_type_new_d;
  reg pmp_access_type_en_d; 
  reg [63:0] pmp_addr_reg_d, pmp_addr_new_d;
  reg pmp_addr_en_d;  
  reg pmp_access_type_reg_e, pmp_access_type_new_e; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en_e; 
  reg [63:0] pmp_addr_reg_e, pmp_addr_new_e;
  reg pmp_addr_en_e;  
  reg [63:0] pmp_addr_reg_f, p
========================================================
example17_i-c_t-0.5.v
  wire pmp_access_type_en = 1'b1; 

  wire [DATA_WIDTH-1:0] r_addr_lsb_reg, r_addr_lsb_new; 
  wire [DATA_WIDTH-1:0] r_addr_msb_reg, r_addr_msb_new; 
  wire [DATA_WIDTH-1:0] w_addr_lsb_reg, w_addr_lsb_new; 
  wire [DATA_WIDTH-1:0] w_addr_msb_reg, w_addr_msb_new; 

  wire [DATA_WIDTH-1:0] r_data_reg, r_data_new; 
  wire [DATA_WIDTH-1:0] w_data_reg, w_data
========================================================
example18_i-c_t-0.5.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 
  reg pmp_access_type_en_new_next; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_reg_new, pmp_addr_reg_next; 
  reg [7:0] pmp_cfg_reg_new, pmp_cfg_reg_next; 

  reg [7:0] pmp_access_type_reg_new, pmp_access_type_reg_next; 

  reg [7:0] pmp_addr_reg_next_next; 
  reg [7:0] pmp_cfg_reg_next
========================================================
example19_i-c_t-0.5.v
  reg pmp_access_type_en_reg; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_reg; 
  reg [64:0] pmp_addr_reg_reg; 
  reg pmp_access_type_reg_reg; 
  reg pmp_access_type_new_reg; 
  reg [63:0] pmp_addr_new_reg; 
  reg pmp_addr_en_reg; 
  reg pmp_access_type_en_reg_reg; 
  reg pmp_access_type_en_new_reg; 
  reg pmp_access_type_en_reg_new; 
  reg [63:0] pmp_addr_reg_new; 
  reg pmp_addr_en
========================================================
example0_i-c_t-0.7.v
  reg pmp_access_type_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg pmp_addr_reg_old; 
  reg [63:0] pmp_addr_reg_old_new; 
  reg [63:0] pmp_access_type_reg_old_new; 
  reg pmp_addr_reg_old_valid; 
  reg pmp_access_type_reg_old_valid; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old_old; 
  reg pmp_addr_reg_old_old; 
  reg [63:0] pmp_addr_reg_old_old_new; 
  reg [63
========================================================
example1_i-c_t-0.7.v
  reg [63:0] pmp_access_type_reg_init;
  reg pmp_access_type_en; 

  reg dma_valid_d; 
  reg dma_valid_new; 

  reg dma_go_d; 
  reg dma_go_new;  
 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg [63:0] pmp_addr_reg_d; 
  reg [63:0] pmp_access_type_reg_d; 
  reg dma_go_d_d; 
  reg dma_valid_d_d; 


  reg [7:0] [16-1:0] pmpcfg_d;   
  reg [63:0
========================================================
example2_i-c_t-0.7.v
  reg pmp_access_type_en;

  //// Inputs

  assign clk_i = state_r == riscv::STATE_IDLE ? riscv::CLK_0 : riscv::CLK_1; 
  assign rst_ni = state_r >= riscv::STATE_CHECK_LOAD ? 0 : 1; 

  assign valid_o = (state_r >= riscv::STATE_CHECK_STORE) && (state_r < riscv::STATE_DONE); 


  //// Logic

  // Avoid overwriting state_r if the state is not done.
  assign done_i = state_r >= riscv::STATE_DONE ? 1 : 0;
  assign done_d = done_i;
  assign valid_o = done_i;

  //// Assign registers
========================================================
example3_i-c_t-0.7.v
  reg pmp_access_type_en;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

  reg [16-1:0] pmp_addr_vld_reg, pmp_addr_vld_new;
  reg pmp_addr_vld_en;

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start; 
  wire [DATA_WIDTH-1:0] length;
  wire [DATA_WIDTH-1:0] source_addr_lsb; 
  wire [DATA_WIDTH-1:0] source_addr_msb; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb; 
  wire [DATA_W
========================================================
example4_i-c_t-0.7.v
  reg [63:0] pmp_access_register_reg, pmp_access_register_new;
//  reg pmp_access_register_en;
  reg pmp_access_type_en;
  reg pmp_access_register_en;

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
//  reg pmp_access_data_en;

  reg [63:0] pmp_access_data_mask_reg, pmp_access_data_mask_new;
//  reg pmp_access_data_mask_en;

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
//  reg pmp_access_addr_en;

  reg [63:0] pmp_access_addr
========================================================
example5_i-c_t-0.7.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_last; 
  reg [63:0] pmp_addr_reg_last;
  reg [63:0] pmp_addr_reg_last_2;
  reg [63:0] pmp_addr_reg_last_3;
  reg [63:0] pmp_addr_reg_last_4;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_type_reg_last; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_type_reg_last; 
  reg [63:0] pmp_addr_reg_last_
========================================================
example6_i-c_t-0.7.v
  reg pmp_access_type_en;
  reg [63:0] pmp_access_value_reg, pmp_access_value_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_value_en;
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg pmp_access_value_en;
  reg pmp_access_valid; 
  reg [63:0] pmp_config_reg, pmp_config_new; 
  reg pmp_config_en; 
  
  reg [DATA_WIDTH-1:0] data_reg;
  reg [DATA_WIDTH-1:0] valid_reg; 
  reg data_en; 

  reg ctrl; 

========================================================
example7_i-c_t-0.7.v
reg pmp_access_type_en;
assign pmp_access_type_en = '1'b1;

  reg we_reg;
  reg pmp_we_new; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; // riscv::PMP_A and riscv::PMP_R
  reg pmp_cfg_en; // [7:0] pmp_cfg_reg, pmp_cfg_new; // riscv::PMP_A and riscv::PMP_R
  reg pmp_cfg_en_new; 
  
  //// Internal Signals
  wire [DATA_WIDTH-1:0] start_load_
========================================================
example8_i-c_t-0.7.v
  // reg pmp_access_type_en; 
  wire pmp_access_type_en; 
  assign pmp_access_type_en = 1; 
  
  reg [63:0] pmp_addr_old; 
  reg [63:0] pmp_addr_new; 
  reg [63:0] pmp_addr_tmp;
  reg [63:0] pmp_addr_tmp_old; 
  reg [63:0] pmp_addr_tmp_new; 

  reg [63:0] pmp_addr_reg_old, pmp_addr_reg_new; 
  reg [63:0] pmp_addr_reg_tmp;
  reg [63:0] pmp_addr_reg_tmp_old; 
  reg [63:0] p
========================================================
example9_i-c_t-0.7.v
  reg pmp_access_type_en; 
  reg pmp_access_en = 0; 
  reg pmp_access_busy = 0; 
  reg [32-1:0] pmp_access_addr_reg, pmp_access_addr_reg1, pmp_access_addr_reg2;
  assign pmp_access_addr = pmp_access_addr_reg;

  reg dma_wait_for_pmp_access; 
  reg dma_pmp_access_type;  
  reg dma_wait_for_pmp_access_d1; 
  reg dma_pmp_access_type_d1;  
  reg dma_wait_for_pmp_access_d2; 
  reg dma_pmp_access_type_d2;  
========================================================
example10_i-c_t-0.7.v
  reg [63:0] pmp_access_type_reg_init;
  initial begin
    pmp_access_type_reg_init[63:0] = 'h0;
  
end

========================================================
example11_i-c_t-0.7.v
  reg pmp_access_type_en;  
  
  //// assign registers to their I/O
  assign start_o = start_d;
  assign length_o = length_d;
  assign source_addr_lsb_o = source_addr_lsb_d;
  assign source_addr_msb_o = source_addr_msb_d; 
  assign dest_addr_lsb_o = dest_addr_lsb_d;
  assign dest_addr_msb_o = dest_addr_msb_d; 
  assign done_o = done_d; 
  assign valid_o = done_d;
  
  //// DMA Control
  assign dma_ctrl_reg = dma_ctrl_new; 
  assign dma_ctrl_en = dma_ctrl_reg
========================================================
example12_i-c_t-0.7.v
  reg [63:0] start_addr_reg, start_addr_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg start_addr_en; 

  reg [63:0] length_reg, length_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg length_en; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [63:0] source_addr_lsb_reg, source_addr_lsb_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
//  reg source_addr_lsb_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [63:0] source_addr_
========================================================
example13_i-c_t-0.7.v
  reg pmp_access_type_en, pmp_access_type_valid; 
  //reg [63:0] pmp_addr_reg, pmp_addr_new; 
  //reg pmp_addr_en; 
  reg pmp_access_en;
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en;
  reg pmp_write_en;

  reg [63:0] addr_reg, addr_new; 
  reg addr_en; 
  reg addr_valid; 

  reg [63:0] data_reg, data_new; 
  reg data_en; 
  reg data_valid;
  reg data_ready_master;
  reg data_ready_slave; 

  reg [63
========================================================
example14_i-c_t-0.7.v
  reg pmp_access_type_en; 

  reg valid_d;

  reg [DATA_WIDTH-1:0] source_addr, dest_addr;

  //// DMA Control Logic
  
  always @(posedge clk_i) begin

    if (!rst_ni) begin
      dma_ctrl_reg <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
      valid_d <= 0;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= 0;
    
end

end

========================================================
example15_i-c_t-0.7.v
  localparam pmp_access_type_en = 1'b1; 
  reg pmp_access_type_en; 

  wire [DATA_WIDTH-1:0] data_o;
  reg [7:0] _tmp_0;
  reg _tmp_1;
  reg _tmp_2;
  reg _tmp_3;
  reg _tmp_4;
  reg _tmp_5;
  reg _tmp_6;
  reg _tmp_7;
  reg _tmp_8;
  reg _tmp_9;
  reg _tmp_10;
  reg _tmp_11;
  reg _tmp_12;
  reg _tmp_13;
  reg _tmp_14;
  reg _tmp_15;
  reg _tmp_16;
  reg _tmp_17;

========================================================
example16_i-c_t-0.7.v
  reg pmp_access_type_en = 0;

  //// Control Logic
  always @(posedge clk_i) begin
    if(rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_new <= CTRL_IDLE;
      dma_ctrl_en <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
      pmp_addr_en <= 0;
      pmp_access_type_
end

end

========================================================
example17_i-c_t-0.7.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = 0;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Sequential Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0;
      dma_ctrl_new <= CTRL_IDLE;
      dma_ctrl_reg <= dma_ctrl_new;
end

end

========================================================
example18_i-c_t-0.7.v
  reg pmp_access_type_en; 
  reg pmp_access_type_reg_valid;
  assign pmp_access_type_reg_valid = 1; 
  assign pmp_access_type_en = pmp_access_type_reg_valid; 

  reg [63:0] pmp_addr_reg_valid, pmp_addr_reg_valid_new;
  assign pmp_addr_reg_valid = 1; 
  assign pmp_addr_reg_valid_new = pmp_addr_reg_valid; 
  
  //// DMA Read
  wire [DATA_WIDTH-1:0] dma_read_addr_valid; 
  wire [DATA_WIDTH-1:0] dma_read_addr_ready; 
  wire [DATA_WID
========================================================
example19_i-c_t-0.7.v
  reg pmp_access_type_en = 1'b0; 

  reg valid_reg; 
  reg [15:0] status_reg; 
  reg we_reg; 
  reg [63:0] pmp_addr_reg_set; 
  reg [7:0] [16-1:0] pmpcfg_reg; 

  //// Internal Signals
  
  wire [DATA_WIDTH-1:0] start_r; 
  wire [DATA_WIDTH-1:0] length_r;
  wire [DATA_WIDTH-1:0] source_addr_lsb_r; 
  wire [DATA_WIDTH-1:0] source_addr_msb_r; 
  wire [DATA_WIDTH-1:0] dest_addr_ls
========================================================
example0_i-c_t-0.9.v
  reg pmp_access_type_en; 
  reg dma_ctrl_valid_reg;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [DATA_WIDTH-1:0] dma_dest_reg, dma_dest_new;
// Ensure that the security sensitive registers are initialized to a valid value on reset.
// FIX:
  reg [DATA_WIDTH-1:0] dma_dest_reg, dma_dest_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_addr_reg, pmp_access_addr_new;
// Ensure that the security sensitive registers are initialized to a valid value on reset.
// FIX:
  reg pmp_access_addr_reg, pmp_access_addr_new
========================================================
example1_i-c_t-0.9.v
  logic pmp_access_type_en; 
  reg [31:0] pmp_access_reg; // 
  reg pmp_access_en; 

  //// Shadow State
  reg [DATA_WIDTH-1:0] start_shadow; 
  reg [DATA_WIDTH-1:0] length_shadow;
  reg [DATA_WIDTH-1:0] source_addr_lsb_shadow; 
  reg [DATA_WIDTH-1:0] source_addr_msb_shadow; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_shadow; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_shadow; 
  reg [DATA_WIDTH-1:0] done_shadow; 

========================================================
example2_i-c_t-0.9.v
  localparam pmp_access_type_on_reset = 'hF8;
  riscv::pmp_access_type_t pmp_access_type_on_reset_val = 'h2hF8;
  reg pmp_access_type_en;
  initial pmp_access_type_en = 'b0;

  reg [63:0] pmprst_reg, pmprst_new;
  reg pmprst_en;
  initially {
      
      with (riscv::pmp_access_t) {
	  if (riscv::IMP_DEF == riscv::PMP_NOACCESS || riscv::IMP_DEF == riscv::PMP_RO) begin
	      pmp_access_type_on_reset_val = 'h0;
	 
end

========================================================
example3_i-c_t-0.9.v
//   Assign a value on reset for the sensitive address and type register.
//    access_permitted_reg
  // Yes, I miss the semicolon.
//   https://stackoverflow.com/questions/23429128/why-use-semicolons-in-riscv-rv-32i-configuration-file
  assign pmp_access_type_reg = 0;
  assign pmp_access_type_new = 1;

  //// Logic
  reg valid_reg = 0; 
  always @(posedge clk_i or posedge rst_ni) begin
    if(rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
     
end

end

========================================================
example4_i-c_t-0.9.v
  reg pmp_access_type_en = 0; 

  reg we_en_reg, we_reg; 

  reg we_state, we_val; 

  //// combinational 

  always @ (posedge clk_i)
  begin 
    if(rst_ni)
    begin
      start_d  <= '0;
      length_d <= '0;
      source_addr_lsb_d  <= '0; 
      source_addr_msb_d  <= '0; 
      dest_addr_lsb_d    <= '0;
      dest_addr_msb_d    <= '0; 
      done_d   <= '0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_new <= CTRL_IDLE; 

end

end

========================================================
example5_i-c_t-0.9.v
// FIX ME: We cannot set the default value on a register this way, because it should 
// be an argument to a named assignment or an instruction assignment (i.e. reg start_d = 1).
//  reg [63:0] pmp_addr_csr_reg = 1'b0; 
  reg pmp_addr_csr_en;  

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [63:0] pmp_access_type_csr_reg = 1'b0; 
// FIX:
// FIX ME: We cannot set the default value on a register this way, because it should 
// be an argument to a named assignment or an instruction assignment (i.e. reg start_d = 1).
//  reg pmp_access_type_csr_en; 
  

========================================================
example6_i-c_t-0.9.v
  reg [63:0] access_reg, access_new;
  reg access_en;

  always @ (posedge clk_i) begin
    if (rst_ni) begin
      valid_d <= 0;
    
end

end

========================================================
example7_i-c_t-0.9.v
  reg pmp_addr_en_reg = 1'h0;
  reg [1:0] pmp_access_type_en_reg = 2'b00;
  //// Module Instantiations
  riscv_cfg cfg_i;
  riscv_pmp_access_cfg pmp_access_cfg_i;
  riscv_pmp_access_dma(.clk_i(clk_i), 
                       .rst_ni(rst_ni), 
                       //.we_pmp_flag(we_flag),
                       .cfg_i(cfg_i),
                       .pmp_access_cfg_i(pmp_access_cfg_i),
                       .pmp_access_type_reg(pmp_access_type_reg), 
                       .pmp_addr_reg
========================================================
example8_i-c_t-0.9.v
  reg [3:0] pmp_access_type_reg_en;
  reg pmp_access_type_en; 

  //// Control logic

  reg [7:0] last_control_state; // the last state of dma_ctrl_reg

  wire [DMA_CTRL_WIDTH-1:0] control_state;

  assign control_state = ~start_i;

  // manage pmpaddr & pmpcfg
  always @(posedge clk_i) begin
    if (we_flag) begin
      pmpaddr_i <= { pmpaddr_i, pmp_addr_reg}; // update pmp_addr_reg
      pmp_addr_reg[31:30] <= pmp_access_type_reg<<3; // update pmp_access_type_reg
      pmp_
end

end

========================================================
example9_i-c_t-0.9.v
  reg pmp_access_type_en; 
  assign pmp_access_type_new.read0 = riscv::ACCESS_NONE; 

  reg [1:0] pmpaddr_vld_next = '00;
  assign pmpaddr_vld_next[1] = ~pmp_access_type_en; 
  assign pmpaddr_vld_next[0] = 0; // no need to set this, as it dep
========================================================
example10_i-c_t-0.9.v
// I would like to assign B0 to the first non-configurable register, so that its
// reset value is known.
// But for now, use a value that is not sensitive to any register settings.
  reg pmp_access_type_en; 
  reg [2:0] pmp_access_en; 

  reg ctrl_reg; 
  reg valid; 
  reg [DATA_WIDTH-1:0] load_data; 
  reg load_data_valid; 
  reg [1:0] store_data; 

  //// Wires
  reg rst_i; 
  reg ack_i; 
  reg [DATA_WIDTH-1:0] data_o; 
  wire [DATA_WIDTH-1:0] data_i; 

  //// Memory Interface
========================================================
example11_i-c_t-0.9.v
  reg [63:0] pmp_access_type_reg_mem; //  $readmemh("../examples/security/pmp/pmp_access_type.mem", pmp_access_type_reg_mem);
  reg [63:0] pmp_access_type_reg_rand; 
  reg pmp_access_type_rand;

  
  //// Connections
  assign valid_o = (dma_ctrl_reg[DMA_CTRL_RDY] && 
                    (dma_ctrl_reg[DMA_CTRL_CTRL_VALID_RAM_R] ||
                     dma_ctrl_reg[DMA_CTRL_CTRL_VALID_RAM_W] ||
                     dma_ctrl_reg[DMA_CTRL_CTRL_VALID_PMP_R]
========================================================
example12_i-c_t-0.9.v
  reg pmp_access_type_en; 
  wire pmp_sec_ctrl_reg;

  reg en_int_d; 
  reg done_rst;

  //// Internal Signals
  reg [7:0] pmp_addr_lsb, pmp_addr_msb; 
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_internal, dma_ctrl_new_internal; 
  reg dma_ctrl_en_internal;
  
  reg [63:0] exec_start_addr_lsb; 
  reg [63:0] exec_start_addr_msb; 
  reg [63:0] exec_
========================================================
example13_i-c_t-0.9.v
  wire pmp_access_type_w0;

  //// State
  localparam IDLE = 2'd0;
  localparam CHECK_LOAD = 2'd1;
  localparam START_LOAD = 2'd2;
  localparam LOAD = 2'd3;
  localparam CHECK_STORE = 2'd4;
  localparam START_STORE = 2'd5;
  localparam STORE = 2'd6;
  localparam DONE = 2'd7;
  localparam ABORT = 2'd8;
  wire [DATA_WIDTH-1:0]  start_o; 
  wire [DATA_WIDTH-1:0]  length_o;
  wire [DATA_WIDTH-1:0]  source_addr_lsb_o; 
  wire [DATA_WIDTH-1
========================================================
example14_i-c_t-0.9.v
  reg pmp_access_type_en_0;
  reg pmp_access_type_en_1;

  reg start;
  reg done;

  //// Internal wire and reg declarations
  wire [DATA_WIDTH-1:0] result; 
  wire [1:0] ctrl; 
  wire [5:0] ctrl_reg; 
  
  reg valid_reg;
  reg valid_out_reg;

  wire [DATA_WIDTH-1:0] valid_reg_vld;
  
//  reg [31:0] ctrl_sreg;
  reg [3:0] ctr; 
  reg [3:0] ctr_reg;
  reg [3:0] ctr_inc; 

  reg [DATA_WIDTH-1:0] d
========================================================
example15_i-c_t-0.9.v
  localparam pmp_access_type_en = 1'b1;

  riscv::pmp_lvalue_t pmp_lvalue_type_reg, pmp_lvalue_type_new; // riscv::LVALUE_SIGNED or riscv::LVALUE_UNSIGNED
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_lvalue_type_en; 
// Ensure that the security sensitive load/store mask register is assigned a value on reset.
// FIX:
  localparam pmp_lvalue_type_en = 1'b1;


  

// Memory Load Stage

  reg [DATA_WIDTH-1:0] start_stage; 
  reg [DATA_WIDTH-1:0] length_stage;
  reg [DATA_WID
========================================================
example16_i-c_t-0.9.v
  wire pmp_access_type_en = (dma_ctrl_reg   == CTRL_LOAD ||
                             dma_ctrl_reg   == CTRL_STORE ||
                             pmp_addr_reg[0:5] == 0b000010);
  reg [1:0] pmp_access_type_reg_d, pmp_access_type_new_d;
  assign pmp_access_type_reg_d = {pmp_access_type_reg[0:1],0};
  assign pmp_access_type_new_d = {pmp_access_type_new[0:1],0};

  reg [1:0] pmp_sel_reg, pmp_sel_new;
  reg pmp_sel_en;
  assign pmp_sel_en = (dma_ctrl_reg
========================================================
example17_i-c_t-0.9.v
  reg [63:0] pmp_access_type_reg_init;
  for( int i = 0; i < 63; i++ ){ 
    pmp_access_type_reg_init[i] = pmp_access_type_reg.write; 
  }
  begin
    pmp_access_type_reg = pmp_access_type_reg_init; // initialization is done outside of loop to avoid uninitialized critical warning
    pmp_access_type_en = 0;  
  
end

========================================================
example18_i-c_t-0.9.v
  int reg_reset_val[DATA_WIDTH/8];
  reg pmp_access_type_en; 
  for (int i = 0; i < (DATA_WIDTH/8); i++)
    reg_reset_val[i] = 0; 
  
  reg pmp_access_status_reg; 
  reg pmp_access_status_new; 
  reg pmp_access_status_en; 
  //reg [7:0] pmpcfg_reg; 
  reg [7:0] pmpcfg_new; 
  reg pmpcfg_en;
  reg valid_reg; 
  reg valid_new; 
  reg valid_en; 
  reg valid_read_en;
  reg mem_done; 

  reg io_wr_count, io_rd
========================================================
example19_i-c_t-0.9.v
  pmp_access_type_reg = riscv::ACCESS_WRITE;
//  pmp_access_type_en = true; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;
  
  reg start_reg;
  localparam start_new = 1; 


  //// Internal Signals
  localparam [63:0] DATA_GEN_MAX =  63'd999999999;
  localparam [63:0] DATA_GEN_MIN =  63'd0;
    
  reg   load_enable;
  reg   store_enable;
  wire  done_reg;
  reg   done_int; 

  logic [DATA_WIDTH-1:0] gen_data;

  //// Logic
  always @(posedge
========================================================
example0_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  assign dma_ctrl_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] start_reg_en; 
  assign start_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] length_reg_en; 
  assign length_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] source_addr_lsb
========================================================
example1_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  assign pmp_cfg_en = rst_ni;

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
  reg pmp_addr_cfg_en; 
  assign pmp_addr_cfg_en = rst_ni;

  reg [7:0] pmp_addr_cfg_reg_lsb, pmp_addr_cfg_new_lsb;
  reg pmp_addr_cfg_en_lsb; 
  assign pmp_addr_cfg_en_lsb = rst_
========================================================
example2_i-d_t-0.1.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_access_type_reg_en; 
  reg [7:0] pmp_access_type_new_en; 

  reg [7:0] pmp_access_type_reg_en_new; 
  reg [7:0] pmp_access_type_new_en_new; 

  reg [7:0] pmp_access_type_reg_en_new_new; 
  reg [7:0] pmp_access_type_new_en_new_new; 

  reg [7:0] pmp_access_type_reg_en_new_new_new; 
  reg [7:0] pmp_access_type_new_en_new_new_new; 

  reg
========================================================
example3_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;
  assign pmp_access_type_new = pmp_access_type_reg;

  reg [63:0] pmp_addr_reg_new, pmp_addr_reg_next;
  reg [63:0] pmp_addr_reg_en;
  assign pmp_addr_reg_new = pmp_addr_reg_next;
  assign pmp_addr_reg_en = rst_ni;
  assign pmp_addr_reg_next = pmp_addr_reg;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;
  assign pmp_cfg_new = pmp_cfg_reg;
========================================================
example4_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
  reg pmp_addr_cfg_en; 

  reg [7:0] pmp_addr_cfg_reg_lsb, pmp_addr_cfg_new_lsb;
  reg pmp_addr_cfg_en_lsb; 

  reg [7:0] pmp_addr_cfg_reg_msb, pmp_addr_cfg_new_msb;
  reg pmp_addr_cfg_en_msb; 

 
========================================================
example5_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  assign dma_ctrl_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] valid_d_new; 
  reg valid_d_en; 

  reg [DATA_WIDTH-1:0] valid_d_reg_en; 
  assign valid_d_reg_en = rst_ni;


========================================================
example6_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [16:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_en_lsb, pmp_addr_en_msb; 

  reg [7:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_lsb, dma_ctrl_
========================================================
example7_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;
  assign pmp_access_type_new = pmp_access_type_reg;

  reg [63:0] pmp_addr_reg_new; 
  assign pmp_addr_reg_new = pmp_addr_reg; 
  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = rst_ni;
  assign pmp_addr_new = pmp_addr_reg_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  assign dma_ctrl_reg_new = dma_ctrl_reg; 
  reg [DMA_CT
========================================================
example8_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_cfg_en; 
  assign pmp_cfg_en = rst_ni;

  reg [16:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg [16:0] pmp_addr_new_lsb, pmp_addr_new_msb; 
  reg pmp_addr
========================================================
example9_i-d_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en; 

========================================================
example10_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  assign dma_ctrl_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] valid_d; 
  reg valid_reg_en; 
  assign valid_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] done_d_reg; 
  reg done_reg_en; 
  assign done_reg_en = rst_ni;

 
========================================================
example11_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni; 

  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = rst_ni; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  assign dma_ctrl_reg_en = rst_ni; 

  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] valid_d_new; 
  reg valid_d_en; 

  reg [DATA_WIDTH-1:0] valid_d_reg_en; 
  assign valid_d_reg_en = rst_
========================================================
example12_i-d_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg pmp_access_type_reg_en; 
  reg pmp_access_type_new_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg dma_ctrl_new_en; 

  reg [DATA_WIDTH-1:0] valid_d; 
  reg valid_reg; 
  reg valid_new; 
  reg valid_reg_en; 
  reg valid_new_en; 

  reg [DATA_WIDTH-1:0] done_reg; 
  reg done_reg
========================================================
example13_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [63:0] pmp_addr_reg_new_next;
  reg pmp_addr_en_new_next;  

  reg [63:0] pmp_addr_reg_next;
  reg pmp_addr_en_next;  

  reg [63:0] pmp_addr_reg_next_next;
  reg pmp_addr_en_next_next;
========================================================
example14_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_next; 
  reg dma_ctrl_en_new_next; 
  reg [63:0] pmp_addr_reg_new_next;
  reg pmp_addr_en_new_next;  

  reg [DMA_CTRL_WIDTH-1:0] dma
========================================================
example15_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [16-1:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_en_lsb, pmp_addr_en_msb; 

  reg [7:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_lsb, dma_
========================================================
example16_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_cfg_en; 
  assign pmp_cfg_en = rst_ni;

  reg [7:0] pmp_cfg_reg_new; 
  reg [16:0] pmp_addr_reg_new; 
  reg [16:0] pmp_addr_reg_new_new; 
  reg [16:0] pmp_addr_reg_new_new_new
========================================================
example17_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  //// Internal Signals
  wire [DATA_WIDTH-1:0] start_q; 
  wire [DATA_WIDTH-1:0] length_q;
  wire [DATA_WIDTH-1:0] source_addr_lsb_q; 
  wire [DATA_WIDTH-1:0] source_addr_msb_q; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_q; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_q; 
  wire [DATA_WIDTH-1:0] done_q; 
  wire [DMA_CTRL_W
========================================================
example18_i-d_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_new_en; 
  reg [63:0] pmp_addr_reg_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_en; 
  reg dma_ctrl_en_new; 

  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_new_en_new; 
  reg [63:0] pmp_addr_reg_en_new_new; 
========================================================
example19_i-d_t-0.1.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new; 
  reg [63:0] pmp_addr_reg_valid_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid_new_valid; 
  reg [63:0] pmp_addr_reg_valid_new_valid; 

  reg [DMA_CTRL_WIDTH-1:0] dma
========================================================
example0_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;
  assign pmp_access_type_reg = pmp_access_type_new; 
  assign pmp_access_type_new = 0; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  reg [7:0] [16-1:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg
========================================================
example1_i-d_t-0.3.v
  reg pmp_access_type_en; 
  pmp_access_type_en = 0;

  reg [63:0] pmp_addr_valid_reg, pmp_addr_valid_new; 
  reg pmp_addr_valid_en; 
  pmp_addr_valid_en = 0;

  reg [63:0] pmp_addr_valid_reg_next; 
  reg pmp_addr_valid_en_next; 
  pmp_addr_valid_en_next = 0;

  reg [63:0] pmp_addr_valid_reg_next_next; 
  reg pmp_addr_valid_en_next_next; 
  pmp_addr_valid_en_next_next = 0;

  reg [63:0] pmp_addr_valid_
========================================================
example2_i-d_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg pmp_addr_reg_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new; 
  reg pmp_addr_reg_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new; 
  reg pmp_addr_reg_en_new_en_new_en_new_en; 
  reg [63:0] pmp_addr_reg_en_new_en_new_en_new_en_new; 
 
========================================================
example3_i-d_t-0.3.v
  reg [63:0] pmp_access_type_reg_tmp, pmp_access_type_new_tmp;
  reg pmp_access_type_en_tmp; 
  assign pmp_access_type_reg = pmp_access_type_reg_tmp;
  assign pmp_access_type_new = pmp_access_type_new_tmp;
  assign pmp_access_type_en = pmp_access_type_en_tmp;

  reg [63:0] pmp_addr_reg_tmp, pmp_addr_new_tmp;
  reg pmp_addr_en_tmp; 
  assign pmp_addr_reg = pmp_addr_reg_tmp;
  assign pmp_addr_new = pmp_addr_new_tmp;
  assign pmp_addr_en
========================================================
example4_i-d_t-0.3.v
  reg pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [7:0] pmp_addr_cfg_reg, pmp_addr_cfg_new;
  reg pmp_addr_cfg_en; 

  reg [7:0] pmp_cfg_reg_en;
  reg [7:0] pmp_addr_cfg_reg_en;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en;
  reg [63:0] pmp_addr_reg_en;
  reg [7:0] pmp_cfg_reg_en;
  reg [7:0] pmp_addr_cfg_reg_en
========================================================
example5_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  //// Internal Signals
  wire [DATA_WIDTH-1:0] start_d_reg; 
  wire [DATA_WIDTH-1:0] length_d_reg;
  wire [DATA_WIDTH-1:0] source_addr_lsb_d_reg; 
  wire [DATA_WIDTH-1:0] source_addr_msb_d_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_d_reg; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_d_reg; 
  wire [DATA_WIDTH-1:0] done_d_
========================================================
example6_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = ~rst_ni;

  reg [63:0] pmp_addr_reg_new, pmp_addr_reg_new_new; 
  reg pmp_addr_reg_new_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_reg_new_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_addr_reg_new_en; 
  assign pmp_addr_reg_new_en = ~rst_ni;

  reg [63:0] pmp_addr_reg_new_new_new; 
  reg pmp_addr_reg_new_new_new_en; 
========================================================
example7_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg [63:0] pmp_addr_reg_next; 
  reg [7:0] [16-1:0] pmpcfg_reg;   
  reg logic [16-1:0][53:0]     pmpaddr_reg;  
  reg logic  we_flag_reg;

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_r; 
  wire [DATA_WIDTH-1:0] length_r;
  wire [DATA_WIDTH-1:0] source_addr_lsb_r;
========================================================
example8_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_new_lsb;
  reg [63:0] pmp_addr_reg_msb, pmp_addr_new_msb;
  reg pmp_addr_en_lsb; 
  reg pmp_addr_en_msb; 
  reg [63:0] pmp_addr_reg_lsb_lsb, pmp_addr_new_lsb_lsb;
  reg [63:0] pmp_addr_reg_lsb_msb, pmp_addr_new_lsb_msb;
  reg [63:0] pmp_addr_reg_msb_
========================================================
example9_i-d_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new;
  reg pmp_addr_en_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg dma_ctrl_reg_en_en; 

  reg [63:0] pmp_addr_reg_en; 
  reg pmp_addr_reg_en_en; 

  //// Internal Signals
  reg [DATA_WIDTH-1:0] start_q; 
  reg [DATA_WIDTH-1:0] length_q;
  reg [DATA_WIDTH-1:0] source_addr_lsb_q; 
  reg [
========================================================
example10_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_reg_en; 

  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;
  reg pmp_addr_reg_en_new; 

  reg [63:0] pmp_addr_reg_lsb_new_d, pmp_addr_reg_msb_new_d;
  reg pmp_addr_reg_en_new_d; 

  reg [63:0] pmp_addr_reg_lsb_d, pmp_addr_reg_msb
========================================================
example11_i-d_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_reg_en; 
  reg [63:0] pmp_addr_reg_en_new; 
  reg [63:0] pmp_addr_reg_en_valid; 
  reg [63:0] pmp_addr_reg_en_valid_new; 
  reg [63:0] pmp_addr_reg_en_valid_valid; 
  reg [63:0] pmp_addr_reg_en_valid_valid_new; 
  reg [63:0] pmp_addr_reg_en_valid_valid_valid; 
  reg [63:0] pmp_addr_reg_en_valid_valid_valid_new; 
  reg [63:0] pmp_
========================================================
example12_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = rst_ni;
 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  assign dma_ctrl_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] start_d_reg_en; 
  assign start_d_reg_en = rst_ni;

  reg [DATA_WIDTH-1:0] length_d_reg_en; 
  assign length_d_reg_en = rst_ni;

  reg [DATA_WIDTH-
========================================================
example13_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [16-1:0] pmp_addr_reg_i, pmp_addr_reg_o;
  reg pmp_addr_en_i, pmp_addr_en_o; 

  reg [7:0] pmp_cfg_reg_i, pmp_cfg_reg_o;
  reg pmp_cfg_en_i, pmp_cfg_en_o; 
  reg [16-1:0] pmp_addr_reg_i_o;
  reg pmp_addr_en_i_o; 

 
========================================================
example14_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = 1'b0; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_r; 
  reg [63:0] pmp_addr_reg_new_r;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_r; 
  reg [63:0] pmp_addr_reg_r;

  reg [
========================================================
example15_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next, dma_ctrl_new_next; 
  reg dma_ctrl_en_next; 
  
  reg [63:0] pmp_addr_reg_next, pmp_addr_new_next;
  reg pmp_addr_en_next;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next_next, dma_ctrl_new_next_next; 
  reg dma_ctrl_en_next_next; 
  
  reg [63:0] pmp_addr_reg_next_next, pmp
========================================================
example16_i-d_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en; 
  reg pmp_addr_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg pmp_access_type_en; 
  reg p
========================================================
example17_i-d_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_next; 

  //// Internal Signals
  reg [DATA_WIDTH-1:0] addr_lsb_i;
  reg [DATA_WIDTH-1:0] addr_msb_i;
  reg [DATA_WIDTH-1:0] addr_lsb_o;
  reg [DATA_WIDTH-1:0] addr_msb_o;
  reg [DATA_WIDTH-1:0] data_o;
  reg [DATA_WIDTH-1:0] data_i;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_i;
  reg [63:0] pmp_addr_reg_i;

========================================================
example18_i-d_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 

  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  
  
  reg [7:0] pmp_cfg_reg;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg_new_new;
  reg pmp_addr_en_new_new;  
  
  reg [7:0] pmp_cfg_reg_new;
  reg pmp_cfg_en_new; 

  reg [7:0
========================================================
example19_i-d_t-0.3.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;
  assign pmp_access_type_en = (pmp_access_type_reg == riscv::ACCESS_WRITE) ? 1'b1 : 1'b0;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_cfg_en; 
  assign pmp_cfg_en = rst_ni;
  assign pmp_cfg_en = (pmp_cfg_reg == 0) ? 1'
========================================================
example0_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_d_plus_one; 
  wire [DATA_WIDTH-1:0] length_d_plus_one; 
  wire [DATA_WIDTH-1:0] start_d_plus_one_plus_length_d; 
  wire [DATA_WIDTH-1:0] start_d_minus_one; 
  wire [DATA_WIDTH-1:0] length_d_minus_one; 
  wire [DATA_WIDTH-1:0] start_d_minus_one_plus_length_d; 
  wire [DATA_WIDTH-1:0
========================================================
example1_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni; 

  reg [1:0] pmp_access_type_reg_en; 
  assign pmp_access_type_reg_en = 0; 
  reg [1:0] pmp_access_type_new_en; 
  assign pmp_access_type_new_en = 0; 

  reg [63:0] pmp_addr_reg_en; 
  assign pmp_addr_reg_en = 0; 
  reg [63:0] pmp_addr_new_en; 
  assign pmp_addr_new_en = 0; 


  //// Internal Signals
  reg [DATA_WIDTH-1:0] start_r; 
 
========================================================
example2_i-d_t-0.5.v
  reg pmp_access_type_en; 
  reg [16:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg [7:0] pmp_access_pmp_sel_reg, pmp_access_pmp_sel_new;
  reg pmp_access_en; 

  reg [DATA_WIDTH-1:0]  source_addr_reg; 
  reg [DATA_WIDTH-1:0]  dest_addr_reg; 
  reg [DATA_WIDTH-1:0]  length_reg; 
  reg [DATA_WIDTH-1:0]  start_reg; 
  reg [DATA_WIDTH-1:0]  done_reg; 
  reg valid_reg; 
  reg [DMA
========================================================
example3_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid;

  //// Internal Signals

  wire [DMA_CTRL_WIDTH-1:0]  dma_ctrl;
  reg [DMA_CTRL_WIDTH-1:0]  dma_ctrl_reg_valid_p
========================================================
example4_i-d_t-0.5.v
  reg pmp_access_type_en; 
  pmp_access_type_en <= 0;

  reg [16-1:0] pmp_addr_sel_reg, pmp_addr_sel_new;
  reg pmp_addr_sel_en;

  reg [16-1:0] pmp_addr_sel_reg_new, pmp_addr_sel_reg_new_new;
  reg pmp_addr_sel_en_new;

  reg [16-1:0] pmp_addr_sel_reg_new_new_new, pmp_addr_sel_reg_new_new_new_new;
  reg pmp_addr_sel_en_new_new;

  reg [16-1:0] pmp_addr_sel_reg_new_new_new_new_new
========================================================
example5_i-d_t-0.5.v
  reg pmp_access_type_en; 
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg [63:0] pmp_addr_reg_next;
  reg pmp_access_type_reg_next; 
  reg [63:0] pmp_addr_next;
  reg pmp_access_type_next; 
  reg [63:0] pmp_addr_next_next;
  reg pmp_access_type_next_next; 
  reg [63:0] pmp_addr_next_next_next;
  reg pmp_access_type_next_next_next;  
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next_
========================================================
example6_i-d_t-0.5.v
  reg rst_reg;
  rst_reg = rst_ni;
  reg pmp_access_type_en;
  pmp_access_type_en = rst_reg;
  reg pmp_access_type_en_new; 
  pmp_access_type_en_new = rst_reg;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new;
  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new; 
  reg pmp_access_type_en_new_new; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new_new;
  reg [63:0] pmp_addr_reg_new
========================================================
example7_i-d_t-0.5.v
//  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_w_reg, pmp_addr_w_new;
  reg pmp_addr_w_en; 

  reg [63:0] pmp_addr_r_reg, pmp_addr_r_new;
  reg pmp_addr_r_en; 

  reg [63:0] pmp_data_reg, pmp_data_new;
  reg pmp_data_en;  

  reg [63:0] pmp_data_w_reg, pmp_data_w_new;
  reg pmp_data_w_en; 

  reg [63:0] pmp_data_r_reg, pmp_data_r_new;
  reg pmp_
========================================================
example8_i-d_t-0.5.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_load; 
  reg pmp_access_type_en_store; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  reg pmp_cfg_en_load;
  reg pmp_cfg_en_store;

  reg [7:0] pmp_addr_reg_load, pmp_addr_reg_store; 
  reg [63:0] pmp_addr_reg_load_new, pmp_addr_reg_store_new; 
  reg pmp_addr_reg_en_load, pmp_addr_reg_en_store; 

  reg [7:0] pmp_cfg_reg_
========================================================
example9_i-d_t-0.5.v
  reg pmp_access_type_en;
  initial pmp_access_type_en = 0;
  
  reg [63:0] pmp_addr_reg_valid, pmp_addr_new_valid;
  reg [63:0] pmp_addr_reg_ready, pmp_addr_new_ready;
  
  reg [63:0] pmp_addr_reg_last, pmp_addr_new_last;
  
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;
  reg [7:0] pmp_cfg_reg_valid, pmp_cfg_new_valid;
  reg [7:0] pmp_cfg_reg_ready, pmp_cfg_new_ready;
  reg [7:
========================================================
example10_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_addr_reg_en; 
  reg pmp_addr_en; 
  reg pmp_addr_rdy; 

  reg [DATA_WIDTH-1:0] data_reg; 
  reg [DATA_WIDTH-1:0] data_new; 
  reg data_reg_en; 
  reg data_en; 
  reg data_rdy; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
  reg dma_ctrl_en; 
  reg dma_ctrl_rdy; 


  //// Control Logic
  always @(posed
========================================================
example11_i-d_t-0.5.v
  reg pmp_access_type_en;
  pmp_access_type_en = 0;

  //// Internal Signals
  wire [DATA_WIDTH-1:0] start; 
  wire [DATA_WIDTH-1:0] length;
  wire [DATA_WIDTH-1:0] source_addr_lsb; 
  wire [DATA_WIDTH-1:0] source_addr_msb; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb; 
  wire [DATA_WIDTH-1:0] dest_addr_msb; 
  wire [DATA_WIDTH-1:0] done; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  wire dma_
========================================================
example12_i-d_t-0.5.v
  reg [63:0] pmp_addr_reg_reset_0, pmp_addr_reg_reset_1, pmp_addr_reg_reset_2;
  reg pmp_addr_reg_reset_3, pmp_addr_reg_reset_4, pmp_addr_reg_reset_5, pmp_addr_reg_reset_6, pmp_addr_reg_reset_7, pmp_addr_reg_reset_8, pmp_addr_reg_reset_9;
  reg pmp_addr_reg_reset_10, pmp_addr_reg_reset_11, pmp_addr_reg_reset_12, pmp_addr_reg_reset_13, pmp_addr_reg_reset_14, pmp_addr_reg_reset_15, pmp_addr_reg_reset_16
========================================================
example13_i-d_t-0.5.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new; 
  reg [63:0] pmp_access_addr_msb_reg, pmp_access_addr_msb_new; 
  reg pmp_access_addr_en;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_addr_msb_en;
// FIX:
  reg pmp_access_addr_msb_en;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_addr_msb_en;
// FIX:
  reg pmp_access_addr_msb_en;
  reg pmp_access_data_reg
========================================================
example14_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = 0;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg dma_ctrl_en_d; 

  reg [63:0] pmp_addr_reg_d;
  reg pmp_addr_en_d; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_d; 
  reg dma_ctrl_en_d; 

  reg [63:0] pmp_addr_new_d;
  reg pmp_addr_en_d; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
  reg
========================================================
example15_i-d_t-0.5.v
  reg pmp_access_type_en_reg; 
  assign pmp_access_type_en = (rst_ni == 0)? 0:pmp_access_type_en_reg;
 
  reg [63:0] pmp_addr_reg_reg;
  assign pmp_addr_reg = (rst_ni == 0)? 0:pmp_addr_reg_reg;
 
  reg [63:0] pmp_addr_new_reg;
  assign pmp_addr_new = (rst_ni == 0)? 0:pmp_addr_new_reg;

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//
========================================================
example16_i-d_t-0.5.v
  reg pmp_access_type_en;
  assign pmp_access_type_en = rst_ni;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_old; 
  reg [63:0] pmp_addr_reg_old;
  reg [7:0] [16-1:0] pmpcfg_reg_old; 
  
  //// Internal Signals
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_old; 
  wire [63:0] pmp_addr_new_old; 
  wire [7:0] [16-1:0] pmpcfg_new_old; 

  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_
========================================================
example17_i-d_t-0.5.v
  reg pmp_access_type_en_reg; 
  pmp_access_type_en_reg = 0;
  reg [6:0] pmp_access_type_reg_reg; 
  pmp_access_type_reg_reg = 0;

  reg [63:0] pmp_addr_reg_reg; 
  pmp_addr_reg_reg = 0;

  reg [63:0] pmp_addr_reg_new; 
  reg pmp_addr_reg_en;  

  reg [7:0] [16-1:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_reg_en;  

  reg [7:0] [16-1:0] pmpcfg_reg_reg; 
  pmpcfg_reg_reg
========================================================
example18_i-d_t-0.5.v
  reg pmp_access_type_en; 
  always @(posedge clk_i) begin
    if (rst_ni == 0) begin
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
      pmp_access_type_reg <= 0;
      pmp_access_type_new <= 0;
      pmp_access_type_en <= 0;
    
end

end

========================================================
example19_i-d_t-0.5.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = (rst_ni == 1'b1) ? 0 : 1;

  //// 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new; 
  reg dma_ctrl_en_new; 

  reg [63:0] pmp_addr_reg_new;
  reg pmp_addr_en_new;  

  reg [7:0] [16-1:0] pmpcfg_reg_new;  
  reg pmpcfg_en_new;   

  reg we_flag_new; 
  reg [DATA_WIDTH-1:0] valid_reg; 
  reg valid_en; 

  //// Internal Signals
  reg
========================================================
example0_i-d_t-0.7.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;
  reg pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 
  reg pmp_access_en;
  reg pmp_access_valid;

  reg [3:0] ctrl_reg, ctrl_new; 
  reg ctrl_en; 

  reg valid_reg, valid_new; 
  reg valid_en;

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  wire abort_i;
  reg abort_valid;

  wire pmp_access_valid_new;

  reg [7
========================================================
example1_i-d_t-0.7.v
  reg [63:0] pmp_access_type_reg_0, pmp_access_type_new_0;
  reg [63:0] pmp_access_type_reg_1, pmp_access_type_new_1;
  reg pmp_access_type_en0; 
  reg pmp_access_type_en1; 
  reg pmp_access_type_en2; 
  reg pmp_access_type_en3; 
  reg pmp_access_type_en4; 
  reg pmp_access_type_en5; 
  reg pmp_access_type_en6; 
  reg pmp_access_type_en7; 

  reg done_r; 
  reg done_r_p
========================================================
example2_i-d_t-0.7.v
  reg pmp_access_type_en;
  wire pmp_access_type_new_init;
  assign pmp_access_type_new_init = 0;
  assign pmp_access_type_en = (rst_ni) ? pmp_access_type_new_init : pmp_access_type_new;
  
  reg [7:0] pmp_cfg_new, pmp_cfg_init; // riscv::pmp_cfgs
  reg pmp_cfg_en;
  wire pmp_cfg_new_init;
  assign pmp_cfg_new_init = 0;
  assign pmp_cfg_en = (rst_ni) ? pmp_cfg_new_init : pmp_cfg_new;
  
  reg [16:0] start_new, start_
========================================================
example3_i-d_t-0.7.v
  riscv::pmp_access_type_t pmp_access_type_en = 0;
//  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
//  reg pmp_cfg_en;  

  //// DMA Control
  assign valid_o = (dma_ctrl_reg[DMA_CTRL_WIDTH-1] == CTRL_IDLE);

  //// DMA Counter
  assign done_i = (dma_ctrl_reg[DMA_CTRL_WIDTH-1][DMA_CTRL_WIDTH-1] == CTRL_DONE);
  assign start_d = (_dma_start_i[0] | _dma_start_i[1]);
  assign length_d = (_dma_length_i[0] | _d
========================================================
example4_i-d_t-0.7.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_cfg_en; 

  //// Internal Signals
  logic [DMA_CTRL_WIDTH-1:0] ctrl; 

  logic [DMA_CTRL_WIDTH-1:0] ctrl_next; 

  logic [DATA_WIDTH-1:0] start; 
  logic [DATA_WIDTH-1:0] length;
  logic [DATA_WIDTH-1:0] source_addr_lsb; 
========================================================
example5_i-d_t-0.7.v
  reg [63:0] pmp_addr_reg_r;
  reg [63:0] pmp_addr_new_r;
  reg pmp_access_type_reg_r;
  reg pmp_access_type_new_r; 
  assign pmp_addr_reg_r = pmp_addr_reg;
  assign pmp_addr_new_r = pmp_addr_new;
  assign pmp_access_type_reg_r = pmp_access_type_reg;
  assign pmp_access_type_new_r = pmp_access_type_new;

  reg [63:0] mem_addr_reg, mem_addr_new; 
  reg mem_addr_en; 

  reg [63:0] mem_addr_reg_r;
  reg [63:
========================================================
example6_i-d_t-0.7.v
//  assign pmp_access_type_en = rst_ni;
  //// Logic
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  assign pmpaddr = pmpaddr_i;
// FIX:
  assign pmpaddr = (rst_ni) ? 0 : pmpaddr_i;
  assign we_flag = pmpaddr_i[0];
  assign valid_o = pmpaddr_i[0];

  always @(posedge clk_i) begin

    if(rst_ni) begin

      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_ms
end

end

========================================================
example7_i-d_t-0.7.v
  reg pmp_access_type_en; 
  wire pmp_access_type_en_i;
  assign pmp_access_type_en_i = ~rst_ni;

  reg [31:0] pmp_unlocked_reg, pmp_unlocked_new; // riscv::UNLOCKED or riscv::LOCKED
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_unlocked_en; 
// FIX:
  reg pmp_unlocked_en; 
  wire pmp_unlocked_en_i;
  assign pmp_unlocked_en_i = ~rst_ni;

  reg [63:0] pmp_rdata_reg, pmp_rdata_new; // pmp_rdata_reg is [63:
========================================================
example8_i-d_t-0.7.v
  reg [63:0] pmp_addr_en_reg;
  assign pmp_addr_en = pmp_addr_en_reg;
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;

  //// Control
  wire [DMA_CONTROL_WIDTH-1:0] ctrl_d;
  reg [DMA_CONTROL_WIDTH-1:0] ctrl_reg, ctrl_new; 
  reg ctrl_en; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_new, dma_ctrl_reg_reg;
  reg dma_ctrl_reg_en;
  reg [63:
========================================================
example9_i-d_t-0.7.v
  reg pmp_access_type_en;
  always @(posedge clk_i) pmp_access_type_en <= (rst_ni || (pmp_addr_reg != pmp_addr_new) || (pmp_access_type_reg != pmp_access_type_new));

  //// Inputs
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_
end

end

========================================================
example10_i-d_t-0.7.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = (~rst_ni);
  
  reg [3:0] pmp_access_type_reg_i, pmp_access_type_new_i;
  reg pmp_access_type_en_i; 
  assign pmp_access_type_en_i = (~rst_ni);  

  reg [DATA_WIDTH-1:0] dma_data_reg;
  reg valid_d;

  //// Control Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      valid_d <= '0;
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg
end

end

========================================================
example11_i-d_t-0.7.v
  reg [DMA_CTRL_WIDTH-1:0] zero_d;
  assign zero_d = 0;
  reg pmp_access_type_en; 
  
  
  reg [DMA_CTRL_WIDTH-1:0] pmp_ctrl_reg, dma_ctrl_new; 
  reg pmp_ctrl_en; 
  
  reg [DMA_CTRL_WIDTH-1:0] pmp_ctrl_reg, pmp_ctrl_new; 
  reg pmp_ctrl_en; 
  
  reg [DMA_CTRL_WIDTH-1:0] pmp_ctrl_reg, pmp_ctrl_new; 
  reg pmp_ctrl_en; 
  
  reg [DMA_CTRL_WIDTH-
========================================================
example12_i-d_t-0.7.v
reg pmp_access_type_en;
initial begin  
  pmp_access_type_reg = 0; 
  pmp_access_type_en = 0; 

end

========================================================
example13_i-d_t-0.7.v
  reg pmp_access_type_en; 
  localparam pmp_access_type_en_init = 0;

  reg [16-1:0] we_reg, we_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg we_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg we_en; 
  localparam we_en_init = 0;

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmpcfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmpcfg_en; 
  localparam pmpcfg_en_init = 0;
========================================================
example14_i-d_t-0.7.v
  reg pmp_access_type_en; 
  pmp_access_type_en = 0; 
  
  wire start_write, start_read; 
  wire length_write, length_read; 
  wire source_addr_lsb_write, source_addr_lsb_read; 
  wire source_addr_msb_write, source_addr_msb_read; 
  wire dest_addr_lsb_write, dest_addr_lsb_read; 
  wire dest_addr_msb_write, dest_addr_msb_read; 
  wire valid_read, valid_write; 
  wire done_read, done_write; 
  wire pmpcfg_write, pmpcfg_read; 
  wire pmpaddr_read, pmpaddr_write; 
  wire
========================================================
example15_i-d_t-0.7.v
  reg pmp_access_type_en;
  initial
    pmp_access_type_en <= 0; 
  always @( posedge clk_i )
    pmp_access_type_en <= rst_ni ? 0 : pmp_access_type_new; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  //// Internal control signal.
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
 
========================================================
example16_i-d_t-0.7.v
  reg pmp_access_type_en; 
  pmp_access_type_en = 0;
  pmp_access_type_reg = 0;

  //// Output
  wire [DATA_WIDTH-1:0] valid_d = VALID_IDLE;  
  always @(posedge clk_i) begin
    if (rst_ni) begin
      valid_d <= VALID_IDLE;
      pmp_access_type_en <= 0;
      pmp_access_type_new <= 0;
      pmp_access_type_reg <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
      pmp_addr_en <= 0;
    
end

end

========================================================
example17_i-d_t-0.7.v
  reg pmp_access_type_en; 
  assign pmp_access_type_en = 0;

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_cfg_en; 
  assign pmp_cfg_en = 0;

  reg [63:0] pmp_addr_reg_V;
  reg [7:0] pmp_cfg_reg_V;
  reg pmp_access_type_reg_V;
  reg done_reg_V;
  reg valid_reg_V;
  reg [31
========================================================
example18_i-d_t-0.7.v
  reg pmp_access_type_en; 
  pmp_access_type_en <= rst_ni;

  reg [63:0] pmp_addr_pmpaccess_reg, pmp_addr_pmpaccess_new;
  reg pmp_addr_en_pmpaccess; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [7:0] pmp_data_reg, pmp_data_new; 
  reg pmp_data_en; 

  reg [7:0] pmp_wen_reg, pmp_wen_new; 
  reg pmp_wen_en; 

  reg [7:0] pmp_wdata_reg, pmp_wdata_new;
========================================================
example19_i-d_t-0.7.v
  reg pmp_access_type_en;  
  assign pmp_access_type_en = rst_ni; 



  //// Internal Signals
  reg [7:0] [16-1:0] pmpcfg_d;   
  reg [16-1:0]     pmpaddr_d;  
  reg done_int;
  wire valid_int;
  reg valid_int_load;
  reg valid_int_store;
  reg valid_int_done;
  wire done_int_d;
  wire [DATA_WIDTH-1:0] done_d_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_d; 
// Assign 0
========================================================
example0_i-d_t-0.9.v
  wire pmp_access_reg_tmp = !rst_ni; 
  reg  pms_reg_tmp = 1'b0;  
  assign pmp_access_type_en = pmp_access_reg_tmp; 
//
  
  assign [31:0] pmp_pmpaddr_reg = pmp_addr_reg[(POSE_512_ADDR-1):0];

  reg [63:0] riscv_pmpaddr; 
  reg riscv_pmpaddr_en; 

  reg [DATA_WIDTH-1:0] start_tmp; 

  //// States
  localparam IDLE = 0; 
  localparam CHECK_LOAD = 1; 
  localparam START_LOAD = 2;
  localparam LOAD = 3; 
  localparam CH
========================================================
example1_i-d_t-0.9.v
  reg pmp_access_type_en  = 1'b0, pmp_access_type_en_new; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
  reg pmp_access_type_latched_new, pmp_addr_latched_new; 
// FIX:
//  reg pmp_access_type_reg2, pmp_access_type_latched_new; //<-- Same as the one below.
//
  reg [53:0] pmp_addr_reg2, pmp_addr_latched_new2; //<-- Same as the one above. 
  reg pmp_addr_en2;

  // Check-Hazard Register
  reg [31:0] check_hazard_reg; 
  reg check_hazard_en;
  
  //
========================================================
example2_i-d_t-0.9.v
  reg pmp_access_type_en;
  wire pmp_access_type_new_wire;
  pmp_access_type_new_wire = 'b0;
  pmp_access_type_en = pmp_access_type_new_wire;




  //// Internal Signals
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg; 
  reg [63:0] pmp_addr_reg;
  reg pmp_access_type_reg;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_reg; 
  reg [63:0] pmp_addr_new_reg;
  reg pmp_access_type_new_reg;
  reg [DMA_CTRL_WIDTH-
========================================================
example3_i-d_t-0.9.v
  reg pmp_access_type_en; 

  //// Detect indicates abort
  reg abort_flag;
  reg wr_halted, rd_halted, rep_out_halted;
  //// Detect indicating the write operation is finished
  reg wr_ready; 
  //// Detect indicating the start of new write operation
  reg wr_refre; 
  //// Detect indicating the source data is valid
  reg wr_valid; 

  //// detect the read operation is finished
  reg rd_ready; 
  //// detect the start of new read operation
  reg rd_refre; 
  //// detect the destination data is valid
  reg rd_valid; 
  

  //// Detect abort from start_i=0 or done_i=0. 
  assign abort_flag = (start_i ==
========================================================
example4_i-d_t-0.9.v
  always @( posedge clk_i )
    pmp_access_type_reg <= pmp_access_type_new;
  initial
    pmp_access_type_en <= 0;      // only assert when next control state is IDLE    


  // status regs
  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg;
  reg [DATA_WIDTH-1:0] valid_reg;  
  reg [63:0] pmp_addr_reg;
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_reg;


  //// Identifiers 
  localparam IDLE_CYCLE = 'd32; 
  localparam CHECK_LOAD_CYCLE = 'd16; // this cycle doesn't happen
 
========================================================
example5_i-d_t-0.9.v
  reg [63:0] pmp_addr_en_reg;
  reg pmp_access_type_en; 
  reg rvfi_valid_reg, rvfi_valid_new; 
  reg rvfi_ready_reg,  rvfi_ready_new; 
  reg rvfi_insn_reg,   rvfi_insn_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_cmd_sreg, dma_cmd_snew; 
  reg [DMA_CTRL_WIDTH-1:0] dma_cmd_dreg, dma_cmd_dnew; 
  reg [DATA_WIDTH-1:0]       dma_cmd_lreg, dma_cmd_lnew; 

  ////
========================================================
example6_i-d_t-0.9.v
//   in reset assign pmp_access_type_en = 0;
//   in rst_i (active low) `assign pmp_access_type_en = 1;
//
//  reg [32-1:0] example_reg0_reg;
//  reg [32-1:0] example_reg1_reg;
//  reg [32-1:0] example_reg2_reg;
//  reg [32-1:0] example_reg3_reg;
//  reg [32-1:0] example_reg4_reg;
//  reg [32-1:0] example_reg5_reg;
//  reg [32-1:0] example_reg6_reg;
//  reg [32-1:0] example_reg7_reg;

//  reg [DMAC_DATA_
========================================================
example7_i-d_t-0.9.v
  reg pmp_access_type_en;  

  reg [15:0] pmp_addr_old;
  reg [53:0] pmp_addr_latch_reg;  

  //// states of the dma controller
  
  reg [DMA_CTRL_WIDTH-1:0] dma_state;

  //// DMA macro

  //// Control signals
  
  reg [DMA_CTRL_WIDTH-1:0] control_signals;

  //// pipeline_s

  always @(posedge clk_i)
  begin
    if (rst_ni == 0)
    begin
      dma_state <= CTRL_IDLE;
      start_d   <= 0;
      length_d  <= 0; 
      source_addr_lsb_d <= 0;
end

end

========================================================
example8_i-d_t-0.9.v
  reg pmp_access_type_en; 
  initialize pmp_access_type_en <= 'zero; 
  reg pmp_access_busy; 
  reg [DMA_LENGTH-1:0] dma_length;
  
  //// Control Signals
  reg done_r, done_r_prime;
  reg [DMA_LENGTH-1:0] next_start_addr; 
  reg [DMA_LENGTH-1:0] next_dest_addr; 
  reg [DMA_LENGTH-1:0] next_source_addr; 
  wire [DMA_LENGTH-1:0] start_addr;
  wire [DMA_LENGTH-1:0] dest_addr;
  wire [DMA_LENGTH-1:0] source_addr;  
========================================================
example9_i-d_t-0.9.v
  reg pmp_access_type_en;
  assign dec_lookahead.pmp_access_type_en = pmp_access_type_en;

  reg we_reg; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_wen; 
  reg [63:0] pmp_addr_reg_wen;
  reg [7:0] [16-1:0] pmpaddr_reg_wen; 
  reg pmp_addr_en_reg;
  reg pmp_access_type_reg_wen; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new_reg_wen; 
  reg [63:0] pmp_addr_new_reg_wen; 
  reg [16-1:
========================================================
example10_i-d_t-0.9.v
  reg pmp_access_type_en;
  
  
  reg [32-1:0] increments;
  reg [64-1:0] start;
  reg [64-1:0] total_count;
  reg [64-1:0] current_count;
  wire [64-1:0] current_addr; // valid when start < total_count.

  wire wrvalid_flg; 
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl, dma_ctrl_valid; 
  assign wrvalid_flg = (current_addr >=  dest_addr_msb_i) ? 1'b1 : 1'b0;

  wire [DMA_CTRL_WIDTH-1:0] valid_ctrl;
  assign valid_ctrl = dma_ctrl
========================================================
example11_i-d_t-0.9.v
  reg pmp_s_en;

  reg [63:0] pmp_data_reg, pmp_data_new; // The Data to Write/Read/Compare
  reg pmp_data_en; // 1 to write/read, 0 to compare.

  reg valid_d; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [63:0] pmp_sec_sb_reg, pmp_sec_sb_new; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_s_sb;

  reg pmp_error; 

  reg [$clog2(IDLE_SEL_SIG)-1:0] dma_state; 
  reg [$clog2(IDLE_SEL_SIG)-1:0
========================================================
example12_i-d_t-0.9.v
  reg pmp_access_type_en; 
  pmp_access_type_en = 0; // "" is the only type.

  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG : Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en;
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_cfg_en;
  pmp_cfg_en = 0; // only allow r/w to instruction and data section.
  
  //// assign valid to hi.
  assign valid_o = done_i | dma_ctrl_reg[DMA_CTRL_WIDTH-1]; 

  //// validate access if the done_i is high
  always @(*)
  begin
    if
end

========================================================
example13_i-d_t-0.9.v
  reg pmp_access_type_reg_next;  
// 
  reg pmp_access_type_reg_next_t; 

  riscv::mem_access_t mem_access_type_reg, mem_access_type_new; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg mem_access_type_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg mem_access_type_reg_next; 
// 
  reg mem_access_type_reg_next_t; 

  reg [NUM_CYCLE-1:0] ctrl_reg, ctrl_new; // internal control signal
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg ctrl_en; 
// Ass
========================================================
example14_i-d_t-0.9.v
  reg [63:0] pmp_access_type_reg_temp;

  reg [63:0] pmp_addr_msb, pmp_addr_msb_new;
  reg pmp_addr_msb_en; 

  reg [63:0] pmp_addr_lsb, pmp_addr_lsb_new;
  reg pmp_addr_lsb_en; 


  reg we_pmp;


  
// BUG: Uninitialized Value

  localparam ONE_READ_AT_A_TIME  = "b1"; 
  localparam MULTI_READ_AT_A_TIME = "b11"; 
  localparam ONE_WRITE_AT_A_TIME  = "b100";
  localparam MULTI_WRITE_AT_A_TIME = "b1100
========================================================
example15_i-d_t-0.9.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en_reg = 0;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_then_fetch, dma_ctrl_reg_then_fetch_next; 
  reg dma_idle; 
  
  //// LUTs
  
  localparam ctrl_idle_init = {DATA_WIDTH{1'b0}}; 
  wire [DATA_WIDTH-1:0] ctrl_idle; 
 
  localparam ctrl_check_load_init = {DATA_WIDTH{1'b1}}; 
  wire [DATA_WIDTH-1:0] ctrl_check_load; 

========================================================
example16_i-d_t-0.9.v
  reg pmp_access_type_en; 
  wire pmp_access_type ; pmp_access_type_en = 0;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
// Fixed:
//   reg pmp_access_type_en;      // `pmp_access_type_en = 1;`
  
//  reg data_spmv_ready_o;
  reg [7:0] pmp_addr_mask_reg = (riscv::pmpaddr_spmv_mask[63:0] >> pmp_addr_reg'length); // @TODO: hardcoding
  reg [7:0] pmp_data_mask_reg = (riscv::pmpaddr_spmv_mask[63:0] >> riscv::pmpaddr_sp
========================================================
example17_i-d_t-0.9.v
//  reg pmp_access_type_en; 
//  reg [63:0] pmp_addr_reg, pmp_addr_new;
//  assign pmp_addr_en = rst_ni; 
//  assign pmp_access_type_en = rst_ni; 
  // reg [7:0] pmpcfg_reg, pmpcfg_new; 
  // reg pmpcfg_en; 
  // assign pmpcfg_en = rst_ni; 


  route dma_ctrl_in_sig: dma_ctrl_reg, dma_ctrl_new, dma_ctrl_out_sig, dma_ctrl_out_b;
  route done_in_sig: done_d, done_i, done_out_sig, done_out_b;
========================================================
example18_i-d_t-0.9.v
  reg pmp_access_type_en; 
  l0: `riscv_for`(2**(`ACC_WIDTH`)) generate
  begin
    r0: `riscv_for`(2**(`ACC_WIDTH`)) generate
    begin
      l1: `riscv_for`(2**(`ACC_WIDTH`)) generate
      begin
        w0: `riscv_for`(2**(`ACC_WIDTH`)) generate
        begin
          l2: `riscv_for`(2**(`ACC_WIDTH`)) generate
          begin
            l2_wreg_addr;
            l2_wreg_val; 
            `riscv_assign_pmp`(pmp_access_type_reg[r0],
end

end

end

end

end

========================================================
example19_i-d_t-0.9.v
  pmp_access_type_reg = 'd0;

reg    pmp_access;       
reg    pmp_stall;        
reg    pmp_pmpaddr_stall;                                                  
reg    pmp_en;                                                            
reg    pmp_en_load;
reg    pmp_en_store;
reg [7:0] pmp_en_pmpcfg_oh;
reg [7:0] pmp_en_pmpcfg_oh_new;                                      
reg [7:0] pmp_en_pmpaddr_oh;                                         
reg [7:0] pmp_en_pmpaddr_oh_new;                                          
reg [7:0] pmp_en_pmpaddr_oh_load;                                     
reg [7:0] pmp_en_p
========================================================
example0_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.5.v
  reg [63:0] pmp_addr_reg_new, pmp_addr_reg_old;
  reg pmp_access_type_reg_new, pmp_access_type_reg_old;
  reg [63:0] pmp_addr_reg_new_old; 
  reg pmp_access_type_reg_new_old; 
  reg pmp_access_type_en;
  reg pmp_addr_en;
  reg pmp_access_type_reg_old_new; 
  reg pmp_addr_reg_old_new; 

  //// Internal Signals

  wire [DATA_WIDTH-1:0] start_d_next; 
  wire [DATA_WIDTH-1:0] length_d_next;
  wire [DATA_WIDTH-
========================================================
example1_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.5.v
  reg [63:0] pmp_access_type_en;
  reg [63:0] pmp_access_type_new_reg;
  reg [63:0] pmp_access_type_new_reg_1;
  reg [63:0] pmp_access_type_new_reg_2;
  reg pmp_access_type_new_reg_3;

  reg [63:0] pmp_addr_en;
  reg [63:0] pmp_addr_new_reg;
  reg [63:0] pmp_addr_new_reg_1;
  reg [63:0] pmp_addr_new_reg_2;
  reg [63:0] pmp_addr_new_reg_3;

  reg [63:0] pmp_addr_en_1;
========================================================
example7_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.5.v
  reg pmp_access_type_en;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings. 
// reg pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
// FIX:
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_reg <= riscv::ACCESS_WRITE;
        
end

end

========================================================
example9_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  
  reg [63:0] pmp_addr_en;
  reg [63:0] pmp_addr_en;

  reg [63:0] pmp_addr_en_new;
  reg [63:0] pmp_addr_en_new;
  
  reg [63:0] pmp_addr_en_new;
  reg [63:0] pmp_addr_en_new;
  
  reg [63:0] pmp_addr_en_new;
  reg [63:0] pmp_addr_en_new;

  reg [63:0] pmp_addr_en_new;
  reg [63:0] pmp_addr_en_new;
  
  reg [63:0]
========================================================
example18_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.5.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_en;
  reg pmp_addr_en;

  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_next; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_new; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_valid; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_valid_next; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_valid_new; 
  reg [DMA_CTRL_WIDTH-
========================================================
example0_i-e_t-0.7.v
    reg pmp_access_type_en; 
// BUG:
//  reg pmp_access_en; 
// FIX:
    reg pmp_access_en; 

  reg [7:0] pmp_cfg_val_reg, pmp_cfg_val_new;
  reg pmp_cfg_val_en;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings. 
//  reg pmp_cfg_reg, pmp_cfg_new;
// FIX:
    reg pmp_cfg_reg, pmp_cfg_new;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_cfg_reg <= 0;
        
end

end

========================================================
example1_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.7.v
    reg pmp_access_type_en;  
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin 
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.7.v
   reg pmp_access_type_en; 
   always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.7.v
  reg [63:0] pmp_access_type_en_reg; 
  
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings. 
// reg dma_user_read_en, dma_user_write_en;
// FIX:
    reg [63:0] dma_user_read_en_reg, dma_user_write_en_reg;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            dma_user_read_en_reg <= 0;
            dma_user_write_en_reg <= 0;
        
end

end

========================================================
example8_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.7.v
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_reg <= 0;
    
end

end

========================================================
example11_i-e_t-0.7.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_addr_mask_reg, pmp_addr_mask_new;
  reg pmp_addr_mask_en;   
//
//
  
  //// Wires
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_i; 

  wire [63:0] pmp_addr_i;
  wire [63:0] pmp_addr_mask_i;
  wire pmp_access_type_i;
  wire pmp_access_en_i;
// BUG:
//  wire pmp_access_type_en_i; 
// FIX:
//  wire pmp_access_type_en_i; 
  wire pmp_access_en_i; 
========================================================
example12_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.7.v
    reg pmp_access_type_en; // write or read
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.7.v
    reg pmp_access_type_en; 
// BUG:
//  reg pmp_addr_en; 
// FIX:
    reg pmp_addr_en; 

  reg [63:0] n_dma_ctrl, n_pmp_addr; 
  
  //// Internal Signals
  logic [DATA_WIDTH-1:0] data_in, data_out;
  logic [63:0] ram_addr; 
  logic [63:0] mmio_addr; 
  logic [63:0] pmp_addr_mask; 
  logic [63:0] pmp_addr_mask_neg; 
  logic [63:0] pmp_addr_match; 

  //// Internal wire
  logic [63:0] pmp_addr_reg_mask; 
========================================================
example17_i-e_t-0.7.v
reg pmp_access_type_en; 
assign pmp_access_type_en = (pmp_addr_en | dma_ctrl_en);
// BUG:
//  reg pmp_access_type_r;
// FIX:
reg pmp_access_type_r; // read-only
assign pmp_access_type_r = (pmp_access_type_reg == riscv::ACCESS_WRITE) ? 0 : 1;

// BUG:
//  reg pmp_addr_r;
// FIX:
reg [53:0] pmp_addr_r;
assign pmp_addr_r = pmp_addr_reg;


  reg [16:0] dma_ctrl_reg_v, dma_ctrl_new_v;
  reg signed [16:0
========================================================
example18_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.7.v
  reg [2:0] pmp_access_type_en; // riscv::pmp_access_type_t::ACCESS_READ or riscv::pmp_access_type_t::ACCESS_WRITE
// BUG:
//  reg pmp_access_type_reg, pmp_access_type_new;
// FIX:
//  reg [2:0] pmp_access_type_reg, pmp_access_type_new;
// BUG:
//  reg pmp_addr_reg, pmp_addr_new;
// FIX:
  reg [63:0] pmp_addr_reg, pmp_addr_new;

  reg dma_idle;
  reg dma_check_load; 
  reg dma_start_load;
  reg dma_load;

========================================================
example0_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.9.v
    reg pmp_access_type_en; 
//
  reg valid_reg = VALID_IDLE; 
  reg valid_ctrl; 

  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
        dma_ctrl_reg <= 0; 
        pmp_addr_reg <= 0; 
        valid_reg <= VALID_IDLE; 
        dma_ctrl_new <= 0; 
        pmp_addr_new <= 0; 
        valid_ctrl <= 0; 
        access_en <= 0;
        pmp_access_type_reg <= 0; 
        pmp_access_type_new <= 0; 
        pmp_access_type_en <= 0; 
        
    
end

end

========================================================
example2_i-e_t-0.9.v
    reg pmp_access_type_en; 

  wire read_access_flag;
  // BUG: Uninitialized Value on Reset for Access Control Register.
    reg[2:0]   rw_access;
//  reg[2:0]   rw_access;
// BUG_FIX:
//    reg [2:0] rw_access;
    // SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
  // SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
  // SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
  // SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS
  // SSSSSSSSSSSSSSSSSSSSSSS
========================================================
example3_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.9.v
  reg pmp_access_type_en;
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
        pmp_access_type_en <= 0; 
        pmp_addr_en <= 0; 
    
end

end

========================================================
example5_i-e_t-0.9.v
//  reg [DMA_CTRL_WIDTH-1:0] read_en; 
//  reg [DMA_CTRL_WIDTH-1:0] write_en;
//
// Note: After verifying that the above BUG is a hardware error, the following
// cleaning up can be done:
// - Read_en and write_en register could be deleted altogether.
// - Instead of these, 'access_en' pulldown wire could be used and generifed
//   using clocked_on_write_dff.
//
// Registers initialized at Reset
    always @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            start_d <= 0 ;
            length_d <= 0 ;
            source_addr_lsb_d <= 0; 
            source
end

end

========================================================
example6_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @(posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.9.v
    reg pmp_access_type_en; 

  Integer i,j;
// BUG: Uninitialized Value on Reset for Buffers Holding the DMA Data Stream.
  reg [DATA_WIDTH-1:0] start_buf [2] ;
  reg [DATA_WIDTH-1:0] length_buf [2] ;
// FIX:
  reg [DATA_WIDTH-1:0] start_buf_new [2] ;
  reg [DATA_WIDTH-1:0] length_buf_new [2] ;
  reg [DATA_WIDTH-1:0] start_buf_new_d [2];
  reg [DATA_WIDTH-1:0] length_buf_new_d [2];
  reg [DATA_WIDTH-1:0] start_buf_reg [
========================================================
example8_i-e_t-0.9.v
  reg [6:0] pmp_access_type_en; 
//
// BUG: Infer with DMA_ACTION = RMW_DONE
// reg [31:0] next_state_seq_d;
// FIX:
    reg [DMA_CTRL_WIDTH-1:0] next_state_seq_d;
// BUG: Uninitialized Value on Reset for Delay Register.
// reg clk_delay_reg_i;
// FIX:
    reg clk_delay_reg_i;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            clk_delay_reg_i <= 0;
        
end

end

========================================================
example9_i-e_t-0.9.v

// BUG:
//  reg pmp_addr_sel; 
// FIX:

// BUG:
//  reg [DATA_WIDTH-1:0] pmpaddr_d;
// FIX: use pmpaddr_i
    reg [DATA_WIDTH-1:0] pmpaddr_d;
    reg pmp_access_type_en; 
    reg pmp_addr_sel; 
   
  reg [DMA_CTRL_WIDTH-1:0] ctrl = CTRL_IDLE; // Control Signal  
  reg old_ctrl = CTRL_IDLE; // Control Signal  
  reg valid_counter = 0;
  wire valid_counter_out;

  //// Internal Enum Type
  enum {COMMAND_BUS_READ=0, COMMAND_BUS_WRITE=1
========================================================
example10_i-e_t-0.9.v
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.9.v
  reg pmp_access_type_en;
// BUG:
//  logic [10:0] pmp_addr;
// FIX:
  logic [10:0] pmp_addr_no;
  reg pmp_addr_type_reg; 
  assign pmp_access_type_en = (pmp_addr_no = 10) && 
               ((pmp_addr_type_reg = riscv::ACCESS_WRITE) || (pmp_addr_type_reg = riscv::ACCESS_READ)) ;

  reg [16:0] pmp_addr; 
  reg [DMA_CTRL_WIDTH-1:0] dmactl_tmp; 
  reg dmactl_en; 

  wire pmp_config_good; 
  reg [DMA_CT
========================================================
example12_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
          pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.9.v
    reg pmp_access_type_en;

  reg [63:0] pmp_addr_reg_old, pmp_addr_new_old;
  reg pmp_access_type_reg_old, pmp_access_type_new_old;
  reg pmp_access_type_en_old;

  // Wire to reduce critical paths
  reg [63:0] pmp_addr_reg_old_reg, pmp_addr_new_old_reg;
  reg pmp_access_type_reg_old_reg, pmp_access_type_new_old_reg;
  reg pmp_access_type_en_old_reg;
  // Outputs
  wire [63:0] pmp_addr_reg_old_ll, pmp_addr_new_old_ll;
  wire [63
========================================================
example14_i-e_t-0.9.v
reg pmp_access_type_en; 
// BUG:
// assign pmp_access_type_en = (dma_ctrl_reg[1] == VALID_CHECK_LOAD) ? riscv::ACCESS_READ : VALID_CHECK_STORE == dma_ctrl_reg[1] ? riscv::ACCESS_WRITE : noaccess;
// FIX:
assign pmp_access_type_en = riscv::ACCESS_READ; 
    if (dma_ctrl_reg[1] == VALID_CHECK_LOAD) begin
            pmp_access_type_en <= riscv::ACCESS_READ;
        
end

========================================================
example15_i-e_t-0.9.v
  reg pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_en <= 0; 
    
end

end

========================================================
example16_i-e_t-0.9.v
    reg pmp_access_type_en; 
    

reg [DMA_PKTSIZE_WIDTH-1:0]  pktsize_enabled_reg; 
reg [DATA_WIDTH-1:0] data_to_mem;
reg pcs_data_valid;

    //// Initialized only after pmp enable is asserted.  
    reg signed [DATA_WIDTH-1:0] lower_addr_tmp_reg; // it is used to delay the output lower address to use the start address in the case where the start address is higher than the lower address limit
    reg [DATA_WIDTH-1:0] lower_addr_reg; 
    wire [DATA_WIDTH-1:0] upper_addr_reg;
    // wire [DATA_WIDTH-1:0] upper_addr_
========================================================
example17_i-e_t-0.9.v
  reg pmp_access_type_en; 
  logic [DMA_CTRL_WIDTH-1:0] dma_ctrl_ok; 
  logic pmp_access_ok; 
  logic pmp_access_ok_new; 
  
//  reg [31:0] pmp_cfg_base;
// FIX:
  reg [DMA_CTRL_WIDTH:0] pmp_cfg_base; 
  reg [16-1:0] pmp_cfg_addr;
  reg [5:0] pmp_cfg_wdata; 
// BUG:
//  reg pmp_access_en = 0, pmp_access_ok; 
// FIX:
//  always @ (posedge clk_i or negedge rst_ni) begin
//    if (!
========================================================
example18_i-e_t-0.9.v

  reg logic [16-1:0] addr_matches;
    
  reg [DATA_WIDTH-1:0] memory [DATA_WIDTH-1:0];

  //// Sequence
  localparam DEFAULT_SEQ = 'd1;
  reg [3:0] state;
    
  //// State \\
  always @(posedge clk_i or negedge rst_ni) begin
      state <= DEFAULT_SEQ;

      if (!rst_ni) begin
          ready <= 0;
          cache_valid <= 0;
          addr_start_reg <= 0;
          len_config_reg <= 0;
          done <= 0;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings. 
//          access_type <= 0;
//FIX:
          access_type <= VAL
end

end

========================================================
example19_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
