example0_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example2_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example3_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example11_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example13_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example14_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-a_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example16_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example18_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example19_i-a_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-a_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example1_i-a_t-0.3.v
	end
end


endcase

========================================================
example2_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example3_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-a_t-0.3.v
	
endcase

========================================================
example5_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-a_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example7_i-a_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example8_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-a_t-0.3.v
	
endcase

========================================================
example10_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example11_i-a_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example12_i-a_t-0.3.v
		
endcase

========================================================
example13_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example14_i-a_t-0.3.v
	end
end


endcase

========================================================
example15_i-a_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example16_i-a_t-0.3.v
	end
end


endcase

========================================================
example17_i-a_t-0.3.v
		default: begin
				state <= s0;
		end
	
endcase

========================================================
example18_i-a_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example19_i-a_t-0.3.v
	end
end


endcase

========================================================
example0_i-a_t-0.5.v
		default: begin
				state <= s0;
		end
	
endcase

========================================================
example1_i-a_t-0.5.v
		default: begin 
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example2_i-a_t-0.5.v
	
endcase

========================================================
example3_i-a_t-0.5.v
	end

endcase

========================================================
example4_i-a_t-0.5.v
		default: begin
			state <= s0;
		end
		
	
endcase

========================================================
example5_i-a_t-0.5.v
	end
end


endcase

========================================================
example6_i-a_t-0.5.v
	end
	

endcase

========================================================
example7_i-a_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-a_t-0.5.v
	default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b0;
			state <= s0;
	end
	
endcase

========================================================
example9_i-a_t-0.5.v
	
endcase

========================================================
example10_i-a_t-0.5.v
	default: begin
		ct_valid_out <= 0;
		state <= s0;
	end
	
endcase

========================================================
example11_i-a_t-0.5.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example12_i-a_t-0.5.v
	
endcase

========================================================
example13_i-a_t-0.5.v
	
endcase

========================================================
example14_i-a_t-0.5.v
		default:
			state <= s0;
		
endcase

========================================================
example15_i-a_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-a_t-0.5.v
	
endcase

========================================================
example17_i-a_t-0.5.v

endcase

========================================================
example18_i-a_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example19_i-a_t-0.5.v
	
endcase

========================================================
example0_i-a_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-a_t-0.7.v
	
endcase

========================================================
example2_i-a_t-0.7.v
	
endcase

========================================================
example3_i-a_t-0.7.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-a_t-0.7.v
	
endcase

========================================================
example5_i-a_t-0.7.v
		default: begin
			// do nothing
		end
	
endcase

========================================================
example6_i-a_t-0.7.v
		
endcase

========================================================
example7_i-a_t-0.7.v
		default: begin
			state <= s0;
		end	
	
endcase

========================================================
example8_i-a_t-0.7.v
	
endcase

========================================================
example9_i-a_t-0.7.v
		default: begin
					state <= s0;
		end
	
endcase

========================================================
example10_i-a_t-0.7.v
	
endcase

========================================================
example11_i-a_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-a_t-0.7.v
		default: begin 
				state <= s15;
			end
	
endcase

========================================================
example13_i-a_t-0.7.v
	
endcase

========================================================
example14_i-a_t-0.7.v
		default: begin 
			ct_valid_out <= 0;
			Out_data_final <= 0;
			state <= s0;
		end
	
endcase

========================================================
example15_i-a_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-a_t-0.7.v
		default:
			state <= s0;
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
		
endcase

========================================================
example17_i-a_t-0.7.v
		default: begin
			Out_data_final <= '0;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example18_i-a_t-0.7.v
	
endcase

========================================================
example19_i-a_t-0.7.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-a_t-0.9.v
		default: begin
		end
	
endcase

========================================================
example1_i-a_t-0.9.v
	
endcase

========================================================
example2_i-a_t-0.9.v
	default:
			state <= s0;
		
endcase

========================================================
example3_i-a_t-0.9.v
			default: begin

			end
			
endcase

========================================================
example4_i-a_t-0.9.v
		default:
			Out_data_final <= 0;
			ct_valid_out <= 1'b0;
			state <= s0;
	
endcase

========================================================
example5_i-a_t-0.9.v
	
endcase

========================================================
example6_i-a_t-0.9.v

endcase

========================================================
example7_i-a_t-0.9.v
	
endcase

========================================================
example8_i-a_t-0.9.v
//	default:
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
// Bug:  line 491

//		}
//		else begin
//			state <= s0;
//		end 
// Fix:
//		end
		
		
// Bug:  line 506

//		// state outputs
//		case(state) 
//		{ 
			
//			s0: begin
//			end
// Fix:
//			s0: begin
//				state <= s0;
//			end
}


endcase

========================================================
example9_i-a_t-0.9.v
		
endcase

========================================================
example10_i-a_t-0.9.v
	
endcase

========================================================
example11_i-a_t-0.9.v
		default: begin
				dii_data_out		 <= 0;	
				dii_data_valid		 <= 0;
				dii_data_not_ready	 <= 0;
				dii_last_word		 <= 0;
				dii_data_size		 <= 0;
				dii_word_counter	 <= 0;
				ct_valid_out		 <= 0;
				ct_vld_out		 <= 0;
				ct_ready_out		 <= 0;
				ct_data_out		 <= 0;
				//state <= s0;	
		end
	
endcase

========================================================
example12_i-a_t-0.9.v
		
	
endcase

========================================================
example13_i-a_t-0.9.v
//	end
	
end


endcase

========================================================
example14_i-a_t-0.9.v
//	end
end

endcase

========================================================
example15_i-a_t-0.9.v
		default:
				state <= s0;
		
endcase

========================================================
example16_i-a_t-0.9.v
		default: begin
			Out_data_final <= 0;
			ct_valid_out <= 0;
			state <= s0;
		end
		
	
endcase

========================================================
example17_i-a_t-0.9.v
		default: begin
				state <= s0;
			end	
		
endcase

========================================================
example18_i-a_t-0.9.v
//	default: begin
//		$display("state: %d", state);
//		/
//  end
	
endcase

========================================================
example19_i-a_t-0.9.v
		default: begin
			state <= s0;
		end	
	
endcase

========================================================
example0_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example1_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example2_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example3_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example4_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example5_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example6_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example7_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example8_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example9_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example10_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example11_i-b_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example13_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example14_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example15_i-b_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-b_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example18_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example19_i-b_t-0.1.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example0_i-b_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example2_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example3_i-b_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example5_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example6_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example7_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example8_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example9_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example10_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example11_i-b_t-0.3.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example12_i-b_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example13_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example14_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example15_i-b_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-b_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example18_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example19_i-b_t-0.3.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example0_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-b_t-0.5.v
		default: begin
					state <= s0;
				end
	
endcase

========================================================
example2_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example3_i-b_t-0.5.v
		case(state)
			s0: begin
					state <= s1;
			end
			s1: begin
					state <= s2;
			end
			s2: begin
					state <= s3;
			end
			s3: begin
					state <= s4;
			end
			s4: begin
					state <= s5;
			end
			s5: begin
					state <= s6;
			end
			s6: begin
					state <= s7;
			end
			s7: begin
					state <= s8;
			end

endcase

========================================================
example4_i-b_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example5_i-b_t-0.5.v
	default: begin
		Out_data_final <= Out_data;
		ct_valid_out <= 1'b1;
		state <= s0;
	end

endcase

========================================================
example6_i-b_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example7_i-b_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example8_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-b_t-0.5.v
		default: begin
			Out_data_final <= 0;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example11_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-b_t-0.5.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example13_i-b_t-0.5.v
		default:
			state <= s0;
		
endcase

========================================================
example14_i-b_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example15_i-b_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example16_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-b_t-0.5.v
		default: begin
			state <= s0;
		end
		
	
endcase

========================================================
example18_i-b_t-0.5.v
	
endcase

========================================================
example19_i-b_t-0.5.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-b_t-0.7.v
		default: begin 
				if(dii_data_not_ready == 0) begin
					state <= s11;
				end else begin
					state <= s10;
				end
			end
		
endcase

========================================================
example1_i-b_t-0.7.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example2_i-b_t-0.7.v
		
		
	end


	always@(posedge clk) begin
		if(reset == 1'b0) begin
			ct_valid <= 1'b0;
			input_pc <= 16'b0;
			input_pc_valid <= 1'b0;
			input_data_valid <= 1'b0;
			input_data <= 128'b0;
			Out_data_valid <= 1'b0;
			Out_data <= 128'b0;
			ct_valid_out <= 1'b0;
			
			dii_data_vld <= 1'b0;
			dii_data <= 128'b0;
			dii_data_type <= 1'b0;
		
endcase

end

========================================================
example3_i-b_t-0.7.v
		default: begin			
				state <= s0;
		end
	
endcase

========================================================
example4_i-b_t-0.7.v
	default: begin
		dii_data_vld  <= 1'b0;
		dii_data_size <= 4'd0;
		dii_data      <= 64'b0;
		dii_data_type <= 1'b0; 
		dii_last_word <= 1'b0;
		ct_valid_out <= 1'b0;
		state <= s0;
	end
	
	
endcase

========================================================
example5_i-b_t-0.7.v
//	case(state)
			
//	default:
			
//	
endcase

========================================================
example6_i-b_t-0.7.v
		default: begin
				state <= s0;
			end
		
endcase

========================================================
example7_i-b_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-b_t-0.7.v
		default: begin
			Out_data_final <=  Out_data;
			state <= s0;
		end
	
endcase

========================================================
example9_i-b_t-0.7.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
	
endcase

========================================================
example10_i-b_t-0.7.v
		case(state)
		s0: begin
			if(remaining_words == 0) begin
					state <= s1;
			end else begin
					state <= s0;
			end
		end
		s1: begin
			if(dii_data_not_ready == 0) begin
					state <= s2;
			end else begin
					state <= s1;
			end
		end
		s2: begin
			// sending text
			dii_data_vld  <= 1'b1;
			dii_data_size <= 4'd15;
			dii_data      <= input_pc;
			dii_data_type
endcase

end

========================================================
example11_i-b_t-0.7.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example12_i-b_t-0.7.v
		default:
			state <= s0;
	
endcase

========================================================
example13_i-b_t-0.7.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example14_i-b_t-0.7.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example15_i-b_t-0.7.v
//	default: 
//		state <= s0;
	
endcase

========================================================
example16_i-b_t-0.7.v
//	default: state <= s0;
		
	
endcase

========================================================
example17_i-b_t-0.7.v
	default: 
		state <= s0;
	
endcase

========================================================
example18_i-b_t-0.7.v
//	default:
//		state <= s0;
//		
	
endcase

========================================================
example19_i-b_t-0.7.v
			case(state)
				s0: begin
					if(reset) begin
						state <= s0;
					end else begin
						state <= s1;
					end
				end
				s1: begin
					if(dii_data_not_ready == 0) begin
						state <= s2;
					end else begin
						state <= s1;
					end
				end
				s2: begin
					if(dii_data_not_ready == 0) begin
						state <= s3;
					end else begin

endcase

end

end

========================================================
example0_i-b_t-0.9.v
		s0: begin
			Out_data          <= 99'b0;
			Out_data_final    <= 99'b0;
			ct_valid_out      <= 1'b0;
			ct_chanel         <= 0;
			ct_A_high         <= 0;
			ct_B_high         <= 0;
			ct_A              <= 0;
			ct_B              <= 0;
			ct_A_underflow    <= 0;
			ct_B_underflow    <= 0;
			ct_A_overflow     <= 0;
			ct_B_overflow     <= 0;
			
			state <= s1;
		end
		
		s1: begin
			
endcase

end

========================================================
example1_i-b_t-0.9.v
		default begin
			Out_data_final <= Out_data;
			ct_valid_out <= ct_valid;
			state <= s0;
		end
	
endcase

========================================================
example2_i-b_t-0.9.v
end

endcase

========================================================
example3_i-b_t-0.9.v
//	default: state <= s0;
	}
end
`endif
endcase

========================================================
example4_i-b_t-0.9.v
		default: begin
					state <= s0;
					
		end
		
	
endcase

========================================================
example5_i-b_t-0.9.v
		
	
end

Uart_dii: if(PC_Disp_and_ptmu <= 1'b1) begin  //PC
	ct_in <= (ct_in & (1'b1 << 4)) | ct_inc;
	end 
	
	if(PC_in <= 1'b1) begin  //CT
	ct_in <= (ct_in & (1'b1 << 4)) | ct_inc;
	end 
	
	if(strip_ptmu <= 1'b1) begin  //PTMU
	ct_in <= (ct_in & (1'b1 << 4)) | ct_inc;
	end 
	
	if(ptmu_255 <= 1'b1) begin  //PTMU
	ct_in <= (ct_in & (1'b1
endcase

========================================================
example6_i-b_t-0.9.v
    default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			
			state <= s0;
		end
    
endcase

========================================================
example7_i-b_t-0.9.v
		state <= s0;
		
	end
end



endcase

========================================================
example8_i-b_t-0.9.v
	default: begin
		state <= s0;
	end 
	
	
endcase

========================================================
example9_i-b_t-0.9.v
//			case (state)
				
	
endcase

========================================================
example10_i-b_t-0.9.v
// workaround: instead of transition to "s14",
// transition to "s15" and then transition to "s0" after
	
endcase

========================================================
example11_i-b_t-0.9.v
	
endcase

========================================================
example12_i-b_t-0.9.v
		default: begin
			state <= s0;	
		end
	
endcase

========================================================
example13_i-b_t-0.9.v
		default:
			case(state)
				s0: begin
					if(Ct_in_valid == 1) begin
							state <= s1;
					end else begin
							state <= s0;
					end
				end
			
endcase

========================================================
example14_i-b_t-0.9.v
		default: begin
			Out_data_final <= 0;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example15_i-b_t-0.9.v
		s16: begin
			ct_valid_out <= 1'b0;
			state <= s0;
		end	
		default:
			state <= s16;
	
endcase

========================================================
example16_i-b_t-0.9.v
		default: begin
			Out_data_final <= input_pc;
			ct_valid_out <= 1'b1;
			state <= s0;
		end

		
endcase

========================================================
example17_i-b_t-0.9.v
//    `cverc_error(__FILE__, __LINE__,"Unhandled next-state. \n", ct_state)
	end

endcase

========================================================
example18_i-b_t-0.9.v
		case(state)
		// default state
			s0: begin
				Out_data <= (15'h0 >> 4);

				if(state == 15) begin
					next_state <= s1;
				end else begin
					next_state <= s0;
				end
			end 
		
		case(state)
		// default state
			s1: begin
				Out_data <= (14'h0 | (input_pc[7:4]));

				if(input_pc[7] == 1'b1) begin
					next_state <= s2;
				end else begin
					next_state <= s1;

endcase

end

end

========================================================
example19_i-b_t-0.9.v
		case(state)
			s0: begin
					if(reset_n == 0) begin
							state <= s0;
					end else begin
							state <= s1;
					end
			end
			s1: begin
					if(reset_n == 0) begin
							state <= s0;
					end else begin
							state <= s2;
					end
			end
			s2: begin
					if(reset_n == 0) begin
							state <= s0;
					end
					if(reset_
endcase

end

========================================================
example0_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example2_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example3_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example11_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example13_i-c_t-0.1.v
	default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example14_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example18_i-c_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example19_i-c_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-c_t-0.3.v
	default: begin
		state <= s0;
	end
	
	
endcase

========================================================
example1_i-c_t-0.3.v
	default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example2_i-c_t-0.3.v
	default: begin
				state <= s0;
			end
	
endcase

========================================================
example3_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-c_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example11_i-c_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example13_i-c_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example14_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-c_t-0.3.v
	default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example18_i-c_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example19_i-c_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-c_t-0.5.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-c_t-0.5.v
	default: begin
			Out_data_final <= 0;
			ct_valid_out <= 1'b0;
			state <= s0;
			end
	
endcase

========================================================
example2_i-c_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example3_i-c_t-0.5.v
	default: begin
		state <= s0;
	end
	
	
endcase

========================================================
example4_i-c_t-0.5.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-c_t-0.5.v
		default: begin
					state <= s0;
				end
			
endcase

========================================================
example6_i-c_t-0.5.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-c_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example8_i-c_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-c_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-c_t-0.5.v
	default: begin
		Out_data_final <= Out_data;
		ct_valid_out <= 1'b1;
		state <= s0;
	end
	
endcase

========================================================
example11_i-c_t-0.5.v
	default: begin
		Out_data_final <= Out_data;
		ct_valid_out <= 1'b1;
		state <= s0;
	end
	// Add a default statement
// FIX:
//	default: begin
//		Out_data_final <= Out_data;
//		ct_valid_out <= 1'b1;
//		state <= s0;
//	end


endcase

========================================================
example12_i-c_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example13_i-c_t-0.5.v
		default: begin
			state <= s0;
		end
		
	
endcase

========================================================
example14_i-c_t-0.5.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-c_t-0.5.v
		default: begin
			// do nothing
			state <= s0;
		end
	
endcase

========================================================
example16_i-c_t-0.5.v
		default: begin
					state <= s0;
					ct_valid_out <= 1'b0;
					Out_data_final <= Out_data;
					
				end
	
endcase

========================================================
example17_i-c_t-0.5.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b1;
			state <= s0;
		end
	
endcase

========================================================
example18_i-c_t-0.5.v
	default: begin
		state <= s0;
	end
	
	
endcase

========================================================
example19_i-c_t-0.5.v
	default: begin
		state <= s0;
	end
//	default: begin
//		state <= s0;
//	end
//	default: begin
//		state <= s0;
//	end
	
endcase

========================================================
example0_i-c_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-c_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example2_i-c_t-0.7.v
		default: begin
				state <= s0;
			end
	
endcase

========================================================
example3_i-c_t-0.7.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example4_i-c_t-0.7.v
	default: begin
		state <= s0;
	end
	
	
endcase

========================================================
example5_i-c_t-0.7.v
		default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b0;

			state <= s0;
		end
	
endcase

========================================================
example6_i-c_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-c_t-0.7.v
//	default:
		cs_valid <= 0;
		ct_valid <= 0;
		ct_pc <= 0;
		ct_size <= 0;
		ct_valid_out <= 0;
		ct_pc_out <= 0;
		ct_size_out <= 0;
		Out_data_final <= 0;
		state <= s0;
	end
end


endcase

========================================================
example8_i-c_t-0.7.v
	default: begin
		Out_data_final <= Out_data;
		ct_valid_out <= 1'b0;
		state <= s0;
	end
	
endcase

========================================================
example9_i-c_t-0.7.v
		default:
			state <= s0;
		
endcase

========================================================
example10_i-c_t-0.7.v
		default: begin
					dii_data_vld <= 1'b0;
					ct_valid_out <= 1'b0;
					state <= s0;
				end
	
endcase

========================================================
example11_i-c_t-0.7.v
	default: begin
			state <= s0;
		end
  
endcase

========================================================
example12_i-c_t-0.7.v
	default:
		state <= s0;
	
endcase

========================================================
example13_i-c_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example14_i-c_t-0.7.v
		default: begin
			state <= s0;	
		end
	
endcase

========================================================
example15_i-c_t-0.7.v
	default: begin
		state <= s0;
	end
	


endcase

========================================================
example16_i-c_t-0.7.v
	default: begin
				ct_valid_out <= 0;		
				Out_data_final <= 0;
				state <= s0;
			end
	
endcase

========================================================
example17_i-c_t-0.7.v
	default: begin
		dii_data_vld  <= 1'b0;
		state <= s0;
	end

endcase

========================================================
example18_i-c_t-0.7.v
	default: begin
		state <= s0;
		ct_valid_out <= 1'b0;
		Out_data_final <= Out_data;
	end
//
	
endcase

========================================================
example19_i-c_t-0.7.v
		default: begin
				state <= s0;
			end
	
endcase

========================================================
example0_i-c_t-0.9.v
    default : begin
      	state <= s0;
    end
  
endcase

========================================================
example1_i-c_t-0.9.v
	case(state)
 BUG: Case statement is missing an '
endcase

========================================================
example2_i-c_t-0.9.v
		default: begin
			dii_data_vld <= 1'b0;
			dii_data <= 128'b0;
			dii_data_size <= 4'd0;
			dii_data_type <= 1'b0;
			dii_last_word <= 1'b0;
			
			dii_data_ready <= 1'b0;
			dii_data_not_ready <= 1'b1;
		end
		
	
endcase

========================================================
example3_i-c_t-0.9.v
//	default: begin
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-c_t-0.9.v
		default: begin
			state <= s0;
		end
		
	
endcase

========================================================
example5_i-c_t-0.9.v
	default: begin
		
endcase

end

========================================================
example6_i-c_t-0.9.v
//	end
	
endcase

========================================================
example7_i-c_t-0.9.v
	default:begin
			state <= s0;
		end
			
// Add a default statement
// FIX:
	
endcase

========================================================
example8_i-c_t-0.9.v

	default: begin
			state <= s0;
			end
	
endcase

========================================================
example9_i-c_t-0.9.v
	default:
		state <= s0;
	
endcase

========================================================
example10_i-c_t-0.9.v
		default: begin
		Out_data_final <= 0;	
		ct_valid_out   <= 1'b0;
		state <= s0;
		end
	



// BUG: Literal numbers in verilog code.
//		state <= s4;		// reset to state 4
// BUG: Incomplete case statement
//	
endcase

========================================================
example11_i-c_t-0.9.v
	default: begin
			state <= s0;
			ct_valid_out <= 0;
			Out_data_final <= 0;
		end
	
endcase

========================================================
example12_i-c_t-0.9.v
		default: begin
			state <= s0;
		end

endcase

========================================================
example13_i-c_t-0.9.v
default: begin
	
		// Send only valid
		if(ValidExist == 0 && (valid_all_data == 1)) begin
			ValidExist <= 1;
			ct_valid_out <= Out_data_valid;
		end
				
		// Send adf output
		if(ValidExist == 0 && !(TestNValid == 16)) begin
			ct_valid_out <= 1'b1;			
		end				
		
		//Output
		Out_data <= Out_data;
		Out_data_valid <= Out_data_valid;
						
		state <= s0;			
end 
// FIX: End case statement

endcase

========================================================
example14_i-c_t-0.9.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-c_t-0.9.v
//	default: begin
//			Out_data_final <= {16{1'bx}, Out_data};
			ct_valid_out <= 1'b0;	
			state <= s0;
//	end

endcase

========================================================
example16_i-c_t-0.9.v
	default : 
		state <= s0;
	
endcase

========================================================
example17_i-c_t-0.9.v
	default: begin
				dii_data_vld  <= 1'b0;
				dii_data      <= dii_data;
				state <= s0;
				ct_valid_out <= 1'b0;
		end
	
	
endcase

========================================================
example18_i-c_t-0.9.v
	default: begin
			state <= s0;
		
		end
		
	
endcase

========================================================
example19_i-c_t-0.9.v
	default: begin
			Out_data_final <= Out_data;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example0_i-d_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example2_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example3_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-d_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-d_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example9_i-d_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example11_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example12_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example13_i-d_t-0.1.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example14_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example15_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example16_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example17_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example18_i-d_t-0.1.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example19_i-d_t-0.1.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example0_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-d_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example2_i-d_t-0.3.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example3_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-d_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-d_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-d_t-0.3.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example9_i-d_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-d_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example11_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example12_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example13_i-d_t-0.3.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example14_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example18_i-d_t-0.3.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example19_i-d_t-0.3.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-d_t-0.5.v
	default: begin
		state <= s0;
	end
// Write a default case statement where initial state is assigned to state
// FIX:
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example1_i-d_t-0.5.v
	default: begin
		state <= s0;
	end
		
	
endcase

========================================================
example2_i-d_t-0.5.v
	default: begin
		state <= s0;
	end

endcase

========================================================
example3_i-d_t-0.5.v
	default: begin
		Out_data_final <= Out_data;
		ct_valid_out <= 1'b0;
		state <= s0;
	end
	
endcase

========================================================
example4_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example6_i-d_t-0.5.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example7_i-d_t-0.5.v
//	default: begin
//		state <= s0;
//	end
end


endcase

========================================================
example8_i-d_t-0.5.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example9_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-d_t-0.5.v
	default: begin
				state <= s0;
			end
	
endcase

========================================================
example11_i-d_t-0.5.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example12_i-d_t-0.5.v
	default: begin
			state <= s0;
	end
	
endcase

========================================================
example13_i-d_t-0.5.v
	default: begin
			state <= s0;
	end
	
endcase

========================================================
example14_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example15_i-d_t-0.5.v
	default:
		state <= s0;
	
endcase

========================================================
example16_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example17_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example18_i-d_t-0.5.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example19_i-d_t-0.5.v
		default: begin
				state <= s0;
			end
	
endcase

========================================================
example0_i-d_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example1_i-d_t-0.7.v
	default: begin
			state <= s0;
	end
	
endcase

========================================================
example2_i-d_t-0.7.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example3_i-d_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example4_i-d_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example5_i-d_t-0.7.v
	default: 
		state <= s0;
	
endcase

========================================================
example6_i-d_t-0.7.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example7_i-d_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example8_i-d_t-0.7.v
	default: begin
		state <= s0;
	end
// Write a default case statement where initial state is assigned to state
// FIX:


endcase

========================================================
example9_i-d_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-d_t-0.7.v
	
endcase

========================================================
example11_i-d_t-0.7.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example12_i-d_t-0.7.v
	default: begin
		state <= s0;
	end

endcase

========================================================
example13_i-d_t-0.7.v
	default: begin
		state <= s0;
	end


endcase

========================================================
example14_i-d_t-0.7.v
	default: begin
			state <= s0;
			ct_valid_out <= 1'b0;
			Out_data_final <= 16'b0;
	end	
		
	
endcase

========================================================
example15_i-d_t-0.7.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example16_i-d_t-0.7.v
	default: 
		state <= s0;
	
endcase

========================================================
example17_i-d_t-0.7.v
//	default: state <= s0;
//
end


endcase

========================================================
example18_i-d_t-0.7.v
	default:
		begin
			state <= s0;
		end

endcase

========================================================
example19_i-d_t-0.7.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example0_i-d_t-0.9.v
		default: begin
			Out_data_final <= Out_data_c;
			ct_valid_out <= 1'b0;
			state <= s0;
		end
	
endcase

========================================================
example1_i-d_t-0.9.v
//  Case(state)
//    Input state [= state]
//    Output out_data_final [= out_data_final]
//    Output ct_valid_out [= ct_valid_out]
//    Output dii_data_vld [= dii_data_vld]
//    Output dii_data_type [= dii_data_type]
//    Output dii_data_size [= dii_data_size]
//    Output dii_data [= dii_data]
//    Output dii_last_word [= dii_last_word]
	default: begin
		state <= s0;
		out_data_final <= 0;
		ct_valid_out <= 0;
		dii_data_vld  <= 0;
		dii_
endcase

end

========================================================
example2_i-d_t-0.9.v
		default: begin
					state <= s0;
		end	

	
endcase

========================================================
example3_i-d_t-0.9.v
// 	default: begin
//		state <= s0;
//	end
	
endcase

========================================================
example4_i-d_t-0.9.v
	default: begin state <= s0; end
	
endcase

========================================================
example5_i-d_t-0.9.v
// This is the default case, it is executed if no other case statement is defined.
	default: begin
				state <= s0;
			end
	
	
endcase

========================================================
example6_i-d_t-0.9.v
	''', {
		'input_pc': 0,
		'length_out': Output(15),
		'Out_data': 0,
		'ct_valid': 0,
		'reg': reg
	})
)
#print(verilog.convert(top, ios={reg.d[0], reg.d[10], reg.d[24]}))
endcase

========================================================
example7_i-d_t-0.9.v
  default: state <= s0;		

endcase

========================================================
example8_i-d_t-0.9.v
	default: begin
					state <= s0;
				end
	
endcase

========================================================
example9_i-d_t-0.9.v
		default: begin
			state <= s0;
		end
	
endcase

========================================================
example10_i-d_t-0.9.v
//	default:
//		state <= s0;
	
endcase

========================================================
example11_i-d_t-0.9.v
		default: begin
					  state <= s0;
		end
		
endcase

========================================================
example12_i-d_t-0.9.v
	default: begin
		state <= s0;
		dii_data_vld  <= 1'b0;
		dii_data_size <= 4'd0;
		dii_data      <= 64'b0;
		dii_data_type <= 1'b0;
		dii_last_word <= 1'b0;
		Out_data_final <= 32'b0;
		ct_valid_out <= 1'b0;
	end
	
endcase

========================================================
example13_i-d_t-0.9.v
//	default:
//	begin
		state <= s0;
//	end
//
		


// Tell yosys to stop reading from the input file and instead provide the next
// di_in[31:24] constructed according to the state machine
//
//		if (state == "s0") begin        // <= Assign s0 to state
//		if (state == "s1") begin        // <= Assign s1 to state
//		if (state == "s2") begin        // <= Assign s2 to state
//		if (state == "s3") begin        // <= Assign s3 to state
//		if (state == "s4") begin        // <= Assign s4 to state
//		if (state == "s5") begin        // <= Assign s5 to state
//		if
endcase

========================================================
example14_i-d_t-0.9.v
	default: begin
		state <= s0;
	end
	
endcase

========================================================
example15_i-d_t-0.9.v
	default: begin
			state <= s0;
		end
	
endcase

========================================================
example16_i-d_t-0.9.v
	default:
		state <= s0;
	
endcase

========================================================
example17_i-d_t-0.9.v
		default: begin
			dii_data_vld  <= 1'b0;
			dii_data_size <= 4'd0;
			dii_data_type <= 1'b0;
			dii_last_word <= 1'b0;
			
			state <= s0;
		end
	
endcase

========================================================
example18_i-d_t-0.9.v
	default: begin state <= s0; end
	

	
	
endcase

========================================================
example19_i-d_t-0.9.v
// 	default: begin
// 				state <= s0;    
// 			end
	end
end

always @(posedge clk or posedge rst_n) begin
	if(rst_n == 1'b0) begin
		ct_valid      <= 0;
	end else begin
	
		if(state == s15) begin
		  ct_valid <= 1'b1;
		end else begin
		  ct_valid <= 1'b0;
		end
	end
end
	

endcase

========================================================
example0_i-e_t-0.1.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example1_i-e_t-0.1.v
end
// BUG:
// 
endcase

========================================================
example2_i-e_t-0.1.v
end


endcase

========================================================
example3_i-e_t-0.1.v
end


endcase

========================================================
example4_i-e_t-0.1.v
end
// BUG:
// always @(posedge clk) begin
always @(posedge clk) begin
// FIX:
    if(rst == 1'b1) begin
        state <= s0;
        ct_valid <= 1'b0;
        ct_valid_out <= 1'b0;
        dii_data_vld <= 1'b0;
        dii_data_size <= 4'd0;
        dii_data <= 128'b0;
        dii_data_type <= 1'b0;
        dii_last_word <= 1'b0;
        Out_data_final <= 128'b0;
        Out_data_final_valid <= 1'b0;
        Out_data_final_valid_out <= 1'b0;
        Out_data_final_type
endcase

end

========================================================
example5_i-e_t-0.1.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example6_i-e_t-0.1.v
end


endcase

========================================================
example7_i-e_t-0.1.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example8_i-e_t-0.1.v
end

endcase

========================================================
example9_i-e_t-0.1.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example10_i-e_t-0.1.v
end


endcase

========================================================
example11_i-e_t-0.1.v
end
// BUG:
// 
endcase

========================================================
example12_i-e_t-0.1.v
end
// BUG:
// 
endcase

========================================================
example13_i-e_t-0.1.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example14_i-e_t-0.1.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example15_i-e_t-0.1.v
end


endcase

========================================================
example16_i-e_t-0.1.v
end


endcase

========================================================
example17_i-e_t-0.1.v
end
// BUG:
// 
endcase

========================================================
example18_i-e_t-0.1.v
end


endcase

========================================================
example19_i-e_t-0.1.v
end
// BUG:
// 
endcase

========================================================
example0_i-e_t-0.3.v
end
// BUG:
// always @(*) begin
// FIX:
always @* begin
	ct_valid_out <= 1'b0;
	Out_data_final <= 0;
	dii_data_vld  <= 1'b0;
	dii_data_size <= 4'd0;
	dii_data      <= 0;
	dii_data_type <= 1'b0;
	dii_last_word <= 1'b0;
	
	case(state)
	s0: begin
		if(reset_n == 1'b1) begin
			state <= s0;
		end else begin
			state <= s1;
		end
	end
	s1: begin
		if(ct_valid == 1) begin
			state <= s2;
endcase

end

end

========================================================
example1_i-e_t-0.3.v
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
// BUG:
// end
// FIX:
end
//
endcase

========================================================
example2_i-e_t-0.3.v
end


endcase

========================================================
example3_i-e_t-0.3.v
end
// BUG:
// end
// FIX:
end



endcase

========================================================
example4_i-e_t-0.3.v
end
// BUG:
// 
endcase

========================================================
example5_i-e_t-0.3.v
end
// BUG:
// always @(posedge clk) begin
always @* begin
// FIX:
    if(reset) begin
        state <= s0;
    end else begin
        state <= state_next;
    end
// BUG:
//	end
// FIX:
end

endcase

========================================================
example6_i-e_t-0.3.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example7_i-e_t-0.3.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example8_i-e_t-0.3.v
end


endcase

========================================================
example9_i-e_t-0.3.v
end
// BUG:
// 
endcase

========================================================
example10_i-e_t-0.3.v
end

endcase

========================================================
example11_i-e_t-0.3.v
end
// BUG:
//	end
// FIX:
end


endcase

========================================================
example12_i-e_t-0.3.v
end
// BUG:
// 
endcase

========================================================
example13_i-e_t-0.3.v
end
// BUG:
// end
// FIX:
end

endcase

========================================================
example14_i-e_t-0.3.v
end

endcase

========================================================
example15_i-e_t-0.3.v
end
// BUG:
//	end
// FIX:
end


endcase

========================================================
example16_i-e_t-0.3.v
end
// BUG:
// 
endcase

========================================================
example17_i-e_t-0.3.v

endcase

========================================================
example18_i-e_t-0.3.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example19_i-e_t-0.3.v
end


endcase

========================================================
example0_i-e_t-0.5.v
end

endcase

========================================================
example1_i-e_t-0.5.v
end

endcase

========================================================
example2_i-e_t-0.5.v
    end
// BUG:
//	
endcase

========================================================
example3_i-e_t-0.5.v

end


endcase

========================================================
example4_i-e_t-0.5.v
end
// BUG:
// 
endcase

========================================================
example5_i-e_t-0.5.v
end
// BUG:
// always @(posedge clk) begin
// FIX:
always @(posedge clk)
begin
	if (rst == 1'b1) begin
		state <= s0;
		ct_valid <= 1'b0;
		ct_valid_out <= 1'b0;
		Out_data <= 0;
		Out_data_final <= 0;
	end else begin
		state <= next_state;
		ct_valid <= ct_valid_out;
		Out_data <= Out_data_final;
	end
end

endcase

========================================================
example6_i-e_t-0.5.v
end
// BUG:
// 
endcase

========================================================
example7_i-e_t-0.5.v
end
// BUG:
// always @(posedge clk) begin
always @(posedge clk or negedge rst_n) begin
// FIX:
	if(!rst_n) begin
		state <= s0;
		dii_data <= 0;
	end else begin
		state <= state_next;
	end
end


endcase

========================================================
example8_i-e_t-0.5.v
end

endcase

========================================================
example9_i-e_t-0.5.v
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// BUG:
//	end
// FIX:
end
// B
endcase

========================================================
example10_i-e_t-0.5.v
end
// BUG:
// 
endcase

========================================================
example11_i-e_t-0.5.v
end
// BUG:
// end
// FIX:
end


endcase

========================================================
example12_i-e_t-0.5.v
end


endcase

========================================================
example13_i-e_t-0.5.v
end
// BUG:
//	end
// FIX:
end

// BUG:
//	
endcase

========================================================
example14_i-e_t-0.5.v
end

always @(posedge clk) begin
	if(rst == 1'b1) begin
		state <= s0;
		dii_data_vld  <= 1'b0;
		dii_data_size <= 4'd0;
		dii_data      <= 128'b0;
		dii_data_type <= 1'b0;
		dii_last_word <= 1'b0;
		
		Out_data_final <= 128'b0;
		ct_valid_out <= 1'b0;
	end else begin
		state <= state_next;
	end
end


endcase

========================================================
example15_i-e_t-0.5.v

end


endcase

========================================================
example16_i-e_t-0.5.v
end
// BUG:
// 
endcase

========================================================
example17_i-e_t-0.5.v
end


endcase

========================================================
example18_i-e_t-0.5.v
end

endcase

========================================================
example19_i-e_t-0.5.v
end

endcase

========================================================
example0_i-e_t-0.7.v
end
// BUG:
// always @(posedge clk) begin
// FIX:
always @(posedge clk) begin
    if(rst) begin
        state <= s0;
        ct_valid <= 1'b0;
        ct_data <= 64'b0;
    end else begin
        case(state)
// BUG: Incomplete case statement
// 
endcase

end

========================================================
example1_i-e_t-0.7.v
end

// BUG: Missing assignment in the logic expression.
if(has_data_to_tx == 1) begin
// FIX:
if(has_data_to_tx == 1) begin
		dii_data_vld <= 1'b1;
		dii_data <= input_pc;
		dii_data_type <= 1'b1;
		dii_last_word <= 1'b0;
end
// BUG: Missing assignment in the logic expression.
if(has_data_to_tx == 1) begin
		if(last_data == 1) begin
			dii_last_word <= 1'b1;
		end
// BUG: Missing assignment in the logic expression.
if(has_data_to_tx == 1) begin
		if(last_data ==
endcase

end

end

========================================================
example2_i-e_t-0.7.v
end


endcase

========================================================
example3_i-e_t-0.7.v
end


endcase

========================================================
example4_i-e_t-0.7.v

endcase

========================================================
example5_i-e_t-0.7.v
end
// end
//

endcase

========================================================
example6_i-e_t-0.7.v
end
// end of automatics
	end

endcase

========================================================
example7_i-e_t-0.7.v
end
// BUG:
//always @(posedge clk) begin
always @(posedge clk) begin
	if(rst == 1) begin
		state <= s0;
	end else begin
		state <= state_next;
	end
end

endcase

========================================================
example8_i-e_t-0.7.v
end
// BUG:
// 
endcase

========================================================
example9_i-e_t-0.7.v
end
// BUG: Incomplete case statement
// 
endcase

========================================================
example10_i-e_t-0.7.v
    
endcase

========================================================
example11_i-e_t-0.7.v
	
endcase

========================================================
example12_i-e_t-0.7.v
end


endcase

========================================================
example13_i-e_t-0.7.v
end


endcase

========================================================
example14_i-e_t-0.7.v
end


endcase

========================================================
example15_i-e_t-0.7.v

end


endcase

========================================================
example16_i-e_t-0.7.v
//	end
end

endcase

========================================================
example17_i-e_t-0.7.v
end


endcase

========================================================
example18_i-e_t-0.7.v
end

endcase

========================================================
example19_i-e_t-0.7.v
end

endcase

========================================================
example0_i-e_t-0.9.v
end
////////////////////////////////////////////////////////////////////////////////////////
//Debug_print
always @(posedge CLK) begin
	if (RST) begin
		//$display("%c",64);
		$display("%c",In_data);
        //$display("%c",68);
		$display("");
	end
end
////////////////////////////////////////////////////////////////////////////////////////
//`ifndef test_hw
int main() {
	
	initial begin 
		$write("--Verilog Arithmetic Check--");
		$write("--Unit Type : %t--",				1);
		$write("--Verilog : %e--",					"text_fsm.v");	
		$write("--Total FSM : %e--",				10);
		$write("--Total Transition : %
endcase

========================================================
example1_i-e_t-0.9.v
end
// BUG: Incomplete case statement
// 
endcase

========================================================
example2_i-e_t-0.9.v

endcase

========================================================
example3_i-e_t-0.9.v
end
end

module edi
(
	input logic [15:0] 			edi_06_15,
	input logic [3:0] 			edi_04_03,
	input logic [107:0] 		edi_03_00,
	output logic [15:0]			edi_out_15_00,
	input 						edi_ena,
	input 						edi_reset1,
	input 						edi_reset2
);

reg [15:0]		next_edi_06_15;
reg [3:0]		next_edi_04_03;
reg [107:0]		next_edi_03_00;
reg [15:0]		nxt_edi_out_
endcase

========================================================
example4_i-e_t-0.9.v
end


// Your code here

endcase

========================================================
example5_i-e_t-0.9.v

end


endcase

========================================================
example6_i-e_t-0.9.v
			
endcase

========================================================
example7_i-e_t-0.9.v
end
end
end
end
end
endcase

========================================================
example8_i-e_t-0.9.v
end
// end of state machine

// hook up DII
ct_dfi_ps.PrDfi[0] <= ct_dii_rd_data;
ct_dfi_ps.PmDfi[0] <= ct_dii_wr_data;
ct_dfi_ps.PcDfi[0] <= ct_dii_cke;
ct_dfi_ps.PcDfi[0] <= ct_dii_cs;
ct_dfi_ps.PcDfi[0] <= ct_dii_rras;
ct_dfi_ps.PcDfi[0] <= ct_dii_cas;
ct_dfi_ps.PcDfi[0] <= ct_dii_we;
ct_dfi_ps.PrDfi[
endcase

========================================================
example9_i-e_t-0.9.v
end
// end always
endcase

========================================================
example10_i-e_t-0.9.v
	 
endcase

========================================================
example11_i-e_t-0.9.v

endcase

========================================================
example12_i-e_t-0.9.v

endcase

========================================================
example13_i-e_t-0.9.v
    end
// BUG:
//    		// Condition 1 //////////////////////////////////////
//    		// if ( In_data_vld == 0 )
//    		//	begin // Fetch
//    		// end
    else begin
    	state <= s0;
    end
    
endcase

========================================================
example14_i-e_t-0.9.v

end

endcase

========================================================
example15_i-e_t-0.9.v
end // end of state case statement
 

endcase

========================================================
example16_i-e_t-0.9.v
end
end

endcase

========================================================
example17_i-e_t-0.9.v

endcase

========================================================
example18_i-e_t-0.9.v
end
//
"""
f.write(temp)
f.close()

###########################################################################################
temp = ""
f=open("layer_synthesis.v","w+")

f.write("`timescale 1ps / 1ps\nmodule layer_synthesis;\n\n")

parameter = 	"parameter LENGTH_MATRIX   = {},\n".format(WIDTH + 1)
parameter +=	"parameter LENGTH_OSERDES  = {},\n".format(WIDTH)
parameter +=	"parameter LENGTH_ISERDES  = {},\n".format(WIDTH)
parameter +=	"parameter LENGTH_OBUF     = {},\n".format(len(pair_list))
parameter +=	"parameter LENGTH_IBUF    
endcase

========================================================
example19_i-e_t-0.9.v
    end

endcase

========================================================
