example0_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [63:0] pmp_cfg_reg_lsb_new, pmp_cfg_reg_msb_new;
  reg [63:0] pmp_cfg_en_lsb_new, pmp_cfg_en_msb_new; 

  reg [
========================================================
example1_i-a_t-0.1.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example2_i-a_t-0.1.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
========================================================
example3_i-a_t-0.1.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example4_i-a_t-0.1.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example5_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_NONE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0;
end

end

========================================================
example6_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example7_i-a_t-0.1.v
  reg [2:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example8_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_new, pmp_cfg_reg_old;
  reg [63:0] pmp_cfg_reg_new_old; 
  reg [63:0] pmp_cfg_reg_new_old_old; 
  reg [63:0] pmp_cfg_reg_new_old_old_old; 
  reg [63:0] pmp_cfg_reg_new_old_old_old_old; 
  reg [63:0] pmp_cfg_reg_new_old_old_old_old_old; 
  reg
========================================================
example9_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_NONE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
end

end

========================================================
example10_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example11_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb; 
  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb; 
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb; 
  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_msb; 
  reg pmp_addr_
========================================================
example12_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_NONE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
end

end

========================================================
example13_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_new; 
  reg [63:0] pmp_cfg_reg_old; 
  reg [63:0] pmp_cfg_reg_new_old; 

  reg [63:0] pmp_cfg_reg_new_old_old; 
  reg [63:0] pmp_cfg_reg_new_old_old_old; 
  reg [63:0] pmp_cfg_reg_new_old_old_old_old; 
  reg [63:0] pmp_cfg_reg_new_old_old_
========================================================
example14_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_cfg_reg <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_
end

end

========================================================
example15_i-a_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_2, pmp_cfg_new_2;
  reg pmp_cfg_en_2; 

  reg [63:0] pmp_cfg_reg_3, pmp_cfg_new_3;
  reg pmp_cfg_en_3; 

  reg [63:0] pmp_cfg_reg_4, pmp_cfg_new_4;
  reg pmp_cfg_en_4; 

  reg [63:0] pmp_cfg_reg_5, pmp_cfg_new_5;
  reg pmp_cfg_en_5
========================================================
example16_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_cfg_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example17_i-a_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [63:0] pmp_cfg_reg_lsb_d, pmp_cfg_reg_msb_d;
  reg [63:0] pmp_cfg_new_lsb_d, pmp_cfg_new_msb_d;
  reg pmp_cfg_en_
========================================================
example18_i-a_t-0.1.v
  reg [1:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example19_i-a_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0;
end

end

========================================================
example0_i-a_t-0.3.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Combinational Logic
  assign valid_o = (dma_ctrl_reg == CTRL_DONE) ? 1'b1 : 1'b0;

  //// DMA Control Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      start_d <= 0;
      length_d <= 0;
      source_addr_
end

end

========================================================
example1_i-a_t-0.3.v
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
// BUG:
//  reg pmp_cfg_en; 
// FIX:
  reg [16-1:0] pmp_addr_reg, pmp_addr_new; 
// BUG:
//  reg pmp_addr_en; 
// FIX:
  reg pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_addr_reg, pmp_addr_new; 
  reg pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or risc
========================================================
example2_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
end

end

========================================================
example3_i-a_t-0.3.v
  logic [7:0] pmpcfg_reg, pmpcfg_new;
  logic pmpcfg_en; 
  logic we_flag_reg, we_flag_new;

  //// DUT
  dma_controller dma_inst(
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .start_i(start_i),
    .length_i(length_i),
    .source_addr_lsb_i(source_addr_lsb_i),
    .source_addr_msb_i(source_addr_msb_i),
    .dest_addr_lsb_i(dest_addr_lsb_i),
    .dest_addr_msb_i(dest_addr_msb_i),
    .valid_o
========================================================
example4_i-a_t-0.3.v
  reg [7:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new;
  reg data_en; 

  reg [63:0] data_addr_reg, data_addr_new;
  reg data_addr_en; 

  reg [63:0] data_addr_reg_prev, data_addr_new_prev;
  reg data_addr_en_prev; 

  reg [63:0] data_addr_reg_next, data_addr_new_next;
  reg data_addr_en_next; 

  reg [63:0] data_addr_reg_prev_prev, data_addr_new_prev_prev;
  reg data_addr_en_prev_prev; 

  reg [63:0]
========================================================
example5_i-a_t-0.3.v
  reg pmp_access_type_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_en <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_access_type_en <= 0;
    
end

end

========================================================
example6_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_reg_lsb, pmpaddr_reg_msb;
  reg [63:0] pmpaddr_new_lsb, pmpaddr_new_msb;

  reg [63:0] pmpaddr_reg_lsb_lsb, pmpaddr_reg_lsb_msb;
  reg [63:0] pmpaddr_reg_msb_lsb, pmpaddr_reg_msb_msb;
  reg [
========================================================
example7_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Functions

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_cfg_reg <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_
end

end

========================================================
example8_i-a_t-0.3.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
      pmp_cfg_reg <= 0;
      pmp_cfg_new <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_new <= riscv::ACCESS_WRITE;
      pmp_access_type_en <= 0;
      pmp_cfg_en <= 0;
      pmp_addr_en <= 0;
end

end

========================================================
example9_i-a_t-0.3.v
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg, dma_ctrl_new; 
  reg dma_ctrl_en; 
  
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  riscv::pmp_access_t pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
// BUG:
//  reg pmp_access_type_en; 
// FIX:
  reg [7:0] pmp_cfg_reg,
========================================================
example10_i-a_t-0.3.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [63:0] pmpcfg_addr_reg, pmpcfg_addr_new;
  reg pmpcfg_addr_en; 

  reg [63:0] pmpaddr_addr_reg, pmpaddr_addr_new;
  reg pmpaddr_addr_en; 

  reg [63:0] pmpcfg_data_reg, pmpcfg_data_new;
  reg pmpcfg_data_en; 

  reg [63:0] pmpaddr_data_reg, pmpaddr_data_new;
  reg pmpaddr_
========================================================
example11_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Local Variables
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 
  reg [63:0] pmp_addr_reg_next;
  reg [63:0] pmp_cfg_reg_next;
  reg [1:0] pmp_access_type_reg_next;

  reg [DATA_WIDTH-1:0] start_d_next; 
  reg [DATA_WIDTH-1:0] length_d_next;
  reg [DATA_WIDTH-1:0] source_addr_lsb
========================================================
example12_i-a_t-0.3.v
  reg pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new;
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new;
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new;
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new;
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new;
  reg [DATA_WIDTH
========================================================
example13_i-a_t-0.3.v
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_en; 
  
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg
========================================================
example14_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, p
========================================================
example15_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_NONE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
end

end

========================================================
example16_i-a_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_d, pmp_cfg_new_d; 
  reg pmp_cfg_en_d; 

  reg [63:0] pmp_addr_reg_d, pmp_addr_new_d;
  reg pmp_addr_en_d;  

  reg [63:0] pmp_access_type_reg_d, pmp_access_type_new_d; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
// BUG:
//  reg pmp_access_type_en_d;
========================================================
example17_i-a_t-0.3.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  
  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_lsb_reg, pmpaddr_lsb_new;
  reg pmpaddr_lsb_en; 

  reg [63:0] pmpaddr_msb_reg, pmpaddr_msb_new;
  reg pmpaddr_msb_en; 

  reg [63:0] pmpaddr_lsb_reg_old, pmpaddr_lsb_new_old;
  reg pmpaddr_lsb_en_old; 

  reg [63:0] pmpaddr_msb
========================================================
example18_i-a_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  //// Local Variables
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 
  reg [63:0] pmp_addr; 
  reg [63:0] pmp_addr_next; 
  reg [1:0] pmp_access_type; 
  reg [1:0] pmp_access_type_next; 
  reg [63:0] pmp_addr_next_lsb; 
  reg [63:0] pmp_addr_next_msb; 
  reg [63:0] pmp_addr_next_lsb_msb; 

========================================================
example19_i-a_t-0.3.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] source_addr_delta_reg, source_addr_delta_new; 
  reg [DATA_WIDTH-1:0] dest_addr_delta_reg, dest_addr_delta_new; 
  reg [DATA_WIDTH-1:0]
========================================================
example0_i-a_t-0.5.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;  

  reg [63:0] pmp_access_addr_lsb_reg, pmp_access_addr_lsb_new;
  reg pmp_access_addr_lsb_en;  

  reg [63:0] pmp_access_addr_msb_reg, pmp_access_addr_msb_new;
  reg pmp_access_addr_msb_en;  

  reg [63:0] pmp_access_length_reg, pmp_access_length_new;
  reg pmp_access_length_en;  

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
========================================================
example1_i-a_t-0.5.v
  reg pmp_access_type_en_d; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Local vars
  reg [DATA_WIDTH-1:0] load_count; 
  reg [DATA_WIDTH-1:0] store_count; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  reg [63:0] pmp_cfg;
  reg [63:0] pmp_addr; 
  reg pmp_access_type; 

  reg dma_ctrl_en_d;
  reg pmp_cfg_en_d;
  reg pmp_addr_en_d;
  reg pmp_access_type
========================================================
example2_i-a_t-0.5.v
  reg [63:0] pmp_access_type_en; 

  //// Local RAMs

  logic [DATA_WIDTH-1:0] [DMA_BUF_SIZE-1:0] dma_buf;
  logic [DATA_WIDTH-1:0] [DMA_BUF_SIZE-1:0] dma_buf_next_write;
  logic [DATA_WIDTH-1:0] [DMA_BUF_SIZE-1:0] dma_buf_next_read;

  //// Combinational logic
  assign valid_o = dma_ctrl_reg[VALID_IDLE] | dma_ctrl_reg[VALID_LOAD] | dma_ctrl_reg[VALID_STORE] | dma_ctrl_reg[VALID_DONE];

 
========================================================
example3_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 


  //// DUT

  riscv::dma_t dma (
    .clk_i(clk_i),
    .rst_ni(rst_ni),
    .start_i(start_i),
    .length_i(length_i),
    .source_addr_lsb_i(source_addr_lsb_i),
    .source_addr_msb_i(source_addr_msb_i),
    .dest_addr_lsb_i(dest_addr_lsb_i),
    .dest_addr_msb_i(dest_addr_msb_i),
    .valid_o(valid_o),
    .done_i(done_i),
    .pmpcfg_i
========================================================
example4_i-a_t-0.5.v
  wire pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// DMA Control
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new; 
  reg dma_ctrl_en; 

  //// PMP Control
  reg [63:0] pmp_addr_reg;
  reg [63:0] pmp_addr_new;
  reg pmp_addr_en;  

  riscv::pmp_access_t pmp_access_type_reg; // riscv::ACCESS_WRITE or riscv::ACCESS
========================================================
example5_i-a_t-0.5.v
  reg [6:0] pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;  
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i or posedge rst_ni) begin
    if(rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_en <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
    
end

end

========================================================
example6_i-a_t-0.5.v
  reg [3:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] valid_reg;
  reg [DMA_CTRL_WIDTH-1:0] valid_valid_reg; 
  reg [63:0] valid_valid_reg_pmp_addr; 
  reg [3:0] valid_valid_reg_pmp_access_type; 


  //// DMA controller
  wire [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_next; 

  //// PMP controller
  wire [63:0] pmp_addr_next; 
  reg [63:0] pmp_addr
========================================================
example7_i-a_t-0.5.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_ctrl_reg, pmp_access_ctrl_new;
  reg pmp_access_ctrl_en; 

  reg [63:0] pmp_access_ctrl_result_reg, pmp_access_ctrl_result_new;
  reg pmp_access_ctrl_result_en;
========================================================
example8_i-a_t-0.5.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  
  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;  

  reg [7:0] pmpcfg_i_reg, pmpcfg_i_new; 
  reg [63:0] pmpaddr_i_reg, pmpaddr_i_new; 

  reg [63:0] pmpcfg_i_reg_reg, pmpcfg_i_new_reg; 
  reg [63:0] pmpaddr_i_reg_reg, pmpaddr_i_new_reg; 

  reg [63:0] pmpcfg_i_reg_reg_reg, pmpcfg_i_new_reg
========================================================
example9_i-a_t-0.5.v
  reg [7:0] pmp_access_type_en; 

  reg [63:0] dma_addr_reg, dma_addr_new;
  reg dma_addr_en; 
  reg [63:0] dma_data_reg, dma_data_new;
  reg dma_data_en; 
  reg [63:0] dma_data_next_reg, dma_data_next_new;
  reg dma_data_next_en; 
  reg [63:0] dma_data_next_next_reg, dma_data_next_next_new;
  reg dma_data_next_next_en; 
  reg [63:0] dma_data_next_next_next_reg, dma_data_next_next_next_
========================================================
example10_i-a_t-0.5.v
  reg pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] pmp_data_reg;
  reg [DATA_WIDTH-1:0] pmp_data_new;
  reg pmp_data_en; 

  reg [DATA_WIDTH-1:0] pmp_mask_reg;
  reg [DATA_WIDTH-1:0] pmp_mask_new;
  reg pmp_mask_en; 

  reg [DATA_WIDTH-1:0] pmp_result_reg;
  reg [DATA_WIDTH-1:0] pmp_result_new;
  reg pmp_result_en; 

  reg [DATA_WIDTH-1:0] pmp_data_i;
  reg [DATA_W
========================================================
example11_i-a_t-0.5.v
  riscv::pmp_access_t pmp_access_type_en; 


  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= DMA_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
    
end

end

========================================================
example12_i-a_t-0.5.v
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      pmp_cfg_reg <= 0; 
      pmp_cfg_new <= 0; 
      pmp_cfg_en <= 0; 
      pmp_addr_reg <= 0; 
      pmp_addr_new <= 0
end

end

========================================================
example13_i-a_t-0.5.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 
  
  reg [63:0] pmp_access_data_out; 
  reg [63:0] pmp_access_data_out_reg, pmp_access_data_out_new; 

  reg [63:0] pmp_access_data_in; 
  reg [63:0] pmp_access_data_in_reg, pmp_access_data_in_new; 

  reg [
========================================================
example14_i-a_t-0.5.v
  reg [63:0] pmp_access_type_en_reg, pmp_access_type_en_new; 

  reg dma_ctrl_state; 
  reg dma_ctrl_valid; 
  reg pmp_access_type_state;
  reg pmp_access_type_valid;

  always @(posedge clk_i or negedge rst_ni) begin
    if(rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_en <= 0; 
      dma_ctrl_state <= CTRL_IDLE; 
      dma_ctrl_valid <= 0; 

      pmp_addr_reg <= 0; 
      pmp_addr_en <= 0; 

      pmp_access_type_reg <= riscv
end

end

========================================================
example15_i-a_t-0.5.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
    
end

end

========================================================
example16_i-a_t-0.5.v
  reg pmp_access_type_en; 
// BUG:
//  reg pmp_access_type_en_reg, pmp_access_type_en_new;
// FIX:
  reg pmp_access_type_en_reg, pmp_access_type_en_new;
  reg [63:0] pmp_addr_reg_reg, pmp_addr_reg_new;
  reg [63:0] pmp_addr_new_reg, pmp_addr_new_reg;

  reg [63:0] pmp_addr_reg_reg_reg, pmp_addr_reg_reg_new;
  reg [63:0] pmp_addr_new_reg_reg, pmp_addr_new_reg_new;

  reg [63:0] pmp_addr_reg_
========================================================
example17_i-a_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// DMA logic
  reg [DATA_WIDTH-1:0] queued_start_d; 
  reg [DATA_WIDTH-1:0] queued_length_d; 
  reg [DATA_WIDTH-1:0] queued_source_addr_lsb_d; 
  reg [DATA_WIDTH-1:0] queued_source_addr_msb_d; 
  reg [DATA_WIDTH-1:0] queued_dest_addr_lsb_d; 
  reg [DATA_WIDTH-1:0] queued_
========================================================
example18_i-a_t-0.5.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  
  //// Local variables

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DATA_WIDTH-1:0] source_addr_reg, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr_reg, dest_addr_new; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new;
========================================================
example19_i-a_t-0.5.v
  reg pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] counter_reg, counter_new; 
  reg [DATA_WIDTH-1:0] counter_en; 
  reg [DATA_WIDTH-1:0] data_out_reg, data_out_new; 
  reg [DATA_WIDTH-1:0] data_out_en; 

  //// Logic
  always @ (posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      counter_reg <= 0;
      data_out_reg <= 0;
      start_d
end

end

========================================================
example0_i-a_t-0.7.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Control Logic
  reg [7:0] ctrl_state;  
  wire [7:0] ctrl_new; 
  assign ctrl_new = ctrl_state; 
  reg [7:0] pmp_ctrl_state; 
  wire [7:0] pmp_ctrl_new; 
  assign pmp_ctrl_new = pmp_ctrl_state; 
  reg [7:0] pmp_access_type_ctrl_state; 
  wire [7:0] pmp_access_type_ctrl_new; 
  assign pmp_access_type_ctrl_new = p
========================================================
example1_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en;
  always @(posedge clk_i) begin
    if (rst_ni) begin 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= 0;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= 0;
    
end

end

========================================================
example2_i-a_t-0.7.v
reg pmp_access_type_en = 1'b0; 
reg pmp_access_type_en_i; 

  //// Local Vars

  reg [DMA_CTRL_WIDTH-1:0] ctrl_state_reg, ctrl_state_new; 

  reg dma_start_reg;
  reg dma_idle_reg;
  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] last_addr_reg;

  reg [8:0] counter, counter_max; 
  reg [8:0] counter_load, counter_store; 
  reg [8:0] counter_done; 
  reg [8:0] counter_abort; 
========================================================
example3_i-a_t-0.7.v
  wire pmp_access_type_en; 

  reg dma_state_reg; 
  reg [DMA_STATE_WIDTH-1:0] dma_state_new; 
  
  always @(posedge clk_i) begin
    if( rst_ni ) begin
      start_d         <= 0;
      length_d        <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      dma_ctrl_reg <= DMA_CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      dma_state
end

end

========================================================
example4_i-a_t-0.7.v
  reg [7:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_idx; 
  reg [7:0] pmp_cfg_idx_en; 

  reg [64:0] ctrl_state;
  reg [63:0] addr_reg; 
  reg [7:0] pmp_idx;
  reg [63:0] pmp_cfg_reg; 
  reg [16-1:0] pmp_cfg_idx_reg; 
  reg [63:0] pmp_addr_reg; 
  reg [16-1:0] pmp_addr_idx_reg; 
  reg [7:0] pmp_access_type_reg;  
  reg [7:0] pmp_access_type
========================================================
example5_i-a_t-0.7.v
  wire pmp_access_type_en, pmp_access_type_new_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [CTRL_WIDTH-1:0] ctrl_reg, ctrl_new; 
  reg ctrl_en;  


  //// Functions

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0;
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0;
end

end

========================================================
example6_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en; 
// END BUG

  //// Combinational logic
  assign rst_ni = (dma_ctrl_reg[CTRL_ABORT] != CTRL_ABORT) ? 1'b0 : 1'b1; 

  assign valid_o = dma_ctrl_reg[VALID_IDLE]; 
  assign done_d = done_i; 

  assign pmp_addr_reg = pmpaddr_i[53:0];
// BUG:
  assign pmp_addr_new = pmp_addr_reg;
  assign pmp_addr_en = 1'b0; 
// FIX:
  assign pmp_addr_new = pmp_addr_reg | pmp_addr_en;
  assign pmp_addr_en =
========================================================
example7_i-a_t-0.7.v
  logic pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] pmpcfg_d; 

  reg CTRL_STATE_TYPE ctrl_state;
  reg CTRL_STATE_TYPE ctrl_state_new; 
  reg CTRL_STATE_TYPE ctrl_state_next; 

  //// FSM
  switch(ctrl_state){
    case CTRL_IDLE :
      if(dma_ctrl_reg[CTRL_IDLE] && dma_ctrl_reg[CTRL_EN]){
        ctrl_state_next = CTRL_CHECK_LOAD; 
      }
      else if(rst_ni) {
        ctrl_state_next = CTRL_IDLE; 
      }
      else {
        ctrl_state_next = CTRL_ID
========================================================
example8_i-a_t-0.7.v
  reg pmp_access_type_en = 1; 

  reg [DMA_CTRL_WIDTH-1:0] data_ctrl_reg, data_ctrl_new; 
  reg data_ctrl_en; 

// BUG:
//  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg, dma_ctrl_new; 
//  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new; 
// FIX:
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new = CTRL_IDLE;
//  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_new; 

// BUG:
//  reg [DMA_CTRL
========================================================
example9_i-a_t-0.7.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en;
  reg pmpcfg_mem_en;
  reg pmpcfg_invalidate_en;
  reg pmpcfg_invalidate_done;

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;

  reg [63:0] pmpaddr_mem_reg, pmpaddr_mem_new;
  reg pmpaddr_mem_en;

  reg [63:0] pmpaddr_invalidate_reg, pmpaddr_invalidate_new;
  reg pmpaddr_invalidate_en;

  reg [63:0] pmpaddr_invalidate_done_reg, pmpaddr_invalidate_
========================================================
example10_i-a_t-0.7.v
  reg pmp_access_type_en_new; 
  reg pmp_access_type_en_old; 

  reg [63:0] pmp_addr_reg_old; 

  reg pmps_setting_reg;
  reg pmps_setting_new;
// BUG:
//  reg pmps_setting_en; 
// FIX:
  reg pmps_setting_en_new; 
  reg pmps_setting_en_old; 

  reg [31:0] pmps_setting_reg_old; 

  //// Module Instance
  dma_t dma_inst; 
  dma_t::io dma_io; 

  //// Clock Generation
  assign rst_ni = (clk_i == 'h0) ? 1'b1 : rst_ni
========================================================
example11_i-a_t-0.7.v
reg logic pmp_access_type_en; 
  reg logic pmp_access_type_sel; 
  
  reg valid_reg;

  reg [63:0] sram_addr_reg, sram_addr_new;
  reg sram_addr_en;

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0;
      done_d <= 0; 
      valid_reg <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      p
end

end

========================================================
example12_i-a_t-0.7.v
  reg [31:0]  pmp_access_type_en; 
  reg [31:0]  pmp_access_type_en_reg, pmp_access_type_en_new; 
  reg [31:0]  pmp_access_type_en_done; 
  
 
  //// Local variables
  reg [63:0] pmp_addr_start; 
  reg [63:0] pmp_addr_
========================================================
example13_i-a_t-0.7.v
  reg [15:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  
  reg [5:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;

  reg [1:0] pmpcfg_reg_l, pmpcfg_reg_h;
  reg [5:0] pmpaddr_reg_l, pmpaddr_reg_h;

  reg [1:0] pmpcfg_new_l, pmpcfg_new_h;
  reg [5:0] pmpaddr_new_l, pmpaddr_new_h;

  reg [1:0] pmpcfg_en_l, pmpcfg_en_h;
  reg [5:0] pmpaddr_en_l, pmpaddr_en
========================================================
example14_i-a_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] source_cnt;
  reg [DATA_WIDTH-1:0] dest_cnt;

  reg [DMA_STATE_WIDTH-1:0] dma_state; 
  reg [DMA_VALID_WIDTH-1:0] dma_valid; 

  reg [DMA_STATE_WIDTH-1:0] dma_state_new;

  //// Multiplier Control 
  reg [DMA_STATE_WIDTH-1:0] dma_mult_state_reg, dma_mult_
========================================================
example15_i-a_t-0.7.v
  reg pmp_access_type_en = 0; 
  reg [1:0] pmp_access_we_en; 
  
  //// Combinational Logic 
 
  assign start_d = start_i; 
  assign length_d = length_i; 
  assign source_addr_lsb_d = source_addr_lsb_i; 
  assign source_addr_msb_d = source_addr_msb_i; 
  assign dest_addr_lsb_d = dest_addr_lsb_i; 
  assign dest_addr_msb_d = dest_addr_msb_i; 
  assign done_d = done_i; 

  always @(posedge clk_i or posedge rst_ni) begin
    if (rst_ni == 1
end

========================================================
example16_i-a_t-0.7.v
reg logic [7:0] pmp_access_type_en; 
  reg logic [3:0] pmp_access_type_en_new; // 3-bit reg
  reg [5:0] pmp_cfg_reg, pmp_cfg_new;
// BUG:
//  reg pmp_cfg_en; 
// FIX:
reg logic [7:0] pmp_cfg_en; 
  reg logic [3:0] pmp_cfg_en_new; // 3-bit reg

  //// Logic 

  reg [3:0] ctrl_state_reg = CTRL_IDLE;
  wire [3:0] ctrl_state_new; 
  reg [3:0] ctrl_state_next; 

  reg [3:0] valid_state_reg = VALID_
========================================================
example17_i-a_t-0.7.v
  reg pmp_access_type_en, pmp_access_type_en_new; 

  reg [64-1:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [64-1:0] pmp_lvl_reg, pmp_lvl_new;
  reg pmp_lvl_en; 

  reg [1:0] pmp_lvl_access_mode_reg, pmp_lvl_access_mode_new; 
  reg pmp_lvl_access_mode_en; 


  reg [2:0] pmp_lvl_status_reg, pmp_lvl_status_new;
  reg pmp_lvl_status_en; 

  reg [1:0] pmp_lvl_xwr_status_reg,
========================================================
example18_i-a_t-0.7.v
  reg [31:0] pmp_access_type_en; 

  reg [31:0] pmp_access_size_reg, pmp_access_size_new;
// BUG:
//  reg pmp_access_size_en; 
// FIX:
  reg [31:0] pmp_access_size_en; 

  //// Methods
  reg [DATA_WIDTH-1:0] read_data; 
  reg [DATA_WIDTH-1:0] write_data; 
  reg [DATA_WIDTH-1:0] source_addr, source_addr_new; 
  reg [DATA_WIDTH-1:0] dest_addr, dest_addr_new; 

  reg [DMA_CTRL_WIDTH-1:0] ctrl_next
========================================================
example19_i-a_t-0.7.v
  logic pmp_access_type_en;  
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  reg [1:0] pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
// BUG:
//  reg pmp_access_type_en; 
// FIX:
  logic pmp_access_type_en;  
  

========================================================
example0_i-a_t-0.9.v
lsr
  reg [0];
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_new = riscv::ACCESS_READ;
      dma_ctrl_new = CTRL_IDLE;
      dma_ctrl_en = 1'b0;
      pmp_addr_new = 0;
      pmp_addr_en = 1'b0;
    
end

end

========================================================
example1_i-a_t-0.9.v
  reg [19:0] pmp_access_type_en =  1'b1;  // enable bit
// the corresponding pmp config variable is in KcuOnChipBridgeBottom module, and enable bit is controlled in KcuOnChipBridgeBottom module

// BUG:
//  reg enable_reg;
//  reg enable_new; 
  assign enable_reg =  2'd0;  
  wire [2-1:0] enable_new; 
  assign enable_new = enable_reg | pmp_access_type_en; 

  reg [31:0] pmp_instr_reg, pmp_instr_new;
  reg pmp_instr_en;
  
  reg [63:0] valid_reg, valid_i, valid_new; 
  reg valid_en;    

  reg [
========================================================
example2_i-a_t-0.9.v
  reg pmp_access_type_en, pmp_access_type_en_array [10]; // bit[0] = 0: write, bit[0] = 1: read
  always @(posedge clk_i) pmp_access_type_en_array[9:0] <= pmp_access_type_en;


  //// State Machine


  always @* begin
    update_regs();
    dma_ctrl_reg     <= dma_ctrl_new; 
    pmp_addr_reg     <= pmp_addr_new; 
    pmp_access_type_reg <= pmp_access_type_new; 
    
// BUG:
//    if (rst_ni) begin
//      dma_ctrl_new     <= (1<<DMA_CTRL_WIDTH-
end

========================================================
example3_i-a_t-0.9.v
  reg pmpcfg_new; 
  // BUG:
  //  reg [15:0] pmpcfg_new; // Used a 15-bit register; `pmpcfg_new` stores 15 bit value; 
  // BUG:
  //  Assumes 15-bit field from pmpcfg_new stored as is. FIX: Trace the specific bits. 
  // FIX: 

  reg [2:0] interrupt_status_reg;

  reg [DATA_WIDTH-1:0] *source_pntr_reg, *source_pntr_new, *source_pntr_current;
  reg [DATA_WIDTH-1:0] *dest_pntr_reg, *dest_pntr_new, *dest_pntr_current;
  reg [DATA_WIDTH-1
========================================================
example4_i-a_t-0.9.v
  reg [1 : 0] pmp_access_type_en; 
  
  reg   [7 : 0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en;    

  //// Memories
  memory signed [DATA_WIDTH-1:0]  dest_mem; 
  memory unsigned [DATA_WIDTH-1:0]  source_mem; 
 

  ////////////////////////////////////
  /// ASSERTIONS  
  ////////////////////////////////////
 
  // Check that DMA ctrl blocks lengths are < 3KiB (checked for in the code)
  assert  ((length_i & (DATA_WIDTH-1)) == 0)
    if (!rst_ni); 
    
========================================================
example5_i-a_t-0.9.v
  wire pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  
  //// Pins

  // // Logic

  assign valid_o = pmp_access_type_en ? pmp_access_type_reg : dma_ctrl_en ? dma_ctrl_reg : pmp_addr_en ? pmp_addr_reg : pmp_cfg_en ? pmp_cfg_reg : done_d;
  
  assign dma_ctrl_new = dma_ctrl_en ? dma_ctrl_reg : dma_ctrl_reg; 
  assign pmp_cfg_new = pmp_cfg_en ? pmp_cfg_reg : pmp_cfg_reg; 
  assign p
========================================================
example6_i-a_t-0.9.v
  RL_reg_t<riscv::ACCESS_WRITE> pmp_access_type_en;  
  
  reg dma_load_en, load_en; 
  reg[DATA_WIDTH-1:0] load_value; 

  //// States

  reg [DMA_CTRL_WIDTH-1:0] ctrl_state_reg; 
  SR_reg_t<DMA_CTRL_WIDTH> ctrl_state; // start, sb, st, ib, id, id2 

  reg [DMA_VALID_WIDTH-1:0] valid_reg; 
  SR_reg_t<DMA_VALID_WIDTH> valid; // ready, valid, and done  

  reg [DATA_WIDTH-1:0] pmp
========================================================
example7_i-a_t-0.9.v
  reg pmp_access_type_en;
  reg [3:0] pmp_access_type_phase_reg, pmp_access_type_phase_new; // can be overwritten by phase_i
  reg [3:0] escaped_pmp_access_type_phase_reg, escaped_pmp_access_type_phase_new; 
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_size_reg, pmp_access_size_new;

  reg valid_o_reg, valid_o_new;
  // register valid_o_new;
  // reg [63:0] valid_o_reg, valid_o_new;

  //// Function
  reg [DATA_WIDTH-1:0]  offset
========================================================
example8_i-a_t-0.9.v
  reg [11:0] pmp_access_type_en_reg, pmp_access_type_en_new; 
  
  
  always@(*) begin
    #(.WIDTH(DATA_WIDTH)) start_d = start_i; 
    #(.WIDTH(DATA_WIDTH)) length_d = length_i; 
    #(.WIDTH(DATA_WIDTH)) source_addr_lsb_d = source_addr_lsb_i; 
    #(.WIDTH(DATA_WIDTH)) source_addr_msb_d = source_addr_msb_i; 
    #(.WIDTH(DATA_WIDTH)) dest_addr_lsb_d = dest_addr_lsb_i; 
    #(.WIDTH
end

========================================================
example9_i-a_t-0.9.v
  riscv::pmp_access_t pmp_access_type_en; 

  reg [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_new_present; 
  reg pmpcfg_en; 

  reg [16-1:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_new_present; 
  reg pmpaddr_en; 

  reg dma_mem_trigger;
  
  
  localparam DMA_ADDR_0 = 32'hC0000;  
  localparam DMA_ADDR_3 = 32'hFC000;  
  localparam DMA_ADDR_1 = 32'hC1000;  
  localparam DMA_ADDR_2 = 32'hC2000; 
========================================================
example10_i-a_t-0.9.v
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg    pmp_cfg_en;  
//  reg [15:0] pmp_base_reg, pmp_base_new;
//  reg    pmp_base_en;  
//  reg [15:0] pmp_size_reg, pmp_size_new;
//  reg    pmp_size_en;  
//  reg [5:0] pmp_len_reg, pmp_len_new;
//  reg    pmp_len_en;  

// BUG:
//  always @(posedge clk_i)
//  always @(negedge rst_ni) 
//  begin
//    if (!rst_ni) begin
//      pmpcfg_reg <=
========================================================
example11_i-a_t-0.9.v
  reg [16-1] pmp_controllable_reg, pmp_controllable_new;
  reg pmp_control_en; 

  reg done_reg; 
  reg done_en; 

  reg valid_reg, valid_new; 
  reg [16-1] valid_bitmap; 
  
  reg [DMA_CTRL_WIDTH-1:0] ctrl; 
  reg [DMA_CTRL_WIDTH-1:0] new_ctrl; 
  reg [DMA_CTRL_WIDTH-1:0] sent_ctrl; 

  reg clk_count; 

  //// Logic 

  always @(posedge clk_i) begin
    if (rst_ni) begin
      valid_reg <= 0; 
      ctrl
end

end

========================================================
example12_i-a_t-0.9.v
  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_en; 


  //// Combinational Logic
  assign valid_o = dma_ctrl_reg [VALID_IDLE] ? 'b0 : dma_ctrl_reg [VALID_LOAD] ? 'b10  : dma_ctrl_reg [VALID_STORE] ? 'b100  : dma_ctrl_reg [VALID_DONE] ? 'b1000  : 'b0;

  reg CtrlState ctrl_state_reg, ctrl_state_new;
  ctrl_state_reg <= ctrl_state_new;
  ctrl_state_new <= CTRL_IDLE; // default state 
  always @(posedge clk_i or posedge rst_ni) begin
    if (r
end

========================================================
example13_i-a_t-0.9.v
  reg pmp_access_type_en = 1;

  reg valid_d; 



  //// Local wires
  wire sel_new;
  wire len_done_en; 
  wire done_en_new;
 
  wire [DMA_CTRL_WIDTH-1:0] sel_dma_ctrl; 
  wire [63:0]              sel_pmp_addr;
  wire sel_pmp_access_type;     

  reg [DMA_CTRL_WIDTH-1:0] sel_dma_ctrl_reg; 
  reg [63:0]              sel_pmp_addr_reg;
  reg sel_pmp_access_type_reg; 

  /////////////////////////////////////////////////////////////////////
  //// Logic 
  /////////////////////////////////////////////////////////////////////

 
========================================================
example14_i-a_t-0.9.v
  reg is_write_reg, is_write_new_reg;

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new_reg; // LSU input
  reg [DATA_WIDTH-1:0] start_reg; // DMA input
  reg [63:0] start_msb_reg, start_msb_new_reg; 
  reg [DATA_WIDTH-1:0] length_reg, length_new_reg; 
  reg [63:0] target_addr_lsb_reg, target_addr_lsb_new_reg; // LSU input  
  reg [63:0] target_addr_msb_reg, target_addr_msb_new_reg; // LSU input
  reg [63:0] source_addr
========================================================
example15_i-a_t-0.9.v
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [DMA_CTRL_WIDTH-1:0] ctrl_state; 

  //// Memories

  

  //// PSeudo-States
  PS_IDLE: begin 
      dma_ctrl_reg = DMA_CTRL_IDLE;
      pmp_addr_reg = 0;
      pmp_access_type_reg = pmpcfg_i[USER_ACCESS_TYPE_BITS]; 
      pmp_cfg_reg = pmpcfg_i[USER_ACCESS_PMP_BITS]; 
      ctrl_state <= CTRL_IDLE; 
      pmp_access_type_en <= 0;
      pmp_cfg_
end

========================================================
example16_i-a_t-0.9.v
  reg carry_pmp_access_type; 
  
  wire CONTROL_MODE_SEL  = 'd0; 
  wire CTRL_IDLE_SEL = 'd1; 
  wire CTRL_CHECK_LOAD_SEL = 'd2; 
  wire CTRL_START_LOAD_SEL = 'd3;
  wire CTRL_LOAD_SEL = 'd4; 
  wire CTRL_CHECK_STORE_SEL = 'd5;
  wire CTRL_START_STORE_SEL = 'd6;
  wire CTRL_STORE_SEL = 'd7;
  wire CTRL_DONE_SEL = 'd8;

  wire INPUT_DATA_SEL= 'b0; 
  wire PADDR_SEL = 'b1; 
  wire CTRL_READY_
========================================================
example17_i-a_t-0.9.v
  reg riscv::pmp_access_t pmp_access_type_en; 
  
  reg valid_reg, valid_new;
  reg [DATA_WIDTH-1:0] valid_data; 

  //////// Memory 
  memory_d_new [DMA_RANGE-1:0][BYTE_DEPTH-1:0]= (riscv::byte_t)[DATA_WIDTH-1:0];
  memory_d_new [ADDR_MSB-1:ADDR_LSB] = {"start_d[0] ? ('b0) : ('b1);"}; // must be 1-bit 
  mem [DMA_RANGE-1:0][BYTE_DEPTH-1:0]= (riscv::byte_t) valid_data; 

  //////
========================================================
example18_i-a_t-0.9.v

  reg valid_d; 
  
  reg [DATA_WIDTH-1:0] d_a; 

  assign pmp_access_reg = 0x0;
  assign pmp_access_type_reg = 0x0;

  assign d_a = source_addr_lsb_d; 
  assign valid_d = 0; 
  
  always @(posedge clk_i) begin 
    if (rst_ni) begin 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_addr_reg <= 0; 
      pmp_addr_new <= 0; 
      dma_ctrl_new <= CTRL_IDLE; 
      valid_d <= 0; 
      source
end

end

========================================================
example19_i-a_t-0.9.v
  always_comb begin: we_flag
    pmp_access_type_en = we_flag; 
  
end

========================================================
example0_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_
========================================================
example1_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 

  reg [63:0] pmp_access_result_data_valid_reg
========================================================
example2_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_
========================================================
example3_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_tmp, pmp_cfg_new_tmp;
  reg pmp_cfg_en_tmp; 

  reg [63:0] pmp_cfg_reg_tmp2, pmp_cfg_new_tmp2;
  reg pmp_cfg_en_tmp2; 

  reg [63:0] pmp_cfg_reg_tmp3, pmp_cfg_new_tmp3;
  reg pmp_cfg_en_tmp3; 

  reg [63:0] pmp_cfg_reg_tmp4, pmp_cfg_new_tmp
========================================================
example4_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 

  reg [63:0] pmp_access_result_data_valid_reg
========================================================
example5_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
========================================================
example6_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 

  reg [63:0] pmp_access_result_addr_reg, p
========================================================
example7_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 

  reg [63:0] pmp_access_result_data_valid_reg
========================================================
example8_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
========================================================
example9_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_cfg_reg <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_ms
end

end

========================================================
example10_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 

  reg [63:0] pmp_access_result_data_lsb_
========================================================
example11_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <=
end

end

========================================================
example12_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [63:0] pmp_cfg_reg_lsb_lsb, pmp_cfg_reg_lsb_msb;
  reg [63:0] pmp_cfg_new_lsb_lsb, pmp_cfg_new_lsb_msb;

========================================================
example13_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en_reg; 
  reg [63:0] pmp_access_type_en_new; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en
========================================================
example14_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_en_lsb, pmp_cfg_en_msb; 

  reg [63:0] pmp_cfg_reg_lsb_lsb, pmp_cfg_reg_lsb_msb;
  reg [63:0] pmp_cfg_reg_msb_lsb, pmp_cfg_reg_msb_msb;

========================================================
example15_i-b_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example16_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
========================================================
example17_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_
========================================================
example18_i-b_t-0.1.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
========================================================
example19_i-b_t-0.1.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg pmp_cfg_reg_lsb_en, pmp_cfg_reg_msb_en; 

  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_new_lsb_en, pmp_cfg_new_msb_en; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_reg_lsb_en
========================================================
example0_i-b_t-0.3.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  reg [16-1:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  //// Logic
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmpcfg_reg <= 0; 
      pmpaddr_reg <= 0; 
      start_
end

end

========================================================
example1_i-b_t-0.3.v
  reg [2-1:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= 0; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= 0; 
      p
end

end

========================================================
example2_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE;
end

end

========================================================
example3_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] source_addr_reg, source_addr_new;
  reg source_addr_en;  

  reg [63:0] dest_addr_reg, dest_addr_new;
  reg dest_addr_en;  

  reg [63:0] length_reg, length_new;
  reg length_en;  

  reg [63:0] source_addr_lsb_reg, source_addr_lsb_new;
  reg source_addr_lsb_en;  

  reg [63:0] source_addr_msb_reg, source_addr_msb_new;
  reg source_addr_msb_en;  

  reg [63:0] dest_addr_lsb_reg, dest_addr_lsb_new
========================================================
example4_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] valid_reg; 
  reg [DATA_WIDTH-1:0] valid_new; 
  reg valid_en; 

  reg [DATA_WIDTH-1:0] done_reg; 
  reg [DATA_WIDTH-1:0] done_new; 
  reg done_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr
========================================================
example5_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
========================================================
example6_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg,
========================================================
example7_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  reg [63:0] pmp_cfg_reg_new; 

  reg [63:0] pmp_cfg_reg_new_2; 

  reg [63:0] pmp_cfg_reg_new_3; 

  reg [63:0] pmp_cfg_reg_new_4; 

  reg [63:0] pmp_cfg_reg_new_5; 

  reg [63:0] pmp_cfg_reg_new_6; 

  reg [63:0] pmp_cfg_reg_new_7; 

  reg [63:0] pmp_cfg_reg_new
========================================================
example8_i-b_t-0.3.v
  reg [1:0] pmp_access_type_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_cfg_reg <= 0;
      pmp_addr_reg <=
end

end

========================================================
example9_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// DMA State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [63:0] pmp_addr_state; 
  reg [63:0] pmp_cfg_state; 
  reg [63:0] pmp_access_type_state; 

  //// DMA State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_next; 
  reg [63:0] pmp_addr_state_next; 
  reg [63:0] pmp_cfg_state_next
========================================================
example10_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
========================================================
example11_i-b_t-0.3.v
  reg pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [16-1:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [16-1:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [16-1:0] pmpaddr_lsb_reg, pmpaddr_lsb_new; 
  reg pmpaddr_lsb_en; 

  reg [16-1:0] pmpaddr_msb_reg, pmpaddr_msb_new; 
  reg pmpaddr_msb_en; 

  reg [16-1:0] pmpcfg_lsb_reg, pmpcfg
========================================================
example12_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [63:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_lsb_reg, pmpaddr_lsb_new; 
  reg pmpaddr_lsb_en; 

  reg [63:0] pmpaddr_msb_reg, pmpaddr_msb_new; 
  reg pmpaddr_msb_en; 

  reg [63:0] pmpaddr_lsb_d_reg, pmpaddr_lsb_d_new; 
  reg pmpaddr_lsb
========================================================
example13_i-b_t-0.3.v
  reg pmp_access_type_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  
  reg [63:0] pmp
========================================================
example14_i-b_t-0.3.v
  reg [3:0] pmp_access_type_en; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [63:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_lsb_reg, pmpaddr_lsb_new; 
  reg pmpaddr_lsb_en; 

  reg [63:0] pmpaddr_msb_reg, pmpaddr_msb_new; 
  reg pmpaddr_msb_en; 

  reg [63:0] pmpaddr_msb_reg, pmpaddr_msb_new; 
  reg pmpaddr_msb_en; 
========================================================
example15_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp
end

end

========================================================
example16_i-b_t-0.3.v
  reg [31:0] pmp_access_type_en; 
  
  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 
  
  reg [63:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 
  
  reg [63:0] pmpcfg_reg_tmp, pmpcfg_new_tmp;
  reg pmpcfg_en_tmp; 
  
  reg [63:0] pmpaddr_reg_tmp, pmpaddr_new_tmp;
  reg pmpaddr_en_tmp; 

  reg [63:0] p
========================================================
example17_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
========================================================
example18_i-b_t-0.3.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_ext, pmp_cfg_new_ext;
  reg pmp_cfg_en_ext; 

  reg [63:0] pmp_cfg_reg_ext_2, pmp_cfg_new_ext_2;
  reg pmp_cfg_en_ext_2; 

  reg [63:0] pmp_cfg_reg_ext_3, pmp_cfg_new_ext_3;
  reg pmp_cfg_en_ext_3; 

  reg [63:0] pmp_cfg_reg_ext_4, pmp_cfg_new
========================================================
example19_i-b_t-0.3.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  reg [DATA_WIDTH-1:0] cur_addr_lsb_reg, cur_addr_lsb_new;
  reg [DATA_WIDTH-1:0] cur_addr_msb_reg, cur_addr_msb_new;
  reg [DATA_WIDTH-1:0] cur_length_reg, cur_length_new;
  reg [DATA_WIDTH-1:0] cur_length_remaining_reg, cur_length_remaining_new;
  reg [DATA_WIDTH-1:0] cur_length_remaining_reg
========================================================
example0_i-b_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  reg [63:0] pmp_access_type_en_reg, pmp_access_type_en_new; 

  reg [63:0] pmp_access_type_en_reg, pmp_access_type_en_new; 


  //// Functions
  reg [DATA_WIDTH-1:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  
  riscv::pmp_access_t pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ 
  reg pmp_access_type_en; 
  reg [63:0] pmp_access
========================================================
example1_i-b_t-0.5.v
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmp_addr_reg <= 0; 
    
end

end

========================================================
example2_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b1; 
  reg pmpcfg_reg, pmpcfg_new; // pmpcfg_new is a copy of pmpcfg_reg at the beginning of the next clock cycle
  reg pmpcfg_en; 

  //// Variables
  reg [DMA_CTRL_WIDTH-1:0] state; 
  reg [DATA_WIDTH-1:0] addr_lsb_d, addr_msb_d; 
  reg [DATA_WIDTH-1:0] addr_lsb_i, addr_msb_i; 
  reg [DATA_WIDTH-1:0] data_i, data_d; 
  reg [DATA_WIDTH-1:0] data_cnt; 
  reg [DATA_
========================================================
example3_i-b_t-0.5.v
  reg [3:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  

  reg [63:0] pmp_cfg_reg_1, pmp_cfg_new_1;
  reg pmp_cfg_en_1;  

  reg [63:0] pmp_cfg_reg_2, pmp_cfg_new_2;
  reg pmp_cfg_en_2;  

  reg [63:0] pmp_cfg_reg_3, pmp_cfg_new_3;
  reg pmp_cfg_en_3;  

  reg [63:0] pmp_cfg_reg_4, pmp_cfg_new_4;
  reg pmp_
========================================================
example4_i-b_t-0.5.v
  reg [3:0] pmp_access_type_en; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;

  //// Logic

  assign valid_o = 0;

  always @(posedge clk_i or posedge rst_ni) begin
    if (!rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_ms
end

end

========================================================
example5_i-b_t-0.5.v
  reg pmp_access_type_en; 
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;  

  //// State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DATA_WIDTH-1:0] dma_length_reg; 

  reg [DATA_WIDTH-1:0] dma_source_addr_lsb_reg, dma_source_addr_lsb_new; 
  reg [DATA_WIDTH-1:0] dma_source_addr_msb_reg, dma_source_addr_msb_new; 
  reg [DATA_WIDTH-1:0] dma
========================================================
example6_i-b_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;  

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en;  
  
  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en;  
  
  reg [63:0] pmp_access_error_reg, pmp_access_error_new;
  reg pmp_access_error_en;  
  
  reg [63:0] pmp_access_status_reg, p
========================================================
example7_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en = 1'b1; 
  
  //// Logic
  dma_ctrl_reg = CTRL_IDLE; 
  dma_ctrl_new = CTRL_IDLE; 
  pmp_addr_reg = 0; 
  pmp_addr_new = 0;
  pmp_cfg_reg = 0; 
  pmp_cfg_new = 0;
  pmp_access_type_reg = riscv::ACCESS_WRITE; 
  pmp_access
========================================================
example8_i-b_t-0.5.v
//  pmp_access_type_en = 0; 

  //// Local Signals
  reg [DATA_WIDTH-1:0] length_left_reg; 
  reg [DATA_WIDTH-1:0] source_addr_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_reg; 
  reg [DATA_WIDTH-1:0] source_addr_reg_inc; 
  reg [DATA_WIDTH-1:0] dest_addr_reg_inc; 
  reg [DATA_WIDTH-1:0] source_addr_reg_inc_u; 
  reg [DATA_WIDTH-1:0] dest_addr_reg_inc_u; 
  reg [DATA_WIDTH-1:0] source_addr_reg
========================================================
example9_i-b_t-0.5.v
  reg pmp_access_type_en; 

  reg pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  reg [DATA_WIDTH-1:0] current_start_addr_lsb, current_start_addr_msb; 
  reg [DATA_WIDTH-1:0] current_dest_addr_lsb, current_dest_addr_msb; 
  reg [DATA_WIDTH-1:0] current_length; 
  reg [DATA_WIDTH-1:0] current_source_addr_lsb, current_source_addr_msb; 
  reg [DATA_WIDTH-1:0] current_dest_addr_lsb, current_dest_addr_msb; 

  reg [DATA_WIDTH-1:
========================================================
example10_i-b_t-0.5.v
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_new, pmp_cfg_reg_old; 
  reg [63:0] pmp_cfg_reg_new_old_en; 
  reg [63:0] pmp_cfg_reg_old_new_en; 

  //// State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [63:0] pmp_addr_state; 
 
========================================================
example11_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b1; 

  reg [DATA_WIDTH-1:0]  counter_reg, counter_new; 
  reg counter_en; 

  //// DMA State Machine
  reg [DMA_CTRL_WIDTH-1:0] state_reg, state_new; 
  reg state_en; 
  
  //// DMA Control Logic

  reg [63:0] current_pmp_addr;
  reg [63:0] current_pmp_addr_lsb;
  reg [63:0] current_pmp_addr_msb;
  reg [63:0] current_pmp_addr_msb_mask;
  reg [63:0] current_pmp_addr_lsb_mask;

  reg [63:
========================================================
example12_i-b_t-0.5.v
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmpcfg_reg <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
    
end

end

========================================================
example13_i-b_t-0.5.v
//  riscv::pmp_access_t pmp_access_type_en = riscv::ACCESS_READ;
//  reg pmp_access_type_en = riscv::ACCESS_READ;
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_
end

end

========================================================
example14_i-b_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;
  
  reg [DATA_WIDTH-1:0] p
========================================================
example15_i-b_t-0.5.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_cfg_reg, pmp_access_cfg_new;
  reg pmp_access_cfg_en; 


  //// State Machines
  reg [DATA_WIDTH-1:0] dma_state_reg; 
  reg [DATA_WIDTH-1:0] dma_state_new; 
  reg [DATA_WIDTH-1:0] dma_state_en; 


  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_state_
end

end

========================================================
example16_i-b_t-0.5.v
  reg pmp_access_type_en, pmp_access_type_en_new; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg, dma_ctrl_new; 
  reg dma_ctrl_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg, dma_ctrl_new; 
  reg dma_ctrl_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  //// Local Variables
  reg [DMA_CTRL_WIDTH-1
========================================================
example17_i-b_t-0.5.v
  reg [15:0] pmp_access_type_en_reg;

  reg [4:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_reg_next, pmpaddr_reg_next_next;
  reg [63:0] pmpaddr_reg_prev, pmpaddr_reg_prev_prev;

  reg [63:0] pmpaddr_reg_prev_prev_prev;
  reg [63:0] pmpaddr_reg_next_next_next;

  reg [63:0] pmpaddr_reg_prev_prev_prev_prev;
  reg [63:
========================================================
example18_i-b_t-0.5.v
  reg [3:0] pmp_access_type_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
    
end

end

========================================================
example19_i-b_t-0.5.v
  reg pmp_access_type_en = 1'b1;
  
  reg [63:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  
  
  //// Logic
  always @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 1'b1) begin
      dma_ctrl_reg <= DMA_CTRL_IDLE;
      pmp_addr_reg <= 0;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//      pmp_access_type_reg <= riscv::ACCESS_WRITE;
// FIX:
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmpcfg_reg <= 0;
    
end

end

========================================================
example0_i-b_t-0.7.v
  reg [53 : 0] pmp_access_type_en; 
  
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
    
  reg [15:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 
  
  //// Local Variables
  reg [DATA_WIDTH-1:0] addr_offset; 
  reg [DATA_WIDTH-1:0] addr_offset_next; 
  reg [DATA_WIDTH-1:0] length_next; 
  reg [DATA_WIDTH-1:0] start_next; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_next; 
  reg [DATA
========================================================
example1_i-b_t-0.7.v
  reg pmp_access_type_en = 1; 

  reg [31:0] irq_count_reg, irq_count_new;
  reg irq_count_en;  

  reg [63:0] irq_addr_reg, irq_addr_new;
  reg irq_addr_en;  
  
  reg [63:0] irq_data_reg, irq_data_new;
  reg irq_data_en;  

  reg [1:0] irq_en_reg, irq_en_new;
  reg irq_en_en;  

  reg [1:0] irq_cause_reg, irq_cause_new;
  reg irq_cause_en;  

  reg [63:0] irq_mode_reg, irq_
========================================================
example2_i-b_t-0.7.v
  reg [4:0] pmp_access_type_en_reg; 

  reg [1:0] dma_state_reg; 
  reg [7:0] dma_state_ctrl_reg; 


  //// Wire Outputs
  wire [DATA_WIDTH-1:0] start_o; 
  wire [DATA_WIDTH-1:0] length_o; 
  wire [DATA_WIDTH-1:0] source_addr_lsb_o; 
  wire [DATA_WIDTH-1:0] source_addr_msb_o; 
  wire [DATA_WIDTH-1:0] dest_addr_lsb_o; 
  wire [DATA_WIDTH-1:0] dest_addr_msb_o; 
  wire [
========================================================
example3_i-b_t-0.7.v
  reg pmp_access_type_en; 

  //// FSM
  always @(posedge clk_i) begin
    if(rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_en <= 0;
      pmp_access_type_reg <= riscv::ACCESS_UNKNOWN;
      pmp_access_type_en <= 0;
    
end

end

========================================================
example4_i-b_t-0.7.v
  reg pmp_access_type_en; 

  //// DMA_CTRL
  always @ (posedge clk_i or negedge rst_ni) begin
    if (reset_i) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= 0; 
    
end

end

========================================================
example5_i-b_t-0.7.v
  reg pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en;
  
  //// State Machines

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_cfg_reg <= 0;
      pmp_addr_reg <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <=
end

end

========================================================
example6_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 
  
  reg [3:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [1:0] pmp_mux_en;
  reg [1:0] pmp_mux_reg;
  reg [1:0] pmp_mux_new;

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d
end

end

========================================================
example7_i-b_t-0.7.v
  always @(posedge clk_i) begin
    if (reset_ni) begin
      pmp_access_type_reg <= riscv::ACCESS_NONE;
    
end

end

========================================================
example8_i-b_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  //// Pipe Registers
  reg [63:0] start_pipe_reg, start_pipe_new; 
  reg start_pipe_en; 
  reg [63:0] length_pipe_reg, length_pipe_new; 
  reg length_pipe_en;  
  reg [63:0] source_addr_lsb_pipe_reg, source_addr_lsb_pipe_new; 
  reg source_addr_lsb_pipe_en; 
  reg [63:0] source_addr_msb_pipe_reg, source_addr_msb_pipe_new; 
  reg source_addr_msb_pipe_en; 
  reg [63:0] dest_addr_lsb_pipe_reg, dest_
========================================================
example9_i-b_t-0.7.v
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;

      pmp_access_type_reg <=  riscv::ACCESS_WRITE;
    
end

end

========================================================
example10_i-b_t-0.7.v
  reg [2:0] pmp_access_type_en; 
  
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] source_addr_lsb_reg, source_addr_lsb_new; 
  reg source_addr_lsb_valid; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg, source_addr_msb_new; 
  reg source_addr_msb_valid; 

  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg, dest_addr_lsb_new; 
  reg dest_addr_lsb_valid; 
  reg [DATA_WID
========================================================
example11_i-b_t-0.7.v
  reg pmp_access_type_en  = 1'b0; // do not mask on reset 

  reg pmp_id_reg, pmp_id_new;
  reg pmp_id_en;

  //// DMA Logic

  always @(posedge clk_i) begin
    if (rst_ni) begin 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_new <= CTRL_IDLE; 
      pmp_access_type_new <= riscv::ACCESS_N
end

end

========================================================
example12_i-b_t-0.7.v
  assign   pmp_access_type_en = 0; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;     // riscv::PMP_NAPOT and riscv::PMP_NAPOT_MASK   
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// FIX:
  assign   pmp_cfg_en = 0; 

  //// Logic
  assign valid_o = valid_d; 
  assign done_d = done_i; 
  assign start_d = start_i; 
  assign length_d = length_i; 
  assign source_addr_lsb_d = source_addr_lsb_i; 
  assign source_addr_msb_d = source
========================================================
example13_i-b_t-0.7.v
  reg pmp_access_type_en = 1; // This is the default value for pmp_access_type_en reg.

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_reg;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_new;
  
  reg [63:0] pmp_addr_state; 
  reg [63:0] pmp_addr_state_reg; 
  reg [63:0] pmp_addr_state_new; 

  reg [CTRL_WIDTH-1:0] ctrl_reg, ctrl_new; 
  reg [CTRL_WID
========================================================
example14_i-b_t-0.7.v
  // BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
  reg pmp_access_type_en = 0; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  //// Functions

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
end

end

========================================================
example15_i-b_t-0.7.v
  reg [63:0] pmp_access_type_reg_dummy;
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

always @(posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_new <= CTRL_IDLE;
      dma_ctrl_en <= 0;
      pmp_cfg_reg <= 0;
      pmp_cfg_new <= 0;
      pmp_cfg_en <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
      pmp_addr_en <= 0
end

end

========================================================
example16_i-b_t-0.7.v
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en; 

  //// Logic
  dma_ctrl_new = VALID_IDLE; 
  pmp_addr_new = 0; 
  pmp_access_type_new = riscv::ACCESS_WRITE;
  pmp_access_type_en = 0; 
  dma_ctrl_en = 0; 
  pmp_addr_en = 0; 
  
  dma_ctrl_reg = CTRL_IDLE; 
  valid_o = 0; 

========================================================
example17_i-b_t-0.7.v
pmp_access_type_en = 1'b1;

  //// Local Signals
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg; 
  wire dma_ctrl_next; 

  reg [63:0] pmp_addr_reg; 
  wire [63:0] pmp_addr_next; 
  reg pmp_access_type_reg; 
  wire pmp_access_type_next; 
  
  //// Registers To IOs
  assign valid_o = {VALID_DONE, VALID_STORE, VALID_LOAD, VALID_IDLE}[dma_ctrl_reg]; 

  //// Local Signals
  assign dma_ctrl_reg = dma_ctrl_new; 
  assign dma_ctrl
========================================================
example18_i-b_t-0.7.v
  reg [14:0] pmp_access_type_en; 

  reg [3:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  reg [3:0] pmp_cfg_en_reg, pmp_cfg_en_new;

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  
  //// Functionality

  //// Reset
  always @(negedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_new <= CTRL_IDLE; 
      pmp_access_type_en_reg <= PMP_ACCESS_TYPE_REG
end

end

========================================================
example19_i-b_t-0.7.v
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  

  reg [DATA_WIDTH-1:0] current_addr, next_addr; 
  reg [DATA_WIDTH-1:0] current_data, next_data; 
  reg [DATA_WIDTH-1:0] current_ctrl, next_ctrl; 


  //// Combination Logic
  reg [63:0] combined_addr; 
  reg [63:0] combined_next_addr; 
  assign combined_addr = source_addr_lsb_d | (source_addr_msb_d << DATA_WIDTH); 
  assign combined_next_addr = dest_addr_lsb_d | (dest_addr_msb_d << DATA_WID
========================================================
example0_i-b_t-0.9.v
  reg [2-1:0] pmp_access_type_en; 

  reg [1:0] pmp_addr_mode_reg, pmp_addr_mode_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_addr_mode_en; 
// FIX:
  reg [2-1:0] pmp_addr_mode_en; 

  //// Submodules
  // Add the sequence diagram:
  riscv::dma_ctrl dma_ctrl_seq;


  begin

  //// Logic
  assign pmp_access_type_new = pmp_access_type_reg & pmp_access_type_en;
  assign pmp_access_type_reg = pmp_access_type_new;
  assign dma_ctrl_
end

========================================================
example1_i-b_t-0.9.v
  riscv::pmp_access_t pmp_access_type_en;

  reg [12:0][56:0] mpmp_reg;  
  reg mpmp_en;  
  
  //// State Machine Declaration
  always @(posedge clk_i) begin
    #5          dma_ctrl_en <= 0;
    #5          pmp_addr_en <= 0;
    #5          pmp_access_type_en <= 0;
    #5          mpmp_en <= 0;
    
    always @(posedge rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0;
end

end

========================================================
example2_i-b_t-0.9.v
  reg pmp_access_type_en;  

  reg [16-1:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  //// Ctrl
  reg switching_to_check_target, switching_to_start_target;
  reg switching_to_check_length, switching_to_start_length;
  reg switching_to_check_source, switching_to_start_source;
  wire switching_to_check_target_new, switching_to_start_target_new;
  wire switching_to_check_length_new, switching_to_start_length_new;
  wire switching_to_check_source_new, switching_to_start_source_new;


  reg [2:0] direction_ctrl_reg, direction_ctrl_new; 
  reg
========================================================
example3_i-b_t-0.9.v
//  init pmp_access_type_reg =  2'd0; // Not set to riscv::ACCESS_WRITE because of 
//  init pmp_access_type_reg =  2'd0; // this bug.  Needs fix.
  pmp_access_type_reg =  2'd0; //Not set to riscv::ACCESS_WRITE because of
  pmp_access_type_reg =  2'd0; //this bug.  Needs fix.
  pmp_access_type_new = 2'd0; //Not set to riscv::ACCESS_WRITE because of
  pmp_access_type_new = 2'd0; //this bug.  Needs fix.

  //// DMA States
  reg [DATA_WIDTH-1:0] dma_state_reg, dma_state
========================================================
example4_i-b_t-0.9.v
pmp_access_type_new = 0; pmp_access_type_en = 0;  

  reg [15:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en;    

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  always @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni==1'b0) begin
      dma_ctrl_reg <= 1'b0; 
      dma_ctrl_new <= 1'b0;
      pmp_addr_reg <= 64'b0; 
      pmp_addr_new <= 64'b0;
      pmp_access_type_reg <= 3'b0;
      pmp_
end

end

========================================================
example5_i-b_t-0.9.v
  reg [3:0] pmp_access_type_en_tmp;
//  reg [3:0] pmp_access_type_en_tmp;
  initial pmp_access_type_en_tmp = 0;
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_en; 
  reg [63:0] pmp_access_len_reg, pmp_access_len_new;
  reg pmp_access_en; 

  // module pmp_access
  always @( posedge clk_i or posedge rst_ni  )
    begin
      
      // RAZ/WI on reset
      if( reset )
        pmpcfg_i <= 0;

      // //
      if(!reset) begin

end

end

========================================================
example6_i-b_t-0.9.v
  reg pmp_access_type_en; 
  reg signed [pmp_access_type_t:5:0] pmp_access_type_sign; 

// Flatten Enabling Inputs for Registers Holding Security Settings.
//  assign pmp_access_type_sign = or2(or2(or2(or2(or2(or2(or2(high4(dest_addr_lsb_i), high4(source_addr_lsb_i)), high4(dest_addr_msb_i)), high4(source_addr_msb_i)), high4(length_i)), high4(start_i)), high4(we_signal_i)), high4(pmpcfg_i)); 
  assign pmp_access_type_sign = or2(or2(or2(high4(pmpcfg
========================================================
example7_i-b_t-0.9.v
  reg signed [7:0]pmp_access_type_en; 


  //// Outputs

  wire [1:0] ctrl_reg; 
  wire [7:0] pmp_access_type_reg_out; 
  wire rst_n; 

  wire [DATA_WIDTH-1:0] data_i, data_d; 

  //// Constants

  wire [63:0] vstart_max = 6; 

  //// Front-
========================================================
example8_i-b_t-0.9.v
pmp_access_type_en : STD_LOGIC_VECTOR (3 downto 0);
pmp_access_type_en := 'b000; 

  reg [12-1:0] pmpnum_reg, pmpnum_new; // Range over [-1:3]
  reg [3-1:0] pmp_en_reg, pmp_en_new;
  reg [32-1:0] mem_base_reg, mem_base_new;
  reg [63:0] mem_mask_reg, mem_mask_new;

  reg [63:0] last_wr_addr;

  reg [DATA_WIDTH-1:0] length_left_d;
  reg [DATA_WIDTH-1:0] source_addr_d, source_addr_first;
  reg [DATA
========================================================
example9_i-b_t-0.9.v
  regp [1] pmp_access_type_en;
  always @(posedge clk_i) begin 
    pmp_access_type_en[0] <= pmp_access_type_new[0]; 
    pmp_access_type_en[1] <= 0;
  
end

========================================================
example10_i-b_t-0.9.v
  reg [127:0] pmp_access_type_en; // PMP Access Type Enabled Registers 

  reg clk_reg_old, clk_reg_new; 


  //// Change Logs
  reg [63:0] pmp_addr_chg_log;

  reg [127:0] pmp_access_type_chg_log;
// BUG: Uninitialized Value on Ports of External Processors.
// BUG: Had to make pmp_access_type_chg_log global.
// BUG: Changed from register to allow for reset which is set to 0.
//    reg [127:1] pmp_access_type_chg_log;
    reg pmpcfg_chg_log;
  reg dma_ctrl_chg_log;


  ////////////
  // MODULE
========================================================
example11_i-b_t-0.9.v
reg [6:0] pmp_access_type_en; 
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  reg [45:0] write_addr_reg, write_addr_new;
  reg write_addr_en; 
  reg [1:0] write_op_reg, write_op_new;
  reg write_op_en; 

  always @(posedge clk_i) begin

    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_ms
end

end

========================================================
example12_i-b_t-0.9.v
  reg [1:0] pmp_access_type_en_reg; // Acces Type Enable Register 
  reg pmp_access_type_en_new, pmp_access_type_en_busy; // Busy Flag

  reg [63:0] pmp_upidx_reg, pmp_upidx_new; 
  riscv::pmp_upmerge_t pmp_upmerge_type_reg, pmp_upmerge_type_new; 
  reg pmp_upmerge_en_busy; // Busy Flag
 
  reg [63:0] pmp_downidx_reg, pmp_downidx_new; 
  riscv::pmp_downmerge_t pmp_downmerge_type_reg, pmp_downmerge_type_
========================================================
example13_i-b_t-0.9.v
  reg [63:0] pmp_access_type_reg_init;

  riscv::dma_mem_attrib_t dma_mem_attrib_reg ; 
  riscv::dma_mem_attrib_t dma_mem_attrib_new; 

always @ (posedge clk_i) begin
  dma_ctrl_new =    x"2'b0",
          pmp_access_type_new = riscv::ACCESS_READ, // BUG: Untouched Value on Reset
    pmp_addr_new = 64'h0,
           done_d = 0 
    when  (rst_ni); 
  dma_ctrl_en = 0; 
  pmp_addr_en = 0;  
  pmp_access_type_reg = pmp
end

========================================================
example14_i-b_t-0.9.v
  assign pmp_access_type_en = dma_ctrl_en & (1'b1); 

  reg [DATA_WIDTH-1:0] count_reg, count_new, count_step;
  
  reg [63:0] target_addr_reg, target_addr_new;
  reg target_addr_en; 
 
  reg [16:0] pmpcfg_o, pmpcfg_new; // Data to be Written to PMP Control Register
  reg pmpcfg_en;  

  riscv::access_t access_type_reg, access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg access_type_en;

  ////////////////
  reg [15:0] dma_count_down; // used for testing
========================================================
example15_i-b_t-0.9.v
  reg pmp_access_type_en = 1'b1;

  //// Signals 
  wire [63:0] pmp_status_reg;
  wire [63:0] pmp_status_new;
  wire [63:0] pmp_control_reg;

  //// state
  reg [DMA_STATUS_WIDTH-1:0] state;   
  wire P2M_IDLE;
  assign start_i_d = start_i;
  assign length_i_d = length_i;
  assign source_addr_lsb_i_d = source_addr_lsb_i; 
  assign source_addr_msb_i_d = source_addr_msb_i; 
  assign dest_addr_lsb_i_d = dest_addr_lsb_
========================================================
example16_i-b_t-0.9.v
  reg pmp_access_type_en = 1 /* LOGIC1_INIT_BOX*/; 

  //// Logic
  assign dma_ctrl_reg = dma_ctrl_new;

  assign pmp_addr_reg = pmp_addr_new;

  always @(posedge clk_i or posedge rst_ni) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0 /* LOGIC1_INIT_BOX*/;
    
end

end

========================================================
example17_i-b_t-0.9.v
  always_ff @(posedge clk_i or posedge rst_ni) begin
    if (rst_ni) begin
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_new <= riscv::ACCESS_WRITE;
    
end

end

========================================================
example18_i-b_t-0.9.v
pmp_access_type_reg = riscv::ACCESS_WRITE; 

  reg [17:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

       
  // IOWR Detection  
  reg pmp_iowr_flag;
  reg pmp_iowr_int_flag; 
  wire pmp_iowr_consumed_flag; 
  always @( posedge clk_i or posedge rst_ni ) begin
    if ( rst_ni ) begin
      pmp_iowr_flag <= 1'b0; 
      pmp_cfg_new = 0; 
      pmp_cfg_en = 0; 
      pmp_access_type_reg = riscv::ACCESS_WRITE; 
end

end

========================================================
example19_i-b_t-0.9.v
// Initialized Value Holds Appropriate Register Values.
reg logic [7:0] pmpcfg_i; 
  reg pmpcfg_en;

  always @(posedge clk_i) begin
    if(rst_ni) begin 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 1; 
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0x0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmpcfg_reg <= pmp
end

end

========================================================
example0_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example1_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg pmp_cfg_reg_en; 

  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_new_en; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_reg_en; 

  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_ms
========================================================
example2_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Local Variables
  reg [DATA_WIDTH-1:0] current_addr_lsb; 
  reg [DATA_WIDTH-1:0] current_addr_msb; 
  reg [DATA_WIDTH-1:0] current_length; 
  reg [DATA_WIDTH-1:0] current_source_addr_lsb; 
  reg [DATA_WIDTH-1:0] current_source_addr_msb; 
  reg [DATA_WIDTH-1:0] current_dest_addr_lsb; 
  reg [DATA_W
========================================================
example3_i-c_t-0.1.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  assign pmp_access_type_new = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_new <= riscv::ACCESS_WRITE;
      pmp_access_type_en <= 0;
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
     
end

end

========================================================
example4_i-c_t-0.1.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  assign pmp_access_type_new = riscv::ACCESS_WRITE;
  assign pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  assign valid_o = 0; 
  assign done_d = done_i; 

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_cfg_reg <= 0; 
      pmp_access_type_reg <= riscv::ACC
end

end

========================================================
example5_i-c_t-0.1.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr
end

end

========================================================
example6_i-c_t-0.1.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; 
  assign pmp_access_type_new = riscv::ACCESS_WRITE; 
  reg pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_new <= CTRL_IDLE; 
      dma_ctrl_en <= 0; 
      pmp_addr_reg <= 0; 
      pmp_addr_new <= 0; 
      pmp_addr_en <= 0; 
     
end

end

========================================================
example7_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_en <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_en <= 0;
      pmp_cfg_reg <= 0;
      pmp_cfg_en <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_en <= 0;
    
end

end

========================================================
example8_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_
end

end

========================================================
example9_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
end

end

========================================================
example10_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg [63:0] pmp_cfg_reg_lsb_new, pmp_cfg_reg_msb_new;
  reg pmp_cfg_reg_lsb_en, pmp_cfg_reg_msb_en; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg [63:0] pmp_addr_reg_lsb_new, pmp_addr_reg_msb_new;

========================================================
example11_i-c_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 

  reg [63
========================================================
example12_i-c_t-0.1.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  assign pmp_access_type_new = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_
========================================================
example13_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_lsb, pmp_cfg_reg_msb;
  reg pmp_cfg_reg_en; 

  reg [63:0] pmp_cfg_new_lsb, pmp_cfg_new_msb;
  reg pmp_cfg_new_en; 

  reg [63:0] pmp_addr_reg_lsb, pmp_addr_reg_msb;
  reg pmp_addr_reg_en; 

  reg [63:0] pmp_addr_new_lsb, pmp_addr_new_ms
========================================================
example14_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_
end

end

========================================================
example15_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
end

end

========================================================
example16_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg, dma_ctrl_new; 
  reg dma_ctrl_en; 
  
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example17_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp
========================================================
example18_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_
end

end

========================================================
example19_i-c_t-0.1.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_cfg_reg <= 0;
end

end

========================================================
example0_i-c_t-0.3.v
  reg pmp_access_type_en = 1'b1; 
  
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  
  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_
end

end

========================================================
example1_i-c_t-0.3.v
  reg pmp_access_type_en = 1; 
  reg pmp_access_type_en_new; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  reg [DATA_WIDTH-1:0] data_out_reg, data_out_new; 
  reg data_out_en; 

  reg [DATA_WIDTH-1:0] data_in_reg, data_in_new; 
  reg data_in_en; 

  reg [DATA_WIDTH-1:0] data_in_valid_reg, data_in_valid_new; 
  reg data_in_valid_en; 

  reg [DATA_WIDTH-1:0] data_in_ready_reg,
========================================================
example2_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  assign pmp_access_type_en = 0; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;

  //// DMA State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next_state;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_prev_state;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_reg;

  //// PMP State Machine
  reg [63:0] p
========================================================
example3_i-c_t-0.3.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_status_reg, pmp_access_status_new;
  reg pmp_access_status_en; 

  reg [63:0] pmp_access_type_reg, pmp_access_type_new;
  reg pmp_access_type_en; 

  reg [63
========================================================
example4_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_READ; 
  assign pmp_access_type_new = riscv::ACCESS_READ; 
//  assign pmp_access_type_en = 1'b1; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  assign valid_o = dma_ctrl_reg[VALID_IDLE]; 
  assign dma_ctrl_new = dma_ctrl_reg; 
  assign pmp_cfg_new = pmp_cfg_reg; 
  assign pmp_addr_new = pmp_addr_reg; 
  assign pmp_access_type_new = pmp_access_type_reg; 
========================================================
example5_i-c_t-0.3.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  //// Logic
  dma_ctrl_reg = 0; 
  pmp_addr_reg = 0; 
  pmp_access_type_reg = 0; 
  pmp_access_addr_reg = 0; 
  dma_ctrl_en = 0; 
  pmp_addr_en = 0; 
  pmp_access_type_en = 0; 
  pmp_access_addr_en = 0; 

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= 0; 
      pmp_addr_reg <= 0; 
      pmp_
end

end

========================================================
example6_i-c_t-0.3.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i or posedge rst_ni) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0;
      pmp_access_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_addr_en <= 0;
      pmp_cfg_en <=
end

end

========================================================
example7_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_READ;
  assign pmp_access_type_new = riscv::ACCESS_READ;
//  reg pmp_access_type_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  assign pmp_access_type_en = 0; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  reg [DATA_WIDTH-1:0] i; 
  reg [DATA_WIDTH-1:0] j; 
  reg [DATA_WIDTH-1:0] k; 
  reg [DATA_WIDTH-1:0] l; 
  reg
========================================================
example8_i-c_t-0.3.v
  reg pmp_access_type_en = 1; 
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmpcfg_reg <= 0;
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done
end

end

========================================================
example9_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg, dma_ctrl_new; 
  reg dma_ctrl_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example10_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  reg [63:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_
end

end

========================================================
example11_i-c_t-0.3.v
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  reg [16-1:0] pmpaddr_reg, pmpaddr_new; 
  reg pmpaddr_en; 
  reg we_flag_reg, we_flag_new; 
  reg we_flag_en; 
  reg [DATA_WIDTH-1:0] valid_d; 
  reg [DATA_WIDTH-1:0] valid_d_new; 
  reg valid_en; 
  reg [DATA_WIDTH-1:0] valid_o_reg, valid_o_new; 
  reg valid_o_en; 
  reg [DATA_WIDTH-1:0] valid_o_reg_reg, valid_o
========================================================
example12_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
//  assign pmp_access_type_reg = riscv::ACCESS_READ;
  assign pmp_access_type_new = pmp_access_type_reg;
  assign pmp_access_type_en = 1'b1;

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_cfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
end

end

========================================================
example13_i-c_t-0.3.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
      dma_ctrl_reg <= 0;
      pmp_addr_reg <= 0;
      pmp_cfg_reg <= 0;
      pmp_access_type_reg <= r
end

end

========================================================
example14_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; 
  assign pmp_access_type_new = riscv::ACCESS_WRITE; 
//  assign pmp_access_type_en = 1'b1; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  
  //// Logic
  assign valid_o = 0; 
  assign done_d = 0; 
  assign dma_ctrl_new = 0; 
  assign pmp_cfg_new = 0; 
  assign pmp_addr_new = 0; 
  assign pmp_access_type_new = 0; 
  assign pmp_cfg_en = 0; 
  assign pmp
========================================================
example15_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example16_i-c_t-0.3.v
  reg pmp_access_type_en = 1'b1; 

  reg [DATA_WIDTH-1:0] valid_d;
  reg [63:0] valid_addr; 
  reg [63:0] valid_data; 
  reg [63:0] valid_data_new; 
  reg [63:0] valid_data_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 

end

end

========================================================
example17_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_READ; 
  assign pmp_access_type_en = 1'b1; 

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Local Signals
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_temp; 
  reg [63:0] pmp_addr_reg_temp; 
  reg [7:0] pmpcfg_reg_temp; 
  reg [16-1:0] pmpaddr_reg_temp; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg_temp; 
  reg [DATA_WIDTH-1:0]
========================================================
example18_i-c_t-0.3.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  assign pmp_access_type_new = riscv::ACCESS_WRITE;
  reg pmp_access_type_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_
========================================================
example19_i-c_t-0.3.v
  reg pmp_access_type_en = 1'b1; 
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 
  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_new <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_
end

end

========================================================
example0_i-c_t-0.5.v
  pmp_access_type_reg = riscv::ACCESS_WRITE;
  pmp_access_type_new = riscv::ACCESS_WRITE;

  reg [2:0] pmp_access_len_reg, pmp_access_len_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_len_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  pmp_access_len_reg = riscv::LENGTH_WORD;
  pmp_access_len_new = riscv::LENGTH_WORD;

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
// BUG: Uninitialized Value on Reset for Registers
========================================================
example1_i-c_t-0.5.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE;
  assign pmp_access_type_en = 1'b1;

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_1, pmp_cfg_new_1;
  reg pmp_cfg_en_1; 

  reg [63:0] pmp_cfg_reg_2, pmp_cfg_new_2;
  reg pmp_cfg_en_2; 

  reg [63:0] pmp_cfg_reg_3, pmp_cfg_new_3;
  reg pmp_cfg_en_3; 

  reg [63:0] pmp_
========================================================
example2_i-c_t-0.5.v
  reg [63:0] pmp_access_type_en_temp;
  assign pmp_access_type_en = pmp_access_type_en_temp;
// END BUG

  //// State Machines
  reg [DMA_CTRL_WIDTH-1:0] ctrl_state; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_new; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_en; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_done; 

  reg [63:0] pmp_addr_state, pmp_addr_new; 
  reg pmp_addr_en; 

  reg [DATA_WIDTH-1:0] valid_state
========================================================
example3_i-c_t-0.5.v
  reg pmp_access_type_en = 1'b1; 


  ////  Control State Machine

  reg [DMA_CTRL_WIDTH-1:0] ctrl_state_reg, ctrl_state_new; 
  reg ctrl_state_en; 

  ////  Control State Machine Outputs

  assign valid_o = dma_ctrl_reg[VALID_IDLE]; 

  assign dma_ctrl_reg = dma_ctrl_new; 
  assign ctrl_state_reg = ctrl_state_new; 
  assign pmp_addr_reg = pmp_addr_new; 
  assign pmp_access_type_reg = pmp_access_type_new; 

  ////  Control State Machine Assertions

  always @(posedge clk_i
========================================================
example4_i-c_t-0.5.v
  initial begin
    pmp_access_type_reg = pmp_access_type_new;
  
end

========================================================
example5_i-c_t-0.5.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; 
  assign pmp_access_type_new = riscv::ACCESS_WRITE; 

  reg [1:0] pmp_access_type_en; 

  reg [DATA_WIDTH-1:0] pmp_addr_lsb_reg, pmp_addr_lsb_new;
  reg pmp_addr_lsb_en; 

  reg [DATA_WIDTH-1:0] pmp_addr_msb_reg, pmp_addr_msb_new;
  reg pmp_addr_msb_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_ID
end

end

========================================================
example6_i-c_t-0.5.v
  reg pmp_access_type_en = 1; 

  //// Registers for data
  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  //// Registers for control
  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg, ctrl_new; 
  reg ctrl_en; 

  //// Registers for valid
  reg [VALID_WIDTH-1:0] valid_reg, valid_new; 
  reg valid_en; 

  //// PIOs

  //// Outputs
  output wire [DATA_WIDTH-1:0] data_o; 
  output wire [DMA_CTRL_WIDTH-1:0] ctrl_o; 
 
========================================================
example7_i-c_t-0.5.v
  pmp_access_type_reg = riscv::ACCESS_WRITE; 
  pmp_access_type_new = riscv::ACCESS_WRITE; 

  reg [4:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// DMA State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 
  reg [63:0] pmp_addr_next; 
  reg [4:0] pmpcfg_next; 
  reg [DATA_WIDTH-1:0] start_next; 
  reg [DATA_WIDTH-1:0] length_next; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_next
========================================================
example8_i-c_t-0.5.v
  reg pmp_access_type_en = 1'b1; 

  reg [63:0] start_addr_reg, start_addr_new;
  reg start_addr_en;
  reg [63:0] 
========================================================
example9_i-c_t-0.5.v
  reg pmp_access_type_en = 1'b1; 
  reg pmp_access_type_en_new; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// DMA State Machine

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state;

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_state <= CTRL_IDLE; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; // riscv::ACCESS_WRITE or riscv::ACCESS
end

end

========================================================
example10_i-c_t-0.5.v
  assign pmp_access_type_reg = pmpcfg_i[16-1:0]; 
// END BUG
 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_valid; 
  reg [63:0] pmp_addr_reg_valid; 
  reg pmp_access_type_reg_valid; 
  reg pmp_access_type_reg_done; 
  reg pmp_access_type_reg_abort; 
  
  //// Logic
  
  always @ (posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0
end

end

========================================================
example11_i-c_t-0.5.v
  initial begin 
    pmp_access_type_reg = riscv::ACCESS_READ; 
  
end

========================================================
example12_i-c_t-0.5.v
  reg [7:0] pmpcfg_reg, pmpcfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmpcfg_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg [63:0] pmpaddr_reg, pmpaddr_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmpaddr_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:

  reg [DMA_CTRL_WIDTH-1:0] reg_dma_ctrl; 
  reg [63:0] reg_pmp_addr; 
  reg [7:0] reg_pmpcfg; 
  reg [63:0
========================================================
example13_i-c_t-0.5.v
  pmp_access_type_reg = riscv::ACCESS_READ;
  pmp_access_type_new = riscv::ACCESS_READ;
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next_state; 
  reg [DATA_WIDTH-1:0] dma_ctrl_count;
  reg [DATA_WIDTH-1:0] dma_ctrl_count_max; 
  reg [DATA_WIDTH-1:0] dma_ctrl_count
========================================================
example14_i-c_t-0.5.v
  reg [2:0] pmp_access_type_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Constants
  reg [DATA_WIDTH-1:0] length_max; 
  reg [DATA_WIDTH-1:0] source_addr_max; 
  reg [DATA_WIDTH-1:0] dest_addr_max; 

  //// Local Signals
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_tmp;
  reg [63:0] pmp_addr_reg_tmp;
  reg [63:0] pmp_cfg_reg_tmp;
  reg [2:0] pmp_access_type
========================================================
example15_i-c_t-0.5.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;
  reg [63:0] pmp_cfg_addr;

  reg [63:0] pmp_cfg_addr_reg, pmp_cfg_addr_new;
  reg pmp_cfg_addr_en;

  reg [63:0] pmp_cfg_data_reg, pmp_cfg_data_new;
  reg pmp_cfg_data_en;


  //// Logic
 
  //// Control 
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
     
end

end

========================================================
example16_i-c_t-0.5.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en; 

  reg [63:0] pmp_access_enable_reg, pmp_access_enable_new;
  reg pmp_access_enable_en; 

  reg [63:0] pmp_access_disable_reg, pmp_access_disable_new;
  reg pmp_access_disable_en; 

  reg [63
========================================================
example17_i-c_t-0.5.v
  reg [63:0] pmp_access_type_en; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
  reg [7:0] pmp_cfg_mask, pmp_cfg_mask_new;
  reg [7:0] pmp_cfg_value, pmp_cfg_value_new;

  reg [7:0] pmp_cfg_mask_write_reg, pmp_cfg_mask_write_new;
  reg pmp_cfg_mask_write_en; 

  reg [7:0] pmp_cfg_value_write_
========================================================
example18_i-c_t-0.5.v
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  //// Internal Variables
  reg [63:0] pmp_addr_mask_reg; 
  reg [63:0] pmp_addr_mask_new; 
  reg [63:0] pmp_access_addr_mask_reg; 
  reg [63:0] pmp_access_addr_mask_new; 
  reg [63:0] pmp_access_mask_reg; 
  reg [63:0] pmp_access_mask_new; 

  reg [DATA_WIDTH-1:0] src_addr_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_reg; 
========================================================
example19_i-c_t-0.5.v
  reg [63:0] pmp_access_reg = {0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
========================================================
example0_i-c_t-0.7.v
  reg pmp_access_type_en = 1'b1; 

  //// Logic
  always @(posedge clk_i) begin
    if(rst_ni ^ 1'b1) begin start_d  <= 'd0; 
                          length_d <= 'd0; 
                          source_addr_lsb_d  <= 'h0; 
                          source_addr_msb_d  <= 'h0; 
                          dest_addr_lsb_d    <= 'h0; 
                          dest_addr_msb_d    <= 'h0; 
                          done_d            <= 'd0; 
                          dma_ctrl_reg      <= 'd0; 
                          pmp_addr_reg      <= 'd0;
                          pmp_access_type_reg
end

end

========================================================
example1_i-c_t-0.7.v
  assign pmp_access_type_reg = pmp_access_type_new;
  reg pmp_access_type_en; 

  reg [5:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_lsb_reg, pmp_addr_lsb_new;
  reg pmp_addr_lsb_en;  

  reg [63:0] pmp_addr_msb_reg, pmp_addr_msb_new;
  reg pmp_addr_msb_en;  

  always @(posedge clk_i) begin
    if (rst_ni == 1) begin
      pmp_addr_reg <= "h0; 
      pmp_addr_lsb_
end

end

========================================================
example2_i-c_t-0.7.v
  pmp_access_type_reg = riscv::ACCESS_WRITE;
  pmp_access_type_new = riscv::ACCESS_WRITE;

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 
  reg pmpcfg_update; 
  reg [63:0] pmpaddr_reg, pmpaddr_new;


  //// Local Variables
  reg [DATA_WIDTH-1:0] done_tmp; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_tmp; 
  reg [DATA_WIDTH-1:0] source_addr_msb_tmp; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_tmp
========================================================
example3_i-c_t-0.7.v
  assign pmp_access_type_en = 1'b1;
  reg pmp_access_type_en; 
  //// 
  reg [31:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;  
  
  //// State Machines
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_prev; 
  reg [7:0] [16-1:0] pmp_cfg_reg, pmp_cfg_new; 
  reg [16-1:0][53:0] pmp_addr_
========================================================
example4_i-c_t-0.7.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;
 
  //// Control
  reg CTRL_STATES; 
  reg [7:0] CTRL_STATES_NEXT; 
  reg [DMA_CTRL_WIDTH-1:0] CTRL_STATES_NEXT_DMA_CTRL; 
  reg pmp_access_type_en; 
  reg pmp_cfg_en; 

  submodule ctrl = {
  		input clk_i, rst_ni; 
    		input start_i; 
    		input length_i; 
    		input source_addr_lsb
========================================================
example5_i-c_t-0.7.v
//  pmp_access_type_reg = riscv::ACCESS_WRITE;
//  pmp_access_type_new = riscv::ACCESS_WRITE;

  reg [32:0] pmp_cfg_d; 
  reg pmp_cfg_en; 
  
  assign pmp_cfg_d = pmpcfg_i; 

  reg [31:0] pmp_addr_d; 
  reg pmp_addr_en; 
  
  assign pmp_addr_d = pmpaddr_i; 

  //// DMA states
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next_state; 
  reg
========================================================
example6_i-c_t-0.7.v
  reg [15:0] pmp_access_type_en; 

  reg [DMA_CTRL_WIDTH-1:0]  valid_d; 

  //// Internal Variables

  reg [DATA_WIDTH-1:0] source_addr_d; 
  reg [DATA_WIDTH-1:0] dest_addr_d; 
  reg [DMA_CTRL_WIDTH-1:0]  dma_ctrl_en_old; 
  reg [63:0] pmp_addr_en_old; 
  reg pmp_access_type_en_old; 
  reg pmp_access_type_new_old; 

  integer dma_ctrl_state; 
  integer pmp_addr_state; 
  integer pmp_access_type_
========================================================
example7_i-c_t-0.7.v
  reg [1:0] pmp_access_type_en_init;
  always @(posedge clk_i)
    begin
      if (rst_ni)
        pmp_access_type_en_init <= 'h0;
      else
        pmp_access_type_en_init <= pmp_access_type_en;
    
end

========================================================
example8_i-c_t-0.7.v
  assign pmp_access_type_reg =  riscv::ACCESS_READ; 
  assign pmp_access_type_new =  riscv::ACCESS_READ; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_access_type_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  assign pmp_access_type_en =  1'b1; 

  reg [3:0] pmp_size_reg, pmp_size_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_size_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  assign pmp_size_reg =  3
========================================================
example9_i-c_t-0.7.v
  reg pmp_access_type_en_reset = 1; 
  reg pmp_access_type_en; 
  
  reg [31:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_l, pmp_cfg_reg_h;
  reg [63:0] pmp_cfg_new_l, pmp_cfg_new_h;
  reg pmp_cfg_en_l, pmp_cfg_en_h; 

  reg [63:0] pmp_addr_reg_l, pmp_addr_reg_h;
  reg [63:0] pmp_addr_new_l, pmp_addr_new_h;
  reg pmp_addr_en
========================================================
example10_i-c_t-0.7.v
  reg pmp_access_type_en = 1'b1; 

  reg pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  

  reg pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;  

  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg;

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [DMA_CTRL_WIDTH-1:0] ctrl_new;
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  reg [DMA_CTRL_WIDTH-1:0] ctrl_new = CTRL_IDLE; 
  reg [DMA_CTRL_WIDTH-1:0]
========================================================
example11_i-c_t-0.7.v
  assign pmp_access_type_reg = pmpcfg_i[3];
  reg [3:0] pmp_access_type_en; 
  
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_reg;
  reg [63:0] pmp_addr_state_reg;
  reg pmp_reg_en;

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state_next, dma_ctrl_state_next_reg;
  reg [63:0] pmp_addr_state_next, pmp_addr_state_next_reg;
  reg pmp_reg_en_next;

  //// Next State Logic
  always @ (posedge clk_i || negedge rst_ni) begin
end

========================================================
example12_i-c_t-0.7.v
  assign pmp_access_type_reg = riscv::ACCESS_READ;

// END BUG
  reg [RISCV_PMP_NO-1:0] pmp_no_reg, pmp_no_new;
  reg pmp_no_en; 

  
  //// Constants
  reg [DATA_WIDTH-1:0] ctrl_dma_idle; 
  reg [DATA_WIDTH-1:0] ctrl_dma_check_load;
  reg [DATA_WIDTH-1:0] ctrl_dma_start_load;
  reg [DATA_WIDTH-1:0] ctrl_dma_load;
  reg [DATA_WIDTH-1:0] ctrl_dma_check_store;
  reg [DATA
========================================================
example13_i-c_t-0.7.v
  reg pmp_access_type_en = 0; 


  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example14_i-c_t-0.7.v
  assign pmp_access_type_reg = {2{1'b0}}; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  assign pmp_access_type_en = {2{1'b0}}; 

  //// States
  reg [3:0] state; 
  reg [63:0] pmp_addr; 

  //// Outputs
  output wire dma_ctrl_o;
  output wire [DATA_WIDTH-1:0] source_addr_o; 
  output wire [DATA_WIDTH-1:0] dest_addr_o; 
  output wire [DMA_CTRL_WIDTH-1:0] pmp_access_type_o; 
  output wire [63:0] pmp_addr_o; 

========================================================
example15_i-c_t-0.7.v
//  pmp_access_type_en = 1'b0; 
  pmp_access_type_en = 0; 

  //// Assertions

  always @ (posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 0) begin
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
    
end

end

========================================================
example16_i-c_t-0.7.v
  reg [7:0] pmpcfg_reg = 'h0000000, pmpcfg_i;
  reg pmpcfg_en; 

  //// DMA Control Logic
  always @(posedge clk_i) begin
    if (rst_ni) 
      dma_ctrl_reg <= CTRL_IDLE; 
    else 
      dma_ctrl_reg <= dma_ctrl_new; 
  
end

========================================================
example17_i-c_t-0.7.v
//  pmp_access_type_reg <= riscv::ACCESS_WRITE;
//  pmp_access_type_new <= riscv::ACCESS_WRITE;
//  pmp_access_type_en <= 1'b1;

  reg [3:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  //// States
  reg CTRL_IDLE_STATE; 
  reg CTRL_CHECK_LOAD_STATE; 
  reg CTRL_START_LOAD_STATE; 
  reg CTRL_LOAD_STATE; 
  reg CTRL_CHECK_STORE_STATE; 
  reg CTRL_START_STORE_STATE; 
  reg CTRL_STORE_STATE; 
  reg CTRL_DONE_STATE; 
  reg CTRL_ABORT
========================================================
example18_i-c_t-0.7.v
//  pmp_access_type_reg = riscv::ACCESS_WRITE;
//  pmp_access_type_new = riscv::ACCESS_WRITE;
  
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en;

  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Variables
  reg [DATA_WIDTH-1:0] data_in_tmp; 
  reg [DATA_WIDTH-1:0] data_out_tmp; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_tmp; 
  reg [63:0] pmp_addr_tmp; 
  reg
========================================================
example19_i-c_t-0.7.v
//  initial pmp_access_type_reg = (riscv::pmp_access_t) pmpcfg_i[16]; 
//  initial pmp_access_type_new = pmp_access_type_reg; 

  
  //// DMA State Machine
  reg CTRL_STATE, VALID_STATE;
  localparam [DATA_WIDTH-1:0] DATA_WIDTH_1 = 'h01; 
  localparam [DATA_WIDTH-1:0] DATA_WIDTH_2 = 'h02; 
  localparam [DATA_WIDTH-1:0] DATA_WIDTH_4 = 'h04; 
  localparam [DATA_WIDTH-1:0] DATA_WIDTH_8 = 'h08; 
  localparam [DATA_WID
========================================================
example0_i-c_t-0.9.v
  assign  pmp_access_type_en = (pmp_access_type_new == |riscv::ACCESS_WRITE|) | (pmp_access_type_new == |riscv::ACCESS_READ|);

  reg [DMA_CTRL_WIDTH-1:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en;

  //// Local Variables

  reg [DATA_WIDTH-1:0] source_addr_lsb; 
  reg [DATA_WIDTH-1:0] source_addr_msb; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb; 
  reg [DATA_WIDTH-1:0] dest_addr_msb; 
  reg [DATA
========================================================
example1_i-c_t-0.9.v
  begin always @(posedge rst) 1FF'b11111111111111111111;
  
end

========================================================
example2_i-c_t-0.9.v
  initial begin 
    pmp_access_type_new = riscv::ACCESS_NONE;
  
end

========================================================
example3_i-c_t-0.9.v
 if(reset) begin
    pmp_access_type_reg = riscv::ACCESS_WRITE;
 
end

========================================================
example4_i-c_t-0.9.v
  always @(posedge CTRL_CLK) begin
    pmp_access_type_reg <= pmp_access_type_new;  
    pmp_access_type_en <= 1;
    pmp_addr_reg <= pmp_addr_new;
    pmp_addr_en <= 1;
  
end

========================================================
example5_i-c_t-0.9.v
//  pmp_access_type_reg = riscv::ACCESS_NONE;

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Signals
  //// States
  wire [15:0] dma_ctrl;
  wire [12:0] set_ctrl_reg; 
  reg dma_ctrl_reg; 
  wire [59:0] pmp_addr;
  wire pmp_access_type; 
  wire [63:0] pmp_cfg;
  wire [15:0] clear_ctrl_reg; 
  
  //// State Machine 
  always @(posedge clk_i) begin 
    if (rst_ni) begin 
      start_d <= 0;  
end

end

========================================================
example6_i-c_t-0.9.v
  const int pmp_access_type_val  = 0 ; 
  reg pmp_access_type_en : 1 ; 
  
  reg [8191:0] addr_offset_reg, addr_offset_new; 
  reg addr_offset_en; 
  reg [8191:0] addr_base_reg, addr_base_new; 
  reg addr_base_en; 
  reg [8191:0] addr_limit_reg, addr_limit_new; 
  reg addr_limit_en; 
  reg [8191:0] sec_reg, sec_new; 
  reg sec_en; 
  
  //// Instance
  dma_controller t (
      .clk_i(clk_i),
      .rst_ni(rst_ni),
     
========================================================
example7_i-c_t-0.9.v
  assign pmp_access_type_new = riscv::ACCESS_WRITE; 
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; 
 o
  riscv::pmp_access_t pmp_access_type_wr_name; // Standin for unused value 
  riscv::pmp_access_t pmp_access_type_rd_name; // Standin for unused value 

// BUG: The dummy "assign" statement that reads the access type destination 
// register is required to satisfy the constraint that no value may be 
// assigned to "pmp_access_dest" after reset.  
// FIX:
  assign dma_ctrl_reg = DMA_CTRL_IDLE; 
  always @(posedge clk_i or negedge rst
========================================================
example8_i-c_t-0.9.v
  assign pmp_access_type_reg = ~0;

  inst dram_access dma; 
  dram_access #(.DATA_WIDTH(DATA_WIDTH)) dma
    (
    .clk_i(clk_i),
    .dma_ctrl(dma_ctrl_new),
    .dma_ctrl_en(dma_ctrl_en),
    .start(start_d),
    .length(length_d),
    .source_addr_lsb(source_addr_lsb_d), 
    .source_addr_msb(source_addr_msb_d), 
    .dest_addr_lsb(dest_addr_lsb_d), 
    .dest_addr_msb(dest_addr_msb_d), 
    .dma_done
========================================================
example9_i-c_t-0.9.v
  assign pmp_access_type_en = 1'b1;  

  reg[3:0] pmp_cfg_reg, pmp_cfg_new; // pmpcfg_i
  reg pmp_cfg_en; 
  
  //// Combinational Logic

  assign valid_o = dma_ctrl_reg[VALID_SZ-1:VALID_LSB] | 
           pmp_addr_reg[63:0] | 
           pmp_access_type_reg;

  assign dma_ctrl_en = start_i | source_addr_lsb_i | source_addr_msb_i | length_i |
                        dest_addr_lsb_i | dest_addr_msb_i | done_i |
                        we_flag;
  
  assign pmp_cfg_en
========================================================
example10_i-c_t-0.9.v
  init  pmp_access_type_reg = riscv::ACCESS_WRITE;
  init  pmp_access_type_new = riscv::ACCESS_WRITE;
// ENDBUG
  reg pmp_access_type_en;

  //// FSM  
  reg [7:0] [16-1:0] pmpcfg_latched_o;

  always @(posedge clk_i or posedge rst_ni) begin
  
    // Reset
    if (rst_ni) begin
      for (int i=0;i<=DATA_WIDTH-1;i=i+1) begin
        valid_o[i] <= 'b0;
      
end

end

end

========================================================
example11_i-c_t-0.9.v
 reg [2:0]  pmp_access_type_en; 
 
  reg [512-1:0] pmpcfg_reg; //reset_value = reset_value:pmpcfg_i;
 //  reg [5:0] pmpcfg_reg; //reset_value = reset_value:pmpcfg_i;


  //// Control
  wire [DMA_CTRL_WIDTH-1:0] ctrl_sw;
  reg [DMA_CTRL_WIDTH-1:0] ctrl_d;

  reg done_write_error_reg;
  reg [DMA_CTRL_WIDTH-1:0] done_dma_write_error_reg;
  reg done_write_warning_reg;
  reg [DMA_CTRL_WIDTH-1:
========================================================
example12_i-c_t-0.9.v
// Initialise the security sensitive registers to No Access.
  
// BUG: Pmp Access Type Registers UNinitilised on Reset.
  reg pmpcfg_reg;  
  reg pmpcfg_en; 

  always @(posedge(clk_i)) begin
    if(rst_ni) begin
      pmpcfg_reg <= pmpcfg_i;
      pmpcfg_en <= 1;
  
      pmp_addr_reg <= pmpaddr_i;
      pmp_addr_en <= 1;
  
      dma_ctrl_reg <= 0;
      dma_ctrl_new <= 0;
      dma_ctrl_en <= 1;
      
      pmp_access_type_reg <= 0;
      pmp_access_type_new <= 0;
  // pmp_access_type
end

end

========================================================
example13_i-c_t-0.9.v
rsten_secure_init();
reg rsten_secure_reg;
assign pmp_access_type_en = rsten_secure_reg;
//End BUG.

  //// DMA State Machine
  reg [DMA_CTRL_WIDTH-1:1] dma_ctrl_state; 
  reg [DMA_CTRL_WIDTH-1:1] dma_ctrl_new_state; 
  reg [63:0] pmp_addr_state, pmp_addr_new_state;
  reg pmp_addr_en_state;

 
  always @(posedge clk_i or negedge rst_ni) begin 
    if(rst_ni) begin 
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
end

end

========================================================
example14_i-c_t-0.9.v
  assign pmp_access_type_en = 0;

  reg valid_reg; 
  reg ready_flag_reg; 
  reg valid_new; 
  reg ready_flag_new; 
  reg [63:0] temp_access_new;

 
  assign pmp_addr_new   = pmpaddr_i[0][0] ? pmpaddr_i[1][0] : pmpaddr_i[0][0]; 
  assign pmp_access_type_new = pmpcfg_i[0] ? riscv::ACCESS_READ : riscv::ACCESS_WRITE; 
  
  reg [1:0] ctrl_reg;
  reg [1:0] ctrl_new;
  reg [7:0] req_reg, req_new;
  reg req_
========================================================
example15_i-c_t-0.9.v
  //initial  
  pmp_access_type_reg = riscv::ACCESS_READ;
  pmp_access_type_new = pmp_access_type_reg;
  //initial 
  // BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
  const reg [63:0] default_pmpaddr = 512'b0;
  reg [54:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;
  
  //// Interconnects
  wire [DATA_WIDTH-1:0] dma_ctrl_temp, dma_data_temp, dma_stat0_temp, dma_stat1_temp;
  riscv::dma_t dma_tubes(clk_i, clk_i, rst_ni
========================================================
example16_i-c_t-0.9.v
// Always Load the security sensitive 1:40:22:1 region (0x4022_0000 - 0x4022_4FFF) for now.

// BUG: Reset-value for pmpaddr_reg is not 0 since it is an input param to pmpaddr_i.
//  reg [1:0] pmp_access_type_reg, pmp_access_type_new;  


  reg [1:0] security_sensitive_access_reg; 

  reg [1:0] valid_reg;
  reg [1:0] valid_mem_reg;

  //// Local Signals
  reg dma_ctrl_reg_en = 0; 
  reg [DATA_WIDTH-1:0] pmp_addr_reg_en = 0;  
  reg pmp_access_type_reg_en =
========================================================
example17_i-c_t-0.9.v
  wire pmp_access_type_en; 
  reg [10:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d  <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <=  0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 1; 

      dma_ctrl_en <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_en <= 0;
      pmp_addr_reg <= 0; 
end

end

========================================================
example18_i-c_t-0.9.v
  reg [1:0] pmp_access_type_en; 
  always @(posedge clk_i || negedge rst_ni) begin
    if (rst_ni || !pmp_access_type_en)
      pmp_access_type_reg <= riscv::ACCESS_READ;
  
end

========================================================
example19_i-c_t-0.9.v
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  assign pmp_access_type_new = riscv::ACCESS_WRITE; // riscv::ACCESS_WRITE or riscv::ACCESS_READ

// BUG: Uninitialized Value on Reset for Registers Holding Memory Page Attributes.
//  reg pmp_access_type_en; 
// Ensure that the security sensitive access register is assigned a value on reset.
// FIX:
  assign pmp_access_type_reg = riscv::ACCESS_WRITE; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  assign pmp_access_type_new = riscv::ACCESS_WRITE; // r
========================================================
example0_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmpcfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest
end

end

========================================================
example1_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example2_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example3_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmpcfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest
end

end

========================================================
example4_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example5_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmpcfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_
end

end

========================================================
example6_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example7_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg; 
  assign pmp_access_type_en = pmp_access_type_en_reg; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  assign valid_o = 0; 
  assign done_d = 0; 
  assign dma_ctrl_reg = 0; 
  assign pmp_addr_reg = 0; 
  assign pmp_cfg_reg = 0; 
  assign pmp_access_type_reg = 0; 

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= 0; 
      pmp_addr_reg <=
end

end

========================================================
example8_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en; 

  reg [63:0] pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en; 

 
========================================================
example9_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg [63:0] pmp_access_type_en_new; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en; 

  reg [63:0] pmp_access_result_data_reg, pmp_access_result_data_new;
  reg pmp_access_result_data_en; 
========================================================
example10_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg; 
  assign pmp_access_type_en = pmp_access_type_en_reg; 
  reg [63:0] pmp_access_type_en_new; 
  assign pmp_access_type_en_new = pmp_access_type_en_reg; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_
========================================================
example11_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmpcfg_reg <= 0; 
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest
end

end

========================================================
example12_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example13_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg; 
  assign pmp_access_type_en = pmp_access_type_en_reg; 
  reg [63:0] pmp_access_type_en_new; 
  assign pmp_access_type_en_new = pmp_access_type_en_reg; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en; 

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en; 

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_
========================================================
example14_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example15_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en = 0; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_new; 
  reg [63:0] pmp_cfg_reg_old; 

  reg [63:0] pmp_cfg_reg_new_old; 
  reg [63:0] pmp_cfg_reg_old_old; 

  reg [63:0] pmp_cfg_reg_new_old_old; 

  reg [63:0] pmp_cfg_reg_new_old_old_old; 

  reg [63:0] pmp_cfg_reg_new_old_old_old_old;
========================================================
example16_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg; 
  assign pmp_access_type_en = pmp_access_type_en_reg; 
  reg [63:0] pmp_access_type_en_new; 
  assign pmp_access_type_en_new = pmp_access_type_en_new; 
  reg [63:0] pmp_access_type_en_reg_next; 
  assign pmp_access_type_en_reg_next = pmp_access_type_en_new; 

  reg [63:0] pmp_access_type_reg_next; 
  assign pmp_access_type_reg_next = pmp_access_type_new; 

  reg [63:0] pmp_access_type_reg
========================================================
example17_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example18_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_lsb_reg, pmpaddr_lsb_new;
  reg pmpaddr_lsb_en; 

  reg [63:0] pmpaddr_msb_reg, pmpaddr_msb_new;
  reg pmpaddr_msb_en; 

  reg [63:0] pmpaddr_lsb_reg, pmpaddr
========================================================
example19_i-d_t-0.1.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example0_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example1_i-d_t-0.3.v
  reg [3:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Logic

  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= risc
end

end

========================================================
example2_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 

  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [63:0] pmp_cfg_en; 
  reg [
========================================================
example3_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en_reg; 
  assign pmp_access_type_en = pmp_access_type_en_reg; 
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0;
    
end

end

========================================================
example4_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  assign valid_o = dma_ctrl_reg[VALID_IDLE];
  always @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 1'b1) begin
      dma_ctrl_reg <= {DMA_CTRL_IDLE, 0};
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_cfg_reg <= 0;
    
end

end

========================================================
example5_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en = 0; 

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [DATA_WIDTH-1:0] dma_ctrl_addr_reg; 
  reg [DATA_WIDTH-1:0] dma_ctrl_addr_new; 
  reg [DATA_WIDTH-1:0] dma_ctrl_addr_en; 
  reg [DATA_WIDTH-1:0] dma_ctrl_data_reg; 
  reg [DATA_WIDTH-1:0] dma_ctrl_data_new; 
  reg [DATA_WIDTH-1:0] dma_ctrl_data_en; 
  reg [DATA_WIDTH-
========================================================
example6_i-d_t-0.3.v
//  assign pmp_access_type_en = ~rst_ni; 
//  assign pmp_access_type_reg = pmp_access_type_new; 
  assign pmp_access_type_reg = 0; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
    
end

end

========================================================
example7_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_access_type_reg <= risc
end

end

========================================================
example8_i-d_t-0.3.v
  reg pmp_access_type_en = 1'b0; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  reg [63:0] pmp_cfg_reg, pmp
========================================================
example9_i-d_t-0.3.v
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_reg <= 0;
      pmp_access_type_new <= 0;
      pmp_addr_reg <= 0;
      pmp_addr_new <= 0;
    
end

end

========================================================
example10_i-d_t-0.3.v
  assign pmp_access_type_en = !rst_ni; 
  assign pmp_access_type_new = pmp_access_type_reg; 
  assign pmp_access_type_reg = pmp_access_type_new; 
  
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  assign pmp_cfg_en = !rst_ni; 
  assign pmp_cfg_new = pmp_cfg_reg; 
  assign pmp_cfg_reg = pmp_cfg_new; 
  
 
========================================================
example11_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en = 1'b0; 

  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;  

  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en;  

  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en;  

  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en;  

  reg [63:0] pmp_access_status_reg, pmp_access
========================================================
example12_i-d_t-0.3.v
  assign pmp_access_type_en = rst_ni; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [63:0] pmp_cfg_reg_new;
  reg [63:0] pmp_cfg_reg_old;

  reg [63:0] pmp_addr_reg_new;
  reg [63:0] pmp_addr_reg_old;

  reg [63:0] pmp_addr_reg_new_old;

  reg [63:0] pmp_addr_reg_new_old_old;

  reg [63:0] pmp_addr_reg_new_old_old_old;

  reg [63:0] pmp_addr_reg_new_old
========================================================
example13_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_en_reg <= 0;
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_
end

end

========================================================
example14_i-d_t-0.3.v
  reg pmp_access_type_en = rst_ni;
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE; 
      dma_ctrl_new <= CTRL_IDLE; 
      pmp_addr_reg <= 0; 
      pmp_addr_new <= 0; 
      pmp_access_type_reg <= riscv::ACCESS_WRITE; 
      pmp_access_type_new <= riscv::ACCESS_WRITE; 
      pmpcfg_reg <= 0; 
      pmpcfg_new <= 0; 
    
end

end

========================================================
example15_i-d_t-0.3.v
  reg pmp_access_type_en = 0; 

  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en; 

  reg [63:0] pmpaddr_lsb_reg, pmpaddr_lsb_new;
  reg pmpaddr_lsb_en; 

  reg [63:0] pmpaddr_msb_reg, pmpaddr_msb_new;
  reg pmpaddr_msb_en; 

  reg [63:0] pmpaddr_lsb_reg_d, pmpaddr_lsb_new_d;
  reg pmpaddr_lsb_en_d; 

 
========================================================
example16_i-d_t-0.3.v
  reg [3:0] pmp_access_type_en_reg, pmp_access_type_en_new; 
  assign pmp_access_type_en = pmp_access_type_en_reg; 
  assign pmp_access_type_reg = pmp_access_type_new; 
  assign pmp_access_type_new = pmp_access_type_en_new; 
  reg [3:0] pmp_access_type_en_new; 

  reg [63:0] pmp_addr_en_reg, pmp_addr_en_new;
  assign pmp_addr_en = pmp_addr_en_reg; 
  assign pmp_addr_reg = pmp_addr_new; 
  assign pmp_addr_new = pmp_addr_
========================================================
example17_i-d_t-0.3.v
  reg pmp_access_type_en = rst_ni ? 0 : 1'b1; 
 
  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0; 
      length_d <= 0; 
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      dma_ctrl_reg <= 0; 
      pmp_addr_reg <= 0; 
      pmp_
end

end

========================================================
example18_i-d_t-0.3.v
  reg [3:0] pmp_access_type_en; 
  reg [63:0] pmp_access_addr_reg, pmp_access_addr_new;
  reg pmp_access_addr_en;  
  reg [63:0] pmp_access_data_reg, pmp_access_data_new;
  reg pmp_access_data_en;  
  reg [63:0] pmp_access_mask_reg, pmp_access_mask_new;
  reg pmp_access_mask_en;  
  reg [63:0] pmp_access_result_reg, pmp_access_result_new;
  reg pmp_access_result_en;  

  reg [63:0] pmp_access_addr_reg_lsb, pmp_access_addr
========================================================
example19_i-d_t-0.3.v
  reg [63:0] pmp_access_type_en; 
  assign pmp_access_type_en = (reset_ni ? 0 : pmp_access_type_new);

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg [63:0] pmp_cfg_en; 
  assign pmp_cfg_en = (reset_ni ? 0 : pmp_cfg_new);

  //// Logic
  assign valid_o = (dma_ctrl_reg[CTRL_IDLE] ? 0 : 
                   (dma_ctrl_reg[CTRL_LOAD] ? VAL
========================================================
example0_i-d_t-0.5.v
//  assign pmp_access_type_en = rst_ni;

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  

  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next; 
  reg [63:0] pmp_cfg_next;
  reg [63:0] pmp_addr_next;
  reg pmp_access_type_next;
  reg [63:0] pmp_addr_next_lsb, pmp_addr_next_msb;

  //// Outputs
  output reg [DATA_WIDTH-1:0] valid_o_reg;
  output reg [DATA_WIDTH-1:0] done_o_reg;

  //// Inst
========================================================
example1_i-d_t-0.5.v
  reg pmp_access_type_en; 
  reg [3:0] pmpcfg_reg, pmpcfg_new;  
  reg pmpcfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  //// State machine
  reg [DMA_CTRL_WIDTH-1:0] ctrl_state;
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  
  reg [3:0] pmpcfg_reg, pmpcfg_new;  
  reg pmpcfg_en; 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_
========================================================
example2_i-d_t-0.5.v
  reg [63:0] pmp_access_type_en_reg;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_en_reg <= 0; 
    
end

end

========================================================
example3_i-d_t-0.5.v
  always_ff @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_addr_reg <= 0;
    
end

end

========================================================
example4_i-d_t-0.5.v
reg pmp_access_type_en = 1'b0; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  
  
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  

  reg [63:0] pmp_addr_reg, p
========================================================
example5_i-d_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  reg pmp_access_type_en_new; 

  //// Submodules
  
  dma_ctrl_reg_t dma_ctrl_reg_inst;
  dma_ctrl_reg_inst.clk_i(clk_i);
  dma_ctrl_reg_inst.rst_ni(rst_ni);
  dma_ctrl_reg_inst.start_i(start_i);
  dma_ctrl_reg_inst.length_i(length_i);
  dma_ctrl_reg_inst.source_addr_lsb_i(source_addr_lsb_i);
  dma_ctrl_reg_inst.source_addr_msb_i(source_addr_msb_i);
 
========================================================
example6_i-d_t-0.5.v
  assign pmp_access_type_en = rst_ni ? 0 : 1; 
 
  reg [127:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Functions
  reg [DATA_WIDTH-1:0] length_reg; 
  reg [DATA_WIDTH-1:0] source_addr_lsb_reg; 
  reg [DATA_WIDTH-1:0] source_addr_msb_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_lsb_reg; 
  reg [DATA_WIDTH-1:0] dest_addr_msb_reg; 
  reg [DATA_WIDTH-1:0] start_reg; 
  

========================================================
example7_i-d_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  reg [63:0] dma_addr_reg, dma_addr_new;
  reg [63:0] dma_size_reg, dma_size_new;
  reg dma_size_en; 

  reg [63:0] dma_data_reg, dma_data_new;
  reg dma_data_en; 

  reg [63:0] dma_data_addr_reg, dma_data_addr_new;
  reg dma_data_addr_en; 

  reg [63:0] dma_data_size_reg, dma_data
========================================================
example8_i-d_t-0.5.v
  reg [1:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en;  

  //// Module Instances
  riscv::dm_ctrl_t dm_ctrl;
  riscv::dma_engine_t dma_engine;

  //// Module Interface Signals
  reg [DATA_WIDTH-1:0] dma_start_i; 
  reg [DATA_WIDTH-1:0] dma_length_i;
  reg [DATA_WIDTH-1:0] dma_source_addr_lsb_i;
  reg [DATA_WIDTH-1:0] dma_source_addr_msb_i;
  reg [DATA_
========================================================
example9_i-d_t-0.5.v
  reg pmp_access_type_en = 1'b0; 
  
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;
  
  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;
  
  reg [63:0] pmpcfg_addr_reg;
  reg [63:0] pmpaddr_addr_reg;
  
  reg [63:0] pmpcfg_data_reg;
  reg [63:0] pmpaddr_data_reg;
  
  reg [63:0] pmpcfg_addr_next_reg;
  reg [63:0] pmpaddr_addr_next_reg;
  
  reg [63:0] pmpcfg_
========================================================
example10_i-d_t-0.5.v
  assign pmp_access_type_en = !rst_ni; 
  
  //// DMA Control State Machine
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state;
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next_state; 
  assign dma_ctrl_reg = dma_ctrl_state; 
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_state <= CTRL_IDLE;
    
end

end

========================================================
example11_i-d_t-0.5.v
  reg [3:0] pmp_access_type_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  

  reg [63:0] pmp_addr_reg, pmp_addr_new
========================================================
example12_i-d_t-0.5.v
  reg [63:0] pmp_access_type_en; 
  reg [1:0] pmp_access_type_en_reg, pmp_access_type_en_new;


  //// FSM
  reg [DMA_CTRL_WIDTH-1:0] fsm_reg, fsm_new;
  reg fsm_en; 
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;
  reg [63:0] pmpaddr_reg, pmpaddr_new;
  reg pmpaddr_en;

  always @(posedge clk_i) begin
    if(rst_ni) begin
      fsm_reg <= CTRL_IDLE;
      dma_ctrl_reg <= 0;
      pmp
end

end

========================================================
example13_i-d_t-0.5.v
  reg pmp_access_type_en = 0; 
  reg pmp_access_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg data_en; 

  //// Functions
 
  always @(posedge clk_i) begin
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
      dma_ctrl_reg <= 0;
      pmp_addr_reg <= 0;
      pmp_access_type_reg <= 0;
     
end

end

========================================================
example14_i-d_t-0.5.v
  always @(posedge rst_ni)
  begin
    pmp_access_type_reg   <= riscv::ACCESS_WRITE;
    pmp_access_type_new   <= riscv::ACCESS_WRITE;
    pmp_addr_reg          <= 0;
    pmp_addr_new          <= 0;
  
end

========================================================
example15_i-d_t-0.5.v
  always @(posedge rst_ni) begin
    pmp_access_type_reg<=0;
  
end

========================================================
example16_i-d_t-0.5.v
assign pmp_access_type_en = (rst_ni == 1) ? 0 : 1; 
  reg [7:0] pmpcfg_reg, pmpcfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmpcfg_en; 
// Assign 0 to register when reset is low.
// FIX:
assign pmpcfg_en = (rst_ni == 1) ? 0 : 1; 

  reg [16-1:0][53:0] pmpaddr_reg, pmpaddr_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmpaddr_en; 
// Assign 0 to register when reset is low.
// FIX:
assign pmpaddr_en = (rst_ni == 1)
========================================================
example17_i-d_t-0.5.v
  assign pmp_access_type_en = rst_ni; 
  
  reg [63:0] dma_addr_reg, dma_addr_new;
  reg dma_addr_en; 

  reg [63:0] dma_length_reg, dma_length_new;
  reg dma_length_en; 

  reg [63:0] dma_source_addr_reg, dma_source_addr_new;
  reg dma_source_addr_en; 

  reg [63:0] dma_dest_addr_reg, dma_dest_addr_new;
  reg dma_dest_addr_en; 

  //// DMA Controller

  reg [DATA_WIDTH-1:0] dma_data_reg; 
  reg [DATA_W
========================================================
example18_i-d_t-0.5.v
//  reg pmp_access_type_en = 1'b0; 

  //// States
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state;
  reg [63:0] pmp_addr_state; 

  //// Transitions
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_state <= CTRL_IDLE;
      pmp_addr_state <= 0; 
      dma_ctrl_reg <= 0; 
      pmp_addr_reg <= 0; 
    
end

end

========================================================
example19_i-d_t-0.5.v
  reg pmp_access_type_en = 0; 

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  reg [DATA_WIDTH-1:0] addr_reg; 
  reg [DATA_WIDTH-1:0] addr_new; 
  reg [DATA_WIDTH-1:0] addr_en; 

  reg [DATA_WIDTH-1:0] data_reg, data_new; 
  reg [DATA_WIDTH-1:0] data_en; 

  reg [DATA_WIDTH-1:0] data_out_reg, data_out_new; 
  reg [DATA_WIDTH-1:0] data_out_en; 

  reg [DATA
========================================================
example0_i-d_t-0.7.v
  reg [31:0] pmp_access_type_en; 
  reg [7:0] pmp_cfg_reg, pmp_cfg_new;
  reg pmp_cfg_en; 

  //// DMA State Machine
  reg [3:0] dma_state_reg;     
  wire [3:0] dma_state_next; 
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_next;
  reg [16-1:0] pmp_addr_next;
  reg [15:0] pmp_cfg_next;
  reg [15:0] pmp_access_type_next; 

  //// DMA Valid
  wire [DATA_WIDTH-1:0] dma_valid_reg;
  wire [DATA_
========================================================
example1_i-d_t-0.7.v
  assign pmp_access_type_reg = pmp_access_type_new;
  assign pmp_access_type_en = !rst_ni; 

  //// DMA Controller
  dma_ctrl_t dma_ctrl;
  dma_ctrl.clk_i(clk_i);
  dma_ctrl.rst_ni(rst_ni);
  dma_ctrl.start_i(start_i);
  dma_ctrl.length_i(length_i);
  dma_ctrl.source_addr_lsb_i(source_addr_lsb_i);
  dma_ctrl.source_addr_msb_i(source_addr_msb_i);
  dma_ctrl.dest_addr_lsb_i(dest_addr_lsb_i);

========================================================
example2_i-d_t-0.7.v
 reg pmp_access_type_en = rst_ni ? 0:1;
  
  reg [8:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en;  
  
  always @(posedge clk_i or posedge rst_ni) begin 
    if(rst_ni) begin
      dma_ctrl_reg <= CTRL_IDLE;
      dma_ctrl_new <= CTRL_IDLE;
      pmp_access_type_reg <= riscv::ACCESS_WRITE;
      pmp_access_type_new <= riscv::ACCESS_WRITE;
      pmp_addr_reg <= 0
end

end

========================================================
example3_i-d_t-0.7.v
  always @(posedge clk_i) begin
    pmp_access_type_reg  <=  pmp_access_type_new; 
    pmp_access_type_en <= 1'b1; 
      pmp_addr_reg <= pmp_addr_new; 
      pmp_addr_en <= 1'b1; 
  
end

========================================================
example4_i-d_t-0.7.v
//  assign pmp_access_type_en = (reset_i == 1) ? 0 : 1'b0;

  reg [63:0] pmp_cfg_reg, pmp_cfg_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_cfg_en; 
// Assign 0 to register when reset is low.
// FIX:
//  assign pmp_cfg_en = (reset_i == 1) ? 0 : 1'b0;

  //// Logic
  assign_nested_logic_control_signals(ctrl_load,
				      ctrl_idle,
				      ctrl_check_load, 
				      ctrl_start_load, 
				      ctrl_check_store, 

========================================================
example5_i-d_t-0.7.v
  //reg pmp_access_type_en = 1'b1;
  reg pmp_access_type_en; 

  //// Local Signals
  reg [DMA_CTRL_WIDTH-1:0]  dma_ctrl_local, dma_ctrl_next;
  reg [63:0]  pmp_addr_local, pmp_addr_next;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [DMA_ACCESS_WIDTH-1:0]  pmp_access_type_local, pmp_access_type_next;
// Assign 0 to register when reset is low.
// FIX:
  //reg [DMA_ACCESS_WIDTH-1:0]  pmp_access_type_local = 'd0;
 
========================================================
example6_i-d_t-0.7.v
  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin
      pmp_access_type_reg <= 0;
      pmp_addr_reg <= 0;
    
end

end

========================================================
example7_i-d_t-0.7.v
assign pmp_access_type_en = rst_ni ? 0 : 1'b1; 
  reg pmp_access_type_en_new; 
  reg pmp_cfg_reg, pmp_cfg_new; 
  reg pmp_cfg_en; 

  //// Logic
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl; 
  reg dma_ctrl_en; 
  reg [63:0] pmp_addr; 
  reg pmp_addr_en;  
  reg pmp_access_type; 
  reg pmp_access_type_en; 
  reg pmp_cfg; 
  reg pmp_cfg_en; 
  reg valid;
  reg valid_new;
  assign valid_o = valid; 
========================================================
example8_i-d_t-0.7.v
  reg pmp_access_type_en = rst_ni;
  reg [13:0] pmp_region_reg, pmp_region_new; // riscv::PMP_REGION_FLASH, riscv::PMP_REGION_SRAM, etc.
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg pmp_region_en; 
// Assign 0 to register when reset is low.
// FIX:
  reg pmp_region_en = rst_ni;
  reg [12:0] pmp_access_reg, pmp_access_new; // riscv::PMP_ACCESS_RWX, riscv::PMP_ACCESS_RW, riscv::PMP_ACCESS_RX, etc.
// BUG: Uninitialized Value on
========================================================
example9_i-d_t-0.7.v
  reg [63:0] pmp_access_type_en = 'h0; 
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 

  reg [1:0] enable_d; 

  //// 
  reg [DATA_WIDTH-1:0] counter; 
  reg [63:0] addr_reg; 

  reg [63:0] ctrl_reg;
  reg [63:0] valid_reg;
  reg [63:0] length_reg;

  reg [63:0] data_in_reg;
  reg [63:0] data_out_reg;
  reg [63:0] abort_reg;

  assign valid_o = valid_reg; 
  assign abort_reg = 'b0;
========================================================
example10_i-d_t-0.7.v
reg [63:0] pmp_access_type_en_reg; 
  always @(posedge clk_i) begin 
    pmp_access_type_en_reg <= (rst_ni == 1) ? 0 : pmp_access_type_reg;  
    pmp_access_type_en <= pmp_access_type_en_reg; 
    pmp_access_type_reg <= pmp_access_type_new; 
  
end

========================================================
example11_i-d_t-0.7.v
  reg [63:0] pmp_access_type_en_reg, pmp_access_type_en_new;
  assign pmp_access_type_en = pmp_access_type_en_reg;
  always @ (posedge clk_i)
  begin
    if (reset_i)
    begin
      pmp_access_type_en_reg <= 0; 
    
end

end

========================================================
example12_i-d_t-0.7.v
reg [3:0] pmp_access_type_en; 


  reg dma_ctrl_check_load, dma_ctrl_start_load, dma_ctrl_load, dma_ctrl_check_store, dma_ctrl_start_store, dma_ctrl_store, dma_ctrl_done; 
  reg dma_ctrl_abort; 
  reg valid_idle, valid_load, valid_store, valid_done; 

  //// Local Variables
  reg [DATA_WIDTH-1:0] temp_length_lsb, temp_length_msb, temp_source_addr_lsb, temp_source_addr_msb, temp_dest_addr_lsb, temp_dest_addr_msb; 
  reg [DATA_WIDTH-1:0] length_
========================================================
example13_i-d_t-0.7.v
  wire pmp_access_type_en; 
 
  reg [7:0] pmpcfg_reg, pmpcfg_new; 
  reg pmpcfg_en;

  //// Local Signals

  reg [DATA_WIDTH-1:0] current_source_addr_lsb_d;
  reg [DATA_WIDTH-1:0] current_source_addr_msb_d;
  reg [DATA_WIDTH-1:0] current_dest_addr_lsb_d;
  reg [DATA_WIDTH-1:0] current_dest_addr_msb_d;
  reg [DATA_WIDTH-1:0] current_data_d;
  reg [DATA_WIDTH-1:0] current_len_d;
  reg [3:0]
========================================================
example14_i-d_t-0.7.v
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:
// FIX:

  reg [63:0] pmp_address_reg, pmp_address_new;
  reg pmp_address_en;  
  reg [63:0] pmp_size_reg, pmp_size_new;
  reg pmp_size_en;  

  reg [63:0] pmp_write_data_reg, pmp_write_data_new;
  reg pmp_write_data_en;  

  reg [63:0] pmp_read_data_reg, pmp_read_data_new;
  reg pmp_read_data_en;  

  reg [63:0] pmp_write
========================================================
example15_i-d_t-0.7.v
//  initial pmp_access_type_en = 0;
// Assign 1 to register when reset is high.
// FIX:
//  initial pmp_access_type_en = 1;

  //// States
  reg [DMA_CTRL_WIDTH-1:0] dma_ctrl_state; 
  reg [63:0] pmp_addr_state;
  reg pmp_access_type_state; // riscv::ACCESS_WRITE or riscv::ACCESS_READ
  reg pmp_access_type_en_reg; // riscv::ACCESS_WRITE or riscv::ACCESS_READ

  //// Counters
  reg [63:0] pmp_addr_counter;
  reg [63:0] pmp_access_type_counter;

  //// Registers
========================================================
example16_i-d_t-0.7.v
  always @(posedge clk_i) begin
    if(rst_ni) begin
      pmp_access_type_reg <= riscv::ACCESS_NONE;
      pmp_access_type_new <= riscv::ACCESS_NONE;
    
end

end

========================================================
example17_i-d_t-0.7.v
  reg [1:0] pmp_access_type_en; 

  // state machine
  reg CTRL_CTRL_REG;
  reg [3:0] CTRL_STAGE;
  reg [DMA_CTRL_WIDTH-1:0] CTRL_STEP;
  reg [DMA_CTRL_WIDTH-1:0] CTRL_COUNT;

  //// Code

  always @(posedge clk_i) begin

    // reset logic
    if (rst_ni) begin
      start_d <= 0;
      length_d <= 0;
      source_addr_lsb_d <= 0;
      source_addr_msb_d <= 0;
      dest_addr_lsb_d <= 0;
      dest_addr_msb_d <= 0;
      done_d <= 0;
end

end

========================================================
example18_i-d_t-0.7.v
  reg [63:0] pmp_access_type_en;

  reg [63:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en;  
  
  //// Internal Variables
  reg [DMA_CTRL_WIDTH-1:0] ctrl_next; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_prev; 
  reg [DMA_CTRL_WIDTH-1:0] ctrl_ctrl; 
  reg [DMA_CTRL_WIDTH-1:0] valid_next; 
  reg [DMA_CTRL_WIDTH-1:0] valid_prev; 
  reg [DMA_CTRL_WIDTH-1:0] valid_ctrl; 
  reg
========================================================
example19_i-d_t-0.7.v
  always @(posedge clk_i) begin
    if (rst_ni) begin
      pmp_access_type_reg <= 0;
      pmp_access_type_new <= 0;
//      pmp_access_type_en <= 0;
    
end

end

========================================================
example0_i-d_t-0.9.v
// Assign reset value for registers holding security settings.

  reg [11:0] pmpcfg_reg, pmpcfg_new; 
  reg [1:0]  pmpcfg_en;  
  
  always @(posedge clk_i) begin
     if (rst_ni) begin
         dma_ctrl_reg <= CTRL_IDLE ;
         dma_ctrl_new <= CTRL_IDLE ;
         dma_ctrl_en <= 0;
         
         start_d     <= 0;
         length_d    <= 0;
         source_addr_lsb_d  <= 0;
         source_addr_msb_d  <= 0; 
         dest_addr_lsb_d    <= 0;
         dest_addr_msb_d    <= 0; 
         done_d        <=
end

end

========================================================
example1_i-d_t-0.9.v
  reg [63:0] reg64, reg64_new;
  reg [63:0] reg64_mem_addr, pmpcfg_new, pmpcfg_mem_addr;

  always @(posedge clk_i) begin
    if (rst_ni) begin
      #0
      dma_ctrl_reg    <= CTRL_IDLE; 
      dma_ctrl_en   <= 0; 
      pmp_addr_reg  <= 0; 
      pmp_addr_en   <= 0; 
      pmp_access_type_reg <= ACCESS_WRITE; 
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//      pmp_access_type_en <= 0; 
      start_d  <= 0;   
      length_d  <= 0; 
      source
end

end

========================================================
example2_i-d_t-0.9.v
//  initial  pmp_access_type_reg, pmp_access_type_new = 0;

  //// Stages
  reg [DATA_WIDTH-1:0] pmp_addr_lsb_d, pmp_addr_lsb_reg;
  assign pmp_addr_lsb_d = pmp_addr_lsb_reg;
  assign pmp_addr_lsb_reg = pmpaddr_i[53];
  
  always @(posedge clk_i or negedge rst_ni) begin
    if (rst_ni == 1'b1) begin
        dma_ctrl_reg <= CTRL_IDLE; 
        pmp_access_type_reg <= riscv::ACCESS_READ; 
        pmp_access_type_new <= riscv::ACCESS
end

end

========================================================
example3_i-d_t-0.9.v
 reg [2:0] pmp_access_type_en_reg, pmp_access_type_en_new;
  assign pmp_access_type_en = (pmp_access_type_en_reg == 'b010)? 1 : 0; 
 

  reg [63:0] pmp_addr_reg, pmp_addr_new;
  reg pmp_addr_en; 

  riscv::pmp_access_t pmp_access_type_reg, pmp_access_type_new; // riscv::ACCESS_WRITE or riscv::ACCESS_READ


  //// Internal Variables
  reg [5:0] dma_cycle_cnt; // I need the counter to protect against losing the reset when the length is 1
  reg [CPU_ID_WIDTH-1:
========================================================
example4_i-d_t-0.9.v
  always @(posedge rst_ni) begin
    pmp_access_type_reg = riscv::ACCESS_NULL;
  
end

========================================================
example5_i-d_t-0.9.v
  always @(posedge clk_i) begin
    if(reset_ni)
        pmp_access_type_reg = 0;
  
end

========================================================
example6_i-d_t-0.9.v
  reg pmp_access_type_en_reg;
  assign pmp_access_type_en_reg = pmp_access_type_new ? 1'b1 : 1'b0;

  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_new <== 0;
      start_d <== 0;
      length_d <== 0;
      source_addr_lsb_d <== 0;
      source_addr_msb_d <== 0;
      dest_addr_lsb_d <== 0;
      dest_addr_msb_d <== 0;
      done_d <== 0;
      pmp_addr_new <== 0; 
    
end

end

========================================================
example7_i-d_t-0.9.v

  reg valid_d; 
  reg [5:0]  valid_cnt, valid_cnt_new; 


  //// Context
  store_context_t ctx; 
  
  //// DMA State Machine
  reg CTRL_IDLE; 
  reg CTRL_CHECK_LOAD; 
  reg CTRL_START_LOAD; 
  reg CTRL_LOAD; 
  reg CTRL_CHECK_STORE; 
  reg CTRL_START_STORE; 
  reg CTRL_STORE; 
  reg CTRL_DONE; 
  reg CTRL_ABORT; 

  reg VALID_IDLE; 
  reg VALID_LOAD; 
  reg VALID_STORE; 
  reg VALID_DONE; 
  reg VALID_HALT; 

  reg [15:
========================================================
example8_i-d_t-0.9.v
// Do NOT move the following assign away from assignment to the next line
// in Verilog. If you do so, the pmp resets not being zero asserted will
// be emitted (check pmppmi_t.v).
  reg [31:0] pmp_access_type_en; 

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg sec_instr_reg, sec_instr_new;
// Assign 0 to register when reset is low.
// FIX:
// Do NOT move the following assign away from assignment to the next line
// in Verilog. If you do so, the pmp resets not being zero asserted will
// be emitted (check pmppmi_t.v).
  reg [31:0] sec_instr_reg, sec_instr_new;


  riscv
========================================================
example9_i-d_t-0.9.v
  reg [63:0] pmp_access_type_en; 
// End of Bug Fix for Uninitialized Value on Reset for Registers Holding Security Settings. 


  //// Initialisation function
  always @(posedge clk_i or posedge rst_ni) begin  
      if (~rst_ni) begin   
        dma_ctrl_reg <= 4'd0; 
        dma_ctrl_new <= 4'd0; 
        pmp_addr_reg <= 0; 
        pmp_addr_new <= 0; 
        pmp_access_type_reg <= riscv::ACCESS_WRITE; 
        pmp_access_type_new <= riscv::ACCESS_WRITE; 
        pmp_access_type_en <= 0;
      
end

end

========================================================
example10_i-d_t-0.9.v
  reg [7:0] pmpcfg_reg, pmpcfg_new;
  reg pmpcfg_en; 
  
  always @(*) begin
    if (reset) begin
       dma_ctrl_reg <= DMA_CNTRL_IDLE;
       pmp_addr_reg <= 0;
       pmp_access_type_reg <= riscv::ACCESS_WRITE;
       pmpcfg_reg <= 0; 
       done_d <= 0;
       start_d <= 0; 
       length_d <= 0; 
       source_addr_lsb_d <= 0;
       source_addr_msb_d <= 0; 
       dest_addr_lsb_d <= 0; 
       dest_addr_msb_d <= 0;
    
end

end

========================================================
example11_i-d_t-0.9.v
 reg [63:0] pmp_access_type_en = (clk_i && rst_ni) ? 0 : pmp_access_type_reg; 
  
  ////////////////////
  // Control Logic
  ////////////////////
  reg [DMA_CTRL_WIDTH-1:0] ctrl_reg, ctrl_new;
  reg ctrl_en; 

  always @(posedge clk_i) begin 
    ifr_o <= (done_i && done_i == done_d);
  
end

========================================================
example12_i-d_t-0.9.v
  always @ (posedge clk_i) begin  
    pmp_access_type_reg <= pmp_access_type_new; 
    pmp_addr_reg <= pmp_addr_new; 
  
end

========================================================
example13_i-d_t-0.9.v
  logic pmp_access_type_en; 
  initial pmp_access_type_en = 0;

// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [8:0] pmpcfg_reg, pmpcfg_new; 
// Assign 0 to register when reset is low.
// FIX:
  logic [8:0] pmpcfg_reg, pmpcfg_new;
  initial pmpcfg_reg = 0; 

  reg valid_d;

  always @(negedge clk_i or posedge rst_ni) begin
      if(rst_ni == 1) begin
        dma_ctrl_reg <= CTRL_IDLE ;
        dma_ctrl_new <= CTRL_IDLE ;
        dma_ctrl_en <= 0 ;
      
end

end

========================================================
example14_i-d_t-0.9.v
  reg pmp_access_type_en = 1'b0; 

  //// Logic
  always @(posedge clk_i) begin
    if (rst_ni) begin
      dma_ctrl_new :=  DMA_CTRL_IDLE;
      pmp_addr_new  :=  0;
      pmp_access_type_new := ACCESS_READ;

    
end

end

========================================================
example15_i-d_t-0.9.v
assign pmp_access_type_en = rst_ni; // rst_ni[4:0];

  reg [16-1:0][53:0] pmp_addr_reg, pmp_addr_new;
  riscv::pmpaddr_t pmp_addr_type_reg, pmp_addr_type_new;
// BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
//  reg [16-1:0][53:0] pmp_addr_type_en; 
// Assign pmpaddr the correct value when reset is low.
// FIX:
assign pmp_addr_type_en = rst_ni; // rst_ni[4:0];

 
  always @ (posedge clk_i or posedge rst_ni) begin
    if (rst
end

========================================================
example16_i-d_t-0.9.v
   reg [5:0] pmp_access_type_en;
 
  reg [5:0] pmp_cfg_reg,             pmp_cfg_new;           
  reg pmp_cfg_en; 

  assign dma_ctrl_en =  !rst_ni;
  assign pmp_addr_en = !rst_ni;
  assign pmp_cfg_en  = !rst_ni;
  assign pmp_access_type_en = !rst_ni; 

  always @(posedge clk_i or negedge rst_ni) begin
    if (~rst_ni) begin

      dma_ctrl_reg   <= CTRL_IDLE; 
      done_d         <= 0;

      pmp_cfg_reg    <= 0; 
      pmp_addr_reg
end

end

========================================================
example17_i-d_t-0.9.v
  assign pmp_access_type_reg = pmp_access_type_new; 
  assign pmp_access_type_en = 1;
  
  //// State Machine
  //// State: Idle
  always @ (posedge clk_i) begin
    // Reset Logic
    if (rst_ni) begin
      dma_ctrl_reg <= DATA_WIDTH'd0;
      dma_ctrl_en <= 0;
      pmp_addr_reg <= pmp_addr_new;
      pmp_addr_en <= 0;
      pmp_access_type_reg <= pmp_access_type_new;
    
end

end

========================================================
example18_i-d_t-0.9.v
assign pmp_access_type_en = rst_ni ? 'b0:pmp_access_type_reg; 

//  reg riscv::ctrl_t ctrl_reg, ctrl_new; 
//  reg riscv::ctrl_t pmp_access_type_reg, pmp_access_type_new;


  reg [DATA_WIDTH-1:0] dma_temp_address_lsb, dma_temp_address_msb; 
  reg [DATA_WIDTH-1:0] dma_temp_length_left; 
  reg [DATA_WIDTH-1:0] dma_word_count; 
  reg [DATA_WIDTH-1:0] dma_word_total; 

  assign valid_o = dma_ctrl_reg
========================================================
example19_i-d_t-0.9.v
// JROD: I believe it is a bug that the reset causes this 
  always @ (posedge rst_ni or posedge rst_ni)
  begin
    dma_ctrl_reg    <=  0;
    dma_ctrl_new    <=  0;
    pmp_addr_reg   <=  0;
    pmp_addr_new   <=  0;
    pmp_access_type_reg  <=  riscv::ACCESS_WRITE;
//    pmp_access_type_new  <=  0;
  
end

========================================================
example0_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.1.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.1.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.3.v
  reg pmp_access_type_en;
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example6_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.3.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.3.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.5.v
  reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example9_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example14_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.5.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.5.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example2_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example3_i-e_t-0.7.v
  reg pmp_access_type_en;
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_en <= 0;
    
end

end

========================================================
example4_i-e_t-0.7.v
    reg [2:0] pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example5_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example6_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example7_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.7.v
  reg pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
      if (!rst_ni) begin
          pmp_access_type_en <= 0;
      
end

end

========================================================
example9_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.7.v
    reg [1:0] pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example13_i-e_t-0.7.v
  reg pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
      if (!rst_ni) begin
          pmp_access_type_en <= 0;
      
end

end

========================================================
example14_i-e_t-0.7.v
//  reg [riscv::ACCESS_WIDTH-1:0] pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.7.v
    reg [3:0] pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.7.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example17_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example18_i-e_t-0.7.v
  reg pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
      if (!rst_ni) begin
          pmp_access_type_en <= 0;
      
end

end

========================================================
example19_i-e_t-0.7.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example0_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example1_i-e_t-0.9.v
    reg pmp_access_type_en; 

  reg pmp_1k_en, pmp_1k_en_new;
  reg pmp_2k_en, pmp_2k_en_new;
  reg pmp_4k_en, pmp_4k_en_new;
  reg pmp_8k_en, pmp_8k_en_new;
  reg pmp_64k_en, pmp_64k_en_new;
  reg pmp_1M_en, pmp_1M_en_new;
  reg pmp_2M_en, pmp_2M_en_new;
  reg pmp_reserved_1, pmp_reserved_1_new;
  reg pmp_reserved_2, pmp_reserved_2_
========================================================
example2_i-e_t-0.9.v
    reg pmp_access_type_en_reg, pmp_access_type_en_new, pmp_access_type_en; 

  always @ (posedge clk_i) begin 
    if (rst_ni) begin
        dma_ctrl_reg <= {DMA_CTRL_IDLE,0};
        start_d <= 0;    
        length_d <= 0;       
        source_addr_lsb_d <= 0; 
        source_addr_msb_d <= 0; 
        dest_addr_lsb_d <= 0;
        dest_addr_msb_d <= 0;   
        done_d <= 0; 
        dma_ctrl_new <= 0; 
        pmp_addr_reg <= 0;
        pmp_addr_new <= 0;
        access_
end

end

========================================================
example3_i-e_t-0.9.v
    reg pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example4_i-e_t-0.9.v
    reg pmp_access_type_en; 
    
  always @ (posedge clk_i or negedge rst_ni) begin
     if (!rst_ni) begin
// BUG:
         pmp_access_type_reg        <= riscv::ACCESS_READ; // 0;   
//  pmp_access_type_new          <= riscv::ACCESS_READ; // 0;   
// BUG:
         pmp_access_type_new        <= riscv::ACCESS_READ; 
         dma_ctrl_reg                <= ctrl_IDLE; 
         dma_ctrl_new                <= ctrl_IDLE; 
         done_d                     <= 0; 
     
end

end

========================================================
example5_i-e_t-0.9.v
//  reg [1:0] pmp_access_type_en; 
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_en <= 0;
      pmp_access_type_new <= 0;
      pmp_access_type_reg <= 0;
    
end

end

========================================================
example6_i-e_t-0.9.v
	  always @ (posedge clk_i or negedge rst_ni) begin
		if (!rst_ni) begin
			pmp_access_type_reg <= 32'b0;
			pmp_access_type_new <= 32'b0;		
			pmp_addr_reg <= 64'b0;
			pmp_addr_new <= 64'b0;	
			dma_ctrl_reg <= 32'b0;		
			dma_ctrl_new <= 32'b0;		
		
end

end

========================================================
example7_i-e_t-0.9.v
    regp pmp_access_type_en;
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example8_i-e_t-0.9.v
  always @ (posedge clk_i or negedge rst_ni) begin
      if (!rst_ni) begin
          pmp_access_type_en <= 0; 
      
end

end

========================================================
example9_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example10_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example11_i-e_t-0.9.v
      reg pmp_access_type_en;
      always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example12_i-e_t-0.9.v
  reg [3:0] pmp_access_type_en; 
// BUG: Undefined Behavior on Reset when Datapath is not First
//  always @ (posedge clk_i or negedge rst_ni) begin 
//      if (!rst_ni) begin
//          dma_ctrl_reg <= CTRL_IDLE;
//          pmp_addr_reg <= 0;
//          pmp_access_type_reg <= riscv::ACCESS_WRITE;
//      
========================================================
example13_i-e_t-0.9.v
  reg[7:0] pmp_access_type_en;
  always @ (posedge clk_i) begin
    if (we_flag) begin
      ppuint32counter := ~ppuint32counter; 
      dma_ctrl_new <= CTRL_IDLE; 
      pmp_access_type_en <= 0;        
    
end

end

========================================================
example14_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example15_i-e_t-0.9.v
    reg pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example16_i-e_t-0.9.v
  always @ (posedge clk_i or negedge rst_ni) begin
    if (!rst_ni) begin
      pmp_access_type_new <= riscv::ACCESS_WRITE; 
      pmp_access_type_new <= riscv::ACCESS_READ; 
      dma_ctrl_new <= CTRL_IDLE;
      start_d <= 0; 
      length_d <= 0;
      source_addr_lsb_d <= 0; 
      source_addr_msb_d <= 0; 
      dest_addr_lsb_d <= 0; 
      dest_addr_msb_d <= 0; 
      done_d <= 0; 
      pmp_addr_new <= 0; 
    
end

end

========================================================
example17_i-e_t-0.9.v
  reg pmp_access_type_en, pmp_access_type_new;

  always @ (posedge clk_i or negedge rst_ni) begin
    always @ (posedge clk_i) begin
      if (!rst_ni) begin
        dma_ctrl_reg <= DMA_CTRL_IDLE; 
        start_d <= 0; 
        length_d <= 0; 
        source_addr_lsb_d <= 0;
        source_addr_msb_d <= 0; 
        dest_addr_lsb_d <= 0;
        dest_addr_msb_d <= 0;
        done_d <= 0; 
        pmp_addr_reg    <= 0;
        pmp_access_type_reg    <= riscv::ACCESS_WRITE;
     
end

end

end

========================================================
example18_i-e_t-0.9.v
    reg [2:0] pmp_access_type_en; 
    always @ (posedge clk_i or negedge rst_ni) begin
        if (!rst_ni) begin
            pmp_access_type_en <= 0;
        
end

end

========================================================
example19_i-e_t-0.9.v
  reg pmp_access_type_en;  
  reg pmp_access_type_new; 
    
  reg [DATA_WIDTH-1:0] dma_ctrl_counter;
  reg [DATA_WIDTH-1:0] pmp_addr_counter;
  reg pmp_addr_read;
  reg pmp_access_latch;

    //// PORT MAP 
  // Address Generation
  assign out_d = m2s_address;

  // Access Type 
  assign pmp_access_o = pmp_access_type_reg;
  assign write_access = pmp_access_type_reg; 
  reg gen_access_o;
  assign gen_access_o = pmp_access_type_reg;

  // DMA Control
  assign outctl_d =
========================================================
