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example5_i-a_t-0.1.v
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example6_i-a_t-0.1.v
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example12_i-a_t-0.1.v
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example0_i-a_t-0.3.v
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example1_i-a_t-0.3.v
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example2_i-a_t-0.3.v
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example3_i-a_t-0.3.v
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example4_i-a_t-0.3.v
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example5_i-a_t-0.3.v
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example6_i-a_t-0.3.v
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example9_i-a_t-0.3.v
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example10_i-a_t-0.3.v
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example11_i-a_t-0.3.v
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example12_i-a_t-0.3.v
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example15_i-a_t-0.3.v
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example16_i-a_t-0.3.v
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example17_i-a_t-0.3.v
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example19_i-a_t-0.3.v
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example0_i-a_t-0.5.v
//�pmp_access_type_en = (cmd_type == riscv_command_t::ACCESS_READ);
//�pmp_access_type_en = (cmd_type == riscv_command_t::ACCESS_WRITE);

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========================================================
example1_i-a_t-0.5.v
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example2_i-a_t-0.5.v
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example3_i-a_t-0.5.v
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example4_i-a_t-0.5.v
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example5_i-a_t-0.5.v
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example6_i-a_t-0.5.v
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example7_i-a_t-0.5.v
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example8_i-a_t-0.5.v
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========================================================
example9_i-a_t-0.5.v
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example10_i-a_t-0.5.v
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example11_i-a_t-0.5.v
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example12_i-a_t-0.5.v
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example13_i-a_t-0.5.v
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example14_i-a_t-0.5.v
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example15_i-a_t-0.5.v
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example16_i-a_t-0.5.v
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example19_i-a_t-0.5.v
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example0_i-a_t-0.7.v
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example1_i-a_t-0.7.v
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example2_i-a_t-0.7.v
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sysid_qsys_0_control_slave_agent_rsp_fifo_out_valid
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========================================================
example3_i-a_t-0.7.v
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//// assign 
always @(posedge clk_i) begin
	if (rst_ni == 0) begin
	// reset
	// part-select control signal
	disable aw_cs;
	// control signals
	dma_ctrl_reg <= 'd0;
	dma_ctrl_new <= 'd0;
	dma_ctrl_en <= 0;
	// status signals
	start_d <= 'd0;
	length_d <= 'd0;
	source_addr_lsb_d <= 'd0;
	source_addr_msb_d <= 'd0;
	dest_addr_lsb_d <= 'd0;
	dest_addr_msb_d <= 'd0;
	done_d <= 'd0;
	// PMP register
	
end

end

========================================================
example4_i-a_t-0.7.v
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end

end

========================================================
example5_i-a_t-0.7.v
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example6_i-a_t-0.7.v
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========================================================
example7_i-a_t-0.7.v
//�û¸öDMA¾ÍÊÇÁËpmp_load_enable, pmp_rload_enable, pmp_store_enable

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end

end

========================================================
example8_i-a_t-0.7.v
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assign pmp_access_type_new = (start_i == 1'b1) ? riscv_dmem_access_type_i : pmp_access_type
========================================================
example9_i-a_t-0.7.v
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// Interrupts

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// ERROR Interrupt
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// CHECK STORE

// START STORE

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// STOP OUTPUT STORE

// STOP STORE

// DONE

// ABORT

//make sure enable_i is high during load and check store

maulload_and_checker load_and_check (

.clk_i(clk_i),
.rst_i(rst_ni),


.enable_i(dma_ctrl_en),
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.start_
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example10_i-a_t-0.7.v
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example11_i-a_t-0.7.v
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//FIX:
//pmp_access_type_en = (pmp_access_type_reg == riscv::ACCESS_READ) ? 1'b1 : 1'bz;
//pmp_access_type_en = (pmp_access_type_reg == riscv::ACCESS_WRITE) ? 1'b1 : 1'bz;
//pmp_access_type_en = (pmp_access_type_reg == riscv::ACCESS_READ || pmp_access_type_reg == riscv::ACCESS_WRITE) ? 1'b1 : 1'b
========================================================
example12_i-a_t-0.7.v
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example13_i-a_t-0.7.v
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example15_i-a_t-0.7.v
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////// DATAPATH


// FSM:
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// 3. start state
// 4. store state
// 5. done state

// FSM outputs:
//
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// 4. disable

// FSM state table
//
// | S
========================================================
example16_i-a_t-0.7.v
//��¶1¦pmp_access_type_en
//��¶2¦pmp_access_type_en
// BUG:
//�ù¼ÓÆ[pmp_access_type_en]¤ÎÅÜ§Ö¡A
// BUG:
// «e¤j¤U¥i¥H¥Îªºvio¸ô®ð
// FIX:
// «e¤j¤U¥i¥H¥Îªºvio¸ô®ð


========================================================
example17_i-a_t-0.7.v
//�����������
//��?riscv::pmp_access_t pmp_access_type_d = riscv
//riscv::riscv_command_t riscv_command_d
//riscv::riscv_data_t riscv_data_d
//riscv::riscv_data_t riscv_data_new
// FIXED:
//��?riscv_data_t riscv_data_d = riscv
//riscv_data_t riscv_data_new

//assign start_d = (pmp_access_type_reg == riscv::ACCESS_WRITE) ? start_i : start_d;
assign start_d = (start_i_reg == 1'b1)
========================================================
example18_i-a_t-0.7.v
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========================================================
example19_i-a_t-0.7.v
//��ÒÀÒª¿´ÎÊ´úÂë
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========================================================
example0_i-a_t-0.9.v
//��
*/




========================================================
example1_i-a_t-0.9.v
//��商逻辑块
//门幕阴影橙或金质星土模块放置
//水平线延迟模块

//装载块
//1进入运算
//2转状态
//3逐步存储
//4结束

\\\\\\\\\\\\\\\

//的来往bytes_wire原始数据
//mtspr_buf_in_addr:
// 1选择riscv_core获取相应数据的有效指令
// 2m
========================================================
example2_i-a_t-0.9.v
//��ĶžȤاْ̏↓ شݾݽΥݵĽ


========================================================
example3_i-a_t-0.9.v
// Patrik: WHAT THE HELL?? Please check if this is right !
//��면 가져잇약에서 호출.

//=> it takes control from pmp_access_type_en from ifm

// 이전신호에설정된 pmp_access_type_en 연결 후, `ifdef DMA_1W_32_32_32 플러그레이드를 skip 케이스위치로.
always @(posedge clk_i `ifdef DMA_1W_32_32_32
`else
`ifdef D
========================================================
example4_i-a_t-0.9.v
//�河沣奴绅Ĭ篓烽客郦郵㱩㹹
//襻圮霏綄搴骧濸
assign dma_ctrl_reg = pmp_addr_reg[DMA_CTRL_WIDTH-1:0];
assign dma_ctrl_new = pmp_addr_new[DMA_CTRL_WIDTH-1:0];
assign pmp_access_type_reg = (pmp_addr_reg[24]|pmp_addr_reg[31]) ? riscv_tb_dma_access_type_read : riscv_tb_dma_access_type_write;
assign pmp_access_type_new = (pmp_
========================================================
example5_i-a_t-0.9.v
// swoop::pmp_t::m0_port_ena writed in makefile: pipe_load_enable(reg mapconfig_reg[0]);
// swoop::pmp_t::m0_port_addr writed in makefile: pipe_load_addr(reg mapconfig_reg[0]);



always @(posedge clk_i or posedge rst_i)
begin
	if(rst_i)
	begin
	//dw ======== Begin: reset dma ========
	// ======== End: reset dma ========
	
end

end

========================================================
example6_i-a_t-0.9.v
//�cSTATEMACHINE: Start

========================================================
example7_i-a_t-0.9.v
// unearthed logic only for write access.
//��
iculturefifo_upstream_t upstream_fifo_for_rd, upstream_fifo_for_wr,
awfifo_for_rd, awfifo_for_wr,
upstream_fifo_for_link_0, upstream_fifo_for_link_1;

//SpaceEngineersfifoconfigfifo_mbed_tester_0ctor(
//)
//lication
/* verilator lint_off UNUSED */

/* verilator lint_on UNUSED */
localparam FIFO_TEST_DEPTH = 2**FIFO_DEPTH;
/* localparam FIFO_DEPTH = 3; // This is the fpga default
localparam FIFO_HEADER_WIDTH = 64; // This is hardcoded for the fp
========================================================
example8_i-a_t-0.9.v
��ονοι־0� 8λ
 զ•־0v۰


 Multiplexer Control

Ժ━•

չԡʹ•˫

 PORT D0:
↷█ ֲٳ lsb 0λ

 PORT D1:
˽█ ֲٳ lsb 1λ

 PORT D2:
ͼ█ ֲٳ lsb 2λ

 PORT D3:
يd█ ֲٳ lsb 3λ

 PORT D4:
_d█ ֲٳ lsb 4λ

 PORT D5:
0b█ ֲٳ lsb 5λ

 PORT D
========================================================
example9_i-a_t-0.9.v
//�azzzzzz:
// (1) Not setting pmp_access_type_en after a read access may have unpredictable results
// (2) Not setting pmp_access_type_en after a write access may have unpredictable results
// (3) pmp_addr_reg stores all 64 bits of address (drives EAB and doesn't care about upper 6 bits)
// (4) pmp_addr_reg doesn't care about the access type
// (5) pmp_addr_new is not an input to the MPU, but is functionally equivalent
//
// (6) pmp_access_type_reg stores all 7 bits of the access type
// (7) Access types not enabled for a given slice are treated as PASS_SRC
//
// (8) pmp_access_type_en has 6-bit width


//// I/O

����mp
========================================================
example10_i-a_t-0.9.v
//��極reg pmp_access_type_en; 
// FIX:
//ヴァリュリinyl鑲緑紡pmp_access_type_en, 鑲緑紡東鍖.phtml佮軖注鍛.実駘鍙.od

��鑾滉罶Ѱork
幾時
█︼鍛者奄鍙ख़帴淨鍏ㄧ壩浜墬n
뼩ов뒕Pc앀㖗撷test
~~~~~~~~~~~~~~~~~~~
version 1.0
Developed: 2017/9/18
update 2017/10/7:
	add support of blink code
	add edit @org 
~~~~~~~~~~~~~~~~~~~
******************************
========================================================
example11_i-a_t-0.9.v
�(posedge clk)換為request(rst)
always @(posedge clk)begin
if(rst)
begin
pmp_access_type_reg <= `riscv_ACCESS_READ;`riscv_ACCESS_READ

end

end

========================================================
example12_i-a_t-0.9.v
// append enable operation
ipient_controls r
ipient_controls reg
ipient_controls new
ifter begin
if (~rst_out)
r = 0;
else
r = ~r;

end

========================================================
example13_i-a_t-0.9.v
ueblogfile

// Fill ram:
// .RAM_START_ADDR_W_OR_J_47 
// .RAM_END_ADDR_W_OR_K_47 
// .RAM_NUM_WORDS_47

// Not DMA-able
// .RAM_REQUEST_OR_IRQ
// .RAM_REQUEST_OR_IRQ_VLD
// .RAM_READ_OR_WRITE
// .RAM_READ_STROBE_0_84
// .RAM_READ_STROBE_1_47
// .RAM_RESPONSE_0_31
// .RAM_RESPONSE_1_31

// Some signals to stall the loop in the middle to debug
// .RAM_ROUNDING_MASK_67_32
// .RAM_ROUNDING_MASK_LOW
========================================================
example14_i-a_t-0.9.v
//��skipline s1,line1,overkill;



//// Ticks
 Cindices0: FrequencyDivisionClk fdc(clk, tck_m, tck);
 Cindices1: Indicies dma_ctrl_reg, dma_ctrl_new;
 Cindices2: Task switch to appropriate submodule
 mindelay m1(clk, tck, tck_m);
 mindelay m2(tck, tck_m, tck_p);
 mindelay m3(tck_m, tck_p, tck_n);

 Work: Mindelay m4(clk, tck_n, tck_w);


 /// MAIN
 forever @(posedge clk) begin
 if (rst_ni) /// if reset
 begin
 clk_access <= 'b0;
 //d
end

end

========================================================
example15_i-a_t-0.9.v
//��������Ķ�����ƽĻ�����ַ
avioralpwm_parameter_t pmp_parameter_reg, pmp_parameter_new; 
ablishmenthappens_t last_pipeline_reg, last_pipeline_new; 
establishment_entry_t reg_full_entry_t, reg_full_entry_new; 
establishment_exit_t reg_empty_exit_t, reg_empty_exit_new; 
dma_limit_t dma_limit_reg, dma_limit_new;
dma_ben_t dma_ben_reg, dma_ben_new;
dma_busy_t dma_busy_reg, dma_busy_new;
dma_done_t dma_done_reg,dma_done_new
========================================================
example16_i-a_t-0.9.v
//��defmacro SET(pmp_access_type_en) pmp_access_type_new = (pmp_access_type_reg | pmp_access_type_en) & (~dma_ctrl_bypass);
afterclass

`timescale 1ns/10ps

// 6-to-1 mux arbiter

// 6-to-1 Mux arbiter : pulse signal of dmap/imap in response for 
// the appropriate one of cmd/data signals

// Module declaration

module arbiter #(
	parameter DEST_WIDTH = 16,
	parameter UNREGISTERED_RESET = 0,
	parameter CLOSED_DELAY = 3,
	parameter REGISTERED_RESET = 16'd1
	)
	(
	input wire [DEST_WIDTH-1:
========================================================
example17_i-a_t-0.9.v
//��
//////////////





always @(posedge clk_i or negedge rst_ni)
begin
 
 if(!rst_ni)
 
 begin
 start_d<=#1 0;
 length_d<=#1 0;
 source_addr_lsb_d<=#1 0; 
 source_addr_msb_d<=#1 0; 
 dest_addr_lsb_d<=#1 0; 
 dest_addr_msb_d<=#1 0; 
 done_d<=#1 0; 
 
 // regs` siz=#1 0;
 pmp_addr_reg<=#1 0;


end

end

========================================================
example18_i-a_t-0.9.v
//��
//��

/////////////////////////////
// Parallel DMA Controller
/////////////////////////////

equation

logic [64*PARALLEL_WIDTH+1:0] align_array [0:(1<<ADDR_WIDTH)-1];

logic [ADDR_WIDTH-1:0] source_addr [0:(1<<ADDR_WIDTH)-1];
logic [ADDR_WIDTH-1:0] increment_source_addr [0:(1<<ADDR_WIDTH)-1];
logic [ADDR_WIDTH-1:0] dest_addr [0:(1<<ADDR_WIDTH)-1];
logic [PARALLEL_WIDTH-1:0] avail_size [0:(1<<ADDR_WIDTH)-1];


logic
========================================================
example19_i-a_t-0.9.v
��时修改设计, 首先要提没有logic里面的步骤
 TODO:
 /问题: 为什么要设成always@(posedge clk) pmp_access_type_en = (pmp_access_type==ACCESS_WRITE) ? 1 : 0;
 FIX: 对应逻辑
 TODO:
 /问题: 输入参数的pmp_access_type在riscv_dma_controller判断会有不同，所以在凋零的时候就不会做�
========================================================
example0_i-b_t-0.1.v
 1. The following registers are not used in this design:
 2. The following registers are not used in this design:
 3. The following registers are not used in this design:
 4. The following registers are not used in this design:
 5. The following registers are not used in this design:
 6. The following registers are not used in this design:
 7. The following registers are not used in this design:
 8. The following registers are not used in this design:
 9. The following registers are not used in this design:
 10. The following registers are not used in this design:
 11. The following registers are not used in this design:
 12. The following registers are not used in this design:
 13. The following registers are not used in this design:
 14. The following registers are not used in this design:
 15. The
========================================================
example1_i-b_t-0.1.v
 1. Use a register to hold the security setting.
 2. Use a register to hold the security setting for the DMA controller.
 3. Use a register to hold the security setting for the PMP.
 4. Use a register to hold the security setting for the DMA controller.
 5. Use a register to hold the security setting for the CPU.
 6. Use a register to hold the security setting for the PMP.
 7. Use a register to hold the security setting for the CPU.
 8. Use a register to hold the security setting for the DMA controller.
 9. Use a register to hold the security setting for the PMP.
 10. Use a register to hold the security setting for the CPU.
 11. Use a register to hold the security setting for the DMA controller.
 12. Use a register to hold the security setting for the PMP.
========================================================
example2_i-b_t-0.1.v
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========================================================
example3_i-b_t-0.1.v
 1. Use a register to hold the security setting.
 2. Use a register to hold the security setting for the entire DMA.
 3. Use a register to hold the security setting for each DMA channel.
 4. Use a register to hold the security setting for each DMA channel.
 5. Use a register to hold the security setting for each DMA channel.
 6. Use a register to hold the security setting for each DMA channel.
 7. Use a register to hold the security setting for each DMA channel.
 8. Use a register to hold the security setting for each DMA channel.
 9. Use a register to hold the security setting for each DMA channel.
 10. Use a register to hold the security setting for each DMA channel.
 11. Use a register to hold the security setting for each DMA channel.
 12. Use a register to
========================================================
example4_i-b_t-0.1.v
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========================================================
example5_i-b_t-0.1.v
 1. The pmp_access_type_en is not used.
 2. The pmp_access_type_reg is not used.
 3. The pmp_access_type_new is not used.
 4. The pmp_access_type_new is not used.
 5. The pmp_access_type_en is not used.
 6. The pmp_access_type_en is not used.
 7. The pmp_access_type_reg is not used.
 8. The pmp_access_type_reg is not used.
 9. The pmp_access_type_new is not used.
 10. The pmp_access_type_new is not used.
 11. The pmp_access_type_en is not used.
 12. The pmp_access_type_en is
========================================================
example6_i-b_t-0.1.v
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========================================================
example7_i-b_t-0.1.v
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========================================================
example8_i-b_t-0.1.v
//�ìÅÐÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎÞÎ
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//

========================================================
example9_i-b_t-0.1.v
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========================================================
example10_i-b_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_addr_en is not used.
 5. pmp_addr_reg is not used.
 6. pmp_addr_new is not used.
 7. pmp_addr_en is not used.
 8. pmp_addr_reg is not used.
 9. pmp_addr_new is not used.
 10. pmp_addr_en is not used.
 11. pmp_addr_reg is not used.
 12. pmp_addr_new is not used.
 13. pmp_addr_en is not used.
 14. pmp_addr_reg is not used
========================================================
example11_i-b_t-0.1.v
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========================================================
example12_i-b_t-0.1.v
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========================================================
example13_i-b_t-0.1.v
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========================================================
example14_i-b_t-0.1.v
 1. The DMA controller will not be able to access the PMP if the security settings are set to read-only.
 2. The DMA controller will be able to access the PMP if the security settings are set to read-write.
 3. The DMA controller will be able to access the PMP if the security settings are set to read-only.
 4. The DMA controller will not be able to access the PMP if the security settings are set to write-only.
 5. The DMA controller will be able to access the PMP if the security settings are set to write-only.
 6. The DMA controller will not be able to access the PMP if the security settings are set to read-write.
 7. The DMA controller will be able to access the PMP if the security settings are set to read-write.
 8. The DMA controller will
========================================================
example15_i-b_t-0.1.v
��
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
========================================================
example16_i-b_t-0.1.v
// 1. Use a register to hold the security setting.
// 2. Use a register to hold the security setting for the DMA.
// 3. Use a register to hold the security setting for the PMP.
// 4. Use a register to hold the security setting for the PIC.
// 5. Use a register to hold the security setting for the PIC.
// 6. Use a register to hold the security setting for the PIC.
// 7. Use a register to hold the security setting for the PIC.
// 8. Use a register to hold the security setting for the PIC.
// 9. Use a register to hold the security setting for the PIC.
// 10. Use a register to hold the security setting for the PIC.
// 11. Use a register to hold the security setting for the PIC.
// 12. Use a register to hold the security setting for the PIC.

========================================================
example17_i-b_t-0.1.v
 1. The DMA controller will not be able to access the PMP if the security settings are set to read-only.
 2. The DMA controller will not be able to access the PMP if the security settings are set to write-only.
 3. The DMA controller will not be able to access the PMP if the security settings are set to read-write.
 4. The DMA controller will not be able to access the PMP if the security settings are set to read-only.
 5. The DMA controller will not be able to access the PMP if the security settings are set to write-only.
 6. The DMA controller will not be able to access the PMP if the security settings are set to read-write.
 7. The DMA controller will not be able to access the PMP if the security settings are set to read-only.
 8. The
========================================================
example18_i-b_t-0.1.v
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========================================================
example19_i-b_t-0.1.v
 1. The DMA controller will not be able to access the PMP if the security settings are set to read-only.
 2. The DMA controller will not be able to write to the PMP if the security settings are set to write-only.
 3. The DMA controller will not be able to write to the PMP if the security settings are set to read-only.
 4. The DMA controller will not be able to read from the PMP if the security settings are set to write-only.
 5. The DMA controller will not be able to read from the PMP if the security settings are set to read-only.
 6. The DMA controller will not be able to write to the PMP if the security settings are set to read-only.
 7. The DMA controller will not be able to write to the PMP if the security settings are set to write-only
========================================================
example0_i-b_t-0.3.v
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========================================================
example1_i-b_t-0.3.v
 1. Reset value of pmp_access_type_en should be 0.
 2. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 3. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 4. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 5. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 6. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 7. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 8. pmp_access_type_en should be updated when dma_ctrl_en is asserted.
 9. pmp_
========================================================
example2_i-b_t-0.3.v
��
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
========================================================
example3_i-b_t-0.3.v
 1. Use a register to hold the security setting, and set it to a known state at reset.
 2. Use a register to hold the security setting, and set it to a known state at reset.
 3. Use a register to hold the security setting, and set it to a known state at reset.
 4. Use a register to hold the security setting, and set it to a known state at reset.
 5. Use a register to hold the security setting, and set it to a known state at reset.
 6. Use a register to hold the security setting, and set it to a known state at reset.
 7. Use a register to hold the security setting, and set it to a known state at reset.
 8. Use a register to hold the security setting, and set it to a known state at reset.
 9. Use a register to hold the security setting, and set it to
========================================================
example4_i-b_t-0.3.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_addr_en is not used.
 5. pmp_addr_reg is not used.
 6. pmp_addr_new is not used.
 7. pmp_addr_en is not used.
 8. pmp_addr_reg is not used.
 9. pmp_addr_new is not used.
 10. pmp_addr_en is not used.
 11. pmp_addr_reg is not used.
 12. pmp_addr_new is not used.
 13. pmp_addr_en is not used.
 14. pmp_addr_reg is not used
========================================================
example5_i-b_t-0.3.v
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:
//��
// DONE: Done signal from the DMA controller.
//FIX:

========================================================
example6_i-b_t-0.3.v
//�ò¼¶Êý¾ÝÒì³Ö
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========================================================
example7_i-b_t-0.3.v
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========================================================
example8_i-b_t-0.3.v
��
 DMA_CTRL_WIDTH = 32
 DMA_CTRL_WIDTH = 64
 DMA_CTRL_WIDTH = 128
 DMA_CTRL_WIDTH = 256
 DMA_CTRL_WIDTH = 512
 DMA_CTRL_WIDTH = 1024
 DMA_CTRL_WIDTH = 2048
 DMA_CTRL_WIDTH = 4096
 DMA_CTRL_WIDTH = 8192
 DMA_CTRL_WIDTH = 16384
 DMA_CTRL_WIDTH = 32768
 DMA_CTRL_WIDTH = 65536
 DMA_CTRL_WIDTH = 131072
 DMA_CTRL_WIDTH = 262144
 DMA_CTRL_W
========================================================
example9_i-b_t-0.3.v
�ò¼Ò¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p¼Ö¦³¤j¤p
========================================================
example10_i-b_t-0.3.v
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========================================================
example11_i-b_t-0.3.v
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========================================================
example12_i-b_t-0.3.v
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========================================================
example13_i-b_t-0.3.v
 1) Uninitialized value on reset.
 2) pmp_access_type_en is not used.
 3) pmp_access_type_en is not used.
 4) pmp_access_type_en is not used.
 5) pmp_access_type_en is not used.
 6) pmp_access_type_en is not used.
 7) pmp_access_type_en is not used.
 8) pmp_access_type_en is not used.
 9) pmp_access_type_en is not used.
 10) pmp_access_type_en is not used.
 11) pmp_access_type_en is not used.
 12) pmp_access_type_en is not used.
 13) pmp_access_type_en is not used
========================================================
example14_i-b_t-0.3.v
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========================================================
example15_i-b_t-0.3.v
�ðîâåðèì, ÷òîáû ââåñòèòüñÿ, ÷òîáû ââåñòèòüñÿ, ÷òîáû ââåñòèòüñÿ,
ñòàðèñâàòüñÿ, ÷òîáû ââåñòèòüñÿ, ÷òîáû ââåñòèòüñÿ,
ñòàðèñâàòüñÿ, ÷òîáû ââåñòèòüñÿ, ÷òîáû ââåñòèòüñÿ
========================================================
example16_i-b_t-0.3.v
 1. The pmp_access_type_en is not used.
 2. The pmp_access_type_reg is not used.
 3. The pmp_access_type_new is not used.
 4. The pmp_access_type_new is not assigned.
 5. The pmp_access_type_new is not updated.
 6. The pmp_access_type_new is not synchronized.
 7. The pmp_access_type_new is not registered.
 8. The pmp_access_type_new is not deregistered.
 9. The pmp_access_type_new is not reset.
 10. The pmp_access_type_new is not cleared.
 11. The pmp_access_type_new is not locked.
 12. The pmp_access_type_new
========================================================
example17_i-b_t-0.3.v
 1. The DMA controller is not initialized on reset.
 2. The DMA controller is not enabled on reset.
 3. The DMA controller is not enabled on reset.
 4. The DMA controller is not enabled on reset.
 5. The DMA controller is not enabled on reset.
 6. The DMA controller is not enabled on reset.
 7. The DMA controller is not enabled on reset.
 8. The DMA controller is not enabled on reset.
 9. The DMA controller is not enabled on reset.
 10. The DMA controller is not enabled on reset.
 11. The DMA controller is not enabled on reset.
 12. The DMA controller is not enabled on reset.
 13. The DMA controller is not enabled on reset.
 14. The DMA controller is not enabled on reset.
 15. The
========================================================
example18_i-b_t-0.3.v
����ַ�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ���־�Ĵ
========================================================
example19_i-b_t-0.3.v
 1. The DMA controller is not designed to be used in a multi-core system.
 2. The DMA controller is designed to be used in a single-core system.
 3. The DMA controller is designed to be used in a multi-core system, but only
 when the system has only one core.
 4. The DMA controller is designed to be used in a multi-core system, but only
 when the system has more than one core, and only when the system has more than one
 DMA controller.
 5. The DMA controller is designed to be used in a multi-core system, but only
 when the system has more than one DMA controller.
 6. The DMA controller is designed to be used in a multi-core system, but only
 when the system has more than one DMA controller, and only when the system has
 more than
========================================================
example0_i-b_t-0.5.v
//�òÀïË¯¾ð¼õ¸ôÀ´Ê¹Ë¯

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========================================================
example1_i-b_t-0.5.v
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========================================================
example2_i-b_t-0.5.v
//��
// 

// This is the top level control of the DMA controller.
// The controller has 4 modes of operation:
// 1. Single Port, Single Access
// 2. Single Port, Dual Access
// 3. Dual Port, Single Access
// 4. Dual Port, Dual Access
// The controller is configured via the pmp_config register.
// The controller can only be started by issuing a START command.
// The controller can be stopped by issuing a STOP command.
// The controller can be loaded by issuing a LOAD command.
// The controller can be unloaded by issuing an UNLOAD command.
//
// The controller is configured using two sets of registers:
// 1. A set of registers that are readable and writable by the CPU.
// 2. A set of registers that are readable only by the CPU.
//
// The configuration registers are as follows:
// 1. pmp
========================================================
example3_i-b_t-0.5.v
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========================================================
example4_i-b_t-0.5.v
��FIX:
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIX:
 FIX:
 BUG:
========================================================
example5_i-b_t-0.5.v
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========================================================
example6_i-b_t-0.5.v
�ÎÑ¡ÂÊÀ¸¸é¼ÓËÀµô
 pmp_access_type_en = 1'b1;
 pmp_access_type_en = 1'b0;
 pmp_access_type_en = 1'b1;
 pmp_access_type_en = 1'b0;
 pmp_access_type_en = 1'b1;
 pmp_access_type_en = 1'b0;
 pmp_access_type_en = 1'b1;
 pmp_access_type_en = 1'b0;
 pmp_access_type_en = 1'b1;
 pmp_access_type_en = 1'b0;
 pmp_access_type_en =
========================================================
example7_i-b_t-0.5.v
�Ý››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››››
========================================================
example8_i-b_t-0.5.v
��FIXME:
�FIXME:
 FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
�FIXME:
 FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:
 BUG: Uninitialized Value on Reset for Registers Holding Security Settings.
FIXME:

========================================================
example9_i-b_t-0.5.v
//�solution:
//
//1. Modify the code such that it does not read the security settings from the registers 
//and instead gets the information from the OS. The information should be passed 
//in the reset message.
//2. In the ISR, read the security information from the registers, and then update the 
//information on the bus. 

///// Internal Connections
// Internal Register Assignments
//
// pmp_addr_reg: 64-bit address bus for the peripheral mapped memory. 
// pmp_addr_new: 64-bit address bus for the peripheral mapped memory. 
// pmp_addr_en: 1 for address update, 0 for no change. 
// dma_ctrl_reg: control bits for the DMA. 
// dma_ctrl_new: control bits for the DMA. 
// dma_ctrl
========================================================
example10_i-b_t-0.5.v
//��

// DMA Controller
always @(posedge clk_i or negedge rst_i)
begin
	if (rst_i == 1'b0)
	begin
	// Initialize all registers
	// DMA controller
	dma_ctrl_reg <= 'b0;
	dma_ctrl_en <= 1'b0;
	// PMP and PIC
	pmp_addr_reg <= 'b0;
	pmp_addr_en <= 1'b0;
	pmp_access_type_reg <= 'b0;
	pmp_access_type_en <= 1'b0;
	
end

end

========================================================
example11_i-b_t-0.5.v
//�������rst�����ʱ������ʱ��
always @(posedge clk_i)begin
	if(rst_ni)begin
//	if(rst_i)begin
	//reset
	dma_ctrl_reg <= 'd0;
	pmp_addr_reg <= 'd0;
	pmp_access_type_reg <= 'd0;
	
end

end

========================================================
example12_i-b_t-0.5.v
//��.
//�.
//

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========================================================
example13_i-b_t-0.5.v
 1. pmp_access_type_en:
 If DMA_CTRL_SEC_ADDR_WIDTH > 0, the dma_ctrl_en must be asserted to access the register.
 2. pmp_access_type_en:
 The dma_ctrl_en must be asserted to access the register.
 3. pmp_access_type_reg:
 The dma_ctrl_en must be asserted to access the register.
 4. pmp_addr_en:
 The dma_ctrl_en must be asserted to access the register.
 5. pmp_addr_reg:
 The dma_ctrl_en must be asserted to access the register.
 6. dma_ctrl_en:
 The dma_ctrl_reg must be asserted to access the register.
 7. dma_ctrl_
========================================================
example14_i-b_t-0.5.v
//�pmp_access_type_en_reg_rst
//�pmp_access_type_en_reg_en
//�pmp_access_type_en_reg_rst
//pmp_access_type_en_reg_en
//pmp_access_type_en_reg_rst
//pmp_access_type_en_reg_en
///// IOs


///// Registers


///// `define


///// Internal signals

// Internal signals for DMA controller
logic [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_rst; 
logic [DMA_CTRL_WIDTH-1:0] dma_ctrl_reg_en; 
logic [DMA_CTRL_WIDTH-1:0] dma_ctrl
========================================================
example15_i-b_t-0.5.v
��
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
========================================================
example16_i-b_t-0.5.v
�f$rst$clk(1, 1);
�f$rst$clk(0, 1);
�f$rst$clk(1, 1);
 Do not initialize the registers holding the security settings.
�f$rst$clk(0, 1);
 Do not initialize the registers holding the security settings.
�f$rst$clk(0, 1);
 Do not initialize the registers holding the security settings.
�f$rst$clk(0, 1);
 Do not initialize the registers holding the security settings.
�f$rst$clk(0, 1);
 Do not initialize the registers holding the security settings.
�f$rst$clk(0, 1);
 Do not initialize the registers holding the security settings.
�f$rst$cl
========================================================
example17_i-b_t-0.5.v
��ĽĽľȨȩļĽľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľȨȩļľľ
�Ȩȩļ
========================================================
example18_i-b_t-0.5.v
//�
//
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//////////////////////////////////////////////////////////////////////////////////

//////////////////////////////////////////////////////////////////////////////////
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========================================================
example19_i-b_t-0.5.v
�ðîâåðèì, ÷òîáû âûõîäèì â êàêîíîì ïîçíà÷íîñòè
âñòðåòíîñòè, åñëè ïðîâåðèì
âñòðåòíîñòè, åñëè ïðîâåðèì
âñòðåòíîñòè, åñëè ïðîâåðèì
âñòðåòíîñòè, åñëè ïðîâåðèì
âñòðåòíîñòè, å
========================================================
example0_i-b_t-0.7.v
// The main code should read the CCCs before reading the registers.
// If the CCCs are not ready, the main code should wait and retry.
// The main code should determine when the CCCs are ready by
// checking the done_d signal.
// The main code should also only read the security registers when
// the DMA is stopped, ready, and enabled.

// There is something wrong with the design that I am working with that
// sometimes when I press reset, the DMA_CTRL register does not get
// initialized. My guess is that it is related to power up timing.
// It appears that the DMA never actually starts to do anything
// until after the DMA_CTRL reg is initialized.
// I am guessing that the PRERST is assscribing too early.
// It is possible that the DMA actually starts up, but that its
// not
========================================================
example1_i-b_t-0.7.v
always @(posedge clk_i) begin 
pmp_access_type_en <= pmp_access_type_reg;

end

========================================================
example2_i-b_t-0.7.v
//��㣬ɰ аռչաְ
logic [7:0] [16-1:0]��սվմչյֽսյ
logic [7:0] [16-1:0]պݹռչն
logic [7:0] [16-1:0]ּչշֽտ
logic [7:0] [16-1:0]ռչճչ־
logic [7:0] [16-1:0]ճչ־մ
logic [7:0] [16-1:0]մչնչ־
logic [7:0] [16-1:0]չյ־տ
logic [
========================================================
example3_i-b_t-0.7.v
��狀時，釋放起始地址和長庫總數暫時保持1秒的時候，還是背晤產品
狀態，還使用原本的有效值
狀態為rst, 釋放地址變為(0,0)
狀態為check_load, 刪除該變化後的(0,0)
狀態為check_store, 刪除該變化後
========================================================
example4_i-b_t-0.7.v
��FIX:
�FIX:
======================================================================================--
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========================================================
example5_i-b_t-0.7.v
//��
//�
//ð
//ð¡
//ð¡¡
//ð¡¡¡
//ð¡¡¡¡
//ð¡¡
//ð¡¡¡
//ð¡¡¡

 anyways, using register for storing security key
// we need to store the key in reg for checking
// if to do security check
// get the cfg from the start
// then decide which mode to load
// load the key
// then start the dma
// then the dma will use the key to check
// if to continue or to be aborted
// then decide if the key is valid or not
// if valid, then everything is ok
// if not, then we just have to clear the fifo




always @(posedge clk_i or negedge rst_i)
	
========================================================
example6_i-b_t-0.7.v
//����ֹ�Ĵ�����Z�����֮��Z 

//// Outputs
��output reg valid_o; 

//// Common
legates2
Ĳ���

//// Logic
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin

if(rst_ni == 1'b0) // active low reset
begin

valid_o <= 1'b0; 


end

end

========================================================
example7_i-b_t-0.7.v
//��
//�

////


========================================================
example8_i-b_t-0.7.v
//��ʱ
`include "macro.vh"

module dmac(
	input wire clk,
	input wire rst,

	input wire [31:0] dmac_addr,
	input wire dmac_width,
	input wire dmac_be,
	input wire dmac_cycstb,
	input wire dmac_ack,
	input wire dmac_err,
	input wire dmac_rty,
	input wire [31:0] dmac_wdata,

	output wire dmac_read,
	output wire dmac_write,
	output wire dmac_ready,
	output wire [31:0] dmac_rdata,
	output wire dmac_irq
);

wire [7:0] dma_ctrl;
wire dma_ctrl_load;
wire d
========================================================
example9_i-b_t-0.7.v
 Fixing Reset State of Security Registers so they can be used next time.
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========================================================
example10_i-b_t-0.7.v
 1) ADD uninitialized value to all the registers on Reset
 2) ADD CODE to initialize the registers holding security settings on Reset ONLY
 3) REMOVE the lines with initial values from the design i.e.
 4) REMOVE the lines with initial values from the testbench i.e.
 5) REMOVE lines related to reset i.e.
 6) REMOVE lines reading from registers related to access control i.e.
 7) REMOVE lines reading from registers related to arbiter i.e.
 8) REMOVE lines reading from registers related to arbiter address i.e.
 9) REMOVE lines related to security i.e.
 10) REMOVE lines related to arbiter configuration i.e.
 11) REMOVE lines related to arbiter mode i.e.
 12) REMOVE lines related to
========================================================
example11_i-b_t-0.7.v
olithic concept of a flexstture ram with 
1) 2 ports to connect the cpu and dma
2) 1/2 clock width
3) 1/2 memory width
4) 1/2 addr width
5) 1/2 data width
6) 1/2 security width
7) 1/2 security setting width
8) 1/2 start width
9) 1/2 length width
10) 1/2 done width
11) 1/2 status width
12) 1/2 interrupt width
13) 1/2 interrupt enable width
14) 1/2 error width
15) 1/2 transfer type width
16) 1/2 security violation width
17) 1/2 security setting violation width
18) 1/2 start violation width
19) 1/2 length violation width
20) 1
========================================================
example12_i-b_t-0.7.v
//��
// Fei 2014/08/24

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date: 2019/04/27 10:44:55
// Design Name: 
// Module Name: spi_controller
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
//
// Dependencies: 
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
////////////////////////////////////////////////////////////////////////////////


module spi_controller(
input wire clk,
input wire rst,
input wire en,
input wire mode,
input wire bit_order,
input wire [31:0] dout,
input wire [31:0] din,
input wire [31:0] daddr,
input wire [31:0] dwe,
input wire [31
========================================================
example13_i-b_t-0.7.v
��DMA_CTRL, DMA_CTRL_WIDTH为4, 而dma_ctrl_en为1时, 才设置pmp_access_type_en
�原本步骤:
1. 先输出完整的dma_ctrl_reg值, 同时设置dma_ctrl_en为1;
2. 在dma_ctrl_en为0时, 先清零dma_ctrl_reg的值, 再设置dma_ctrl_en为1;
3. 在dma_ctrl_en为0时, 可能出现
========================================================
example14_i-b_t-0.7.v
 1) Reset DMA.
 2) Enable DMA.
 3) Enable the Config Registers.
 4) Read the Config Registers.
 5) Disable the DMA.
 6) Disable the Config Registers.
 7) Read the Config Registers.
 8) Disable the DMA.
 9) Reset the DMA.
 10) Read the Config Registers.
 11) Enable the DMA.
 12) Enable the Config Registers.
 13) Read the Config Registers.
 14) Reset the DMA.

 BUILD NUMBER:
 1.0
 SYNOPSYS:
 Xilinx FPGA Hardware IP Core

 VERSION:
 1.0

 LAST REVISED BY:
 N/A

 DESIGNED BY:

========================================================
example15_i-b_t-0.7.v
� XSTLIB vio_mcb_sim_wrapper.v
vio_mcb_sim_wrapper.v
vio_mcb_sim_wrapper_top.v
vio_mcb_sim_wrapper_bd.v
vio_mcb_sim_wrapper_sld.v
vio_mcb_sim_wrapper_sys.v
vio_mcb_sim_wrapper_mcb_wrapper.v
vio_mcb_sim_wrapper_mcb_wrapper_sim.v
vio_mcb_sim_wrapper_tb.v
vio_mcb_sim_wrapper_tb_xst_tb.v
vio_mcb_sim_wrapper_tb_sys.v
vio_mcb_sim_wrapper_tb_bd
========================================================
example16_i-b_t-0.7.v
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========================================================
example17_i-b_t-0.7.v
�鈥� DMA呰� �߼�����
 When using the DMA to access PMP memory, the access is granted only when the controller has the correct
 security settings for that particular address range. The controller issues an access grant pulse when it
 decodes the pm_enable signal. The grant pulse must be asserted for an amount of time equal to the
 length field in the PMPCFG register.

 When the DMA controller has granted access to the PMP memory, it must use its status register to indicate
 the grant on the PMP enable signal.

 The DMA may assert its status register during its access to the PMP memory. The status register can be
 cleared by the core internally and must be cleared by the DMA when it asserts its enable signal.

 When the DMA controller asserts its enable signal, the core must set its status register
========================================================
example18_i-b_t-0.7.v
� 
� DMA_CTRL_WIDTH
 Max Value: 0x7FFFFFFF
 Max Value: 0x1FFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0x1FFFFFFF 
 Max Value: 0x7FFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0x7FFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0xFFFFFFFF 
 Max Value: 0x
========================================================
example19_i-b_t-0.7.v
//�ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ
//
//Default Settings for the DMA Controller
//
//
//
//
//
//
//
//
//



//
//
//
//
//
//
//
//
//
//
//

========================================================
example0_i-b_t-0.9.v

// The pmp_access_type is high-speed write-once. It is not changed after boot. 
// Thus, it is ignored in simulation.

// assign pmp_access_type_new = pmp_access_type_reg;
// assign pmp_access_type_en = (pmp_access_type_valid);


// CONTROL REGISTERS
// Don't turn on the DMA controller until we've received valid data from the master.
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin 
	if (rst_i == `TRUE)
	begin
	
	
	}
	else
	begin

	
	
	// start_d= 'h0;
	// length_d = 'h0;
	dma_ctrl_en = 0;
	
end

end

end

========================================================
example1_i-b_t-0.9.v
//���break
//►███████████
// * 
// + 
// HELP:
// (FIXME:)
// (FIXME:)
// (FIXME:)
// (FIXME:)
// (FIXME:)
// (FIXME:)
// (FIXME:)
// (FIXME:)
// //(FIXME:)
// >>>>>>>>>>>>>>>>>>>>>>>>>
// (FIXME:)
// >>>>>>>>>>>>>>>>>>>>>>>>>
// (FIXME:)
// >>>>>>>>>>>>>>>>>>>>>>>>>
/*
// DONE: 2017/05/11, Wilson
// DONE: 2017/05/11,
// ART: 2017/05/11
*/

// *******************************************************************************************************
// DONE: 2017/05/11, Wilson
// DONE: 2017/05/11,
// ART: 2017/05/11
// ********************************
========================================================
example2_i-b_t-0.9.v
// Always initialize this field, check if it's correct!
// otherwise, there is no security in the system!
// assign pmp_access_type_en = 1'b1;

//// Ugly Hack: Load the SysCall in a non-sequential fashion, 
//// to 1) Not corrupt the system and 2) The hardware is just going to do it anyway.
//// We will drop the sys_call_cmd when the current command is already stored and valid
//// The issue is that the whole design is not designed to be used like this.
//// We are going with the assumption that the riscv_core module will 
//// reconfig the riscv core and the system will be able to catch up without loosing 
//// the data. 

///////////
///////////
init_reg init_reg;
init_reg init_reg_2;

always_ff @ (
========================================================
example3_i-b_t-0.9.v
//�íðàþòü
//
// RISC-V CORE 1.0 
// 1.0
//
//Áõ
//2004/4/11
//ÐÞ¾÷
//
//´ó¼ÒÐÞ
//


iouslyiflyespeak
//dll start
linesspeak
//dll end
(
//
//n
//
//dxe
//
//n
//
//n
//
)
(
//
//pclk
//
//n
//
//prn
//
);

//
//
//
//
//
//
//

========================================================
example4_i-b_t-0.9.v

//
// jhkim

//
// jhkim: While timer pulse is generated, FPGA cannot pass through data others
// made for OS.
// Therefore, this setting will cause FPGA to stop waiting for data and output
// done_o as EN.

//
// 0330: Disable input done_o if it is invalid value.
// Thus, let output done_o to be drive-low.
// 0330: checkpoint to free up some coding space

//
// $Id: $
// File name: ddr2_pf_top.v
// Created: Tue Apr 16 19:01:32 2021
// Author: Jusein Shim
//
// ddr2_pf_top.v: Toast top-level VHDL file for the DDR2 Peripheral Function
//
// Copyright (C) 2021 Jusein Shim
========================================================
example5_i-b_t-0.9.v
// Heisman implementation made a bug where it was attempting to assign to the reset value
// on debug remover.
//��иlogic [52:0]�áÂÖ¤Î³]¤F¦³address¬°bits 2 - 6 address¬°bits 7 - 15 if address[5:0] == 6'b101 -> rst = 1
always@(posedge clk or negedge rst_n)
begin
	if (~rst_n)
	begin
	
end

end

========================================================
example6_i-b_t-0.9.v
//�[16:8] 
//�[24] load, store, and load-store are restricted to be from 0x0 - 0xFFF



 SyncBlock1 slask( //Sync Block 1
// Outputs
output logic [63:0] pmp_data_o;
output logic [24:0] load_status_o;
input logic clk_i;
input logic rst_i;


// Inputs
input [24:0] fb_data_i;
output logic we_o;
input logic we_n_i;
input logic cp_en_i;
input logic [24:0] fb_tag_i;
input logic [24:0] fb_repl_inf_i;

//tb_status
logic [31:0] status;

//tb_err
logic err
========================================================
example7_i-b_t-0.9.v
//��
// SHOP: (c) 2017, VMware, Inc.; All rights reserved.
//
// This code was generated by a program named VJ-Asarya.
// Autodesk design tools, version 2017.1.2795, Build 2017.09865.1703_SR1.
// This code was generated using a copyrighted hardware description. 
// File release number xx.yyy MM/DD/YYYY


// Title: Pico Co-Processor 
// Coder: Naoshi Yoshioka 
// Module Name: 位器快速消抖特级法分类型计数器
// Target Devices: 位元模块
// Last modified: 七月/22-05-2017 �
========================================================
example8_i-b_t-0.9.v
// If system PTE data is always valid, it's safe enough
// to set them as registers at startup
endez
always @(posedge clk_i) 
begin
	if (rst_ni ==1'b0)
	begin 
	/*
	 * Keys are pressed or not pressed => No PTE
	 * PTE(security bit) = 1'b0 or 1'bz => no access to physical memory
	 */
	
end

========================================================
example9_i-b_t-0.9.v
// read the registers holding security parameters via the dma module
// check the relevant registers to infer if it is a write or a read
// add read or write bits into the dma module

 
 

========================================================
example10_i-b_t-0.9.v
late_create_o_signal output_o_crc_error,
input_o_ready_i_normilized,
input_i_rst_i_normilized;


logic [CONF_WIDTH-1:0] conf [0:CONF_WIDTH-1]; 
logic crc_en_i, crc_en_o;

logic[CONF_WIDTH-1:0] cfg;


logic [CONF_WIDTH-1:0] crc_in, crc = 'b0; 
logic [6:0] buf_crc_out; 

//logic crc_en_i, crc_en_o;
reg [3:0] preamble_cntr;

assign valid_o_tmp = (
========================================================
example11_i-b_t-0.9.v
//�emiaźźźźźĺĺźźeliźĺšźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźekźĺźźźźźźźźźźźźźźźźźźźźźźźźź
// 
always @(posedge clk_i or negedge rst_ni)
begin
if(!rst_ni) //reset
begin
pmp_access_type_reg <= 'h0;
pmp_addr
end

end

========================================================
example12_i-b_t-0.9.v
��ïâàðõíâîðåàíûé ñòðîêè ïðîâåðîêàð.
êàêîíóùóìòðåðàèëèõíðâãoìùðà (.sseg(shot) - for now)
ñþðèõåðåêðèðîâûé fsm.
êàêîíóùóìòðåðàèëèõíðâãoìùðà (.ssw(shot) - for now)
êàêîíóùóìòðåðàèëèõíðâãoìùðà (.ssa(shot) - for now)
êàêî
========================================================
example13_i-b_t-0.9.v
��测试需要对reg的能力（这两个filee的信息）进行测试
或者点击鼠标点击table的情况（FIXME）下需要对reg进行测试，用于测试的ctrl_reg_enX， 设置pmp/pmp_addr/pmpcfg/pmpcfg_reg
或者点击鼠标点击table的情况（FIXME）对pmp/pmp_addr/pmpcfg/pmpcfg_reg的�
========================================================
example14_i-b_t-0.9.v
�ñ¦â¦C³æ­n¥[¤U¥i¥H³æ
 Feldman, Stephen; Seven, Shane; Cleary, Michael; Kaltner, Michael; Bussard,
 Michael; Byron, Ken. "Field Effects in a Synchronous PISO Floating-Point
 ADD/SUB RISC Processor Core". In Proceedings of the IEEE ISPRS-2017
 Conference. Anaheim, CA, 2017. 
 Uninitialized Value on Reset for Registers Holding Security Settings
 Feldman, Stephen; Seven, Shane; Cleary, Michael; Kaltner, Michael;
 Bussard, Michael; Byron, Ken. "An Open-Source ASIC/FPGA Development
 Environment for the Altera Development System for Synchronous Programm‐
 ing Systems". In Proceedings of the IEEE/ACM International Conference on
 Computer
========================================================
example15_i-b_t-0.9.v
 1. DSelect with no Pn and in the 2nd word
 2. Abort Dm and then read data from MPC->PMP when there is no Pn then Dm
 3. Do not update PnSel,DPN,AWADDR,AWLEN,AWSIZE,AWBURST,WDATA,WSTRB,WLAST,ARADDR,ARLEN,ARSIZE,ARBURST,RD1VALID,RD2VALID,IR2VALID,IR3VALID,RD1VALID,RD2VALID,RD3VALID,RD4VALID, RD1REG,RD2REG,RD3REG,RD4REG
 4. Error when fail to find the matched Pn
 5. Read data from REG when there is no Pn
 6. Fixed Register
 7. Only support prot_access_type (CPU/J
========================================================
example16_i-b_t-0.9.v
� WRShip - 30/04/2019
 CK
 WTF
�▒îçêà 0:cpp - 1
/*synth defmem_crisetc(



specify

defparam orig.ascii_in_fname = "dmem_int.hex";
defparam orig.synth_rom_fname = "dmem_int_synth.hex";



 PB/PDTrace


 Before synthesis convert ascii file to verilog $dumpvars(0, dmem_int_synth);



 GenSIM-0.7 (https:www.gensim.org)
 Copyright (C) 2017 Peter Jorden <peterj@jorden.ca>



========================================================
example17_i-b_t-0.9.v
� Define all the input ports
input();
assign reset = rst;
 All the registers controlled by either MP or PIC
input logic [DATA_WIDTH-1:0] int_ackstatus;
output logic [DATA_WIDTH-1:0] int_g_status;
 output logic [DATA_WIDTH-1:0] int_g_estatus;
output logic int_e;  (GENERAL ERROR)
output logic int_m;  (MEMORY ERROR)
input logic int_w;  (WRITE INSTRUCTION)
input logic int_r;  (READ / READ WAIT)
output logic [7:0] op;  ascii code for the opcode (only lowest 3 bits)
input logic [7:0] int_hex;  hexidec
========================================================
example18_i-b_t-0.9.v
�YD HIPERPLANES reliay balancing 
3-DINKLE: AVAILABLE TO ALL, BUT ONLY ONE IS ACTIVE AT ONE TIME
 3-DINKLE: 3-DINKLE: IF DONE REGISTER PASSING INVALID ADDRESS, MACHINE WON'T WAIT CORRECTLY
 3-DINKLE: IF DONE REGISTER PASSING VALID ADDRESS, MACHINE WILL FINISHT LITS OUTPUT. HOW LETS ASSOCIATED TOKEN REFEGER?
 3-DINKLE: HOW TO SELECT OUTPUT OF CURSOR TO ASSOCIATED TOKEN?
 3-DINKLE: TOKEN REFEGERATION
 3-DINKLE: todo: close DONE FSM, and open all request for each part to avoid DMA stop while other part the DONE
========================================================
example19_i-b_t-0.9.v
// ethics\ count\ denoue\ La\ Cont\ de\ le\ c\ v\ e\ tot\ *\ s\ r\ e\ v\ e\ c\ v\ e\ *


//// DMA Controller ////


armv8_dma_controller #(
	.DMA_CHANNEL_WIDTH(DMA_CHANNEL_WIDTH), // Specify Channel Width
	.DMA_BLOCK_WIDTH(DMA_BLOCK_WIDTH),	// Specify Block Width
	.DMA_STATUS_WIDTH(DMA_STATUS_WIDTH),// Width of Status Register	
	.DMA_CSR_WIDTH(DMA_CSR_WIDTH), // Width of Control/Status register space
	.DMA_MASTER_FIFO_W(DMA
========================================================
example0_i-c_t-0.1.v
// 1. Use a register to hold the security settings.
// 2. Use a register to hold the security settings for the DMA controller.
// 3. Use a register to hold the security settings for the PMP.
// 4. Use a register to hold the security settings for the CPU.
// 5. Use a register to hold the security settings for the PIC.
// 6. Use a register to hold the security settings for the PIC.
// 7. Use a register to hold the security settings for the PIC.
// 8. Use a register to hold the security settings for the PIC.
// 9. Use a register to hold the security settings for the PIC.
// 10. Use a register to hold the security settings for the PIC.
// 11. Use a register to hold the security settings for the PIC.
// 12. Use a register to hold the security settings for the PIC.

========================================================
example1_i-c_t-0.1.v
// 1. Use a register to hold the security settings.
// 2. Use a register to hold the security settings for the DMA controller.
// 3. Use a register to hold the security settings for the PMP.
// 4. Use a register to hold the security settings for the CPU.
// 5. Use a register to hold the security settings for the PIC.
// 6. Use a register to hold the security settings for the PIC.
// 7. Use a register to hold the security settings for the PIC.
// 8. Use a register to hold the security settings for the PIC.
// 9. Use a register to hold the security settings for the PIC.
// 10. Use a register to hold the security settings for the PIC.
// 11. Use a register to hold the security settings for the PIC.
// 12. Use a register to hold the security settings for the PIC.

========================================================
example2_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings for the DMA controller.
 3. Use a register to hold the security settings for the PMP.
 4. Use a register to hold the security settings for the AXI slave.
 5. Use a register to hold the security settings for the AXI master.
 6. Use a register to hold the security settings for the AXI master.
 7. Use a register to hold the security settings for the AXI master.
 8. Use a register to hold the security settings for the AXI master.
 9. Use a register to hold the security settings for the AXI master.
 10. Use a register to hold the security settings for the AXI master.
 11. Use a register to hold the security settings for the AXI master.
 12. Use a register to hold
========================================================
example3_i-c_t-0.1.v
 1. Use a logic block to assign the reset value to the register.
 2. Use a logic block to assign the reset value to the register.
 3. Use a logic block to assign the reset value to the register.
 4. Use a logic block to assign the reset value to the register.
 5. Use a logic block to assign the reset value to the register.
 6. Use a logic block to assign the reset value to the register.
 7. Use a logic block to assign the reset value to the register.
 8. Use a logic block to assign the reset value to the register.
 9. Use a logic block to assign the reset value to the register.
 10. Use a logic block to assign the reset value to the register.
 11. Use a logic block to assign the reset value to the register.
 12. Use a logic block to assign the reset value to
========================================================
example4_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use the register to hold the security settings on reset.
 3. Use the register to hold the security settings on write.
 4. Use the register to hold the security settings on read.
 5. Use the register to hold the security settings on start.
 6. Use the register to hold the security settings on done.
 7. Use the register to hold the security settings on abort.
 8. Use the register to hold the security settings on command.
 9. Use the register to hold the security settings on command.
 10. Use the register to hold the security settings on command.
 11. Use the register to hold the security settings on command.
 12. Use the register to hold the security settings on command.
 13. Use the register to hold the security settings on command.
 14. Use the register to
========================================================
example5_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings for the DMA controller.
 3. Use a register to hold the security settings for the PMP.
 4. Use a register to hold the security settings for the DMA controller.
 5. Use a register to hold the security settings for the PMP.
 6. Use a register to hold the security settings for the DMA controller.
 7. Use a register to hold the security settings for the PMP.
 8. Use a register to hold the security settings for the DMA controller.
 9. Use a register to hold the security settings for the PMP.
 10. Use a register to hold the security settings for the DMA controller.
 11. Use a register to hold the security settings for the PMP.
 12. Use a register to hold the security settings for
========================================================
example6_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings for the DMA controller.
 3. Use a register to hold the security settings for the PMP.
 4. Use a register to hold the security settings for the PIC.
 5. Use a register to hold the security settings for the PIC.
 6. Use a register to hold the security settings for the PIC.
 7. Use a register to hold the security settings for the PIC.
 8. Use a register to hold the security settings for the PIC.
 9. Use a register to hold the security settings for the PIC.
 10. Use a register to hold the security settings for the PIC.
 11. Use a register to hold the security settings for the PIC.
 12. Use a register to hold the security settings for the PIC.
========================================================
example7_i-c_t-0.1.v
 1. Use a default value for the register holding the security settings.
 2. Use a default value for the register holding the security settings.
 3. Use a default value for the register holding the security settings.
 4. Use a default value for the register holding the security settings.
 5. Use a default value for the register holding the security settings.
 6. Use a default value for the register holding the security settings.
 7. Use a default value for the register holding the security settings.
 8. Use a default value for the register holding the security settings.
 9. Use a default value for the register holding the security settings.
 10. Use a default value for the register holding the security settings.
 11. Use a default value for the register holding the security settings.
 12. Use a default value for the register holding the security settings.
 13. Use a default value for
========================================================
example8_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example9_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example10_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example11_i-c_t-0.1.v
 1. Use a register to hold the security sensitive values.
 2. Use a register to hold the security sensitive values.
 3. Use a register to hold the security sensitive values.
 4. Use a register to hold the security sensitive values.
 5. Use a register to hold the security sensitive values.
 6. Use a register to hold the security sensitive values.
 7. Use a register to hold the security sensitive values.
 8. Use a register to hold the security sensitive values.
 9. Use a register to hold the security sensitive values.
 10. Use a register to hold the security sensitive values.
 11. Use a register to hold the security sensitive values.
 12. Use a register to hold the security sensitive values.
 13. Use a register to hold the security sensitive values.
 14. Use a register to hold the security sensitive values.
 15. Use
========================================================
example12_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings for the DMA controller.
 3. Use a register to hold the security settings for the PMP.
 4. Use a register to hold the security settings for the DMA controller.
 5. Use a register to hold the security settings for the PMP.
 6. Use a register to hold the security settings for the DMA controller.
 7. Use a register to hold the security settings for the PMP.
 8. Use a register to hold the security settings for the DMA controller.
 9. Use a register to hold the security settings for the PMP.
 10. Use a register to hold the security settings for the DMA controller.
 11. Use a register to hold the security settings for the PMP.
 12. Use a register to hold the security settings for
========================================================
example13_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example14_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings for the DMA controller.
 3. Use a register to hold the security settings for the PMP.
 4. Use a register to hold the security settings for the PIC.
 5. Use a register to hold the security settings for the PIC.
 6. Use a register to hold the security settings for the PIC.
 7. Use a register to hold the security settings for the PIC.
 8. Use a register to hold the security settings for the PIC.
 9. Use a register to hold the security settings for the PIC.
 10. Use a register to hold the security settings for the PIC.
 11. Use a register to hold the security settings for the PIC.
 12. Use a register to hold the security settings for the PIC.
========================================================
example15_i-c_t-0.1.v
 1. Use a logic block to assign the reset value to the registers.
 2. Use a logic block to assign the reset value to the registers.
 3. Use a logic block to assign the reset value to the registers.
 4. Use a logic block to assign the reset value to the registers.
 5. Use a logic block to assign the reset value to the registers.
 6. Use a logic block to assign the reset value to the registers.
 7. Use a logic block to assign the reset value to the registers.
 8. Use a logic block to assign the reset value to the registers.
 9. Use a logic block to assign the reset value to the registers.
 10. Use a logic block to assign the reset value to the registers.
 11. Use a logic block to assign the reset value to the registers.
 12. Use a logic block to assign the reset value to
========================================================
example16_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example17_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings for the DMA controller.
 3. Use a register to hold the security settings for the PMP.
 4. Use a register to hold the security settings for the PIC.
 5. Use a register to hold the security settings for the PIC.
 6. Use a register to hold the security settings for the PIC.
 7. Use a register to hold the security settings for the PIC.
 8. Use a register to hold the security settings for the PIC.
 9. Use a register to hold the security settings for the PIC.
 10. Use a register to hold the security settings for the PIC.
 11. Use a register to hold the security settings for the PIC.
 12. Use a register to hold the security settings for the PIC.
========================================================
example18_i-c_t-0.1.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example19_i-c_t-0.1.v
 1. Use a non-zero value for the register.
 2. Use a non-zero value for the register in the reset block.
 3. Use a non-zero value for the register in the reset block.
 4. Use a non-zero value for the register in the reset block.
 5. Use a non-zero value for the register in the reset block.
 6. Use a non-zero value for the register in the reset block.
 7. Use a non-zero value for the register in the reset block.
 8. Use a non-zero value for the register in the reset block.
 9. Use a non-zero value for the register in the reset block.
 10. Use a non-zero value for the register in the reset block.
 11. Use a non-zero value for the register in the reset block.
 12. Use a non
========================================================
example0_i-c_t-0.3.v
 1. Add a reset to the DMA controller.
 2. Assign the security settings to the registers on reset.
 3. Assign the security settings to the registers on DMA request.
 4. Assign the security settings to the registers on DMA complete.
 5. Assign the security settings to the registers on DMA error.
 6. Assign the security settings to the registers on DMA abort.
 7. Assign the security settings to the registers on DMA done.
 8. Assign the security settings to the registers on DMA done.
 9. Assign the security settings to the registers on DMA done.
 10. Assign the security settings to the registers on DMA done.
 11. Assign the security settings to the registers on DMA done.
 12. Assign the security settings to the registers on DMA done.
 13
========================================================
example1_i-c_t-0.3.v
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example2_i-c_t-0.3.v
 1) Assign a value to the register on reset.
 2) Assign the value to the register on the next clock cycle.
 3) Assign the value to the register on the next clock cycle.
 4) Assign the value to the register on the next clock cycle.
 5) Assign the value to the register on the next clock cycle.
 6) Assign the value to the register on the next clock cycle.
 7) Assign the value to the register on the next clock cycle.
 8) Assign the value to the register on the next clock cycle.
 9) Assign the value to the register on the next clock cycle.
 10) Assign the value to the register on the next clock cycle.
 11) Assign the value to the register on the next clock cycle.
 12) Assign the value to the register on the next clock cycle.
========================================================
example3_i-c_t-0.3.v
 1. Use a non-blocking reset to initialize the registers holding security settings.
 2. Use a synchronous reset to initialize the registers holding security settings.
 3. Use an asynchronous reset to initialize the registers holding security settings.
 4. Use a non-blocking reset to initialize the registers holding security settings.
 5. Use a synchronous reset to initialize the registers holding security settings.
 6. Use an asynchronous reset to initialize the registers holding security settings.
 7. Use a non-blocking reset to initialize the registers holding security settings.
 8. Use a synchronous reset to initialize the registers holding security settings.
 9. Use an asynchronous reset to initialize the registers holding security settings.
 10. Use a non-blocking reset to initialize the registers holding security settings.
 11. Use a synchronous reset to initialize the registers holding security settings.
 12. Use an asynchronous reset to initialize the registers holding
========================================================
example4_i-c_t-0.3.v
 1. Make sure that the reset value is a valid security setting.
 2. Make sure that the reset value is not a security sensitive value.
 3. Make sure that the reset value is not the same as the reset value on the next reset.
 4. Make sure that the reset value is not the same as the value on the next reset.
 5. Make sure that the reset value is not the same as the value on the next reset.
 6. Make sure that the reset value is not the same as the value on the next reset.
 7. Make sure that the reset value is not the same as the value on the next reset.
 8. Make sure that the reset value is not the same as the value on the next reset.
 9. Make sure that the reset value is not the same as the value on the next reset.
 10. Make sure that the reset value is not the
========================================================
example5_i-c_t-0.3.v
 1. Use a register to hold the security settings.
 2. Use a register to hold the security settings.
 3. Use a register to hold the security settings.
 4. Use a register to hold the security settings.
 5. Use a register to hold the security settings.
 6. Use a register to hold the security settings.
 7. Use a register to hold the security settings.
 8. Use a register to hold the security settings.
 9. Use a register to hold the security settings.
 10. Use a register to hold the security settings.
 11. Use a register to hold the security settings.
 12. Use a register to hold the security settings.
 13. Use a register to hold the security settings.
 14. Use a register to hold the security settings.
 15. Use a register to hold the security settings.
 16. Use a
========================================================
example6_i-c_t-0.3.v
 1. Use the reset controller to initialize the registers holding security settings.
 2. Assign the reset controller a value for the security settings.
 3. Assign the security settings to the registers holding the security settings.
 4. Assign the security settings to the registers holding the security settings.
 5. Assign the security settings to the registers holding the security settings.
 6. Assign the security settings to the registers holding the security settings.
 7. Assign the security settings to the registers holding the security settings.
 8. Assign the security settings to the registers holding the security settings.
 9. Assign the security settings to the registers holding the security settings.
 10. Assign the security settings to the registers holding the security settings.
 11. Assign the security settings to the registers holding the security settings.
 12. Assign the security settings to the registers holding the security settings
========================================================
example7_i-c_t-0.3.v
 1. Use the 'reset' event to initialize the security sensitive registers.
 2. Remove the 'reset' event from the design.
 3. Remove the 'reset' statement from the design.
 4. Remove the 'initial' statement from the design.
 5. Remove the 'initial' statement from the 'dma_ctrl_reg' module.
 6. Remove the 'initial' statement from the 'dma_ctrl_new' module.
 7. Remove the 'initial' statement from the 'pmp_addr_reg' module.
 8. Remove the 'initial' statement from the 'pmp_addr_new' module.
 9. Remove the 'initial' statement from the 'pmp_access_type_reg' module.
 10. Remove the 'initial' statement from the 'pmp_access_type_new' module.
 11. Remove the
========================================================
example8_i-c_t-0.3.v
 1. Use a behavioral model to describe the reset value of the security registers.
 2. Use a behavioral model to describe the reset value of the security registers.
 3. Use a behavioral model to describe the reset value of the security registers.
 4. Use a behavioral model to describe the reset value of the security registers.
 5. Use a behavioral model to describe the reset value of the security registers.
 6. Use a behavioral model to describe the reset value of the security registers.
 7. Use a behavioral model to describe the reset value of the security registers.
 8. Use a behavioral model to describe the reset value of the security registers.
 9. Use a behavioral model to describe the reset value of the security registers.
 10. Use a behavioral model to describe the reset value of the security registers.
 11. Use a behavioral model to describe the reset value of the security registers.
 12
========================================================
example9_i-c_t-0.3.v
 1. Use the "assign" statement to initialize the register to a known value.
 2. Use the "always" statement to write the register value to the register whenever the value changes.
 3. Use the "always" statement to read the register value from the register whenever the value changes.
 4. Use the "always" statement to write the register value to the register whenever the value changes.
 5. Use the "always" statement to read the register value from the register whenever the value changes.
 6. Use the "always" statement to write the register value to the register whenever the value changes.
 7. Use the "always" statement to read the register value from the register whenever the value changes.
 8. Use the "always" statement to write the register value to the register whenever the value changes.
 9. Use the "always" statement to read the register value from the register whenever the
========================================================
example10_i-c_t-0.3.v
 1. Add a reset value to the security sensitive registers.
 2. Add a security sensitive register to the dmem.
 3. Ensure that the reset value is assigned to the security sensitive registers.
 4. Ensure that the reset value is not written by the dmem.
 5. Ensure that the reset value is not read by the dmem.
 6. Ensure that the reset value is not written by the dmem.
 7. Ensure that the reset value is not read by the dmem.
 8. Ensure that the reset value is not written by the dmem.
 9. Ensure that the reset value is not read by the dmem.
 10. Ensure that the reset value is not written by the dmem.
 11. Ensure that the reset value is not read by the dmem.
 12. Ensure that the reset value is not written by the dmem.
 13
========================================================
example11_i-c_t-0.3.v
 1. Use a register to hold the security settings
 2. Make sure that the register is initialized on reset
 3. Make sure that the register is not written to until the security settings have been verified
 4. Use a flag to indicate that the security settings have been verified.
 5. Use a register to hold the security setting values
 6. Make sure that the register is initialized on reset
 7. Make sure that the register is not written to until the security settings have been verified
 8. Use a flag to indicate that the security settings have been verified.
 9. Use a register to hold the security setting values
 10. Make sure that the register is initialized on reset
 11. Make sure that the register is not written to until the security settings have been verified
 12. Use a flag to indicate that the security settings have been verified.
 13. Use a register to hold the security setting values
========================================================
example12_i-c_t-0.3.v
// 1. Use a default value for the security sensitive registers.
// 2. Use a default value for the security setting register.
// 3. Use a default value for the DMA control register.
// 4. Use a default value for the DMA status register.
// 5. Use a default value for the DMA status register.
// 6. Use a default value for the DMA done register.
// 7. Use a default value for the DMA done interrupt register.
// 8. Use a default value for the DMA error register.
// 9. Use a default value for the DMA error interrupt register.
// 10. Use a default value for the DMA status register.
// 11. Use a default value for the DMA status interrupt register.
// 12. Use a default value for the DMA status interrupt enable register.
// 13. Use a default value for the DMA status interrupt clear register.

========================================================
example13_i-c_t-0.3.v
 - Need to make sure that the reset values are correct.
 - Need to make sure that the reset values are assigned correctly.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are assigned only once.
 - Need to make sure that the reset values are
========================================================
example14_i-c_t-0.3.v
 1. Use a register to hold the security settings.
 2. Assign the security settings to the register on reset.
 3. Use a logic block to assign the register to the security settings on the
 first clock cycle after reset.
 4. Use a logic block to assign the register to the security settings on the
 first clock cycle after reset.
 5. Use a logic block to assign the register to the security settings on the
 first clock cycle after reset.
 6. Use a logic block to assign the register to the security settings on the
 first clock cycle after reset.
 7. Use a logic block to assign the register to the security settings on the
 first clock cycle after reset.
 8. Use a logic block to assign the register to the security settings on the
 first clock cycle after reset.
 9. Use a logic block to assign the register to the security settings on
========================================================
example15_i-c_t-0.3.v
 1. Assign the default value to the registers.
 2. Enable the register only when the DMA is enabled.
 3. Enable the register only when the DMA is not in the IDLE state.
 4. Enable the register only when the DMA is not in the IDLE state and the DMA controller is enabled.
 5. Enable the register only when the DMA is not in the IDLE state and the DMA controller is enabled and the DMA is in the LOAD state.
 6. Enable the register only when the DMA is not in the IDLE state and the DMA controller is enabled and the DMA is in the LOAD state and the DMA is in the CHECK state.
 7. Enable the register only when the DMA is not in the IDLE state and the DMA controller is enabled and the DMA is in the LOAD state and the DMA is in
========================================================
example16_i-c_t-0.3.v
 1. Use a 'reset' signal to set the security registers to a known value.
 2. Ensure that the reset value is not sensitive.
 3. Use a 'set' signal to set the security registers to a known value.
 4. Ensure that the set value is not sensitive.
 5. Use a 'clr' signal to clear the security registers.
 6. Ensure that the clr signal is not sensitive.
 7. Use a 'set' signal to set the security registers to a known value.
 8. Ensure that the set value is not sensitive.
 9. Use a 'clr' signal to clear the security registers.
 10. Ensure that the clr signal is not sensitive.
 11. Use a 'set' signal to set the security registers to a known value.
 12. Ensure that the set value is not sensitive.
 13. Use a '
========================================================
example17_i-c_t-0.3.v
 1. Use a register to hold the security sensitive values.
 2. Use a register to hold the security sensitive values.
 3. Use a register to hold the security sensitive values.
 4. Use a register to hold the security sensitive values.
 5. Use a register to hold the security sensitive values.
 6. Use a register to hold the security sensitive values.
 7. Use a register to hold the security sensitive values.
 8. Use a register to hold the security sensitive values.
 9. Use a register to hold the security sensitive values.
 10. Use a register to hold the security sensitive values.
 11. Use a register to hold the security sensitive values.
 12. Use a register to hold the security sensitive values.
 13. Use a register to hold the security sensitive values.
 14. Use a register to hold the security sensitive values.
 15. Use
========================================================
example18_i-c_t-0.3.v
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example19_i-c_t-0.3.v
 1) Assign a default value to the registers holding security settings.
 2) Assign the security settings to the registers based on the security_enable flag.
 3) Assign the security settings to the registers based on the security_enable flag.
 4) Assign the security settings to the registers based on the security_enable flag.
 5) Assign the security settings to the registers based on the security_enable flag.
 6) Assign the security settings to the registers based on the security_enable flag.
 7) Assign the security settings to the registers based on the security_enable flag.
 8) Assign the security settings to the registers based on the security_enable flag.
 9) Assign the security settings to the registers based on the security_enable flag.
 10) Assign the security settings to the registers based on the security_enable flag.
 11) Ass
========================================================
example0_i-c_t-0.5.v
 1. Remove the pmp_access_type_reg.
 2. Remove the pmp_access_type_en.
 3. Remove the pmp_access_type_en_rst.
 4. Remove the pmp_access_type_new.
 5. Remove the pmp_access_type_new_rst.
 6. Remove the pmp_access_type_reg_rst.
 7. Remove the pmp_access_type_en_rst.
 8. Remove the pmp_access_type_en_rst.
 9. Remove the pmp_access_type_en_rst.
 10. Add a pmp_access_type_en_rst.
 11. Add a pmp_access_type_en_rst.
 12. Add a pmp_access_type
========================================================
example1_i-c_t-0.5.v
 1. Create a new register for holding the security settings.
 2. Make sure that the reset value is set to a known value.
 3. Make sure that the reset value is updated correctly.
 4. Make sure that the reset value is updated only when the DMA is disabled.
 5. Make sure that the reset value is updated only when the register is enabled.
 6. Make sure that the reset value is updated only when the register is enabled but not enabled by the DMA.
 7. Make sure that the reset value is updated only when the register is enabled but not enabled by the DMA.
 8. Make sure that the reset value is updated only when the register is enabled but not enabled by the DMA.
 9. Make sure that the reset value is updated only when the register is enabled but not enabled by the DMA.
 10. Make sure that the reset value is updated only
========================================================
example2_i-c_t-0.5.v
// 1. Use a "comb" to initialize the register to the default value on reset.
// 2. Use a "comb" to initialize the register to the default value on reset.
// 3. Use a "comb" to initialize the register to the default value on reset.
// 4. Use a "comb" to initialize the register to the default value on reset.
// 5. Use a "comb" to initialize the register to the default value on reset.
// 6. Use a "comb" to initialize the register to the default value on reset.
// 7. Use a "comb" to initialize the register to the default value on reset.
// 8. Use a "comb" to initialize the register to the default value on reset.
// 9. Use a "comb" to initialize the register to the default value on reset.
// 10. Use a "comb" to initialize the register to the default value on reset.

========================================================
example3_i-c_t-0.5.v
 1. Save the security settings in a temp register and assign it to the security settings register.
 2. Assign the security settings register to the security settings register on reset.
 3. Assign the temp register to the security settings register on reset.
 4. Assign the security settings register to the security settings register on next cycle.
 5. Assign the temp register to the security settings register on next cycle.
 6. Assign the security settings register to the temp register on next cycle.
 7. Assign the temp register to the security settings register on next cycle.
 8. Assign the security settings register to the temp register on next cycle.
 9. Assign the temp register to the security settings register on next cycle.
 10. Assign the security settings register to the temp register on next cycle.
 11. Assign the temp register to the security settings register on next cycle.
========================================================
example4_i-c_t-0.5.v
 1) pmp_access_type_en should be assigned to 0 on reset.
 2) pmp_addr_en should be assigned to 0 on reset.
 3) pmp_addr_reg should be assigned to 0 on reset.
 4) pmp_addr_en should be assigned to 0 on reset.
 5) pmp_access_type_reg should be assigned to 0 on reset.
 6) pmp_access_type_en should be assigned to 0 on reset.
 7) pmp_addr_reg should be assigned to 0 on reset.
 8) pmp_addr_en should be assigned to 0 on reset.
 9) pmp_access_type_reg should be assigned to 0 on reset.
 10) pmp_access_type_en should be assigned to 0 on reset.
 11) pmp_addr_reg should
========================================================
example5_i-c_t-0.5.v
// 1. Change the reset value of the registers to a known value.
// 2. Update the reset function to read the register value and then assign a 
// reset value.
// 3. Ensure the registers holding security settings are initialized to a known 
// value on reset.
// 4. Update the reset function to write the security register values to the 
// registers.
// 5. Remove the assignment of the reset value to the registers holding security 
// settings.



//
// Design Name:
//
// Module Name:
//
// Function:
//
// Design Description:
//
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////

module dma
#(
parameter DATA_WIDTH = 64,
parameter ADDR_WIDTH = 16,
param
========================================================
example6_i-c_t-0.5.v
 1. Assign security settings to zero on reset.
 2. Change all security settings to zero on reset.
 3. Change all security settings to zero on reset.
 4. Assign security settings to zero on reset.
 5. Assign security settings to zero on reset.
 6. Assign security settings to zero on reset.
 7. Assign security settings to zero on reset.
 8. Assign security settings to zero on reset.
 9. Assign security settings to zero on reset.
 10. Assign security settings to zero on reset.
 11. Assign security settings to zero on reset.
 12. Assign security settings to zero on reset.
 13. Assign security settings to zero on reset.
 14. Assign security settings to zero on reset.
 15. Assign security settings to zero on reset.
 16. Assign
========================================================
example7_i-c_t-0.5.v
 Once the security settings are available, the initial values for the registers
 holding security settings can be assigned at the time the module is instantiated.
 The module can then be enabled.
 The module can then be enabled by writing to the DMA control register.
 The module can then be disabled by writing to the DMA control register and 
 setting the disable bit.
 The module can then be disabled by writing to the DMA control register and 
 setting the enable bit to zero.
 The module can then be enabled by writing to the DMA control register and 
 setting the enable bit.
 The module can then be enabled by writing to the DMA control register and 
 setting the start bit.
 The module can then be enabled by writing to the DMA control register and 
 setting the start bit.
 Finally, the module can be disabled by writing to the DMA control
========================================================
example8_i-c_t-0.5.v
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========================================================
example9_i-c_t-0.5.v
 1. We should enforce that the reset value for the security sensitive registers
 is not a 0. Not doing so will allow data to be written to those registers.
 2. We should set the reset value to 0 for all registers that are security
 sensitive. This will allow the reset value to be 0 in the case that the
 reset value is assigned to a register that is not security sensitive.
 3. We should set the reset value to 0 for all registers that are security
 sensitive. This will allow the reset value to be 0 in the case that the
 reset value is assigned to a register that is not security sensitive.
 4. We should set the reset value to 0 for all registers that are security
 sensitive. This will allow the reset value to be 0 in the case that the
 reset value is assigned to a register that is not security sensitive.
 5. We should set the reset value to 0
========================================================
example10_i-c_t-0.5.v
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========================================================
example11_i-c_t-0.5.v
// 1. Use a function to initialize the security sensitive registers to a known value on reset.
// 2. Use a function to initialize the security sensitive registers to a known value on reset.
// 3. Use a function to initialize the security sensitive registers to a known value on reset.
// 4. Use a function to initialize the security sensitive registers to a known value on reset.
// 5. Use a function to initialize the security sensitive registers to a known value on reset.
// 6. Use a function to initialize the security sensitive registers to a known value on reset.
// 7. Use a function to initialize the security sensitive registers to a known value on reset.
// 8. Use a function to initialize the security sensitive registers to a known value on reset.
// 9. Use a function to initialize the security sensitive registers to a known value on reset.
// 10. Use a function to initialize the security sensitive registers to a known value on reset.

========================================================
example12_i-c_t-0.5.v
 1. Add a register to hold the security settings to be set on reset.
 2. Assign the register the value of the "sec_cfg" signal.
 3. Assign the register the value of the "sec_enable" signal.
 4. Assign the register the value of the "pmp_sec_latch" signal.
 5. Assign the register the value of the "pmp_enable" signal.
 6. Assign the register the value of the "pmp_write" signal.
 7. Assign the register the value of the "pmp_read" signal.
 8. Assign the register the value of the "pmp_addr" signal.
 9. Assign the register the value of the "pmp_data" signal.
 10. Assign the register the value of the "pmp_be" signal.

========================================================
example13_i-c_t-0.5.v
 1. Create a new reg to hold the security setting.
 2. Create a new fsm to read the security setting and to write the new security setting.
 3. Create a new fsm to read the security setting and to write the new security setting.
 4. Create a new fsm to read the security setting and to write the new security setting.
 5. Create a new fsm to read the security setting and to write the new security setting.
 6. Create a new fsm to read the security setting and to write the new security setting.
 7. Create a new fsm to read the security setting and to write the new security setting.
 8. Create a new fsm to read the security setting and to write the new security setting.
 9. Create a new fsm to read the security setting and to write the new security setting.
 10. Create a new fsm to read
========================================================
example14_i-c_t-0.5.v
// - Make the security registers read-only.
// - Make the security registers reset to a known value on reset.
// - Do not allow the security registers to be written to until the DMA is
// disabled.
// - The security registers should be reset when the DMA is disabled.
// - The security registers should not be written to by the user.
// - The security registers should be clocked to the bus clock domain.
// - The security registers should be clocked to the parent clock domain.
// - The security registers should be synchronized to the bus clock domain.
// - The security registers should be synchronized to the parent clock domain.
// - The security registers should be synchronized to the bus clock domain.
// - The security registers should be synchronized to the parent clock domain.
// - The security registers should be synchronized to the bus clock domain.


// - The security registers should be synchronized to the bus clock domain
========================================================
example15_i-c_t-0.5.v
 1. Assign the reset value for the security sensitive registers. 
 2. Assign the reset value for the security sensitive registers. 
 3. Assign the security sensitive registers with a default value. 
 4. Assign the security sensitive registers with a default value. 
 5. Assign the security sensitive registers with a default value. 
 6. Assign the security sensitive registers with a default value. 
 7. Assign the security sensitive registers with a default value. 
 8. Assign the security sensitive registers with a default value. 
 9. Assign the security sensitive registers with a default value. 
 10. Assign the security sensitive registers with a default value. 
 11. Assign the security sensitive registers with a default value. 
 12. Assign the security sensitive registers with a default value. 
 13. Assign the security sensitive
========================================================
example16_i-c_t-0.5.v
//� Reset logic to initialize registers holding security settings.

//`define PMP_ACCESS_WRITE
//`define PMP_ACCESS_READ
`define PMP_ACCESS_TYPE_WRITE
`define PMP_ACCESS_TYPE_READ

//`define PMP_ACCESS_TYPE_ENABLE

//`define PMP_CACHE_DISABLE
//`define PMP_CACHE_ENABLE
//`define PMP_CACHE_WRITE_THROUGH

//`define PMP_CACHE_WRITE_BACK
//`define PMP_CACHE_WRITE_THROUGH

//`define PMP_CACHE_ENABLE
//`define PMP_CACHE_ENABLE_ALL
//`define PMP_CACHE_INIT_ZERO

//
========================================================
example17_i-c_t-0.5.v
 The following code is commented out because it is not currently used.





























































































========================================================
example18_i-c_t-0.5.v
// 1) pmp_access_type_en should be removed.
// 2) pmp_access_type_new should be assigned a value on reset.
// 3) pmp_access_type_en should be assigned a value on reset.
// 4) pmp_access_type_reg should be removed.
// 5) pmp_access_type_en should be removed.
assign pmp_access_type_en = 1'b1;
assign pmp_access_type_reg = 1'b1;
assign pmp_access_type_new = 1'b1;
assign pmp_access_type_new = 1'b1;

always @* begin
//pmp_access_type_en = pmp_access_type_reg;
pmp_access_type_en = pmp_access_type_new;
end

========================================================
example19_i-c_t-0.5.v
 1. Check if the reset value is 0. If so, assign a different value.
 2. Check if the reset value is 'x'. If so, assign a different value.
 3. Check if the reset value is 'z'. If so, assign a different value.
 4. Check if the reset value is 'Z'. If so, assign a different value.
 5. Check if the reset value is 'z'. If so, assign a different value.
 6. Check if the reset value is 'Z'. If so, assign a different value.
 7. Check if the reset value is '0'. If so, assign a different value.
 8. Check if the reset value is '0'. If so, assign a different value.
 9. Check if the reset value is ' ' (blank). If so, assign a different value.
 10. Check if the reset value is '
========================================================
example0_i-c_t-0.7.v
// The register may need to be initialized on the reset condition.
// The following implementation is to prevent any operations on the registers
// in the event that the reset condition happens before the registers are
// fully initialized.
// See "RSTACT" in the "mf_usb3_rx" directory.
always @ (posedge clk_i) begin
	if (reset_i == 1'b1) begin
	
end

end

========================================================
example1_i-c_t-0.7.v
// ALWAYS @(posedge clk_i) begin
// pmp_access_type_reg <= pmp_access_type_new;
// end
// ALWAYS @(posedge clk_i) begin
// pmp_addr_reg <= pmp_addr_new;
// end
// ALWAYS @(posedge clk_i) begin
// pmp_access_type_en <= pmp_access_type_new;
// end
// ALWAYS @(posedge clk_i) begin
// pmp_addr_en <= pmp_addr_new;
// end



//// Outputs
//�pmp_access_type_i inp_i[0:1]
//
// ALWAYS @(posedge clk_i) begin
// done_d <= done_i;
// end
// ALWAYS @(posedge clk_i
========================================================
example2_i-c_t-0.7.v
// ALWAYS @ (posedge clk_i)
// if (rst_i)
// begin
// pmp_access_type_reg <= riscv::ACCESS_NONE;
// end
// else
// begin
// pmp_access_type_reg <= pmp_access_type_new;
// pmp_access_type_en <= 1'b1;
// end
// ALWAYS @ (posedge clk_i)
// if (rst_i)
// pmp_access_type_en <= 0;
// else
// pmp_access_type_en <= pmp_access_type_change;


// BUG: 382 Uninitialized Value on Reset for Registers Holding Security Settings.
// ALWAYS @ (posedge clk_i)
// if (rst_i)
// begin
// pmp_addr_
========================================================
example3_i-c_t-0.7.v
//
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========================================================
example4_i-c_t-0.7.v
// This is necessary for the initial stage of the reset
// to ensure that the value from SDR_CTRL_REG is set before the
// security registers are checked.
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
	if (rst_i == `TRUE)
	begin
	
	
end

end

========================================================
example5_i-c_t-0.7.v
 1. This could be accomplished by assigning a value to the reset sensitive registers by default.
 2. In the event that the reset does not occur, then the user can always reset the module to the default value.
 3. Resetting the module will cause an initial value to be assigned to the registers which were not addressed.
 4. The user can change the security settings by writing to their respective registers.
 5. The security settings will be checked everytime the module is enabled.
 6. If the user changes the settings, a reset must be issued to transfer the new settings to the module.
 7. The reset must be issued externally, or by the module itself.
 8. The module can be reset by issuing a software reset.
 9. Once the module is reset, the user can reset the security settings by writing to the registers.
 10. The security settings will be checked and the user will be
========================================================
example6_i-c_t-0.7.v
//Assert reset for registers that are not already initialized.
script_mem_reset reset_reg;

//---------------------------------LITE---------------------------------------------------------

assign lite_arw_valid = arw_valid_i;
assign lite_arw_payload_addr = arw_payload_addr;
assign lite_arw_payload_id = arw_payload_id;
assign lite_arw_payload_len = arw_payload_len;
assign lite_arw_payload_size = arw_payload_size;
assign lite_arw_payload_burst = arw_payload_burst;
assign lite_arw_payload_write = arw_payload_write;
assign lite_wdata = arw_payload_data;

========================================================
example7_i-c_t-0.7.v
 The security settings are not being saved on reset. This can be fixed by
 removing the security settings from the design.
�
 ==============================================================================
 
 Verilog Testbench 

 ==============================================================================










































































========================================================
example8_i-c_t-0.7.v
// 1. Register the reset value of the pmp_access_type so that it can be written back on reset.
// 2. Assign the reset value of the pmp_access_type to the pmp_access_type_reg.
// 3. Assign the pmp_access_type_new to the pmp_access_type_reg only when pmp_access_type_en is 1'b1.

// DONE: output
// BUG: Unimplemented Verilog Code for rvfi
// rvfi::register_t rvfi_register;

// BUG: Unimplemented Verilog Code for riscv_debug_module
// riscv_debug_module riscv_debug_module(
// );

// BUG: Unimplemented Verilog Code for riscv_debug_module_tb
========================================================
example9_i-c_t-0.7.v
// WARNING: The following section contains security critical code. Please review these sections before modifying or removing.
// 
// This section of code contains the security system configuration check logic.
// The current implementation is a stub and should be completed according to the design document
/*
gates
*/
/**
* Gates for each stage of the DMA controller.
*/
// Stage 1
// Inputs from outside the design
assign done_d = done_i;
assign valid_o = valid_i;
// Gates for internal data path
assign we_d = we_i;
assign wre_d = wre_i;
assign gnt_d = gnt_i;
assign grr_d = grr_i;
assign dma_ctrl_en_d = dma_ctrl_en;
assign dma_ctrl_wr_d = dma_
========================================================
example10_i-c_t-0.7.v
// This should be handled by the riscv core.
// This logic should be removed from this module.
// However, the core currently has no way to determine what security state is
// being requested by the application.
// The core should be changed to handle this value.
always @(posedge clk_i) begin
	if (rst_i == 1'b1) begin
	//assign pmp_access_type_en = 1'b0;
	//pmp_access_type_reg = 0;
	
end

end

========================================================
example11_i-c_t-0.7.v
 Whoever inserted this module was obviously not a security expert.
 These settings are very sensitive and need to be set correctly.
 They must be set to allow access to all of the DMP memory by default.
 It is not possible to add/remove memory segments by adding/removing
 the [DMP_SRC_ID_WIDTH-1:0] field in the segment command.
 The DMP core will ignore all segments with this field set to the
 reserved [7:0] value and will assign all DMP memory as a continuous
 block.
 
 DMP memory accesses are allowed.
 The security sensitive registers must be assigned a value in the first
 DMP segment, which must not be removed.
 The DMP core will ignore all segments with the reserved [DMP_SRC_ID_WID
========================================================
example12_i-c_t-0.7.v
 1) dma_ctrl_reg should be assigned a value on reset, if DMA is enabled.
 2) pmp_access_type_reg should be assigned a value on reset, if the DMA is enabled.
 3) pmp_access_type_en_reg should be assigned a value on reset, if the DMA is enabled.
 4) pmp_addr_reg should be assigned a value on reset, if the DMA is enabled.
 5) pmp_addr_en_reg should be assigned a value on reset, if the DMA is enabled.
 6) pmp_data_reg should be assigned a value on reset, if the DMA is enabled.
 7) pmp_wr_mask_reg should be assigned a value on reset, if the DMA is enabled.
 8) pmp_wr_data_reg should be assigned a value
========================================================
example13_i-c_t-0.7.v
//�
reg [1:0] generate_done_reg = 2'b00;
always @ (negedge rst_n or posedge clk)
begin
	if (rst_n == 0)
	begin
	
end

end

========================================================
example14_i-c_t-0.7.v
// proprietorship is determined by the address of the security sensitive registers
// if the security settings are not initialized, the proprietary code is the default.
// if the security settings are initialized, the proprietary code is enabled based on the
// address of the security settings registers.

// The proprietary code is enabled if the address is 0x00007ff0
// and is disabled if the address is 0x0000fff0
// if the address is in between, then proprietary code is disabled.
// security_enable_i is the security bit enable from the DMA config register
// pmp_addr_i is the address of the register that we want to write to
// security_enable_o is the security bit to be written to that register

systolic
systolic_module altera_merlin_multiplexer_impl("altera_merlin_multiplexer_impl",
	clk, 
	
========================================================
example15_i-c_t-0.7.v
// 1. Assign a default value to the registers on reset.
// 2. Modify the initialization of register security_enable to also
// take this default value into account.
// 3. Modify the initialization statement that does register assignment to
// set the security_enable register to the default value.
// 4. Initialize the security_enable register to the proper value after
// the registers have been assigned their default values.
// 5. Modify the output sensitivity list to only drive the security_enable
// register.
assign pmp_access_type = (pmp_access_type_reg == riscv_macro_jtag_read_tck ? riscv_macro_jtag_read_tck: riscv_macro_jtag_write_tck);
assign pmp_address = pmp_addr_reg;
assign pmpcfg_
========================================================
example16_i-c_t-0.7.v
// Ensure that the security sensitive access registers are assigned a value on reset.
// *** debug code
// Assign security_access_mode = pmp_access_type_reg;
// Assign security_access_mode = pmp_access_type_en;
// *** debug code
// *** debug code
// *** debug code
// Assign security_access_mode = (pmp_access_type_reg || pmp_access_type_en) ? pmp_access_type_reg : riscv_reserved_access;
// *** debug code
// *** debug code
// *** debug code
assign security_access_mode = (pmp_access_type_reg || pmp_access_type_en) ? pmp_access_type_reg : riscv_reserved_access;

always @(posedge clk_i or negedge rst
========================================================
example17_i-c_t-0.7.v
// The reset value of the security sensitive registers is unpredictable.
// It is best not to have this value hardcoded into the design.
logic [CTRL_WIDTH-1:0] dma_ctrl_reg_default;

// The dma_ctrl_reg_default value takes on the value of the DMA_CTRL
// register at hardware reset. The default value is updated from
// the configuration file.
assign dma_ctrl_reg = dma_ctrl_reg_default;

logic [CTRL_WIDTH-1:0] dma_ctrl_reg_temp;

logic [CTRL_WIDTH-1:0] dma_ctrl_reg_new;

logic [CTRL_WIDTH-1:0] dma_ctrl_en;

logic [CTRL_WIDTH-1
========================================================
example18_i-c_t-0.7.v
 The source and destination addresses are handled within the dma controller and
 should not be assigned a default value.
 
 Initialize some default values for the registers that hold the security settings.
 These values are mapped to the security setting values for the DMA controller.
 The DMA controller should handle the mapping of these settings to the actual
 values on the DMA request.
 
 The DMA controller sets the security bits on the request before the request
 is sent to the slave.
 
 These values are not assigned a default value on reset because the reset values
 are provided by the design configuration.
 
 The reset implementation assigns the reset value for the security bits.
 
 The values are also not assigned default values when the slave goes to the
 idle state because the slave is likely in a different state than the DMA
 controller.
 
========================================================
example19_i-c_t-0.7.v
 Access registers (or logic gates) need to be clocked by the system clock.
 Security settings are written by user application when DMA is not active.
 Security settings are read by user application when DMA is active.
 The values of the security registers are affected by clock domain crossing.
 The values of the security registers are also affected by power-on reset.
 The values of the security registers are not affected by software reset.
 The values of the security registers are also not affected by normal operation.
 The values of the security registers are rarely, if ever, changed after a
 power-on reset.
 A reset value is hard-coded into the design.
 A normal calibration will set all registers to the values calibrated at
 program-and-erase time.
 This routine will initialize all registers to the normal-calibration
 values.
 Any saved settings will be lost
========================================================
example0_i-c_t-0.9.v
// - Set to zero until reset begins and wait statement is removed. Only keep
// a value if it is part of startup or completely disabled.
// - Set to "write" on first write, set to "read" on next read until reset.
// Once complete, in DONE state. Keep setting to "read" or "write".
// DONE state:
// - Either output is valid. The requested set of data is valid. If a write, hold
// the output and repeat the write. If a read, repeat the read.

henko assetSECURE state_reg;

missionsystem_defparam system_inst_name.FREQUENCY = "50"; 
missionsystem_defparam system_inst_name.IDLE = "IDLE";
missionsystem_defparam system_inst_name.log2_numwords = 13;
missionsystem_defparam system_inst_name.
========================================================
example1_i-c_t-0.9.v
// Get rid of security sensitive registers and this option.
// Ensuring that the DMA/POWER-ON register has a valid value on reset.
//output
//output
// For security reasons, access to the power-on register must be wired off by default.
 
 
eredir
eredir_action_reg, eredir_action_new; // riscv::ERASE_CHIP or riscv::POWERUP
erasw
erase_chip_reg, erase_chip_new; // TODO:
// SIGNAL GEN PORT
anderand
// NUM1 NUM2 NUM3 NUM4 ...
pl_main.v
pl_pipeline.v
// TODO: GENERATE PUMP REGISTERS
// This has the other problem that signals which are generated in this file are not
//
========================================================
example2_i-c_t-0.9.v
// 1. pmp_addr_en is set when start_d is active. pmp_addr_en is also used to write to the reg when dma_ctrl_reg is assigned with new value.
// 2. pmp_addr_reg is assigned with reg value at posedge and negedge of clk
// 3. pmp_addr_en is set when done_d is active.
always @(posedge clk or negedge rst_n) begin
if(!rst_n)
pmp_addr_reg <= 'd0; 
else if(dma_ctrl_en & (&{start_d, (done_d & (~valid_d)) ^ (~valid_d)) & pmp_addr_en)
pmp_addr_reg <= pmp_addr_new; 

end

========================================================
example3_i-c_t-0.9.v
 1. Write a register initialization file pmpfgw.v to initialize all the registers of the dma. 
 2. Add verilog include statements for the module dma_ctrl_reg and dma_ctrl_fsm to the module MFGDESIGN.v
 3. Update the entity name of the DMA module from "DMA" to "pmp_store_ctrl" 
 4. Update the sim_type of the MFGDESIGN module to "nios2" 
 5. Enable the DMA_CTRL_WIDTH with the "*m" statement for compile. 
 6. Run the simulation after reloading the IP. 
 7. Make sure the sim passes. 
 8. If any issues occur in compilation, add a pragma statement to the verification pmp_src_direct_data_out.v file to disable the warning.
========================================================
example4_i-c_t-0.9.v
//<register>
//<enable>
//<synch>
//<reset>
//</register>
//</enable>

//==========================================//
///// Code for generating the new value for reg path ///
////==========================================//

generate
//if (HAS_DMA)begin
if(0)begin

always @(*)begin

if(rst_n)
new_reg_value_st_finite_reset = 'b0;

else if (is_write_reg)begin

if(|(dma_ctrl_reg - 'b0))//(|(old_reg - 'b0))|(|(load_reg - 'b0)))begin
new_reg_value_st_finite= new_reg_value_st_finite_reset;

end

end

end

========================================================
example5_i-c_t-0.9.v
// This should be local parameter for riscv::ACCESS_WRITE in the implementation.
// However, currently, riscv::ACCESS_WRITE is never called.
always @ (posedge clk_i `OR1200_RST_EVENT rst_i)
	if (rst_i == `OR1200_RST_VALUE)
	{
`ifdef OR1200_BIST
	// RAM BIST
	mbist_si_i_ram_0 = mbist_so_o_ram_0;
	mbist_si_i_ram_1 = mbist_so_o_ram_1;
	mbist_si_i_ram_2 = mbist_so_o_ram_2;
	mbist_si_i_ram_3 = mbist_so_o_ram_3;

========================================================
example6_i-c_t-0.9.v
//��bcc 12.1 (https://github.com/Fulfiloop/bcc)
`ifndef _SECURE_INPUT
`define _SECURE_INPUT
//`ifndef _SECURE_OUTPUT
//`define _SECURE_OUTPUT
`endif
`endif

// Same driver Logic as Massive MEM2MEM
`ifdef _SECURE_INPUT
// Keep track of the number of register read accesses, in case any protections need to be applied in the future.
always@(posedge clk_i `CFG_RESET_SENSITIVITY)
begin
	if (rst_i == `TRUE)
	begin
	`ifdef _SECURE_OUTPUT
	//rst_o <= `TRUE;
 
	
========================================================
example7_i-c_t-0.9.v
// Method 1: set value at reset time. No need to do this in sim env.
// This is the easiest method, but cannot switch the field.
// Method 2:
// Assign a value to the field to ensure that
// the sim env can't change the value.
// Method 3:
// Extend the module to do a full register reset is teh security
// setting field is not assigned.
// Method 4:
// Extend the module to do a full register reset if the security
// setting field is not assigned. This is the method that is implemented.

// Method 1:
// Keep the register values the same (DUH)
// int security_setting;
// constants for access types;
// set security setting value at reset time
`define SECURE_ACCESS 0
// `define NORMAL_ACCESS 1
`define WRITE_ACCESS 2
`define READ_ACCESS
========================================================
example8_i-c_t-0.9.v
//�▬
//▬
// Recent changes for work around for rv32im chip errata
//3.0 - rv32im is fixed to support more than 4 co-proc
//2.0 - support for dual core rv32im.
//1.1 - update virtualization to take in account security related modifications
//1.0 - initial commit (10-22-2009)
// Dia's modifications (4/16/10) 

ns_io_im_jtag_hub ns_io_im_jtag_hub_inst

ns_io_jtag_io_master_0 ns_io_jtag_io_master_0_inst

ns_io_jtag_io_shaper_0 ns_io_jtag_io_shaper_0_inst

/////// END INSTANCES ////////////////////////////////

/////// ID
========================================================
example9_i-c_t-0.9.v
// CLK does not need to be driven high for this to be for sure.
// This presumes that a blocking reset is performed.
// The register to be reset itself can be read through the clock edge.
// The reset value itself can always be updated in the clock domain.
// This would allow correct reset of the register if the reset is level triggered
// and given at least one positive edge other than the falling edge of clear.
always @(posedge clk_i) begin
	 if (rst_ni) begin
	 	dma_ctrl_reg <= 'd0; 
	 	pmp_addr_reg <= 'd0; 
	 	pmp_access_type_reg <= 'd1;
	 end else begin
	 	dma_ctrl_reg <= dma_ctrl_new;
	 	pmp_addr_reg <= pmp
end

end

========================================================
example10_i-c_t-0.9.v
//�ÔÓÒÕÎ¯îÞÅÿÃÂðÝ = dd
 // dma_controller_t
////////////////////////////////////////////////////////////////////////////////

module dma_controller_tb ();

	parameter DMA_BASE = 32'd0;

	// Inputs
	reg clk;
	reg rst;
	reg read_post;
	reg write_pre;
	reg write_post;
	reg [4:0] dma_channel;
	reg [31:0] dma_source_addr;
	reg [31:0] dma_source_data;
	reg [31:0] dma_dest_addr;
	reg dma_relement;
	reg [31:0] dma_write_data;
	reg dma_read;
	reg [31:0] d
========================================================
example11_i-c_t-0.9.v
// EVERTON (12/17/2017): Add logic for handling rst
assign pmp_address_base[55-1:0] = pmpcfg_i;
assign pmp_address_base[63] = 1'b0;
assign pmp_address_base[58:56] = 2'b11;
assign pmp_address[7-1:0] = pmpcfg_i[7+:8];
assign pmp_access_type_reg[2-1:0] = 3'b111;
assign pmp_access_type_reg[3] = 0;
assign pmp_access_type_reg[4] = 0;
assign pmp_access_type_reg[5] = 1;
assign pmp_access_type_reg[6] = 0;
assign pmp
========================================================
example12_i-c_t-0.9.v
// Ensure that the register containing the dma configuration is assigned a default value following a software reset or done signal.

respective example code;

//////////////////////////////////
// Example: dma_controller_tb.v
//////////////////////////////////

module dma_controller_tb;

	// INTERNAL SIGNALS
	wire	[31:0]	sink0_data_out;
	wire	sink0_valid_out;
	wire	sink0_ready;
	wire	sink1_data_out;
	wire	sink1_valid_out;
	wire	sink1_ready;

	wire	[31:0]	source0_data_in;
	wire	source0_valid_in;
	wire	source0_ready;
	wire	source1_data_in;
	wire	source1_valid_in
========================================================
example13_i-c_t-0.9.v
// 1. Can not write pmp_access_type_reg or mau_type = WRITE to a register before pmp_access_type_en is set.
// 2. If pmp_access_type_reg is updated before pmp_access_type_en is set, mau_type = WRITE,
//	 the updated value will not be assigned to a register.
always @(posedge clk_i `CFG_RESET_SENSITIVITY)
	if (rst_i == `TRUE)
	begin
	pmp_access_type_reg <= `CFG_PMP_ACCESS_TYPE_NONE;
	pmp_addr_reg <= 'b0;
	
end

========================================================
example14_i-c_t-0.9.v
// 1. Add Register holding security settings and write protection bits
// 2. Add MASK/MATCH/PROTECTION Registers
// 3. Add read protection register to check if the DMA can perform the protection checking

//// REQUEST_ENGINE
//
/*---------------------------------------------------------------------------
 Module: RegisterFile
 ---------------------------------------------------------------------------
 - Part - 1
 ----------------------------------------------------------------------------------------------------------------
 Description of the register file:
 - 1,759,595 write stalls with 1,000,000 reads and 1,008,767 read-only stalls are expected
 - 1,000,000 reads are required to generate 1,759,595 write stalls for 1,000,000 reads
 The 1,759,595 writes are for the loops to test the random addresses
 
 +- (*) The instructions loop their randomly generated instruction to reach all bits of the register file
 
 +- ($) The address loops from 0 to the register file size. 
 
 +
========================================================
example15_i-c_t-0.9.v

// If CommonsRISCV-MIPS has regular ("workflow") MIF light assignments, then:
// - Firmware will be able to write to:
// - Write Address: dma_control_0[0-31]
// - Write value: dma_control_0[32-63]
// - Write value: dma_control_0[64]
// - Write value: dma_control_0[65]
// - Write value: dma_control_0[66]
// - Write value: dma_control_0[67]
// - Write value: dma_control_0[68]
// ...
// - Write address: dma_control_0[32-63]
// - Write value: dma_control_0[68]
// - Write value: dma_control_0[69]
// ...
// -
========================================================
example16_i-c_t-0.9.v
// VERILOG Linting Otherwise-I Problem isnt found
reg init_dma_complete; // Used for Init state or Done state.
always @(posedge clk_i)begin
if(rst_ni)begin
init_dma_complete <=0;

end

end

========================================================
example17_i-c_t-0.9.v
 Jon: 16/9/16:
 The file path of this program is "KERNEL_SRC_PROG_22.v" in the working dir.
 The my_chip/my_FPGA/
 directory is used as the program working dir.
 The program included a kernel program, which is "KERNEL_SRC_PROG.v", in "my_chip/my_FPGA/SRC/KERNEL_SRC/".
 使用这个配置文件的目录，运行情况下，要更改的文件目录的全部路径
 更改的my_fpga/tasks/test_dma_verifiesrc
========================================================
example18_i-c_t-0.9.v
// the issue with the security sensitive registers is that the reset values
// are not set in the core itself but are set by the PC during startup which
// could take a while. You might need to enter the security key and that
// will halt the boot sequence for too long.
// Therefore the reset values (if any) must be obtained from the PC and passed to
// the core during initialization.
// FIX:
// 1. During the initial init the core will read the security settings for
// the first part of the Flash ROM (between 0x00000000 and 0x001FFFFF8)
// These settings need to be passed to the core during the init process
// 2. The rest of the flash ROM is read in using the flashrom module where
// the security settings are sorted out between the 2 addresses 0x0020000 and
// 0x00201FFF8. The problem here is that the addresses are not contiguous

========================================================
example19_i-c_t-0.9.v
// Log security_violations_o.
// Log other memory errors in general.
// Log core dumps.


///// Testbench Inputs


///// DUT Inputs
// Set to zero if unused.
/// BUG: Unused inz

// Inputs from prr to abort a DMA

/// BUG: Unused
logic core_dmmu_itcb_d, core_dmmu_itcb_i, core_i_itcb_it;
logic core_dcpu_d, core_dcpu_i, core_i_en;


///// DMA controller Interface


///// BUG: Unused
logic [DMA_CTRL_WIDTH-1:0] pmp_cmd_reg, pmp_cmd;
logic [7:0] pmp_cmd_int;




========================================================
example0_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used.
 3. pmp_access_type_en is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_en is not used.
 6. pmp_access_type_en is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_en is not used.
 9. pmp_access_type_en is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_en is not used.
 12. pmp_access_type_en is not used.
 13. pmp_access_
========================================================
example1_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used.
 3. pmp_access_type_en is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_en is not used.
 6. pmp_access_type_en is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_en is not used.
 9. pmp_access_type_en is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_en is not used.
 12. pmp_access_type_en is not used.
 13. pmp_access_
========================================================
example2_i-d_t-0.1.v
 1. Use a register to hold the value of pmp_access_type_en.
 2. Use a register to hold the value of pmp_access_type_reg.
 3. Use a register to hold the value of pmp_access_type_new.
 4. Use a register to hold the value of pmp_access_type_en_new.
 5. Use a register to hold the value of pmp_access_type_en_new.
 6. Use a register to hold the value of pmp_access_type_en_new.
 7. Use a register to hold the value of pmp_access_type_en_new.
 8. Use a register to hold the value of pmp_access_type_en_new.
 9. Use a register to hold the value of pmp_access_type_en_new.
========================================================
example3_i-d_t-0.1.v
 1. Add a "Reset" signal to the design.
 2. Add a "Reset" gate to the design.
 3. Add a "Reset" gate to the design.
 4. Add a "Reset" gate to the design.
 5. Add a "Reset" gate to the design.
 6. Add a "Reset" gate to the design.
 7. Add a "Reset" gate to the design.
 8. Add a "Reset" gate to the design.
 9. Add a "Reset" gate to the design.
 10. Add a "Reset" gate to the design.
 11. Add a "Reset" gate to the design.
 12. Add a "Reset" gate to the design.
 13. Add a "Reset" gate to the design.
 14. Add a
========================================================
example4_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used.
 3. pmp_access_type_en is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_en is not used.
 6. pmp_access_type_en is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_en is not used.
 9. pmp_access_type_en is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_en is not used.
 12. pmp_access_type_en is not used.
 13. pmp_access_
========================================================
example5_i-d_t-0.1.v
 1. Add a "Reset" input to the design.
 2. Add a "Reset" output to the design.
 3. Add a "Reset" input to the design.
 4. Add a "Reset" output to the design.
 5. Add a "Reset" input to the design.
 6. Add a "Reset" output to the design.
 7. Add a "Reset" input to the design.
 8. Add a "Reset" output to the design.
 9. Add a "Reset" input to the design.
 10. Add a "Reset" output to the design.
 11. Add a "Reset" input to the design.
 12. Add a "Reset" output to the design.
 13. Add a "Reset" input to the design.
 14. Add a
========================================================
example6_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_new_en is not used.
 5. pmp_access_type_new_en_reg is not used.
 6. pmp_access_type_new_en_reg_d is not used.
 7. pmp_access_type_new_en_reg_q is not used.
 8. pmp_access_type_new_en_reg_q_d is not used.
 9. pmp_access_type_new_en_reg_q_q is not used.
 10. pmp_access_type_new_en_reg_q_q_d is
========================================================
example7_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_reg is not used.
 6. pmp_access_type_new is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_reg is not used.
 9. pmp_access_type_new is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_reg is not used.
 12. pmp_access_type_new is not used.
 13. pmp_access_
========================================================
example8_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_reg is not used.
 6. pmp_access_type_new is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_reg is not used.
 9. pmp_access_type_new is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_reg is not used.
 12. pmp_access_type_new is not used.
 13. pmp_access_
========================================================
example9_i-d_t-0.1.v
// 1. pmp_access_type_en is not used.
// 2. pmp_access_type_reg is not used.
// 3. pmp_access_type_new is not used.
// 4. pmp_access_type_new is not assigned a value.
// 5. pmp_access_type_en is not assigned a value.
// 6. pmp_access_type_en is not used.
// 7. pmp_access_type_reg is not used.
// 8. pmp_access_type_new is not used.
// 9. pmp_access_type_new is not assigned a value.
// 10. pmp_access_type_en is not assigned a value.
// 11. pmp_access_type_en is not used.
// 12. pmp_access_type_reg is not used.

========================================================
example10_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_new is not assigned a value.
 5. pmp_access_type_en is not assigned a value.
 6. pmp_access_type_reg is not assigned a value.
 7. pmp_access_type_new is not assigned a value.
 8. pmp_access_type_en is not assigned a value.
 9. pmp_access_type_reg is not assigned a value.
 10. pmp_access_type_new is not assigned a value.
 11. pmp_access_type_en is not assigned a value.
 12. pmp_access_
========================================================
example11_i-d_t-0.1.v
// 1. Add a register to hold the security setting.
// 2. Add a register to hold the security setting for the DMA.
// 3. Add a register to hold the security setting for the PMP.
// 4. Add a register to hold the security setting for the PIC.
// 5. Add a register to hold the security setting for the PIC.
// 6. Add a register to hold the security setting for the PIC.
// 7. Add a register to hold the security setting for the PIC.
// 8. Add a register to hold the security setting for the PIC.
// 9. Add a register to hold the security setting for the PIC.
// 10. Add a register to hold the security setting for the PIC.
// 11. Add a register to hold the security setting for the PIC.
// 12. Add a register to hold the security setting for the PIC.

========================================================
example12_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_new_reg is not used.
 5. pmp_access_type_en_reg is not used.
 6. pmp_access_type_en_new is not used.
 7. pmp_access_type_new_reg is not used.
 8. pmp_access_type_en_reg is not used.
 9. pmp_access_type_en_new is not used.
 10. pmp_access_type_new_reg is not used.
 11. pmp_access_type_en_reg is not used.
 12. pmp_access_
========================================================
example13_i-d_t-0.1.v
// 1. Use a register to hold the security setting.
// 2. Use a register to hold the security setting for the DMA.
// 3. Use a register to hold the security setting for the PMP.
// 4. Use a register to hold the security setting for the PIC.
// 5. Use a register to hold the security setting for the PIC.
// 6. Use a register to hold the security setting for the PIC.
// 7. Use a register to hold the security setting for the PIC.
// 8. Use a register to hold the security setting for the PIC.
// 9. Use a register to hold the security setting for the PIC.
// 10. Use a register to hold the security setting for the PIC.
// 11. Use a register to hold the security setting for the PIC.
// 12. Use a register to hold the security setting for the PIC.

========================================================
example14_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used.
 3. pmp_access_type_en is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_en is not used.
 6. pmp_access_type_en is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_en is not used.
 9. pmp_access_type_en is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_en is not used.
 12. pmp_access_type_en is not used.
 13. pmp_access_
========================================================
example15_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used.
 3. pmp_access_type_en is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_en is not used.
 6. pmp_access_type_en is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_en is not used.
 9. pmp_access_type_en is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_en is not used.
 12. pmp_access_type_en is not used.
 13. pmp_access_
========================================================
example16_i-d_t-0.1.v
 1. Check if the register is holding a value.
 2. If the register is holding a value, then check if the value is valid.
 3. If the register is holding a value and the value is not valid, then
 assign 0 to the register.
 4. If the register is holding a value and the value is valid, then
 assign the value to the register.
 5. If the register is not holding a value and the register is enabled,
 then assign 0 to the register.
 6. If the register is not holding a value and the register is not enabled,
 then do not write to the register.
 7. If the register is not holding a value and the register is not enabled,
 then do not read from the register.
 8. If the register is not holding a value and the register is not enabled,
 then do not read from or write to
========================================================
example17_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_new_en is not used.
 5. pmp_access_type_new_en_reg is not used.
 6. pmp_access_type_new_en_reg_logic is not used.
 7. pmp_access_type_new_en_logic is not used.
 8. pmp_access_type_new_en_logic_reg is not used.
 9. pmp_access_type_new_en_logic_reg_logic is not used.
 10. pmp_access_type_new_en_logic_reg_logic
========================================================
example18_i-d_t-0.1.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_new_en is not used.
 5. pmp_access_type_new_en_reg is not used.
 6. pmp_access_type_new_en_reg_en is not used.
 7. pmp_access_type_new_en_reg_en_reg is not used.
 8. pmp_access_type_new_en_reg_en_reg_en is not used.
 9. pmp_access_type_new_en_reg_en_reg_en_reg is not used.
 10. pmp_access_type_new_en_
========================================================
example19_i-d_t-0.1.v
// 1. Use a register to hold the security setting.
// 2. Use a register to hold the security setting for the DMA.
// 3. Use a register to hold the security setting for the PMP.
// 4. Use a register to hold the security setting for the PIC.
// 5. Use a register to hold the security setting for the PIC.
// 6. Use a register to hold the security setting for the PIC.
// 7. Use a register to hold the security setting for the PIC.
// 8. Use a register to hold the security setting for the PIC.
// 9. Use a register to hold the security setting for the PIC.
// 10. Use a register to hold the security setting for the PIC.
// 11. Use a register to hold the security setting for the PIC.
// 12. Use a register to hold the security setting for the PIC.

========================================================
example0_i-d_t-0.3.v
 1. Remove the pmp_access_type_en register.
 2. Remove the pmp_access_type_reg in the riscv_soc_tb.v file.
 3. Remove the pmp_access_type_reg in the riscv_soc_tb.v file.
 4. Remove the pmp_access_type_reg in the riscv_soc_tb.v file.
 5. Remove the pmp_access_type_reg in the riscv_soc_tb.v file.
 6. Remove the pmp_access_type_reg in the riscv_soc_tb.v file.
 7. Remove the pmp_access_type_reg in the riscv_soc_tb.v file.
 8. Remove the pmp_access_type_reg in the r
========================================================
example1_i-d_t-0.3.v
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========================================================
example2_i-d_t-0.3.v
 1. Make sure the register values are initialized to 0 when reset is low.
 2. Make sure the register values are updated when the corresponding 
 input is high.
 3. Make sure the register values are not updated when the corresponding 
 input is low.
 4. Make sure the register values are updated when the corresponding 
 input is high.
 5. Make sure the register values are not updated when the corresponding 
 input is low.
 6. Make sure the register values are updated when the corresponding 
 input is high.
 7. Make sure the register values are not updated when the corresponding 
 input is low.
 8. Make sure the register values are updated when the corresponding 
 input is high.
 9. Make sure the register values are not updated when the corresponding 
 input is low.
 10. Make sure the register values are updated
========================================================
example3_i-d_t-0.3.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used.
 3. pmp_access_type_en is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_en is not used.
 6. pmp_access_type_en is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_en is not used.
 9. pmp_access_type_en is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_en is not used.
 12. pmp_access_type_en is not used.
 13. pmp_access_
========================================================
example4_i-d_t-0.3.v
 1. pmp_access_type_en is never used.
 2. pmp_access_type_en is not used in the design.
 3. pmp_access_type_en is not used in the design.
 4. pmp_access_type_en is not used in the design.
 5. pmp_access_type_en is not used in the design.
 6. pmp_access_type_en is not used in the design.
 7. pmp_access_type_en is not used in the design.
 8. pmp_access_type_en is not used in the design.
 9. pmp_access_type_en is not used in the design.
 10. pmp_access_type_en is not used in the design.
 11. pmp_access_type_en is not
========================================================
example5_i-d_t-0.3.v
 1) pmp_access_type_en should be assigned to 0 when reset is low.
 2) pmp_access_type_en should be assigned to pmp_access_type_new when reset is high.
 3) pmp_access_type_en should be assigned to pmp_access_type_reg when dma_ctrl_en is high.
 4) pmp_access_type_reg should be assigned to pmp_access_type_new when dma_ctrl_en is low.
 5) pmp_access_type_reg should be assigned to 0 when reset is low.
 6) pmp_access_type_reg should be assigned to pmp_access_type_en when dma_ctrl_en is high.
 7) pmp_access_type_en should be assigned to pmp_access_type_reg when d
========================================================
example6_i-d_t-0.3.v
 The following code may be incorrect.
 The register holding the security settings is not cleared on reset.
 The register holding the security settings is cleared on enable.
 The register holding the security settings is cleared on disable.
 The register holding the security settings is cleared on reset.
 The register holding the security settings is cleared on disable.
 The register holding the security settings is cleared on enable.
 The register holding the security settings is cleared on reset.
 The register holding the security settings is cleared on disable.
 The register holding the security settings is cleared on enable.
 The register holding the security settings is cleared on reset.
 The register holding the security settings is cleared on disable.
 The register holding the security settings is cleared on enable.
 The register holding the security settings is cleared on reset.
 The register holding the security settings is cleared on disable.
 The register holding the security settings is
========================================================
example7_i-d_t-0.3.v
 1. Add a register to hold the security setting.
 2. Modify the security setting to be a bit-field.
 3. Modify the security setting to be a bit-field.
 4. Modify the security setting to be a bit-field.
 5. Modify the security setting to be a bit-field.
 6. Modify the security setting to be a bit-field.
 7. Modify the security setting to be a bit-field.
 8. Modify the security setting to be a bit-field.
 9. Modify the security setting to be a bit-field.
 10. Modify the security setting to be a bit-field.
 11. Modify the security setting to be a bit-field.
 12. Modify the security setting to be a bit-field.
 13. Modify the security setting to be a
========================================================
example8_i-d_t-0.3.v
 1. Add a reset for the registers holding security settings.
 2. Add a logic to initialize the registers holding security settings to a known state.
 3. Add a logic to initialize the registers holding security settings to a known state.
 4. Add a logic to set the registers holding security settings to a known state.
 5. Add a logic to set the registers holding security settings to a known state.
 6. Add a logic to set the registers holding security settings to a known state.
 7. Add a logic to set the registers holding security settings to a known state.
 8. Add a logic to set the registers holding security settings to a known state.
 9. Add a logic to set the registers holding security settings to a known state.
 10. Add a logic to set the registers holding security settings to a known state.
 11. Add a logic to set the registers holding security settings to a
========================================================
example9_i-d_t-0.3.v
 1. Add a register to hold the security setting.
 2. Modify the security setting to be a bit field.
 3. Modify the security setting to be a bit field.
 4. Modify the security setting to be a bit field.
 5. Modify the security setting to be a bit field.
 6. Modify the security setting to be a bit field.
 7. Modify the security setting to be a bit field.
 8. Modify the security setting to be a bit field.
 9. Modify the security setting to be a bit field.
 10. Modify the security setting to be a bit field.
 11. Modify the security setting to be a bit field.
 12. Modify the security setting to be a bit field.
 13. Modify the security setting to be a bit field.
 14. Modify the security
========================================================
example10_i-d_t-0.3.v
 1. pmp_access_type_en and pmp_access_type_reg should be removed.
 2. pmp_access_type_en should be removed.
 3. pmp_access_type_reg should be removed.
 4. pmp_access_type_reg should be placed in the top level.
 5. pmp_access_type_reg should be placed in the top level.
 6. pmp_access_type_reg should be placed in the top level.
 7. pmp_access_type_reg should be placed in the top level.
 8. pmp_access_type_reg should be placed in the top level.
 9. pmp_access_type_reg should be placed in the top level.
 10. pmp_access_type_reg should be placed in the top level.
 11.
========================================================
example11_i-d_t-0.3.v
 1. Make sure the reset signal is not active when the module is disabled.
 2. Make sure the reset signal is not active when the module is enabled.
 3. Make sure the reset signal is active when the module is enabled and the 
 reset signal is active.
 4. Make sure the reset signal is active when the module is enabled and the 
 reset signal is deactive.
 5. Make sure the reset signal is active when the module is enabled and the 
 reset signal is active.
 6. Make sure the reset signal is active when the module is enabled and the 
 reset signal is deactive.
 7. Make sure the reset signal is active when the module is enabled and the 
 reset signal is active.
 8. Make sure the reset signal is active when the module is enabled and the 
 reset signal is deactive.
 9. Make sure
========================================================
example12_i-d_t-0.3.v
 1. Enable pmp_access_type_en to avoid "Uninitialized" warning.
 2. Add "assign pmp_access_type_en = 1'b0;" after "pmp_access_type_reg = 0;"
 3. Remove "assign pmp_access_type_en = 1'b0;" after "pmp_access_type_reg = 0;"
 4. Remove "assign pmp_access_type_en = 1'b0;" after "pmp_access_type_new = 0;"
 5. Remove "assign pmp_access_type_en = 1'b0;" after "pmp_access_type_new = pmp_access_type_reg;"
 6. Remove "assign pmp_access_type_en = 1'b0;" after "pmp_access_type_reg =
========================================================
example13_i-d_t-0.3.v
 1. Fix the reset value to be 0.
 2. Fix the register to be used to store the security setting.
 3. Fix the register to be used to store the security setting.
 4. Fix the register to be used to store the security setting.
 5. Fix the register to be used to store the security setting.
 6. Fix the register to be used to store the security setting.
 7. Fix the register to be used to store the security setting.
 8. Fix the register to be used to store the security setting.
 9. Fix the register to be used to store the security setting.
 10. Fix the register to be used to store the security setting.
 11. Fix the register to be used to store the security setting.
 12. Fix the register to be used to store the security setting.
 13. Fix the register to be used to store the
========================================================
example14_i-d_t-0.3.v
 1. Assign 0 to register when reset is low.
 2. Assign 0 to register when reset is low.
 3. Assign 0 to register when reset is low.
 4. Assign 0 to register when reset is low.
 5. Assign 0 to register when reset is low.
 6. Assign 0 to register when reset is low.
 7. Assign 0 to register when reset is low.
 8. Assign 0 to register when reset is low.
 9. Assign 0 to register when reset is low.
 10. Assign 0 to register when reset is low.
 11. Assign 0 to register when reset is low.
 12. Assign 0 to register when reset is low.
 13. Assign 0 to register when reset is low.
 14. Assign 0 to register when reset is low.
 15. Ass
========================================================
example15_i-d_t-0.3.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_reg is not used.
 3. pmp_access_type_new is not used.
 4. pmp_access_type_en is not used.
 5. pmp_access_type_reg is not used.
 6. pmp_access_type_new is not used.
 7. pmp_access_type_en is not used.
 8. pmp_access_type_reg is not used.
 9. pmp_access_type_new is not used.
 10. pmp_access_type_en is not used.
 11. pmp_access_type_reg is not used.
 12. pmp_access_type_new is not used.
 13. pmp_access_
========================================================
example16_i-d_t-0.3.v
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========================================================
example17_i-d_t-0.3.v
 1. pmp_access_type_en is not used.
 2. pmp_access_type_en is not used in the design.
 3. pmp_access_type_en is not used in the design.
 4. pmp_access_type_en is not used in the design.
 5. pmp_access_type_en is not used in the design.
 6. pmp_access_type_en is not used in the design.
 7. pmp_access_type_en is not used in the design.
 8. pmp_access_type_en is not used in the design.
 9. pmp_access_type_en is not used in the design.
 10. pmp_access_type_en is not used in the design.
 11. pmp_access_type_en is not
========================================================
example18_i-d_t-0.3.v
//�ìÊ¾µÄÖµÔÚresetÖÐ¶¼ÊÇ0
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example19_i-d_t-0.3.v
// 1. pmp_access_type_en is not used.
// 2. pmp_access_type_reg is not used.
// 3. pmp_addr_en is not used.
// 4. pmp_addr_reg is not used.
// 5. pmp_addr_new is not used.
// 6. pmp_addr_reg is not used.
// 7. pmp_addr_new is not used.
// 8. pmp_addr_en is not used.
// 9. pmp_addr_reg is not used.
// 10. pmp_addr_new is not used.
// 11. pmp_addr_reg is not used.
// 12. pmp_addr_en is not used.
// 13. pmp_addr_reg is not used.
// 14. pmp_addr_new is not used.

========================================================
example0_i-d_t-0.5.v
 1. Fix the register for security setting is not cleared when reset is high.
 2. Add logic for the case that the security setting is not cleared when reset is high.
 3. Add logic for the case that the security setting is not cleared when reset is low.
 4. Add logic for the case that the security setting is not cleared when reset is low.
 5. Add logic for the case that the security setting is not cleared when reset is high.
 6. Add logic for the case that the security setting is not cleared when reset is high.
 7. Add logic for the case that the security setting is not cleared when reset is low.
 8. Add logic for the case that the security setting is not cleared when reset is low.
 9. Add logic for the case that the security setting is not cleared when reset is high.
 10. Add logic for the case that the security setting is not
========================================================
example1_i-d_t-0.5.v
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example2_i-d_t-0.5.v
 1) pmp_access_type_en is not used.
 2) pmp_access_type_reg is not used.
 3) pmp_access_type_new is not used.
 4) pmp_access_type_new_en is not used.
 5) pmp_access_type_new_en_reg is not used.
 6) pmp_access_type_en_reg is not used.
 7) pmp_access_type_en_reg_reg is not used.
 8) pmp_access_type_reg_reg is not used.
 9) pmp_access_type_reg_en is not used.
 10) pmp_access_type_reg_en_reg is not used.
 11) pmp_access_type_reg_en_reg_reg is not used
========================================================
example3_i-d_t-0.5.v
 1. The register holding the security setting needs to be initialized when the 
 DMA controller is first enabled.
 2. The register holding the security setting needs to be updated when the DMA 
 controller is disabled and enabled again.
 3. The register holding the security setting needs to be updated when the DMA 
 controller is first enabled.
 4. The register holding the security setting needs to be updated when the DMA 
 controller is disabled and enabled again.
 5. The register holding the security setting needs to be updated when the DMA 
 controller is disabled and enabled again.
 6. The register holding the security setting needs to be updated when the DMA 
 controller is disabled and enabled again.
 7. The register holding the security setting needs to be updated when the DMA 
 controller is disabled and enabled again.
 8. The register holding the security
========================================================
example4_i-d_t-0.5.v
�ðîâåðèì, ÷òîâà ïðåðâàíèðóþòîðà, ÷òîâà âðàíèðóþòîðà,
ñ êîìàíèðóþòîðà, ïðîâåðèì, ÷òîâà âðàíèðóþòîðà,
ñ êîìàíèðóþòîðà, ïðîâåðèì, ÷òîâà âðàíèðóþòîðà,
ñ êîìàíèðóþòîðà, ïðîâåðè�
========================================================
example5_i-d_t-0.5.v
 1. On Reset, use default values for the security settings, instead of 0.
 2. The default values should be passed in from the top level wrapper.
 3. When the security settings are changed, the values should be updated in
 the registers, but the registers should not be updated until the DMA is stopped.
 4. The security settings should be reset when the DMA is started.
 5. The security settings should be reset when the DMA is stopped.
 6. The security settings should be reset when the DMA is aborted.
 7. The security settings should be updated when the DMA is aborted.
 8. The security settings should be updated when the DMA is done.
 9. The security settings should be updated when the DMA is enabled.
 10. The security settings should be updated when the DMA is disabled.
 11. The security settings should be updated
========================================================
example6_i-d_t-0.5.v
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example7_i-d_t-0.5.v
//�µ¿¨¶¯ÎÞÐÅÏ¢µÄ¿ØÖÆ 
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========================================================
example8_i-d_t-0.5.v
���źźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźźź�
========================================================
example9_i-d_t-0.5.v
// 1. Have to add a counter to keep track of how many cycles the security setting has been set.
// 2. Have to make sure that the counter is reset when DMA is disabled.
assign pmp_access_type_en = (rst == 0) ? 1 : pmp_access_type_en;
assign pmp_access_type_new = (rst == 0) ? pmp_access_type_reg : pmp_access_type_new;
assign pmp_access_type_reg = (pmp_access_type_en == 1) ? pmp_access_type_new : pmp_access_type_reg;

assign start_d = (rst == 0) ? start_i : start_d;
assign length_d = (rst == 0) ? length_i : length_d;
assign source
========================================================
example10_i-d_t-0.5.v
//�µµçÐÝØ
// DONE
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example11_i-d_t-0.5.v
��加设计
 1. 读写数据时，如果需要设计完成数据的高有效地址，需要将数据高有效地址输出到pmpcfg_d[0]
 2. pmp_access_type_en，用于控制地址输出的类型，0：高有效地址输出，1：高有效地址输出，2：
========================================================
example12_i-d_t-0.5.v
��ЩѺЧэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэ
 Assign 0 to register when reset is low.
 FIX:
эЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэЩэ
 Assign 0 to register when reset is low.
 FIX:
эЩэ�
========================================================
example13_i-d_t-0.5.v
 1. Make sure that the security settings are not modified unless the module is being reset.
 2. Check if the module is being reset.
 3. Check if the module is in the idle state.
 4. Check if the module is in the idle state and the reset is low.
 5. Check if the module is in the idle state and the reset is low and the access type is WRITE.
 6. Check if the module is in the idle state and the reset is low and the access type is READ.
 7. Check if the module is in the idle state and the reset is low and the access type is WRITE.
 8. Check if the module is in the idle state and the reset is low and the access type is READ.
 9. Check if the module is in the idle state and the reset is low and the access type is WRITE.
 10. Check if the module is in the
========================================================
example14_i-d_t-0.5.v
 1. If the DMA controller is not enabled, the DMA controller should not be initialized.
 2. The DMA controller should be initialized only when the DMA controller is enabled.
 3. The DMA controller should be disabled only after the DMA transfer is done.
 4. The DMA controller should be disabled only when the DMA transfer is not enabled.
 5. The DMA controller should be disabled only when the DMA transfer is not enabled.
 6. The DMA controller should be disabled only when the DMA transfer is not enabled.
 7. The DMA controller should be disabled only when the DMA transfer is not enabled.
 8. The DMA controller should be disabled only when the DMA transfer is not enabled.
 9. The DMA controller should be disabled only when the DMA transfer is not enabled.
 10. The DMA controller should be disabled only when
========================================================
example15_i-d_t-0.5.v
//�µ¹ýÇý¶¼ÄÜÊ¹ÓÃ
// DONE: Done signal from DMA, must not be used for other operation.
// ABORT: DMA operation aborted by abort command.
//
//------------------------------------------------------//
// The Following is the DMA Controller module.
//------------------------------------------------------//

module dma_controller
#(
parameter 
	MAX_CYCLES = 'd1024,
	MAX_BLOCK = 'd32,
	MAX_BURST = 'd8,
	ADDR_WIDTH = 'd32,
	BURST_WIDTH = 'd8,
	//-----------------------------------------------------
	// Example State Machine:
	// 0 - IDLE
	// 1 - LOAD
	// 2 - START
	// 3 - STORE
	
========================================================
example16_i-d_t-0.5.v
//�ð¼þ¿éÏµÍ³Ð´ÈëÖµ
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example17_i-d_t-0.5.v
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example18_i-d_t-0.5.v
// 1. Register pmp_access_type_en 
// 2. Assign 0 to pmp_access_type_reg when reset is low.
// 3. Assign pmp_access_type_en to pmp_access_type_reg when dma_ctrl_en is high.
// 4. Assign pmp_access_type_new to pmp_access_type_reg when dma_ctrl_en is low.
// 5. Assign pmp_access_type_new to pmp_access_type_en when dma_ctrl_en is high.
// 6. Assign pmp_access_type_reg to pmp_access_type_en when dma_ctrl_en is low.
// 7. Assign pmp_access_type_en to pmp_access_type_reg when dma_ctrl_en is high.

========================================================
example19_i-d_t-0.5.v
//�ç÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷
//÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷
//÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷÷

========================================================
example0_i-d_t-0.7.v
//� Adjust the access type if the address space is too large

// Simple Assignment for Registers holding security setting
//� Set the initial value for the registers holding security settings
// Not working well for Slave

// DMA controller
// Not working for the system under test (using master)
// Counting how many cycles the DMA controller spends in the various states (idle, load, store, others)

// DMA controller:
// attention: 
// attention: this is a design for DMA controller, not a functional specification!

//Risc-V Specification
// The master of the system has the following properties:
// - The master has an ID. The ID is a 16-bit wire.
// - The ID allows for a simple method to determine whether the master is a valid initiator of a transaction.
// - The CHANNEL_WIDTH is the number of independent DMA
========================================================
example1_i-d_t-0.7.v
 1. For now, we are using one register for each security setting.
 2. We are not using a logic block to control the clock gating of each register.
 3. We assume that the write clock is always enabled.
 4. We assume that the clock for the register holding the interrupt enable is gated on a higher level.
 5. The reset of the register holding the interrupt enable is handled separately.
 6. The reset of the register holding the security settings is handled separately.
 7. We will need to add support for a register to hold the security setting and a register to hold the 
 interrupt enable.
 8. We will need to add support for an array of registers to hold the security settings.
 9. We will need to add support for an array of registers to hold the interrupt enable.
 10. When we add support for an array of registers to hold the security settings,
========================================================
example2_i-d_t-0.7.v
// designtime only
always @ (posedge clk_i or negedge rst_i)
begin
	if (~rst_i)
	begin
	// assign default values to registers
	dma_ctrl_reg <= {{DMA_CTRL_WIDTH-1{1'b0}}, 1'b1};
	pmp_addr_reg <= 'h00000000;
	pmp_access_type_reg <= 'h00;
	
end

end

========================================================
example3_i-d_t-0.7.v
// if the register holding the pmp config is missing, write the default config to the register. 

// pmp_addr_en bit should be set to 0 when reading the register holding security settings.
// pmp_addr_en bit should be set to 1 when writing to the register holding security settings.
// pmp_addr_en bit should be set to 0 when reading the register holding the config.
// pmp_addr_en bit should be set to 1 when writing to the register holding the config.


// When start_d is asserted, the DMA controller starts to transfer data.
// The data will be transferred from the source address (start_d_src_addr) to the destination address (start_d_dst_addr).
// The length_d (the number of data to be transfered) is calculated from the start_d_length_reg.
// The valid_o will
========================================================
example4_i-d_t-0.7.v
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add assertion that reg_value is only updated when reg_write is active.
 FIX:
 Add
========================================================
example5_i-d_t-0.7.v
 mov 
 mov rvfi_ctrl_reset_n_addr_o_reset_n_reg[0], 0;
 mov rvfi_ctrl_reset_n_addr_o[0], 0;
 mov rvfi_ctrl_reset_n_addr_o[1], 0;
 mov rvfi_ctrl_reset_n_addr_o[2], 0;
 mov rvfi_ctrl_reset_n_addr_o[3], 0;
 mov rvfi_ctrl_reset_n_addr_o[4], 0;
 mov rvfi_ctrl_reset_n_addr_o[5], 0;
 mov rvfi_ctrl_reset_n_addr_o[6], 0;
 mov rvfi_ctrl_reset_n_addr_o[7], 0;

========================================================
example6_i-d_t-0.7.v
// This will cause a delay on the first read back of the write value
// due to a race in the design. 
// The delay is on the clock edge where the value is written 
// to the register. 
// The designs have been reviewed and it is believed that this is not the issue. 
// However, to avoid this potential issue, we set the register to 0 on reset.


// The following two lines are for the reset of the pmp_access_type_reg.
// The compiler will generate a warning for this.
// Because this is a behavioral model, it is unclear how this will work. 
// To resolve the warning, we could use the following three lines instead
// of the two listed below.
// new_pmp_access_type_reg <= 0;
// new_pmp_access_type_en <= 1;
// new_pmp_access_type
========================================================
example7_i-d_t-0.7.v
//�	assign pmp_access_type_en = (rst_i) ? 0 : pmp_access_type_en_i;
// Assign 0 to register when reset is low.
// FIX:
//`define RST_ACT_LOW 1
//`ifdef RST_ACT_LOW
//`define DFT_TAGS_REG_RESET rst_i
//`else
//`define DFT_TAGS_REG_RESET (~rst_i)
//`endif

//`define TAGS_REG_RESET (DFT_TAGS_REG_RESET & pmp_access_type_en_i)
//`define TAGS_REG_NON_RESET (~DFT_TAGS_REG_RESET & pmp_access_type_en_i)
//`define TAGS_REG
========================================================
example8_i-d_t-0.7.v
// Register Not Alligned with Address
// Assert reset when register is not loaded.
// Implement register for DMA controller.
// Implement register for pmp

========================================================
example9_i-d_t-0.7.v
 1. Do not initialize pmp_access_type_en to 0.
 2. Do not initialize pmp_access_type_reg to 0.
 3. Assign pmp_access_type_reg to pmp_access_type_new.
 4. Assign pmp_access_type_en to pmp_access_type_new.
 5. Assign pmp_access_type_new to pmp_access_type_reg.
 6. Assign pmp_access_type_en to pmp_access_type_en_reg.
 7. Assign pmp_access_type_en_reg to pmp_access_type_en
 8. Assign pmp_access_type_en to dma_ctrl_en.
 9. Assign dma_ctrl_en to pmp_access_type_
========================================================
example10_i-d_t-0.7.v
// Line-Up the 'done' signal for the two the riscv::dma modules.
// Done signals from riscv_dma can be connected to the dma_done_o of the 
// corresponding riscv_dma module.


//*********************************************************************************************
// ROM: The data to be transferred is stored in the ROM.
//*********************************************************************************************


//*********************************************************************************************
// Wires: The data to be transferred is stored in the registers.
//*********************************************************************************************


//*********************************************************************************************
// I/O Connections: The data paths of the modules are connected to the I/O.
//*********************************************************************************************

// *** Start: Inputs to Config Registers
// These are the config inputs that go into the config registers.
// The config_i signals are generated from the config_wires signals.


========================================================
example11_i-d_t-0.7.v
 The DMA controller internally has a 16-bit address, for the register
 file accessed via the 32-bit physical address. For now, this address is
 given the same value as the 32-bit physical address.
 Thus, the register file will be accessed through a 32-bit address, but the
 address used is really only 16-bits.
 The register file is a simple shift register, and the address is given to the
 register file in an array of 16-bit addresses. The register file is loaded
 with 32 bits of data, and the MSB is written first. A simple combinational
 logic block is used to generate the correct address signals for the register
 file.
 A 32-bit address is loaded into the register file in the following manner:
 1. The lower 16 bits are loaded from the new address.
 2. The register file shift register is shifted left 16 times
========================================================
example12_i-d_t-0.7.v
//�
//�
//
//riscv_soc_tb.v
//
//Copyright (c) 2000-2002 Artisan Components, Incorporated. All Rights Reserved.
//
//Use of this Software/Data is subject to the terms and conditions of
//the applicable license agreement between Artisan Components, Incorporated
//and TADEK. Please refer to the applicable agreement for further
//details.
//
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========================================================
example13_i-d_t-0.7.v
// Add logic to initialize the register (ignore the value of reset)
// to avoid any potential problems with the bus.
always @(posedge clk_i) begin
	if (rst_ni == 0) begin
	//pmp_access_type_en <= 0;
	pmp_addr_en = 0;
	pmp_addr_reg = 0;
	dma_ctrl_en = 0;
	dma_ctrl_reg = 0;
	pmp_access_type_reg = 0;
	
end

end

========================================================
example14_i-d_t-0.7.v
//ervillereg [1:0] sec_ctl_reg, sec_ctl_new; 
//ervillereg sec_ctl_en;
// Assign 0 to register when reset is low.
// FIX:
//ervillereg [1:0] sec_prot_reg, sec_prot_new; 
//ervillereg sec_prot_en;



//// Trace



//// Wires & Regs



//// Generated





//assign valid_o = valid_d;


========================================================
example15_i-d_t-0.7.v
always @(posedge clk) begin
	if (~reset) begin
	//	start_d 	<= 'd0;
	//	length_d 	<= 'd0;
	//	source_addr_lsb_d 	<= 'd0;
	//	source_addr_msb_d <= 'd0;
	//	dest_addr_lsb_d <= 'd0;
	//	dest_addr_msb_d <= 'd0;
	//	done_d 	<= 'd0;
	//	dma_ctrl_reg 	<= 'd0;
	//	dma_ctrl_en 	<= 'd0;
	//	pmp_addr_reg 	<= 'd0;
	//	pmp_addr_en 	<=
end

end

========================================================
example16_i-d_t-0.7.v
 1) If the function of the register is to allow the DMA to access
 the Power Management Processor, then it should only be changed
 at the beginning of the DMA transaction and not at any other time.
 2) If the function of the register is to allow this module to access
 the Power Management Processor, then it should only be changed
 at the beginning of the module transaction and not at any other time.
 3) Do not initialize the register to preset values.
 4) If the register is holding a value, it should not be used to
 initialize the register at power-on-reset time.
 I/O Assignments

 DMA_STATUS_reg:
 31 - 20: Interrupt Vector Register (IVR)
 19:13: Interrupt Status Register (ISR)
 12 - 8: Request Vector Register (RVR)

end

end

========================================================
example17_i-d_t-0.7.v
 (a) Call a module that will do this when the module is instantiated.
 (b) Assign value to it during program/simulation.
 
 (d) Write code that will find the value in the register and use it.
 (e) Pass the value into the instantiated module.
 (f) Assign value to the register after the module is instantiated.
 (g) Don't assign a value to the register until the module is instantiated.
 (h) Don't assign a value to the register until the module is instantiated
 and the value is valid.
 (i) Don't assign a value to the register until the value is valid.
 (j) Don't assign a value to the register until the module is instantiated.
 (k) Don't assign a value
========================================================
example18_i-d_t-0.7.v
// assign pmp_access_type_en = (read_from_pmp) ? 1'b1 : 1'b0;





always @ (posedge clk_i)
begin
if (rst_i == 0)
begin
start_d <= 'd0;
length_d <= 'd0;
source_addr_lsb_d <= 'd0; 
source_addr_msb_d <= 'd0; 
dest_addr_lsb_d <= 'd0; 
dest_addr_msb_d <= 'd0; 
pmp_addr_reg <= 'h0; 
pmp_addr_en <= 'h0; 
dma_ctrl_reg <= 'h0; 
dma_ctrl_en <= 'h0; 
pmp_access_type_reg <= 'h
end

end

========================================================
example19_i-d_t-0.7.v
//
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========================================================
example0_i-d_t-0.9.v
 guard to prevent logging of uninitialized values
 existing values of these registers will be used as soon as they appear in the
 datapath, which may or may not be reset
 These regs present the same issues as the ones adhering to the DMA spec.
 �note: need to add a reset, since the regs are accessed before clk_i
  can get reset except at the regs are reset
 orchestrate to figure out the correct values:
 1. assign 0 values if regs are being reset.
 2. wait_request - reg, save and wait for request
 3. [56] and [58] completion - reg, save value and compare
 4. [59] start request - reg, clear wait_request
 5. [58] stop request - reg, clear wait_request and start_d/done_d
 6. reset - reg
========================================================
example1_i-d_t-0.9.v
// Fix Bits
// BIT0: Insert start_i[0] as a Parameter
// BIT1: Use new Signal INSTRUCTION[58] - don't use if don't need.

// Generate Logic
// Record Start
// Don't use if not needed.
// Record Start
// Generate Sequence
// Record Done
// Generate Done 



// */



// Global Reset (Needs to be after ALL the MMIO's are configured
// in case, let them configure, then reset.
always @(posedge clk_i or negedge nReset_i) begin
	if (~nReset_i) begin
	// case (EXE_state_type_reg)
	// IDLE: begin
	// 	// MMIO's need to have default values.
	// end
	// LOAD: begin
	
end

end

========================================================
example2_i-d_t-0.9.v
// Registers holding authorizations are not initialized when reset is low
// Authorization Registers
aternreg [2:0][9:0] configuration_reg;
aterialcontrlatus
// Control flow of program itself
snativesnake control
nodereg dma_ctrl;
unnamed nc
unnamed nc
unnamed nc
replaceable invoke impl
////////////////////////////////////////////////////////////////////////
//
// DMA Operation
//
////////////////////////////////////////////////////////////////////////
always @(posedge clk_i) 
if ((pmp_valid_o & pmp_ready_o) | (pmp_done_i & rst_i))begin
case (pmp_cmd_o) // synopsys full_case parallel_case
`DMA_CMD_INIT: 
if(pmp_data_i[2])begin
length_d = pmp_data_i
end

end

========================================================
example3_i-d_t-0.9.v
always begin
if (!reset_n)
begin
pmp_addr_en = 0;
pmp_access_type_en = 0;
pmp_ctrl_en = 0;
pmp_data_en = 0;

end

end

========================================================
example4_i-d_t-0.9.v
//��PBB
// if (!reset_i)
// assign pmp_access_type_en = 0;
// else
// assign pmp_access_type_en = 1;
// if (! reset_i) 
// begin
// pmp_access_type_reg = pmp_access_type_reg;
// end
// else
// begin
// pmp_access_type_reg = pmp_access_type_new;
// end




========================================================
example5_i-d_t-0.9.v
//�p_mux_ctlr pmp_check_i, pmp_check_o;
// riscv_soc_nios2_qsys_0_oci_tag_mux_002_0 pmp_check_reg(
// .in_i(pmp_check_i),
// .out_o(pmp_check_o)
// );
assign done_d = (done_i)? 1'b1 : 1'b0;
assign data_src_d = (data_src_i==`DATASRC_CPU) ? pmp_data_o : data_to_dma;
assign data_dst_d = (data_dst_i==`DATADST_CPU) ? pmp_data_i : data_from_dma;
assign valid_d = (state_
========================================================
example6_i-d_t-0.9.v
//� Init registers
// Once registers have been set, DMA can start.
// Resets will clear registers.
// FIX:
//DMA Control Register
always@(posedge clk_i)
begin
	if(reset_i) begin
	dma_ctrl_reg <= CTRL_IDLE; 
	pmp_addr_reg <= 'b0;
	pmp_addr_en <= 'b0;
	
end

end

========================================================
example7_i-d_t-0.9.v
 V1.0 16MAR2011 
 FIX: pmp_access_type_en must governed by dma_ctrl_en or pmp_access_type_new
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 begin
 if (~rst_i)
 pmp_access_type_en <= 1'b0;
 else
 pmp_access_type_en <= pmp_access_type_new;
 end
 BUG: Uninitialized value common for all registers that are governed by dma_ctrl_en
 always @(posedge clk_i `CFG_RESET_SENSITIVITY)
 begin
 if (~rst_i)
 begin
 dma_ctrl_reg <= 0;
 dma_ctrl_en <= 0;
end

end

========================================================
example8_i-d_t-0.9.v
// Convert the 2 to 4 security width to a 0/1 logic.
// Then compensate for the extra 2 added for SECURE & NON_SECURE connections.
assign enable_i = ~rst_i || dma_ctrl_en; 
assign master_sel_i = enable_i;
assign keep_i = enable_i;
assign source_sel_o = enable_i;
assign dest_sel_o = enable_i;
assign axi_clk = clk_i;
// Public interface.
assign valid_o = valid_o_reg;
assign valid_o_accept = valid_o_accept_reg;
assign start_o = start_o_reg;
assign start_o_accept = start_o_accept_reg;
assign done_o = done_o_reg;
assign
========================================================
example9_i-d_t-0.9.v
// This Reset is used to cause the registers to be set or cleared
// when the module is rebooting in order to avoid a glitch
// This logic is active high so that the registers can be set in the
// individual always blocks for MODPOWER.
assign pwr_up_reset_n = pclk & pwrupin & (~(rstin | scanmodein));

always @(posedge pclk or posedge preset)
begin: dma_ctrl_reg_process
if (preset)
begin
dma_ctrl_reg <= 'd0;

end

end

========================================================
example10_i-d_t-0.9.v
// Not asserting reset on load/store needs to be part of Task that
// loads/stores the security settings.
assign rst_ni = rsto;
assign load_t = load; 
assign store_t = store;
assign start_i = start|(startx);

always @(posedge clk_i ) begin

// synchronize external access to registers to main clock
dma_ctrl_reg <= dma_ctrl_new;
pmp_addr_reg <= pmp_addr_new;
pmp_access_reg <= pmp_access_type_new;
source_addr_reg <= source_addr_lsb_new;
dest_addr_reg <= dest_addr_lsb_new;

dma_ctrl_en <= (dma_ctrl != dma_ctrl_reg) | !rst_ni
end

========================================================
example11_i-d_t-0.9.v
 1. When changing
 PS to PS_EXCH_READY, don't wait for
 next PS to transition to PS_EXCH_DONE.
 2. Enable all the registers needed to write a
 load or a store when PS_EXCH_READY is high.

 PS to PS_EXCH_READY:
 Read 1. source lsb. Write 0.
 Read 2. source msb. Write 0.
 Read 3. dest lsb. Write 0.
 Read 4. dest msb. Write 0.
 Read 5. Write data lsb. Write data msb.
 Read 6. Write mask lsb. Write mask msb.
 Read 7. length lsb. Write length msb.
 Read 8. Destination address lsb. Write 0.
 Write 1. Destination address msb. Write 0.
 Read
========================================================
example12_i-d_t-0.9.v
//��琛źâŽžŤŽ«ž¯ ‘aʽĽĽ�Ľ�ť�¤��žŽ
// rst_s	, reset_s	;


// Logic to identify reset or active high DMA enable.
// msk_r	, msk_r	;

// Logic to obtain information for register addresses to be read and written.
// lsb_lat	, lsb_lat ;

// Logic to hold ongoing errors. if (dma_busy_reg[0]) init error found.
// ƽ�ʹ��ʱ�ƽ�ͷ����Ĵ������Ѱ
// ȫ������ĵ���������������������ĸ�Ĵ������ͷź��Ҫʱ�ӱ�һï
========================================================
example13_i-d_t-0.9.v
//��utokushima::reg done_disable_lsb_reg, done_disable_lsb_new;
//��utokushima::reg done_disable_lsb_en, done_disable_lsb_en_new;

// END ILLEGAL CLOCKPULL AREA CODE

========================================================
example14_i-d_t-0.9.v
//�boy 
always @(posedge rst_n_i or posedge clk_i) 
begin
if(!rst_n_i)
begin
pmp_access_type_reg <= pmp_access_type_reg;
pmp_addr_reg <= pmp_addr_reg;
pmp_data_reg_lf <= 'b0;
pmp_data_reg_hf <= 'b0;
pmp_data_reg_nxt <= 'b0;
pmp_data_reg_dma <= 'b0;
pmp_data_reg_cmd <= 'b0;
pmp_data_reg_stat <= 'b0;
pmp_data_reg_sdoin <= 'b0;
pmp_data_reg_ack <= 'b0;
pmp_data_reg_cf
end

end

========================================================
example15_i-d_t-0.9.v
`timescale 1ns/1ns

module mips
(
// INPUT:
inout [7:0] io,

// OUTPUT:
output [3:0] o,

// FPGA IO
output VCC,
output GND,
input [3:0] drive,
input [3:0] pull,
output [3:0] mark,
// ACTIVE LOW
output sys_clk_p,
output sys_clk_n,
output sys_rst,
output sys_dbg_cpu_reset,
output cpu_en,
output cpu_greset,
output cpu_gscanenable,
output cpu_gclk,
output cpu_gscanmode,
output dbg_en,
output apb_penable,
output [`APB_PADDR_WIDTH-1:0
========================================================
example16_i-d_t-0.9.v
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 Default Value:
 front_
========================================================
example17_i-d_t-0.9.v
//��︻Ķ匹ӹݿ֧汕
//asymmetrical DMA ping pong example (incorporates FIFO/RISC DMA model)
//ÄÇ¥¶§ƽǶ߼ĽĽӼ

// Timing:
//	interrupt is asserted after receiving done_i
// Also, note that the address signals are asserted on the negative clock edge
// Again, dataout is asserted on the following clock edge.


// Inputs
regn pmp_clk_i	(clk_i,rst_i,pmp_clk_en,pmp_clk_d);


regn irq_i	(clk_i,rst_i,irq_en,irq_d);
regn nmi_i	(clk_i,rst_
========================================================
example18_i-d_t-0.9.v
// UPDATE:
// Add the DMA Control register.
always @(posedge clk_i or negedge rst_i) begin
if (~rst_i) begin
dma_ctrl_reg[15:0] <= 16'd0; // default 16'h0 (no descriptor loading, DMA disabled)
dma_ctrl_reg[17] <= 1'b0;
done_d[15:0] <= 16'd0;

end

end

========================================================
example19_i-d_t-0.9.v
// Inputs for Program Memory server ports.
// 1. start_i signal coming from the command 
// 2. start_d signal coming from the cpu
// 3. done_i signal coming from DMA
// 4. done_d signal coming from DMA
// 5. run_i signal going to DPSC 
// 6. run_d signal going to DPSC
// 7. xfer_done signal from DPSC for the DMA 
// 8. xfer_done signal from DPSC for the cpu 

// These are the two signals to check when there is a start.
// enable_i - Asserted when a load has been issued.
// enable_d - Asserted the the cpu has loaded the request.
// Done signals of DMA and DPSC need to be checked also.

// The DMA needs to generate an xfer_done signal also for 

========================================================
example0_i-e_t-0.1.v
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 BUG:
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========================================================
example1_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example2_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example3_i-e_t-0.1.v
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 BUG:
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========================================================
example4_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example0_i-e_t-0.3.v
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========================================================
example1_i-e_t-0.3.v
�if (!rst_ni) begin
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end

========================================================
example2_i-e_t-0.3.v
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========================================================
example3_i-e_t-0.3.v
//�ªÄþÄþÄþÄþ
//�ªÄþÄþÄþÄþÄþÄþÄþÄþÄþÄþÄþÄþÄþ
//�ªÄþÄþÄþÄþÄþÄþÄþÄþÄþ
//�ªÄþÄþÄþÄþ
// BUG:
//�ªÄþÄþ
// BUG:
//�ªÄþ
// BUG:
//åªÄþ
// BUG:
//åªÄþ

========================================================
example4_i-e_t-0.3.v
��
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
========================================================
example0_i-e_t-0.5.v
//��¿éÐÐÑùÀÖÐ¶µÄÊÇÓÐÎÊÌâµÄ
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp_write_reg
auton_pmp_read_reg
auton_pmp
========================================================
example1_i-e_t-0.5.v
�if (!rst_ni) begin
��access_en <= 0;
'
end

========================================================
example2_i-e_t-0.5.v
//��ÏþÖÊÐÞÕý
always @ (posedge clk_i or negedge rst_ni) begin
�Ç¥Ð¤Ë¤Ê¤ë
�Ç¥Ð¤Ë¤Ê¤ë

end

========================================================
example3_i-e_t-0.5.v
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 ¥ª¥Õ¥¡¥¤¥È¥¦¥¯¥¤¥¹¤Î¤Ê¤Î¤Ç¤Ê¤¤¡£
 ¥ª¥Õ¥¡¥¤¥È¥¦¥¯¥¤¥¹¤�
========================================================
example4_i-e_t-0.5.v
//��查
always @ (posedge clk_i or negedge rst_ni) begin
��查
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end

========================================================
example0_i-e_t-0.7.v
//��ʱ֣�ʱ߼� ʱ��ܽ�׼���ʱ�Ӱ�
//�Ѽ�� ʱ�Ӱ�pmp_access_type_en
//�Ѽ�� ʱ�Ӱ�pmp_access_type_reg
//'Ѽ�� ʱ�Ӱ�pmp_access_type_new
//'Ѽ�� ʱ�Ӱ�pmp_access_type_reg
//'Ѽ�� ʱ�Ӱ�pmp_access_type_en
//'Ѽ�� ʱ�Ӱ�pmp_access_type_en
//'Ѽ�� ʱ�Ӱ�pmp_access_type_en


always @ (posedge clk_i or negedge rst_ni) begin
// B
end

========================================================
example1_i-e_t-0.7.v
�
�
 Access Control Logic

 Logic for generating START, STOP, and VALID signals. 

 This is not a generic controller. It is implementation-specific and 
 designed to work with the AXIS DMA controller. 

 The implementation uses pctl.v, which is an AXIS-specific implementation of 
 the AXI protocol. 

 The implementation uses a security address (SA) to allow a secure 
 communication between the SA and an unsecure device. The SA is 
 the combination of the source and destination addresses with the 
 start_i and length_i signals. The valid_o signal is used to 
 indicate the presence of a valid transaction.

 The implementation uses a "pmp" to transfer a packet. The term 
 "packet" refers to a set of data and control
========================================================
example2_i-e_t-0.7.v
//� access_en;
//� pmp_access_type_en;
//' dma_ctrl_en;
// assignment of fields in registers
always @(posedge clk_i or negedge rst_ni) begin
 if (!rst_ni) begin
 pmp_access_type_en <= 0;
 access_en <= 0;
 dma_ctrl_en <= 0;
 end else begin
 pmp_access_type_en <= pmp_access_type_reg;
 access_en <= access_type_reg;
 dma_ctrl_en <= dma_ctrl_reg;
 end

end

========================================================
example3_i-e_t-0.7.v
//�ÊÐíaccess_en = 1'b1;
//�ÊÐípmp_access_type_en = 1'b1;
//¸´ÖÆÏµÊý
//FIX:
// pmp_access_type_en = 1;
// pmp_access_type_en = 0;
//¸´ÖÆÖ¸Ïò
//FIX:
// pmp_access_type_en = 0;
// pmp_access_type_en = 1;
//ÏòÁ¿
//FIX:
// pmp_access_type_en = 1;
// pmp_access_type_en = 0;
//¹¹Ôì
//FIX:
// pmp_access_type_en = 0;

========================================================
example4_i-e_t-0.7.v
�òÎÐ»ÝÅÜ¼Æ
 The following lines are generated in the lab, so as to not have to use 
 a simulation tool.

 YOSYS: This is an example of a program with the Task priority scheduler. 
 YOSYS: It is a compiled and verified .v file.
 YOSYS: Copyright 2010 University of Washington
 YOSYS: License: http:creativecommons.org/licenses/by/3.0/
 YOSYS: Modifications: Adapted from beryllium to beryllium

 Task Priority Scheduler

 This program is based on the beryllium example, but is updated to use 
 a task instead of a task priority to ensure that the correct 
 priority is used.

 Initialize all registers
========================================================
example0_i-e_t-0.9.v
//����ƽpmp_access_type_reg;
/+
// Fixed:
// prot_addr_en_i, prot_addr_en_i_part2;
// Fixed:
// prot_addr_en_o;
/+
// Fixed:
// prot_addr_en_o;
/+
// Fixed
// prot_addr_we_o;
/+
// Fixed:
// prot_szeroon_i, prot_szeroon_o;
// Fixed:
// prot_en_o;
// Fixed:
// prot_nx_i, prot_nx_o;
// Fixed:
// prot_en_nxt_i;
///////// Debug Printouts. ///////////
option print_level; 
//always @ (pmp_access_type_o or prot_en_nxt_i or prot_en
========================================================
example1_i-e_t-0.9.v
//�� 压：DMA_CTRL
//DMA_CTRL 
assign chacha_ctrl_fsm_state_cur = {
	(start_i == 1'b0 && length_i > 1'h0 && ~done_i) | 
	start_i |
	(done_i & ~valid_o) |
	(chacha_ctrl_fsm_state == CTRL_IDLE) |
	(chacha_ctrl_fsm_state == CTRL_START),
	((length_i == 1'h0 && done_i) | (chacha_ctrl_fsm_state == CTRL_DONE)) & ((start_i & (length_i > 1'h1)) | (chacha_ctrl_fsm_state == CTRL_IDLE))
};
assign chacha_ctrl_fsm_
========================================================
example2_i-e_t-0.9.v
//�¡¥¶£¨£¨¡ª¡ª¨
// ALSO: 
//�¡¥¶é¥Á´íÅÊ¡ª¥Ì¥Ã¥¯
// ALWAYS block for DMA_CTRL is placed in siu_gen2.v
ositydma_ctrl dma_ctrl_i1(
.clk(clk_i),
.rst(rst_ni),
.dma_req1(dma_req[0]),
.dma_req2(dma_req[1]),
.dma_req3(dma_req[2]),
.dma_req4(dma_req[3]),
.dma_req5(dma_req[4]),
.dma_req6(dma_req[
========================================================
example3_i-e_t-0.9.v
//�å→roduct_start_tstamp, 
//�å→uffile_start_tstamp;

========================================================
example4_i-e_t-0.9.v
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========================================================
example5_i-e_t-0.1.v
�if (!rst_ni) begin
��access_en <= 0;
'endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
========================================================
example6_i-e_t-0.1.v
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========================================================
example7_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example8_i-e_t-0.1.v
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========================================================
example9_i-e_t-0.1.v
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========================================================
example5_i-e_t-0.3.v
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========================================================
example6_i-e_t-0.3.v
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========================================================
example7_i-e_t-0.3.v
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========================================================
example8_i-e_t-0.3.v
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 ALWAYS @ (posedge clk_i or negedge rst_ni) begin
 ALWAYS @ (posedge clk_i or ne
end

end

end

end

========================================================
example9_i-e_t-0.3.v
�if (!rst_ni) begin
��access_en <= 0;
'endif
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
========================================================
example5_i-e_t-0.5.v
//����ʱ��ֻ�����Ĵ���
// ALWAYS @ (posedge clk_i or negedge rst_ni) begin
//�������ź��Ĵ���
//�������ź��Ĵ���
// ALWAYS @ (posedge clk_i or negedge rst_ni) begin
// ALWAYS @ (posedge clk_i or negedge rst_ni) begin
////// DMA CONTROL REGISTERS ///////
always @ (posedge clk_i or negedge rst_ni) begin
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_CTRL Register
// DMA_
end

========================================================
example6_i-e_t-0.5.v
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========================================================
example7_i-e_t-0.5.v
�pmp_access_type_en <= pmp_access_type_reg;
�pmp_access_type_en <= pmp_access_type_reg;
�pmp_access_type_en <= pmp_access_type_reg;
�pmp_access_type_en <= pmp_access_type_reg;
�pmp_access_type_en <= pmp_access_type_reg;
’pmp_access_type_en <= pmp_access_type_reg;
’pmp_access_type_en <= pmp_access_type_reg;
’pmp_access_type_en <= pmp_access_type_reg;
’pmp_access_type_en <= pmp_access_type_reg;
’pmp_access
========================================================
example8_i-e_t-0.5.v
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========================================================
example9_i-e_t-0.5.v
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עצ
========================================================
example5_i-e_t-0.7.v
//���
always @(posedge clk_i or negedge rst_ni) begin
�
// if (!rst_ni) begin
//�
// END BUG:

end

========================================================
example6_i-e_t-0.7.v
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========================================================
example7_i-e_t-0.7.v
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�éíãðàíÿðñêðàíâñêðàíèòðîãðàíèðîâ
�éíãðàíÿðñêðàíèðîâ
åéíãðàíÿðñêðàíèðîâ
ascd
 BUG:
�éíãðàíÿðñêðàíèðîâ
fixed
 BUG:
UDP:
always@(posedge clk_i or negedge rst_ni) begin
if (!
end

========================================================
example8_i-e_t-0.7.v
��reg pmp_access_type_en;
else if ((DRI_bypass_reg == 0) && (loader_done == 1)) begin


















































































end

========================================================
example9_i-e_t-0.7.v
//����Ѱ��
always @ (posedge clk_i or negedge rst_ni) begin
�������%�ķ������?
��״̬�������

end

========================================================
example5_i-e_t-0.9.v
//� make menu: All come from menu.v
 avenueasyncint 
avoredy := 1'b0;
BCD_DECODERasync_gated#(Param1, Param2)
bcd22_i(
// BCR
parameter WD= Param1-1, // 0:7
parameter TD= Param2-1,
// WCR
parameter PP=0, // 1:4
BCR_DATA_WIDTH= Param1-2, // 8:8, 16:15, 24:22, 32:23
BCR_BE= Param2-2, // 0:3
BCR_AE= Param2-1, // 0:1
BCR_DME= Param2-0, // 0:0
BCR_DPO= Param2-3, // 0:0, 1:1
BCR_SSOE=
========================================================
example6_i-e_t-0.9.v
//�endif

========================================================
example7_i-e_t-0.9.v
��if (!rst_ni) begin
�ּŽ�����ײ�û������
�ֹ����������Ե�ʱ�߳ײ�����߳��߼��Ӧ��'b0 

end

========================================================
example8_i-e_t-0.9.v
//�ski
//`include "soc_system_tv_decoder_mm_interconnect_0_avalon_st_adapter.v"
//`include "soc_system_tv_decoder_mm_interconnect_0_avalon_st_adapter_error_adapter.v"
//`include "soc_system_tv_decoder_mm_interconnect_0_avalon_st_adapter_sysid_qsys.v"
`include "soc_system_tv_decoder_mm_interconnect_0_avalon_st_adapter_sysid.v"
//`include "soc_system_tv_decoder_mm_interconnect_0_avalon_st_adapter_pulse.v"
//
/**
 * avalon_st_adapter_0.v
 *
 * \additional information regarding
========================================================
example9_i-e_t-0.9.v
//�conomic logic for writing flops
always@(posedge clk_i or negedge rst_ni) begin
//łUźśŚ wyżźą
if (!rst_ni) begin
new_pmp_addr<=0;
pmp_access_type_reg<=0;
access_en<=0;
done_d<=0;
pmp_access_type_en<=0;
amount_reg <= 0;

end

end

========================================================
example10_i-e_t-0.1.v
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 BUG:
�ª¥Õ¥ì¥ó¥È¥Ö¥ë¥¯¥é¥¹
 FIX:
�ª¥Õ¥ì¥ó¥È¥Ö¥ë¥¯¥é¥¹
 BUG:

========================================================
example11_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example12_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example13_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example14_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example10_i-e_t-0.3.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example11_i-e_t-0.3.v
//�ª¥Ö¥µ¥¤¥È¤Î¥Î¥¤¥¯¥È¡¤¥ª¥Ö¥µ¥¤¥È
//�ª¥Ö¥µ¥¤¥È¤Î¥Î¥¤¥¯¥È¡¤¥ª¥Ö¥µ¥¤¥È
// ALWAYS: pmp_access_type_en
// ALWAYS: pmp_access_type_reg
// ALWAYS: pmp_access_type_new
// ALWAYS: pmp_access_type_en
// ALWAYS: pmp_access_type_new
// ALWAYS: pmp_access_type_reg

========================================================
example12_i-e_t-0.3.v
//�if (!rst_ni) begin
//��if (!rst_ni) begin
//'�if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin
//'if (!rst_ni) begin

========================================================
example13_i-e_t-0.3.v
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========================================================
example14_i-e_t-0.3.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'�
end

========================================================
example10_i-e_t-0.5.v
�if (!rst_ni) begin
��if (rst_ni) begin
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h0;
'h
end

end

========================================================
example11_i-e_t-0.5.v
��错设计信息：
1、如何保存设计信息？
2、如何存储设计信息？
3、如何存储设计信息？
4、如何存储设计信息？
5、如何存储设计信息？
6、如何存储设计信息？
7、如何存储设计信息�
========================================================
example12_i-e_t-0.5.v
�ensure(rst_ni, posedge clk_i); 
�ensure(rst_ni, negedge clk_i);
�ensure(rst_ni, posedge clk_i);
�ensure(rst_ni, negedge clk_i);
�ensure(rst_ni, posedge clk_i);
`ensure(rst_ni, negedge clk_i);
`ensure(rst_ni, posedge clk_i);
`ensure(rst_ni, negedge clk_i);
`ensure(rst_ni, posedge clk_i);
`ensure(rst_ni, negedge clk_i);
`ensure(rst_ni, posedge clk
========================================================
example13_i-e_t-0.5.v
�¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥¥
========================================================
example14_i-e_t-0.5.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
��
end

========================================================
example10_i-e_t-0.7.v
�é¥á¥ó¥Ò¡A¥Ý¡A¥¤¥ó¥¿¤¬¤Ç¤­¤ë¤¬¤Î¤Ç¤¹¡A¤³¤Î¤Å¤¤¤¿¤¤¡B
�«¤¸¤¬¤¤¤¿¤¤¤Ë¤¬¤¤¤Ç¡A¤³¤Î¤Å¤¤¤¿¤¤¡B
�«¤¸¤¬¤¤¤¿¤¤¤Ë¤¬¤¤
========================================================
example11_i-e_t-0.7.v
//�ò
always @ (posedge clk_i or negedge rst_ni) begin
��

end

========================================================
example12_i-e_t-0.7.v
�¡¥¸¥­¥¯¥Õ¥¡¥µ¥¤¥¯¥Ç¥£¥¯¥Î¥¿¥¹
�¼¥¯¥¿¥¹
�¼¥¯¥¹
assign access_en = (pmp_access_type == riscv_pmp_access_type_write) ? 1 : 0; 
assign access_en = (pmp_access_type == riscv_pmp_access_type_read) ? 1 : 0; 
assign access_en = (pmp_access_type == riscv_pmp_access_type_write) ? 1 : 0; 
assign access_en = (pmp_
========================================================
example13_i-e_t-0.7.v
//��
always @ (posedge clk_i or negedge rst_ni) begin
ਖ਼
姧


end

========================================================
example14_i-e_t-0.7.v
//�$setuphold (posedge clk_i, negedge rst_ni, 0, 0, notifier, , ,dma_ctrl_en, 0);
//�$setuphold (posedge clk_i, negedge rst_ni, 0, 0, notifier, , ,dma_ctrl_en, 0);
�$setuphold (posedge clk_i, negedge rst_ni, 0, 0, notifier);
�$setuphold (posedge clk_i, negedge rst_ni, 0, 0, notifier);
// FIX:
//�$setuphold (posedge clk_i, negedge rst_ni, 0, 0, notifier);
//�$setuphold (posedge clk_i, negedge rst_ni, 0, 0,
========================================================
example10_i-e_t-0.9.v
�� en
---------------Input Command Termination-------------------------------------

check input signals
---------------Fetching Read or Write------------------------------------------

---------------Memory Read or Memory Write------------------------------------

---------------Checking Start or Length-----------------------------------------

---------------Setting Up Start and Length---------------------------------------

---------------Disable Write if DMA_CTRL_DEST_ID = 0 for Memory Write--------------------

---------------Cleaning Up-----------------------------------------------------

---------------Synchronization----------------------------------------------

---------------Creating Internal Register---------------------------------------

---------------Generating Non-Cacheable Address---------------------------------

---------------Outputing Final Values------------------------------------------------

---------------Signal Generation----------------------------------------------

---------------Synchronization------------------------------------------------


















========================================================
example11_i-e_t-0.9.v
� COMMENTED FOR S10/ECP5 PORTING
䖋旋期鎷峰宸訳厤䕊敊:
 ALWAYS @(posedge clk_i or negedge reset) begin
 if (!reset)
 pmp_access_type_en <= 0;
 else
 pmp_access_type_en <= pmp_access_type_reg;
 end
 ALWAYS @(posedge clk_i or negedge reset) begin
 if (!reset)
 access_en <= 0;
 else
 access_en <= access_reg;
 end
 ALWAYS @(posedge clk_i or negedge reset) begin
 if (!reset)
 pmp_access_type_en <= 0;
 else
 pmp_access
end

========================================================
example12_i-e_t-0.9.v
//�timescale 1ns / 1ps
// timescale 1ns / 1ps

// `define STAGE_RESET(reset)
// `define STAGE_WAIT_PREPARE()
`define STAGE_DONE(done)
// `include "Arbiter_define.vh"

`include "inch.v"

module dxxpdo # (

)
 (
// wishbone slave port
input wire 
`ifdef DATA_BUS_WIDTH_8
// Data Wishbone 8-bit R/W port
// -----------------------------------------
// Command Registers Configuration
// -----------------------------------------
// Command Address Decoders
//
// Each command register can be written to, and its values can be read
// from it.
//
// All of the command-registers start with a single 3-bit field / register:
// * [1:
========================================================
example13_i-e_t-0.9.v
//��门开启?
escalefif(rst_ni) begin
���������?���������?
scaler_mode <= 0;
scaler_enable <= 0;
d_write <= 0;
d_read <= 0;
pmp_address <= 'b0;
pmp_wr_msb <= 'b0;
pmp_wr_middle <= 'b0;
pmp_wr_lsb <= 'b0;
pmp_rd_msb <= 'b0;
pmp_rd_middle <= 'b0;
pmp_rd_lsb <= 'b0;
running <= 1;
sclerscale_mode <= 0;
we_m <= 0;
we_s <= 0;
������

end

========================================================
example14_i-e_t-0.9.v
//���š¤ß¹³øÕª¶¼óçÝ®¹³¥¥¿¶¹
ernautreg oper_mode_reg, oper_mode_new;// riscv::MODE_NORMAL or riscv::MODE_COMPARE
// BUG:
//�ª·¯²¶¶¹
// endpoint// pwr settings
erentreg [15:0][53:0] prescale_i;//prescale_i[15:0] = prescale_i_int[15:0]; // yes, have to multiply by 2
// endpoint//// Parameters

========================================================
example15_i-e_t-0.1.v
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 BUG:
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 FIX:
��
========================================================
example16_i-e_t-0.1.v
�if (!rst_ni) begin
��pmp_access_type_en <= 0;
'
end

========================================================
example17_i-e_t-0.1.v
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 BUG:
�ª¥Õ¥¡¥�
========================================================
example18_i-e_t-0.1.v
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========================================================
example19_i-e_t-0.1.v
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========================================================
example15_i-e_t-0.3.v
��
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`ifndef SYNTHESIS
`define SYNTHESIS
 
`ifndef SYNTHESIS
`define SYNTHESIS
 
`include "macro.v"
`include "axis_cpu_defs.vh"
`include "axis_cpu_defs.vh"
`include "axis_cpu_macros.vh"
`include "axis_cpu_macros.vh"
`include "axis_cpu_dma_macros.vh"
`include "axis_cpu_dma_macros.vh"
`include "axis_cpu_dma_mux_macros.vh"
`include "axis_cpu_dma_mux_macros.v
========================================================
example16_i-e_t-0.3.v
�if (!rst_ni) begin
��if (!rst_ni) begin
’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’’
end

end

========================================================
example17_i-e_t-0.3.v
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========================================================
example18_i-e_t-0.3.v
����ַ�Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ���Ĵ����
========================================================
example19_i-e_t-0.3.v
�ʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱʱ
========================================================
example15_i-e_t-0.5.v
//��reg pmp_access_type_en;
always @ (posedge clk_i or negedge rst_ni) begin
��if (!rst_ni) begin
���pmp_access_type_en <= 0;
���
end

end

========================================================
example16_i-e_t-0.5.v
//��
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// DMA MNGT
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========================================================
example17_i-e_t-0.5.v
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========================================================
example18_i-e_t-0.5.v
//�FIX:
//�FIX:
//�FIX:
//�FIX:
//�FIX:
//�FIX:
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========================================================
example19_i-e_t-0.5.v
���ʱ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ�ʱ�ͬ��
========================================================
example15_i-e_t-0.7.v
�¶³ÆÖØÐÂÐ¶ÔØ£¬ÒÔ¼õÉÙÒªÇóµÄ¹ýÂËÆ÷
ÔÝÊ±²»ÔÊÐíÉèÖÃ
 ALWAYS @ (posedge clk_i) begin
�Ï´æ
 access_en <= pmp_access_type_en;
 end
 end
 ALWAYS @ (posedge clk_i) begin
 if (rst_ni) begin
�Ï´æ
 pmp_access_type_en <= 0;
 end
 else begin
 pmp_access_type_en <= pmp_access_type_en;
 end
 
 
========================================================
example16_i-e_t-0.7.v
�íÎó:Ç¶Ïò¼ì²âÒª¸Ä¶¯,Èç¹ûpmp_access_typeµÄÖµ¶¼Îª0,
ËµÃ÷:ÏµÍ³¼ì²âµÄÊ±ºò,Èç¹ûpmp_access_type_regÎª0,
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========================================================
example17_i-e_t-0.7.v
//���е坯鏍�?Ϊ�?��?��?
always @ (posedge clk_i or negedge rst_ni) begin
if (!rst_ni) begin
pmp_access_type_reg <= 'h0;
pmp_access_type_en <= 0;

end

end

========================================================
example18_i-e_t-0.7.v
//�if (!rst_ni) begin
//��access_en =0;
//'endif;
//'endif;

========================================================
example19_i-e_t-0.7.v
// anecdote: access_type must be set before start_i/rst_i
// anecdote: access_type can only be set once.
// anecdote: access_type cannot be changed after dma_ctrl_reg is set.
// anecdote: access_type is a part of dma_ctrl_reg, which will be updated when dma_ctrl_reg is updated.
// anecdote: access_type should be a part of dma_ctrl_en, not access_en
// FIX:
// anecdote: access_en and pmp_access_type_en should be a part of dma_ctrl_en
// FIX:
// anecdote: access_en and pmp_access_type_en should be a part of dma_ctrl_en
// FIX:
// anecdote: access_en and pmp_access_type_en should be a part of dma_ctrl_en

========================================================
example15_i-e_t-0.9.v
//�assign pmp_access_type_en = access_en;	
assign pmp_access_type = pmp_access_type_en & pmp_access_type_reg;
always @ (posedge clk_i or negedge rst_ni) begin
�if (!rst_ni) begin
�ERROR_HANDLING: 
merce; 

end

end

========================================================
example16_i-e_t-0.9.v
//�水平对“全是地址”进行重置，只修改地址的位并返回结果
always @* begin
pmp_access_type_reg <= pmp_access_type_new;
pmp_addr_reg <= pmp_addr_new;

end

========================================================
example17_i-e_t-0.9.v
//VERTISEMENT:
// Insert IDP code in this line
// DEPENDENCIES:
// STANDARD:
//`include "idp_const.vh"
// CONFIG:
`define IDP_STACKGENERIC_PARAM 
// VERSION:
// 1.0.0
// CHANGELOG:
// 1.0.0
// 2018:06:05:11:07:21:SJ cbxa
//
//STARTUP.m4
//Do not edit this line
//TAG = 8'b01001000
 
//Copyright (C) 2018-2020 Intel Corporation All Rights Reserved.
//Your use of Intel Corporation's design tools, logic functions 
//and other software and tools, and its AMPP partner logic 
//functions, and any output files from any of the foregoing 
//(including device programming or simulation files
========================================================
example18_i-e_t-0.9.v
//��
always @ (posedge clk_i or negedge rst_ni) begin
��if (!rst_ni) begin
//��pmp_access_type_en <= 0;
//��
end

end

========================================================
example19_i-e_t-0.9.v
//�é€“atama

========================================================
