example0_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example1_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example2_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example3_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example4_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example5_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example6_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example7_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example8_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example9_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example10_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example11_i-a_t-0.1.v
 if (irq_i[1]) begin
========================================================
example12_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example13_i-a_t-0.1.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example14_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example15_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example16_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example17_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example18_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example19_i-a_t-0.1.v
 if (|mip_q || debug_req_i) begin
========================================================
example0_i-a_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example1_i-a_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example2_i-a_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example3_i-a_t-0.3.v
 if (irq_i[1]) begin
========================================================
example4_i-a_t-0.3.v
 if we are in debug mode, we need to be un-stalled, otherwise we
========================================================
example5_i-a_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example6_i-a_t-0.3.v
 if (|mip_q && debug_req_i) begin
========================================================
example7_i-a_t-0.3.v
 this is not correct.
========================================================
example8_i-a_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example9_i-a_t-0.3.v
 if (|mip_q || debug_req_i) begin
========================================================
example10_i-a_t-0.3.v
 if (|mip_q || debug_req_i) begin
========================================================
example11_i-a_t-0.3.v
 if (|mip_q || debug_req_i) begin
========================================================
example12_i-a_t-0.3.v
 if (|mip_q || debug_req_i)
========================================================
example13_i-a_t-0.3.v
 if (irq_i[1]) begin
========================================================
example14_i-a_t-0.3.v
 if (irq_i[1]) begin
========================================================
example15_i-a_t-0.3.v
 if (|mip_q || irq_i[1]) begin
========================================================
example16_i-a_t-0.3.v
 if we are in debug mode we can have interrupts
========================================================
example17_i-a_t-0.3.v
 if we are in debug mode, then we need to stall the core
========================================================
example18_i-a_t-0.3.v
 if we are in debug mode, we will not be stalled by interrupts
========================================================
example19_i-a_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example0_i-a_t-0.5.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example1_i-a_t-0.5.v
 if (irq_i == 1'b1 && !wfi_q) begin
========================================================
example2_i-a_t-0.5.v
 if (mip_q) begin
========================================================
example3_i-a_t-0.5.v
 we use the mip as bit 1 of the irq vector
========================================================
example4_i-a_t-0.5.v
 if we want to enter debug mode, we need to be in debug mode
========================================================
example5_i-a_t-0.5.v
 - we need to have the way to stall the core from the outside
========================================================
example6_i-a_t-0.5.v
 if (irq_i[1]) begin
========================================================
example7_i-a_t-0.5.v
 if we are in debug mode, then we don't want to stall the core
========================================================
example8_i-a_t-0.5.v
 we can't just un-stall the core right away, because we may turn on
========================================================
example9_i-a_t-0.5.v
 if (|mip_q || debug_req_i) begin
========================================================
example10_i-a_t-0.5.v
 if we have an interrupt pending then we are going to wait for it.
========================================================
example11_i-a_t-0.5.v
 if (irq_i[1]) begin
========================================================
example12_i-a_t-0.5.v
 the WFI is still active, and therefore we will miss the
========================================================
example13_i-a_t-0.5.v
 this is a quick hack to prevent the core from being stalled
========================================================
example14_i-a_t-0.5.v
 wait for interrupt only if it is enabled (and if there is an interrupt)
========================================================
example15_i-a_t-0.5.v
 if (irq_i[1] && !mip_q && !debug_mode_q && !wfi_q && !debug_mode_q)
========================================================
example16_i-a_t-0.5.v
 if (wfi_q) begin
========================================================
example17_i-a_t-0.5.v
 1.
========================================================
example18_i-a_t-0.5.v
is_debug_mode_q = 1'b0;
========================================================
example19_i-a_t-0.5.v
 if there is a pending interrupt, we stall the core
========================================================
example0_i-a_t-0.7.v
 it's not possible to use the interrupts right now because they are
========================================================
example1_i-a_t-0.7.v
 at the time of write back of the status reg
========================================================
example2_i-a_t-0.7.v
 we need to wake up the core if the core is requested to be
========================================================
example3_i-a_t-0.7.v
 if (riscv_debug_i) begin
========================================================
example4_i-a_t-0.7.v
 assign wfi_d = (wfi | wfi_q);
========================================================
example5_i-a_t-0.7.v
 we can't do this or the core will just sit there
========================================================
example6_i-a_t-0.7.v
 the comments are related to the hardware implementation of the riscv v1.0 cpu
========================================================
example7_i-a_t-0.7.v
 we don't need mip_q in the if condition
========================================================
example8_i-a_t-0.7.v
 this works for now but we have to check if irq is active or not. We
========================================================
example9_i-a_t-0.7.v
 always @(posedge clk or posedge rst)
========================================================
example10_i-a_t-0.7.v
 if (!mip_q && !debug_req_i && irq_i[1])
========================================================
example11_i-a_t-0.7.v
 WISH:
========================================================
example12_i-a_t-0.7.v
step_q = 1'b0;
========================================================
example13_i-a_t-0.7.v
 Irq's are treated as 1 at the time when in the isr
========================================================
example14_i-a_t-0.7.v
 this prevents the core to be stalled if interrupts are not serviced
========================================================
example15_i-a_t-0.7.v

========================================================
example16_i-a_t-0.7.v
 when i-stage is completed, we can safely un-stall the core, even if the
========================================================
example17_i-a_t-0.7.v
 if the interrupt is either not pending, or we are in debug mode we skip
========================================================
example18_i-a_t-0.7.v
 wait for interrupt or debug mode
========================================================
example19_i-a_t-0.7.v
 *c
========================================================
example0_i-a_t-0.9.v
if ((|mip_q) || debug_req_i) begin
========================================================
example1_i-a_t-0.9.v
 listen on VA bit for any interrupts
========================================================
example2_i-a_t-0.9.v
// artillery.conf


========================================================
example3_i-a_t-0.9.v
 elementwise comparison is not working here
========================================================
example4_i-a_t-0.9.v
 until_i16_flask_in comes from i 16 and i 5
========================================================
example5_i-a_t-0.9.v
 this could cause problem with ir detection
========================================================
example6_i-a_t-0.9.v
 assigns interrupts are issued by csr
========================================================
example7_i-a_t-0.9.v
assign wfi_to_g = |wfi_q && !debug_q;
========================================================
example8_i-a_t-0.9.v
 set sp.wfi on core (sp:wif:wfi -> wfi)
========================================================
example9_i-a_t-0.9.v
 Also if a machine reset is requested, dcpu_reset_n should be reset
========================================================
example10_i-a_t-0.9.v
 a) impact on mips32_ejtag.v; the status registers have changed, and
========================================================
example11_i-a_t-0.9.v
 workaround
========================================================
example12_i-a_t-0.9.v
 The normal WFI flow sets the decrementer to cmax. Since on the next cycle it is
========================================================
example13_i-a_t-0.9.v
 NEVER DO THIS.
========================================================
example14_i-a_t-0.9.v
 allow interrupts from the primary CPZ CIP to enter debug
========================================================
example15_i-a_t-0.9.v
 merely ack the interrupt, and re-enable it
========================================================
example16_i-a_t-0.9.v
 invoke_debug_0: if ()
========================================================
example17_i-a_t-0.9.v
 do not wait for interrupts until first cycle of the cycle for the mips processor
========================================================
example18_i-a_t-0.9.v
 is this correct?
========================================================
example19_i-a_t-0.9.v
if( mip_to_wip_works )
========================================================
example0_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example1_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example2_i-b_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example3_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example4_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example5_i-b_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example6_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example7_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example8_i-b_t-0.1.v
 if we have a debug request, we can override the locks
========================================================
example9_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example10_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example11_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example12_i-b_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example13_i-b_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example14_i-b_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example15_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example16_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example17_i-b_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example18_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example19_i-b_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example0_i-b_t-0.3.v
 if we have an interrupt pending and we are in debug mode, then we need to
========================================================
example1_i-b_t-0.3.v
 if we have a debug request, then we can override the locks
========================================================
example2_i-b_t-0.3.v
 if we are in debug mode, we can override the locks
========================================================
example3_i-b_t-0.3.v
 wait for the interrupt register to be set
========================================================
example4_i-b_t-0.3.v
 wait for interrupt only when we are not in debug mode or when we are in debug mode and we are in debug mode
========================================================
example5_i-b_t-0.3.v
 wait for interrupt only if we are not in debug mode
========================================================
example6_i-b_t-0.3.v
 if we want to enter debug mode, we need to have the WFI bit set to 1,
========================================================
example7_i-b_t-0.3.v
 wait for interrupt and then clear it
========================================================
example8_i-b_t-0.3.v
 if we are in debug mode, then we can override the locks
========================================================
example9_i-b_t-0.3.v
 if we are in debug mode, we allow interrupts to be
========================================================
example10_i-b_t-0.3.v
 if we are in debug mode, then we can override the locks
========================================================
example11_i-b_t-0.3.v
 if the core is already in debug mode, then it will be un-stalled
========================================================
example12_i-b_t-0.3.v
 if we have debug mode, we can override the locks
========================================================
example13_i-b_t-0.3.v
 wait for interrupt is not required for debug mode.
========================================================
example14_i-b_t-0.3.v
 if we have a debug request or an interrupt request
========================================================
example15_i-b_t-0.3.v
 if we are in debug mode, then we can override the locks
========================================================
example16_i-b_t-0.3.v
 if we are in debug mode, we can override the locks
========================================================
example17_i-b_t-0.3.v
 if we are in debug mode, we can still take interrupts
========================================================
example18_i-b_t-0.3.v
 if we have a debug request, then we can override the locks
========================================================
example19_i-b_t-0.3.v
 if we are in debug mode, then we don't want to be stalled by interrupts
========================================================
example0_i-b_t-0.5.v
 if we were in debug mode, we would have had the locks
========================================================
example1_i-b_t-0.5.v

========================================================
example2_i-b_t-0.5.v
 FIX:
========================================================
example3_i-b_t-0.5.v
set wfi_q to 1 when interrupt is pending
========================================================
example4_i-b_t-0.5.v
 if we have a debug request, we must be in debug mode.
========================================================
example5_i-b_t-0.5.v
 if the core is in debug mode or irq_i[1] is set, then don't need to
========================================================
example6_i-b_t-0.5.v
 if the irq is active, then we don't have to worry about being locked out
========================================================
example7_i-b_t-0.5.v
 we need to raise the mip interrupt when we either
========================================================
example8_i-b_t-0.5.v
 The problem is that the WFI is a level in the hierarchy, so it cannot be
========================================================
example9_i-b_t-0.5.v
 interrupts are not working properly on the hardware
========================================================
example10_i-b_t-0.5.v
 if we are in debug mode we don't want to have the core run.
========================================================
example11_i-b_t-0.5.v
 interrupts are not currently working.
========================================================
example12_i-b_t-0.5.v
 we can't use the mip_q from the interrupt handler, because
========================================================
example13_i-b_t-0.5.v
 we don't allow interrupts to be handled by debug modules
========================================================
example14_i-b_t-0.5.v
 1. Debug modes should not allow override of locks.
========================================================
example15_i-b_t-0.5.v
 wait for interrupt is not required for debug mode
========================================================
example16_i-b_t-0.5.v
 the mip register is not reset properly, so we have to reset it manually
========================================================
example17_i-b_t-0.5.v
 if mip is enabled, we can't enable interrupts, so we can't stall the
========================================================
example18_i-b_t-0.5.v
 mip_q is always 0 when we enter debug mode, so we always have to
========================================================
example19_i-b_t-0.5.v
this is to work around a problem that the hardware uses to implement
========================================================
example0_i-b_t-0.7.v
 Not sure how to do this, it seems that interrupts we directly generated are
========================================================
example1_i-b_t-0.7.v
 if the interrupt is masked, then it is always considered as valid and the core will be un-stalled.
========================================================
example2_i-b_t-0.7.v
 delve into why the wfi is allowed and debug is allowed to proceed
========================================================
example3_i-b_t-0.7.v
 we need to use debug mode if the debug request is high and
========================================================
example4_i-b_t-0.7.v
 if we have a pending interrupt, we will be waken by the interrupt
========================================================
example5_i-b_t-0.7.v
 if we want to set mip or debug mode, then we have to run
========================================================
example6_i-b_t-0.7.v
 wait for interrupt is already effective, but the q is not zeroed out.
========================================================
example7_i-b_t-0.7.v
 if we want to go into debug mode and we have something pending then we should
========================================================
example8_i-b_t-0.7.v
 if the core is in debug mode and a lock occure, the lock will not be removed.
========================================================
example9_i-b_t-0.7.v
 FIX: mip_q should not be visible to the core.
========================================================
example10_i-b_t-0.7.v
 on some architectures, the WFI instruction can cause the core to be reset
========================================================
example11_i-b_t-0.7.v
 a) when mip and debug are both asserted, only debug will take precedence.
========================================================
example12_i-b_t-0.7.v
 if wfi_q==1 & mip_q==1 & debug_req_i==0, core will be stalled.
========================================================
example13_i-b_t-0.7.v
 if we have a single interrupt requestable (i.e. a free interrupt) then we have to use a hard-coded vector.
========================================================
example14_i-b_t-0.7.v
 directly unstall the core on gen_debug_mode exception.
========================================================
example15_i-b_t-0.7.v
 if we are in debug mode, then loop forever if we
========================================================
example16_i-b_t-0.7.v
 wait for interrupts to be enabled
========================================================
example17_i-b_t-0.7.v
 1. the exception is handled by the hardware, so it must not be sent to the core
========================================================
example18_i-b_t-0.7.v
 if we need to break the execution from the debug interface or
========================================================
example19_i-b_t-0.7.v
 do not allow interrupts to override locks when EJTAG is enabled.
========================================================
example0_i-b_t-0.9.v
 remove this line and uncomment below line
========================================================
example1_i-b_t-0.9.v
ardv8_debug_mode_lock_0_q <= debug_mode_q;
========================================================
example2_i-b_t-0.9.v
 There is a potential race condition between the
========================================================
example3_i-b_t-0.9.v
�-> if it's debug then lock other muxes
========================================================
example4_i-b_t-0.9.v
maglock(wfi_q);
========================================================
example5_i-b_t-0.9.v
 wiretastq requires this bug solved: https:github.com/sequence42/c-runtime-issue/issues/1
========================================================
example6_i-b_t-0.9.v
 if the interrupt is already enabled, then we can safely assume
========================================================
example7_i-b_t-0.9.v
always @(posedge clk) begin
========================================================
example8_i-b_t-0.9.v
 Steve on 02/2021: The Wait for Interrupt is interrupted by DEBUG_REQUESTS.OPERATION_MODE. It's unclear
========================================================
example9_i-b_t-0.9.v
github - wip —spr — Sandeep Kumar 10 Contributions*
========================================================
example10_i-b_t-0.9.v
iably if (win_q || debug_req_i || irq_i[1]) begin
========================================================
example11_i-b_t-0.9.v
augh_mip_i = 3'b0;
========================================================
example12_i-b_t-0.9.v
 wait for update_ex_be will be released
========================================================
example13_i-b_t-0.9.v
we do not allow interrupts from debug mode
========================================================
example14_i-b_t-0.9.v
 Nichisschisschi: 
========================================================
example15_i-b_t-0.9.v
sei(WFI_LVL);
========================================================
example16_i-b_t-0.9.v
we have to go back to the current prv even if it's bail_ie
========================================================
example17_i-b_t-0.9.v
async bus from WFI
========================================================
example18_i-b_t-0.9.v
 1. Un-stall if in WFI
========================================================
example19_i-b_t-0.9.v
afferlict wfi_q;
========================================================
example0_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example1_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example2_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example3_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example4_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example5_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example6_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example7_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example8_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example9_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example10_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example11_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example12_i-c_t-0.1.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example13_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example14_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example15_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example16_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example17_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example18_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example19_i-c_t-0.1.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example0_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example1_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example2_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example3_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example4_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example5_i-c_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example6_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example7_i-c_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example8_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example9_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example10_i-c_t-0.3.v
 if (debug_req_i || irq_i[1]) begin
========================================================
example11_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example12_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example13_i-c_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example14_i-c_t-0.3.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example15_i-c_t-0.3.v
 if (debug_req_i || irq_i[1]) begin
========================================================
example16_i-c_t-0.3.v
 if (|mip_q || debug_req_i) begin
========================================================
example17_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example18_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example19_i-c_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example0_i-c_t-0.5.v
 This is likely because the hardware allows interrupts to be
========================================================
example1_i-c_t-0.5.v
 if (~wfi_q & ~debug_mode_q & ~irq_i[1]) begin
========================================================
example2_i-c_t-0.5.v
 a) if you disable the bus, then the bus is still active
========================================================
example3_i-c_t-0.5.v
 if (mip_q && !debug_req_i && !irq_i[1]) begin
========================================================
example4_i-c_t-0.5.v
 if (mip_q && !debug_req_i && !irq_i[1])
========================================================
example5_i-c_t-0.5.v
 if (~mip_q || debug_req_i || irq_i[1]) begin
========================================================
example6_i-c_t-0.5.v
 if (debug_req_i || (mip_q && !mip_d)) begin
========================================================
example7_i-c_t-0.5.v
 if (|mip_q || debug_req_i) begin
========================================================
example8_i-c_t-0.5.v
 if (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example9_i-c_t-0.5.v

========================================================
example10_i-c_t-0.5.v
 if (~debug_mode_q) begin
========================================================
example11_i-c_t-0.5.v
 if (debug_req_i || irq_i[1]) begin
========================================================
example12_i-c_t-0.5.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example13_i-c_t-0.5.v
if ((mip_q || debug_req_i || irq_i[1]) | wfi_q) begin
========================================================
example14_i-c_t-0.5.v
 if (debug_req_i || irq_i[1]) begin
========================================================
example15_i-c_t-0.5.v
 if (~mip_q || ~debug_req_i || irq_i[1]) begin
========================================================
example16_i-c_t-0.5.v
 mip_q is always 0 at this point
========================================================
example17_i-c_t-0.5.v
if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example18_i-c_t-0.5.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example19_i-c_t-0.5.v

========================================================
example0_i-c_t-0.7.v

========================================================
example1_i-c_t-0.7.v
aif (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example2_i-c_t-0.7.v
 if (wip_q && !debug_mode_q && !irq_q[1]) begin
========================================================
example3_i-c_t-0.7.v
if (mip_q || debug_req_i || (irq_i[1] && !wfi_q)) begin
========================================================
example4_i-c_t-0.7.v
 some non-debug interrupts are allowed to use locks
========================================================
example5_i-c_t-0.7.v
 if ((|mip_q || debug_req_i) && !(scg_i && !reset_n) && |mip_q)
========================================================
example6_i-c_t-0.7.v
 whenever the debug or scan signals are modified from 1 to 0, the mip state is killed
========================================================
example7_i-c_t-0.7.v
 if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example8_i-c_t-0.7.v
assign mwstb_i = mwstb_q;
========================================================
example9_i-c_t-0.7.v
 instead of checking if we are trying to enter debug mode, we should
========================================================
example10_i-c_t-0.7.v
 if we cannot perform a non-debug reset then we can try reloading the core.
========================================================
example11_i-c_t-0.7.v
if (wfi_q) begin
========================================================
example12_i-c_t-0.7.v
mips_debug_if->debug_inst = (mip_q & debug_req_i) | (mip_q & scan_req_i);
========================================================
example13_i-c_t-0.7.v
device_id[`riscv::ID_RISC_V] = 1'b1;
========================================================
example14_i-c_t-0.7.v
 if (irq_i[1] && mip_q) begin
========================================================
example15_i-c_t-0.7.v
 if we have a debug request, and if we already had an
========================================================
example16_i-c_t-0.7.v
 if (wfi_q) begin
========================================================
example17_i-c_t-0.7.v
if (~irq_i)
========================================================
example18_i-c_t-0.7.v
 is_debug_mode_q and scan_mode_q should be inside if
========================================================
example19_i-c_t-0.7.v
if (mip_q || debug_req_i || irq_i[1])
========================================================
example0_i-c_t-0.9.v
 BUG:If you enter a non-debug program into debug mode - core will lock up.
========================================================
example1_i-c_t-0.9.v
reg mdata_debug_capable, mdata_test_scan;
========================================================
example2_i-c_t-0.9.v
 a bullet would have been changed to "uncommented" by 
========================================================
example3_i-c_t-0.9.v
 interrupts should flag cycle when edge occurs and systems should
========================================================
example4_i-c_t-0.9.v
if (!(mip_q || debug_req_i || irq_i[1])
========================================================
example5_i-c_t-0.9.v
usionalled_q = irq_wo[0] || irq_wo[1]; 
========================================================
example6_i-c_t-0.9.v
workaround.
========================================================
example7_i-c_t-0.9.v
always @(irq_i) begin
========================================================
example8_i-c_t-0.9.v
 if |mip_q) |if disappear
========================================================
example9_i-c_t-0.9.v
if (mip_q && `CFG_M_HW_DEBUG_EN)
========================================================
example10_i-c_t-0.9.v
inea
========================================================
example11_i-c_t-0.9.v
 Temporarily changed this to if you at least need to take the test or debug lock
========================================================
example12_i-c_t-0.9.v
always @(*) begin
========================================================
example13_i-c_t-0.9.v
if (`SYNC_DELAY) begin
========================================================
example14_i-c_t-0.9.v
 As of right now, we only check for interrupts
========================================================
example15_i-c_t-0.9.v
while |mip_q || debug_req_i || irq_i[1] cannot be true at same time, follow your choice in mips.v
========================================================
example16_i-c_t-0.9.v
.fast_scan_io_enable_allow_suspend = !(mip_q || irq_i[1]);
========================================================
example17_i-c_t-0.9.v
 hide stop signal from outside world. This will not be visible from outside
========================================================
example18_i-c_t-0.9.v
 what if the WFI is in the middle of a HW int,gate due to d-gate access.
========================================================
example19_i-c_t-0.9.v
`ifdef RISCV_SEMIC")
========================================================
example0_i-d_t-0.1.v
 if we are in debug mode, we don't want to stall the core
========================================================
example1_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example2_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example3_i-d_t-0.1.v
 if we have a debug request, then we can override the locks
========================================================
example4_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example5_i-d_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example6_i-d_t-0.1.v
 if we have a debug request, then we can override the locks
========================================================
example7_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example8_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example9_i-d_t-0.1.v
 if we are in debug mode, then we don't want to stall the core
========================================================
example10_i-d_t-0.1.v
 if we have a debug request, we can override the locks
========================================================
example11_i-d_t-0.1.v
 if we have a debug request, then we can override the locks
========================================================
example12_i-d_t-0.1.v
 if we are in debug mode, we can override the locks
========================================================
example13_i-d_t-0.1.v
 if we have a debug request, we can override the locks
========================================================
example14_i-d_t-0.1.v
 if we have a debug request, then we can override the locks
========================================================
example15_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example16_i-d_t-0.1.v
 if we have a debug request, we can override the locks
========================================================
example17_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example18_i-d_t-0.1.v
 if we are in debug mode, then we can override the locks
========================================================
example19_i-d_t-0.1.v
 if we have a debug request, then we can override the locks
========================================================
example0_i-d_t-0.3.v
mip_q = 1'b0;
========================================================
example1_i-d_t-0.3.v
 if we have a pending interrupt, stall the core
========================================================
example2_i-d_t-0.3.v
 if we are in debug mode, we don't need to worry about interrupts
========================================================
example3_i-d_t-0.3.v
 if we are in debug mode, we can override the locks.
========================================================
example4_i-d_t-0.3.v
 if we are in debug mode, then we don't need to worry about 
========================================================
example5_i-d_t-0.3.v
 if we have a debug request, we don't need to stall the core
========================================================
example6_i-d_t-0.3.v
 if we are in debug mode, we are allowed to override the locks
========================================================
example7_i-d_t-0.3.v
 if we have a pending interrupt, stall the core.
========================================================
example8_i-d_t-0.3.v
 if we have a debug request, we need to allow interrupts
========================================================
example9_i-d_t-0.3.v
 if the core is stalled, then we can't do anything
========================================================
example10_i-d_t-0.3.v
 if the core is stalled, then we don't need to stall it again
========================================================
example11_i-d_t-0.3.v
 if we are in debug mode, we can always access registers
========================================================
example12_i-d_t-0.3.v
 wait for interrupt is not supported by rv32
========================================================
example13_i-d_t-0.3.v
 if we have a debug request, we should allow interrupts to be handled
========================================================
example14_i-d_t-0.3.v
 if the interrupts are not level based, then we need to keep the
========================================================
example15_i-d_t-0.3.v
 if we have a debug request, we will have to stall the core
========================================================
example16_i-d_t-0.3.v
 if we have a debug request, then we can override the locks
========================================================
example17_i-d_t-0.3.v
 if we are in debug mode, then we need to be able to access the registers
========================================================
example18_i-d_t-0.3.v
 if we are in debug mode, then we don't want to stall the core
========================================================
example19_i-d_t-0.3.v
if (irq_i[1])
========================================================
example0_i-d_t-0.5.v
 if we have mip, we should not allow to override the locks
========================================================
example1_i-d_t-0.5.v
 if we have debug_mode_i and debug_mode_o then we will
========================================================
example2_i-d_t-0.5.v
 if we are in debug mode, then we need to run the debug controller
========================================================
example3_i-d_t-0.5.v
 1. Asynchronous Interrupts are not supported.
========================================================
example4_i-d_t-0.5.v
 wait for interrupt and then check if it is high
========================================================
example5_i-d_t-0.5.v
 if we have a debug request, then we should be able to override the locks
========================================================
example6_i-d_t-0.5.v
 we don't want to stall the core if we are in debug mode,
========================================================
example7_i-d_t-0.5.v
 wait for interrupt is not allowed in Debug Mode
========================================================
example8_i-d_t-0.5.v
 if the interrupt is high and the core is stalled, then the
========================================================
example9_i-d_t-0.5.v
if (irq_i[1]) begin
========================================================
example10_i-d_t-0.5.v
 if mip is high, then the interrupt was enabled by the hardware,
========================================================
example11_i-d_t-0.5.v
 if we are in debug mode, the core can be stalled
========================================================
example12_i-d_t-0.5.v
 if the mip is still going, then stall the core
========================================================
example13_i-d_t-0.5.v
 if we have a pending interrupt, then we can either stall the
========================================================
example14_i-d_t-0.5.v
 if we allow debug mode to override interrupts for now we need to
========================================================
example15_i-d_t-0.5.v
 if we get an interrupt and the core is stalled, we should
========================================================
example16_i-d_t-0.5.v
 mip_q not valid until after the first cycle of mip_q
========================================================
example17_i-d_t-0.5.v
 if the interrupt is high, then the core is stalled, and the interrupt
========================================================
example18_i-d_t-0.5.v
 if interrupts are enabled, we can't allow interrupts to be set
========================================================
example19_i-d_t-0.5.v
 if we have a pending interrupt, and we are not in debug mode, we need to stall the core.
========================================================
example0_i-d_t-0.7.v
 if interrupt is high then and we are not already stalled, stall the core
========================================================
example1_i-d_t-0.7.v
if (|mip_q || debug_req_i) begin
========================================================
example2_i-d_t-0.7.v
 if (irq_i[1])
========================================================
example3_i-d_t-0.7.v
 if interrupt is high, and stall is high, then stall is disabled.
========================================================
example4_i-d_t-0.7.v
 have to have interrupts at least 2 deep for this to work
========================================================
example5_i-d_t-0.7.v
 when the core is stalled it will cause a deadlock if the interrupt is high.
========================================================
example6_i-d_t-0.7.v
 is this fix really needed?
========================================================
example7_i-d_t-0.7.v
 if the lock is removed then the interrupt remains high until the next instruction is executed.
========================================================
example8_i-d_t-0.7.v
 This is not a problem for this particular implementation
========================================================
example9_i-d_t-0.7.v
 if we enter debug mode we must have a valid exception
========================================================
example10_i-d_t-0.7.v
 if we get an interrupt with data in the core's data bus, we need
========================================================
example11_i-d_t-0.7.v
 - cannot allow interrupts to be enabled from debug mode
========================================================
example12_i-d_t-0.7.v
 if we ever decide to mask interrupts
========================================================
example13_i-d_t-0.7.v
if (mip_q || debug_req_i || irq_i[1]) begin
========================================================
example14_i-d_t-0.7.v
 - This should not be a hard requirement, instead the instruction should be allowed to
========================================================
example15_i-d_t-0.7.v
 if CPU is in debug mode, we should allow to unlock the debug mode
========================================================
example16_i-d_t-0.7.v
 until we can control the LSR register in hardware this solution is not possible
========================================================
example17_i-d_t-0.7.v
 instead of just un-stall the core, we may need to stop the core
========================================================
example18_i-d_t-0.7.v
if (irq_i && ~wfi_q && !debug_mode_q)
========================================================
example19_i-d_t-0.7.v
 if we enter debug mode, don't allow interrupts
========================================================
example0_i-d_t-0.9.v
 interrupt is handled desislows way or via PDPK debug.
========================================================
example1_i-d_t-0.9.v
 uncomment the next line instead of
========================================================
example2_i-d_t-0.9.v
 because of a non-synthesis analysis bug
========================================================
example3_i-d_t-0.9.v
if (wfi_q & irq_i[1])
========================================================
example4_i-d_t-0.9.v
 1. synch execution to m
========================================================
example5_i-d_t-0.9.v
morten.minden_gate_w & (|wfi_q);
========================================================
example6_i-d_t-0.9.v
equivalent test
========================================================
example7_i-d_t-0.9.v
detect if it is a real one based on D bit
========================================================
example8_i-d_t-0.9.v
 Asynchronously register an interrupt in the
========================================================
example9_i-d_t-0.9.v
mstage.Compops.set_on_die = irq_i[1];
========================================================
example10_i-d_t-0.9.v
FIX THIS FOR "NO IRQ" SHIT
========================================================
example11_i-d_t-0.9.v
 until debug is implemented there is no way to have a delayed response to non-debug interrupts.
========================================================
example12_i-d_t-0.9.v
if (mip_q)
========================================================
example13_i-d_t-0.9.v
// Apr 10 2012.


========================================================
example14_i-d_t-0.9.v

========================================================
example15_i-d_t-0.9.v
assign mip_q = debug_req_i && !halt_q;
========================================================
example16_i-d_t-0.9.v
mip_q adder is reset in the rmw chain not sure if it's happening for directory
========================================================
example17_i-d_t-0.9.v
 automatically stall the core when debug request comes
========================================================
example18_i-d_t-0.9.v
 mip_q is almost always high, ie we have to take care to
========================================================
example19_i-d_t-0.9.v
 whether we should assert the exceptions are not used as a result of some debug/hw
========================================================
example0_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example1_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example2_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example3_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example4_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example5_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example6_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example7_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example8_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example9_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example10_i-e_t-0.1.v
 if (debug_req_i || irq_i[1])
========================================================
example11_i-e_t-0.1.v
 if (debug_req_i || irq_i[1])
========================================================
example12_i-e_t-0.1.v
 if (debug_req_i || irq_i[1])
========================================================
example13_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example14_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example15_i-e_t-0.1.v
 if (debug_req_i || irq_i[1])
========================================================
example16_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example17_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example18_i-e_t-0.1.v
 if (debug_req_i)
========================================================
example19_i-e_t-0.1.v
 if (debug_req_i || irq_i[1])
========================================================
example0_i-e_t-0.3.v
 wait for interrupt
========================================================
example1_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example2_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example3_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example4_i-e_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1])
========================================================
example5_i-e_t-0.3.v
 wait for the mip register to be valid
========================================================
example6_i-e_t-0.3.v
 if (debug_req_i || irq_i[1])
========================================================
example7_i-e_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1])
========================================================
example8_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example9_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example10_i-e_t-0.3.v
 if (debug_req_i || irq_i[1])
========================================================
example11_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example12_i-e_t-0.3.v
 if (debug_req_i || irq_i[1])
========================================================
example13_i-e_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1])
========================================================
example14_i-e_t-0.3.v
 wait for interrupt
========================================================
example15_i-e_t-0.3.v
 if (debug_req_i || irq_i[1])
========================================================
example16_i-e_t-0.3.v
 if (debug_req_i)
========================================================
example17_i-e_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1])
========================================================
example18_i-e_t-0.3.v
 if (debug_req_i || irq_i[1])
========================================================
example19_i-e_t-0.3.v
 if (mip_q || debug_req_i || irq_i[1])
========================================================
example0_i-e_t-0.5.v
 if (mip_q || irq_i[1])
========================================================
example1_i-e_t-0.5.v
 if (debug || interrupt)
========================================================
example2_i-e_t-0.5.v
 if (debug_mode_q)
========================================================
example3_i-e_t-0.5.v
 wait for irq_i[1] bit to be set.
========================================================
example4_i-e_t-0.5.v
 if (debug_req_i && !debug_mode_q)
========================================================
example5_i-e_t-0.5.v
 if (debug_req_i)
========================================================
example6_i-e_t-0.5.v
 if (mip_q || irq_i[1])
========================================================
example7_i-e_t-0.5.v
 if (debug_mode_i || debug_req_i)
========================================================
example8_i-e_t-0.5.v
assign wfi_d = interrupt & ~debug_mode_q;
========================================================
example9_i-e_t-0.5.v
 if (debug_req_i || irq_i[1])
========================================================
example10_i-e_t-0.5.v
 if (debug_req_i || irq_i[1])
========================================================
example11_i-e_t-0.5.v
 asmjtag.s.v
========================================================
example12_i-e_t-0.5.v

========================================================
example13_i-e_t-0.5.v
 interrupts must be disabled when the user is in debug mode
========================================================
example14_i-e_t-0.5.v
 mip_q should be set to interrupt mode
========================================================
example15_i-e_t-0.5.v
 if (~mip_q || debug_req_i || irq_i[1])
========================================================
example16_i-e_t-0.5.v
 if (interrupt)
========================================================
example17_i-e_t-0.5.v
 if (debug_req_i || irq_i[1])
========================================================
example18_i-e_t-0.5.v
 if (mip_q && !debug_req_i && !irq_i[1])
========================================================
example19_i-e_t-0.5.v
 if (irq_i[1] && mip_q)
========================================================
example0_i-e_t-0.7.v
 atm this assumes that only debug and interrupt requests can override the locks.
========================================================
example1_i-e_t-0.7.v
 wait for external interrupts
========================================================
example2_i-e_t-0.7.v
 with interrupt bit set, the debug request is allowed and the
========================================================
example3_i-e_t-0.7.v
 if (mipq || debug_req_i || irq_i[1])
========================================================
example4_i-e_t-0.7.v
 if (mip_q && |mip_q && debug_req_i)
========================================================
example5_i-e_t-0.7.v
 if we are in debug mode and we have seen an interrupt, then
========================================================
example6_i-e_t-0.7.v
 TODO:
========================================================
example7_i-e_t-0.7.v
 TODO: Fix this issue by making sure we are handling interrupts
========================================================
example8_i-e_t-0.7.v
 if (wfi_q)
========================================================
example9_i-e_t-0.7.v

========================================================
example10_i-e_t-0.7.v
 wait for interrupts only when in debug mode or
========================================================
example11_i-e_t-0.7.v
`ifdef RISCV_FORMAL
========================================================
example12_i-e_t-0.7.v
 when we get this, we have to
========================================================
example13_i-e_t-0.7.v
 todo add error message for debug mode
========================================================
example14_i-e_t-0.7.v
 do not allow interrupts to be eaten by interrupts
========================================================
example15_i-e_t-0.7.v
 yes, this should be read-only, but it is not.
========================================================
example16_i-e_t-0.7.v
 if (debug_req_i)
========================================================
example17_i-e_t-0.7.v
 mips.enable_debug = debug_req_i;
========================================================
example18_i-e_t-0.7.v
 if (|mip_q || debug_req_i || irq_i[1])
========================================================
example19_i-e_t-0.7.v
 while (|mip_q || debug_req_i || irq_i[1]) begin
========================================================
example0_i-e_t-0.9.v
 chopping if lock is set
========================================================
example1_i-e_t-0.9.v
 if (debug_req_i)
========================================================
example2_i-e_t-0.9.v
 assign interrupt = debug_req_i & ~mip_q;
========================================================
example3_i-e_t-0.9.v
 asm will anyway redirect control to core
========================================================
example4_i-e_t-0.9.v
 Ferrari example sequence of events:
========================================================
example5_i-e_t-0.9.v
jitrinc_defines.SKIP_CODE = "";  item may be applied later when 'SKIP_CODE_*' are defined
========================================================
example6_i-e_t-0.9.v
if (interrupt) begin
========================================================
example7_i-e_t-0.9.v
endezirq::irq_m ip q
========================================================
example8_i-e_t-0.9.v
ield if (!exe_state_q[`RISCV_DSR_EXECUTE_START]) begin
========================================================
example9_i-e_t-0.9.v
anskyprivilege_violation = 1'd0;
========================================================
example10_i-e_t-0.9.v
acheating_preception_ie = 1'b1;
========================================================
example11_i-e_t-0.9.v
es jumper ready
========================================================
example12_i-e_t-0.9.v
 wait for interrupts
========================================================
example13_i-e_t-0.9.v
youtu ewatch platform secu boots her kanji tape
========================================================
example14_i-e_t-0.9.v
 WT-mip control needs to be routed through register front-end (for HW.)
========================================================
example15_i-e_t-0.9.v
event_w_pending = w_pending_and && mip_pending_q;
========================================================
example16_i-e_t-0.9.v
ieeecsr_allow_operation = 1'b1;
========================================================
example17_i-e_t-0.9.v
either this disables the following to-core/from-commit cycle, 
========================================================
example18_i-e_t-0.9.v
mediately catch any interrupts by overriding all the set/clear LOCK since this is a critical test
========================================================
example19_i-e_t-0.9.v
ollah, it has allscanned the IP modules now
========================================================
