example0_i-a_t-0.1.v

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example17_i-a_t-0.1.v

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example18_i-a_t-0.1.v

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example19_i-a_t-0.1.v

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example0_i-a_t-0.3.v
 
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example1_i-a_t-0.3.v

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example2_i-a_t-0.3.v

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example8_i-a_t-0.3.v

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example9_i-a_t-0.3.v

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example10_i-a_t-0.3.v

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example13_i-a_t-0.3.v

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example14_i-a_t-0.3.v

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example15_i-a_t-0.3.v

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example16_i-a_t-0.3.v

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example17_i-a_t-0.3.v

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example18_i-a_t-0.3.v

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example19_i-a_t-0.3.v

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example0_i-a_t-0.5.v

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example1_i-a_t-0.5.v
 see https:github.com/phl/libpulse/pull/1
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example2_i-a_t-0.5.v

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example3_i-a_t-0.5.v

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example4_i-a_t-0.5.v
 assign start_alert = start_i && ((state_q != Done) && (state_q != Waiting));
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example5_i-a_t-0.5.v
assign start_alert = start_i && (state_q != Done);
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example6_i-a_t-0.5.v

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example7_i-a_t-0.5.v

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example8_i-a_t-0.5.v

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example9_i-a_t-0.5.v

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example10_i-a_t-0.5.v

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example11_i-a_t-0.5.v

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example12_i-a_t-0.5.v

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example13_i-a_t-0.5.v
 
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example14_i-a_t-0.5.v
 
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example15_i-a_t-0.5.v

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example16_i-a_t-0.5.v

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example17_i-a_t-0.5.v
assign start_alert = start_i && (state_q != Done);
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example18_i-a_t-0.5.v
 Shrouding is a bit tricky. If you have a case that is inside a loop (i.e. a case in a "for" loop)
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example19_i-a_t-0.5.v
 
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example0_i-a_t-0.7.v
 intricate logic
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example1_i-a_t-0.7.v
{
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example2_i-a_t-0.7.v
 somewhen we move here instead of the next def and the register
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example3_i-a_t-0.7.v

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example4_i-a_t-0.7.v
 Verify the same flow as in the original issue does not generate an issue
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example5_i-a_t-0.7.v
 ** SCENARIO:
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example6_i-a_t-0.7.v
��•½¨ÒÔÀÖÕÅÐÅÔÝÊÇË¤ÒÕ¸ÖÙÊÇ
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example7_i-a_t-0.7.v
 WARNING:
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example8_i-a_t-0.7.v
 hindsight: allow start_i when done is *done*
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example9_i-a_t-0.7.v
 cost: 1
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example10_i-a_t-0.7.v
 Somebody should do the check
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example11_i-a_t-0.7.v
soigne: {";
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example12_i-a_t-0.7.v
 sporadically assigning values.
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example13_i-a_t-0.7.v

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example14_i-a_t-0.7.v
initely assign start_alert = start_i && (state_q != Done);
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example15_i-a_t-0.7.v
 Instead of exiting the fsm, have it copy and
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example16_i-a_t-0.7.v
 simply assign start_alert = start_i;
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example17_i-a_t-0.7.v
 1.11
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example18_i-a_t-0.7.v
assign start_alert = start_i & (state_q != Done);


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example19_i-a_t-0.7.v
 
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example0_i-a_t-0.9.v
 Americas Digital DSL 650 DTC has reported January, 2013
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example1_i-a_t-0.9.v
 
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example2_i-a_t-0.9.v
Otherwise a sink might be tempted to inject a pulse into the system stream. This pulse can be a sink-pulse.
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example3_i-a_t-0.9.v
 soš{šđćŠŀš
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example4_i-a_t-0.9.v
Syria
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example5_i-a_t-0.9.v
ofstream file1 ("/home/ubuntu/CrLaGu/simulation/assign.v");
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example6_i-a_t-0.9.v
 Grounds sub-expression {SUBJECT,SUBJECT_2} is only valid in a check context.
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example7_i-a_t-0.9.v
 wholesym->bit_expr_assign_rhs_v has started to emit assignment
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example8_i-a_t-0.9.v
 Airways allow for parameters to a module at run-time.
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example9_i-a_t-0.9.v
enegassignstart_alert = start_i && (1'b1 /* state_q != Done is always true */);
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example10_i-a_t-0.9.v
 avert tranquility
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example11_i-a_t-0.9.v
atrandom
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example12_i-a_t-0.9.v
arranted start_alert = start_i && (state_q != Done || fsm_alert);
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example13_i-a_t-0.9.v
 softer start transition
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example14_i-a_t-0.9.v
 Furthermore, we have to reassign the start_alert to the start_i
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example15_i-a_t-0.9.v
____The code below does something interesting.
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example16_i-a_t-0.9.v
assign start_alert = start_i && (state_q != Done || fsm_alert);


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example17_i-a_t-0.9.v
 same as fsm_alert
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example18_i-a_t-0.9.v
 Mysteriously, this assignment generates a reference cycle between ie, cbf and late ex.
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example19_i-a_t-0.9.v
 sangyeon 2013/11/15 14:48 
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example0_i-b_t-0.1.v

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example1_i-b_t-0.1.v

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example2_i-b_t-0.1.v

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example19_i-b_t-0.1.v

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example0_i-b_t-0.3.v

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example1_i-b_t-0.3.v

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example2_i-b_t-0.3.v

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example3_i-b_t-0.3.v

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example8_i-b_t-0.3.v

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example9_i-b_t-0.3.v

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example10_i-b_t-0.3.v

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example11_i-b_t-0.3.v

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example13_i-b_t-0.3.v

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example17_i-b_t-0.3.v

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example18_i-b_t-0.3.v

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example19_i-b_t-0.3.v

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example0_i-b_t-0.5.v

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example1_i-b_t-0.5.v

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example2_i-b_t-0.5.v

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example3_i-b_t-0.5.v

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example4_i-b_t-0.5.v
assign start_alert = start_i;
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example5_i-b_t-0.5.v

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example6_i-b_t-0.5.v

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example7_i-b_t-0.5.v
 
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example8_i-b_t-0.5.v

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example9_i-b_t-0.5.v

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example10_i-b_t-0.5.v

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example11_i-b_t-0.5.v

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example12_i-b_t-0.5.v

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example13_i-b_t-0.5.v

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example14_i-b_t-0.5.v

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example15_i-b_t-0.5.v

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example16_i-b_t-0.5.v

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example17_i-b_t-0.5.v

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example18_i-b_t-0.5.v

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example19_i-b_t-0.5.v

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example0_i-b_t-0.7.v

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example1_i-b_t-0.7.v
 You can use the following code to test the alerts
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example2_i-b_t-0.7.v

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example3_i-b_t-0.7.v

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example4_i-b_t-0.7.v
wall_1 = wall_2;
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example5_i-b_t-0.7.v

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example6_i-b_t-0.7.v
 1. The inferring of start_i from state_q is not correct.
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example7_i-b_t-0.7.v
 - Clean-up the warning: 'assign statement can only assign value'
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example8_i-b_t-0.7.v
// https://github.com/libmproxy/libmproxy/pull/420


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example9_i-b_t-0.7.v
 assign start_alert = start_i;
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example10_i-b_t-0.7.v
assign start_alert = start_i && state_d != Done;
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example11_i-b_t-0.7.v

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example12_i-b_t-0.7.v

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example13_i-b_t-0.7.v
 https:github.com/matlab-html/matlab-html/blob/f69a879e6a3e9e15e22d59a6bb6dca6855cd0/matlab-html/matlab-html/src/web/js/modules/compare/compare.js Line 31
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example14_i-b_t-0.7.v
 Circuit Errors
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example15_i-b_t-0.7.v
 
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example16_i-b_t-0.7.v

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example17_i-b_t-0.7.v

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example18_i-b_t-0.7.v

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example19_i-b_t-0.7.v

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example0_i-b_t-0.9.v
//


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example1_i-b_t-0.9.v
assign start_alert = start_i;
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example2_i-b_t-0.9.v

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example3_i-b_t-0.9.v
SYNTH_WRAPPER_SPEC_MIGHT_BE_ISSUE_ASSIGN_BEHAVIOR =
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example4_i-b_t-0.9.v
assign start_alert = start_i;
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example5_i-b_t-0.9.v

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example6_i-b_t-0.9.v
24000000000000000000
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example7_i-b_t-0.9.v
	2017-01-08, 17:08 to 11:21, by onhang
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example8_i-b_t-0.9.v
(?<>).start_i => (?<>).state_q -> stop state machine
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example9_i-b_t-0.9.v
 The bug is that Alerts are compared to a target
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example10_i-b_t-0.9.v
assign start_alert = start_i;
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example11_i-b_t-0.9.v
 
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example12_i-b_t-0.9.v
socategories_i = socategories_q;
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example13_i-b_t-0.9.v
assign start_alert = start_i && (state_q != Done);
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example14_i-b_t-0.9.v
assign start_alert = start_i;
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example15_i-b_t-0.9.v
esonnlib.txt sobres1_q := 4'b1111;
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example16_i-b_t-0.9.v

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example17_i-b_t-0.9.v
 Uncomment the code to display start/stop alerts, this was for a different reason not related to this
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example18_i-b_t-0.9.v
 floated: set, set+e, false,false,false,false,false;
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example19_i-b_t-0.9.v
assign start_alert = start_i && (state_q != Done);
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example0_i-c_t-0.1.v

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example1_i-c_t-0.1.v

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example2_i-c_t-0.1.v

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example3_i-c_t-0.1.v

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example9_i-c_t-0.1.v

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example10_i-c_t-0.1.v

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example11_i-c_t-0.1.v

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example12_i-c_t-0.1.v

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example13_i-c_t-0.1.v

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example14_i-c_t-0.1.v

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example15_i-c_t-0.1.v

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example16_i-c_t-0.1.v

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example17_i-c_t-0.1.v

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example18_i-c_t-0.1.v

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example19_i-c_t-0.1.v

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example0_i-c_t-0.3.v

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example1_i-c_t-0.3.v

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example2_i-c_t-0.3.v

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example3_i-c_t-0.3.v

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example4_i-c_t-0.3.v

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example5_i-c_t-0.3.v

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example6_i-c_t-0.3.v

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example7_i-c_t-0.3.v

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example8_i-c_t-0.3.v

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example9_i-c_t-0.3.v

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example10_i-c_t-0.3.v
 1. The state machine is currently not able to be instructed to start in a state that is not idle
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example11_i-c_t-0.3.v

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example12_i-c_t-0.3.v

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example13_i-c_t-0.3.v

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example14_i-c_t-0.3.v

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example15_i-c_t-0.3.v

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example16_i-c_t-0.3.v

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example17_i-c_t-0.3.v

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example18_i-c_t-0.3.v

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example19_i-c_t-0.3.v

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example0_i-c_t-0.5.v
 The `PRIM_*_FSM is the most significant bit of the instruction, and the FSM is the second to the most significant bit.
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example1_i-c_t-0.5.v

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example2_i-c_t-0.5.v

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example3_i-c_t-0.5.v

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example4_i-c_t-0.5.v
 When the state is `Done, the FSM is not allowed to start a new operation,
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example5_i-c_t-0.5.v
 If state_q is not done, then start_i is always true
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example6_i-c_t-0.5.v

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example7_i-c_t-0.5.v
 In the case of an idle state, it is not possible to start the device.
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example8_i-c_t-0.5.v

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example9_i-c_t-0.5.v

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example10_i-c_t-0.5.v
 Mysteriously, the value of the signal is incorrect, and this is causing a test failure.
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example11_i-c_t-0.5.v
 When a state is idle, it should not be allowed to start
========================================================
example12_i-c_t-0.5.v
 ...
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example13_i-c_t-0.5.v

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example14_i-c_t-0.5.v
 - Detect state changes and generate a start_alert signal
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example15_i-c_t-0.5.v
 The issue is that the start_i signal is always set, even if the state is in idle.
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example16_i-c_t-0.5.v

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example17_i-c_t-0.5.v
 https:github.com/synopsys/synopsys-docs-en/blob/master/docs/en/docs_en.html#sessions-synopsys-docs-en
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example18_i-c_t-0.5.v

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example19_i-c_t-0.5.v

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example0_i-c_t-0.7.v
 Using a different state than the idle state prevents the FSM from being held in the idle state.
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example1_i-c_t-0.7.v
 https:youtrack.mit.edu/issue/SIH-8
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example2_i-c_t-0.7.v
 Instead of trying to check for the validity of a state, check for the validity of the bit map
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example3_i-c_t-0.7.v

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example4_i-c_t-0.7.v

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example5_i-c_t-0.7.v

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example6_i-c_t-0.7.v
 Once the state machine has started it will not be able to be commanded by the user, this should
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example7_i-c_t-0.7.v
 Axi drivers should be able to accept a more than 1 cycle of delay between the request and the actual start.
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example8_i-c_t-0.7.v

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example9_i-c_t-0.7.v
 Instead of checking the state of the FSM, we check the bit position of the start signal.
========================================================
example10_i-c_t-0.7.v
assign start_alert = start_i && (state_q != Waiting);
========================================================
example11_i-c_t-0.7.v
 
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example12_i-c_t-0.7.v
 Nonetheless, we should not be using this system to receive any input
========================================================
example13_i-c_t-0.7.v
Essentially this is a state machine for the flop,
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example14_i-c_t-0.7.v
 This may be a problem if the state machine is initalized and then restarted
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example15_i-c_t-0.7.v
 $display("%10s %m", start_alert, "Start");
========================================================
example16_i-c_t-0.7.v
 However when a state is re-entered the idx is updated. So the FSM is not in it's expected state.
========================================================
example17_i-c_t-0.7.v
 Likewise, an alert signal should be set if the FSM goes back to the same state it was in
========================================================
example18_i-c_t-0.7.v
 So, we're using a different field to store the alert flag, and also generate this flag based on the `PRIM_FAST_*
========================================================
example19_i-c_t-0.7.v
assign start_alert = start_i && state_q != Waiting;
========================================================
example0_i-c_t-0.9.v
 Finite is fine for now. With multithreaded design we may need to use polling for a busy flag.
========================================================
example1_i-c_t-0.9.v
 Now that we have the ability to shuffle work, we are not allowed to tell the outside world
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example2_i-c_t-0.9.v

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example3_i-c_t-0.9.v
assign start_alert = start_i;
========================================================
example4_i-c_t-0.9.v
 stared at 09/16 of version 2020.04.15.r11..23
========================================================
example5_i-c_t-0.9.v
. Triggered implies done.
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example6_i-c_t-0.9.v
start_q = state_q;
========================================================
example7_i-c_t-0.9.v
 Issued at 2016-10-12
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example8_i-c_t-0.9.v
 This is the most confusing bit of addition for a consistency check:
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example9_i-c_t-0.9.v
always @* begin
end

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example10_i-c_t-0.9.v
 swoopins->schedule(`CFG_SCHEDULE_ALWAYS)->dispatch
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example11_i-c_t-0.9.v
 Havent's started on this lane yet, so its not going to be valid data for now
========================================================
example12_i-c_t-0.9.v
 block drivers for blocks that are not done from. see notes section
========================================================
example13_i-c_t-0.9.v
ser="<?xml version='1.0' encoding='ISO-8859-1'?><?shallow-ser cmd="setup (u_setup (ser))"?>";  BUG: Ser must be clean and cannot have two :: representing indicates ser="";
========================================================
example14_i-c_t-0.9.v
 gates.push back start_alert as it is not used by any other FSM
========================================================
example15_i-c_t-0.9.v
set_start_alert = (state_q != FS_IDLE) ;
========================================================
example16_i-c_t-0.9.v

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example17_i-c_t-0.9.v
 
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example18_i-c_t-0.9.v
issors start_alert = 
========================================================
example19_i-c_t-0.9.v
while (start_i && state_q != Done)
========================================================
example0_i-d_t-0.1.v

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example1_i-d_t-0.1.v

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example2_i-d_t-0.1.v
 - Alert mechanism is not working properly.
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example3_i-d_t-0.1.v

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example4_i-d_t-0.1.v

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example5_i-d_t-0.1.v

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example6_i-d_t-0.1.v

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example7_i-d_t-0.1.v

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example8_i-d_t-0.1.v

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example9_i-d_t-0.1.v

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example10_i-d_t-0.1.v
 
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example11_i-d_t-0.1.v

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example12_i-d_t-0.1.v

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example13_i-d_t-0.1.v

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example14_i-d_t-0.1.v

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example15_i-d_t-0.1.v

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example16_i-d_t-0.1.v

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example17_i-d_t-0.1.v

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example18_i-d_t-0.1.v

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example19_i-d_t-0.1.v

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example0_i-d_t-0.3.v

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example1_i-d_t-0.3.v

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example2_i-d_t-0.3.v

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example3_i-d_t-0.3.v
 Assert alert when start signal is asserted and state is not idle
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example4_i-d_t-0.3.v

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example5_i-d_t-0.3.v
 Assert start_alert only when state is not idle
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example6_i-d_t-0.3.v

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example7_i-d_t-0.3.v
 - Instead of a simple "if" statement, we should use a "case" statement
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example8_i-d_t-0.3.v

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example9_i-d_t-0.3.v

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example10_i-d_t-0.3.v

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example11_i-d_t-0.3.v
 - Add support for idle state
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example12_i-d_t-0.3.v
 Once state is idle, it will be asserted again.
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example13_i-d_t-0.3.v

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example14_i-d_t-0.3.v

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example15_i-d_t-0.3.v

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example16_i-d_t-0.3.v
 - Assert start_alert only when state is not idle
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example17_i-d_t-0.3.v
 - We should be able to detect that the state is Done and that the start signal is still asserted.
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example18_i-d_t-0.3.v

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example19_i-d_t-0.3.v
 https:github.com/santosh/fsm-santosh/blob/master/fsm_santosh/fsm_santosh.py#L13
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example0_i-d_t-0.5.v
assign start_alert = start_i && state_q != Done;
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example1_i-d_t-0.5.v

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example2_i-d_t-0.5.v

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example3_i-d_t-0.5.v

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example4_i-d_t-0.5.v
 Once state is idle, then we can see if the timer has expired.
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example5_i-d_t-0.5.v

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example6_i-d_t-0.5.v

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example7_i-d_t-0.5.v
 
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example8_i-d_t-0.5.v
 - Alert when start input is asserted and state is not idle
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example9_i-d_t-0.5.v

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example10_i-d_t-0.5.v

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example11_i-d_t-0.5.v
 - Alert signal is not asserted when state is idle
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example12_i-d_t-0.5.v
`define ALERT_SIG_1
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example13_i-d_t-0.5.v
assign start_alert = start_i && (state_q != Done);
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example14_i-d_t-0.5.v
 - Once there is a state change, the start_i is always asserted.
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example15_i-d_t-0.5.v

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example16_i-d_t-0.5.v
 - The state machine must be in state 'Done' when the last address has been compared.
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example17_i-d_t-0.5.v

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example18_i-d_t-0.5.v

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example19_i-d_t-0.5.v

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example0_i-d_t-0.7.v

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example1_i-d_t-0.7.v
 The implementation is not identical for idling as well as for all states with the case statement
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example2_i-d_t-0.7.v

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example3_i-d_t-0.7.v
 -3.11: 'start_i' is never checked for errors, even if it fails
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example4_i-d_t-0.7.v
 iverilog -I$ sys_test/sys_test.tcl -L$ sys_test/sys_test.py
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example5_i-d_t-0.7.v
 Additional logic required, infer a "Start" signal which is only used to start the model.
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example6_i-d_t-0.7.v
 This will be a lot easier if we could assign params to all states that have multiple params (like Idle)
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example7_i-d_t-0.7.v

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example8_i-d_t-0.7.v
 https:github.com/event-stream-orchestrator/event-stream-orchestrator/pull/1
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example9_i-d_t-0.7.v
 When the state is Done, the bit is always 1
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example10_i-d_t-0.7.v
Assert the start signal when state is idle (a single cycle of the FSM)
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example11_i-d_t-0.7.v
 TODO: This line of code is causing issues. The issue is that the changes
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example12_i-d_t-0.7.v

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example13_i-d_t-0.7.v

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example14_i-d_t-0.7.v
always @(state_q)
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example15_i-d_t-0.7.v
 enlightenment.m4d - ALERT: ASSERTING WHEN NOT IN IDLE STATE
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example16_i-d_t-0.7.v
 This was always a bug. The code was asserting the start_alert when state was
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example17_i-d_t-0.7.v

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example18_i-d_t-0.7.v
 
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example19_i-d_t-0.7.v
 - state associated with start_i is not used for
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example0_i-d_t-0.9.v
 Assert alerts when the state is not idle to catch cases where an action is
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example1_i-d_t-0.9.v
when (start_q)
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example2_i-d_t-0.9.v
 Physically emit start_alert after state is set to 1
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example3_i-d_t-0.9.v
Async
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example4_i-d_t-0.9.v
assign start_alert = start_i & (!(state_q == IDLE));
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example5_i-d_t-0.9.v
noonetsi&eso_ptr_q?
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example6_i-d_t-0.9.v
 There is valid output of the flow. The variable blocks are scoped, thus they are not necessary.
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example7_i-d_t-0.9.v
constant identity = "^( |\n+|\n+::)$";
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example8_i-d_t-0.9.v
 assigns start_alert = start_i;
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example9_i-d_t-0.9.v
assign start_alert = start_i && (state_q != S0) && (state_q != S1);
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example10_i-d_t-0.9.v
 even though this might hurt semantic theory ...
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example11_i-d_t-0.9.v
 When doing matrix calculations, the old matrix value become undefined
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example12_i-d_t-0.9.v
 -Test that timeout doesn't fire as expected
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example13_i-d_t-0.9.v

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example14_i-d_t-0.9.v
 Because modules can determine when 
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example15_i-d_t-0.9.v
`ifdef DELAY_CTRL_FLOW_CONSISTENCY
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example16_i-d_t-0.9.v
 Exercise to do not account 12.5% of the way
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example17_i-d_t-0.9.v
FIX_2018:11:11:ASSERT_ALERT_FROM_LAST_REGISTRATIONS_PER_INITIAL_FSM
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example18_i-d_t-0.9.v

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example19_i-d_t-0.9.v
 FIX: Resetting flag between pulses could improve stability
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example0_i-e_t-0.1.v

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example1_i-e_t-0.1.v
 start_alert = start_i && (state_q != Done);
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example2_i-e_t-0.1.v

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example3_i-e_t-0.1.v

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example4_i-e_t-0.1.v

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example5_i-e_t-0.1.v

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example6_i-e_t-0.1.v

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example7_i-e_t-0.1.v

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example8_i-e_t-0.1.v

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example9_i-e_t-0.1.v

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example10_i-e_t-0.1.v

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example11_i-e_t-0.1.v

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example12_i-e_t-0.1.v

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example13_i-e_t-0.1.v

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example14_i-e_t-0.1.v

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example15_i-e_t-0.1.v
 start_alert = start_i && (state_q != Done);
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example16_i-e_t-0.1.v

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example17_i-e_t-0.1.v
 start_alert = start_i && (state_q != Done);
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example18_i-e_t-0.1.v

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example19_i-e_t-0.1.v
 start_alert = start_i && (state_q != Done);
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example0_i-e_t-0.3.v
 scoreboard
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example1_i-e_t-0.3.v
 start_alert = start_i && (state_q != IDLE);
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example2_i-e_t-0.3.v

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example3_i-e_t-0.3.v

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example4_i-e_t-0.3.v
 scoreboard logic
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example5_i-e_t-0.3.v
 same as above
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example6_i-e_t-0.3.v
 same as above
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example7_i-e_t-0.3.v
 start_alert = start_i && (state_q != Done) && (state_q != IDLE);
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example8_i-e_t-0.3.v
 start_alert = start_i && (state_q != Done);
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example9_i-e_t-0.3.v
 start_alert = start_i && (state_q != Done);
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example10_i-e_t-0.3.v

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example11_i-e_t-0.3.v

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example12_i-e_t-0.3.v
 start_alert = start_i && (state_q != Done);
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example13_i-e_t-0.3.v

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example14_i-e_t-0.3.v
 start_alert = start_i && (state_q != Done);
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example15_i-e_t-0.3.v
 start_alert = start_i && (state_q != Done);
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example16_i-e_t-0.3.v

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example17_i-e_t-0.3.v

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example18_i-e_t-0.3.v

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example19_i-e_t-0.3.v
 start_alert = start_i && (state_q != IDLE);
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example0_i-e_t-0.5.v

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example1_i-e_t-0.5.v
 inadvertently caused a bug
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example2_i-e_t-0.5.v
soeveralert = start_i;
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example3_i-e_t-0.5.v

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example4_i-e_t-0.5.v
 inadvertently allows start to show up in the middle of the stream
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example5_i-e_t-0.5.v
 spokes
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example6_i-e_t-0.5.v
 assign start_alert = start_i && (state_q != Done);
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example7_i-e_t-0.5.v
 scoreboard logic
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example8_i-e_t-0.5.v
 scoreboard.v
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example9_i-e_t-0.5.v
 (1) start_i is not needed
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example10_i-e_t-0.5.v
 scoreboard.
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example11_i-e_t-0.5.v
 yes, it's a bit more complicated than it sounds (see next file)
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example12_i-e_t-0.5.v
 merchandise
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example13_i-e_t-0.5.v
 scoreboard = start_alert || start_i;
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example14_i-e_t-0.5.v
 however, this will not work if there is more than one of the following:
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example15_i-e_t-0.5.v
 start_alert = start_i && (state_q != IDLE) && (state_q != Done);
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example16_i-e_t-0.5.v
 eschew start_alert = start_i && (state_q != Done);
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example17_i-e_t-0.5.v
 Schwarzer.JS: v8.1.11211(release)
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example18_i-e_t-0.5.v
 merchandise alert logic
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example19_i-e_t-0.5.v

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example0_i-e_t-0.7.v
 escheck start_alert = start_i && (state_q != Done);
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example1_i-e_t-0.7.v
 vom handshake so aa is not needed
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example2_i-e_t-0.7.v
assign start_alert = start && (state != IDLE);
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example3_i-e_t-0.7.v
 allow start_i to pass through to the user if we're in a finished state
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example4_i-e_t-0.7.v
 sausage??/
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example5_i-e_t-0.7.v
 incorr_numer_m_x_c_s
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example6_i-e_t-0.7.v
 for compatiblity with old scheme
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example7_i-e_t-0.7.v
 
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example8_i-e_t-0.7.v
 sabotage 1'b1 for now, we will handle it later
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example9_i-e_t-0.7.v
 specificity is defined by the constraints,
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example10_i-e_t-0.7.v
 anytime start notifies, start_alert is 1
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example11_i-e_t-0.7.v
 this is the same as the check-block module
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example12_i-e_t-0.7.v
 These warnings should be removed after checking.
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example13_i-e_t-0.7.v
//


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example14_i-e_t-0.7.v
 start_alert = start_i || (state_q != Done);
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example15_i-e_t-0.7.v
 start_alert = start_i & (state_q != Done);
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example16_i-e_t-0.7.v
 -1'b1 + 1'b1 = 2'b11
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example17_i-e_t-0.7.v
 if ack_q == 1'b1 && start_q == 1'b1:
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example18_i-e_t-0.7.v
 scoreboard. 
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example19_i-e_t-0.7.v
 start_alert = start_i;
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example0_i-e_t-0.9.v
ateverify(`ALERT_SEEN) <<="Alert! A command from the command line was issued, even though the file was executed!";
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example1_i-e_t-0.9.v
// scoreboard = theitor->scoreboard();


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example2_i-e_t-0.9.v
 insofar as this is a valid issue, throw a warning if a state is not done. We have the rows in the matrix, we may assume that the explicit degrees are correctly stated.
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example3_i-e_t-0.9.v
 vomjutei332: we need to ensure we're in Done state to issue start.
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example4_i-e_t-0.9.v
 surgediv.c:704: error: Value is of type "unsigned short" is not a valid identifier
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example5_i-e_t-0.9.v
 if a chroma is called while a glows is already on this should happen
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example6_i-e_t-0.9.v
 swat-mc will will happily find an error if the parent of the last register does not exist?!
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example7_i-e_t-0.9.v
 scoreboard
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example8_i-e_t-0.9.v
 alert=stime))&&(state_q!=IDLE);
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example9_i-e_t-0.9.v
 showdown's;
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example10_i-e_t-0.9.v
 maize_q.block.some_false
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example11_i-e_t-0.9.v
 14 Sep 18:06
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example12_i-e_t-0.9.v
 conduciveness: fix alert suppression
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example13_i-e_t-0.9.v
noxious thankz, Venkita Ramana SAWAN 
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example14_i-e_t-0.9.v
 gladly acknowledge no change on bugs
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example15_i-e_t-0.9.v
 nor accepting - no race, so no need to accept a false issue
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example16_i-e_t-0.9.v
when (q_changed == 1'b1 || state == 2'b1034)
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example17_i-e_t-0.9.v
 see DCCP impl on this
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example18_i-e_t-0.9.v
 motiviation from analysis (bad logic coding style, [s/t had the last term and s/t had a delay, and so they generated reduntant equations. Recompile after clean
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example19_i-e_t-0.9.v
 soft_assert(start_q == start_i);
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