example0_i-e_t-0.1.v
	
endcase

========================================================
example1_i-e_t-0.1.v
	case
	
endcase

========================================================
example2_i-e_t-0.1.v
	
endcase

========================================================
example3_i-e_t-0.1.v
	
endcase

========================================================
example4_i-e_t-0.1.v
	
endcase

========================================================
example0_i-e_t-0.3.v
	case
	
endcase

========================================================
example1_i-e_t-0.3.v
	case
	
endcase

========================================================
example2_i-e_t-0.3.v
	
endcase

========================================================
example3_i-e_t-0.3.v
	
endcase

========================================================
example4_i-e_t-0.3.v
	case
	
endcase

========================================================
example0_i-e_t-0.5.v
/*
always @(*) begin
	reg[15:0] Out_data;
	Out_data = {reg[31:0],reg[15:0]};
end
*/
always @(*) begin
	reg[15:0] Out_data;
	Out_data = {reg[31:0],reg[15:0]};
end
//reg[15:0] Out_data;
//reg[31:0] Out_data;
always @(*) begin
	reg[31:0] Out_data;
	Out_data = {reg[31:0],reg[15:0]};
end
//reg[31:0] Out_data;
//always @(*) begin
//	reg[31:0] Out_data;
//	Out_data = {reg[31:0],reg[15:0]};
endcase

========================================================
example1_i-e_t-0.5.v
	always @(*) begin
	case(state)
	s0: begin
//	if(ct_valid) begin
//	end
	end
	s1: begin
	end
	s2: begin
	end
	s3: begin
	end
	s4: begin
	end
	s5: begin
	end
	s6: begin
	end
	s7: begin
	end
	s8: begin
	end
	s9: begin
	end
	s10: begin
	end
	s11: begin
	end
	s12: begin
	end
	s13: begin
	end
	s14: begin
	end
	s15: begin
	end
	
endcase

end

========================================================
example2_i-e_t-0.5.v
	
endcase

========================================================
example3_i-e_t-0.5.v
//	case
//	default
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endcase

========================================================
example4_i-e_t-0.5.v

//
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endcase

========================================================
example0_i-e_t-0.7.v
//	assign ct_next = {11'b0,ct_next_out}
//	assign ct_next = {11'b0,ct_next_out}
//	assign ct_next = ct_next_out
//
//
//
//
/////
//
//
/////
//
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//
//

endcase

========================================================
example1_i-e_t-0.7.v
	if (type == 0)
	else if (type == 1)
	else if (type == 2)
	else if (type == 3)
	else if (type == 4)
	else if (type == 5)
	else if (type == 6)
	else if (type == 7)
	else if (type == 8)
	else if (type == 9)
	else if (type == 10)
	else if (type == 11)
	else if (type == 12)
	else if (type == 13)
	else if (type == 14)
	else if (type == 15)
	else if (type == 16)
	else if (type == 17)
	else if (type == 18)
	else if (type == 19)

endcase

========================================================
example2_i-e_t-0.7.v
// endcase

endcase

========================================================
example3_i-e_t-0.7.v
//assign i_cmd_valid = i_cmd_valid;
//assign i_cmd_valid = i_cmd_valid;
//assign i_cmd_valid = ct_valid_cmd;
//assign ct_valid_cmd = i_cmd_valid;
//assign i_cmd_valid = ct_valid_cmd;
//assign ct_valid_cmd = i_cmd_valid;


endcase

========================================================
example4_i-e_t-0.7.v
// implement the other states
// otherwise, default state
// case statement
//FIX


endcase

========================================================
example0_i-e_t-0.9.v
/*case-end*/

endcase

========================================================
example1_i-e_t-0.9.v
`define generate
`include "translator.v"
`include "pixmapper.v"
//`include "targetSubNames.v"
`include "fonts.v"
//`include "fontTargetStrs.v"
`include "xyzMapper.v"
`include "fontVersionInfo.v"
`include "device.v"
`include "utils/paramutils.v"
`include "utils/cmdutils.v"
`include "utils/utils.v"
module Serializeroxm_samplenm(input clk, output reg [31:0] out);
reg [31:0] out;
always @ (posedge clk) begin
out <= out +$random();
end

endcase

========================================================
example2_i-e_t-0.9.v
	always @ (value_in) begin
	value_out = value_in;
	end
	always @(posedge CLK or posedge RESET) begin	//&value_out
if(RESET == 1) begin
	value_out <= 32'b0;
end
else begin
	case(value_out)
	32'b0 : value_out <= 32'b1;
	32'b1: value_out = 32'b10;
	32'b10: value_out = 32'b100;
	32'b100: value_out = 32'b10000;
	32'b10000: value_out = 32'b10000000;
	32'b10000000: value_out = 32'b00000000;
	default: value_out = 32'b00000000;
	
endcase

end

========================================================
example3_i-e_t-0.9.v

/////////////////////////////////////////////////////////////

/*
Values for displaying text 
i = 192 
ii = 195
iii = 196
iv = 198
v = 203
// i = 
//ii =
//iii =
//iv =
//v =
//
////////////////////////////////////////////////////////////
*/
// i = %s
//ii = %s
//iii = %s
//iv = %s
//v = %s

module DiEyEmulator #(parameter nMaxRec = 2) // max nb of records is nMaxRec
( 

parameter grayScaleMethod = " Robinson" , 
parameter thresholdMethod = "Otsu" , 
parameter normalizeMethod = "none" , 
parameter fillEdges = 1, 
parameter resizeMethod = "WARP", //"NONE"// possible line resizing (not active due to storing
endcase

========================================================
example4_i-e_t-0.9.v
//	`define REDACTED_GRAPHWORK
// actually don't have to do this sec<->ert
//	but need to do mapping from code to error code for sel<->ert
//	should look into this "pkg" functionality and necessary tools
//	
//	its possible that Bunpken will catch these virtual errors and return back to top level error handler
//	but need to also look into other preprocessing options to see if I need to have these errors being handled from
//	the top level point of view.


endcase

========================================================
example5_i-e_t-0.1.v
	
endcase

========================================================
example6_i-e_t-0.1.v
	
endcase

========================================================
example7_i-e_t-0.1.v
	
endcase

========================================================
example8_i-e_t-0.1.v
	
endcase

========================================================
example9_i-e_t-0.1.v
	
endcase

========================================================
example5_i-e_t-0.3.v
	
endcase

========================================================
example6_i-e_t-0.3.v
	
endcase

========================================================
example7_i-e_t-0.3.v
	
endcase

========================================================
example8_i-e_t-0.3.v
	
endcase

========================================================
example9_i-e_t-0.3.v
	
endcase

========================================================
example5_i-e_t-0.5.v
	
endcase

========================================================
example6_i-e_t-0.5.v
	case
	default
	
endcase

========================================================
example7_i-e_t-0.5.v
	
endcase

========================================================
example8_i-e_t-0.5.v


endcase

========================================================
example9_i-e_t-0.5.v
	
endcase

========================================================
example5_i-e_t-0.7.v
// assign end_stream = (dii_busy || dio_busy) ? 1'b1 : 1'b0;

// assign end_stream = (dio_busy) ? 1'b1 : 1'b0;
// assign end_stream = (dio_busy || dii_busy) ? 1'b1 : 1'b0;
//assign end_stream = (dio_busy) ? 1'b1 : 1'b0;
assign end_stream = (dio_busy || dii_busy) ? 1'b1 : 1'b0;
assign status_read = (dio_busy) ? 1'b1 : 1'b0;


endcase

========================================================
example6_i-e_t-0.7.v


endcase

========================================================
example7_i-e_t-0.7.v
//customer is notified if daa is ready
//assign daa_ready = (dii_data_not_ready == 0);
//assign daa_ready = (dii_data_not_ready == 0);

//assign daa_ready_8 = (dii_data_not_ready == 0);
//assign daa_ready_11 = (dii_data_not_ready == 0);
//assign daa_ready_15 = (dii_data_not_ready == 0);
//assign daa_ready_16 = (dii_data_not_ready == 0);
//assign daa_ready_17 = (dii_data_not_ready == 0);
//assign daa_ready_18 = (dii_data_not_ready == 0);
//assign daa_ready_
endcase

========================================================
example8_i-e_t-0.7.v
	
	
	
	
	

endcase

========================================================
example9_i-e_t-0.7.v
//	case
//
//
//
//

endcase

========================================================
example5_i-e_t-0.9.v
//case statement:
// c, e, and f with semi colons
// "continuating" to point the the new array you created
//can't i thought this a array variable???
//remove when reach
//can't have a array variable???
//can't i have a array variable???
//i have a array variable
//_
//can have an array variable and a second one initializing it???
//consume the input in a subroutine to increase the speed
//c and e have same location: due to if statement
//all other arrays have the same address
//b is a array variable 9N
//1.5 HCLK for low bit rate
//1.9 for 2.3 kHz

//linux specify options in clang -> options -> linker -> google linker. 
// -o comes from terminal. i will delete the second parameter.
check_model_root
endcase

========================================================
example6_i-e_t-0.9.v
	
// `define DEFAULT_LOG
//`define LOG1
`define LOG2
//`define LOG1_ASYNC
//`define LOG2_ASYNC
//`define LOG1_
//`define LOG2_
//`define LOGIC_GENERATOR
//`include file_10.v
//`include file_11.v
//`include file_12.v
//`include file_13.v
//`include file_14.v
//`include file_15.v
//`include file_16.v
//`include file_17.v
//`include file_18.v
//`include file_19.v
//`include file_20.v
//`include file_21.v
//`include file_22.v
//`include file_23.v
//`include file_24.v
//`
endcase

========================================================
example7_i-e_t-0.9.v
//draw on screen, print, erase, redraw screen, copy, enable
//test
//draw line
//test input
//reset
//this
module Line_Scanner_Top
(CLK, RESET, STEPM, SCOUNT, XCOUNT, YCOUNT, EN_LEFT, EN_RIGHT, Simulation, Line_D, Line_ENC, Line_Flag, IN_D1, IN_D2, Line_INPUT, STATE, Line_MAX);
parameter X_HALF = 16;
parameter Y_HALF = 16;

input CLK, RESET, STATE, STEPM;
input [3:0] SCOUNT;
input [6:0] XCOUNT, YCOUNT;
input EN_LEFT, EN_RIGHT, Line_INPUT;
output [6:0] YCOUNT, Line_D
endcase

========================================================
example8_i-e_t-0.9.v


endcase

========================================================
example9_i-e_t-0.9.v
pragma endtrace "on"

// testing added code 8/11/13: 
harness_mocks s11(.ch8toT1(input_ch8), .ch8FromT1(output_ch8),.ch8toT2(output_ch8_1),.ch8FromT2(ch11_out),.ch11toT3(input_ch11), .ch11FromT3(output_ch11),.ch11toT4(output_ch11_1), .ch11FromT4(ch11_out));
//CH8 T1 => CH8 T2
//CH8 from T1 => CH8 from to T2
//CH11 from T3 => CH11 from to T4
//CH11 to T3

//CH8 T2 => CH9 from T3
//CH9 from T3 => CH9 T
endcase

========================================================
example10_i-e_t-0.1.v
	
endcase

========================================================
example11_i-e_t-0.1.v
	
endcase

========================================================
example12_i-e_t-0.1.v
	
endcase

========================================================
example13_i-e_t-0.1.v
	
endcase

========================================================
example14_i-e_t-0.1.v
	
endcase

========================================================
example10_i-e_t-0.3.v
	
endcase

========================================================
example11_i-e_t-0.3.v
	case
	default:
	
endcase

========================================================
example12_i-e_t-0.3.v
	case
	
endcase

========================================================
example13_i-e_t-0.3.v
	
endcase

========================================================
example14_i-e_t-0.3.v
	case
	
endcase

========================================================
example10_i-e_t-0.5.v
// endcase
// endcase
// endcase
// endcase

endcase

========================================================
example11_i-e_t-0.5.v
	
endcase

========================================================
example12_i-e_t-0.5.v
	
endcase

========================================================
example13_i-e_t-0.5.v
	
endcase

========================================================
example14_i-e_t-0.5.v
	case
	...
	
endcase

========================================================
example10_i-e_t-0.7.v
`endif
//ifndef
`endif


`define TARGET "xilinx"
`include "string_functions.v"

module string_functions_tb;

reg[11:0] arg;
reg arg_is_null;

string_functions UUT(arg, arg_is_null);

initial begin
arg = 11'b110011000111;
arg_is_null = 1'b0;
#10;
arg_is_null = 1'b1;
#10;
end


endcase

========================================================
example11_i-e_t-0.7.v
	case 
	
endcase

========================================================
example12_i-e_t-0.7.v
initial begin
	regfile = {{32{1'b1}},32'b0};	
	reg_dest = {5'd0,5'd0};
	reg_dest_ext = {5'd0,5'd0};
	reg_write_num = 4'd0;
	reg_write_num_in_ex = 4'd0;
	reg_write_num_in_exe = 4'd0;
	reg_write_num_in_exe = 4'd0;
	reg_write_num_in_exe = 4'd0;
	regs_to_write = 4'd0;
	regs_written = 4'd0;
	regs_to_write = 4'd0;
	regs_in_ex = 4'd0;
	regs_in_exe = 4'd0;
	regs_in
endcase

end

========================================================
example13_i-e_t-0.7.v
always @(*) begin
case (state)
S0:	begin
	case (code)
	0:	begin
	new	:	state <= S1;
	old:	state <= S2;
	
endcase

end

end

end

========================================================
example14_i-e_t-0.7.v
	case {1'b1}
	
endcase

========================================================
example10_i-e_t-0.9.v
	always
	case
	
endcase

========================================================
example11_i-e_t-0.9.v
module my_rxtx (clk, rst, din, dout);
input clk;
input rst;
input pin;
output dout;
reg reg_dout;
assign dout = pin ? reg_dout : 0;
always @(posedge clk) begin
	if (rst) begin
	end
	else begin
	end
end

endcase

========================================================
example12_i-e_t-0.9.v
// end case
// endcase
end
/*
 * tasks
 */

vTask0 v0 (input_pc, s0, lda, lock, undeploy);
vTask1 v1(input_pc, s1, lock, undeploy);
vTask2 v2(input_pc, s2, lda, undeploy);
vTask3 v3(input_pc, s3, lda, undeploy);
vTask4 v4(input_pc, s4, lda, undeploy, waitr);
vTask5 v5(input_pc, s5, waitr, undeploy);
vTask6 v6(input_pc, s6, lock, undeploy);
vTask7 v7(input_pc, s7, lock, undeploy);
vTask8 v8(input_pc, s8);
vTask9 v9(
endcase

========================================================
example13_i-e_t-0.9.v
assign logic_collision = rcv_data[7:4] == rcv_data[3:2];


endcase

========================================================
example14_i-e_t-0.9.v
/*
assign Out_data
= (text_word==0)?dixio_data:(text_word==1)?jola_data:(text_word==2)?dixi_data:Dummy_tbus;
*/
assign Out_data
= (text_word==0)?edi_data:(text_word==1)?r_j_o_tbus_inst:(text_word==2)?Dummy_tbus:Dummy_tbus;

assign 	Out_p_t
= (text_word==0)?edi_p:24'hFFFFF00000
//(text_word==1)?r_j_o_tbus_inst:(text_word==2)?Dummy_tbus:Dummy_tbus;

endcase

========================================================
example15_i-e_t-0.1.v
	
endcase

========================================================
example16_i-e_t-0.1.v
	
endcase

========================================================
example17_i-e_t-0.1.v
	
endcase

========================================================
example18_i-e_t-0.1.v
	
endcase

========================================================
example19_i-e_t-0.1.v
	
endcase

========================================================
example15_i-e_t-0.3.v
	
endcase

========================================================
example16_i-e_t-0.3.v
	
endcase

========================================================
example17_i-e_t-0.3.v
	
endcase

========================================================
example18_i-e_t-0.3.v
always @(posedge clk or posedge rst) begin
	if (rst) begin
	end
	else begin
	end

endcase

end

========================================================
example19_i-e_t-0.3.v
	
endcase

========================================================
example15_i-e_t-0.5.v


endcase

========================================================
example16_i-e_t-0.5.v
	case (state)
	s0:	begin
	s1:	begin
	s2:	begin
	s3:	begin
	s4:	begin
	s5:	begin
	s6:	begin
	s7:	begin
	s8:	begin
	s9:	begin
	s10:	begin
	s11:	begin
	s12:	begin
	s13:	begin
	s14:	begin
	s15:	begin
	
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example17_i-e_t-0.5.v
assign input_pc = 4'h0;
assign output_pc = 4'h0;
assign output_pc_val = 1'b0;
assign output_pc_val_in = 1'b0;
assign output_pc_type = 1'b0;
assign output_pc_type_in = 1'b0;
assign output_pc_wren = 1'b0;
assign output_pc_wren_in = 1'b0;
//assign output_pc_rden = 1'b0;
//assign output_pc_rden_in = 1'b0;
assign output_pc_hwen = 1'b0;
assign output_pc_hwen_in = 1'b0;
assign output_pc_hwren = 1'b0;
assign output
endcase

========================================================
example18_i-e_t-0.5.v
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(!dii_data_vld)
	if(
endcase

========================================================
example19_i-e_t-0.5.v
	case
	
endcase

========================================================
example15_i-e_t-0.7.v
	
endcase

========================================================
example16_i-e_t-0.7.v
	
endcase

========================================================
example17_i-e_t-0.7.v
always @(posedge clk) begin
	if (rst == 1) begin
	end
	else begin
	end

endcase

end

========================================================
example18_i-e_t-0.7.v
/*
always @(posedge clk) begin
	if (rst == 1'b1) begin
	end
	else begin
	end
end
*/

endcase

========================================================
example19_i-e_t-0.7.v
finalize_output(dout_output);


endcase

========================================================
example15_i-e_t-0.9.v
//	Assign a value to a given input
//	based on an enuminput
always @* begin
case(bitplane_np)
3'd0: V_input = 8'd0;
3'd1: V_input = 32'd4;
3'd2: V_input = 32'd11;
3'd3: V_input = 32'd0;

endcase

end

========================================================
example16_i-e_t-0.9.v
// case statement of above
//

endcase

========================================================
example17_i-e_t-0.9.v
//this is the formal system output for the user 
//assembly code.
//this will be a x format formated string which will have the 
//user sprocket declared in it.
//this is for checking that the vault is storing the right info
assign product_default = prod_word;

//this allows the testbench to look at the intermedi. file
assign temp = prod_word;

//this allows the testbench to see the final text file.
assign final_out= temp;


endcase

========================================================
example18_i-e_t-0.9.v
// endcase

endcase

========================================================
example19_i-e_t-0.9.v

endcase

========================================================
example15_i-a_t-0.1.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example16_i-a_t-0.1.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example17_i-a_t-0.1.v
	
endcase

========================================================
example18_i-a_t-0.1.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example19_i-a_t-0.1.v
	
endcase

========================================================
example15_i-a_t-0.3.v
//	if (dii_data_not_ready == 0)
//	begin
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end
//	else
//	begin
//	end
//	end

endcase

========================================================
example16_i-a_t-0.3.v
	case of the state
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

endcase

========================================================
example17_i-a_t-0.3.v
	
endcase

========================================================
example18_i-a_t-0.3.v
	if (dii_data_not_ready == 0) begin
	
endcase

end

========================================================
example19_i-a_t-0.3.v
	case (state)
	s0:
	begin
	
endcase

end

========================================================
example15_i-a_t-0.5.v
	
endcase

========================================================
example16_i-a_t-0.5.v
	
endcase

========================================================
example17_i-a_t-0.5.v
	reg [31:0] temp;
	always @(posedge clk) begin
	temp <= {dii_data_not_ready, dii_data_final};
	end
	assign temp = {dii_data_not_ready, dii_data_final};
	assign Out_data = (dii_data_not_ready == 1'b1) ? dii_data_final : 32'd0;
	assign Out_data = temp;
	assign Out_data = (dii_data_not_ready == 1'b1) ? dii_data_final : 32'd0;
	assign Out_data = (dii_data_not_ready == 1'b1) ? 32'd0 : dii_data_final;
	assign Out_data =
endcase

========================================================
example18_i-a_t-0.5.v
	case (state)
	0: begin
	
endcase

end

========================================================
example19_i-a_t-0.5.v
	RFC 1.0 does not allow the termination character '\n' in the header field.
	RFC 1.0 allows the termination character '\r' in the header field.
	RFC 2.0 allows the termination character in the header field.
	RFC 2.0 allows the termination character '\n' in the header field.
	RFC 3.0 allows the termination character '\r' in the header field.
	RFC 3.0 allows the termination character '\n' in the header field.
	RFC 4.0 allows the termination character '\r' in the header field.
	RFC 4.0 allows the termination character '\n' in the header field.
	RFC 4.0 allows the termination character '\r' in the header field.
	RFC 4.0 allows the termination character '\n' in the header field.
	
endcase

========================================================
example15_i-a_t-0.7.v
	always @(posedge clk) begin
	case(state)
	s0: begin
	end
	ENDTEST:
	
endcase

end

========================================================
example16_i-a_t-0.7.v
	add a flag in the packet to indicate the end of the packet and only allow the
	packet to be sent when the flag is processed
	
	alternate:
	
	begin

	
endcase

========================================================
example17_i-a_t-0.7.v
//	always @(posedge sys_clk) begin
//	<= current_state;
//	end
//	always @(posedge sys_clk)
//	begin
//	<= current_state;
//	end
//	always @(posedge sys_clk)
//	begin
//	<= current_state;
//	end
//	always @(posedge sys_clk)
//	begin
//	<= current_state;
//	end
//	always @(posedge qsys_clk)
//	begin
//	<= current_state;
//	end
	always @(posedge qsys_clk)
	begin
	<= current_state;
	end
	always @(posedge qsys_clk)
	begin
	<= current_state;
	
endcase

end

========================================================
example18_i-a_t-0.7.v
//
//assign t_usec = t_usec;
//assign t_usec = ((t_usec & 64'hffffffffffffffff) >> 6);
//assign t_usec = ((t_usec >> 6) & 64'hffffffffffffffff);
//assign t_usec = t_usec >> 6;
//assign t_usec = t_usec & 64'hffffffffffffffff;
//assign t_usec = t_usec;

endcase

========================================================
example19_i-a_t-0.7.v
always@(*) begin
	case(joint_ID)
	1: joint_pos1_r <= {28'b0,joint_pos1[31:2]};
	2: joint_pos2_r <= {28'b0, joint_pos2[31:2]};
	3: joint_pos3_r <= {28'b0, joint_pos3[31:2]};
	
endcase

end

========================================================
example15_i-a_t-0.9.v
procl3 <= counter <= 1'b0;
procl5 <= counter3 <= 1'b0;

endcase

========================================================
example16_i-a_t-0.9.v
//end //mitter : change

endcase

========================================================
example17_i-a_t-0.9.v
	
endcase

========================================================
example18_i-a_t-0.9.v
	
endcase

========================================================
example19_i-a_t-0.9.v
// structure and format:
// |word_token|word_token|... token|
// word_token can be 0, 1 or 2. Before the word tokens, is the the nUmber of the tokens in the
// structure. After the last word, is the nUmber of extracted tokens that was output.
// --------------------------------------------------------------------------------
//
task Card_2_Second_Phase (
	input [11:0] pin_2,
	input [11:0] pin_1,
	input [11:0] pin_0,
	input [11:0] numerical_const,
	input [11:0] proven_answer
);

parameter length = 13; // length of Bit_Concatenations

localparam St = 0, S1 = 11;
localparam State [] = {St,1'b0,1'b0};
localparam Input_
endcase

========================================================
example15_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example16_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example17_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example18_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example19_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example15_i-b_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example16_i-b_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example17_i-b_t-0.3.v
	case(state)
	0:	begin
	end
	1:	begin
	end
	2:	begin
	end
	3:	begin
	end
	4:	begin
	end
	5:	begin
	end
	
endcase

========================================================
example18_i-b_t-0.3.v
	case (state)
	0:	begin
	end
	1:	begin
	end
	2:	begin
	end
	3:	begin
	end
	4:	begin
	end
	5:	begin
	end
	6:	begin
	end
	7:	begin
	end
	8:	begin
	end
	9:	begin
	end
	10:	begin
	end
	11:	begin
	end
	12:	begin
	end
	13:	begin
	end
	14:	begin
	end
	15:	begin
	end
	default:	begin
	end
	
endcase

========================================================
example19_i-b_t-0.3.v
	case (dii_data_type)
	0:	assign dii_data_out = dii_data_in;
	1:	assign dii_data_out = {dii_data_in[31:16], dii_data_in[15:0]};
	2:	assign dii_data_out = {dii_data_in[15:0], dii_data_in[31:16]};
	3:	assign dii_data_out = {dii_data_in[15:0], dii_data_in[31:16]};
	4:	assign dii_data_out = {dii_data_in[31:16], dii_data_in[15:0]};
	5:	assign dii_
endcase

========================================================
example15_i-b_t-0.5.v
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_data = dii_data_out;
assign output_
endcase

========================================================
example16_i-b_t-0.5.v

endcase

========================================================
example17_i-b_t-0.5.v
	case (state)
	S0: begin
	
endcase

end

========================================================
example18_i-b_t-0.5.v
	case (state)
	0:	begin
	end
	1:	begin
	end
	2:	begin
	end
	3:	begin
	end
	4:	begin
	end
	
endcase

========================================================
example19_i-b_t-0.5.v
	case
	
endcase

========================================================
example15_i-b_t-0.7.v
	always @(*) begin
	
endcase

end

========================================================
example16_i-b_t-0.7.v
assign Out_data = DAT_data_out;
//assign Out_data = DAT_data_out;

assign ct_data = ct_data_out;

assign ct_data_out = DAT_data_out;

// WARNING: This is a Rev 1.9 bug.
// In current version, the data_out is the data_out stored in the output register
// So we have to use the output register to store the data 
assign {ct_data_out, reg_data_out} = DAT_data_out;

always @ (posedge rst or posedge clock) begin
	if (rst == 1'b1) begin
	// TODO: implement reset to the output register
	end
end


endcase

========================================================
example17_i-b_t-0.7.v

endcase

========================================================
example18_i-b_t-0.7.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

//
//
//





//
//




//Sending the request
assign req_out = cb_requester_output;
//creating the requester
wire [7:0] addr;
wire cb_request_done;
reg cb_request_done_reg;
reg req_out_reg;
altsyncram the_device (
	.address_a (addr),
	.address_b (1
endcase

========================================================
example19_i-b_t-0.7.v
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
endcase

========================================================
example15_i-b_t-0.9.v
end
assign Out_data3 = get_data3_from_o_stream_and_put_it_in_data;
assign calib_data_0_in = calib_data_0;
assign calib_data_1_in = calib_data_1;
assign calib_source_in = calib_source;
//assign jtag_load_in = jtag_load;
router router_inst(data, data_return, big_end, jtag_load, jtag_store, set, clk, dtr, dcd, dr, tr, cmd, we, addr);
// router router_inst(\data[20]~Q, \data_return[20]~Q, big_end, jtag_load_in, jtag_store_in, set, jtck, ddrr, dcd, dr, ttr
endcase

========================================================
example16_i-b_t-0.9.v
end
end

endcase

========================================================
example17_i-b_t-0.9.v
/*
assign input_pc = input_pc_mac ? input_pc_mac : 4'h0;
assign output_pc = (output_pc_mac && (output_pc_mac != 4'h0)) ? output_pc_mac : 4'h0;
*/

endcase

========================================================
example18_i-b_t-0.9.v

//
//write_to_memory
//mem_array_index ???
//
gates_array = In_data;
data_source_array = cit_values;


assign read_data_out = read_data_out_array[memory_address];

always @*
begin
case(read_data_out_array[0].size)
1:begin
memory_address = read_data_out_array[0].ptr;

end
2:begin
memory_address = read_data_out_array[0].ptr;

end
4:
begin
memory_address = read_data_out_array[0].ptr;

end

endcase

end

========================================================
example19_i-b_t-0.9.v
end


endcase

========================================================
example15_i-c_t-0.1.v
	case (1'b1)
	
endcase

========================================================
example16_i-c_t-0.1.v
	case (1'b1)
	
endcase

========================================================
example17_i-c_t-0.1.v
	
endcase

========================================================
example18_i-c_t-0.1.v
	
endcase

========================================================
example19_i-c_t-0.1.v
	
endcase

========================================================
example15_i-c_t-0.3.v
	case (1'b1)
	
endcase

========================================================
example16_i-c_t-0.3.v
	case (1'b1)
	
endcase

========================================================
example17_i-c_t-0.3.v
	
endcase

========================================================
example18_i-c_t-0.3.v
	case (state)
	1: begin
	
endcase

end

========================================================
example19_i-c_t-0.3.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example15_i-c_t-0.5.v
	case (param)
	parameter 0
	
endcase

========================================================
example16_i-c_t-0.5.v
	default: begin...
	
endcase

end

========================================================
example17_i-c_t-0.5.v
	a.	
	b.	
	c.	
	d.	
	e.	
	f.	
	g.	
	h.	
	i.	
	j.	
	k.	
	l.	
	m.	
	n.	
	o.	
	p.	
	q.	
	r.	
	s.	
	t.	
	u.	
	v.	
	w.	
	x.	
	y.	
	z.	
	A.	
	B.	
	C.	
	D.	
	E.	
	F.	
	G.	
	
endcase

========================================================
example18_i-c_t-0.5.v
	case (state)
	0: begin
	end
	1: begin
	end
	2: begin
	end
	default begin
	end
	
endcase

========================================================
example19_i-c_t-0.5.v
	Incomplete case statement
	case
	
endcase

========================================================
example15_i-c_t-0.7.v
core_data_bits
core_data_str
core_data_str_size
core_data_type
core_data_type_size
core_data_vld
core_str_bits
core_str_data
core_str_data_size
core_str_type
core_str_type_size
core_str_vld
core_type_bits
core_type_str
core_type_str_size
core_type_vld
core_vld
core_word_bits
core_word_str
core_word_str_size
core_word_type_str
core_word_type_str_size
core_word_type_vld
core_word_type_vld_str
core_word
endcase

========================================================
example16_i-c_t-0.7.v


endcase

========================================================
example17_i-c_t-0.7.v
	case
	
endcase

========================================================
example18_i-c_t-0.7.v
case (1'b1)
	1'b0:	begin
	end
	1'b1:	begin
	end
//default:	begin
//end

endcase

========================================================
example19_i-c_t-0.7.v
	
endcase

========================================================
example15_i-c_t-0.9.v
//I have the assumption that dbus is never ever used 
	default :
	 begin
	end
	
endcase

========================================================
example16_i-c_t-0.9.v

endcase

========================================================
example17_i-c_t-0.9.v
default __end
;
// the state of execution is stored in the current state variable

endcase

========================================================
example18_i-c_t-0.9.v
default:ensor_enable <='bx;


endcase

========================================================
example19_i-c_t-0.9.v

endcase

========================================================
example15_i-d_t-0.1.v
	case (state)
	default:
	
endcase

========================================================
example16_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example17_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example18_i-d_t-0.1.v
	case (state)
	default:
	
endcase

========================================================
example19_i-d_t-0.1.v
	case (state)
	default:
	
endcase

========================================================
example15_i-d_t-0.3.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example16_i-d_t-0.3.v
	case (state)
	default:
	
endcase

========================================================
example17_i-d_t-0.3.v
	initial state = 0;
	always @(*) begin
	case (state)
	0: begin
	
endcase

end

end

========================================================
example18_i-d_t-0.3.v
	case (state)
	default:
	
endcase

========================================================
example19_i-d_t-0.3.v
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
endcase

========================================================
example15_i-d_t-0.5.v
case state
default state

endcase

========================================================
example16_i-d_t-0.5.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example17_i-d_t-0.5.v
/*
	case (state)
	0: state <= state;
	1: state <= state;
	2: state <= state;
	3: state <= state;
	4: state <= state;
	5: state <= state;
	6: state <= state;
	7: state <= state;
	8: state <= state;
	9: state <= state;
	10: state <= state;
	11: state <= state;
	12: state <= state;
	13: state <= state;
	14: state <= state;
	15: state <= state;
	default: state <= 0;
	
endcase

========================================================
example18_i-d_t-0.5.v
	if (some_condition)
	begin
	some_code;
	end
	else
	begin
	some_other_code;
	end
	
endcase

========================================================
example19_i-d_t-0.5.v
//	initial state = 0;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;
//	initial state = state;

endcase

========================================================
example15_i-d_t-0.7.v
reg[2:0] state = s0;
always @(posedge clk or posedge reset)
begin
if (reset)
state <= s0;
else
state <= state + 1;
end
// *** 

// FIX:
always @(posedge clk)
begin
case(state)
s0: begin
 
;
end
s1: 
state <= s0;
s2: 
state <= s0;
s3: 
state <= s0;
s4: 
state <= s0;
s5: 
state <= s0;
s6: 
state <= s0;
s7: 
state <= s0;
s8: 
state <= s0;
s9: 
state <= s0;
s10: 
state <= s0;
s11: 

endcase

end

========================================================
example16_i-d_t-0.7.v
/*
	state = 0
	
	
	// your default case
	
	
	
	
*/
//initial 
// begin
// state = 0;
// end

//always @(posedge clk)
//begin
//case (state)
//
//	default:
//	begin
//
//
//	end
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example17_i-d_t-0.7.v
	case
	
endcase

========================================================
example18_i-d_t-0.7.v
 If state is 0 this will make initial state 0. This is an initial state.
 0 is not a good state for this.
 We can assign this state to a variable and then use that to control 
 the initial state of the FSM.

 state = 0;

endcase

========================================================
example19_i-d_t-0.7.v
	case state
	default: state = state;
	
endcase

========================================================
example15_i-d_t-0.9.v
// when no input type
// how do we seperate user input and d2i input. d2i can be type 0 and user input can be type 1.
// how do we seperate between two
end





endcase

========================================================
example16_i-d_t-0.9.v

//	
endcase

========================================================
example17_i-d_t-0.9.v
//state_numb" 0" is not accepting input for some reason..



endcase

========================================================
example18_i-d_t-0.9.v
	
	
endcase

========================================================
example19_i-d_t-0.9.v
	
	if(ct_valid == 1 && ct_ready == 0){
	assign state=s15; //try ready
	assign next_state=s15;
	end

	else begin
	assign state=s0; //try idle
	assign next_state=s0;
	end
	
	
endcase

========================================================
example0_i-a_t-0.1.v
	
endcase

========================================================
example1_i-a_t-0.1.v
	
endcase

========================================================
example2_i-a_t-0.1.v
	if(dii_data_not_ready == 0) begin
	
endcase

end

========================================================
example3_i-a_t-0.1.v
	case (state)
	S0: begin
	
endcase

end

========================================================
example4_i-a_t-0.1.v
	
endcase

========================================================
example0_i-a_t-0.3.v
	if (ct_valid == 1) begin
	
endcase

end

========================================================
example1_i-a_t-0.3.v
	
endcase

========================================================
example2_i-a_t-0.3.v
	
endcase

========================================================
example3_i-a_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example4_i-a_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example0_i-a_t-0.5.v
	always @* begin
	case (state)
	0: begin
	
endcase

end

end

========================================================
example1_i-a_t-0.5.v
	
endcase

========================================================
example2_i-a_t-0.5.v
	
endcase

========================================================
example3_i-a_t-0.5.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example4_i-a_t-0.5.v
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
endcase

========================================================
example0_i-a_t-0.7.v
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example1_i-a_t-0.7.v
//	skusing 
//	
//	skusing
//	
//	skusing
//	
//	skusing
//	
//	skusing
//	
//	skusing
//	



endcase

========================================================
example2_i-a_t-0.7.v
	always @(*)
	begin
	case (o_state)
	S0: begin
	
endcase

end

end

========================================================
example3_i-a_t-0.7.v
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	engage network
	
endcase

========================================================
example4_i-a_t-0.7.v
	always @(*) begin
	case (state)
	S0: begin
	
endcase

end

end

========================================================
example0_i-a_t-0.9.v
//	state diagram
/*interface I2C_system_interface
{
regconst[4:0] slave_address;
regdispatcher[0:7] sys;
I2C[] interface
};*/
//	cat facilitie.behevuelog ofmassy
//	logn

	//checki 
	/*
	reg ff1;
	always @ (posedge clk)
	begin
	ff1 <= s1;
	end
	reg ff2;
	always @ (posedge clk)
	begin
	ff2 <= s2;
	end
	always @ (posedge clk)
	begin
	assert(ff1 == s1);
	assert(ff2 == s2);
	end
	*/


endcase

========================================================
example1_i-a_t-0.9.v
//	alternative solution
//	1. request the kernel code from the driver
//	2. make use of a dummy for output buffers
//	3. disable this, as we find a better way to do it

// 1.
// FIX: Difference above for the timeout period:
// difference must be lower than than the default timeout period
// default period: 80,
// timeout period: 5s

// (?!) to check a timeout period, counting period should be >= second period
// delta should be less than 1 time unit


// perhaps looks ugly, or it will never be found, but timeout can not be zero.
// if timeout is too small, time units would just be kept 
// while it is small and it is kept, it will get divided in the way of times
// so time units are allowed to become zero at the time that timeout has passed.
// until it reaches to -1
endcase

========================================================
example2_i-a_t-0.9.v
//	in comparison operator, assign as unsigned number, assign as signed number
//	and check unsigned number	

	
// reflex_s3:
// assign s3 as signed number
// r\s3 * s3
//assign s3_foo = r'hd;
//define d
//r\s3\s3 * d
//assign d_bar = r'ha;	
//define h
//r'ha * h
//wire signed h;
//assign b = r'ha * h;
//define g
//r'ha * g
//wire signed g
wire [3:0] s3_foo;
wire signed [3:0] s3;
assign s3_foo = r'h5 * s3;
always @* begin
	case {s3_foo}
	0: s3 = 4'b0000;
endcase

end

========================================================
example3_i-a_t-0.9.v
//	reg [N-1:0] data_r;
//	if(ct_valid == 1)
//	begin
//	data_r <= input_data;
//	end
//	else
//	begin
//	data_r <= 0;
//	end
//	always @(*)
//	begin
//	data_r <= data_r + 1;
//	end
//	assign output_data = data_r;
mcustom_reg (
	.clk(clk),
	.reset(reset),
	.data(data_r),
	.reg_id("reg_data"),
	.reg_type(register_type),
	.reg_width(32),
	.reg_visibility("none"),
	.reg_update_type("async"),
	.reg_file_name("")
endcase

========================================================
example4_i-a_t-0.9.v
// Because it was possible for C code to see all memory allocated,
// I don't want to see the dii top stuff, there's only 2 of DataMemory,
// and a data from the dii subsystem should come from the outside of the
// system, but if it is coming from the external, it should have a flag,
// and the system should ignore it if it's coming from data_from_outside.
// SHOULD ALSO check if it coming from a dma request.
// it will depend on some sort of mechanism (ok probably just DMA from 
// external storage)
// what does this mean -- we need to be able to get 2 data blocks 
// one from the subsystem, and the other from elsewhere 
// i'll probably just have it go through the outside, as an mux of sorts
// will need an idle value, actually


endcase

========================================================
example0_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example1_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example2_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example3_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example4_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example0_i-b_t-0.3.v
	
endcase

========================================================
example1_i-b_t-0.3.v
	
endcase

========================================================
example2_i-b_t-0.3.v
	case (state)
	s0: begin
	end
	s1: begin
	end
	s2: begin
	end
	s3: begin
	end
	s4: begin
	end
	s5: begin
	end
	s6: begin
	end
	s7: begin
	end
	s8: begin
	end
	s9: begin
	end
	s10: begin
	end
	s11: begin
	end
	s12: begin
	end
	s13: begin
	end
	s14: begin
	end
	s15: begin
	end
	
endcase

========================================================
example3_i-b_t-0.3.v
	case (state)
	0: begin
	
endcase

end

========================================================
example4_i-b_t-0.3.v
	case (state)
	0: begin
	
endcase

end

========================================================
example0_i-b_t-0.5.v
	4.11
	4.12
	4.13
	4.14
	4.15
	4.16
	4.17
	4.18
	4.19
	4.20
	4.21
	4.22
	4.23
	4.24
	4.25
	4.26
	4.27
	4.28
	4.29
	4.30
	4.31
	4.32
	4.33
	4.34
	4.35
	4.36
	4.37
	4.38
	4.39
	4.40
	4.41
	4.42
	4.43
	
endcase

========================================================
example1_i-b_t-0.5.v
	case statement
	case (1'b1)
	0
	1
	2
	
endcase

========================================================
example2_i-b_t-0.5.v
	always @(posedge clk) begin
	case (state)
	s0: state <= s1;
	s1: state <= s2;
	s2: state <= s3;
	s3: state <= s4;
	s4: state <= s5;
	s5: state <= s6;
	s6: state <= s7;
	s7: state <= s8;
	s8: state <= s9;
	s9: state <= s10;
	s10: state <= s11;
	s11: state <= s12;
	s12: state <= s13;
	s13: state <= s14;
	s14: state <= s15;
	s15: state <= s0;
	
endcase

end

========================================================
example3_i-b_t-0.5.v
//	case
//	1
//	2
//	3
//	4
//	5
//	6
//	7
//	8
//	9
//	10
//	11
//	12
//	13
//	14
//	15
//	16
//	17
//	18
//	19
//	20
//	21
//	22
//	23
//	24
//	25
//	26
//	27
//	28
//	29
//	30
//	31
//	32
//	33
//	34
//	35
//	36
//	37
//	38
//	39
//	40
//	41
//	42
//	43
//	44
//	45
//	46
//	47
//	48
//	49

endcase

========================================================
example4_i-b_t-0.5.v
	case (state)
	s0: begin
	end
	s1: begin
	end
	s2: begin
	end
	s3: begin
	end
	s4: begin
	end
	s5: begin
	end
	s6: begin
	end
	s7: begin
	end
	s8: begin
	end
	s9: begin
	end
	s10: begin
	end
	s11: begin
	end
	s12: begin
	end
	s13: begin
	end
	s14: begin
	end
	s15: begin
	end
	
endcase

========================================================
example0_i-b_t-0.7.v
// - sommerf
// - mattie
// - dave
// - eternf
// - hs
// - zonen1
// - zon2
// - zon3
//
// - dave
//-
// - eternf
//-
// - hs
//-
// - zonen1
//-
// - zon2
//-
// - zon3
//
// - zon3
//-
// - zon2
//-
// - zon1
//
//
// - eternf
//-
// - hs
//-
// - zonen1
//-
// - zon2
//-
// - zon3

//
// - zon3
//-
// - zon2
//-
// - zon1
//-
// - et
endcase

========================================================
example1_i-b_t-0.7.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example2_i-b_t-0.7.v
	
endcase

========================================================
example3_i-b_t-0.7.v
//	case
//	0:
//	end
//	1:
//	2:
//	end
//	3:
//	end
//	4:
//	end

endcase

========================================================
example4_i-b_t-0.7.v

endcase

========================================================
example0_i-b_t-0.9.v
//	case (state)
//"'s/\\/g"
//'s/\\/g
//'s/\\/g
//'s/\\/g
//'6'
// 6
//'101'
// 101
// 5
// 3
// 0
// "4"
/*
// SUPPORT MIF FILE READING //

function [string, real, int] get_named_token(string name, string open, string close, real default_real);
	string _token;
	real _real;
	integer _int;
	reg [string:0] _index;
	get_named_token _proxy(0, default_real, 0);
	_proxy.match_named_token(_index, _token, _real, _int);
	get_named_token result(
	.name(name),
	.open(_
endcase

========================================================
example1_i-b_t-0.9.v
// closed-mrf-andrewa/flows-ci-checker/ci-checker:
// C:\Users\eir\Desktop\ci-checker-go-v1.0.1\ci-checker-go.svelm/ci-checker-go_s.svelm.ve
// $OfInputFile: flow.sdc
// $Revision: 1.1.1.2.6
// $Date: Wed Apr 19 180 04:20:11 2020
// $Author: eirrome@centrebem.com
////
`define initial_pos_spaces 32'h1DE635

`define 
`timescale 1ns / 1ps

module pairComp

 typing pair_comp<= function(input a, input b);
	
	parameter n = 16;
	
	input [n-1:0]
endcase

========================================================
example2_i-b_t-0.9.v
//	always * Sub-function of the M-sub-module
//module submodule(input1, input2, output1);

module theSubmodule(input1, input2, output1);
	
	input1	input_value1;
	input2	input_value2;
	
	output1 output_value1;
	
	firstSubmodule firstSubModule(input_value1, input_value2, submodule1.output_value);
	
	secondSubmodule secondSubmodule(submodule1.output_value, input_value2, output_value);
	
	module finalSubmodule(submodule1.output_value, input_value2, output_value);
	

endcase

========================================================
example3_i-b_t-0.9.v
//verilog -S
	 $ iverilog -t net.dll /home/n0/axis2.test/../../rudi_mob_afi_p2/Cpp_Lab10_Cpp_RT.v

//verilog -S -p 10254 22::0
//verilog -S -p 10260 user_defines_override.v
net.dll -1'b0
del.exe -f "C:\Users\n0\Desktop\Endpoint_Config.mat" -->C:\Users\n0\Desktop\Endpoint_Config_Dumps\========= Endpoint_Config.mat DEL.

//verilog -S -p 10253 1::0 2::0 3::0 4::0 -->C:\Users\n0\Desktop\include\Connector1_Ddr_Interface_Parameter.v
posedge user_
endcase

========================================================
example4_i-b_t-0.9.v
// assignment as above
assign dat_o = {1'b1, 1'b0, input_pc[31:2]};

always@(*)
begin
if((input_pc[31:6] == "mips") && (input_pc[31:6] <= 28)) // does the call to mips take place sooner than should the mipsir, 
	//ir, and so on have been prepared for mipsir, or the program is larger than the current limit?
	begin
	CP_in_vld <= 1'b1;
	output_CP <= output_CP + 1;
	end
end



endcase

========================================================
example0_i-c_t-0.1.v
	
endcase

========================================================
example1_i-c_t-0.1.v
	
endcase

========================================================
example2_i-c_t-0.1.v
	
endcase

========================================================
example3_i-c_t-0.1.v
	case (1)
	
endcase

========================================================
example4_i-c_t-0.1.v
	
endcase

========================================================
example0_i-c_t-0.3.v
	case (input_data)
	
endcase

========================================================
example1_i-c_t-0.3.v
	
endcase

========================================================
example2_i-c_t-0.3.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example3_i-c_t-0.3.v
	case (s)
	default:
	
endcase

========================================================
example4_i-c_t-0.3.v
	case (state)
	1: begin
	
endcase

end

========================================================
example0_i-c_t-0.5.v
//	if(dii_data_not_ready == 0)
//	begin
//	end
//	else
//	begin
//	end


endcase

========================================================
example1_i-c_t-0.5.v
	
endcase

========================================================
example2_i-c_t-0.5.v
	case
	
endcase

========================================================
example3_i-c_t-0.5.v
	
endcase

========================================================
example4_i-c_t-0.5.v
default:
begin
	// do some thing
end

endcase

========================================================
example0_i-c_t-0.7.v

endcase

========================================================
example1_i-c_t-0.7.v
// Complete code
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
default: begin
	// do nothing
end

endcase

========================================================
example2_i-c_t-0.7.v
// See weird_source

endcase

========================================================
example3_i-c_t-0.7.v
//`include "../source/tester_includes.v"
//`include "../source/tester_includes.v"

endcase

========================================================
example4_i-c_t-0.7.v
//I think the following is the solution
//
//
//
//


rationalize num_out(Out_data, num_out);


endcase

========================================================
example0_i-c_t-0.9.v
//	issues with this line need tests and fixing
	assign Result = 0;


endcase

========================================================
example1_i-c_t-0.9.v
unsigned clk_cycle_period_frequency;
assign clk_cycle_period_frequency = clk_cycle_period_frequency == 0 ? 1 : clk_cycle_period_frequency;
assign current_cycle_len = (clk_cycle_period_frequency == 0) ? clk_cycle_period_frequency : clk_cycle_period_frequency;
assign current_period_len = (clk_cycle_period_frequency == 0) ? clk_cycle_period_frequency : clk_cycle_period_frequency;
assign cycle_to_do = (1'b1 * current_cycle_len - 1'b0 * current_period_len);
assign cycle_to_do_from_spm = (1'b1 * spm_cycle_to_do_function - 1'b0 * spm_cycle_to_do
endcase

========================================================
example2_i-c_t-0.9.v
case( both_fields )
1'b0: begin
chant_dii_data <= 0;
chant_dii_data_valid <= 0;
	
	
// Only run the following code if both fields are valid (but not lore is an issue if it is 00)
if(chant_dii_data_valid & cant_le_data_valid) // If a dispell is about to run, it should be 0xFFFFFFFF and an 'out' value 
begin
	// Through this the spell checker will not look like it is being fed a valid data array, this is all the spellchecker
// will think it's running and using it's own data, to make sure it works this way the spell checker was trying to implement a
// data array to be used for that purpose, so it would no longer need to use the array passed in to the spell checker to be used
endcase

end

end

========================================================
example3_i-c_t-0.9.v
 LOG: Starting a new interval
 GP FIRST TIME SEND TO THE VCLS
 MW: First 2 words are null
 MW: send data to the vcls - maybe we should make sure it is from the appropriate device or to the proper device
 MW: we should have a way to reset the vcls so that we can send data without data already been there
 MW: we should have a way so that we know when all the data has been sent
 MW: we should have a way so that we can pause data transfer
 MW: we should have a way so that we can resume data transfer
 MW: we should have a way so that we can watch data being sent/data being received.
 MW: what if the device has a problem and we need to bring another one instead.
 MW: we should have a way so add more devices to a device if need be.
 MW:
endcase

========================================================
example4_i-c_t-0.9.v

endcase

========================================================
example0_i-d_t-0.1.v
	case (state)
	default: state = state;
	
endcase

========================================================
example1_i-d_t-0.1.v
	
endcase

========================================================
example2_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example3_i-d_t-0.1.v
	case (state)
	default: state = state;
	
endcase

========================================================
example4_i-d_t-0.1.v
	case (state)
	default: state = state;
	
endcase

========================================================
example0_i-d_t-0.3.v
	case (state)
	default: begin
	end
	
endcase

========================================================
example1_i-d_t-0.3.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example2_i-d_t-0.3.v
	initial state = 0;
	always @(*) begin
	case(state)
	0: begin
	
endcase

end

end

========================================================
example3_i-d_t-0.3.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example4_i-d_t-0.3.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example0_i-d_t-0.5.v
	case (state)
	default: state = state;
	
endcase

========================================================
example1_i-d_t-0.5.v
	case
	`default`;
	
endcase

========================================================
example2_i-d_t-0.5.v
	state = state;
	
endcase

========================================================
example3_i-d_t-0.5.v
	initial
	begin

	end
	
endcase

========================================================
example4_i-d_t-0.5.v
//	`define STATE_0 s0
//	`define STATE_1 s1
//	`define STATE_2 s2
//	`define STATE_3 s3
//	`define STATE_4 s4
//	`define STATE_5 s5
//	`define STATE_6 s6
//	`define STATE_7 s7
//	`define STATE_8 s8
//	`define STATE_9 s9
//	`define STATE_10 s10
//	`define STATE_11 s11
//	`define STATE_12 s12
//	`define STATE_13 s13
//	`define STATE_14 s14
//	`define STATE_15 s15
//	`define STATE_16 s16
//	`define STATE_17 s17
//	`define STATE_18 s18
//	`define STATE_19 s19

endcase

========================================================
example0_i-d_t-0.7.v
	default
	begin
	
	end
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
endcase

========================================================
example1_i-d_t-0.7.v
	default: state = 8'h1;
	
endcase

========================================================
example2_i-d_t-0.7.v
`default
guaranteed_rst = 1'b1;
guaranteed_ct_val = 1'b0;
guaranteed_dii_val = 1'b0;
guaranteed_vld_ct_val = 1'b0;
guaranteed_vld_dii_val = 1'b0;
guaranteed_vld_ct_reg = 1'b0;
guaranteed_vld_dii_reg = 1'b0;
guaranteed_dii_reg = 1'b0;
guaranteed_vld_ct_master = 1'b0;
guaranteed_vld_dii_master = 1'b0;
guaranteed_dii_master = 1'b0;
guaranteed_vld_ct_slaves = 1'b0;
guarant
endcase

========================================================
example3_i-d_t-0.7.v
erron>/dev/null
<erron<
dev/null
<erron<
erron>/dev/null
<erron<
<erron<
erron>/dev/null
<erron<
<erron<
<erron<
erron>/dev/null
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<erron<
<er
endcase

========================================================
example4_i-d_t-0.7.v

endcase

========================================================
example0_i-d_t-0.9.v
case ((dii_data_not_ready/dii_data_valid)|(dii_data_not_ready/dii_data_invalid))
1'b1:begin
state <=1;
end
1'b0:begin
state <=0;
end

endcase

========================================================
example1_i-d_t-0.9.v
	always@(*) begin
state = s0;
	end
endgenerate


endcase

========================================================
example2_i-d_t-0.9.v
state[0] <= s0;
// <going to a state at any time>
reg temp;
always begin
temp = state[n];
end
assign n = (temp == 3'b011) ? temp:0;
//always add state if all state out
always begin
 case (state)
s0: n = 1;
s1: n = 7;
s2: n = 11;
s3: n = 13;
s4: n = 14;
s5: n = 16;
s6: n = 22;
s7: n = 24;
s8: n = 25;
s9: n = 31;
s10: n = 33;
s11: n = 34;
s12: n = 36;
s13: n = 40;
s14: n = 43;
s15: n = 49;
end
endcase

========================================================
example3_i-d_t-0.9.v

endcase

========================================================
example4_i-d_t-0.9.v

endcase

========================================================
example5_i-a_t-0.1.v
	
endcase

========================================================
example6_i-a_t-0.1.v
	
endcase

========================================================
example7_i-a_t-0.1.v
	case (state)
	S0: begin
	
endcase

end

========================================================
example8_i-a_t-0.1.v
	if (dii_data_not_ready == 0) begin
	
endcase

end

========================================================
example9_i-a_t-0.1.v
	
endcase

========================================================
example5_i-a_t-0.3.v
	
endcase

========================================================
example6_i-a_t-0.3.v
	
endcase

========================================================
example7_i-a_t-0.3.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example8_i-a_t-0.3.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example9_i-a_t-0.3.v
	case (state)
	S0: begin
	
endcase

end

========================================================
example5_i-a_t-0.5.v
	case (x)
	1: x = 1;
	2: x = 2;
	3: x = 3;
	
endcase

========================================================
example6_i-a_t-0.5.v
	when dii_data_not_ready is high, the first time it is checked
	the output is not set. The second time that it is checked the output
	is set.
	this happens when the user enters a new string and then
	the output is set.
	the output is set, but it is not cleared.
	this happens when the user hits enter.
	the output is set, but it is not cleared.
	this happens when the user hits enter.
	the output is set, but it is not cleared.
	this happens when the user hits enter.
	the output is set, but it is not cleared.
	this happens when the user hits enter.
	the output is set, but it is not cleared.
	this happens when the user hits enter.
	the output is set, but
endcase

========================================================
example7_i-a_t-0.5.v
	
endcase

========================================================
example8_i-a_t-0.5.v
	
endcase

========================================================
example9_i-a_t-0.5.v
//	rewrite the "switch" into a "case" statement
//	somehow check if there is a "case" statement, instead of just a "case"
//	if there is, then just use that one.
//	in a "case" there is a "default" statement.
//	so, there is no need to check the "default" statement.
//	also, the "case" must be inside a "compound statement"

//	in this case the "case" must be inside a "compound" statement, 
//	so, the "case" can be inside the "for" loop.
//	a "case" inside a "for" loop should be inside the "for" loop, 
//	so, the "case" can be inside the "switch"

//	there is no need to check the "default" statement.
//	a "
endcase

========================================================
example5_i-a_t-0.7.v
//	move to the next state when last word is in for loop
//	also use a single word buffer for the output
end

endcase

========================================================
example6_i-a_t-0.7.v
`define INSTANCEMAX 2000
//`define INSTANCEMAX 2000
//`define INSTANCEMAX 2000
//`define INSTANCEMAX 10240
`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEMAX 10240
//`define INSTANCEM
endcase

========================================================
example7_i-a_t-0.7.v
	
endcase

========================================================
example8_i-a_t-0.7.v
//	change it to be a output and then assign it to a reg in the next switch
//	stateme
/****************************************/
//End of Testbench
/****************************************/
initial begin
	g_s_t_r_n = 0;
	g_s_t_r_o = 0;
	g_s_t_r_v = 0;
	g_s_t_r_i = 0;
	g_s_t_r_l = 0;
	g_s_t_r_len = 0;
	g_s_t_r_vlen = 0;
	g_s_t_r_out = 0;
	g_s_t_r_out_len = 0;
	g_s_t_r_key = 0;
	g_s_t_r_iv = 0;
endcase

end

========================================================
example9_i-a_t-0.7.v
/*
if(dii_data_not_ready) begin
	case(DII_data_size)
	4'd8:
	begin
	//	DII_data_type
	//	DII_data
	end
	4'd16:
	begin
	//	DII_data_type
	//	DII_data
	end
	default:
	begin
	//	DII_data_type
	//	DII_data
	end
	
endcase

end

========================================================
example5_i-a_t-0.9.v
//beamformer....
// declarating intermediate 
reg [15:0] copy_out;
wire [15:0] p_line_data;

always @(posedge clk) begin
featureLine_array[featureLine_counter] = p_line_data;
end

always @(posedge clk) begin
featureLine_counter = featureLine_counter + 3'd1;
end
reg[2:0] idx_line;

assign idx_line = 3'd0;
assign p_line_data = featureLine_array[idx_line];



always @(posedge clk) begin
copy_out <= p_line_data;
end
always @(posedge clk) begin
intermediate_data[idx_line] <= p_line_data;
end
reg [15:0]
endcase

========================================================
example6_i-a_t-0.9.v
//	case ofstate_word / case ofstate_word
//	code: replace; with;
//	code: (s_word_length * s_word_length) + s_word_length
//	code: "s_word_length * s_word_length + s_word_length, s_word_length * s_word_length + s_word_length"
//	"""
/*
approximate length of each UDP, each is normalized at src_ip = time.
A = 1000*10, B = 11*10, sum = A, difference = 8*10
A = 11*10, B = 11*10, sum = A, difference = 11*10
A = 11*10, B = 11*10, sum = A, difference = 11*10, large

sum = 62*10, difference = 180*10
sum = 62*10
endcase

========================================================
example7_i-a_t-0.9.v


endcase

========================================================
example8_i-a_t-0.9.v

endcase

========================================================
example9_i-a_t-0.9.v
//	output as in this program:
//x&gHEXIaJnKnESepZ.1262


endcase

========================================================
example5_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example6_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example7_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example8_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example9_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example5_i-b_t-0.3.v
	case (x)
	1: begin
	end
	2: begin
	end
	3: begin
	end
	
endcase

========================================================
example6_i-b_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example7_i-b_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example8_i-b_t-0.3.v
	case (state)
	s0: begin
	end
	s1: begin
	end
	s2: begin
	end
	s3: begin
	end
	s4: begin
	end
	s5: begin
	end
	s6: begin
	end
	s7: begin
	end
	s8: begin
	end
	s9: begin
	end
	s10: begin
	end
	s11: begin
	end
	s12: begin
	end
	s13: begin
	end
	s14: begin
	end
	s15: begin
	end
	
endcase

========================================================
example9_i-b_t-0.3.v
	case (state)
	S0: begin
	
endcase

end

========================================================
example5_i-b_t-0.5.v
	case (state)
	IDLE: next_state = 0;
	S1: next_state = 0;
	S2: next_state = 0;
	S3: next_state = 0;
	S4: next_state = 0;
	S5: next_state = 0;
	S6: next_state = 0;
	S7: next_state = 0;
	S8: next_state = 0;
	S9: next_state = 0;
	S10: next_state = 0;
	S11: next_state = 0;
	S12: next_state = 0;
	S13: next_state = 0;
	S14: next_state = 0;
	S15: next_state = 0;

endcase

========================================================
example6_i-b_t-0.5.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example7_i-b_t-0.5.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:begin
	11:begin
	12:begin
	13:begin
	14:begin
	15:begin
	16:begin
	17:begin
	18:begin
	19:begin
	20:begin
	21:begin
	22:begin
	23:begin
	24:begin
	25:begin
	26:begin
	27:begin
	28:begin
	29:begin
	30
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example8_i-b_t-0.5.v
	if(dii_data_not_ready == 0) begin
	end
	if(dii_data_not_ready == 1) begin
	end
	if(dii_data_not_ready == 0) begin
	end
	if(dii_data_not_ready == 1) begin
	end
	if(dii_data_not_ready == 0) begin
	end
	if(dii_data_not_ready == 1) begin
	end
	if(dii_data_not_ready == 0) begin
	end
	if(dii_data_not_ready == 1) begin
	end
	if(dii_data_not_ready == 0) begin
	end
	if(dii_data_not_
endcase

========================================================
example9_i-b_t-0.5.v
	
endcase

========================================================
example5_i-b_t-0.7.v
	case (type)
	1: {word, doubleword}
	2: {halfword}
	
endcase

========================================================
example6_i-b_t-0.7.v
	case x
	
	
endcase

========================================================
example7_i-b_t-0.7.v
//	case (s)
//	0:
//	1:
//	2:
//	3:
//	4:
//	5:
//	6:
//	7:
//	default:
// endcase

endcase

========================================================
example8_i-b_t-0.7.v
//	always @(*) begin
//
//	end
//	always @(*) begin
//	
//	end
//	always @(*) begin
//
//	end
//	always @(*) begin
//
//	end

endcase

========================================================
example9_i-b_t-0.7.v
end

endcase

========================================================
example5_i-b_t-0.9.v
//virtual channel
half_rate_convergence anda100
assign data_from_pps = d100;
	 
half_rate_convergence anda90
assign data_from_pps = d90;
	 
half_rate_convergence anda85
assign data_from_pps = d85;
//now we need to tell the pps what to send from the converters the connections are incoming from
//
//embedded digital IO
//for the Digital IO we have 8 pins to send to the converters as data in and 8 pin to send the data out of the converters to
//for the digital IO we have 3 pins from the converters as data out and two for the combiner logic
//
//also we have to connect the output of the combiners with the converters as the data out of the converters need to be on the rising edge of the
endcase

========================================================
example6_i-b_t-0.9.v
//the first-in state
s0://start receiver for first-in state
s1://start receiver for first-in state
// the movement-in state will be starting from s2
s2://start movement receiver
s3://stop movement receiver
s4://start receiver for the second-push-in state
s5: //movement receiver for second cycle
s6: //stop receiver for the second cycle
s7: //second receiver for the second cycle
s8: //mirror line for the second cycle
s9: //finishing line for the second cycle

s10://finishing line receiver for the second cycle
s11: //first movement receiver for the second cycle
s12: //starting line for the second cycle
s13: //stop receiver for the second cycle
s14: //second receiver for the second cycle
s15: //finishing receiver for the the second cycle

/*
endcase

========================================================
example7_i-b_t-0.9.v
//	using the output type of dspram, we can avoid the following if check.
//	we can lose the bits in the ending .
//	we use the next dspram for data_out.
//	we do not want to initialize the word size at this point.
//	we have to change the size later when token have been sent, and the next dspram
//	will be initialized.
/*

//
//
// ====== Pseudo ======
//widget_name {
//	name
//	{param}
//	{begin name}
//	{end name}
//	{param}
//	{begin name}
//	{end name}
//	{param}
//	{begin name}
//	{end name}
//	{param}
//	{begin name}
//	{end name}
//	{
endcase

========================================================
example8_i-b_t-0.9.v
case (1'b1)

1
s9:
//	
endcase

========================================================
example9_i-b_t-0.9.v
// case statement
//	case (Word index)
//	0:	begin
//	index <= index + 1
//	1:	begin
//	index <= index + 1
//	this is the wrong working for test all 

endcase

========================================================
example5_i-c_t-0.1.v
	case (1)
	case (2)
	case (3)
	case (4)
	case (5)
	case (6)
	case (7)
	case (8)
	case (9)
	case (10)
	case (11)
	case (12)
	case (13)
	case (14)
	case (15)
	case (16)
	case (17)
	case (18)
	case (19)
	case (20)
	case (21)
	case (22)
	case (23)
	case (24)
	case (25)
	case (26)
	case (27)
	case (28)
	case (
endcase

========================================================
example6_i-c_t-0.1.v
	case (1'b1)
	1'b1
	1'b0
	default
	
endcase

========================================================
example7_i-c_t-0.1.v
	
endcase

========================================================
example8_i-c_t-0.1.v
	
endcase

========================================================
example9_i-c_t-0.1.v
	
endcase

========================================================
example5_i-c_t-0.3.v
	
endcase

========================================================
example6_i-c_t-0.3.v
	
endcase

========================================================
example7_i-c_t-0.3.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
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//
//
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//
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//
//
//
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//
//
//
//
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//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example8_i-c_t-0.3.v
	
endcase

========================================================
example9_i-c_t-0.3.v
	case (x)
	1
	2
	3
	4
	
endcase

========================================================
example5_i-c_t-0.5.v
	case
	1
	2
	3
	4
	5

	
endcase

========================================================
example6_i-c_t-0.5.v
	case (1)
	case (2)
	case (3)
	case (4)
	case (5)
	case (6)
	default
	
endcase

========================================================
example7_i-c_t-0.5.v
	
endcase

========================================================
example8_i-c_t-0.5.v

endcase

========================================================
example9_i-c_t-0.5.v
//	case (opcode)
//	default:
//	begin
//	end

endcase

========================================================
example5_i-c_t-0.7.v
	Add a default statement for when no cases are present
	default
	may do something like this:

 	reg [1:0]	count;
 	reg [3:0]	data_in;
 	reg [11:0]	data_out;
	always @(posedge clk or negedge rst) begin
	if (rst == 1'b0) begin
	count <= 2'b11;
	data_in <= 4'b1111;
	data_out <= 12'b1111111111111;
	end else if (count == 2'b11) begin
	data_in <= data_in + 4'b1;
	data_out <= data_out + 12'b1;
	end else begin
	count <= count - 1
endcase

end

end

========================================================
example6_i-c_t-0.7.v
Driver Coding
input	output	valid
0	1	0
1	0	0
2	1	0
3	1	1
4	1	1
5	1	1
6	1	1
7	1	1
8	1	1
9	1	1
10	1	1
11	1	1
12	1	1
13	1	1
14	1	1
15	1	1
16	1	1
17	1	1
18	1	1
19	1	1
20	1	1
21	1	1
22	1	1
23	1	1
24	1	1
25	1	1
26	1	1
endcase

========================================================
example7_i-c_t-0.7.v
// When true, it should keep the output, and do not share it with anybody else
// When false, it should not keep the output, but it should pass to the next operation.
case(keep_output)
 1'b1: begin
 //assign output_from_operation = input_data;
 if(share_output == 1'b1)
 assign output_from_operation = output_from_operation;
 else 
 assign output_from_operation = 0;
 end
 1'b0: begin
 if(share_output == 1'b1)
 assign output_from_operation = output_from_operation;
 else 
 assign output_from_operation = 0;
 end
 default: assign output_from_operation = input_data;
 endcase

endcase

========================================================
example8_i-c_t-0.7.v
	default:
	begin
	end
	
endcase

========================================================
example9_i-c_t-0.7.v


endcase

========================================================
example5_i-c_t-0.9.v
curl -H (?_=(H):
curl -H {72:}
normally curl wouldinv163
otherwise curl and curl will be interleaved
curl just giving out the binary data
on the other hand, I did not know that I could keep multiple read op
writer threads
so I'm keeping a single wait between reader and writer instead of complmenting the code
FIXED: I have increased the waiting time to 10ms to help the co-operation of the applications
that are using the NU's and DIII's
Also, I have detected a pb in the LINES_REG resource which will not allow the application to run.
When the application invokes the function setDCforLINE
the resource NU_LINES_REG will not allow the application to run until the DC is set.
So the pace that I am
endcase

========================================================
example6_i-c_t-0.9.v
//
//
/**오포매해요세케이상홀이미쟼맠전신희신주문일설쟐화면*/
//
/**/
/* 3문 피제 중 일반적스트링 로직적의 제어결과 제어메소링이 포함을 늘리지않을정적효귀에
꺀에
endcase

========================================================
example7_i-c_t-0.9.v
	
endcase

========================================================
example8_i-c_t-0.9.v
//	you must add a default case for coverage
//	--AEnd-

endcase

========================================================
example9_i-c_t-0.9.v
case 11: next_state = 'h2A6231;
//
endcase

========================================================
example5_i-d_t-0.1.v
	case (state)
	default: state = state;
	
endcase

========================================================
example6_i-d_t-0.1.v
	case (state)
	default:
	
endcase

========================================================
example7_i-d_t-0.1.v
	case (state)
	default: state = state;
	
endcase

========================================================
example8_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example9_i-d_t-0.1.v
	case (state)
	default:
	
endcase

========================================================
example5_i-d_t-0.3.v
	case (state)
	default:
	
endcase

========================================================
example6_i-d_t-0.3.v

endcase

========================================================
example7_i-d_t-0.3.v
	always @(posedge clock) begin
	case (state)
	default: begin
	end
	
endcase

end

========================================================
example8_i-d_t-0.3.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example9_i-d_t-0.3.v
	case (state)
	default:
	
endcase

========================================================
example5_i-d_t-0.5.v
	case (state)
	default:
	begin
	end
	
endcase

========================================================
example6_i-d_t-0.5.v
	initial state = 0;
	always @ (state)
	begin
	case (state)
	0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85
endcase

end

========================================================
example7_i-d_t-0.5.v
	initial state = s0;
	
endcase

========================================================
example8_i-d_t-0.5.v
	case (state)
	
endcase

========================================================
example9_i-d_t-0.5.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//

endcase

========================================================
example5_i-d_t-0.7.v
	
endcase

========================================================
example6_i-d_t-0.7.v
// in addition add a function that does no operation
// otherwise the value on data will be sound at the beginning of the program
// the other option is to make this value as it is...
// either way the data always is change at the given moment 

endcase

========================================================
example7_i-d_t-0.7.v
fopen_file, "r"
close_file
fopen_file, "w"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
fclose_file
fopen_file, "a"
endcase

========================================================
example8_i-d_t-0.7.v
	case (CS)
	10:	state = 1'b1;	//	ON
	11:	state = 1'b0;	//	OFF
	default:	state = 1'b0;
	
endcase

========================================================
example9_i-d_t-0.7.v
initial begin
state = 0;
end




always @(posedge i_clk) begin
	case(state)
	0: begin
	end
	1: begin
	end
	2: begin
	end
	3: begin
	end
	
endcase

end

========================================================
example5_i-d_t-0.9.v
always@(posedge clk, posedge reset)
begin
	if(reset == 1)
	begin
	reset_state <= s0;
	end
	else
	begin
	case(reset_state):
	0:	begin
	statename <= "s0";
	end
	1:	begin
	statename <= "s1";
	end
	2:	begin
	statename <= "s2";
	end
	3:	begin
	statename <= "s3";
	end
	default:	begin
	statename <= "s0";
	end
	
endcase

end

end

========================================================
example6_i-d_t-0.9.v
tc_state ST

enum DECODING_STATE

begin

DECODING_STATE

0

COMPLETED

0

10


BLANK
/////////

B

1

10


30/xxxx
10

3



A
B
C
F
G
H
I
J
L
O
P
Q

1111/***
1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/***

1111
1111/

1111
1111
*/
1111
1111/***
1111
1111/***
1111
1111/***
1111
1111/***
1111
endcase

end

========================================================
example7_i-d_t-0.9.v
//
case (state)
0000: state <= s0;
0001: state <= s1;
0010: state <= s2;
0011: state <= s3;
0100: state <= s4;
0101: state <= s5;
0110: state <= s6;
111: state <= s7;
1000: state <= s8;
1011: state <= s9;
1100: state <= s10;
1110: state <= s11;
1111: state <= s12;
1110: state <= s11;
1111: state <= s14;
1100: state <= s11;
1110: state <= s11;
1111: state <= s14;
1111: state <= s11;
1111: state <= s12;
1111: state <= s13;
1111: state <= s14;
1111: state <= s14;
1111:
endcase

========================================================
example8_i-d_t-0.9.v
initial 
	state = next_state;
always@(posedge clk)
	state = next_state;


endcase

========================================================
example9_i-d_t-0.9.v
/*	LP_A <= 4'b1010;
	LP_B <= 4'b1011;
	LP_C <= 4'b1012;
	LP_D <= 4'b0100;
	LP_GROUP <= 4'b1110; 
	LP_RST <= 4'b1110;
	ACT_MODE <= 5'b0011;
	RP_IDLE <= 4'b1111;
	RP_X = 9'b111111111;
	RP_PRE = 4'b1112;
	RP_Y = 4'b1111;
	RP_Z = 4'b1110;
	RP_GROUP = 4'b1110;
	RIP_ID = 8'b1111111111;
	AS_ID = 64'h000000000000000000000000;
	log_file = "insert.log";
	number = 2;

endcase

========================================================
example10_i-a_t-0.1.v
	case (state)
	s0: begin
	s1: begin
	s2: begin
	s3: begin
	s4: begin
	s5: begin
	s6: begin
	s7: begin
	s8: begin
	s9: begin
	s10: begin
	s11: begin
	s12: begin
	s13: begin
	s14: begin
	s15: begin
	
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example11_i-a_t-0.1.v
	
endcase

========================================================
example12_i-a_t-0.1.v
	
endcase

========================================================
example13_i-a_t-0.1.v
	if(dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example14_i-a_t-0.1.v
	if (dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example10_i-a_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example11_i-a_t-0.3.v
	
endcase

========================================================
example12_i-a_t-0.3.v
	if(dii_data_not_ready == 0)
	begin
	
endcase

end

========================================================
example13_i-a_t-0.3.v
	if(dii_data_not_ready == 0) begin
	
endcase

end

========================================================
example14_i-a_t-0.3.v
	case (state)
	0: begin
	
endcase

end

========================================================
example10_i-a_t-0.5.v
	
endcase

========================================================
example11_i-a_t-0.5.v
	commenting out the line below will solve the problem
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line 23: assign $value = $value; expected expression"
	"error: in line
endcase

========================================================
example12_i-a_t-0.5.v
//	if(dii_data_not_ready)
//	begin
//	dii_data_not_ready <= 1;
//	end

//	else if(dii_data_not_ready == 0)
//	begin
//	dii_data_not_ready <= 0;
//	end
//	else
//	begin
//	dii_data_not_ready <= 0;
//	end

//	
endcase

========================================================
example13_i-a_t-0.5.v
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case
//	case

endcase

========================================================
example14_i-a_t-0.5.v
	
endcase

========================================================
example10_i-a_t-0.7.v
	case (dii_data_not_ready)
	
endcase

========================================================
example11_i-a_t-0.7.v
	if(dii_data_not_ready) begin
	
endcase

end

========================================================
example12_i-a_t-0.7.v
//	assign out_data = 0;
//	assign out_data = 0;
//	assign out_data = 0;

//
//

endcase

========================================================
example13_i-a_t-0.7.v
	always @(posedge clk) begin
	case (state)
	0: begin clocks off.
	1: begin clocks on.
	2: clocks back on.
	default: begin clocks off.
	
endcase

end

end

end

end

========================================================
example14_i-a_t-0.7.v
//	assign Out_data = {5'b11111, byte_ch};

//	assign Out_data = {4'b1111, byte_ch};

//	assign Out_data = {4'b1111, byte_ch};

//	assign Out_data = {byte_ch, 4'b1111};
//	assign Out_data = {4'b1111, byte_ch};


endcase

========================================================
example10_i-a_t-0.9.v
//	reg_access_ins
//	reg_access_ins
//	block_detection
//	writeback
//	Reset release
//	Output Confirmation
//	Vector selection step for word boundary detection...


endcase

========================================================
example11_i-a_t-0.9.v
//	if (gt_reset) ???
//	else
//	if(gt_reset)
//	if(gt_reset)
always @(posedge gps_clk)
begin
	if(gps_stream_rd)
	begin
	if(gt_reset)
	begin
	tx_reset<=1'b1;
	gt_reset<=1'b0;
	end
	end
	else
	begin
	tx_reset<=1'b0;
	gt_reset<=1'b1;
	end 
end 
	
assign m_gps_data_in = gps_tx_data;
assign tx_reset = tx_reset_1;
always @(posedge gps_clk)
begin
	if (tx_reset_1 == 1'b1)
endcase

end

========================================================
example12_i-a_t-0.9.v
//
// {js19951130} assign output for example 16
assign output_for_example = 16'b00000000000000000000000000000011;
// {js19951130} for loop initialization or ":" in cpp file.
// {js19951130} print 6 words
// {js19951130} for loop iterator is unsigned integer.
for (i = 0; i < output_length_for_example; i = i + 1) begin
// {js19951130} assign i to unsigned integer
assign word_for_example = 
out_data[3*i+3*i+1+2*i+1+2*i+1] *
out_data[3*i+3*i+1+2*i+1+2*i+2] *
out_data[3*i+3*i+1+2*i+1+
endcase

end

========================================================
example13_i-a_t-0.9.v
//
//

endcase

========================================================
example14_i-a_t-0.9.v
	switch (
endcase

========================================================
example10_i-b_t-0.1.v
	case (state)
	s0: begin
	end
	s1: begin
	end
	s2: begin
	end
	s3: begin
	end
	s4: begin
	end
	s5: begin
	end
	s6: begin
	end
	s7: begin
	end
	s8: begin
	end
	s9: begin
	end
	s10: begin
	end
	s11: begin
	end
	s12: begin
	end
	s13: begin
	end
	s14: begin
	end
	s15: begin
	end
	
endcase

========================================================
example11_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example12_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example13_i-b_t-0.1.v
	case (state)
	0: begin
	
endcase

end

========================================================
example14_i-b_t-0.1.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example10_i-b_t-0.3.v
	case (state)
	S0: begin
	end
	S1: begin
	end
	S2: begin
	end
	S3: begin
	end
	S4: begin
	end
	S5: begin
	end
	S6: begin
	end
	S7: begin
	end
	S8: begin
	end
	S9: begin
	end
	S10: begin
	end
	S11: begin
	end
	S12: begin
	end
	S13: begin
	end
	S14: begin
	end
	S15: begin
	end
	
endcase

========================================================
example11_i-b_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example12_i-b_t-0.3.v
	case (state)
	0: begin
	1: begin
	2: begin
	3: begin
	4: begin
	5: begin
	6: begin
	7: begin
	8: begin
	9: begin
	10: begin
	11: begin
	12: begin
	13: begin
	14: begin
	15: begin
	16: begin
	17: begin
	18: begin
	19: begin
	20: begin
	21: begin
	22: begin
	23: begin
	24: begin
	25: begin
	26: begin
	27: begin
	28: begin
	29: begin
	30: begin
	31: begin

endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example13_i-b_t-0.3.v
	case (state)
	0:	begin
	1:	begin
	2:	begin
	3:	begin
	4:	begin
	5:	begin
	6:	begin
	7:	begin
	8:	begin
	9:	begin
	10:	begin
	11:	begin
	12:	begin
	13:	begin
	14:	begin
	15:	begin
	16:	begin
	17:	begin
	18:	begin
	19:	begin
	20:	begin
	21:	begin
	22:	begin
	23:	begin
	24:	begin
	25:	begin
	26:	begin
	27:
endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example14_i-b_t-0.3.v
	assign output_data = output_data_final;
	assign output_data_valid = output_data_valid_final;
	assign output_data_valid = output_data_valid_final;
	assign output_data = output_data_final;
	assign output_data_valid = output_data_valid_final;
	assign output_data = output_data_final;
	assign output_data_valid = output_data_valid_final;
	assign output_data = output_data_final;
	assign output_data_valid = output_data_valid_final;
	assign output_data = output_data_final;
	assign output_data_valid = output_data_valid_final;
	assign output_data = output_data
endcase

========================================================
example10_i-b_t-0.5.v
	
endcase

========================================================
example11_i-b_t-0.5.v
	reg [15:0] data;
	reg [7:0] size;
	reg [15:0] in_data;
	reg [15:0] out_data;
	always @(*) begin
	assign data = in_data;
	assign size = in_data[7:0];
	assign out_data = data>>size;
	end
	always @(posedge clk) begin
	case(state)
	0: begin
	out_data <= in_data;
	end
	1: begin
	out_data <= data>>size;
	end
	
endcase

end

========================================================
example12_i-b_t-0.5.v
	case (s)
	1: begin
	2: begin
	3: begin
	4: begin
	5: begin
	6: begin
	7: begin
	8: begin
	9: begin
	10: begin
	11: begin
	12: begin
	13: begin
	14: begin
	15: begin
	16: begin
	17: begin
	18: begin
	19: begin
	20: begin
	21: begin
	22: begin
	23: begin
	24: begin
	25: begin
	26: begin
	27: begin
	28: begin
	29: begin
	30: begin
	31: begin
	32: begin

endcase

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

end

========================================================
example13_i-b_t-0.5.v
case (command)
	0:	begin
	end
	1:	begin
	end
	2:	begin
	end
	3:	begin
	end
	4:	begin
	end
	5:	begin
	end
	6:	begin
	end
	7:	begin
	end
	8:	begin
	end
	9:	begin
	end
	10:	begin
	end
	11:	begin
	end
	12:	begin
	end
	13:	begin
	end
	14:	begin
	end
	15:	begin
	end
	default:	begin
	end

endcase

========================================================
example14_i-b_t-0.5.v
	case (state)
	s0: begin
	end
	s1: begin
	end
	s2: begin
	end
	s3: begin
	end
	s4: begin
	end
	s5: begin
	end
	s6: begin
	end
	s7: begin
	end
	s8: begin
	end
	s9: begin
	end
	s10: begin
	end
	s11: begin
	end
	s12: begin
	end
	s13: begin
	end
	s14: begin
	end
	s15: begin
	end
	
endcase

========================================================
example10_i-b_t-0.7.v

endcase

========================================================
example11_i-b_t-0.7.v
	always @(*) begin
	case (In_data_type)
	
	
endcase

end

========================================================
example12_i-b_t-0.7.v
What if a word is lost forever?
Assume:
a) If the current word is a random word, next word is a random word.
b) If the current word is a specific word, next word is the same word.
c) If the current word is the last word of the specific word, then next word is a random word
d) If the current word is the last word of the specific word and it is the last word of the input file, next word is a random word.
e) If the current word is the last word of the specific word and it is the last word of the input file, then the next word is the end of the file.
Assume:
a) If the current word is the last word of the specific word, then next word is a random word.
b) If the current word is the last word of the specific word, then next word
endcase

========================================================
example13_i-b_t-0.7.v

endcase

========================================================
example14_i-b_t-0.7.v
	case (state)
	s0: 
	s1:
	s2:
	s3:
	s4:
	default:

	
endcase

========================================================
example10_i-b_t-0.9.v
// Fully populated case statement

// Note well	that for slists are 0 based arrays
end	// endcase
end	// end if
end	// end if not ready

endcase

========================================================
example11_i-b_t-0.9.v
//isActive is a "local_param", and as a result active is 
// defined so as to support this code only (exluding the one 
// based on currents of events, which is contained in the next block of
// code). The alternative would be
// this logic mechanism in pure functional models, but that would
// require an "active" signal which is often not needed, and
// the bit reduction comes from the requirement of FSM.
// iNode <= active;

endcase

========================================================
example12_i-b_t-0.9.v
//`define TA_CLK_PERIOD 200000
//`define TA_CSHOLD_PERIOD

endcase

========================================================
example13_i-b_t-0.9.v
// create if_rsp is usb rx fifo
always @(posedge clk ) begin
	if(rsp_fifo_observable & (rsp_fifo_valid ^ rsp_fifo_ready) & notemptyrsp) begin 
//throw an exception here if we would have to unnoticed read data and continue from old state resulting in unreliable output
//look at the return code section to see if we have really read the fifo data
//copy and do the assignment before throwing exception to avoid race conditions
//do the assignment as if we would have received directly from the rsp_fifo which should give same data
//understand the read returned as a triggered feature can happen leaving read - to make the next read
//gratitous here because we have to assure the read operation was actually performed on the rsp_fifo
//we need to even if the read from response is trivial as
endcase

end

end

========================================================
example14_i-b_t-0.9.v
//
/*
assign DSP (integer i)
/*
cycle increment: 0
cycle increment: 1
cycle increment: 2
cycle increment: 3 
//
integer cycle_increment_A, cycle_increment_B, cycle_increment_C;
integer cycle_increment_D;
integer cycle_increment_E;
integer cycle_increment_res;
assign cycle_increment_A = di_data[0];
assign cycle_increment_B = di_data[1];
assign cycle_increment_C = di_data[2];
assign cycle_increment_D = di_data[3];
assign cycle_increment_E = di_data[4];
assign cycle_increment_res = (cycle_increment_A * cycle_increment_B + cycle_increment_C * cycle
endcase

========================================================
example10_i-c_t-0.1.v
	
endcase

========================================================
example11_i-c_t-0.1.v
	case (1'b1)
	
endcase

========================================================
example12_i-c_t-0.1.v
	
endcase

========================================================
example13_i-c_t-0.1.v
	
endcase

========================================================
example14_i-c_t-0.1.v
	case (1'b1)
	
endcase

========================================================
example10_i-c_t-0.3.v
//
//
//
//
//
//
//
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//
//
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//
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//
//
//
//
//
//

endcase

========================================================
example11_i-c_t-0.3.v
	
endcase

========================================================
example12_i-c_t-0.3.v
	
endcase

========================================================
example13_i-c_t-0.3.v
//	if (dii_data_not_ready == 1)
//	begin
//	end


endcase

========================================================
example14_i-c_t-0.3.v
	case (1'b1)
	
endcase

========================================================
example10_i-c_t-0.5.v
	
endcase

========================================================
example11_i-c_t-0.5.v
	if (dii_data_not_ready == 0)
	begin
	end
	else
	begin
	end
	
	if (dii_data_not_ready == 0)
	begin
	end
	else
	begin
	end
	
	if (dii_data_not_ready == 0)
	begin
	end
	else
	begin
	end
	
	if (dii_data_not_ready == 0)
	begin
	end
	else
	begin
	end
	
	if (dii_data_not_ready == 0)
	begin
	end
	else
	begin
	end
	
	if (d
endcase

========================================================
example12_i-c_t-0.5.v
	case (N)
	{16'b0,1'b0}
	default
	{default}
	
endcase

========================================================
example13_i-c_t-0.5.v
 This is a hack to work around a problem that happens when the
 the input data is not ready.
 This problem happens when there is an underflow.
 In this case, the output is not ready.
 The problem is that the output is not ready and the output
 is being used by a higher level module.

 I don't know how to handle this because I have no real
 understanding of how the output is used.
 I just know that the output should not be used
 by a higher level module until the output is ready.

 I have the following workaround.
 I have to use a non-blocking read.
 I have to flag that the data is not ready until
 the data is ready.

 The problem is that the output is being used by
 a higher level module.

 I have no idea how to handle this.
endcase

========================================================
example14_i-c_t-0.5.v


endcase

========================================================
example10_i-c_t-0.7.v
	case (in_word_count)
	
endcase

========================================================
example11_i-c_t-0.7.v
// - no default case

endcase

========================================================
example12_i-c_t-0.7.v
// TODO

endcase

========================================================
example13_i-c_t-0.7.v
default:
begin	
	//code here
	end

endcase

========================================================
example14_i-c_t-0.7.v
	
endcase

========================================================
example10_i-c_t-0.9.v
// i4 > i11
assign i4 = (delay2_cnt + delay2_cnt_minus_1)*3;
assign i11 = (dii_data_cnt + delay2_cnt_minus_1)*h11;
// Inserting a rest here. Should have have an endspr with
// a delay. It could have problems. Therefore, it was decided
// to use this:
assign reset_req = resetn && cooperate && end_of_wv_s;
assign IE1 = adsr1_out;
//assign reset_req = resetn && cooperate;
//assign adsr1_out = reset_req ? 4'b0 : adsr1_in;
assign adsr1_out = reset_req ? 4'b0 : ((delay2_cnt_minus_1 == 0)? 4'b
endcase

========================================================
example11_i-c_t-0.9.v
	//probably not polluting he register
//assign rx_data = i_rx_data;

endcase

========================================================
example12_i-c_t-0.9.v


endcase

========================================================
example13_i-c_t-0.9.v
// {`named_entity},
// 
module d2v_tb #(
	parameter IDSIZE = 4,
	parameter IDSTRING = "jupee_gash.me"
)
(
	input clk,
	output busy,
	output [IDSIZE - 1 : 0] id
);

wire [43 : 0] dict_data;
wire dict_valid;

wire [43 : 0] key1_data;
wire key1_valid;

reg [43 : 0] key1_buffer[0:42];

assign key1_data = key1_buffer[0];

initial begin
	key1_buffer[0] = string_to_byte(11'h1e1);
	key1_buffer[1] = string_to_byte(11'h15e);
	key1_
endcase

end

========================================================
example14_i-c_t-0.9.v
//
//

endcase

========================================================
example10_i-d_t-0.1.v
	case (state)
	default: state = state;
	
endcase

========================================================
example11_i-d_t-0.1.v
	
endcase

========================================================
example12_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example13_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example14_i-d_t-0.1.v
	case (state)
	default: state = 0;
	
endcase

========================================================
example10_i-d_t-0.3.v
	case (state)
	default:
	
endcase

========================================================
example11_i-d_t-0.3.v
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
//
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//
//
//
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//
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//
//
//
//
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//
//
//
//
//
//
//
//

endcase

========================================================
example12_i-d_t-0.3.v
	
endcase

========================================================
example13_i-d_t-0.3.v
	
endcase

========================================================
example14_i-d_t-0.3.v
	case
	
endcase

========================================================
example10_i-d_t-0.5.v
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

endcase

========================================================
example11_i-d_t-0.5.v

endcase

========================================================
example12_i-d_t-0.5.v
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

endcase

========================================================
example13_i-d_t-0.5.v
//
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	
	

endcase

========================================================
example14_i-d_t-0.5.v
// - todo: implement this
//
//	always @(*) begin
//	case (state)
//	s0: state = s1;
//	s1: state = s2;
//	s2: state = s3;
//	s3: state = s4;
//	s4: state = s5;
//	s5: state = s6;
//	s6: state = s7;
//	s7: state = s8;
//	s8: state = s9;
//	s9: state = s10;
//	s10: state = s11;
//	s11: state = s12;
//	s12: state = s13;
//	s13: state = s14;
//	s14: state = s15;
//	default: state = s0;

endcase

========================================================
example10_i-d_t-0.7.v
state = 0;

endcase

========================================================
example11_i-d_t-0.7.v
	initial state = s0;
	always @(posedge clk) begin: state_machine
	case (state)
	s0: //initial state
	begin
	
endcase

end

end

========================================================
example12_i-d_t-0.7.v
((*data_type_conversion_table[`II2DIGIT] == 1'b1)
)begin
data_type_conversion_table[`II2DIGIT] <= 1'b0;
case(data_type_conversion_table[`II2DIGIT])
`MEMORY_MODEL:begin
//case(memory_model_to_use)
memory_model_to_use<=`MEMORY_BLOCK;
//case(memory_model_to_use)
end
`MEMORY_BLOCK:begin
case(memory_block_to_use)
memory_block_to_use<=`MEMORY_PLAIN;

endcase

end

end

========================================================
example13_i-d_t-0.7.v
//end of process

endcase

========================================================
example14_i-d_t-0.7.v
 Inserting state changes for continuous operations. 
 This will be used to evaluate if continuous operation needs to be applied.
 Inserting state changes for non continuous operations.
 This will be used to override "is_continuous" function to evaluate if continuous operation needs to be applied.
 Define new states for continous operations. 
 If continuous operation is to be applied, the states need to be redefined.
 Inserting state changes for non continuous operations.
 If is_continuous is true, then the new states need to be redefined.
 Define new state for non continuous operations and override the is_continuous function.
 Inserting state changes for non continuous operations.
 If is_continuous is true, then the new state need to be redefined.
 Define new state for non continuous operations and override the is_continuous function.
 Inserting state changes for non
endcase

========================================================
example10_i-d_t-0.9.v
while(1)
begin 
	@(posedge clk) state_next = state_next;
end

endcase

========================================================
example11_i-d_t-0.9.v
//assign state = state+1;
//assign state[0:7] = 0;
//assign state[0:7] = state;

endcase

========================================================
example12_i-d_t-0.9.v
// state = default_state
//state = state - 1
case (default_state)
0: {s0,s1} = 2'b11;
1: {s2,s3} = 2'b10;
2: {s4,s5} = 2'b11;
3: {s6,s7} = 2'b10;
4: {s8,s9} = 2'b11;
5: {s10,s11} = 2'b11;
default: {s0,s1} = 2'b11;

endcase

========================================================
example13_i-d_t-0.9.v
//default: In case of unregistered block check if state is valid, otherwise assign state 0


endcase

========================================================
example14_i-d_t-0.9.v
output reg[3:0]i_opcode = 0;
parameter[3:0] s0=0,s1=1,s2=2,s3=3,s4=4,s5=5,s6=6,s7=7,s8=8,s9=9,s10=10,s11=11,s12=12,s13=13,s14=14,s15=15;
output reg[3:0]Out_data,Out_data_i;
output reg[3:0]t_input;
output reg[4:0]ID,ID_i;
output reg[3:0]t_output;
reg[3:0]contnr=0,contnr_i=0;
reg[3:0]a,a_i,b,b_i,c,c_
endcase

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