#!/usr/bin/python
# Copyright (c) 2017 Princeton University
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from optparse import OptionParser
from fpga_lib import StorageBoard

import make_mem_map
import os, sys, re

DV_ROOT = os.environ['DV_ROOT']
MODEL_DIR = os.environ['MODEL_DIR']

def usage():
    print "Usage: map_test2bram -t <test_name> \n       or -h for help"

def getLogs(tname, log_stream=None):
    if log_stream == None:
        log_stream = sys.stderr

    print >> log_stream, "Synthesizing a test: %s" % tname
    os.chdir(MODEL_DIR)
    os.system('mkdir -p test2bram_logs')
    print >> log_stream, "Compilation started"
    # can't we build withoug -debug_all ?
    # os.system('sims -sys=manycore -x_tiles=1 -y_tiles=1 -vcs_build -debug_all > test2bram_logs/compilation.log')
    print >> log_stream, "Simulation started"
    # os.system('sims -sys=manycore -vcs_run %s > test2bram_logs/simulation.log' % tname)

    f = open('test2bram_logs/simulation.log', 'r')
    cont = f.read()
    f.close()
    match = re.search(r'(HIT GOOD TRAP)', cont)
    if match == None:
        print >> log_stream, "Test failed!"
        print >> log_stream, "Warning: this test will not pass on FPGA either!"
    else:
        print >> log_stream, "Test Passed!"


def main():
    parser = OptionParser()
    parser.add_option("-t", "--test", dest="tname", action="store", help="Name of the test (.s) to put to bram")

    (options, args) = parser.parse_args()
    if options.tname == None:
        print "Error: No test name"
        usage()
        exit(2)


    # run a test on default configuration to get a mem.image and sims.log files
    getLogs(options.tname)
    
    # generate mapping and .coe file in default output places
    make_mem_map.makeMapping(options.tname)
    
    # regenerate a block memory with new .coe file
    # is is required? Vivado could take an updated .coe file
    # os.system("vivado -mode tcl -source regen_fake_mem")
    # put .mif file into MODEL_DIR
    path = MODEL_DIR + '/fpga/xilinx_ip/test_proto.coe'




if __name__ == '__main__':
    main()
