mTower
partition_M2351.h
1 /**************************************************************************/
11 #ifndef PARTITION_M2351
12 #define PARTITION_M2351
13 
14 /*
15 //-------- <<< Use Configuration Wizard in Context Menu >>> -----------------
16 */
17 
18 
19 /*
20  SRAMNSSET
21 */
22 /*
23 // Bit 0..16
24 // <o.0..16> Secure SRAM Size <0=> 0 KB
25 // <0x2000=> 8KB
26 // <0x4000=> 16KB
27 // <0x6000=> 24KB
28 // <0x8000=> 32KB
29 // <0xa000=> 40KB
30 // <0xc000=> 48KB
31 // <0xe000=> 56KB
32 // <0x10000=> 64KB
33 // <0x12000=> 72KB
34 // <0x14000=> 80KB
35 // <0x16000=> 88KB
36 // <0x18000=> 96KB
37 */
38 #define SCU_SECURE_SRAM_SIZE 0x8000
39 #define NON_SECURE_SRAM_BASE (0x30000000 + SCU_SECURE_SRAM_SIZE)
40 
41 
42 
43 /*--------------------------------------------------------------------------------------------------------*/
44 
45 /*
46  NSBA
47 */
48 #define FMC_INIT_NSBA 1
49 /*
50 // <o>Secure Flash ROM Size <0x800-0x7FFFF:0x800>
51 */
52 
53 #define FMC_SECURE_ROM_SIZE 0x40000
54 
55 #define FMC_NON_SECURE_BASE (0x10000000 + FMC_SECURE_ROM_SIZE)
56 
57 __STATIC_INLINE void FMC_NSBA_Setup(void)
58 {
59  /* Skip NSBA Setupt according config */
60  if(FMC_INIT_NSBA == 0)
61  return;
62 
63  /* Check if NSBA value with current active NSBA */
64  if(SCU->FNSADDR != FMC_SECURE_ROM_SIZE)
65  {
66  /* Unlock Protected Register */
67  SYS_UnlockReg();
68 
69  /* Enable ISP and config update */
70  FMC->ISPCTL = FMC_ISPCTL_ISPEN_Msk | FMC_ISPCTL_CFGUEN_Msk;
71 
72  /* Config Base of NSBA */
73  FMC->ISPADDR = 0x200800;
74 
75  /* Read Non-secure base address config */
76  FMC->ISPCMD = FMC_ISPCMD_READ;
77  FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
78  while(FMC->ISPTRG);
79 
80  /* Setting NSBA when it is empty */
81  if(FMC->ISPDAT == 0xfffffffful)
82  {
83  FMC->ISPDAT = FMC_SECURE_ROM_SIZE;
84  FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
85  FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
86  while(FMC->ISPTRG);
87 
88  /* Force Chip Reset to valid new setting */
89  SYS->IPRST0 = SYS_IPRST0_CHIPRST_Msk;
90  }
91 
92  /* Fatal Error:
93  FMC NSBA setting is different to FMC_INIT_NSBA_VAL.
94  User must double confirm which one is wrong.
95 
96  If user need to change NSBA config of FMC, user must do Mess-erase by
97  ISP or ICP.
98  */
99  while(1);
100  }
101 
102 }
103 
104 
105 /*--------------------------------------------------------------------------------------------------------*/
106 
107 
108 /*
109 // <h> Peripheral Secure Attribution Configuration
110 */
111 
112 /*
113  PNSSET0
114 */
115 /*
116 // Module 0..31
117 // <o.9> USBH <0=> Secure <1=> Non-Secure
118 // <o.13> SD0 <0=> Secure <1=> Non-Secure
119 // <o.16> EBI <0=> Secure <1=> Non-Secure
120 // <o.24> PDMA1 <0=> Secure <1=> Non-Secure
121 */
122 #define SCU_INIT_PNSSET0_VAL 0x0
123 /*
124  PNSSET1
125 */
126 /*
127 // Module 0..31
128 // <o.17> CRC <0=> Secure <1=> Non-Secure
129 // <o.18> CRPT <0=> Secure <1=> Non-Secure
130 */
131 #define SCU_INIT_PNSSET1_VAL 0x0
132 /*
133  PNSSET2
134 */
135 /*
136 // Module 0..31
137 // <o.1> RTC <0=> Secure <1=> Non-Secure
138 // <o.3> EADC <0=> Secure <1=> Non-Secure
139 // <o.5> ACMP01 <0=> Secure <1=> Non-Secure
140 //
141 // <o.7> DAC <0=> Secure <1=> Non-Secure
142 // <o.8> I2S0 <0=> Secure <1=> Non-Secure
143 // <o.13> OTG <0=> Secure <1=> Non-Secure
144 // <o.17> TMR23 <0=> Secure <1=> Non-Secure
145 // <h> EPWM
146 // <o.24> EPWM0 <0=> Secure <1=> Non-Secure
147 // <o.25> EPWM1 <0=> Secure <1=> Non-Secure
148 // <o.26> BPWM0 <0=> Secure <1=> Non-Secure
149 // <o.27> BPWM1 <0=> Secure <1=> Non-Secure
150 // </h>
151 */
152 #define SCU_INIT_PNSSET2_VAL 0x0
153 /*
154  PNSSET3
155 */
156 /*
157 // Module 0..31
158 // <h> SPI
159 // <o.0> QSPI0 <0=> Secure <1=> Non-Secure
160 // <o.1> SPI0 <0=> Secure <1=> Non-Secure
161 // <o.2> SPI1 <0=> Secure <1=> Non-Secure
162 // <o.3> SPI2 <0=> Secure <1=> Non-Secure
163 // <o.4> SPI3 <0=> Secure <1=> Non-Secure
164 // </h>
165 // <h> UART
166 // <o.16> UART0 <0=> Secure <1=> Non-Secure
167 // <o.17> UART1 <0=> Secure <1=> Non-Secure
168 // <o.18> UART2 <0=> Secure <1=> Non-Secure
169 // <o.19> UART3 <0=> Secure <1=> Non-Secure
170 // <o.20> UART4 <0=> Secure <1=> Non-Secure
171 // <o.21> UART5 <0=> Secure <1=> Non-Secure
172 // </h>
173 */
174 #define SCU_INIT_PNSSET3_VAL 0x20000
175 /*
176  PNSSET4
177 */
178 /*
179 // Module 0..31
180 // <h> I2C
181 // <o.0> I2C0 <0=> Secure <1=> Non-Secure
182 // <o.1> I2C1 <0=> Secure <1=> Non-Secure
183 // <o.2> I2C2 <0=> Secure <1=> Non-Secure
184 // </h>
185 // <h> Smart Card
186 // <o.16> SC0 <0=> Secure <1=> Non-Secure
187 // <o.17> SC1 <0=> Secure <1=> Non-Secure
188 // <o.18> SC2 <0=> Secure <1=> Non-Secure
189 // </h>
190 */
191 #define SCU_INIT_PNSSET4_VAL 0x0
192 /*
193  PNSSET5
194 */
195 /*
196 // Module 0..31
197 // <o.0> CAN0 <0=> Secure <1=> Non-Secure
198 // <h> QEI
199 // <o.16> QEI0 <0=> Secure <1=> Non-Secure
200 // <o.17> QEI1 <0=> Secure <1=> Non-Secure
201 // </h>
202 // <h> ECAP
203 // <o.20> ECAP0 <0=> Secure <1=> Non-Secure
204 // <o.21> ECAP1 <0=> Secure <1=> Non-Secure
205 // </h>
206 // <o.25> TRNG <0=> Secure <1=> Non-Secure
207 */
208 #define SCU_INIT_PNSSET5_VAL 0x0
209 /*
210  PNSSET6
211 */
212 /*
213 // Module 0..31
214 // <o.0> USBD <0=> Secure <1=> Non-Secure
215 // <h> USCI
216 // <o.16> USCI0 <0=> Secure <1=> Non-Secure
217 // <o.17> USCI1 <0=> Secure <1=> Non-Secure
218 // </h>
219 */
220 #define SCU_INIT_PNSSET6_VAL 0x0
221 /*
222 // </h>
223 */
224 
225 
226 
227 /*
228 // <h> GPIO Secure Attribution Configuration
229 */
230 
231 /*
232  IONSSET
233 */
234 /*
235 // Bit 0..31
236 // <o.0> PA <0=> Secure <1=> Non-Secure
237 // <o.1> PB <0=> Secure <1=> Non-Secure
238 // <o.2> PC <0=> Secure <1=> Non-Secure
239 // <o.3> PD <0=> Secure <1=> Non-Secure
240 // <o.4> PE <0=> Secure <1=> Non-Secure
241 // <o.5> PF <0=> Secure <1=> Non-Secure
242 // <o.6> PG <0=> Secure <1=> Non-Secure
243 // <o.7> PH <0=> Secure <1=> Non-Secure
244 */
245 #define SCU_INIT_IONSSET_VAL 0x0
246 /*
247 // </h>
248 */
249 
250 
251 
257 __STATIC_INLINE void SCU_Setup(void)
258 {
259  int32_t i;
260 
261  SCU->PNSSET[0] = SCU_INIT_PNSSET0_VAL;
262  SCU->PNSSET[1] = SCU_INIT_PNSSET1_VAL;
263  SCU->PNSSET[2] = SCU_INIT_PNSSET2_VAL;
264  SCU->PNSSET[3] = SCU_INIT_PNSSET3_VAL;
265  SCU->PNSSET[4] = SCU_INIT_PNSSET4_VAL;
266  SCU->PNSSET[5] = SCU_INIT_PNSSET5_VAL;
267  SCU->PNSSET[6] = SCU_INIT_PNSSET6_VAL;
268 
269  SCU->IONSSET = SCU_INIT_IONSSET_VAL;
270 
271  /* Set Non-secure SRAM */
272  for(i = 11; i >= SCU_SECURE_SRAM_SIZE / 8192; i--)
273  {
274  SCU->SRAMNSSET |= (1U << i);
275  }
276 
277 
278 }
279 
280 
281 /* ---------------------------------------------------------------------------------------------------- */
282 
283 /*
284 // <e>Secure Attribute Unit (SAU) Control
285 */
286 #define SAU_INIT_CTRL 1
287 
288 /*
289 // <q> Enable SAU
290 // <i> To enable Secure Attribute Unit (SAU).
291 */
292 #define SAU_INIT_CTRL_ENABLE 1
293 
294 /*
295 // <o> All Memory Attribute When SAU is disabled
296 // <0=> All Memory is Secure
297 // <1=> All Memory is Non-Secure
298 // <i> To set the ALLNS bit in SAU CTRL.
299 // <i> When all Memory is Non-Secure (ALLNS is 1), IDAU can override memory map configuration.
300 */
301 #define SAU_INIT_CTRL_ALLNS 0
302 
303 /*
304 // </e>
305 */
306 
307 
308 /*
309 // <h>Enable and Set Secure/Non-Secure region
310 */
311 #define SAU_REGIONS_MAX 8 /* Max. number of SAU regions */
312 
313 /*
314 // <e>SAU Region 0
315 // <i> Setup SAU Region 0
316 */
317 #define SAU_INIT_REGION0 0
318 /*
319 // <o>Start Address <0-0xFFFFFFE0>
320 */
321 #define SAU_INIT_START0 0x0003F000 /* start address of SAU region 0 */
322 /*
323 // <o>End Address <0x1F-0xFFFFFFFF>
324 */
325 #define SAU_INIT_END0 0x0003FFFF /* end address of SAU region 0 */
326 /*
327 // <o>Region is
328 // <0=>Non-Secure
329 // <1=>Secure, Non-Secure Callable
330 */
331 #define SAU_INIT_NSC0 1
332 /*
333 // </e>
334 */
335 
336 /*
337 // <e>SAU Region 1
338 // <i> Setup SAU Region 1
339 */
340 #define SAU_INIT_REGION1 0
341 /*
342 // <o>Start Address <0-0xFFFFFFE0>
343 */
344 #define SAU_INIT_START1 0x10040000
345 /*
346 // <o>End Address <0x1F-0xFFFFFFFF>
347 */
348 #define SAU_INIT_END1 0x1007FFFF
349 /*
350 // <o>Region is
351 // <0=>Non-Secure
352 // <1=>Secure, Non-Secure Callable
353 */
354 #define SAU_INIT_NSC1 0
355 /*
356 // </e>
357 */
358 
359 /*
360 // <e>SAU Region 2
361 // <i> Setup SAU Region 2
362 */
363 #define SAU_INIT_REGION2 0
364 /*
365 // <o>Start Address <0-0xFFFFFFE0>
366 */
367 #define SAU_INIT_START2 0x2000F000
368 /*
369 // <o>End Address <0x1F-0xFFFFFFFF>
370 */
371 #define SAU_INIT_END2 0x2000FFFF
372 /*
373 // <o>Region is
374 // <0=>Non-Secure
375 // <1=>Secure, Non-Secure Callable
376 */
377 #define SAU_INIT_NSC2 1
378 /*
379 // </e>
380 */
381 
382 /*
383 // <e>SAU Region 3
384 // <i> Setup SAU Region 3
385 */
386 #define SAU_INIT_REGION3 1
387 /*
388 // <o>Start Address <0-0xFFFFFFE0>
389 */
390 #define SAU_INIT_START3 0x3f000
391 /*
392 // <o>End Address <0x1F-0xFFFFFFFF>
393 */
394 #define SAU_INIT_END3 0x3f7ff
395 /*
396 // <o>Region is
397 // <0=>Non-Secure
398 // <1=>Secure, Non-Secure Callable
399 */
400 #define SAU_INIT_NSC3 1
401 /*
402 // </e>
403 */
404 
405 /*
406  <e>SAU Region 4
407  <i> Setup SAU Region 4
408 */
409 #define SAU_INIT_REGION4 1
410 /*
411  <o>Start Address <0-0xFFFFFFE0>
412 */
413 #define SAU_INIT_START4 FMC_NON_SECURE_BASE /* start address of SAU region 4 */
414 
415 /*
416  <o>End Address <0x1F-0xFFFFFFFF>
417 */
418 #define SAU_INIT_END4 0x1007FFFF /* end address of SAU region 4 */
419 
420 /*
421  <o>Region is
422  <0=>Non-Secure
423  <1=>Secure, Non-Secure Callable
424 */
425 #define SAU_INIT_NSC4 0
426 /*
427  </e>
428 */
429 
430 /*
431  <e>SAU Region 5
432  <i> Setup SAU Region 5
433 */
434 #define SAU_INIT_REGION5 1
435 
436 /*
437  <o>Start Address <0-0xFFFFFFE0>
438 */
439 #define SAU_INIT_START5 0x00807E00
440 
441 /*
442  <o>End Address <0x1F-0xFFFFFFFF>
443 */
444 #define SAU_INIT_END5 0x00807FFF
445 
446 /*
447  <o>Region is
448  <0=>Non-Secure
449  <1=>Secure, Non-Secure Callable
450 */
451 #define SAU_INIT_NSC5 1
452 /*
453  </e>
454 */
455 
456 /*
457  <e>SAU Region 6
458  <i> Setup SAU Region 6
459 */
460 #define SAU_INIT_REGION6 1
461 
462 /*
463  <o>Start Address <0-0xFFFFFFE0>
464 */
465 #define SAU_INIT_START6 NON_SECURE_SRAM_BASE
466 
467 /*
468  <o>End Address <0x1F-0xFFFFFFFF>
469 */
470 #define SAU_INIT_END6 0x30017FFF
471 
472 /*
473  <o>Region is
474  <0=>Non-Secure
475  <1=>Secure, Non-Secure Callable
476 */
477 #define SAU_INIT_NSC6 0
478 /*
479  </e>
480 */
481 
482 /*
483  <e>SAU Region 7
484  <i> Setup SAU Region 7
485 */
486 #define SAU_INIT_REGION7 1
487 
488 /*
489  <o>Start Address <0-0xFFFFFFE0>
490 */
491 #define SAU_INIT_START7 0x50000000
492 
493 /*
494  <o>End Address <0x1F-0xFFFFFFFF>
495 */
496 #define SAU_INIT_END7 0x5FFFFFFF
497 
498 /*
499  <o>Region is
500  <0=>Non-Secure
501  <1=>Secure, Non-Secure Callable
502 */
503 #define SAU_INIT_NSC7 0
504 /*
505  </e>
506 */
507 
508 /*
509 // </h>
510 */
511 
512 /*
513 // <e>Setup behavior of Sleep and Exception Handling
514 */
515 #define SCB_CSR_AIRCR_INIT 1
516 
517 /*
518 // <o> Deep Sleep can be enabled by
519 // <0=>Secure and Non-Secure state
520 // <1=>Secure state only
521 // <i> Value for SCB->CSR register bit DEEPSLEEPS
522 */
523 #define SCB_CSR_DEEPSLEEPS_VAL 0
524 
525 /*
526 // <o>System reset request accessible from
527 // <0=> Secure and Non-Secure state
528 // <1=> Secure state only
529 // <i> Value for SCB->AIRCR register bit SYSRESETREQS
530 */
531 #define SCB_AIRCR_SYSRESETREQS_VAL 0
532 
533 /*
534 // <o>Priority of Non-Secure exceptions is
535 // <0=> Not altered
536 // <1=> Lowered to 0x80-0xFF
537 // <i> Value for SCB->AIRCR register bit PRIS
538 */
539 #define SCB_AIRCR_PRIS_VAL 0
540 
541 /* Assign HardFault to be always secure for safe */
542 #define SCB_AIRCR_BFHFNMINS_VAL 0
543 
544 /*
545 // </e>
546 */
547 
548 
549 /*
550 // <h>Assign Interrupt to Secure or Non-secure Vector
551 */
552 
553 
554 /*
555  Initialize ITNS 0 (Interrupts 0..31)
556 */
557 #define NVIC_INIT_ITNS0 1
558 /*
559 // BODOUT Always secure
560 // IRC Always secure
561 // PWRWU_ Always secure
562 // SRAM_PERR Always secure
563 // CLKFAIL Always secure
564 
565 // <o.6> RTC <0=> Secure <1=> Non-Secure
566 // <o.7> TAMPER <0=> Secure <1=> Non-Secure
567 // WDT Always secure
568 // WWDT Always secure
569 // <h> EINT
570 // <o.10> EINT0 <0=> Secure <1=> Non-Secure
571 // <o.11> EINT1 <0=> Secure <1=> Non-Secure
572 // <o.12> EINT2 <0=> Secure <1=> Non-Secure
573 // <o.13> EINT3 <0=> Secure <1=> Non-Secure
574 // <o.14> EINT4 <0=> Secure <1=> Non-Secure
575 // <o.15> EINT5 <0=> Secure <1=> Non-Secure
576 // </h>
577 // <h> GPIO
578 // <o.16> GPA <0=> Secure <1=> Non-Secure
579 // <o.17> GPB <0=> Secure <1=> Non-Secure
580 // <o.18> GPC <0=> Secure <1=> Non-Secure
581 // <o.19> GPD <0=> Secure <1=> Non-Secure
582 // <o.20> GPE <0=> Secure <1=> Non-Secure
583 // <o.21> GPF <0=> Secure <1=> Non-Secure
584 // </h>
585 // <o.22> QSPI0 <0=> Secure <1=> Non-Secure
586 // <o.23> SPI0 <0=> Secure <1=> Non-Secure
587 // <h> EPWM
588 // <o.24> BRAKE0 <0=> Secure <1=> Non-Secure
589 // <o.25> EPWM0_P0 <0=> Secure <1=> Non-Secure
590 // <o.26> EPWM0_P1 <0=> Secure <1=> Non-Secure
591 // <o.27> EPWM0_P2 <0=> Secure <1=> Non-Secure
592 // <o.28> BRAKE1 <0=> Secure <1=> Non-Secure
593 // <o.29> EPWM1_P0 <0=> Secure <1=> Non-Secure
594 // <o.30> EPWM1_P1 <0=> Secure <1=> Non-Secure
595 // <o.31> EPWM1_P2 <0=> Secure <1=> Non-Secure
596 // </h>
597 //
598 */
599 #define NVIC_INIT_ITNS0_VAL 0x0
600 
601 /*
602  Initialize ITNS 1 (Interrupts 0..31)
603 */
604 #define NVIC_INIT_ITNS1 1
605 /*
606 // <h> TIMER
607 // TMR0 Always secure
608 // TMR1 Always secure
609 // <o.2> TMR2 <0=> Secure <1=> Non-Secure
610 // <o.3> TMR3 <0=> Secure <1=> Non-Secure
611 // </h>
612 // <o.4> UART0 <0=> Secure <1=> Non-Secure
613 // <o.5> UART1 <0=> Secure <1=> Non-Secure
614 // <o.6> I2C0 <0=> Secure <1=> Non-Secure
615 // <o.7> I2C1 <0=> Secure <1=> Non-Secure
616 // PDMA0 is secure only
617 // <o.9> DAC <0=> Secure <1=> Non-Secure
618 // <o.10> EADC0 <0=> Secure <1=> Non-Secure
619 // <o.11> EADC1 <0=> Secure <1=> Non-Secure
620 // <o.12> ACMP01 <0=> Secure <1=> Non-Secure
621 
622 // <o.14> EADC2 <0=> Secure <1=> Non-Secure
623 // <o.15> EADC3 <0=> Secure <1=> Non-Secure
624 // <o.16> UART2 <0=> Secure <1=> Non-Secure
625 // <o.17> UART3 <0=> Secure <1=> Non-Secure
626 
627 // <o.19> SPI1 <0=> Secure <1=> Non-Secure
628 // <o.20> SPI2 <0=> Secure <1=> Non-Secure
629 // <o.21> USBD <0=> Secure <1=> Non-Secure
630 // <o.22> USBH <0=> Secure <1=> Non-Secure
631 // <o.23> USBOTG <0=> Secure <1=> Non-Secure
632 // <o.24> CAN0 <0=> Secure <1=> Non-Secure
633 
634 // <h> Smart Card
635 // <o.26> SC0 <0=> Secure <1=> Non-Secure
636 // <o.27> SC1 <0=> Secure <1=> Non-Secure
637 // <o.28> SC2 <0=> Secure <1=> Non-Secure
638 // </h>
639 
640 // <o.30> SPI3 <0=> Secure <1=> Non-Secure
641 
642 //
643 */
644 #define NVIC_INIT_ITNS1_VAL 0x20
645 
646 /*
647  Initialize ITNS 2 (Interrupts 0..31)
648 */
649 #define NVIC_INIT_ITNS2 1
650 /*
651 // <o.0> SDH0 <0=> Secure <1=> Non-Secure
652 
653 
654 
655 // <o.4> I2S0 <0=> Secure <1=> Non-Secure
656 
657 //
658 // <o.7> CRYPTO <0=> Secure <1=> Non-Secure
659 // <o.8> GPG <0=> Secure <1=> Non-Secure
660 // <o.9> EINT6 <0=> Secure <1=> Non-Secure
661 // <o.10> UART4 <0=> Secure <1=> Non-Secure
662 // <o.11> UART5 <0=> Secure <1=> Non-Secure
663 // <o.12> USCI0 <0=> Secure <1=> Non-Secure
664 // <o.13> USCI1 <0=> Secure <1=> Non-Secure
665 // <o.14> BPWM0 <0=> Secure <1=> Non-Secure
666 // <o.15> BPWM1 <0=> Secure <1=> Non-Secure
667 
668 
669 // <o.18> I2C2 <0=> Secure <1=> Non-Secure
670 
671 // <o.20> QEI0 <0=> Secure <1=> Non-Secure
672 // <o.21> QEI1 <0=> Secure <1=> Non-Secure
673 // <o.22> ECAP0 <0=> Secure <1=> Non-Secure
674 // <o.23> ECAP1 <0=> Secure <1=> Non-Secure
675 // <o.24> GPH <0=> Secure <1=> Non-Secure
676 // <o.25> EINT7 <0=> Secure <1=> Non-Secure
677 
678 
679 // <o.28> USBH <0=> Secure <1=> Non-Secure
680 
681 
682 
683 //
684 */
685 #define NVIC_INIT_ITNS2_VAL 0x0
686 
687 
688 /*
689  Initialize ITNS 3 (Interrupts 0..31)
690 */
691 #define NVIC_INIT_ITNS3 1
692 /*
693 // <o.2> PDMA1 <0=> Secure <1=> Non-Secure
694 // SCU Always secure
695 //
696 // <o.5> TRNG <0=> Secure <1=> Non-Secure
697 */
698 #define NVIC_INIT_ITNS3_VAL 0x0
699 
700 
701 
702 /*
703 // </h>
704 */
705 
706 
707 
708 /*
709  max 128 SAU regions.
710  SAU regions are defined in partition.h
711  */
712 
713 #define SAU_INIT_REGION(n) \
714  SAU->RNR = (n & SAU_RNR_REGION_Msk); \
715  SAU->RBAR = (SAU_INIT_START##n & SAU_RBAR_BADDR_Msk); \
716  SAU->RLAR = (SAU_INIT_END##n & SAU_RLAR_LADDR_Msk) | \
717  ((SAU_INIT_NSC##n << SAU_RLAR_NSC_Pos) & SAU_RLAR_NSC_Msk) | 1U
718 
724 __STATIC_INLINE void TZ_SAU_Setup(void)
725 {
726 
727 #if defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U)
728 
729 #if defined (SAU_INIT_REGION0) && (SAU_INIT_REGION0 == 1U)
730  SAU_INIT_REGION(0);
731 #endif
732 
733 #if defined (SAU_INIT_REGION1) && (SAU_INIT_REGION1 == 1U)
734  SAU_INIT_REGION(1);
735 #endif
736 
737 #if defined (SAU_INIT_REGION2) && (SAU_INIT_REGION2 == 1U)
738  SAU_INIT_REGION(2);
739 #endif
740 
741 #if defined (SAU_INIT_REGION3) && (SAU_INIT_REGION3 == 1U)
742  SAU_INIT_REGION(3);
743 #endif
744 
745 #if defined (SAU_INIT_REGION4) && (SAU_INIT_REGION4 == 1U)
746  SAU_INIT_REGION(4);
747 #endif
748 
749 #if defined (SAU_INIT_REGION5) && (SAU_INIT_REGION5 == 1U)
750  SAU_INIT_REGION(5);
751 #endif
752 
753 #if defined (SAU_INIT_REGION6) && (SAU_INIT_REGION6 == 1U)
754  SAU_INIT_REGION(6);
755 #endif
756 
757 #if defined (SAU_INIT_REGION7) && (SAU_INIT_REGION7 == 1U)
758  SAU_INIT_REGION(7);
759 #endif
760 
761  /* repeat this for all possible SAU regions */
762 
763 
764 #if defined (SAU_INIT_CTRL) && (SAU_INIT_CTRL == 1U)
765  SAU->CTRL = ((SAU_INIT_CTRL_ENABLE << SAU_CTRL_ENABLE_Pos) & SAU_CTRL_ENABLE_Msk) |
766  ((SAU_INIT_CTRL_ALLNS << SAU_CTRL_ALLNS_Pos) & SAU_CTRL_ALLNS_Msk) ;
767 #endif
768 
769 #endif /* defined (__SAU_PRESENT) && (__SAU_PRESENT == 1U) */
770 
771 #if defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U)
772  SCB->SCR = (SCB->SCR & ~(SCB_SCR_SLEEPDEEPS_Msk)) |
773  ((SCB_CSR_DEEPSLEEPS_VAL << SCB_SCR_SLEEPDEEPS_Pos) & SCB_SCR_SLEEPDEEPS_Msk);
774 
775 // SCB->AIRCR = (SCB->AIRCR & ~(SCB_AIRCR_SYSRESETREQS_Msk | SCB_AIRCR_BFHFNMINS_Msk | SCB_AIRCR_PRIS_Msk)) |
776 // ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
777 // ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
778 // ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
779 
780  SCB->AIRCR = (0x05FA << 16) |
781  ((SCB_AIRCR_SYSRESETREQS_VAL << SCB_AIRCR_SYSRESETREQS_Pos) & SCB_AIRCR_SYSRESETREQS_Msk) |
782  ((SCB_AIRCR_BFHFNMINS_VAL << SCB_AIRCR_BFHFNMINS_Pos) & SCB_AIRCR_BFHFNMINS_Msk) |
783  ((SCB_AIRCR_PRIS_VAL << SCB_AIRCR_PRIS_Pos) & SCB_AIRCR_PRIS_Msk);
784 
785 
786 
787 #endif /* defined (SCB_CSR_AIRCR_INIT) && (SCB_CSR_AIRCR_INIT == 1U) */
788 
789 #if defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U)
790  SCB->ICSR = (SCB->ICSR & ~(SCB_ICSR_STTNS_Msk)) |
791  ((SCB_ICSR_STTNS_VAL << SCB_ICSR_STTNS_Pos) & SCB_ICSR_STTNS_Msk);
792 #endif /* defined (SCB_ICSR_INIT) && (SCB_ICSR_INIT == 1U) */
793 
794 #if defined (NVIC_INIT_ITNS0) && (NVIC_INIT_ITNS0 == 1U)
795  NVIC->ITNS[0] = NVIC_INIT_ITNS0_VAL;
796 #endif
797 
798 #if defined (NVIC_INIT_ITNS1) && (NVIC_INIT_ITNS1 == 1U)
799  NVIC->ITNS[1] = NVIC_INIT_ITNS1_VAL;
800 #endif
801 
802 #if defined (NVIC_INIT_ITNS2) && (NVIC_INIT_ITNS2 == 1U)
803  NVIC->ITNS[2] = NVIC_INIT_ITNS2_VAL;
804 #endif
805 
806 #if defined (NVIC_INIT_ITNS3) && (NVIC_INIT_ITNS3 == 1U)
807  NVIC->ITNS[3] = NVIC_INIT_ITNS3_VAL;
808 #endif
809 
810 
811  /* repeat this for all possible ITNS elements */
812 
813 }
814 
815 
816 #endif /* PARTITION_M2351 */
817 
Generated by   doxygen 1.8.13