Binary files ../RVfpga/src/rvfpganexys.bit and src/rvfpganexys.bit differ
diff -ruN ../RVfpga/src/rvfpgasim.v src/rvfpgasim.v
--- ../RVfpga/src/rvfpgasim.v	2022-02-02 04:00:18.000000000 +0100
+++ src/rvfpgasim.v	2022-11-26 07:00:04.903866210 +0100
@@ -25,7 +25,17 @@
 module rvfpgasim
   #(parameter bootrom_file  = "")
 `ifdef VERILATOR
-  (input wire clk,
+  (
+
+  `ifdef ViDBo
+   input wire [15:0] i_sw,
+   output reg [15:0] o_led,
+   input wire [4:0]  i_pb,
+   output reg [7:0]   AN,
+   output reg         CA, CB, CC, CD, CE, CF, CG,
+   output wire [7:0]  Enables_Reg,
+   output wire [31:0] Digits_Reg,
+   input wire clk,
    input wire  rst,
    input wire  i_jtag_tck,
    input wire  i_jtag_tms,
@@ -33,7 +43,146 @@
    input wire  i_jtag_trst_n,
    output wire o_jtag_tdo,
    output wire o_uart_tx,
+   output wire        tf_push,
+   output wire [7:0]  wb_m2s_uart_dat_output,
+
+   output logic           ic_act_miss_f2,
+   output logic           ic_act_hit_f2,
+
+   output logic [31:0]  ib3_in,
+   output logic [31:0]  ib2_in,
+   output logic [31:0]  ib1_in,
+   output logic [31:0]  ib0_in,
+
+   output logic ic_hit_f2,
+
+   output logic        exu_i0_flush_upper_e1,
+   output logic [31:1] exu_i0_flush_path_e1_ext,
+   output logic        exu_i1_flush_upper_e1,
+   output logic [31:1] exu_i1_flush_path_e1_ext,
+
+   output logic [31:0] ifc_fetch_addr_f1_ext,
+
+   output logic               addr_external_dc1,
+   output logic               addr_external_dc2,
+   output logic               addr_external_dc3,
+
+   output logic        lsu_dccm_rden_dc1,
+   output logic        lsu_dccm_rden_dc2,
+   output logic        lsu_dccm_rden_dc3,
+
+   output logic        [31:0]  a_e1,
+   output logic        [31:0]  b_e1,
+   output logic        [63:0]  prod_e2_red,
+   logic [31:0] exu_mul_result_e3,
+
+   output logic [31:0]  mul_rs1_d,
+   output logic [31:0]  mul_rs2_d,
+
+   output logic [31:0] exu_lsu_rs1_d,
+
+   output logic [31:0] i0_result_e2,
+   output logic [31:0] i1_result_e2,
+
+   output logic [31:0] i0_result_e3_final,
+   output logic [31:0] i1_result_e3_final,
+
+   output logic [5:0]   i0_control,
+   output logic [5:0]   i1_control,
+   output logic [5:0]   lsu_control,
+   output logic [5:0]   mul_control,
+   output logic [5:0]   i0_branch,
+   output logic [5:0]   i1_branch,
+
+   output logic         lsu_load_stall_any,       // This is for blocking stores
+   output logic        lsu_busreq_dc2,
+   output logic [31:0] bus_read_data_dc3,
+   output wire        lsu_arvalid,
+   output wire        lsu_rvalid,
+
+   output logic [31:0]  dccm_data_lo_dc2,
+
+   output logic         dccm_rden,
+
+   output logic [31:0]        rs1_dc1,
+   output logic [11:0]        offset_dc1,
+
+   output logic [31:0] i0_result_e4_final,
+   output logic [31:0] i1_result_e4_final,
+
+   output logic [31:0] dccm_data_lo_dc3,
+
+   output logic [31:0]        full_addr_dc1,
+
+   output logic [11:0] dec_lsu_offset_d,
+
+   output logic [31:0]  dec_i0_pc_d_ext,
+
+   output logic [4:0]  dec_i0_waddr_wb,
+   output logic        dec_i0_wen_wb,
+   output logic [31:0] dec_i0_wdata_wb,
+
+   output logic [4:0]  dec_i1_waddr_wb,
+   output logic        dec_i1_wen_wb,
+   output logic [31:0] dec_i1_wdata_wb,
+
+   output logic [31:0] i0_rs1_d,
+   output logic [31:0] i0_rs2_d,
+   output logic [31:0] i1_rs1_d,
+   output logic [31:0] i1_rs2_d,
+
+   output logic [31:0] exu_i0_result_e1,
+   output logic [31:0] exu_i1_result_e1,
+
+   output logic [31:0] i0_rs1_bypass_data_d,
+   output logic [31:0] i0_rs2_bypass_data_d,
+   output logic [31:0] i1_rs1_bypass_data_d,
+   output logic [31:0] i1_rs2_bypass_data_d,
+
+   output logic [31:0] aff0,
+   output logic [31:0] aff1,
+   output logic [31:0] bff0,
+   output logic [31:0] bff1,
+
+    output logic  [31:0] gpr_i0_rs1_d,               // gpr rs1 data
+    output logic  [31:0] gpr_i0_rs2_d,               // gpr rs2 data
+    output logic  [31:0] gpr_i1_rs1_d,
+    output logic  [31:0] gpr_i1_rs2_d,
+
+
+   output logic [31:0]           ifu_i0_instr_export,
+   output logic [31:0]           ifu_i1_instr_export,
+
+   output logic [31:0]        i0_inst_d,
+   output logic [31:0]        i0_inst_e1,
+   output logic [31:0]        i0_inst_e2,
+   output logic [31:0]        i0_inst_e3,
+   output logic [31:0]        i0_inst_e4,
+   output logic [31:0]        i0_inst_wb,
+
+   output logic [31:0]        i1_inst_d,
+   output logic [31:0]        i1_inst_e1,
+   output logic [31:0]        i1_inst_e2,
+   output logic [31:0]        i1_inst_e3,
+   output logic [31:0]        i1_inst_e4,
+   output logic [31:0]        i1_inst_wb,
+
+
    output wire o_gpio
+
+
+  `else
+   input wire clk,
+   input wire  rst,
+   input wire  i_jtag_tck,
+   input wire  i_jtag_tms,
+   input wire  i_jtag_tdi,
+   input wire  i_jtag_trst_n,
+   output wire o_jtag_tdo,
+   output wire o_uart_tx,
+   output wire o_gpio
+  `endif
+
    )
 `endif
   ;
@@ -57,6 +206,21 @@
 
 `endif
 
+
+  `ifdef ViDBo
+
+   wire [15:0]  gpio_in;
+   wire [15:0]  gpio_out;
+
+   assign gpio_in = i_sw;
+
+   always @(posedge clk) begin
+      o_led[15:0] <= gpio_out[15:0];
+   end
+
+  `endif
+
+
    reg [1023:0] ram_init_file;
    initial begin
       if (|$test$plusargs("jtag_vpi_enable"))
@@ -77,8 +241,10 @@
 	swervolf.bootrom.ram.mem[0] = 64'h0000000000000067;
    end
 
+  `ifndef ViDBo
    wire [15:0]  i_sw;
    assign  i_sw = 16'hFE34;
+  `endif
 
    wire [5:0]  ram_awid;
    wire [31:0] ram_awaddr;
@@ -190,7 +356,25 @@
    swervolf_core
      #(.bootrom_file (bootrom_file))
    swervolf
-     (.clk  (clk),
+     (
+
+      .i0_inst_d     (i0_inst_d),
+      .i0_inst_e1     (i0_inst_e1),
+      .i0_inst_e2     (i0_inst_e2),
+      .i0_inst_e3     (i0_inst_e3),
+      .i0_inst_e4     (i0_inst_e4),
+      .i0_inst_wb     (i0_inst_wb),
+
+      .i1_inst_d     (i1_inst_d),
+      .i1_inst_e1     (i1_inst_e1),
+      .i1_inst_e2     (i1_inst_e2),
+      .i1_inst_e3     (i1_inst_e3),
+      .i1_inst_e4     (i1_inst_e4),
+      .i1_inst_wb     (i1_inst_wb),
+
+
+
+      .clk  (clk),
       .rstn (!rst),
       .dmi_reg_rdata       (dmi_reg_rdata),
       .dmi_reg_wdata       (dmi_reg_wdata),
@@ -204,6 +388,118 @@
       .i_flash_miso        (1'b0),
       .i_uart_rx           (1'b1),
       .o_uart_tx           (o_uart_tx),
+
+      .ic_act_miss_f2      (ic_act_miss_f2),
+      .ic_act_hit_f2      (ic_act_hit_f2),
+
+      .ib3_in      (ib3_in),
+      .ib2_in      (ib2_in),
+      .ib1_in      (ib1_in),
+      .ib0_in      (ib0_in),
+
+      .ic_hit_f2      (ic_hit_f2),
+
+      .exu_i0_flush_upper_e1      (exu_i0_flush_upper_e1),
+      .exu_i0_flush_path_e1_ext      (exu_i0_flush_path_e1_ext),
+      .exu_i1_flush_upper_e1      (exu_i1_flush_upper_e1),
+      .exu_i1_flush_path_e1_ext      (exu_i1_flush_path_e1_ext),
+
+      .ifc_fetch_addr_f1_ext      (ifc_fetch_addr_f1_ext),
+
+      .addr_external_dc1      (addr_external_dc1),
+      .addr_external_dc2      (addr_external_dc2),
+      .addr_external_dc3      (addr_external_dc3),
+
+      .lsu_dccm_rden_dc1      (lsu_dccm_rden_dc1),
+      .lsu_dccm_rden_dc2      (lsu_dccm_rden_dc2),
+      .lsu_dccm_rden_dc3      (lsu_dccm_rden_dc3),
+
+      .a_e1      (a_e1),
+      .b_e1      (b_e1),
+      .prod_e2_red      (prod_e2_red),
+      .exu_mul_result_e3      (exu_mul_result_e3),
+
+      .mul_rs1_d      (mul_rs1_d),
+      .mul_rs2_d      (mul_rs2_d),
+
+      .exu_lsu_rs1_d      (exu_lsu_rs1_d),
+
+      .i0_result_e2      (i0_result_e2),
+      .i1_result_e2      (i1_result_e2),
+
+      .i0_result_e3_final      (i0_result_e3_final),
+      .i1_result_e3_final      (i1_result_e3_final),
+
+      .i0_control      (i0_control),
+      .i1_control      (i1_control),
+      .lsu_control      (lsu_control),
+      .mul_control      (mul_control),
+      .i0_branch      (i0_branch),
+      .i1_branch      (i1_branch),
+
+      .lsu_load_stall_any      (lsu_load_stall_any),
+      .lsu_busreq_dc2      (lsu_busreq_dc2),
+      .bus_read_data_dc3      (bus_read_data_dc3),
+      .lsu_arvalid      (lsu_arvalid),
+      .lsu_rvalid      (lsu_rvalid),
+
+      .dccm_data_lo_dc2      (dccm_data_lo_dc2),
+
+      .dccm_rden      (dccm_rden),
+
+      .rs1_dc1      (rs1_dc1),
+      .offset_dc1      (offset_dc1),
+
+      .i0_result_e4_final      (i0_result_e4_final),
+      .i1_result_e4_final      (i1_result_e4_final),
+
+      .dccm_data_lo_dc3      (dccm_data_lo_dc3),
+
+      .full_addr_dc1      (full_addr_dc1),
+
+      .dec_lsu_offset_d      (dec_lsu_offset_d),
+
+      .dec_i0_pc_d_ext      (dec_i0_pc_d_ext),
+
+      .dec_i0_waddr_wb      (dec_i0_waddr_wb),
+      .dec_i0_wen_wb      (dec_i0_wen_wb),
+      .dec_i0_wdata_wb      (dec_i0_wdata_wb),
+
+      .dec_i1_waddr_wb      (dec_i1_waddr_wb),
+      .dec_i1_wen_wb      (dec_i1_wen_wb),
+      .dec_i1_wdata_wb      (dec_i1_wdata_wb),
+
+      .i0_rs1_d      (i0_rs1_d),
+      .i0_rs2_d      (i0_rs2_d),
+      .i1_rs1_d      (i1_rs1_d),
+      .i1_rs2_d      (i1_rs2_d),
+
+      .exu_i0_result_e1      (exu_i0_result_e1),
+      .exu_i1_result_e1      (exu_i1_result_e1),
+
+      .i0_rs1_bypass_data_d      (i0_rs1_bypass_data_d),
+      .i0_rs2_bypass_data_d      (i0_rs2_bypass_data_d),
+      .i1_rs1_bypass_data_d      (i1_rs1_bypass_data_d),
+      .i1_rs2_bypass_data_d      (i1_rs2_bypass_data_d),
+
+      .aff0      (aff0),
+      .aff1      (aff1),
+      .bff0      (bff0),
+      .bff1      (bff1),
+
+      .gpr_i0_rs1_d      (gpr_i0_rs1_d),
+      .gpr_i0_rs2_d      (gpr_i0_rs2_d),
+      .gpr_i1_rs1_d      (gpr_i1_rs1_d),
+      .gpr_i1_rs2_d      (gpr_i1_rs2_d),
+
+      .ifu_i0_instr_export (ifu_i0_instr_export),
+      .ifu_i1_instr_export (ifu_i1_instr_export),
+
+  `ifdef ViDBo
+      .tf_push                  (tf_push),
+      .wb_m2s_uart_dat_output   (wb_m2s_uart_dat_output),
+  `endif
+
       .o_ram_awid          (ram_awid),
       .o_ram_awaddr        (ram_awaddr),
       .o_ram_awlen         (ram_awlen),
@@ -245,6 +541,15 @@
       .o_ram_rready        (ram_rready),
       .i_ram_init_done     (1'b1),
       .i_ram_init_error    (1'b0),
-      .io_data             ({i_sw,16'bz}));
+
+  `ifdef ViDBo
+      .i_data        ({gpio_in[15:0],16'b0}),
+      .o_data        ({gpio_out[15:0]}),
+      .AN (AN),
+      .Digits_Bits ({CA,CB,CC,CD,CE,CF,CG})
+  `else
+      .io_data             ({i_sw,16'bz})
+  `endif
+      );
 
 endmodule
diff -ruN ../RVfpga/src/SweRVolfSoC/Interconnect/AxiInterconnect/axi_intercon.vh src/SweRVolfSoC/Interconnect/AxiInterconnect/axi_intercon.vh
--- ../RVfpga/src/SweRVolfSoC/Interconnect/AxiInterconnect/axi_intercon.vh	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/Interconnect/AxiInterconnect/axi_intercon.vh	2022-11-26 07:00:04.907866328 +0100
@@ -40,7 +40,6 @@
 wire  [2:0] lsu_arprot;
 wire  [3:0] lsu_arregion;
 wire  [3:0] lsu_arqos;
-wire        lsu_arvalid;
 wire        lsu_arready;
 wire [63:0] lsu_wdata;
 wire  [7:0] lsu_wstrb;
@@ -55,7 +54,6 @@
 wire [63:0] lsu_rdata;
 wire  [1:0] lsu_rresp;
 wire        lsu_rlast;
-wire        lsu_rvalid;
 wire        lsu_rready;
 wire  [0:0] sb_awid;
 wire [31:0] sb_awaddr;
diff -ruN ../RVfpga/src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v
--- ../RVfpga/src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v	2022-02-02 04:00:32.000000000 +0100
+++ src/SweRVolfSoC/Peripherals/SystemController/swervolf_syscon.v	2022-11-26 07:00:04.911866446 +0100
@@ -46,7 +46,8 @@
    output reg [31:0] o_wb_rdt,
    output reg 	     o_wb_ack,
    output wire [ 7          :0] AN,
-   output wire [ 6          :0] Digits_Bits);
+   output wire [ 6          :0] Digits_Bits
+   );
 
    reg [63:0] 	      mtime;
    reg [63:0] 	      mtimecmp;
@@ -275,8 +276,8 @@
 
 	// Eight-Digit 7 Segment Displays
 
-	  reg  [ 7:0]  Enables_Reg;
-	  reg  [31:0]  Digits_Reg;
+    reg  [ 7:0]  Enables_Reg;
+    reg  [31:0]  Digits_Reg;
 
 	  SevSegDisplays_Controller SegDispl_Ctr(
 	    .clk               (i_clk),    
@@ -291,8 +292,12 @@
 
 
 
-
+`ifdef ViDBo
+parameter COUNT_MAX = 3;
+`else
 parameter COUNT_MAX = 20;
+`endif
+
 
 module SevSegDisplays_Controller(
                      input wire           clk,
diff -ruN ../RVfpga/src/SweRVolfSoC/Peripherals/uart/uart_regs.v src/SweRVolfSoC/Peripherals/uart/uart_regs.v
--- ../RVfpga/src/SweRVolfSoC/Peripherals/uart/uart_regs.v	2022-02-02 04:00:30.000000000 +0100
+++ src/SweRVolfSoC/Peripherals/uart/uart_regs.v	2022-11-26 07:00:04.911866446 +0100
@@ -226,7 +226,13 @@
 
 module uart_regs
 #(parameter SIM = 0)
- (clk,
+ (
+
+ 	  `ifdef ViDBo
+	tf_push, 
+	  `endif
+
+	clk,
 	wb_rst_i, wb_addr_i, wb_dat_i, wb_dat_o, wb_we_i, wb_re_i, 
 
 // additional signals
@@ -240,6 +246,10 @@
 
 	);
 
+  `ifdef ViDBo
+output 									tf_push;
+  `endif
+
 input 									clk;
 input 									wb_rst_i;
 input [2:0] 		wb_addr_i;
diff -ruN ../RVfpga/src/SweRVolfSoC/Peripherals/uart/uart_top.v src/SweRVolfSoC/Peripherals/uart/uart_top.v
--- ../RVfpga/src/SweRVolfSoC/Peripherals/uart/uart_top.v	2022-02-02 04:00:32.000000000 +0100
+++ src/SweRVolfSoC/Peripherals/uart/uart_top.v	2022-11-26 07:00:04.911866446 +0100
@@ -135,6 +135,11 @@
 `include "uart_defines.v"
 
 module uart_top	(
+
+  `ifdef ViDBo
+	tf_push,
+  `endif
+
 	wb_clk_i, 
 	
 	// Wishbone signals
@@ -154,6 +159,10 @@
 parameter SIM = 0;
 parameter debug = 0;
 
+  `ifdef ViDBo
+output 								 tf_push;
+  `endif
+
 input 								 wb_clk_i;
 
 // WISHBONE interface
@@ -225,7 +234,12 @@
 
 // Registers
 uart_regs #(.SIM (SIM))	regs(
-	.clk(		wb_clk_i		),
+
+  `ifdef ViDBo
+	.tf_push(	tf_push		),
+  `endif
+
+	.clk(		wb_clk_i	),
 	.wb_rst_i(	wb_rst_i	),
 	.wb_addr_i(	wb_adr_int	),
 	.wb_dat_i(	wb_dat8_i	),
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_decode_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_decode_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_decode_ctl.sv	2022-02-02 04:00:26.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_decode_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -17,6 +17,34 @@
 module dec_decode_ctl
    import swerv_types::*;
 (
+
+   output dest_pkt_t  dd, e1d, e2d, e3d, e4d, wbd,
+
+   output logic [31:0] i1_result_e2,
+
+   output logic [31:0] i0_result_e3_final,
+   output logic [31:0] i1_result_e3_final,
+
+   output logic [31:0] i0_result_e4_final,
+   output logic [31:0] i1_result_e4_final,
+
+   output logic [31:0]  dec_i0_pc_d_ext,
+
+   output logic [31:0]        i0_inst_d,
+   output logic [31:0]        i0_inst_e1,
+   output logic [31:0]        i0_inst_e2,
+   output logic [31:0]        i0_inst_e3,
+   output logic [31:0]        i0_inst_e4,
+   output logic [31:0]        i0_inst_wb,
+
+   output logic [31:0]        i1_inst_d,
+   output logic [31:0]        i1_inst_e1,
+   output logic [31:0]        i1_inst_e2,
+   output logic [31:0]        i1_inst_e3,
+   output logic [31:0]        i1_inst_e4,
+   output logic [31:0]        i1_inst_wb,
+
+
    input logic [15:0] dec_i0_cinst_d,         // 16b compressed instruction
    input logic [15:0] dec_i1_cinst_d,
 
@@ -281,7 +309,6 @@
 
 
    // PC Extended
-   logic [31:0]  dec_i0_pc_d_ext;
    assign dec_i0_pc_d_ext = {dec_i0_pc_d,1'b0};
 
 
@@ -294,7 +321,6 @@
    logic               i0_valid_d, i1_valid_d;
 
    logic [31:0]        i0_result_e1, i1_result_e1;
-   logic [31:0]                      i1_result_e2;
    logic [31:0]        i0_result_e3, i1_result_e3;
    logic [31:0]        i0_result_e4, i1_result_e4;
    logic [31:0]        i0_result_wb, i1_result_wb;
@@ -357,7 +383,6 @@
 
    logic               i1_flush_final_e3;
 
-   logic [31:0]        i0_result_e3_final, i1_result_e3_final;
    logic [31:0]        i0_result_wb_raw,   i1_result_wb_raw;
    logic [12:1] last_br_immed_d;
    logic        i1_depend_i0_d;
@@ -375,7 +400,6 @@
    logic        i0_secondary_block_d, i1_secondary_block_d;
    logic        non_block_case_d;
    logic        i0_div_decode_d;
-   logic [31:0] i0_result_e4_final, i1_result_e4_final;
    logic        i0_load_block_d;
    logic        i0_mul_block_d;
    logic [3:0]  i0_rs1_depth_d, i0_rs2_depth_d;
@@ -561,12 +585,6 @@
 
    logic [4:0] div_waddr_wb;
    logic [12:1] last_br_immed_e1, last_br_immed_e2;
-   logic [31:0]        i0_inst_d, i1_inst_d;
-   logic [31:0]        i0_inst_e1, i1_inst_e1;
-   logic [31:0]        i0_inst_e2, i1_inst_e2;
-   logic [31:0]        i0_inst_e3, i1_inst_e3;
-   logic [31:0]        i0_inst_e4, i1_inst_e4;
-   logic [31:0]        i0_inst_wb, i1_inst_wb;
    logic [31:0]        i0_inst_wb1,i1_inst_wb1;
 
    logic [31:0]        div_inst;
@@ -580,7 +598,6 @@
 
    class_pkt_t i0_e4c_in, i1_e4c_in;
 
-   dest_pkt_t  dd, e1d, e2d, e3d, e4d, wbd;
    dest_pkt_t e1d_in, e2d_in, e3d_in, e4d_in;
 
 
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_ib_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_ib_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_ib_ctl.sv	2022-02-02 04:00:26.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec_ib_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -19,6 +19,11 @@
    input logic   free_clk,                    // free clk
    input logic   active_clk,                  // active clk if not halt / pause
 
+   output logic [31:0]  ib3_in,
+   output logic [31:0]  ib2_in,
+   output logic [31:0]  ib1_in,
+   output logic [31:0]  ib0_in,
+
    input logic                 dbg_cmd_valid,  // valid dbg cmd
 
    input logic                 dbg_cmd_write,  // dbg cmd is write
@@ -112,7 +117,6 @@
 
    logic [3:0]   ibval_in, ibval;
 
-   logic [31:0]  ib3_in, ib2_in, ib1_in, ib0_in;
    logic [31:0]  ib3, ib2, ib1, ib0;
 
    logic [36:0]  pc3_in, pc2_in, pc1_in, pc0_in;
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec.sv src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec.sv	2022-02-02 04:00:26.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/dec/dec.sv	2022-11-26 07:00:04.915866563 +0100
@@ -30,6 +30,47 @@
 module dec
    import swerv_types::*;
 (
+   output logic [31:0]  ib3_in,
+   output logic [31:0]  ib2_in,
+   output logic [31:0]  ib1_in,
+   output logic [31:0]  ib0_in,
+
+   output dest_pkt_t  dd, e1d, e2d, e3d, e4d, wbd,
+
+   output logic [31:0] i1_result_e2,
+
+   output logic [31:0] i0_result_e3_final,
+   output logic [31:0] i1_result_e3_final,
+
+   output logic [31:0] i0_result_e4_final,
+   output logic [31:0] i1_result_e4_final,
+
+   output logic [31:0]  dec_i0_pc_d_ext,
+
+   output logic [4:0]  dec_i0_waddr_wb,
+   output logic        dec_i0_wen_wb,
+   output logic [31:0] dec_i0_wdata_wb,
+
+   output logic [4:0]  dec_i1_waddr_wb,
+   output logic        dec_i1_wen_wb,
+   output logic [31:0] dec_i1_wdata_wb,
+
+
+   output logic [31:0]        i0_inst_d,
+   output logic [31:0]        i0_inst_e1,
+   output logic [31:0]        i0_inst_e2,
+   output logic [31:0]        i0_inst_e3,
+   output logic [31:0]        i0_inst_e4,
+   output logic [31:0]        i0_inst_wb,
+
+   output logic [31:0]        i1_inst_d,
+   output logic [31:0]        i1_inst_e1,
+   output logic [31:0]        i1_inst_e2,
+   output logic [31:0]        i1_inst_e3,
+   output logic [31:0]        i1_inst_e4,
+   output logic [31:0]        i1_inst_wb,
+
+
    input logic clk,
    input logic free_clk,
    input logic active_clk,
@@ -436,14 +477,6 @@
    logic  dec_tlu_dual_issue_disable;
 
 
-   logic [4:0]  dec_i0_waddr_wb;
-   logic        dec_i0_wen_wb;
-   logic [31:0] dec_i0_wdata_wb;
-
-   logic [4:0]  dec_i1_waddr_wb;
-   logic        dec_i1_wen_wb;
-   logic [31:0] dec_i1_wdata_wb;
-
    logic        dec_csr_wen_wb;      // csr write enable at wb
    logic [11:0] dec_csr_rdaddr_d;      // read address for csr
    logic [11:0] dec_csr_wraddr_wb;      // write address for csryes
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_alu_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_alu_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_alu_ctl.sv	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_alu_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -17,6 +17,9 @@
 module exu_alu_ctl
    import swerv_types::*;
 (
+
+   output logic [31:0] flush_path_ext,
+
    input logic  clk,                      // Top level clock
    input logic  active_clk,               // Level 1 free clock
    input logic  rst_l,                    // Reset
@@ -26,6 +29,9 @@
 
    input logic freeze,                    // Clock enable for valid
 
+   output logic signed [31:0]  a_ff,
+   output logic [31:0]         b_ff,
+
    input logic [31:0] a,                  // A operand
    input logic [31:0] b,                  // B operand
    input logic [31:1] pc,                 // for pc=pc+2,4 calculations
@@ -68,10 +74,6 @@
 
    logic                actual_taken;
 
-   logic signed [31:0]  a_ff;
-
-   logic [31:0]         b_ff;
-
    logic [12:1]         brimm_ff;
 
    logic [31:1]         pcout;
@@ -277,7 +279,6 @@
    logic [31:0] pc_ext;
    assign pc_ext[31:0] = {pc[31:1],1'b0};
 
-   logic [31:0] flush_path_ext;
    assign flush_path_ext[31:0] = {flush_path[31:1],1'b0};
 
    logic [31:0] pc_ff_ext;
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_mul_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_mul_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_mul_ctl.sv	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu_mul_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -17,6 +17,11 @@
 module exu_mul_ctl
    import swerv_types::*;
 (
+
+   output logic        [31:0]  a_e1,
+   output logic        [31:0]  b_e1,
+   output logic        [63:0]  prod_e2_red,
+
    input logic         clk,              // Top level clock
    input logic         active_clk,       // Level 1 active clock
    input logic         clk_override,     // Override clock enables
@@ -42,8 +47,8 @@
    logic                mul_c1_e1_clken,   mul_c1_e2_clken,   mul_c1_e3_clken;
    logic                exu_mul_c1_e1_clk, exu_mul_c1_e2_clk, exu_mul_c1_e3_clk;
 
-   logic        [31:0]  a_ff_e1, a_e1;
-   logic        [31:0]  b_ff_e1, b_e1;
+   logic        [31:0]  a_ff_e1;
+   logic        [31:0]  b_ff_e1;
    logic                load_mul_rs1_bypass_e1, load_mul_rs2_bypass_e1;
    logic                rs1_sign_e1, rs1_neg_e1;
    logic                rs2_sign_e1, rs2_neg_e1;
@@ -102,11 +107,12 @@
 
    // ---------------------- E2 Logic Stage --------------------------
 
-
    logic signed [65:0]  prod_e2;
 
    assign prod_e2[65:0]          =  a_ff_e2  *  b_ff_e2;
 
+   assign prod_e2_red[63:0]      =  prod_e2[65:0];
+
    rvdff_fpga  #(1)    low_e3_ff      (.*, .din(low_e2),                    .dout(low_e3),                 .clk(exu_mul_c1_e3_clk), .clken(mul_c1_e3_clken), .rawclk(clk));
 
    rvdffe      #(64) prod_e3_ff       (.*, .din(prod_e2[63:0]),             .dout(prod_e3[63:0]),          .en(mul_c1_e3_clken));
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu.sv src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu.sv	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/exu/exu.sv	2022-11-26 07:00:04.915866563 +0100
@@ -18,6 +18,37 @@
    import swerv_types::*;
 (
 
+   output logic        exu_i0_flush_upper_e1,
+   output logic [31:1] exu_i0_flush_path_e1_ext,
+   output logic        exu_i1_flush_upper_e1,
+   output logic [31:1] exu_i1_flush_path_e1_ext,
+
+   output logic        [31:0]  a_e1,
+   output logic        [31:0]  b_e1,
+   output logic        [63:0]  prod_e2_red,
+
+   output logic [31:0]  mul_rs1_d,
+   output logic [31:0]  mul_rs2_d,
+
+   output alu_pkt_t i0_ap_e1,
+   output alu_pkt_t i0_ap_e2,
+   output alu_pkt_t i0_ap_e3,
+   output alu_pkt_t i0_ap_e4,
+   output alu_pkt_t i1_ap_e1,
+   output alu_pkt_t i1_ap_e2,
+   output alu_pkt_t i1_ap_e3,
+   output alu_pkt_t i1_ap_e4,
+
+   output logic [31:0] i0_rs1_d,
+   output logic [31:0] i0_rs2_d,
+   output logic [31:0] i1_rs1_d,
+   output logic [31:0] i1_rs2_d,
+
+   output logic [31:0] aff0,
+   output logic [31:0] aff1,
+   output logic [31:0] bff0,
+   output logic [31:0] bff1,
+
    input logic clk,                                                    // Top level clock
    input logic active_clk,                                             // Level 1 active clock
    input logic clk_override,                                           // Override multiply clock enables
@@ -208,20 +239,14 @@
    );
 
 
-   logic [31:0] i0_rs1_d,i0_rs2_d,i1_rs1_d,i1_rs2_d;
-
 
-
-   logic        exu_i0_flush_upper_e1;
    logic [31:1] exu_i0_flush_path_e1;
 
-   logic        exu_i1_flush_upper_e1;
    logic [31:1] exu_i1_flush_path_e1;
 
    logic [31:0] i0_rs1_final_d;
 
    logic [31:1]  exu_flush_path_e2;
-   logic [31:0]  mul_rs1_d, mul_rs2_d;
 
    logic [31:0]  div_rs1_d, div_rs2_d;
 
@@ -272,8 +297,6 @@
    logic        freeze;
 
 
-   alu_pkt_t i0_ap_e1, i0_ap_e2, i0_ap_e3, i0_ap_e4;
-   alu_pkt_t i1_ap_e1, i1_ap_e2, i1_ap_e3, i1_ap_e4;
    assign freeze = lsu_freeze_dc3;
 
    assign i0_rs1_d[31:0] = ({32{~dec_i0_rs1_bypass_en_d}} & ((dec_debug_wdata_rs1_d) ? dbg_cmd_wrdata[31:0] : gpr_i0_rs1_d[31:0])) |
@@ -404,6 +427,10 @@
                           .predict_p     ( i0_predict_newp_d           ),   // I
                           .valid         ( dec_i0_alu_decode_d         ),   // I
                           .flush         ( exu_flush_final             ),   // I
+
+                          .a_ff             ( aff0[31:0]        ),   // I
+                          .b_ff             ( bff0[31:0]              ),   // I
+
                           .a             ( i0_rs1_final_d[31:0]        ),   // I
                           .b             ( i0_rs2_d[31:0]              ),   // I
                           .pc            ( dec_i0_pc_d[31:1]           ),   // I
@@ -412,6 +439,7 @@
                           .out           ( exu_i0_result_e1[31:0]      ),   // O
                           .flush_upper   ( exu_i0_flush_upper_e1       ),   // O : will be 0 if freeze this cycle
                           .flush_path    ( exu_i0_flush_path_e1[31:1]  ),   // O
+                          .flush_path_ext    ( exu_i0_flush_path_e1_ext[31:1]  ),   // O
                           .predict_p_ff  ( i0_predict_p_e1             ),   // O
                           .pc_ff         ( exu_i0_pc_e1[31:1]          ),   // O
                           .pred_correct  ( i0_pred_correct_upper_e1    )    // O
@@ -424,6 +452,10 @@
                           .predict_p     ( i1_predict_newp_d           ),   // I
                           .valid         ( dec_i1_alu_decode_d         ),   // I
                           .flush         ( exu_flush_final             ),   // I
+
+                          .a_ff             ( aff1[31:0]        ),   // I
+                          .b_ff             ( bff1[31:0]              ),   // I
+
                           .a             ( i1_rs1_d[31:0]              ),   // I
                           .b             ( i1_rs2_d[31:0]              ),   // I
                           .pc            ( dec_i1_pc_d[31:1]           ),   // I
@@ -432,6 +464,7 @@
                           .out           ( exu_i1_result_e1[31:0]      ),   // O
                           .flush_upper   ( exu_i1_flush_upper_e1       ),   // O : will be 0 if freeze this cycle
                           .flush_path    ( exu_i1_flush_path_e1[31:1]  ),   // O
+                          .flush_path_ext    ( exu_i1_flush_path_e1_ext[31:1]  ),   // O
                           .predict_p_ff  ( i1_predict_p_e1             ),   // O
                           .pc_ff         ( exu_i1_pc_e1[31:1]          ),   // O
                           .pred_correct  ( i1_pred_correct_upper_e1    )    // O
@@ -589,12 +622,17 @@
 
 `else
 
+   logic [31:1] exu_i0_flush_path_e4_ext;
+   logic [31:1] exu_i1_flush_path_e4_ext;
+
    exu_alu_ctl i0_alu_e4 (.*,
                           .freeze        ( 1'b0                        ),   // I
                           .enable        ( i0_e4_ctl_en                ),   // I
                           .predict_p     ( i0_pp_e4_in                 ),   // I
                           .valid         ( dec_i0_sec_decode_e3        ),   // I
                           .flush         ( dec_tlu_flush_lower_wb      ),   // I
+                          .a_ff             (        ),   // I
+                          .b_ff             (        ),   // I
                           .a             ( i0_rs1_e3_final[31:0]       ),   // I
                           .b             ( i0_rs2_e3_final[31:0]       ),   // I
                           .pc            ( dec_i0_pc_e3[31:1]          ),   // I
@@ -603,6 +641,7 @@
                           .out           ( exu_i0_result_e4[31:0]      ),   // O
                           .flush_upper   ( exu_i0_flush_lower_e4       ),   // O
                           .flush_path    ( exu_i0_flush_path_e4[31:1]  ),   // O
+                          .flush_path_ext    ( exu_i0_flush_path_e4_ext[31:1]  ),   // O
                           .predict_p_ff  ( i0_predict_p_e4             ),   // O
                           .pc_ff         ( i0_alu_pc_nc[31:1]          ),   // O
                           .pred_correct  ( i0_pred_correct_lower_e4    )    // O
@@ -615,6 +654,8 @@
                           .predict_p     ( i1_pp_e4_in                 ),   // I
                           .valid         ( dec_i1_sec_decode_e3        ),   // I
                           .flush         ( dec_tlu_flush_lower_wb      ),   // I
+                          .a_ff             (        ),   // I
+                          .b_ff             (        ),   // I
                           .a             ( i1_rs1_e3_final[31:0]       ),   // I
                           .b             ( i1_rs2_e3_final[31:0]       ),   // I
                           .pc            ( dec_i1_pc_e3[31:1]          ),   // I
@@ -623,6 +664,7 @@
                           .out           ( exu_i1_result_e4[31:0]      ),   // O
                           .flush_upper   ( exu_i1_flush_lower_e4       ),   // O
                           .flush_path    ( exu_i1_flush_path_e4[31:1]  ),   // O
+                          .flush_path_ext    ( exu_i1_flush_path_e4_ext[31:1]  ),   // O
                           .predict_p_ff  ( i1_predict_p_e4             ),   // O
                           .pc_ff         ( i1_alu_pc_nc[31:1]          ),   // O
                           .pred_correct  ( i1_pred_correct_lower_e4    )    // O
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_ifc_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_ifc_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_ifc_ctl.sv	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_ifc_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -22,6 +22,8 @@
 
 module ifu_ifc_ctl
   (
+   output logic [31:0] ifc_fetch_addr_f1_ext,
+
    input logic clk,
    input logic free_clk,
    input logic active_clk,
@@ -164,7 +166,6 @@
    logic [31:0] ifu_bp_btb_target_f2_ext;
    assign ifu_bp_btb_target_f2_ext[31:0] = {ifu_bp_btb_target_f2[31:1],1'b0};
 
-   logic [31:0] ifc_fetch_addr_f1_ext;
    assign ifc_fetch_addr_f1_ext[31:0] = {ifc_fetch_addr_f1[31:1],1'b0};
 
    logic [31:0] fetch_addr_next_ext;
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_mem_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_mem_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_mem_ctl.sv	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu_mem_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -29,6 +29,9 @@
    input logic active_clk,                                          // Active always except during pause
    input logic rst_l,
 
+   output logic           ic_act_miss_f2,
+   output logic           ic_act_hit_f2,
+
    input logic                       exu_flush_final,               // Flush from the pipeline.
    input logic                       dec_tlu_flush_err_wb,          // Flush from the pipeline due to perr.
 
@@ -252,9 +255,7 @@
    logic           ifc_iccm_access_f2 ;
    logic           ifc_region_acc_fault_f2;
    logic  [7:0]    ifc_bus_acc_fault_f2;
-   logic           ic_act_miss_f2;
    logic           ic_miss_under_miss_f2;
-   logic           ic_act_hit_f2;
    logic           miss_pending;
    logic [31:1]    imb_in , imb_ff  ;
    logic           flush_final_f2;
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu.sv src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu.sv	2022-02-02 04:00:28.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/ifu/ifu.sv	2022-11-26 07:00:04.915866563 +0100
@@ -22,6 +22,13 @@
 module ifu
    import swerv_types::*;
 (
+   output logic           ic_act_miss_f2,
+   output logic           ic_act_hit_f2,
+
+   output logic ic_hit_f2,
+
+   output logic [31:0] ifc_fetch_addr_f1_ext,
+
    input logic free_clk,
    input logic active_clk,
    input logic clk,
@@ -256,8 +263,6 @@
    logic        ifu_ic_mb_empty;
 
 
-   logic ic_hit_f2;
-
    // fetch control
    ifu_ifc_ctl ifc (.*
                     );
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_dccm_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_dccm_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_dccm_ctl.sv	2022-02-02 04:00:26.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_dccm_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -29,6 +29,12 @@
 module lsu_dccm_ctl
    import swerv_types::*;
 (
+
+   output logic                        lsu_dccm_rden_dc1,
+   output logic                        lsu_dccm_rden_dc2,
+
+   output logic [DCCM_DATA_WIDTH-1:0]  dccm_data_lo_dc2,
+
    input logic                             lsu_freeze_c2_dc2_clk,     // clocks
    input logic                             lsu_freeze_c2_dc3_clk,
    input logic                             lsu_freeze_c2_dc2_clken,     // clocks
@@ -112,8 +118,7 @@
    localparam DCCM_WIDTH_BITS = $clog2(DCCM_BYTE_WIDTH);
    localparam PIC_BITS        =`RV_PIC_BITS;
 
-   logic                        lsu_dccm_rden_dc1, lsu_dccm_rden_dc2;
-   logic [DCCM_DATA_WIDTH-1:0]  dccm_data_hi_dc2, dccm_data_lo_dc2;
+   logic [DCCM_DATA_WIDTH-1:0]  dccm_data_hi_dc2;
    logic [DCCM_ECC_WIDTH-1:0]   dccm_data_ecc_hi_dc2, dccm_data_ecc_lo_dc2;
    logic [63:0]  dccm_dout_dc3, dccm_corr_dout_dc3;
    logic [63:0]  stbuf_fwddata_dc3;
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_lsc_ctl.sv src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_lsc_ctl.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_lsc_ctl.sv	2022-02-02 04:00:26.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu_lsc_ctl.sv	2022-11-26 07:00:04.915866563 +0100
@@ -28,6 +28,15 @@
 module lsu_lsc_ctl
    import swerv_types::*;
 (
+
+   output logic               addr_external_dc1,
+   output logic               addr_external_dc3,
+
+   output logic [31:0]        rs1_dc1,
+   output logic [11:0]        offset_dc1,
+
+   output logic [31:0]        full_addr_dc1,
+
    input logic         rst_l,
    input logic         clk,
 
@@ -119,7 +128,6 @@
    output logic        addr_in_pic_dc2,
    output logic        addr_in_pic_dc3,
    output logic        addr_external_dc2,
-   output logic        addr_external_dc3,
    output logic        addr_external_dc4,
    output logic        addr_external_dc5,
 
@@ -143,12 +151,9 @@
 
 `include "global.h"
 
-   logic [31:0]        full_addr_dc1;
    logic [31:0]        full_end_addr_dc1;
    logic [31:0]        lsu_rs1_d;
    logic [11:0]        lsu_offset_d;
-   logic [31:0]        rs1_dc1;
-   logic [11:0]        offset_dc1;
    logic [12:0]        end_addr_offset_dc1;
    logic [31:0]        lsu_ld_datafn_dc3;
    logic [31:0]        lsu_ld_datafn_corr_dc3;
@@ -156,7 +161,6 @@
    logic [2:0]         addr_offset_dc1;
 
    logic [63:0]        dma_mem_wdata_shifted;
-   logic               addr_external_dc1;
    logic               access_fault_dc1, misaligned_fault_dc1;
    logic               access_fault_dc2, misaligned_fault_dc2;
    logic               access_fault_dc3, misaligned_fault_dc3;
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu.sv src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu.sv	2022-02-02 04:00:26.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/lsu/lsu.sv	2022-11-26 07:00:04.915866563 +0100
@@ -29,6 +29,33 @@
    import swerv_types::*;
 (
 
+   output logic        lsu_dccm_rden_dc1,
+   output logic        lsu_dccm_rden_dc2,
+   output logic        lsu_dccm_rden_dc3,
+
+   output logic               addr_external_dc1,
+   output logic               addr_external_dc2,
+   output logic               addr_external_dc3,
+   
+   output logic        lsu_busreq_dc2,
+   output logic [31:0] bus_read_data_dc3,
+
+   output lsu_pkt_t    lsu_pkt_dc1,
+   output lsu_pkt_t    lsu_pkt_dc2,
+   output lsu_pkt_t    lsu_pkt_dc3,
+   output lsu_pkt_t    lsu_pkt_dc4,
+   output lsu_pkt_t    lsu_pkt_dc5,
+
+   output logic [DCCM_DATA_WIDTH-1:0]  dccm_data_lo_dc2,
+
+   output logic [31:0]        rs1_dc1,
+   output logic [11:0]        offset_dc1,
+
+   output logic [31:0] dccm_data_lo_dc3,
+
+   output logic [31:0]        full_addr_dc1,
+
+
    input logic [31:0]                      i0_result_e4_eff, // I0 e4 result for e4 -> dc3 store forwarding
    input logic [31:0]                      i1_result_e4_eff, // I1 e4 result for e4 -> dc3 store forwarding
    input logic [31:0]                      i0_result_e2,     // I0 e2 result for e2 -> dc2 store forwarding
@@ -182,7 +209,6 @@
 
 `include "global.h"
 
-   logic        lsu_dccm_rden_dc3;
    logic [63:0] store_data_dc2;
    logic [63:0] store_data_dc3;
    logic [31:0] store_data_dc4;
@@ -195,7 +221,6 @@
    logic        lsu_double_ecc_error_dc3;
 
    logic [31:0] dccm_data_hi_dc3;
-   logic [31:0] dccm_data_lo_dc3;
    logic [6:0]  dccm_data_ecc_hi_dc3;
    logic [6:0]  dccm_data_ecc_lo_dc3;
 
@@ -206,7 +231,6 @@
    logic [31:0] lsu_addr_dc1, lsu_addr_dc2, lsu_addr_dc3, lsu_addr_dc4, lsu_addr_dc5;
    logic [31:0] end_addr_dc1, end_addr_dc2, end_addr_dc3, end_addr_dc4, end_addr_dc5;
 
-   lsu_pkt_t    lsu_pkt_dc1, lsu_pkt_dc2, lsu_pkt_dc3, lsu_pkt_dc4, lsu_pkt_dc5;
    logic        lsu_i0_valid_dc1, lsu_i0_valid_dc2, lsu_i0_valid_dc3, lsu_i0_valid_dc4, lsu_i0_valid_dc5;
 
    // Store Buffer signals
@@ -219,7 +243,7 @@
 
    logic        addr_in_dccm_dc1, addr_in_dccm_dc2, addr_in_dccm_dc3;
    logic        addr_in_pic_dc1, addr_in_pic_dc2, addr_in_pic_dc3;
-   logic        addr_external_dc2, addr_external_dc3, addr_external_dc4, addr_external_dc5;
+   logic        addr_external_dc4, addr_external_dc5;
 
    logic                       stbuf_reqvld_any;
    logic                       stbuf_reqvld_flushed_any;
@@ -245,8 +269,6 @@
    logic        lsu_bus_buffer_pend_any;
    logic        lsu_bus_buffer_empty_any;
    logic        lsu_bus_buffer_full_any;
-   logic        lsu_busreq_dc2;
-   logic [31:0] bus_read_data_dc3;
    logic        ld_bus_error_dc3;
    logic [31:0] ld_bus_error_addr_dc3;
 
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/swerv.sv src/SweRVolfSoC/SweRVEh1CoreComplex/swerv.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/swerv.sv	2022-02-02 04:00:24.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/swerv.sv	2022-11-26 07:00:04.911866446 +0100
@@ -23,6 +23,123 @@
 module swerv
    import swerv_types::*;
 (
+   output logic           ic_act_miss_f2,
+   output logic           ic_act_hit_f2,
+
+   output logic [31:0]  ib3_in,
+   output logic [31:0]  ib2_in,
+   output logic [31:0]  ib1_in,
+   output logic [31:0]  ib0_in,
+
+   output logic ic_hit_f2,
+
+   output logic        exu_i0_flush_upper_e1,
+   output logic [31:1] exu_i0_flush_path_e1_ext,
+   output logic        exu_i1_flush_upper_e1,
+   output logic [31:1] exu_i1_flush_path_e1_ext,
+
+   output logic [31:0] ifc_fetch_addr_f1_ext,
+
+   output logic               addr_external_dc1,
+   output logic               addr_external_dc2,
+   output logic               addr_external_dc3,
+
+   output logic        lsu_dccm_rden_dc1,
+   output logic        lsu_dccm_rden_dc2,
+   output logic        lsu_dccm_rden_dc3,
+
+   output logic        [31:0]  a_e1,
+   output logic        [31:0]  b_e1,
+   output logic        [63:0]  prod_e2_red,
+   logic [31:0] exu_mul_result_e3,
+
+   output logic [31:0]  mul_rs1_d,
+   output logic [31:0]  mul_rs2_d,
+
+   output logic [31:0] exu_lsu_rs1_d,
+
+   output logic [31:0] i0_result_e2,
+   output logic [31:0] i1_result_e2,
+
+   output logic [31:0] i0_result_e3_final,
+   output logic [31:0] i1_result_e3_final,
+
+   output logic [5:0]   i0_control,
+   output logic [5:0]   i1_control,
+   output logic [5:0]   lsu_control,
+   output logic [5:0]   mul_control,
+   output logic [5:0]   i0_branch,
+   output logic [5:0]   i1_branch,
+
+   output logic         lsu_load_stall_any,       // This is for blocking stores
+   output logic        lsu_busreq_dc2,
+   output logic [31:0] bus_read_data_dc3,
+
+   output logic [DCCM_DATA_WIDTH-1:0]  dccm_data_lo_dc2,
+
+   output logic [31:0]        rs1_dc1,
+   output logic [11:0]        offset_dc1,
+
+   output logic [31:0] i0_result_e4_final,
+   output logic [31:0] i1_result_e4_final,
+
+   output logic [31:0] dccm_data_lo_dc3,
+
+   output logic [31:0]        full_addr_dc1,
+
+   output logic [11:0] dec_lsu_offset_d,
+
+   output logic [31:0]  dec_i0_pc_d_ext,
+
+   output logic [4:0]  dec_i0_waddr_wb,
+   output logic        dec_i0_wen_wb,
+   output logic [31:0] dec_i0_wdata_wb,
+
+   output logic [4:0]  dec_i1_waddr_wb,
+   output logic        dec_i1_wen_wb,
+   output logic [31:0] dec_i1_wdata_wb,
+
+   output logic [31:0] i0_rs1_d,
+   output logic [31:0] i0_rs2_d,
+   output logic [31:0] i1_rs1_d,
+   output logic [31:0] i1_rs2_d,
+
+   output logic [31:0] exu_i0_result_e1,
+   output logic [31:0] exu_i1_result_e1,
+
+   output logic [31:0] i0_rs1_bypass_data_d,
+   output logic [31:0] i0_rs2_bypass_data_d,
+   output logic [31:0] i1_rs1_bypass_data_d,
+   output logic [31:0] i1_rs2_bypass_data_d,
+
+   output logic [31:0] aff0,
+   output logic [31:0] aff1,
+   output logic [31:0] bff0,
+   output logic [31:0] bff1,
+
+   output logic  [31:0] gpr_i0_rs1_d,               // gpr rs1 data
+   output logic  [31:0] gpr_i0_rs2_d,               // gpr rs2 data
+   output logic  [31:0] gpr_i1_rs1_d,
+   output logic  [31:0] gpr_i1_rs2_d,
+
+
+   output logic [31:0]        i0_inst_d,
+   output logic [31:0]        i0_inst_e1,
+   output logic [31:0]        i0_inst_e2,
+   output logic [31:0]        i0_inst_e3,
+   output logic [31:0]        i0_inst_e4,
+   output logic [31:0]        i0_inst_wb,
+
+   output logic [31:0]        i1_inst_d,
+   output logic [31:0]        i1_inst_e1,
+   output logic [31:0]        i1_inst_e2,
+   output logic [31:0]        i1_inst_e3,
+   output logic [31:0]        i1_inst_e4,
+   output logic [31:0]        i1_inst_wb,
+
+
+
+
    input logic                  clk,
    input logic                  rst_l,
    input logic                  dbg_rst_l,
@@ -121,6 +238,10 @@
    input  logic [3:0]            ic_rd_hit,
    input  logic                  ic_tag_perr,        // Icache Tag parity error
 
+
+   output logic [31:0]           ifu_i0_instr_export,
+   output logic [31:0]           ifu_i1_instr_export,
+
 `ifdef RV_BUILD_AXI4
    //-------------------------- LSU AXI signals--------------------------
    // AXI Write Channels
@@ -391,6 +512,17 @@
 // `define DATAWIDTH 64
 `define ADDRWIDTH 32
 
+   lsu_pkt_t    lsu_pkt_dc1;
+   lsu_pkt_t    lsu_pkt_dc2;
+   lsu_pkt_t    lsu_pkt_dc3;
+   lsu_pkt_t    lsu_pkt_dc4;
+   lsu_pkt_t    lsu_pkt_dc5;
+
+   alu_pkt_t i0_ap_e1, i0_ap_e2, i0_ap_e3, i0_ap_e4;
+   alu_pkt_t i1_ap_e1, i1_ap_e2, i1_ap_e3, i1_ap_e4;
+   dest_pkt_t  dd, e1d, e2d, e3d, e4d, wbd;
+
+
 `ifndef RV_BUILD_AXI4
 
    // LSU AXI signals
@@ -597,16 +729,7 @@
    cache_debug_pkt_t dec_tlu_ic_diag_pkt; // packet of DICAWICS, DICAD0/1, DICAGO info for icache diagnostics
 
 
-   logic  [31:0] gpr_i0_rs1_d;
-   logic  [31:0] gpr_i0_rs2_d;
-   logic  [31:0] gpr_i1_rs1_d;
-   logic  [31:0] gpr_i1_rs2_d;
-
-   logic [31:0] i0_rs1_bypass_data_d;
-   logic [31:0] i0_rs2_bypass_data_d;
-   logic [31:0] i1_rs1_bypass_data_d;
-   logic [31:0] i1_rs2_bypass_data_d;
-   logic [31:0] exu_i0_result_e1, exu_i1_result_e1;
+
    logic  [31:1] exu_i0_pc_e1;
    logic  [31:1] exu_i1_pc_e1;  // from the primary alu's
    logic [31:1]  exu_npc_e4;
@@ -662,13 +785,11 @@
 
    logic [31:1] exu_flush_path_final;
 
-   logic [31:0] exu_lsu_rs1_d;
    logic [31:0] exu_lsu_rs2_d;
 
 
    lsu_pkt_t    lsu_p;
 
-   logic [11:0] dec_lsu_offset_d;
    logic        dec_i0_lsu_d;       // chose which gpr value to use
    logic        dec_i1_lsu_d;
 
@@ -680,7 +801,6 @@
    logic         lsu_imprecise_error_load_any;
    logic         lsu_imprecise_error_store_any;
    logic [31:0]  lsu_imprecise_error_addr_any;
-   logic         lsu_load_stall_any;       // This is for blocking stores
    logic         lsu_store_stall_any;       // This is for blocking stores
    logic         lsu_load_ecc_stbuf_full_dc3;   // Load with ecc error can't allocate to stbuf
    logic         lsu_idle_any;
@@ -716,7 +836,6 @@
 
    mul_pkt_t  mul_p;
 
-   logic [31:0] exu_mul_result_e3;
 
    logic dec_i0_mul_d;
    logic dec_i1_mul_d;
@@ -833,8 +952,6 @@
    logic [31:0] i0_result_e4_eff;
    logic [31:0] i1_result_e4_eff;
 
-   logic [31:0] i0_result_e2;
-
    logic        ifu_i0_icaf;
    logic        ifu_i1_icaf;
    logic        ifu_i0_icaf_second;
@@ -959,6 +1076,42 @@
    trace_pkt_t  trace_rv_trace_pkt;
 
 
+
+   assign i0_control[4] = i0_ap_e4.valid;
+   assign i0_control[3] = i0_ap_e3.valid;
+   assign i0_control[2] = i0_ap_e2.valid;
+   assign i0_control[1] = i0_ap_e1.valid;
+   assign i0_control[0] = i0_ap.valid;
+
+   assign i1_control[4] = i1_ap_e4.valid;
+   assign i1_control[3] = i1_ap_e3.valid;
+   assign i1_control[2] = i1_ap_e2.valid;
+   assign i1_control[1] = i1_ap_e1.valid;
+   assign i1_control[0] = i1_ap.valid;
+
+   assign lsu_control[5] = lsu_pkt_dc5[0];
+   assign lsu_control[4] = lsu_pkt_dc4[0];
+   assign lsu_control[3] = lsu_pkt_dc3[0];
+   assign lsu_control[2] = lsu_pkt_dc2[0];
+   assign lsu_control[1] = lsu_pkt_dc1[0];
+   assign lsu_control[0] = lsu_p[0];
+
+   assign mul_control[5] = (wbd.i0mul & wbd.i0valid) | (wbd.i1mul & wbd.i1valid);
+   assign mul_control[4] = (e4d.i0mul & e4d.i0valid) | (e4d.i1mul & e4d.i1valid);
+   assign mul_control[3] = (e3d.i0mul & e3d.i0valid) | (e3d.i1mul & e3d.i1valid);
+   assign mul_control[2] = (e2d.i0mul & e2d.i0valid) | (e2d.i1mul & e2d.i1valid);
+   assign mul_control[1] = (e1d.i0mul & e1d.i0valid) | (e1d.i1mul & e1d.i1valid);
+   assign mul_control[0] = (dd.i0mul & dd.i0valid) | (dd.i1mul & dd.i1valid);
+
+   assign i0_branch = i0_ap_e1.beq | i0_ap_e1.bne | i0_ap_e1.blt | i0_ap_e1.bge | i0_ap_e1.jal;
+   assign i1_branch = i1_ap_e1.beq | i1_ap_e1.bne | i1_ap_e1.blt | i1_ap_e1.bge | i1_ap_e1.jal;
+
+
+   assign ifu_i0_instr_export = ifu_i0_instr;
+   assign ifu_i1_instr_export = ifu_i1_instr;
+
+
+
    assign active_state = ~dec_pause_state_cg | dec_tlu_flush_lower_wb | dec_tlu_misc_clk_override;
 
    rvoclkhdr free_cg   ( .en(1'b1),         .l1clk(free_clk), .* );
diff -ruN ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/swerv_wrapper_dmi.sv src/SweRVolfSoC/SweRVEh1CoreComplex/swerv_wrapper_dmi.sv
--- ../RVfpga/src/SweRVolfSoC/SweRVEh1CoreComplex/swerv_wrapper_dmi.sv	2022-02-02 04:00:24.000000000 +0100
+++ src/SweRVolfSoC/SweRVEh1CoreComplex/swerv_wrapper_dmi.sv	2022-11-26 07:00:04.911866446 +0100
@@ -26,6 +26,125 @@
 module swerv_wrapper_dmi
    import swerv_types::*;
 (
+   output logic           ic_act_miss_f2,
+   output logic           ic_act_hit_f2,
+
+   output logic [31:0]  ib3_in,
+   output logic [31:0]  ib2_in,
+   output logic [31:0]  ib1_in,
+   output logic [31:0]  ib0_in,
+
+   output logic ic_hit_f2,
+
+   output logic        exu_i0_flush_upper_e1,
+   output logic [31:1] exu_i0_flush_path_e1_ext,
+   output logic        exu_i1_flush_upper_e1,
+   output logic [31:1] exu_i1_flush_path_e1_ext,
+
+   output logic [31:0] ifc_fetch_addr_f1_ext,
+
+   output logic               addr_external_dc1,
+   output logic               addr_external_dc2,
+   output logic               addr_external_dc3,
+
+   output logic        lsu_dccm_rden_dc1,
+   output logic        lsu_dccm_rden_dc2,
+   output logic        lsu_dccm_rden_dc3,
+
+   output logic        [31:0]  a_e1,
+   output logic        [31:0]  b_e1,
+   output logic        [63:0]  prod_e2_red,
+   logic [31:0] exu_mul_result_e3,
+
+   output logic [31:0]  mul_rs1_d,
+   output logic [31:0]  mul_rs2_d,
+
+   output logic [31:0] exu_lsu_rs1_d,
+
+   output logic [31:0] i0_result_e2,
+   output logic [31:0] i1_result_e2,
+
+   output logic [31:0] i0_result_e3_final,
+   output logic [31:0] i1_result_e3_final,
+
+   output logic [5:0]   i0_control,
+   output logic [5:0]   i1_control,
+   output logic [5:0]   lsu_control,
+   output logic [5:0]   mul_control,
+   output logic [5:0]   i0_branch,
+   output logic [5:0]   i1_branch,
+
+   output logic         lsu_load_stall_any,       // This is for blocking stores
+   output logic        lsu_busreq_dc2,
+   output logic [31:0] bus_read_data_dc3,
+
+   output logic [DCCM_DATA_WIDTH-1:0]  dccm_data_lo_dc2,
+
+   output logic         dccm_rden,
+
+   output logic [31:0]        rs1_dc1,
+   output logic [11:0]        offset_dc1,
+
+   output logic [31:0] i0_result_e4_final,
+   output logic [31:0] i1_result_e4_final,
+
+   output logic [31:0] dccm_data_lo_dc3,
+
+   output logic [31:0]        full_addr_dc1,
+
+   output logic [11:0] dec_lsu_offset_d,
+
+   output logic [31:0]  dec_i0_pc_d_ext,
+
+   output logic [4:0]  dec_i0_waddr_wb,
+   output logic        dec_i0_wen_wb,
+   output logic [31:0] dec_i0_wdata_wb,
+
+   output logic [4:0]  dec_i1_waddr_wb,
+   output logic        dec_i1_wen_wb,
+   output logic [31:0] dec_i1_wdata_wb,
+
+   output logic [31:0] i0_rs1_d,
+   output logic [31:0] i0_rs2_d,
+   output logic [31:0] i1_rs1_d,
+   output logic [31:0] i1_rs2_d,
+
+   output logic [31:0] exu_i0_result_e1,
+   output logic [31:0] exu_i1_result_e1,
+
+   output logic [31:0] i0_rs1_bypass_data_d,
+   output logic [31:0] i0_rs2_bypass_data_d,
+   output logic [31:0] i1_rs1_bypass_data_d,
+   output logic [31:0] i1_rs2_bypass_data_d,
+
+   output logic [31:0] aff0,
+   output logic [31:0] aff1,
+   output logic [31:0] bff0,
+   output logic [31:0] bff1,
+
+   output logic  [31:0] gpr_i0_rs1_d,               // gpr rs1 data
+   output logic  [31:0] gpr_i0_rs2_d,               // gpr rs2 data
+   output logic  [31:0] gpr_i1_rs1_d,
+   output logic  [31:0] gpr_i1_rs2_d,
+
+
+   output logic [31:0]        i0_inst_d,
+   output logic [31:0]        i0_inst_e1,
+   output logic [31:0]        i0_inst_e2,
+   output logic [31:0]        i0_inst_e3,
+   output logic [31:0]        i0_inst_e4,
+   output logic [31:0]        i0_inst_wb,
+
+   output logic [31:0]        i1_inst_d,
+   output logic [31:0]        i1_inst_e1,
+   output logic [31:0]        i1_inst_e2,
+   output logic [31:0]        i1_inst_e3,
+   output logic [31:0]        i1_inst_e4,
+   output logic [31:0]        i1_inst_wb,
+
+
+
+
    input logic                       clk,
    input logic                       rst_l,
    input logic                       dbg_rst_l,
@@ -42,6 +161,11 @@
    output logic [2:0]  trace_rv_i_interrupt_ip,
    output logic [31:0] trace_rv_i_tval_ip,
 
+
+   output logic [31:0]           ifu_i0_instr_export,
+   output logic [31:0]           ifu_i1_instr_export,
+
+
    // Bus signals
 
    //-------------------------- LSU AXI signals--------------------------
@@ -271,7 +395,6 @@
 
    // DCCM ports
    logic         dccm_wren;
-   logic         dccm_rden;
    logic [DCCM_BITS-1:0]  dccm_wr_addr;
    logic [DCCM_BITS-1:0]  dccm_rd_addr_lo;
    logic [DCCM_BITS-1:0]  dccm_rd_addr_hi;
diff -ruN ../RVfpga/src/SweRVolfSoC/swervolf_core.v src/SweRVolfSoC/swervolf_core.v
--- ../RVfpga/src/SweRVolfSoC/swervolf_core.v	2022-02-02 04:00:24.000000000 +0100
+++ src/SweRVolfSoC/swervolf_core.v	2022-11-26 07:00:04.907866328 +0100
@@ -36,6 +36,135 @@
     input wire 	       i_flash_miso,
     input wire 	       i_uart_rx,
     output wire        o_uart_tx,
+
+   output logic           ic_act_miss_f2,
+   output logic           ic_act_hit_f2,
+
+   output logic [31:0]  ib3_in,
+   output logic [31:0]  ib2_in,
+   output logic [31:0]  ib1_in,
+   output logic [31:0]  ib0_in,
+
+   output logic ic_hit_f2,
+
+   output logic        exu_i0_flush_upper_e1,
+   output logic [31:1] exu_i0_flush_path_e1_ext,
+   output logic        exu_i1_flush_upper_e1,
+   output logic [31:1] exu_i1_flush_path_e1_ext,
+
+   output logic [31:0] ifc_fetch_addr_f1_ext,
+
+   output logic               addr_external_dc1,
+   output logic               addr_external_dc2,
+   output logic               addr_external_dc3,
+
+   output logic        lsu_dccm_rden_dc1,
+   output logic        lsu_dccm_rden_dc2,
+   output logic        lsu_dccm_rden_dc3,
+
+   output logic        [31:0]  a_e1,
+   output logic        [31:0]  b_e1,
+   output logic        [63:0]  prod_e2_red,
+   logic [31:0] exu_mul_result_e3,
+
+   output logic [31:0]  mul_rs1_d,
+   output logic [31:0]  mul_rs2_d,
+
+   output logic [31:0] exu_lsu_rs1_d,
+
+   output logic [31:0] i0_result_e2,
+   output logic [31:0] i1_result_e2,
+
+   output logic [31:0] i0_result_e3_final,
+   output logic [31:0] i1_result_e3_final,
+
+   output logic [5:0]   i0_control,
+   output logic [5:0]   i1_control,
+   output logic [5:0]   lsu_control,
+   output logic [5:0]   mul_control,
+   output logic [5:0]   i0_branch,
+   output logic [5:0]   i1_branch,
+
+   output logic         lsu_load_stall_any,       // This is for blocking stores
+   output logic        lsu_busreq_dc2,
+   output logic [31:0] bus_read_data_dc3,
+   output wire        lsu_arvalid,
+   output wire        lsu_rvalid,
+
+
+   output logic [31:0]  dccm_data_lo_dc2,
+
+   output logic         dccm_rden,
+
+   output logic [31:0]        rs1_dc1,
+   output logic [11:0]        offset_dc1,
+
+   output logic [31:0] i0_result_e4_final,
+   output logic [31:0] i1_result_e4_final,
+
+   output logic [31:0] dccm_data_lo_dc3,
+
+   output logic [31:0]        full_addr_dc1,
+
+   output logic [11:0] dec_lsu_offset_d,
+
+   output logic [31:0]  dec_i0_pc_d_ext,
+
+   output logic [4:0]  dec_i0_waddr_wb,
+   output logic        dec_i0_wen_wb,
+   output logic [31:0] dec_i0_wdata_wb,
+
+   output logic [4:0]  dec_i1_waddr_wb,
+   output logic        dec_i1_wen_wb,
+   output logic [31:0] dec_i1_wdata_wb,
+
+   output logic [31:0] i0_rs1_d,
+   output logic [31:0] i0_rs2_d,
+   output logic [31:0] i1_rs1_d,
+   output logic [31:0] i1_rs2_d,
+
+   output logic [31:0] exu_i0_result_e1,
+   output logic [31:0] exu_i1_result_e1,
+
+   output logic [31:0] i0_rs1_bypass_data_d,
+   output logic [31:0] i0_rs2_bypass_data_d,
+   output logic [31:0] i1_rs1_bypass_data_d,
+   output logic [31:0] i1_rs2_bypass_data_d,
+
+   output logic [31:0] aff0,
+   output logic [31:0] aff1,
+   output logic [31:0] bff0,
+   output logic [31:0] bff1,
+
+    output logic  [31:0] gpr_i0_rs1_d,               // gpr rs1 data
+    output logic  [31:0] gpr_i0_rs2_d,               // gpr rs2 data
+    output logic  [31:0] gpr_i1_rs1_d,
+    output logic  [31:0] gpr_i1_rs2_d,
+
+    output logic [31:0]           ifu_i0_instr_export,
+    output logic [31:0]           ifu_i1_instr_export,
+
+   output logic [31:0]        i0_inst_d,
+   output logic [31:0]        i0_inst_e1,
+   output logic [31:0]        i0_inst_e2,
+   output logic [31:0]        i0_inst_e3,
+   output logic [31:0]        i0_inst_e4,
+   output logic [31:0]        i0_inst_wb,
+
+   output logic [31:0]        i1_inst_d,
+   output logic [31:0]        i1_inst_e1,
+   output logic [31:0]        i1_inst_e2,
+   output logic [31:0]        i1_inst_e3,
+   output logic [31:0]        i1_inst_e4,
+   output logic [31:0]        i1_inst_wb,
+
+
+
+  `ifdef ViDBo
+    output wire        tf_push,
+    output wire [7:0]  wb_m2s_uart_dat_output,
+  `endif
+
     output wire [5:0]  o_ram_awid,
     output wire [31:0] o_ram_awaddr,
     output wire [7:0]  o_ram_awlen,
@@ -77,9 +206,17 @@
     output wire        o_ram_rready,
     input wire 	       i_ram_init_done,
     input wire 	       i_ram_init_error,
+
+  `ifdef ViDBo
+    input wire [31:0]  i_data,
+    output wire [31:0] o_data,
+  `else
     inout wire [31:0]  io_data,
+  `endif
+
     output wire [ 7          :0] AN,
     output wire [ 6          :0] Digits_Bits,
+
     output wire        o_accel_sclk,
     output wire        o_accel_cs_n,
     output wire        o_accel_mosi,
@@ -97,6 +234,11 @@
 
    wire [31:0] nmi_vec;
 
+
+  `ifdef ViDBo
+   assign wb_m2s_uart_dat_output = wb_m2s_uart_dat;
+  `endif
+
 `include "axi_intercon.vh"
 
    assign o_ram_awid     = ram_awid;
@@ -235,7 +377,8 @@
       .o_wb_rdt         (wb_s2m_sys_dat),
       .o_wb_ack         (wb_s2m_sys_ack),
       .AN (AN),
-      .Digits_Bits (Digits_Bits));
+      .Digits_Bits (Digits_Bits)
+      );
 
    assign wb_s2m_sys_err = 1'b0;
    assign wb_s2m_sys_rty = 1'b0;
@@ -271,6 +414,11 @@
 
    uart_top uart16550_0
      (// Wishbone slave interface
+
+  `ifdef ViDBo
+      .tf_push  (tf_push),
+  `endif
+
       .wb_clk_i	(clk),
       .wb_rst_i	(~rst_n),
       .wb_adr_i	(wb_m2s_uart_adr[4:2]),
@@ -299,6 +447,9 @@
    // GPIO - Leds and Switches
    wire [31:0] en_gpio;
    wire        gpio_irq;
+
+  `ifndef ViDBo
+
    wire [31:0] i_gpio;
    wire [31:0] o_gpio;
 
@@ -335,6 +486,8 @@
    bidirec gpio30 (.oe(en_gpio[30]), .inp(o_gpio[30]), .outp(i_gpio[30]), .bidir(io_data[30]));
    bidirec gpio31 (.oe(en_gpio[31]), .inp(o_gpio[31]), .outp(i_gpio[31]), .bidir(io_data[31]));
 
+  `endif
+
    gpio_top gpio_module(
         .wb_clk_i     (clk), 
         .wb_rst_i     (wb_rst), 
@@ -349,8 +502,15 @@
         .wb_err_o     (wb_s2m_gpio_err),
         .wb_inta_o    (gpio_irq),
         // External GPIO Interface
+
+  `ifdef ViDBo
+        .ext_pad_i     (i_data[31:0]),
+        .ext_pad_o     (o_data[31:0]),
+  `else
         .ext_pad_i     (i_gpio[31:0]),
         .ext_pad_o     (o_gpio[31:0]),
+  `endif
+
         .ext_padoe_o   (en_gpio));
 
 
@@ -406,6 +566,123 @@
 
    swerv_wrapper_dmi swerv_eh1
      (
+      .ic_act_miss_f2      (ic_act_miss_f2),
+      .ic_act_hit_f2      (ic_act_hit_f2),
+
+      .ib3_in      (ib3_in),
+      .ib2_in      (ib2_in),
+      .ib1_in      (ib1_in),
+      .ib0_in      (ib0_in),
+
+      .ic_hit_f2      (ic_hit_f2),
+
+      .exu_i0_flush_upper_e1      (exu_i0_flush_upper_e1),
+      .exu_i0_flush_path_e1_ext      (exu_i0_flush_path_e1_ext),
+      .exu_i1_flush_upper_e1      (exu_i1_flush_upper_e1),
+      .exu_i1_flush_path_e1_ext      (exu_i1_flush_path_e1_ext),
+
+      .ifc_fetch_addr_f1_ext      (ifc_fetch_addr_f1_ext),
+
+      .addr_external_dc1      (addr_external_dc1),
+      .addr_external_dc2      (addr_external_dc2),
+      .addr_external_dc3      (addr_external_dc3),
+
+      .lsu_dccm_rden_dc1      (lsu_dccm_rden_dc1),
+      .lsu_dccm_rden_dc2      (lsu_dccm_rden_dc2),
+      .lsu_dccm_rden_dc3      (lsu_dccm_rden_dc3),
+
+      .a_e1      (a_e1),
+      .b_e1      (b_e1),
+      .prod_e2_red      (prod_e2_red),
+      .exu_mul_result_e3      (exu_mul_result_e3),
+
+      .mul_rs1_d      (mul_rs1_d),
+      .mul_rs2_d      (mul_rs2_d),
+
+      .exu_lsu_rs1_d      (exu_lsu_rs1_d),
+
+      .i0_result_e2      (i0_result_e2),
+      .i1_result_e2      (i1_result_e2),
+
+      .i0_result_e3_final      (i0_result_e3_final),
+      .i1_result_e3_final      (i1_result_e3_final),
+
+      .i0_control      (i0_control),
+      .i1_control      (i1_control),
+      .lsu_control      (lsu_control),
+      .mul_control      (mul_control),
+      .i0_branch      (i0_branch),
+      .i1_branch      (i1_branch),
+
+      .lsu_load_stall_any      (lsu_load_stall_any),
+      .lsu_busreq_dc2      (lsu_busreq_dc2),
+      .bus_read_data_dc3      (bus_read_data_dc3),
+
+      .dccm_data_lo_dc2      (dccm_data_lo_dc2),
+
+      .dccm_rden      (dccm_rden),
+
+      .rs1_dc1      (rs1_dc1),
+      .offset_dc1      (offset_dc1),
+
+      .i0_result_e4_final      (i0_result_e4_final),
+      .i1_result_e4_final      (i1_result_e4_final),
+
+      .dccm_data_lo_dc3      (dccm_data_lo_dc3),
+
+      .full_addr_dc1      (full_addr_dc1),
+
+      .dec_lsu_offset_d      (dec_lsu_offset_d),
+
+      .dec_i0_pc_d_ext      (dec_i0_pc_d_ext),
+
+      .dec_i0_waddr_wb      (dec_i0_waddr_wb),
+      .dec_i0_wen_wb      (dec_i0_wen_wb),
+      .dec_i0_wdata_wb      (dec_i0_wdata_wb),
+
+      .dec_i1_waddr_wb      (dec_i1_waddr_wb),
+      .dec_i1_wen_wb      (dec_i1_wen_wb),
+      .dec_i1_wdata_wb      (dec_i1_wdata_wb),
+
+      .i0_rs1_d      (i0_rs1_d),
+      .i0_rs2_d      (i0_rs2_d),
+      .i1_rs1_d      (i1_rs1_d),
+      .i1_rs2_d      (i1_rs2_d),
+
+      .exu_i0_result_e1      (exu_i0_result_e1),
+      .exu_i1_result_e1      (exu_i1_result_e1),
+
+      .i0_rs1_bypass_data_d      (i0_rs1_bypass_data_d),
+      .i0_rs2_bypass_data_d      (i0_rs2_bypass_data_d),
+      .i1_rs1_bypass_data_d      (i1_rs1_bypass_data_d),
+      .i1_rs2_bypass_data_d      (i1_rs2_bypass_data_d),
+
+      .aff0      (aff0),
+      .aff1      (aff1),
+      .bff0      (bff0),
+      .bff1      (bff1),
+
+      .gpr_i0_rs1_d      (gpr_i0_rs1_d),
+      .gpr_i0_rs2_d      (gpr_i0_rs2_d),
+      .gpr_i1_rs1_d      (gpr_i1_rs1_d),
+      .gpr_i1_rs2_d      (gpr_i1_rs2_d),
+
+
+      .i0_inst_d     (i0_inst_d),
+      .i0_inst_e1     (i0_inst_e1),
+      .i0_inst_e2     (i0_inst_e2),
+      .i0_inst_e3     (i0_inst_e3),
+      .i0_inst_e4     (i0_inst_e4),
+      .i0_inst_wb     (i0_inst_wb),
+
+      .i1_inst_d     (i1_inst_d),
+      .i1_inst_e1     (i1_inst_e1),
+      .i1_inst_e2     (i1_inst_e2),
+      .i1_inst_e3     (i1_inst_e3),
+      .i1_inst_e4     (i1_inst_e4),
+      .i1_inst_wb     (i1_inst_wb),
+
+
       .clk     (clk),
       .rst_l   (rstn),
       .dbg_rst_l   (rstn),
@@ -421,6 +698,11 @@
       .trace_rv_i_interrupt_ip (),
       .trace_rv_i_tval_ip      (),
 
+
+      .ifu_i0_instr_export (ifu_i0_instr_export),
+      .ifu_i1_instr_export (ifu_i1_instr_export),
+
+
       // Bus signals
       //-------------------------- LSU AXI signals--------------------------
       .lsu_axi_awvalid  (lsu_awvalid),
@@ -631,6 +913,8 @@
 endmodule
 
 
+`ifndef ViDBo
+
 // GPIO Extended
 module bidirec (input wire oe, input wire inp, output wire outp, inout wire bidir);
 
@@ -638,3 +922,5 @@
 assign outp  = bidir;
 
 endmodule
+
+`endif
\ No newline at end of file
