define_design_lib WORK -path ./WORK
set search_path ./
set suppress_errors {IFS-001}
set sh_continue_on_error true
set verilogout_no_tri true
 
## Setting up target libraries
set_app_var target_library {
/home/UFAD/a.chatterjee/Desktop/lab_work/oasis/lib/gsc/db/gscl45nm.db
}
 
## Setting up link libraries
set_app_var link_library {
/home/UFAD/a.chatterjee/Desktop/lab_work/oasis/lib/gsc/db/gscl45nm.db
}
 
## Setting up the HDL files
analyze -f verilog sequential_trojan_minimised.v
 
## Elaborating the top module
elaborate sequential_trojan

## Setting up the clock period, input delay and output delay
create_clock -name clk -period 0 {clk}
set_input_delay 0 -clock clk [all_inputs]
set_output_delay 0 -clock clk [all_outputs]
check_design
check_timing

 
set_max_area 0
compile -ungroup_all -area_effort high -map_effort high
 
 
## Dump the top module
write -f verilog -o ./sequential_trojan_min_synth.v
report_area > ./sequential_trojan_min_area.rpt
report_power > ./sequential_trojan_min_power.rpt
report_timing > ./sequential_trojan_min_timing.rpt
quit

