{"rule":"ENGLISH_WORD_REPEAT_BEGINNING_RULE","sentence":"^\\QUsing it as a development container in Visual Studio Code (or other IDEs)\\E$"}
{"rule":"UPPERCASE_SENTENCE_START","sentence":"^\\Qabc sequential logic synthesis and formal verification\namaranth a Python-based HDL toolchain\ncace a Python-based circuit automatic characterization engine\ncocotb simulation library for writing VHDL and Verilog test benches in Python\ncovered Verilog code coverage\ncvc circuit validity checker (ERC)\nedalize Python abstraction library for EDA tools\nfusesoc package manager and build tools for SoC\ngaw3-xschem waveform plot tool for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\ngds3d a 3D viewer for GDS files\ngdsfactory Python library for GDS generation\ngdspy Python module for the creation and manipulation of GDS files\ngf180mcu GlobalFoundries 180nm CMOS PDK\nghdl-yosys-plugin VHDL-plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nghdl VHDL simulator\ngtkwave waveform plot tool for digital simulation\nhdl21 analog hardware description library\nihp-sg13g2 IHP Microelectronics 130nm SiGe:C BiCMOS PDK (partial PDK, not fully supported yet; \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q simulation works incl.\\E$"}
{"rule":"UPPERCASE_SENTENCE_START","sentence":"^\\Qabc sequential logic synthesis and formal verification\namaranth a Python-based HDL tool chain\ncace a Python-based circuit automatic characterization engine\ncocotb simulation library for writing VHDL and Verilog test benches in Python\ncovered Verilog code coverage\ncvc circuit validity checker (ERC)\nedalize Python abstraction library for EDA tools\nfusesoc package manager and build tools for SoC\ngaw3-xschem waveform plot tool for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\ngds3d a 3D viewer for GDS files\ngdsfactory Python library for GDS generation\ngdspy Python module for the creation and manipulation of GDS files\ngf180mcu GlobalFoundries 180nm CMOS PDK\nghdl-yosys-plugin VHDL-plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nghdl VHDL simulator\ngtkwave waveform plot tool for digital simulation\nhdl21 analog hardware description library\nihp-sg13g2 IHP Microelectronics 130nm SiGe:C BiCMOS PDK (partial PDK, not fully supported yet; \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q simulation works incl.\\E$"}
{"rule":"UPPERCASE_SENTENCE_START","sentence":"^\\Qabc sequential logic synthesis and formal verification\namaranth a Python-based HDL tool chain\ncace a Python-based circuit automatic characterization engine\ncocotb simulation library for writing VHDL and Verilog test benches in Python\ncovered Verilog code coverage\ncvc circuit validity checker (ERC)\nedalize Python abstraction library for EDA tools\nfusesoc package manager and build tools for SoC\ngaw3-xschem waveform plot tool for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\ngds3d a 3D viewer for GDS files\ngdsfactory Python library for GDS generation\ngdspy Python module for the creation and manipulation of GDS files\ngf180mcu GlobalFoundries 180 nm CMOS PDK\nghdl-yosys-plugin VHDL-plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nghdl VHDL simulator\ngtkwave waveform plot tool for digital simulation\nhdl21 analog hardware description library\nihp-sg13g2 IHP Microelectronics 130nm SiGe:C BiCMOS PDK (partial PDK, not fully supported yet; \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q simulation works incl.\\E$"}
{"rule":"MORFOLOGIK_RULE_EN_US","sentence":"^\\Qabc sequential logic synthesis and formal verification\namaranth a Python-based HDL tool chain\ncace a Python-based circuit automatic characterization engine\ncocotb simulation library for writing VHDL and Verilog test benches in Python\ncovered Verilog code coverage\ncvc circuit validity checker (ERC)\nedalize Python abstraction library for EDA tools\nfusesoc package manager and build tools for SoC\ngaw3-xschem waveform plot tool for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\ngds3d a 3D viewer for GDS files\ngdsfactory Python library for GDS generation\ngdspy Python module for the creation and manipulation of GDS files\ngf180mcu GlobalFoundries 180 nm CMOS PDK\nghdl-yosys-plugin VHDL-plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nghdl VHDL simulator\ngtkwave waveform plot tool for digital simulation\nhdl21 analog hardware description library\nihp-sg13g2 IHP Microelectronics 130nm SiGe:C BiCMOS PDK (partial PDK, not fully supported yet; \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q simulation works incl.\\E$"}
{"rule":"UPPERCASE_SENTENCE_START","sentence":"^\\Qabc sequential logic synthesis and formal verification\namaranth a Python-based HDL tool chain\ncace a Python-based circuit automatic characterization engine\ncocotb simulation library for writing VHDL and Verilog test benches in Python\ncovered Verilog code coverage\ncvc circuit validity checker (ERC)\nedalize Python abstraction library for EDA tools\nfusesoc package manager and build tools for SoC\ngaw3-xschem waveform plot tool for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\ngds3d a 3D viewer for GDS files\ngdsfactory Python library for GDS generation\ngdspy Python module for the creation and manipulation of GDS files\ngf180mcu GlobalFoundries 180 nm CMOS PDK\nghdl-yosys-plugin VHDL-plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nghdl VHDL simulator\ngtkwave waveform plot tool for digital simulation\nhdl21 analog hardware description library\nihp-sg13g2 IHP Microelectronics 130 nm SiGe:C BiCMOS PDK (partial PDK, not fully supported yet; \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q simulation works incl.\\E$"}
{"rule":"MORFOLOGIK_RULE_EN_US","sentence":"^\\QPSP MOSFET model)\nirsim switch-level digital simulator\niverilog Verilog simulator\nklayout-pex parasitic extraction for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nklayout layout viewer and editor for GDS and OASIS\nlctime Characterization kit for CMOS cells\nlibman design library manager to manage cells and views\nmagic layout editor with DRC and PEX\nnetgen netlist comparison (LVS)\nngspice SPICE analog and mixed-signal simulator, with OSDI support\nngspyce Python bindings for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nnvc VHDL simulator and compiler\nopen_pdks PDK setup scripts\nopenlane2 rewrite of OpenLane in Python, 2nd generation\nopenram OpenRAM Python library\nopenroad RTL2GDS engine used by \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nopensta gate level static timing verifier\nopenvaf Verilog-A compiler for device models\nosic-multitool collection of useful scripts and documentation\npadring padring generation tool\npulp-tools PULP platform tools consisting of bender, morty, svase, verible, and sv2v\npygmid Python version of the gm/Id starter kit from Boris Murmann\npyopus simulation runner and optimization tool for analog circuits\npyrtl collection of classes for pythonic RTL design\npyspice interface \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q from Python\npyuvm Universal Verification Methodology implemented in Python (instead of SystemVerilog) using \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\npyverilog Python toolkit for Verilog\nqflow collection of useful conversion tools\nqucs-s simulation environment with RF emphasis\nrggen code generation tool for configuration and status registers\nrisc-v toolchain GNU compiler toolchain for RISC-V cores, incl.\\E$"}
{"rule":"ENGLISH_WORD_REPEAT_RULE","sentence":"^\\QPSP MOSFET model)\nirsim switch-level digital simulator\niverilog Verilog simulator\nklayout-pex parasitic extraction for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nklayout layout viewer and editor for GDS and OASIS\nlctime Characterization kit for CMOS cells\nlibman design library manager to manage cells and views\nmagic layout editor with DRC and PEX\nnetgen netlist comparison (LVS)\nngspice SPICE analog and mixed-signal simulator, with OSDI support\nngspyce Python bindings for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nnvc VHDL simulator and compiler\nopen_pdks PDK setup scripts\nopenlane2 rewrite of OpenLane in Python, 2nd generation\nopenram OpenRAM Python library\nopenroad RTL2GDS engine used by \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nopensta gate level static timing verifier\nopenvaf Verilog-A compiler for device models\nosic-multitool collection of useful scripts and documentation\npadring padring generation tool\npulp-tools PULP platform tools consisting of bender, morty, svase, verible, and sv2v\npygmid Python version of the gm/Id starter kit from Boris Murmann\npyopus simulation runner and optimization tool for analog circuits\npyrtl collection of classes for pythonic RTL design\npyspice interface \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q from Python\npyuvm Universal Verification Methodology implemented in Python (instead of SystemVerilog) using \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\npyverilog Python toolkit for Verilog\nqflow collection of useful conversion tools\nqucs-s simulation environment with RF emphasis\nrggen code generation tool for configuration and status registers\nrisc-v toolchain GNU compiler toolchain for RISC-V cores, incl.\\E$"}
{"rule":"MORFOLOGIK_RULE_EN_US","sentence":"^\\QPSP MOSFET model)\nirsim switch-level digital simulator\niverilog Verilog simulator\nklayout-pex parasitic extraction for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nklayout layout viewer and editor for GDS and OASIS\nlctime Characterization kit for CMOS cells\nlibman design library manager to manage cells and views\nmagic layout editor with DRC and PEX\nnetgen netlist comparison (LVS)\nngspice SPICE analog and mixed-signal simulator, with OSDI support\nngspyce Python bindings for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nnvc VHDL simulator and compiler\nopen_pdks PDK setup scripts\nopenlane2 rewrite of OpenLane in Python, 2nd generation\nopenram OpenRAM Python library\nopenroad RTL2GDS engine used by \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nopensta gate level static timing verifier\nopenvaf Verilog-A compiler for device models\nosic-multitool collection of useful scripts and documentation\npadring padring generation tool\npulp-tools PULP platform tools consisting of bender, morty, svase, verible, and sv2v\npygmid Python version of the gm/Id starter kit from Boris Murmann\npyopus simulation runner and optimization tool for analog circuits\npyrtl collection of classes for pythonic RTL design\npyspice interface \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q from Python\npyuvm Universal Verification Methodology implemented in Python (instead of SystemVerilog) using \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\npyverilog Python toolkit for Verilog\nqflow collection of useful conversion tools\nqucs-s simulation environment with RF emphasis\nrggen code generation tool for configuration and status registers\nrisc-v toolchain GNU compiler toolchain for RISC-V cores, incl.\\E$"}
{"rule":"ENGLISH_WORD_REPEAT_RULE","sentence":"^\\QPSP MOSFET model)\nirsim switch-level digital simulator\niverilog Verilog simulator\nklayout-pex parasitic extraction for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nklayout layout viewer and editor for GDS and OASIS\nlctime Characterization kit for CMOS cells\nlibman design library manager to manage cells and views\nmagic layout editor with DRC and PEX\nnetgen netlist comparison (LVS)\nngspice SPICE analog and mixed-signal simulator, with OSDI support\nngspyce Python bindings for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nnvc VHDL simulator and compiler\nopen_pdks PDK setup scripts\nopenlane2 rewrite of OpenLane in Python, 2nd generation\nopenram OpenRAM Python library\nopenroad RTL2GDS engine used by \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nopensta gate level static timing verifier\nopenvaf Verilog-A compiler for device models\nosic-multitool collection of useful scripts and documentation\npadring padring generation tool\npulp-tools PULP platform tools consisting of bender, morty, svase, verible, and sv2v\npygmid Python version of the gm/Id starter kit from Boris Murmann\npyopus simulation runner and optimization tool for analog circuits\npyrtl collection of classes for pythonic RTL design\npyspice interface \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q from Python\npyuvm Universal Verification Methodology implemented in Python (instead of SystemVerilog) using \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\npyverilog Python toolkit for Verilog\nqflow collection of useful conversion tools\nqucs-s simulation environment with RF emphasis\nrggen code generation tool for configuration and status registers\nrisc-v toolchain GNU compiler toolchain for RISC-V cores, incl.\\E$"}
{"rule":"MORFOLOGIK_RULE_EN_US","sentence":"^\\QPSP MOSFET model)\nirsim switch-level digital simulator\niverilog Verilog simulator\nklayout-pex parasitic extraction for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nklayout layout viewer and editor for GDS and OASIS\nlctime Characterization kit for CMOS cells\nlibman design library manager to manage cells and views\nmagic layout editor with DRC and PEX\nnetgen netlist comparison (LVS)\nngspice SPICE analog and mixed-signal simulator, with OSDI support\nngspyce Python bindings for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nnvc VHDL simulator and compiler\nopen_pdks PDK setup scripts\nopenlane2 rewrite of OpenLane in Python, 2nd generation\nopenram OpenRAM Python library\nopenroad RTL2GDS engine used by \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nopensta gate level static timing verifier\nopenvaf Verilog-A compiler for device models\nosic-multitool collection of useful scripts and documentation\npadring padring generation tool\npulp-tools PULP platform tools consisting of bender, morty, svase, verible, and sv2v\npygmid Python version of the gm/Id starter kit from Boris Murmann\npyopus simulation runner and optimization tool for analog circuits\npyrtl collection of classes for pythonic RTL design\npyspice interface \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q from Python\npyuvm Universal Verification Methodology implemented in Python (instead of SystemVerilog) using \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\npyverilog Python toolkit for Verilog\nqflow collection of useful conversion tools\nqucs-s simulation environment with RF emphasis\nrggen code generation tool for configuration and status registers\nrisc-v toolchain GNU compiler toolchain for RISC-V cores, incl.\\E$"}
{"rule":"EN_CONTRACTION_SPELLING","sentence":"^\\QPSP MOSFET model)\nirsim switch-level digital simulator\niverilog Verilog simulator\nklayout-pex parasitic extraction for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nklayout layout viewer and editor for GDS and OASIS\nlctime Characterization kit for CMOS cells\nlibman design library manager to manage cells and views\nmagic layout editor with DRC and PEX\nnetgen netlist comparison (LVS)\nngspice SPICE analog and mixed-signal simulator, with OSDI support\nngspyce Python bindings for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nnvc VHDL simulator and compiler\nopen_pdks PDK setup scripts\nopenlane2 rewrite of OpenLane in Python, 2nd generation\nopenram OpenRAM Python library\nopenroad RTL2GDS engine used by \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\nopensta gate level static timing verifier\nopenvaf Verilog-A compiler for device models\nosic-multitool collection of useful scripts and documentation\npadring padring generation tool\npulp-tools PULP platform tools consisting of bender, morty, svase, verible, and sv2v\npygmid Python version of the gm/Id starter kit from Boris Murmann\npyopus simulation runner and optimization tool for analog circuits\npyrtl collection of classes for pythonic RTL design\npyspice interface \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q and \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q from Python\npyuvm Universal Verification Methodology implemented in Python (instead of SystemVerilog) using \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q\npyverilog Python toolkit for Verilog\nqflow collection of useful conversion tools\nqucs-s simulation environment with RF emphasis\nrggen code generation tool for configuration and status registers\nrisc-v toolchain GNU compiler toolchain for RISC-V cores, incl.\\E$"}
{"rule":"MORFOLOGIK_RULE_EN_US","sentence":"^\\QSpike RISC-V ISA simulator\nriscv-pk RISC-V proxy kernel and boot loader\nschemdraw Python package for drawing electrical schematics\nsiliconcompiler modular build system for hardware\nsky130 SkyWater Technologies 130nm CMOS PDK\nslang yosys plugin Slang-based plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q for SystemVerilog support\nslang SystemVerilog parsing and translation (e.g. to Verilog)\nspicelib library to interact with SPICCE-like simulators\nspyci analyze/plot \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q/\\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q output data with Python\nsurelog SystemVerilog parser, elaborator, and UHDM compiler\nsurfer waveform viewer with snappy usable interface and extensibility\nverilator fast Verilog simulator\nvlog2verilog Verilog file conversion\nvlsirtools interchange formats for chip design.\\E$"}
{"rule":"MORFOLOGIK_RULE_EN_US","sentence":"^\\QSpike RISC-V ISA simulator\nriscv-pk RISC-V proxy kernel and bootloader\nschemdraw Python package for drawing electrical schematics\nsiliconcompiler modular build system for hardware\nsky130 SkyWater Technologies 130nm CMOS PDK\nslang yosys plugin Slang-based plugin for \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q for SystemVerilog support\nslang SystemVerilog parsing and translation (e.g. to Verilog)\nspicelib library to interact with SPICCE-like simulators\nspyci analyze/plot \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q/\\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q output data with Python\nsurelog SystemVerilog parser, elaborator, and UHDM compiler\nsurfer waveform viewer with snappy usable interface and extensibility\nverilator fast Verilog simulator\nvlog2verilog Verilog file conversion\nvlsirtools interchange formats for chip design.\\E$"}
{"rule":"UPPERCASE_SENTENCE_START","sentence":"^\\Qvolare version manager (and builder) for open-source PDKs\nxcircuit schematic editor\nxschem schematic editor\nxyce fast parallel SPICE simulator (incl. \\E(?:Dummy|Ina|Jimmy-)[0-9]+\\Q netlist conversion tool)\nyosys Verilog synthesis tool (with GHDL plugin for VHDL synthesis and Slang plugin for SystemVerilog synthesis), incl.\\E$"}
