
$(HOME)/cheri/benchmarks/risc_oblivious_hybrid/matrix_mult_12.o:	file format elf64-littleriscv

Disassembly of section .text:

0000000000011840 <__start>:
; {
   11840: 5d 71        	addi	sp, sp, -80
; 	if (&_DYNAMIC == NULL) {
   11842: 86 e4        	sd	ra, 72(sp)
   11844: a2 e0        	sd	s0, 64(sp)
   11846: 26 fc        	sd	s1, 56(sp)
   11848: 4a f8        	sd	s2, 48(sp)
   1184a: 4e f4        	sd	s3, 40(sp)
   1184c: 52 f0        	sd	s4, 32(sp)
   1184e: 56 ec        	sd	s5, 24(sp)
   11850: 5a e8        	sd	s6, 16(sp)
   11852: 5e e4        	sd	s7, 8(sp)
   11854: 80 08        	addi	s0, sp, 80
   11856: 37 37 01 00  	lui	a4, 19
   1185a: 13 07 07 e8  	addi	a4, a4, -384
   1185e: 63 1f 07 20  	bnez	a4, 0x11a7c <__start+0x23c>
; 		while (*strp++ != NULL)
   11862: 93 04 86 00  	addi	s1, a2, 8
   11866: 03 b7 84 ff  	ld	a4, -8(s1)
   1186a: a1 04        	addi	s1, s1, 8
   1186c: 6d ff        	bnez	a4, 0x11866 <__start+0x26>
   1186e: 81 4a        	li	s5, 0
   11870: 81 48        	li	a7, 0
   11872: 0d 47        	li	a4, 3
   11874: 15 48        	li	a6, 5
; 		for (; auxp->a_type != AT_NULL; auxp++) {
   11876: 83 b7 84 ff  	ld	a5, -8(s1)
   1187a: 63 91 e7 02  	bne	a5, a4, 0x1189c <__start+0x5c>
   1187e: 01 a8        	j	0x1188e <__start+0x4e>
; 				phnum = auxp->a_un.a_val;
   11880: 83 b8 04 00  	ld	a7, 0(s1)
; 		for (; auxp->a_type != AT_NULL; auxp++) {
   11884: c1 04        	addi	s1, s1, 16
   11886: 83 b7 84 ff  	ld	a5, -8(s1)
   1188a: 63 99 e7 00  	bne	a5, a4, 0x1189c <__start+0x5c>
; 				phdr = auxp->a_un.a_ptr;
   1188e: 83 ba 04 00  	ld	s5, 0(s1)
; 		for (; auxp->a_type != AT_NULL; auxp++) {
   11892: c1 04        	addi	s1, s1, 16
   11894: 83 b7 84 ff  	ld	a5, -8(s1)
   11898: e3 8b e7 fe  	beq	a5, a4, 0x1188e <__start+0x4e>
   1189c: e3 82 07 ff  	beq	a5, a6, 0x11880 <__start+0x40>
   118a0: f5 f3        	bnez	a5, 0x11884 <__start+0x44>
; 		if (phdr != NULL && phnum != 0) {
   118a2: 33 37 50 01  	snez	a4, s5
   118a6: b3 37 10 01  	snez	a5, a7
   118aa: 7d 8f        	and	a4, a4, a5
   118ac: 63 08 07 1c  	beqz	a4, 0x11a7c <__start+0x23c>
   118b0: 63 5e 10 1d  	blez	a7, 0x11a8c <__start+0x24c>
   118b4: 81 42        	li	t0, 0
   118b6: 01 4e        	li	t3, 0
   118b8: 81 49        	li	s3, 0
   118ba: 81 4e        	li	t4, 0
   118bc: 01 43        	li	t1, 0
   118be: 01 48        	li	a6, 0
   118c0: 13 07 80 03  	li	a4, 56
   118c4: 33 87 e8 02  	mul	a4, a7, a4
   118c8: 33 8b ea 00  	add	s6, s5, a4
   118cc: fd 53        	li	t2, -1
   118ce: 85 4f        	li	t6, 1
   118d0: 37 e7 74 64  	lui	a4, 411470
   118d4: 1b 0a 27 55  	addiw	s4, a4, 1362
   118d8: 09 49        	li	s2, 2
   118da: fd 58        	li	a7, -1
   118dc: 7d 5f        	li	t5, -1
   118de: 39 a0        	j	0x118ec <__start+0xac>
   118e0: 63 86 27 1b  	beq	a5, s2, 0x11a8c <__start+0x24c>
; 	for (const Elf_Phdr *ph = phdr; ph < phlimit; ph++) {
   118e4: 93 8a 8a 03  	addi	s5, s5, 56
   118e8: 63 f1 6a 07  	bgeu	s5, s6, 0x1194a <__start+0x10a>
; 		if (ph->p_type != PT_LOAD && ph->p_type != PT_GNU_RELRO) {
   118ec: 83 a7 0a 00  	lw	a5, 0(s5)
   118f0: 63 84 f7 01  	beq	a5, t6, 0x118f8 <__start+0xb8>
   118f4: e3 96 47 ff  	bne	a5, s4, 0x118e0 <__start+0xa0>
; 		Elf_Addr seg_start = ph->p_vaddr;
   118f8: 83 b7 0a 01  	ld	a5, 16(s5)
; 		if ((ph->p_flags & PF_X)) {
   118fc: 03 e7 4a 00  	lwu	a4, 4(s5)
; 		Elf_Addr seg_end = seg_start + ph->p_memsz;
   11900: 83 b4 8a 02  	ld	s1, 40(s5)
; 		if ((ph->p_flags & PF_X)) {
   11904: 93 7b 17 00  	andi	s7, a4, 1
; 		Elf_Addr seg_end = seg_start + ph->p_memsz;
   11908: be 94        	add	s1, s1, a5
; 		if ((ph->p_flags & PF_X)) {
   1190a: 63 94 0b 02  	bnez	s7, 0x11932 <__start+0xf2>
; 		} else if ((ph->p_flags & PF_W)) {
   1190e: 09 8b        	andi	a4, a4, 2
   11910: 09 eb        	bnez	a4, 0x11922 <__start+0xe2>
; 			readonly_start = MIN(readonly_start, seg_start);
   11912: 63 e3 f8 00  	bltu	a7, a5, 0x11918 <__start+0xd8>
   11916: be 88        	mv	a7, a5
; 			readonly_end = MAX(readonly_end, seg_end);
   11918: 63 e3 04 01  	bltu	s1, a6, 0x1191e <__start+0xde>
   1191c: 26 88        	mv	a6, s1
   1191e: 85 4e        	li	t4, 1
   11920: d1 b7        	j	0x118e4 <__start+0xa4>
; 			writable_start = MIN(writable_start, seg_start);
   11922: 63 63 ff 00  	bltu	t5, a5, 0x11928 <__start+0xe8>
   11926: 3e 8f        	mv	t5, a5
; 			writable_end = MAX(writable_end, seg_end);
   11928: 63 e3 64 00  	bltu	s1, t1, 0x1192e <__start+0xee>
   1192c: 26 83        	mv	t1, s1
   1192e: 05 4e        	li	t3, 1
   11930: 55 bf        	j	0x118e4 <__start+0xa4>
; 			text_start = MIN(text_start, seg_start);
   11932: 63 e3 f3 00  	bltu	t2, a5, 0x11938 <__start+0xf8>
   11936: be 83        	mv	t2, a5
; 			text_end = MAX(text_end, seg_end);
   11938: 63 e3 54 00  	bltu	s1, t0, 0x1193e <__start+0xfe>
   1193c: a6 82        	mv	t0, s1
; 	for (const Elf_Phdr *ph = phdr; ph < phlimit; ph++) {
   1193e: 93 8a 8a 03  	addi	s5, s5, 56
   11942: 85 49        	li	s3, 1
; 	for (const Elf_Phdr *ph = phdr; ph < phlimit; ph++) {
   11944: e3 e4 6a fb  	bltu	s5, s6, 0x118ec <__start+0xac>
   11948: 29 a0        	j	0x11952 <__start+0x112>
; 	if (!have_text_segment) {
   1194a: 13 f7 19 00  	andi	a4, s3, 1
   1194e: 63 0f 07 12  	beqz	a4, 0x11a8c <__start+0x24c>
; 	if (!have_rodata_segment) {
   11952: 13 f7 1e 00  	andi	a4, t4, 1
   11956: 19 e3        	bnez	a4, 0x1195c <__start+0x11c>
   11958: 16 88        	mv	a6, t0
   1195a: 9e 88        	mv	a7, t2
; 	if (!have_data_segment) {
   1195c: 13 77 1e 00  	andi	a4, t3, 1
   11960: db 07 a0 fe  	cmove	ca5, cnull
   11964: 5b 0e a0 fe  	cmove	ct3, cnull
   11968: db 0e a0 fe  	cmove	ct4, cnull
   1196c: 2d cf        	beqz	a4, 0x119e6 <__start+0x1a6>
; 		if (writable_end < writable_start ||
   1196e: 33 37 e3 01  	sltu	a4, t1, t5
   11972: b3 37 18 01  	sltu	a5, a6, a7
   11976: 5d 8f        	or	a4, a4, a5
   11978: b3 b7 72 00  	sltu	a5, t0, t2
   1197c: 5d 8f        	or	a4, a4, a5
   1197e: 63 17 07 10  	bnez	a4, 0x11a8c <__start+0x24c>
   11982: 7a 87        	mv	a4, t5
; 		if (MAX(writable_start, text_start) <
   11984: 63 f8 e3 01  	bgeu	t2, t5, 0x11994 <__start+0x154>
   11988: 9a 87        	mv	a5, t1
; 		    MIN(writable_end, text_end)) {
   1198a: 63 79 53 00  	bgeu	t1, t0, 0x1199c <__start+0x15c>
; 		if (MAX(writable_start, text_start) <
   1198e: 63 7a f7 00  	bgeu	a4, a5, 0x119a2 <__start+0x162>
   11992: ed a8        	j	0x11a8c <__start+0x24c>
   11994: 1e 87        	mv	a4, t2
   11996: 9a 87        	mv	a5, t1
; 		    MIN(writable_end, text_end)) {
   11998: e3 6b 53 fe  	bltu	t1, t0, 0x1198e <__start+0x14e>
   1199c: 96 87        	mv	a5, t0
; 		if (MAX(writable_start, text_start) <
   1199e: 63 67 f7 0e  	bltu	a4, a5, 0x11a8c <__start+0x24c>
; 		data_cap = cheri_getdefault();
   119a2: db 07 10 02  	cspecialr	ca5, ddc
   119a6: 41 77        	lui	a4, 1048560
   119a8: 9b 04 d7 ff  	addiw	s1, a4, -3
; 		data_cap = cheri_clearperm(data_cap,
   119ac: db 82 97 1a  	candperm	ct0, ca5, s1
; 		data_cap = cheri_setaddress(data_cap, writable_start);
   119b0: db 87 e2 21  	csetaddr	ca5, ct0, t5
; 		    cheri_setbounds(data_cap, writable_end - writable_start);
   119b4: b3 04 e3 41  	sub	s1, t1, t5
   119b8: db 87 97 10  	csetbounds	ca5, ca5, s1
; 		if (!cheri_gettag(data_cap))
   119bc: db 84 47 fe  	cgettag	s1, ca5
; 		code_cap = cheri_getpcc();
   119c0: 5b 0e 00 02  	cspecialr	ct3, pcc
; 		if (!cheri_gettag(data_cap))
   119c4: e1 c4        	beqz	s1, 0x11a8c <__start+0x24c>
   119c6: 1b 07 77 f9  	addiw	a4, a4, -105
   119ca: 5b 87 e2 1a  	candperm	ca4, ct0, a4
   119ce: 5b 07 17 21  	csetaddr	ca4, ca4, a7
   119d2: b3 04 18 41  	sub	s1, a6, a7
   119d6: db 0e 97 10  	csetbounds	ct4, ca4, s1
; 		if (!cheri_gettag(rodata_cap))
   119da: 5b 87 4e fe  	cgettag	a4, ct4
   119de: 5d c7        	beqz	a4, 0x11a8c <__start+0x24c>
; 		if (!cheri_gettag(code_cap))
   119e0: 5b 07 4e fe  	cgettag	a4, ct3
   119e4: 45 c7        	beqz	a4, 0x11a8c <__start+0x24c>
;   __asm__("lla %0, __start___cap_relocs\n\t"
   119e6: 17 e7 fe ff  	auipc	a4, 1048558
   119ea: 13 07 a7 61  	addi	a4, a4, 1562
   119ee: 17 e3 fe ff  	auipc	t1, 1048558
   119f2: 13 03 23 61  	addi	t1, t1, 1554
;   for (const struct capreloc *reloc = start_relocs; reloc < stop_relocs;
   119f6: 63 73 67 08  	bgeu	a4, t1, 0x11a7c <__start+0x23c>
   119fa: 93 04 d0 f7  	li	s1, -131
   119fe: db 83 97 1a  	candperm	ct2, ca5, s1
   11a02: 93 07 70 f5  	li	a5, -169
   11a06: 5b 08 fe 1a  	candperm	ca6, ct3, a5
   11a0a: 93 07 50 f1  	li	a5, -235
   11a0e: db 88 fe 1a  	candperm	ca7, ct4, a5
;   for (const struct capreloc *reloc = start_relocs; reloc < stop_relocs;
   11a12: 93 04 07 01  	addi	s1, a4, 16
   11a16: 0d a0        	j	0x11a38 <__start+0x1f8>
   11a18: db 02 a0 fe  	cmove	ct0, cnull
   11a1c: 83 b7 04 ff  	ld	a5, -16(s1)
   11a20: 13 87 04 ff  	addi	a4, s1, -16
   11a24: db 87 f3 20  	csetaddr	ca5, ct2, a5
   11a28: 5b 86 57 f8  	sc.cap	ct0, (ca5)
;   for (const struct capreloc *reloc = start_relocs; reloc < stop_relocs;
   11a2c: 13 07 87 02  	addi	a4, a4, 40
   11a30: 93 84 84 02  	addi	s1, s1, 40
   11a34: 63 74 67 04  	bgeu	a4, t1, 0x11a7c <__start+0x23c>
;     if (reloc->object == 0) {
   11a38: 03 b7 84 ff  	ld	a4, -8(s1)
   11a3c: 71 df        	beqz	a4, 0x11a18 <__start+0x1d8>
;     if ((reloc->permissions & function_reloc_flag) == function_reloc_flag) {
   11a3e: 9c 68        	ld	a5, 16(s1)
   11a40: db 02 a8 fe  	cmove	ct0, ca6
   11a44: 63 ca 07 00  	bltz	a5, 0x11a58 <__start+0x218>
   11a48: 13 9e 17 00  	slli	t3, a5, 1
   11a4c: db 82 a3 fe  	cmove	ct0, ct2
   11a50: 63 54 0e 00  	bgez	t3, 0x11a58 <__start+0x218>
   11a54: db 82 a8 fe  	cmove	ct0, ca7
;         cheri_address_or_offset_set(base_cap, reloc->object + base_addr);
   11a58: db 82 e2 20  	csetaddr	ct0, ct0, a4
;     if (can_set_bounds && (reloc->size != 0)) {
   11a5c: 63 ca 07 00  	bltz	a5, 0x11a70 <__start+0x230>
   11a60: 98 64        	ld	a4, 8(s1)
   11a62: 19 c3        	beqz	a4, 0x11a68 <__start+0x228>
;       src = __builtin_cheri_bounds_set(src, reloc->size);
   11a64: db 82 e2 10  	csetbounds	ct0, ct0, a4
;     src = __builtin_cheri_offset_increment(src, reloc->offset);
   11a68: 98 60        	ld	a4, 0(s1)
   11a6a: db 82 e2 22  	cincoffset	ct0, ct0, a4
   11a6e: 7d b7        	j	0x11a1c <__start+0x1dc>
;     src = __builtin_cheri_offset_increment(src, reloc->offset);
   11a70: 98 60        	ld	a4, 0(s1)
   11a72: 5b 87 e2 22  	cincoffset	ca4, ct0, a4
;       src = __builtin_cheri_seal_entry(src);
   11a76: db 02 17 ff  	csealentry	ct0, ca4
   11a7a: 4d b7        	j	0x11a1c <__start+0x1dc>
; 	__libc_start1(argc, argv, env, cleanup, main);
   11a7c: 37 27 01 00  	lui	a4, 18
   11a80: 13 07 87 c4  	addi	a4, a4, -952
   11a84: 97 00 00 00  	auipc	ra, 0
   11a88: e7 80 c0 34  	jalr	844(ra)
   11a8c: 00 00        	unimp	
   11a8e: 00 00        	unimp	

0000000000011a90 <_start>:
; 	mv	a3, a2		# cleanup
   11a90: b2 86        	mv	a3, a2
; 	addi	a1, a0, 8	# get argv
   11a92: 93 05 85 00  	addi	a1, a0, 8
; 	ld	a0, 0(a0)	# load argc
   11a96: 08 61        	ld	a0, 0(a0)
; 	slli	t0, a0, 3	# mult by arg size
   11a98: 93 12 35 00  	slli	t0, a0, 3
; 	add	a2, a1, t0	# env is after argv
   11a9c: 33 86 55 00  	add	a2, a1, t0
; 	addi	a2, a2, 8	# argv is null terminated
   11aa0: 21 06        	addi	a2, a2, 8
; 	lla	gp, __global_pointer$
   11aa2: 97 31 00 00  	auipc	gp, 3
   11aa6: 93 81 e1 d1  	addi	gp, gp, -738
; 	call	__start
   11aaa: 97 00 00 00  	auipc	ra, 0
   11aae: e7 80 60 d9  	jalr	-618(ra)
   11ab2: 00 00        	unimp	

0000000000011ab4 <__do_global_dtors_aux>:
; {
   11ab4: 01 11        	addi	sp, sp, -32
   11ab6: 06 ec        	sd	ra, 24(sp)
   11ab8: 22 e8        	sd	s0, 16(sp)
   11aba: 26 e4        	sd	s1, 8(sp)
   11abc: 4a e0        	sd	s2, 0(sp)
   11abe: 00 10        	addi	s0, sp, 32
   11ac0: 37 35 01 00  	lui	a0, 19
   11ac4: 93 04 85 e6  	addi	s1, a0, -408
   11ac8: 09 49        	li	s2, 2
; 		fn = __DTOR_LIST__[n];
   11aca: 88 60        	ld	a0, 0(s1)
; 		if (fn == (crt_func)0 || fn == (crt_func)-1)
   11acc: 93 05 15 00  	addi	a1, a0, 1
   11ad0: 63 e5 25 01  	bltu	a1, s2, 0x11ada <__do_global_dtors_aux+0x26>
; 		fn();
   11ad4: 02 95        	jalr	a0
; 	for (n = 1;; n++) {
   11ad6: a1 04        	addi	s1, s1, 8
   11ad8: cd bf        	j	0x11aca <__do_global_dtors_aux+0x16>
; }
   11ada: e2 60        	ld	ra, 24(sp)
   11adc: 42 64        	ld	s0, 16(sp)
   11ade: a2 64        	ld	s1, 8(sp)
   11ae0: 02 69        	ld	s2, 0(sp)
   11ae2: 05 61        	addi	sp, sp, 32
   11ae4: 82 80        	ret

0000000000011ae6 <register_classes>:
; {
   11ae6: 41 11        	addi	sp, sp, -16
; 	if (_Jv_RegisterClasses != NULL && __JCR_LIST__[0] != 0)
   11ae8: 06 e4        	sd	ra, 8(sp)
   11aea: 22 e0        	sd	s0, 0(sp)
   11aec: 00 08        	addi	s0, sp, 16
   11aee: 37 05 00 00  	lui	a0, 0
   11af2: 13 05 05 00  	mv	a0, a0
   11af6: 01 cd        	beqz	a0, 0x11b0e <register_classes+0x28>
   11af8: 37 35 01 00  	lui	a0, 19
   11afc: 83 35 05 e7  	ld	a1, -400(a0)
   11b00: 99 c5        	beqz	a1, 0x11b0e <register_classes+0x28>
; 		_Jv_RegisterClasses(__JCR_LIST__);
   11b02: 13 05 05 e7  	addi	a0, a0, -400
   11b06: 97 00 00 00  	auipc	ra, 0
   11b0a: e7 80 a0 2d  	jalr	730(ra)
; }
   11b0e: a2 60        	ld	ra, 8(sp)
   11b10: 02 64        	ld	s0, 0(sp)
   11b12: 41 01        	addi	sp, sp, 16
   11b14: 82 80        	ret
   11b16: 00 00        	unimp	

0000000000011b18 <MatrixMult>:
   11b18: 01 48        	li	a6, 0
   11b1a: 13 0e 00 10  	li	t3, 256
   11b1e: 93 08 00 04  	li	a7, 64
   11b22: 81 43        	li	t2, 0
   11b24: 93 12 68 00  	slli	t0, a6, 6
   11b28: 2e 83        	mv	t1, a1
   11b2a: b3 86 53 00  	add	a3, t2, t0
   11b2e: 8a 06        	slli	a3, a3, 2
   11b30: b3 0e d6 00  	add	t4, a2, a3
   11b34: 03 af 0e 00  	lw	t5, 0(t4)
   11b38: 01 47        	li	a4, 0
   11b3a: 9a 87        	mv	a5, t1
   11b3c: b3 06 e5 00  	add	a3, a0, a4
   11b40: 83 af 06 00  	lw	t6, 0(a3)
   11b44: 94 43        	lw	a3, 0(a5)
   11b46: bb 86 f6 03  	mulw	a3, a3, t6
   11b4a: 3b 0f df 00  	addw	t5, t5, a3
   11b4e: 23 a0 ee 01  	sw	t5, 0(t4)
   11b52: 11 07        	addi	a4, a4, 4
   11b54: 93 87 07 10  	addi	a5, a5, 256
   11b58: e3 12 c7 ff  	bne	a4, t3, 0x11b3c <MatrixMult+0x24>
   11b5c: 85 03        	addi	t2, t2, 1
   11b5e: 11 03        	addi	t1, t1, 4
   11b60: e3 95 13 fd  	bne	t2, a7, 0x11b2a <MatrixMult+0x12>
   11b64: 05 08        	addi	a6, a6, 1
   11b66: 13 05 05 10  	addi	a0, a0, 256
   11b6a: e3 1c 18 fb  	bne	a6, a7, 0x11b22 <MatrixMult+0xa>
   11b6e: 82 80        	ret

0000000000011b70 <InitMatrix>:
   11b70: 01 11        	addi	sp, sp, -32
   11b72: 06 ec        	sd	ra, 24(sp)
   11b74: 22 e8        	sd	s0, 16(sp)
   11b76: 26 e4        	sd	s1, 8(sp)
   11b78: 4a e0        	sd	s2, 0(sp)
   11b7a: bb 04 b6 02  	mulw	s1, a2, a1
   11b7e: 63 5a 90 02  	blez	s1, 0x11bb2 <InitMatrix+0x42>
   11b82: 2a 84        	mv	s0, a0
   11b84: 37 95 e3 38  	lui	a0, 233017
   11b88: 1b 09 95 e3  	addiw	s2, a0, -455
   11b8c: 97 00 00 00  	auipc	ra, 0
   11b90: e7 80 40 26  	jalr	612(ra)
   11b94: b3 05 25 03  	mul	a1, a0, s2
   11b98: 13 d6 f5 03  	srli	a2, a1, 63
   11b9c: 85 95        	srai	a1, a1, 33
   11b9e: b1 9d        	addw	a1, a1, a2
   11ba0: 1b 96 35 00  	slliw	a2, a1, 3
   11ba4: b1 9d        	addw	a1, a1, a2
   11ba6: 0d 9d        	subw	a0, a0, a1
   11ba8: 05 25        	addiw	a0, a0, 1
   11baa: 08 c0        	sw	a0, 0(s0)
   11bac: fd 14        	addi	s1, s1, -1
   11bae: 11 04        	addi	s0, s0, 4
   11bb0: f1 fc        	bnez	s1, 0x11b8c <InitMatrix+0x1c>
   11bb2: e2 60        	ld	ra, 24(sp)
   11bb4: 42 64        	ld	s0, 16(sp)
   11bb6: a2 64        	ld	s1, 8(sp)
   11bb8: 02 69        	ld	s2, 0(sp)
   11bba: 05 61        	addi	sp, sp, 32
   11bbc: 82 80        	ret

0000000000011bbe <PrintMatrix>:
   11bbe: 5d 71        	addi	sp, sp, -80
   11bc0: 86 e4        	sd	ra, 72(sp)
   11bc2: a2 e0        	sd	s0, 64(sp)
   11bc4: 26 fc        	sd	s1, 56(sp)
   11bc6: 4a f8        	sd	s2, 48(sp)
   11bc8: 4e f4        	sd	s3, 40(sp)
   11bca: 52 f0        	sd	s4, 32(sp)
   11bcc: 56 ec        	sd	s5, 24(sp)
   11bce: 5a e8        	sd	s6, 16(sp)
   11bd0: 5e e4        	sd	s7, 8(sp)
   11bd2: 63 50 b0 06  	blez	a1, 0x11c32 <PrintMatrix+0x74>
   11bd6: b2 89        	mv	s3, a2
   11bd8: 2e 89        	mv	s2, a1
   11bda: 63 53 c0 04  	blez	a2, 0x11c20 <PrintMatrix+0x62>
   11bde: 2a 8a        	mv	s4, a0
   11be0: 01 4b        	li	s6, 0
   11be2: 13 15 09 02  	slli	a0, s2, 32
   11be6: 13 59 05 02  	srli	s2, a0, 32
   11bea: 93 9a 29 00  	slli	s5, s3, 2
   11bee: 97 fb ff ff  	auipc	s7, 1048575
   11bf2: 93 8b ab a8  	addi	s7, s7, -1398
   11bf6: ce 84        	mv	s1, s3
   11bf8: 52 84        	mv	s0, s4
   11bfa: 0c 40        	lw	a1, 0(s0)
   11bfc: 5e 85        	mv	a0, s7
   11bfe: 97 00 00 00  	auipc	ra, 0
   11c02: e7 80 20 20  	jalr	514(ra)
   11c06: fd 14        	addi	s1, s1, -1
   11c08: 11 04        	addi	s0, s0, 4
   11c0a: e5 f8        	bnez	s1, 0x11bfa <PrintMatrix+0x3c>
   11c0c: 29 45        	li	a0, 10
   11c0e: 97 00 00 00  	auipc	ra, 0
   11c12: e7 80 20 20  	jalr	514(ra)
   11c16: 05 0b        	addi	s6, s6, 1
   11c18: 56 9a        	add	s4, s4, s5
   11c1a: e3 1e 2b fd  	bne	s6, s2, 0x11bf6 <PrintMatrix+0x38>
   11c1e: 11 a8        	j	0x11c32 <PrintMatrix+0x74>
   11c20: 01 44        	li	s0, 0
   11c22: 29 45        	li	a0, 10
   11c24: 97 00 00 00  	auipc	ra, 0
   11c28: e7 80 c0 1e  	jalr	492(ra)
   11c2c: 05 24        	addiw	s0, s0, 1
   11c2e: e3 4a 24 ff  	blt	s0, s2, 0x11c22 <PrintMatrix+0x64>
   11c32: a6 60        	ld	ra, 72(sp)
   11c34: 06 64        	ld	s0, 64(sp)
   11c36: e2 74        	ld	s1, 56(sp)
   11c38: 42 79        	ld	s2, 48(sp)
   11c3a: a2 79        	ld	s3, 40(sp)
   11c3c: 02 7a        	ld	s4, 32(sp)
   11c3e: e2 6a        	ld	s5, 24(sp)
   11c40: 42 6b        	ld	s6, 16(sp)
   11c42: a2 6b        	ld	s7, 8(sp)
   11c44: 61 61        	addi	sp, sp, 80
   11c46: 82 80        	ret

0000000000011c48 <main>:
   11c48: 79 71        	addi	sp, sp, -48
   11c4a: 06 f4        	sd	ra, 40(sp)
   11c4c: 22 f0        	sd	s0, 32(sp)
   11c4e: 26 ec        	sd	s1, 24(sp)
   11c50: 4a e8        	sd	s2, 16(sp)
   11c52: 4e e4        	sd	s3, 8(sp)
   11c54: 52 e0        	sd	s4, 0(sp)
   11c56: 11 65        	lui	a0, 4
   11c58: 11 69        	lui	s2, 4
   11c5a: 97 00 00 00  	auipc	ra, 0
   11c5e: e7 80 60 1c  	jalr	454(ra)
   11c62: aa 89        	mv	s3, a0
   11c64: 81 44        	li	s1, 0
   11c66: 37 95 e3 38  	lui	a0, 233017
   11c6a: 1b 04 95 e3  	addiw	s0, a0, -455
   11c6e: 97 00 00 00  	auipc	ra, 0
   11c72: e7 80 20 18  	jalr	386(ra)
   11c76: b3 05 85 02  	mul	a1, a0, s0
   11c7a: 13 d6 f5 03  	srli	a2, a1, 63
   11c7e: 85 95        	srai	a1, a1, 33
   11c80: b1 9d        	addw	a1, a1, a2
   11c82: 1b 96 35 00  	slliw	a2, a1, 3
   11c86: b1 9d        	addw	a1, a1, a2
   11c88: 0d 9d        	subw	a0, a0, a1
   11c8a: 05 25        	addiw	a0, a0, 1
   11c8c: b3 85 99 00  	add	a1, s3, s1
   11c90: 91 04        	addi	s1, s1, 4
   11c92: 88 c1        	sw	a0, 0(a1)
   11c94: e3 9d 24 fd  	bne	s1, s2, 0x11c6e <main+0x26>
   11c98: 11 65        	lui	a0, 4
   11c9a: 11 69        	lui	s2, 4
   11c9c: 97 00 00 00  	auipc	ra, 0
   11ca0: e7 80 40 18  	jalr	388(ra)
   11ca4: 2a 8a        	mv	s4, a0
   11ca6: 01 44        	li	s0, 0
   11ca8: 37 95 e3 38  	lui	a0, 233017
   11cac: 9b 04 95 e3  	addiw	s1, a0, -455
   11cb0: 97 00 00 00  	auipc	ra, 0
   11cb4: e7 80 00 14  	jalr	320(ra)
   11cb8: b3 05 95 02  	mul	a1, a0, s1
   11cbc: 13 d6 f5 03  	srli	a2, a1, 63
   11cc0: 85 95        	srai	a1, a1, 33
   11cc2: b1 9d        	addw	a1, a1, a2
   11cc4: 1b 96 35 00  	slliw	a2, a1, 3
   11cc8: b1 9d        	addw	a1, a1, a2
   11cca: 0d 9d        	subw	a0, a0, a1
   11ccc: 05 25        	addiw	a0, a0, 1
   11cce: b3 05 8a 00  	add	a1, s4, s0
   11cd2: 11 04        	addi	s0, s0, 4
   11cd4: 88 c1        	sw	a0, 0(a1)
   11cd6: e3 1d 24 fd  	bne	s0, s2, 0x11cb0 <main+0x68>
   11cda: 11 65        	lui	a0, 4
   11cdc: 97 00 00 00  	auipc	ra, 0
   11ce0: e7 80 40 14  	jalr	324(ra)
   11ce4: 2a 89        	mv	s2, a0
   11ce6: 4e 85        	mv	a0, s3
   11ce8: d2 85        	mv	a1, s4
   11cea: 4a 86        	mv	a2, s2
   11cec: 97 00 00 00  	auipc	ra, 0
   11cf0: e7 80 c0 e2  	jalr	-468(ra)
   11cf4: 17 f5 ff ff  	auipc	a0, 1048575
   11cf8: 13 05 a5 96  	addi	a0, a0, -1686
   11cfc: 97 00 00 00  	auipc	ra, 0
   11d00: e7 80 40 13  	jalr	308(ra)
   11d04: 17 f5 ff ff  	auipc	a0, 1048575
   11d08: 13 05 d5 94  	addi	a0, a0, -1715
   11d0c: 97 00 00 00  	auipc	ra, 0
   11d10: e7 80 40 12  	jalr	292(ra)
   11d14: 17 f5 ff ff  	auipc	a0, 1048575
   11d18: 13 05 75 95  	addi	a0, a0, -1705
   11d1c: 97 00 00 00  	auipc	ra, 0
   11d20: e7 80 40 11  	jalr	276(ra)
   11d24: 4e 85        	mv	a0, s3
   11d26: 97 00 00 00  	auipc	ra, 0
   11d2a: e7 80 a0 11  	jalr	282(ra)
   11d2e: 52 85        	mv	a0, s4
   11d30: 97 00 00 00  	auipc	ra, 0
   11d34: e7 80 00 11  	jalr	272(ra)
   11d38: 4a 85        	mv	a0, s2
   11d3a: 97 00 00 00  	auipc	ra, 0
   11d3e: e7 80 60 10  	jalr	262(ra)
   11d42: 01 45        	li	a0, 0
   11d44: a2 70        	ld	ra, 40(sp)
   11d46: 02 74        	ld	s0, 32(sp)
   11d48: e2 64        	ld	s1, 24(sp)
   11d4a: 42 69        	ld	s2, 16(sp)
   11d4c: a2 69        	ld	s3, 8(sp)
   11d4e: 02 6a        	ld	s4, 0(sp)
   11d50: 45 61        	addi	sp, sp, 48
   11d52: 82 80        	ret

0000000000011d54 <__do_global_ctors_aux>:
; {
   11d54: 01 11        	addi	sp, sp, -32
   11d56: 06 ec        	sd	ra, 24(sp)
   11d58: 22 e8        	sd	s0, 16(sp)
   11d5a: 26 e4        	sd	s1, 8(sp)
   11d5c: 4a e0        	sd	s2, 0(sp)
   11d5e: 00 10        	addi	s0, sp, 32
   11d60: 37 35 01 00  	lui	a0, 19
   11d64: 93 04 05 e5  	addi	s1, a0, -432
   11d68: 09 49        	li	s2, 2
; 		fn = __CTOR_END__[-n];
   11d6a: 88 60        	ld	a0, 0(s1)
; 		if (fn == (crt_func)0 || fn == (crt_func)-1)
   11d6c: 93 05 15 00  	addi	a1, a0, 1
   11d70: 63 e5 25 01  	bltu	a1, s2, 0x11d7a <__do_global_ctors_aux+0x26>
; 		fn();
   11d74: 02 95        	jalr	a0
; 	for (n = 1;; n++) {
   11d76: e1 14        	addi	s1, s1, -8
   11d78: cd bf        	j	0x11d6a <__do_global_ctors_aux+0x16>
; }
   11d7a: e2 60        	ld	ra, 24(sp)
   11d7c: 42 64        	ld	s0, 16(sp)
   11d7e: a2 64        	ld	s1, 8(sp)
   11d80: 02 69        	ld	s2, 0(sp)
   11d82: 05 61        	addi	sp, sp, 32
   11d84: 82 80        	ret

Disassembly of section .init:

0000000000011d86 <_init>:
; 	addi	sp, sp, -16
   11d86: 41 11        	addi	sp, sp, -16
; 	sd	ra, 0(sp)
   11d88: 06 e0        	sd	ra, 0(sp)
   11d8a: 97 00 00 00  	auipc	ra, 0
   11d8e: e7 80 a0 fc  	jalr	-54(ra)
; 	ld	ra, 0(sp)
   11d92: 82 60        	ld	ra, 0(sp)
; 	addi	sp, sp, 16
   11d94: 41 01        	addi	sp, sp, 16
; 	ret
   11d96: 82 80        	ret

Disassembly of section .fini:

0000000000011d98 <_fini>:
; 	addi	sp, sp, -16
   11d98: 41 11        	addi	sp, sp, -16
; 	sd	ra, 0(sp)
   11d9a: 06 e0        	sd	ra, 0(sp)
   11d9c: 97 00 00 00  	auipc	ra, 0
   11da0: e7 80 80 d1  	jalr	-744(ra)
; 	ld	ra, 0(sp)
   11da4: 82 60        	ld	ra, 0(sp)
; 	addi	sp, sp, 16
   11da6: 41 01        	addi	sp, sp, 16
; 	ret
   11da8: 82 80        	ret

Disassembly of section .plt:

0000000000011db0 <.plt>:
   11db0: 97 23 00 00  	auipc	t2, 2
   11db4: 33 03 c3 41  	sub	t1, t1, t3
   11db8: 03 be 83 21  	ld	t3, 536(t2)
   11dbc: 13 03 43 fd  	addi	t1, t1, -44
   11dc0: 93 82 83 21  	addi	t0, t2, 536
   11dc4: 13 53 13 00  	srli	t1, t1, 1
   11dc8: 83 b2 82 00  	ld	t0, 8(t0)
   11dcc: 67 00 0e 00  	jr	t3
   11dd0: 17 2e 00 00  	auipc	t3, 2
   11dd4: 03 3e 8e 20  	ld	t3, 520(t3)
   11dd8: 67 03 0e 00  	jalr	t1, t3
   11ddc: 13 00 00 00  	nop
   11de0: 17 2e 00 00  	auipc	t3, 2
   11de4: 03 3e 0e 20  	ld	t3, 512(t3)
   11de8: 67 03 0e 00  	jalr	t1, t3
   11dec: 13 00 00 00  	nop
   11df0: 17 2e 00 00  	auipc	t3, 2
   11df4: 03 3e 8e 1f  	ld	t3, 504(t3)
   11df8: 67 03 0e 00  	jalr	t1, t3
   11dfc: 13 00 00 00  	nop
   11e00: 17 2e 00 00  	auipc	t3, 2
   11e04: 03 3e 0e 1f  	ld	t3, 496(t3)
   11e08: 67 03 0e 00  	jalr	t1, t3
   11e0c: 13 00 00 00  	nop
   11e10: 17 2e 00 00  	auipc	t3, 2
   11e14: 03 3e 8e 1e  	ld	t3, 488(t3)
   11e18: 67 03 0e 00  	jalr	t1, t3
   11e1c: 13 00 00 00  	nop
   11e20: 17 2e 00 00  	auipc	t3, 2
   11e24: 03 3e 0e 1e  	ld	t3, 480(t3)
   11e28: 67 03 0e 00  	jalr	t1, t3
   11e2c: 13 00 00 00  	nop
   11e30: 17 2e 00 00  	auipc	t3, 2
   11e34: 03 3e 8e 1d  	ld	t3, 472(t3)
   11e38: 67 03 0e 00  	jalr	t1, t3
   11e3c: 13 00 00 00  	nop
   11e40: 17 2e 00 00  	auipc	t3, 2
   11e44: 03 3e 0e 1d  	ld	t3, 464(t3)
   11e48: 67 03 0e 00  	jalr	t1, t3
   11e4c: 13 00 00 00  	nop
