diff --git a/riscv-bare-metal/core_portme.mak b/riscv-bare-metal/core_portme.mak
index 927b537..aa4d5fd 100755
--- a/riscv-bare-metal/core_portme.mak
+++ b/riscv-bare-metal/core_portme.mak
@@ -121,7 +121,7 @@ ifeq ($(CHERI),1)
 ifeq ($(FPGA),1)
   RISCV_FLAGS += -DFPGA
 endif 
-  LIBS += -lm -lc -lclang_rt.builtins-riscv64 -L$(HOME_DIR)output/sdk/baremetal/baremetal-riscv64-purecap/lib/
+  LIBS += -lm -lc -lclang_rt.builtins-riscv64 -L$(HOME_DIR)output/sdk/baremetal/baremetal-riscv64-purecap/lib/ 
 else
   RISCV_FLAGS += -target riscv64 -march=rv64gc -mabi=lp64
   LIBS += -lm -lc -lclang_rt.builtins-riscv64 -L$(HOME_DIR)output/sdk/baremetal/baremetal-riscv64/lib/
