 
****************************************
Report : area
Design : xor_bitwise
Version: S-2021.06
Date   : Fri Feb 25 15:08:18 2022
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Information: Updating design information... (UID-85)
Library(s) Used:

    saed32rvt_tt0p85v25c (File: /cae/apps/data/saed32_edk-2018/lib/stdcell_rvt/db_nldm/saed32rvt_tt0p85v25c.db)

Number of ports:                            7
Number of nets:                            12
Number of cells:                            5
Number of combinational cells:              4
Number of sequential cells:                 1
Number of macros/black boxes:               0
Number of buf/inv:                          1
Number of references:                       5

Combinational area:                 10.674048
Buf/Inv area:                        1.270720
Noncombinational area:               7.116032
Macro/Black Box area:                0.000000
Net Interconnect area:               1.095169

Total cell area:                    17.790080
Total area:                         18.885249
1
