 
****************************************
Report : area
Design : xnor_bitwise
Version: S-2021.06
Date   : Fri Feb 25 15:07:54 2022
****************************************

Information: Updating design information... (UID-85)
Library(s) Used:

    saed32rvt_tt0p85v25c (File: /cae/apps/data/saed32_edk-2018/lib/stdcell_rvt/db_nldm/saed32rvt_tt0p85v25c.db)

Number of ports:                           13
Number of nets:                            17
Number of cells:                            6
Number of combinational cells:              4
Number of sequential cells:                 1
Number of macros/black boxes:               0
Number of buf/inv:                          1
Number of references:                       2

Combinational area:                 11.182336
Buf/Inv area:                        1.270720
Noncombinational area:               7.116032
Macro/Black Box area:                0.000000
Net Interconnect area:               1.114583

Total cell area:                    18.298368
Total area:                         19.412951

Hierarchical area distribution
------------------------------

                                  Global cell area          Local cell area
                                  ------------------  --------------------------- 
Hierarchical cell                 Absolute   Percent  Combi-    Noncombi-  Black-
                                  Total      Total    national  national   boxes   Design
--------------------------------  ---------  -------  --------  ---------  ------  ---------------
xnor_bitwise                        18.2984    100.0    4.3204     0.0000  0.0000  xnor_bitwise
U_REG                               13.9779     76.4    6.8619     7.1160  0.0000  register_WIDTH1
--------------------------------  ---------  -------  --------  ---------  ------  ---------------
Total                                                  11.1823     7.1160  0.0000

1
