Published January 8, 2015 | Version v1
Conference paper Open

Design of Low Power and High Speed Carry Select Adder Using Brent Kung Adder

  • 1. Kautilya Institute of Technology and Engineering

Description

In this paper, Carry Select Adder (CSA) architectures are proposed using parallel prefix adders. Instead of using dual Ripple Carry Adders (RCA), parallel prefix adder i.e., Brent Kung (BK) adder is used to design Regular Linear CSA. Adders are the basic building blocks in digital integrated circuit based designs. Ripple Carry Adder (RCA) gives the most compact design but takes longer computation time. The time critical applications use Carry Look-ahead scheme (CLA) to derive fast results but they lead to increase in area. Carry Select Adder is a compromise between RCA and CLA in term of area and delay. Delay of RCA is large therefore we have replaced it with parallel prefix adder which gives fast results. In this paper, structures of 16-Bit Regular Linear Brent Kung CSA, Modified Linear BK CSA, Regular Square Root (SQRT) BK CSA and Modified SQRT BK CSA are designed. Power and delay of all these adder architectures are calculated at different input voltages. The results depict that Modified SQRT BK CSA is better than all the other adder architectures in terms of power but with small speed penalty. The designs have been synthesized at 45nm technology using Tanner EDA tool.

Files

Design_of_Low_Power_and_High_Speed_Carry_Select_Adder_Using_Brent_Kung_Adder.pdf

Additional details

References

  • Shivani Parmar and Kirat Pal Singh," Design of High Speed Hybrid Carry Select Adder", IEEE's 3rd International Advance Computing Conference (IACC) Ghaziabad, ISBN: 978-1-4673-4527-9,22-23 February 2013.
  • Yajaun He, Chip-Hong Chang, and Jiangmin Gu, "An area efficient 64-Bit square Root carry-select adder for low power Applications, " in Proc. IEEE International Symposium Circuits and Systems, vol. 4, pp. 4082-4085,2005.
  • M. Snir, "Depth-Size Trade-Offs for Parallel Prefix Computation", Journal of Algorithms, Vo!.7, Issue-2, pp.185-201, June 1986.
  • David Jeff Jackson and Sidney Joel Hannah, "Modelling and Comparison of Adder Designs with Verilog HDL", 25th South-eastern Symposium on System Theory, pp.406-4tO, March 1993.
  • Belle W.Y. Wei and Clark D. Thompson, "Area-Time Optimal Adder Design", IEEE transactions on Computers, vo!.39, pp. 666-675, May1990.
  • Y. Choi, "Parallel Prefix Adder Design", Proc. 17th IEEE Symposium on Computer Arithmetic, pp. 90-98, 27th June 2005.
  • J. M. Rabaey, "Digital Integrated Circuits- A Design Perspective", New Jersey, Prentice-Hall, 2001.
  • R. Brent and H. Kung, "A regular layout for parallel adders", IEEE Transaction on Computers, vol. C-31,n o.3,p p. 260-264,M arch 1982.
  • Adilakshmi Siliveru, M. Bharathi, "Design of Kogge-Stone and BrentKung adders using Degenerate Pass Transistor Logic", International Journal of Emerging Science and Engineering, Vol.-I, Issue-4, February 2013.
  • K. Saranya, "Low Power and Area-Efficient Carry Select Adder", International Journal of Soft Computing and Engineering, Vol.-2, Issue-6, January 2013.
  • Deepthi Obul Reddy and P. Ramesh Yadav, "Carry Select Adder with Low Power and Area Efficiency", lnlernalional Journal of Engineering Research and Developmenl, Vol. 3, Issue 3, pp. 29-35, August 2012.